1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef __QCOM_GDSC_H__ 7 #define __QCOM_GDSC_H__ 8 9 #include <linux/err.h> 10 #include <linux/pm_domain.h> 11 12 struct regmap; 13 struct regulator; 14 struct reset_controller_dev; 15 16 /** 17 * struct gdsc - Globally Distributed Switch Controller 18 * @pd: generic power domain 19 * @regmap: regmap for MMIO accesses 20 * @gdscr: gsdc control register 21 * @gds_hw_ctrl: gds_hw_ctrl register 22 * @cxcs: offsets of branch registers to toggle mem/periph bits in 23 * @cxc_count: number of @cxcs 24 * @pwrsts: Possible powerdomain power states 25 * @en_rest_wait_val: transition delay value for receiving enr ack signal 26 * @en_few_wait_val: transition delay value for receiving enf ack signal 27 * @clk_dis_wait_val: transition delay value for halting clock 28 * @resets: ids of resets associated with this gdsc 29 * @reset_count: number of @resets 30 * @rcdev: reset controller 31 * @dev: the device holding the GDSC, used for pm_runtime calls 32 */ 33 struct gdsc { 34 struct generic_pm_domain pd; 35 struct generic_pm_domain *parent; 36 struct regmap *regmap; 37 unsigned int gdscr; 38 unsigned int gds_hw_ctrl; 39 unsigned int clamp_io_ctrl; 40 unsigned int *cxcs; 41 unsigned int cxc_count; 42 unsigned int en_rest_wait_val; 43 unsigned int en_few_wait_val; 44 unsigned int clk_dis_wait_val; 45 const u8 pwrsts; 46 /* Powerdomain allowable state bitfields */ 47 #define PWRSTS_OFF BIT(0) 48 #define PWRSTS_RET BIT(1) 49 #define PWRSTS_ON BIT(2) 50 #define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON) 51 #define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON) 52 const u16 flags; 53 #define VOTABLE BIT(0) 54 #define CLAMP_IO BIT(1) 55 #define HW_CTRL BIT(2) 56 #define SW_RESET BIT(3) 57 #define AON_RESET BIT(4) 58 #define POLL_CFG_GDSCR BIT(5) 59 #define ALWAYS_ON BIT(6) 60 #define RETAIN_FF_ENABLE BIT(7) 61 #define NO_RET_PERIPH BIT(8) 62 struct reset_controller_dev *rcdev; 63 unsigned int *resets; 64 unsigned int reset_count; 65 66 const char *supply; 67 struct regulator *rsupply; 68 struct device *dev; 69 }; 70 71 struct gdsc_desc { 72 struct device *dev; 73 struct gdsc **scs; 74 size_t num; 75 }; 76 77 #ifdef CONFIG_QCOM_GDSC 78 int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *, 79 struct regmap *); 80 void gdsc_unregister(struct gdsc_desc *desc); 81 int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain); 82 #else 83 static inline int gdsc_register(struct gdsc_desc *desc, 84 struct reset_controller_dev *rcdev, 85 struct regmap *r) 86 { 87 return -ENOSYS; 88 } 89 90 static inline void gdsc_unregister(struct gdsc_desc *desc) {}; 91 #endif /* CONFIG_QCOM_GDSC */ 92 #endif /* __QCOM_GDSC_H__ */ 93