1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef __QCOM_GDSC_H__ 7 #define __QCOM_GDSC_H__ 8 9 #include <linux/err.h> 10 #include <linux/pm_domain.h> 11 12 struct regmap; 13 struct regulator; 14 struct reset_controller_dev; 15 16 /** 17 * struct gdsc - Globally Distributed Switch Controller 18 * @pd: generic power domain 19 * @regmap: regmap for MMIO accesses 20 * @gdscr: gsdc control register 21 * @collapse_ctrl: APCS collapse-vote register 22 * @collapse_mask: APCS collapse-vote mask 23 * @gds_hw_ctrl: gds_hw_ctrl register 24 * @cxcs: offsets of branch registers to toggle mem/periph bits in 25 * @cxc_count: number of @cxcs 26 * @pwrsts: Possible powerdomain power states 27 * @en_rest_wait_val: transition delay value for receiving enr ack signal 28 * @en_few_wait_val: transition delay value for receiving enf ack signal 29 * @clk_dis_wait_val: transition delay value for halting clock 30 * @resets: ids of resets associated with this gdsc 31 * @reset_count: number of @resets 32 * @rcdev: reset controller 33 * @dev: the device holding the GDSC, used for pm_runtime calls 34 */ 35 struct gdsc { 36 struct generic_pm_domain pd; 37 struct generic_pm_domain *parent; 38 struct regmap *regmap; 39 unsigned int gdscr; 40 unsigned int collapse_ctrl; 41 unsigned int collapse_mask; 42 unsigned int gds_hw_ctrl; 43 unsigned int clamp_io_ctrl; 44 unsigned int *cxcs; 45 unsigned int cxc_count; 46 unsigned int en_rest_wait_val; 47 unsigned int en_few_wait_val; 48 unsigned int clk_dis_wait_val; 49 const u8 pwrsts; 50 /* Powerdomain allowable state bitfields */ 51 #define PWRSTS_OFF BIT(0) 52 #define PWRSTS_RET BIT(1) 53 #define PWRSTS_ON BIT(2) 54 #define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON) 55 #define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON) 56 const u16 flags; 57 #define VOTABLE BIT(0) 58 #define CLAMP_IO BIT(1) 59 #define HW_CTRL BIT(2) 60 #define SW_RESET BIT(3) 61 #define AON_RESET BIT(4) 62 #define POLL_CFG_GDSCR BIT(5) 63 #define ALWAYS_ON BIT(6) 64 #define RETAIN_FF_ENABLE BIT(7) 65 #define NO_RET_PERIPH BIT(8) 66 struct reset_controller_dev *rcdev; 67 unsigned int *resets; 68 unsigned int reset_count; 69 70 const char *supply; 71 struct regulator *rsupply; 72 struct device *dev; 73 }; 74 75 struct gdsc_desc { 76 struct device *dev; 77 struct gdsc **scs; 78 size_t num; 79 }; 80 81 #ifdef CONFIG_QCOM_GDSC 82 int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *, 83 struct regmap *); 84 void gdsc_unregister(struct gdsc_desc *desc); 85 int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain); 86 #else 87 static inline int gdsc_register(struct gdsc_desc *desc, 88 struct reset_controller_dev *rcdev, 89 struct regmap *r) 90 { 91 return -ENOSYS; 92 } 93 94 static inline void gdsc_unregister(struct gdsc_desc *desc) {}; 95 #endif /* CONFIG_QCOM_GDSC */ 96 #endif /* __QCOM_GDSC_H__ */ 97