1 /* 2 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/bitops.h> 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/jiffies.h> 18 #include <linux/kernel.h> 19 #include <linux/ktime.h> 20 #include <linux/pm_domain.h> 21 #include <linux/regmap.h> 22 #include <linux/reset-controller.h> 23 #include <linux/slab.h> 24 #include "gdsc.h" 25 26 #define PWR_ON_MASK BIT(31) 27 #define EN_REST_WAIT_MASK GENMASK_ULL(23, 20) 28 #define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16) 29 #define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12) 30 #define SW_OVERRIDE_MASK BIT(2) 31 #define HW_CONTROL_MASK BIT(1) 32 #define SW_COLLAPSE_MASK BIT(0) 33 #define GMEM_CLAMP_IO_MASK BIT(0) 34 35 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */ 36 #define EN_REST_WAIT_VAL (0x2 << 20) 37 #define EN_FEW_WAIT_VAL (0x8 << 16) 38 #define CLK_DIS_WAIT_VAL (0x2 << 12) 39 40 #define RETAIN_MEM BIT(14) 41 #define RETAIN_PERIPH BIT(13) 42 43 #define TIMEOUT_US 100 44 45 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd) 46 47 static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg) 48 { 49 u32 val; 50 int ret; 51 52 ret = regmap_read(sc->regmap, reg, &val); 53 if (ret) 54 return ret; 55 56 return !!(val & PWR_ON_MASK); 57 } 58 59 static int gdsc_hwctrl(struct gdsc *sc, bool en) 60 { 61 u32 val = en ? HW_CONTROL_MASK : 0; 62 63 return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val); 64 } 65 66 static int gdsc_poll_status(struct gdsc *sc, unsigned int reg, bool en) 67 { 68 ktime_t start; 69 70 start = ktime_get(); 71 do { 72 if (gdsc_is_enabled(sc, reg) == en) 73 return 0; 74 } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US); 75 76 if (gdsc_is_enabled(sc, reg) == en) 77 return 0; 78 79 return -ETIMEDOUT; 80 } 81 82 static int gdsc_toggle_logic(struct gdsc *sc, bool en) 83 { 84 int ret; 85 u32 val = en ? 0 : SW_COLLAPSE_MASK; 86 unsigned int status_reg = sc->gdscr; 87 88 ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val); 89 if (ret) 90 return ret; 91 92 /* If disabling votable gdscs, don't poll on status */ 93 if ((sc->flags & VOTABLE) && !en) { 94 /* 95 * Add a short delay here to ensure that an enable 96 * right after it was disabled does not put it in an 97 * unknown state 98 */ 99 udelay(TIMEOUT_US); 100 return 0; 101 } 102 103 if (sc->gds_hw_ctrl) { 104 status_reg = sc->gds_hw_ctrl; 105 /* 106 * The gds hw controller asserts/de-asserts the status bit soon 107 * after it receives a power on/off request from a master. 108 * The controller then takes around 8 xo cycles to start its 109 * internal state machine and update the status bit. During 110 * this time, the status bit does not reflect the true status 111 * of the core. 112 * Add a delay of 1 us between writing to the SW_COLLAPSE bit 113 * and polling the status bit. 114 */ 115 udelay(1); 116 } 117 118 return gdsc_poll_status(sc, status_reg, en); 119 } 120 121 static inline int gdsc_deassert_reset(struct gdsc *sc) 122 { 123 int i; 124 125 for (i = 0; i < sc->reset_count; i++) 126 sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]); 127 return 0; 128 } 129 130 static inline int gdsc_assert_reset(struct gdsc *sc) 131 { 132 int i; 133 134 for (i = 0; i < sc->reset_count; i++) 135 sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]); 136 return 0; 137 } 138 139 static inline void gdsc_force_mem_on(struct gdsc *sc) 140 { 141 int i; 142 u32 mask = RETAIN_MEM | RETAIN_PERIPH; 143 144 for (i = 0; i < sc->cxc_count; i++) 145 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask); 146 } 147 148 static inline void gdsc_clear_mem_on(struct gdsc *sc) 149 { 150 int i; 151 u32 mask = RETAIN_MEM | RETAIN_PERIPH; 152 153 for (i = 0; i < sc->cxc_count; i++) 154 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0); 155 } 156 157 static inline void gdsc_deassert_clamp_io(struct gdsc *sc) 158 { 159 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl, 160 GMEM_CLAMP_IO_MASK, 0); 161 } 162 163 static inline void gdsc_assert_clamp_io(struct gdsc *sc) 164 { 165 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl, 166 GMEM_CLAMP_IO_MASK, 1); 167 } 168 169 static int gdsc_enable(struct generic_pm_domain *domain) 170 { 171 struct gdsc *sc = domain_to_gdsc(domain); 172 int ret; 173 174 if (sc->pwrsts == PWRSTS_ON) 175 return gdsc_deassert_reset(sc); 176 177 if (sc->flags & CLAMP_IO) 178 gdsc_deassert_clamp_io(sc); 179 180 ret = gdsc_toggle_logic(sc, true); 181 if (ret) 182 return ret; 183 184 if (sc->pwrsts & PWRSTS_OFF) 185 gdsc_force_mem_on(sc); 186 187 /* 188 * If clocks to this power domain were already on, they will take an 189 * additional 4 clock cycles to re-enable after the power domain is 190 * enabled. Delay to account for this. A delay is also needed to ensure 191 * clocks are not enabled within 400ns of enabling power to the 192 * memories. 193 */ 194 udelay(1); 195 196 /* Turn on HW trigger mode if supported */ 197 if (sc->flags & HW_CTRL) { 198 ret = gdsc_hwctrl(sc, true); 199 if (ret) 200 return ret; 201 /* 202 * Wait for the GDSC to go through a power down and 203 * up cycle. In case a firmware ends up polling status 204 * bits for the gdsc, it might read an 'on' status before 205 * the GDSC can finish the power cycle. 206 * We wait 1us before returning to ensure the firmware 207 * can't immediately poll the status bits. 208 */ 209 udelay(1); 210 } 211 212 return 0; 213 } 214 215 static int gdsc_disable(struct generic_pm_domain *domain) 216 { 217 struct gdsc *sc = domain_to_gdsc(domain); 218 int ret; 219 220 if (sc->pwrsts == PWRSTS_ON) 221 return gdsc_assert_reset(sc); 222 223 /* Turn off HW trigger mode if supported */ 224 if (sc->flags & HW_CTRL) { 225 unsigned int reg; 226 227 ret = gdsc_hwctrl(sc, false); 228 if (ret < 0) 229 return ret; 230 /* 231 * Wait for the GDSC to go through a power down and 232 * up cycle. In case we end up polling status 233 * bits for the gdsc before the power cycle is completed 234 * it might read an 'on' status wrongly. 235 */ 236 udelay(1); 237 238 reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr; 239 ret = gdsc_poll_status(sc, reg, true); 240 if (ret) 241 return ret; 242 } 243 244 if (sc->pwrsts & PWRSTS_OFF) 245 gdsc_clear_mem_on(sc); 246 247 ret = gdsc_toggle_logic(sc, false); 248 if (ret) 249 return ret; 250 251 if (sc->flags & CLAMP_IO) 252 gdsc_assert_clamp_io(sc); 253 254 return 0; 255 } 256 257 static int gdsc_init(struct gdsc *sc) 258 { 259 u32 mask, val; 260 int on, ret; 261 unsigned int reg; 262 263 /* 264 * Disable HW trigger: collapse/restore occur based on registers writes. 265 * Disable SW override: Use hardware state-machine for sequencing. 266 * Configure wait time between states. 267 */ 268 mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK | 269 EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK; 270 val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL; 271 ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val); 272 if (ret) 273 return ret; 274 275 /* Force gdsc ON if only ON state is supported */ 276 if (sc->pwrsts == PWRSTS_ON) { 277 ret = gdsc_toggle_logic(sc, true); 278 if (ret) 279 return ret; 280 } 281 282 reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr; 283 on = gdsc_is_enabled(sc, reg); 284 if (on < 0) 285 return on; 286 287 /* 288 * Votable GDSCs can be ON due to Vote from other masters. 289 * If a Votable GDSC is ON, make sure we have a Vote. 290 */ 291 if ((sc->flags & VOTABLE) && on) 292 gdsc_enable(&sc->pd); 293 294 if (on || (sc->pwrsts & PWRSTS_RET)) 295 gdsc_force_mem_on(sc); 296 else 297 gdsc_clear_mem_on(sc); 298 299 sc->pd.power_off = gdsc_disable; 300 sc->pd.power_on = gdsc_enable; 301 pm_genpd_init(&sc->pd, NULL, !on); 302 303 return 0; 304 } 305 306 int gdsc_register(struct gdsc_desc *desc, 307 struct reset_controller_dev *rcdev, struct regmap *regmap) 308 { 309 int i, ret; 310 struct genpd_onecell_data *data; 311 struct device *dev = desc->dev; 312 struct gdsc **scs = desc->scs; 313 size_t num = desc->num; 314 315 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 316 if (!data) 317 return -ENOMEM; 318 319 data->domains = devm_kcalloc(dev, num, sizeof(*data->domains), 320 GFP_KERNEL); 321 if (!data->domains) 322 return -ENOMEM; 323 324 data->num_domains = num; 325 for (i = 0; i < num; i++) { 326 if (!scs[i]) 327 continue; 328 scs[i]->regmap = regmap; 329 scs[i]->rcdev = rcdev; 330 ret = gdsc_init(scs[i]); 331 if (ret) 332 return ret; 333 data->domains[i] = &scs[i]->pd; 334 } 335 336 /* Add subdomains */ 337 for (i = 0; i < num; i++) { 338 if (!scs[i]) 339 continue; 340 if (scs[i]->parent) 341 pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd); 342 } 343 344 return of_genpd_add_provider_onecell(dev->of_node, data); 345 } 346 347 void gdsc_unregister(struct gdsc_desc *desc) 348 { 349 int i; 350 struct device *dev = desc->dev; 351 struct gdsc **scs = desc->scs; 352 size_t num = desc->num; 353 354 /* Remove subdomains */ 355 for (i = 0; i < num; i++) { 356 if (!scs[i]) 357 continue; 358 if (scs[i]->parent) 359 pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd); 360 } 361 of_genpd_del_provider(dev->of_node); 362 } 363