1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/bitops.h> 7 #include <linux/delay.h> 8 #include <linux/err.h> 9 #include <linux/export.h> 10 #include <linux/jiffies.h> 11 #include <linux/kernel.h> 12 #include <linux/ktime.h> 13 #include <linux/pm_domain.h> 14 #include <linux/regmap.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/reset-controller.h> 17 #include <linux/slab.h> 18 #include "gdsc.h" 19 20 #define PWR_ON_MASK BIT(31) 21 #define EN_REST_WAIT_MASK GENMASK_ULL(23, 20) 22 #define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16) 23 #define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12) 24 #define SW_OVERRIDE_MASK BIT(2) 25 #define HW_CONTROL_MASK BIT(1) 26 #define SW_COLLAPSE_MASK BIT(0) 27 #define GMEM_CLAMP_IO_MASK BIT(0) 28 #define GMEM_RESET_MASK BIT(4) 29 30 /* CFG_GDSCR */ 31 #define GDSC_POWER_UP_COMPLETE BIT(16) 32 #define GDSC_POWER_DOWN_COMPLETE BIT(15) 33 #define GDSC_RETAIN_FF_ENABLE BIT(11) 34 #define CFG_GDSCR_OFFSET 0x4 35 36 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */ 37 #define EN_REST_WAIT_VAL 0x2 38 #define EN_FEW_WAIT_VAL 0x8 39 #define CLK_DIS_WAIT_VAL 0x2 40 41 /* Transition delay shifts */ 42 #define EN_REST_WAIT_SHIFT 20 43 #define EN_FEW_WAIT_SHIFT 16 44 #define CLK_DIS_WAIT_SHIFT 12 45 46 #define RETAIN_MEM BIT(14) 47 #define RETAIN_PERIPH BIT(13) 48 49 #define TIMEOUT_US 500 50 51 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd) 52 53 enum gdsc_status { 54 GDSC_OFF, 55 GDSC_ON 56 }; 57 58 /* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */ 59 static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status) 60 { 61 unsigned int reg; 62 u32 val; 63 int ret; 64 65 if (sc->flags & POLL_CFG_GDSCR) 66 reg = sc->gdscr + CFG_GDSCR_OFFSET; 67 else if (sc->gds_hw_ctrl) 68 reg = sc->gds_hw_ctrl; 69 else 70 reg = sc->gdscr; 71 72 ret = regmap_read(sc->regmap, reg, &val); 73 if (ret) 74 return ret; 75 76 if (sc->flags & POLL_CFG_GDSCR) { 77 switch (status) { 78 case GDSC_ON: 79 return !!(val & GDSC_POWER_UP_COMPLETE); 80 case GDSC_OFF: 81 return !!(val & GDSC_POWER_DOWN_COMPLETE); 82 } 83 } 84 85 switch (status) { 86 case GDSC_ON: 87 return !!(val & PWR_ON_MASK); 88 case GDSC_OFF: 89 return !(val & PWR_ON_MASK); 90 } 91 92 return -EINVAL; 93 } 94 95 static int gdsc_hwctrl(struct gdsc *sc, bool en) 96 { 97 u32 val = en ? HW_CONTROL_MASK : 0; 98 99 return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val); 100 } 101 102 static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status) 103 { 104 ktime_t start; 105 106 start = ktime_get(); 107 do { 108 if (gdsc_check_status(sc, status)) 109 return 0; 110 } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US); 111 112 if (gdsc_check_status(sc, status)) 113 return 0; 114 115 return -ETIMEDOUT; 116 } 117 118 static int gdsc_update_collapse_bit(struct gdsc *sc, bool val) 119 { 120 u32 reg, mask; 121 int ret; 122 123 if (sc->collapse_mask) { 124 reg = sc->collapse_ctrl; 125 mask = sc->collapse_mask; 126 } else { 127 reg = sc->gdscr; 128 mask = SW_COLLAPSE_MASK; 129 } 130 131 ret = regmap_update_bits(sc->regmap, reg, mask, val ? mask : 0); 132 if (ret) 133 return ret; 134 135 return 0; 136 } 137 138 static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status) 139 { 140 int ret; 141 142 if (status == GDSC_ON && sc->rsupply) { 143 ret = regulator_enable(sc->rsupply); 144 if (ret < 0) 145 return ret; 146 } 147 148 ret = gdsc_update_collapse_bit(sc, status == GDSC_OFF); 149 150 /* If disabling votable gdscs, don't poll on status */ 151 if ((sc->flags & VOTABLE) && status == GDSC_OFF) { 152 /* 153 * Add a short delay here to ensure that an enable 154 * right after it was disabled does not put it in an 155 * unknown state 156 */ 157 udelay(TIMEOUT_US); 158 return 0; 159 } 160 161 if (sc->gds_hw_ctrl) { 162 /* 163 * The gds hw controller asserts/de-asserts the status bit soon 164 * after it receives a power on/off request from a master. 165 * The controller then takes around 8 xo cycles to start its 166 * internal state machine and update the status bit. During 167 * this time, the status bit does not reflect the true status 168 * of the core. 169 * Add a delay of 1 us between writing to the SW_COLLAPSE bit 170 * and polling the status bit. 171 */ 172 udelay(1); 173 } 174 175 ret = gdsc_poll_status(sc, status); 176 WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n"); 177 178 if (!ret && status == GDSC_OFF && sc->rsupply) { 179 ret = regulator_disable(sc->rsupply); 180 if (ret < 0) 181 return ret; 182 } 183 184 return ret; 185 } 186 187 static inline int gdsc_deassert_reset(struct gdsc *sc) 188 { 189 int i; 190 191 for (i = 0; i < sc->reset_count; i++) 192 sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]); 193 return 0; 194 } 195 196 static inline int gdsc_assert_reset(struct gdsc *sc) 197 { 198 int i; 199 200 for (i = 0; i < sc->reset_count; i++) 201 sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]); 202 return 0; 203 } 204 205 static inline void gdsc_force_mem_on(struct gdsc *sc) 206 { 207 int i; 208 u32 mask = RETAIN_MEM; 209 210 if (!(sc->flags & NO_RET_PERIPH)) 211 mask |= RETAIN_PERIPH; 212 213 for (i = 0; i < sc->cxc_count; i++) 214 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask); 215 } 216 217 static inline void gdsc_clear_mem_on(struct gdsc *sc) 218 { 219 int i; 220 u32 mask = RETAIN_MEM; 221 222 if (!(sc->flags & NO_RET_PERIPH)) 223 mask |= RETAIN_PERIPH; 224 225 for (i = 0; i < sc->cxc_count; i++) 226 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0); 227 } 228 229 static inline void gdsc_deassert_clamp_io(struct gdsc *sc) 230 { 231 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl, 232 GMEM_CLAMP_IO_MASK, 0); 233 } 234 235 static inline void gdsc_assert_clamp_io(struct gdsc *sc) 236 { 237 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl, 238 GMEM_CLAMP_IO_MASK, 1); 239 } 240 241 static inline void gdsc_assert_reset_aon(struct gdsc *sc) 242 { 243 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl, 244 GMEM_RESET_MASK, 1); 245 udelay(1); 246 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl, 247 GMEM_RESET_MASK, 0); 248 } 249 250 static void gdsc_retain_ff_on(struct gdsc *sc) 251 { 252 u32 mask = GDSC_RETAIN_FF_ENABLE; 253 254 regmap_update_bits(sc->regmap, sc->gdscr, mask, mask); 255 } 256 257 static int gdsc_enable(struct generic_pm_domain *domain) 258 { 259 struct gdsc *sc = domain_to_gdsc(domain); 260 int ret; 261 262 if (sc->pwrsts == PWRSTS_ON) 263 return gdsc_deassert_reset(sc); 264 265 if (sc->flags & SW_RESET) { 266 gdsc_assert_reset(sc); 267 udelay(1); 268 gdsc_deassert_reset(sc); 269 } 270 271 if (sc->flags & CLAMP_IO) { 272 if (sc->flags & AON_RESET) 273 gdsc_assert_reset_aon(sc); 274 gdsc_deassert_clamp_io(sc); 275 } 276 277 ret = gdsc_toggle_logic(sc, GDSC_ON); 278 if (ret) 279 return ret; 280 281 if (sc->pwrsts & PWRSTS_OFF) 282 gdsc_force_mem_on(sc); 283 284 /* 285 * If clocks to this power domain were already on, they will take an 286 * additional 4 clock cycles to re-enable after the power domain is 287 * enabled. Delay to account for this. A delay is also needed to ensure 288 * clocks are not enabled within 400ns of enabling power to the 289 * memories. 290 */ 291 udelay(1); 292 293 /* Turn on HW trigger mode if supported */ 294 if (sc->flags & HW_CTRL) { 295 ret = gdsc_hwctrl(sc, true); 296 if (ret) 297 return ret; 298 /* 299 * Wait for the GDSC to go through a power down and 300 * up cycle. In case a firmware ends up polling status 301 * bits for the gdsc, it might read an 'on' status before 302 * the GDSC can finish the power cycle. 303 * We wait 1us before returning to ensure the firmware 304 * can't immediately poll the status bits. 305 */ 306 udelay(1); 307 } 308 309 if (sc->flags & RETAIN_FF_ENABLE) 310 gdsc_retain_ff_on(sc); 311 312 return 0; 313 } 314 315 static int gdsc_disable(struct generic_pm_domain *domain) 316 { 317 struct gdsc *sc = domain_to_gdsc(domain); 318 int ret; 319 320 if (sc->pwrsts == PWRSTS_ON) 321 return gdsc_assert_reset(sc); 322 323 /* Turn off HW trigger mode if supported */ 324 if (sc->flags & HW_CTRL) { 325 ret = gdsc_hwctrl(sc, false); 326 if (ret < 0) 327 return ret; 328 /* 329 * Wait for the GDSC to go through a power down and 330 * up cycle. In case we end up polling status 331 * bits for the gdsc before the power cycle is completed 332 * it might read an 'on' status wrongly. 333 */ 334 udelay(1); 335 336 ret = gdsc_poll_status(sc, GDSC_ON); 337 if (ret) 338 return ret; 339 } 340 341 if (sc->pwrsts & PWRSTS_OFF) 342 gdsc_clear_mem_on(sc); 343 344 /* 345 * If the GDSC supports only a Retention state, apart from ON, 346 * leave it in ON state. 347 * There is no SW control to transition the GDSC into 348 * Retention state. This happens in HW when the parent 349 * domain goes down to a Low power state 350 */ 351 if (sc->pwrsts == PWRSTS_RET_ON) 352 return 0; 353 354 ret = gdsc_toggle_logic(sc, GDSC_OFF); 355 if (ret) 356 return ret; 357 358 if (sc->flags & CLAMP_IO) 359 gdsc_assert_clamp_io(sc); 360 361 return 0; 362 } 363 364 static int gdsc_init(struct gdsc *sc) 365 { 366 u32 mask, val; 367 int on, ret; 368 369 /* 370 * Disable HW trigger: collapse/restore occur based on registers writes. 371 * Disable SW override: Use hardware state-machine for sequencing. 372 * Configure wait time between states. 373 */ 374 mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK | 375 EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK; 376 377 if (!sc->en_rest_wait_val) 378 sc->en_rest_wait_val = EN_REST_WAIT_VAL; 379 if (!sc->en_few_wait_val) 380 sc->en_few_wait_val = EN_FEW_WAIT_VAL; 381 if (!sc->clk_dis_wait_val) 382 sc->clk_dis_wait_val = CLK_DIS_WAIT_VAL; 383 384 val = sc->en_rest_wait_val << EN_REST_WAIT_SHIFT | 385 sc->en_few_wait_val << EN_FEW_WAIT_SHIFT | 386 sc->clk_dis_wait_val << CLK_DIS_WAIT_SHIFT; 387 388 ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val); 389 if (ret) 390 return ret; 391 392 /* Force gdsc ON if only ON state is supported */ 393 if (sc->pwrsts == PWRSTS_ON) { 394 ret = gdsc_toggle_logic(sc, GDSC_ON); 395 if (ret) 396 return ret; 397 } 398 399 on = gdsc_check_status(sc, GDSC_ON); 400 if (on < 0) 401 return on; 402 403 if (on) { 404 /* The regulator must be on, sync the kernel state */ 405 if (sc->rsupply) { 406 ret = regulator_enable(sc->rsupply); 407 if (ret < 0) 408 return ret; 409 } 410 411 /* 412 * Votable GDSCs can be ON due to Vote from other masters. 413 * If a Votable GDSC is ON, make sure we have a Vote. 414 */ 415 if (sc->flags & VOTABLE) { 416 ret = gdsc_update_collapse_bit(sc, false); 417 if (ret) 418 goto err_disable_supply; 419 } 420 421 /* Turn on HW trigger mode if supported */ 422 if (sc->flags & HW_CTRL) { 423 ret = gdsc_hwctrl(sc, true); 424 if (ret < 0) 425 goto err_disable_supply; 426 } 427 428 /* 429 * Make sure the retain bit is set if the GDSC is already on, 430 * otherwise we end up turning off the GDSC and destroying all 431 * the register contents that we thought we were saving. 432 */ 433 if (sc->flags & RETAIN_FF_ENABLE) 434 gdsc_retain_ff_on(sc); 435 } else if (sc->flags & ALWAYS_ON) { 436 /* If ALWAYS_ON GDSCs are not ON, turn them ON */ 437 gdsc_enable(&sc->pd); 438 on = true; 439 } 440 441 if (on || (sc->pwrsts & PWRSTS_RET)) 442 gdsc_force_mem_on(sc); 443 else 444 gdsc_clear_mem_on(sc); 445 446 if (sc->flags & ALWAYS_ON) 447 sc->pd.flags |= GENPD_FLAG_ALWAYS_ON; 448 if (!sc->pd.power_off) 449 sc->pd.power_off = gdsc_disable; 450 if (!sc->pd.power_on) 451 sc->pd.power_on = gdsc_enable; 452 453 ret = pm_genpd_init(&sc->pd, NULL, !on); 454 if (ret) 455 goto err_disable_supply; 456 457 return 0; 458 459 err_disable_supply: 460 if (on && sc->rsupply) 461 regulator_disable(sc->rsupply); 462 463 return ret; 464 } 465 466 int gdsc_register(struct gdsc_desc *desc, 467 struct reset_controller_dev *rcdev, struct regmap *regmap) 468 { 469 int i, ret; 470 struct genpd_onecell_data *data; 471 struct device *dev = desc->dev; 472 struct gdsc **scs = desc->scs; 473 size_t num = desc->num; 474 475 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 476 if (!data) 477 return -ENOMEM; 478 479 data->domains = devm_kcalloc(dev, num, sizeof(*data->domains), 480 GFP_KERNEL); 481 if (!data->domains) 482 return -ENOMEM; 483 484 for (i = 0; i < num; i++) { 485 if (!scs[i] || !scs[i]->supply) 486 continue; 487 488 scs[i]->rsupply = devm_regulator_get(dev, scs[i]->supply); 489 if (IS_ERR(scs[i]->rsupply)) 490 return PTR_ERR(scs[i]->rsupply); 491 } 492 493 data->num_domains = num; 494 for (i = 0; i < num; i++) { 495 if (!scs[i]) 496 continue; 497 scs[i]->regmap = regmap; 498 scs[i]->rcdev = rcdev; 499 ret = gdsc_init(scs[i]); 500 if (ret) 501 return ret; 502 data->domains[i] = &scs[i]->pd; 503 } 504 505 /* Add subdomains */ 506 for (i = 0; i < num; i++) { 507 if (!scs[i]) 508 continue; 509 if (scs[i]->parent) 510 pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd); 511 else if (!IS_ERR_OR_NULL(dev->pm_domain)) 512 pm_genpd_add_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd); 513 } 514 515 return of_genpd_add_provider_onecell(dev->of_node, data); 516 } 517 518 void gdsc_unregister(struct gdsc_desc *desc) 519 { 520 int i; 521 struct device *dev = desc->dev; 522 struct gdsc **scs = desc->scs; 523 size_t num = desc->num; 524 525 /* Remove subdomains */ 526 for (i = 0; i < num; i++) { 527 if (!scs[i]) 528 continue; 529 if (scs[i]->parent) 530 pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd); 531 else if (!IS_ERR_OR_NULL(dev->pm_domain)) 532 pm_genpd_remove_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd); 533 } 534 of_genpd_del_provider(dev->of_node); 535 } 536 537 /* 538 * On SDM845+ the GPU GX domain is *almost* entirely controlled by the GMU 539 * running in the CX domain so the CPU doesn't need to know anything about the 540 * GX domain EXCEPT.... 541 * 542 * Hardware constraints dictate that the GX be powered down before the CX. If 543 * the GMU crashes it could leave the GX on. In order to successfully bring back 544 * the device the CPU needs to disable the GX headswitch. There being no sane 545 * way to reach in and touch that register from deep inside the GPU driver we 546 * need to set up the infrastructure to be able to ensure that the GPU can 547 * ensure that the GX is off during this super special case. We do this by 548 * defining a GX gdsc with a dummy enable function and a "default" disable 549 * function. 550 * 551 * This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU 552 * driver. During power up, nothing will happen from the CPU (and the GMU will 553 * power up normally but during power down this will ensure that the GX domain 554 * is *really* off - this gives us a semi standard way of doing what we need. 555 */ 556 int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain) 557 { 558 /* Do nothing but give genpd the impression that we were successful */ 559 return 0; 560 } 561 EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable); 562