1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/bitops.h> 7 #include <linux/delay.h> 8 #include <linux/err.h> 9 #include <linux/jiffies.h> 10 #include <linux/kernel.h> 11 #include <linux/ktime.h> 12 #include <linux/pm_domain.h> 13 #include <linux/regmap.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/reset-controller.h> 16 #include <linux/slab.h> 17 #include "gdsc.h" 18 19 #define PWR_ON_MASK BIT(31) 20 #define EN_REST_WAIT_MASK GENMASK_ULL(23, 20) 21 #define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16) 22 #define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12) 23 #define SW_OVERRIDE_MASK BIT(2) 24 #define HW_CONTROL_MASK BIT(1) 25 #define SW_COLLAPSE_MASK BIT(0) 26 #define GMEM_CLAMP_IO_MASK BIT(0) 27 #define GMEM_RESET_MASK BIT(4) 28 29 /* CFG_GDSCR */ 30 #define GDSC_POWER_UP_COMPLETE BIT(16) 31 #define GDSC_POWER_DOWN_COMPLETE BIT(15) 32 #define CFG_GDSCR_OFFSET 0x4 33 34 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */ 35 #define EN_REST_WAIT_VAL (0x2 << 20) 36 #define EN_FEW_WAIT_VAL (0x8 << 16) 37 #define CLK_DIS_WAIT_VAL (0x2 << 12) 38 39 #define RETAIN_MEM BIT(14) 40 #define RETAIN_PERIPH BIT(13) 41 42 #define TIMEOUT_US 500 43 44 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd) 45 46 enum gdsc_status { 47 GDSC_OFF, 48 GDSC_ON 49 }; 50 51 /* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */ 52 static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status) 53 { 54 unsigned int reg; 55 u32 val; 56 int ret; 57 58 if (sc->flags & POLL_CFG_GDSCR) 59 reg = sc->gdscr + CFG_GDSCR_OFFSET; 60 else if (sc->gds_hw_ctrl) 61 reg = sc->gds_hw_ctrl; 62 else 63 reg = sc->gdscr; 64 65 ret = regmap_read(sc->regmap, reg, &val); 66 if (ret) 67 return ret; 68 69 if (sc->flags & POLL_CFG_GDSCR) { 70 switch (status) { 71 case GDSC_ON: 72 return !!(val & GDSC_POWER_UP_COMPLETE); 73 case GDSC_OFF: 74 return !!(val & GDSC_POWER_DOWN_COMPLETE); 75 } 76 } 77 78 switch (status) { 79 case GDSC_ON: 80 return !!(val & PWR_ON_MASK); 81 case GDSC_OFF: 82 return !(val & PWR_ON_MASK); 83 } 84 85 return -EINVAL; 86 } 87 88 static int gdsc_hwctrl(struct gdsc *sc, bool en) 89 { 90 u32 val = en ? HW_CONTROL_MASK : 0; 91 92 return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val); 93 } 94 95 static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status) 96 { 97 ktime_t start; 98 99 start = ktime_get(); 100 do { 101 if (gdsc_check_status(sc, status)) 102 return 0; 103 } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US); 104 105 if (gdsc_check_status(sc, status)) 106 return 0; 107 108 return -ETIMEDOUT; 109 } 110 111 static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status) 112 { 113 int ret; 114 u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK; 115 116 if (status == GDSC_ON && sc->rsupply) { 117 ret = regulator_enable(sc->rsupply); 118 if (ret < 0) 119 return ret; 120 } 121 122 ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val); 123 if (ret) 124 return ret; 125 126 /* If disabling votable gdscs, don't poll on status */ 127 if ((sc->flags & VOTABLE) && status == GDSC_OFF) { 128 /* 129 * Add a short delay here to ensure that an enable 130 * right after it was disabled does not put it in an 131 * unknown state 132 */ 133 udelay(TIMEOUT_US); 134 return 0; 135 } 136 137 if (sc->gds_hw_ctrl) { 138 /* 139 * The gds hw controller asserts/de-asserts the status bit soon 140 * after it receives a power on/off request from a master. 141 * The controller then takes around 8 xo cycles to start its 142 * internal state machine and update the status bit. During 143 * this time, the status bit does not reflect the true status 144 * of the core. 145 * Add a delay of 1 us between writing to the SW_COLLAPSE bit 146 * and polling the status bit. 147 */ 148 udelay(1); 149 } 150 151 ret = gdsc_poll_status(sc, status); 152 WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n"); 153 154 if (!ret && status == GDSC_OFF && sc->rsupply) { 155 ret = regulator_disable(sc->rsupply); 156 if (ret < 0) 157 return ret; 158 } 159 160 return ret; 161 } 162 163 static inline int gdsc_deassert_reset(struct gdsc *sc) 164 { 165 int i; 166 167 for (i = 0; i < sc->reset_count; i++) 168 sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]); 169 return 0; 170 } 171 172 static inline int gdsc_assert_reset(struct gdsc *sc) 173 { 174 int i; 175 176 for (i = 0; i < sc->reset_count; i++) 177 sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]); 178 return 0; 179 } 180 181 static inline void gdsc_force_mem_on(struct gdsc *sc) 182 { 183 int i; 184 u32 mask = RETAIN_MEM | RETAIN_PERIPH; 185 186 for (i = 0; i < sc->cxc_count; i++) 187 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask); 188 } 189 190 static inline void gdsc_clear_mem_on(struct gdsc *sc) 191 { 192 int i; 193 u32 mask = RETAIN_MEM | RETAIN_PERIPH; 194 195 for (i = 0; i < sc->cxc_count; i++) 196 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0); 197 } 198 199 static inline void gdsc_deassert_clamp_io(struct gdsc *sc) 200 { 201 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl, 202 GMEM_CLAMP_IO_MASK, 0); 203 } 204 205 static inline void gdsc_assert_clamp_io(struct gdsc *sc) 206 { 207 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl, 208 GMEM_CLAMP_IO_MASK, 1); 209 } 210 211 static inline void gdsc_assert_reset_aon(struct gdsc *sc) 212 { 213 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl, 214 GMEM_RESET_MASK, 1); 215 udelay(1); 216 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl, 217 GMEM_RESET_MASK, 0); 218 } 219 static int gdsc_enable(struct generic_pm_domain *domain) 220 { 221 struct gdsc *sc = domain_to_gdsc(domain); 222 int ret; 223 224 if (sc->pwrsts == PWRSTS_ON) 225 return gdsc_deassert_reset(sc); 226 227 if (sc->flags & SW_RESET) { 228 gdsc_assert_reset(sc); 229 udelay(1); 230 gdsc_deassert_reset(sc); 231 } 232 233 if (sc->flags & CLAMP_IO) { 234 if (sc->flags & AON_RESET) 235 gdsc_assert_reset_aon(sc); 236 gdsc_deassert_clamp_io(sc); 237 } 238 239 ret = gdsc_toggle_logic(sc, GDSC_ON); 240 if (ret) 241 return ret; 242 243 if (sc->pwrsts & PWRSTS_OFF) 244 gdsc_force_mem_on(sc); 245 246 /* 247 * If clocks to this power domain were already on, they will take an 248 * additional 4 clock cycles to re-enable after the power domain is 249 * enabled. Delay to account for this. A delay is also needed to ensure 250 * clocks are not enabled within 400ns of enabling power to the 251 * memories. 252 */ 253 udelay(1); 254 255 /* Turn on HW trigger mode if supported */ 256 if (sc->flags & HW_CTRL) { 257 ret = gdsc_hwctrl(sc, true); 258 if (ret) 259 return ret; 260 /* 261 * Wait for the GDSC to go through a power down and 262 * up cycle. In case a firmware ends up polling status 263 * bits for the gdsc, it might read an 'on' status before 264 * the GDSC can finish the power cycle. 265 * We wait 1us before returning to ensure the firmware 266 * can't immediately poll the status bits. 267 */ 268 udelay(1); 269 } 270 271 return 0; 272 } 273 274 static int gdsc_disable(struct generic_pm_domain *domain) 275 { 276 struct gdsc *sc = domain_to_gdsc(domain); 277 int ret; 278 279 if (sc->pwrsts == PWRSTS_ON) 280 return gdsc_assert_reset(sc); 281 282 /* Turn off HW trigger mode if supported */ 283 if (sc->flags & HW_CTRL) { 284 ret = gdsc_hwctrl(sc, false); 285 if (ret < 0) 286 return ret; 287 /* 288 * Wait for the GDSC to go through a power down and 289 * up cycle. In case we end up polling status 290 * bits for the gdsc before the power cycle is completed 291 * it might read an 'on' status wrongly. 292 */ 293 udelay(1); 294 295 ret = gdsc_poll_status(sc, GDSC_ON); 296 if (ret) 297 return ret; 298 } 299 300 if (sc->pwrsts & PWRSTS_OFF) 301 gdsc_clear_mem_on(sc); 302 303 ret = gdsc_toggle_logic(sc, GDSC_OFF); 304 if (ret) 305 return ret; 306 307 if (sc->flags & CLAMP_IO) 308 gdsc_assert_clamp_io(sc); 309 310 return 0; 311 } 312 313 static int gdsc_init(struct gdsc *sc) 314 { 315 u32 mask, val; 316 int on, ret; 317 318 /* 319 * Disable HW trigger: collapse/restore occur based on registers writes. 320 * Disable SW override: Use hardware state-machine for sequencing. 321 * Configure wait time between states. 322 */ 323 mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK | 324 EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK; 325 val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL; 326 ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val); 327 if (ret) 328 return ret; 329 330 /* Force gdsc ON if only ON state is supported */ 331 if (sc->pwrsts == PWRSTS_ON) { 332 ret = gdsc_toggle_logic(sc, GDSC_ON); 333 if (ret) 334 return ret; 335 } 336 337 on = gdsc_check_status(sc, GDSC_ON); 338 if (on < 0) 339 return on; 340 341 /* 342 * Votable GDSCs can be ON due to Vote from other masters. 343 * If a Votable GDSC is ON, make sure we have a Vote. 344 */ 345 if ((sc->flags & VOTABLE) && on) 346 gdsc_enable(&sc->pd); 347 348 /* If ALWAYS_ON GDSCs are not ON, turn them ON */ 349 if (sc->flags & ALWAYS_ON) { 350 if (!on) 351 gdsc_enable(&sc->pd); 352 on = true; 353 sc->pd.flags |= GENPD_FLAG_ALWAYS_ON; 354 } 355 356 if (on || (sc->pwrsts & PWRSTS_RET)) 357 gdsc_force_mem_on(sc); 358 else 359 gdsc_clear_mem_on(sc); 360 361 if (!sc->pd.power_off) 362 sc->pd.power_off = gdsc_disable; 363 if (!sc->pd.power_on) 364 sc->pd.power_on = gdsc_enable; 365 pm_genpd_init(&sc->pd, NULL, !on); 366 367 return 0; 368 } 369 370 int gdsc_register(struct gdsc_desc *desc, 371 struct reset_controller_dev *rcdev, struct regmap *regmap) 372 { 373 int i, ret; 374 struct genpd_onecell_data *data; 375 struct device *dev = desc->dev; 376 struct gdsc **scs = desc->scs; 377 size_t num = desc->num; 378 379 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 380 if (!data) 381 return -ENOMEM; 382 383 data->domains = devm_kcalloc(dev, num, sizeof(*data->domains), 384 GFP_KERNEL); 385 if (!data->domains) 386 return -ENOMEM; 387 388 for (i = 0; i < num; i++) { 389 if (!scs[i] || !scs[i]->supply) 390 continue; 391 392 scs[i]->rsupply = devm_regulator_get(dev, scs[i]->supply); 393 if (IS_ERR(scs[i]->rsupply)) 394 return PTR_ERR(scs[i]->rsupply); 395 } 396 397 data->num_domains = num; 398 for (i = 0; i < num; i++) { 399 if (!scs[i]) 400 continue; 401 scs[i]->regmap = regmap; 402 scs[i]->rcdev = rcdev; 403 ret = gdsc_init(scs[i]); 404 if (ret) 405 return ret; 406 data->domains[i] = &scs[i]->pd; 407 } 408 409 /* Add subdomains */ 410 for (i = 0; i < num; i++) { 411 if (!scs[i]) 412 continue; 413 if (scs[i]->parent) 414 pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd); 415 } 416 417 return of_genpd_add_provider_onecell(dev->of_node, data); 418 } 419 420 void gdsc_unregister(struct gdsc_desc *desc) 421 { 422 int i; 423 struct device *dev = desc->dev; 424 struct gdsc **scs = desc->scs; 425 size_t num = desc->num; 426 427 /* Remove subdomains */ 428 for (i = 0; i < num; i++) { 429 if (!scs[i]) 430 continue; 431 if (scs[i]->parent) 432 pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd); 433 } 434 of_genpd_del_provider(dev->of_node); 435 } 436