1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 5 * Copyright (c) 2022, Linaro Limited 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/module.h> 10 #include <linux/of_device.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/clock/qcom,sm8550-gcc.h> 14 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "clk-regmap-phy-mux.h" 22 #include "gdsc.h" 23 #include "reset.h" 24 25 enum { 26 DT_BI_TCXO, 27 DT_SLEEP_CLK, 28 DT_PCIE_0_PIPE, 29 DT_PCIE_1_PIPE, 30 DT_PCIE_1_PHY_AUX, 31 DT_UFS_PHY_RX_SYMBOL_0, 32 DT_UFS_PHY_RX_SYMBOL_1, 33 DT_UFS_PHY_TX_SYMBOL_0, 34 DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE, 35 }; 36 37 enum { 38 P_BI_TCXO, 39 P_GCC_GPLL0_OUT_EVEN, 40 P_GCC_GPLL0_OUT_MAIN, 41 P_GCC_GPLL4_OUT_MAIN, 42 P_GCC_GPLL7_OUT_MAIN, 43 P_GCC_GPLL9_OUT_MAIN, 44 P_PCIE_0_PIPE_CLK, 45 P_PCIE_1_PHY_AUX_CLK, 46 P_PCIE_1_PIPE_CLK, 47 P_SLEEP_CLK, 48 P_UFS_PHY_RX_SYMBOL_0_CLK, 49 P_UFS_PHY_RX_SYMBOL_1_CLK, 50 P_UFS_PHY_TX_SYMBOL_0_CLK, 51 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 52 }; 53 54 static struct clk_alpha_pll gcc_gpll0 = { 55 .offset = 0x0, 56 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 57 .clkr = { 58 .enable_reg = 0x52018, 59 .enable_mask = BIT(0), 60 .hw.init = &(struct clk_init_data){ 61 .name = "gcc_gpll0", 62 .parent_data = &(const struct clk_parent_data){ 63 .index = DT_BI_TCXO, 64 }, 65 .num_parents = 1, 66 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 67 }, 68 }, 69 }; 70 71 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 72 { 0x1, 2 }, 73 { } 74 }; 75 76 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 77 .offset = 0x0, 78 .post_div_shift = 10, 79 .post_div_table = post_div_table_gcc_gpll0_out_even, 80 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 81 .width = 4, 82 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 83 .clkr.hw.init = &(struct clk_init_data){ 84 .name = "gcc_gpll0_out_even", 85 .parent_hws = (const struct clk_hw*[]) { 86 &gcc_gpll0.clkr.hw, 87 }, 88 .num_parents = 1, 89 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 90 }, 91 }; 92 93 static struct clk_alpha_pll gcc_gpll4 = { 94 .offset = 0x4000, 95 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 96 .clkr = { 97 .enable_reg = 0x52018, 98 .enable_mask = BIT(4), 99 .hw.init = &(struct clk_init_data){ 100 .name = "gcc_gpll4", 101 .parent_data = &(const struct clk_parent_data){ 102 .index = DT_BI_TCXO, 103 }, 104 .num_parents = 1, 105 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 106 }, 107 }, 108 }; 109 110 static struct clk_alpha_pll gcc_gpll7 = { 111 .offset = 0x7000, 112 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 113 .clkr = { 114 .enable_reg = 0x52018, 115 .enable_mask = BIT(7), 116 .hw.init = &(struct clk_init_data){ 117 .name = "gcc_gpll7", 118 .parent_data = &(const struct clk_parent_data){ 119 .index = DT_BI_TCXO, 120 }, 121 .num_parents = 1, 122 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 123 }, 124 }, 125 }; 126 127 static struct clk_alpha_pll gcc_gpll9 = { 128 .offset = 0x9000, 129 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 130 .clkr = { 131 .enable_reg = 0x52018, 132 .enable_mask = BIT(9), 133 .hw.init = &(struct clk_init_data){ 134 .name = "gcc_gpll9", 135 .parent_data = &(const struct clk_parent_data){ 136 .index = DT_BI_TCXO, 137 }, 138 .num_parents = 1, 139 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 140 }, 141 }, 142 }; 143 144 static const struct parent_map gcc_parent_map_0[] = { 145 { P_BI_TCXO, 0 }, 146 { P_GCC_GPLL0_OUT_MAIN, 1 }, 147 { P_GCC_GPLL0_OUT_EVEN, 6 }, 148 }; 149 150 static const struct clk_parent_data gcc_parent_data_0[] = { 151 { .index = DT_BI_TCXO }, 152 { .hw = &gcc_gpll0.clkr.hw }, 153 { .hw = &gcc_gpll0_out_even.clkr.hw }, 154 }; 155 156 static const struct parent_map gcc_parent_map_1[] = { 157 { P_BI_TCXO, 0 }, 158 { P_GCC_GPLL0_OUT_MAIN, 1 }, 159 { P_SLEEP_CLK, 5 }, 160 { P_GCC_GPLL0_OUT_EVEN, 6 }, 161 }; 162 163 static const struct clk_parent_data gcc_parent_data_1[] = { 164 { .index = DT_BI_TCXO }, 165 { .hw = &gcc_gpll0.clkr.hw }, 166 { .index = DT_SLEEP_CLK }, 167 { .hw = &gcc_gpll0_out_even.clkr.hw }, 168 }; 169 170 static const struct parent_map gcc_parent_map_2[] = { 171 { P_BI_TCXO, 0 }, 172 { P_SLEEP_CLK, 5 }, 173 }; 174 175 static const struct clk_parent_data gcc_parent_data_2[] = { 176 { .index = DT_BI_TCXO }, 177 { .index = DT_SLEEP_CLK }, 178 }; 179 180 static const struct parent_map gcc_parent_map_3[] = { 181 { P_BI_TCXO, 0 }, 182 { P_GCC_GPLL0_OUT_MAIN, 1 }, 183 { P_GCC_GPLL4_OUT_MAIN, 5 }, 184 { P_GCC_GPLL0_OUT_EVEN, 6 }, 185 }; 186 187 static const struct clk_parent_data gcc_parent_data_3[] = { 188 { .index = DT_BI_TCXO }, 189 { .hw = &gcc_gpll0.clkr.hw }, 190 { .hw = &gcc_gpll4.clkr.hw }, 191 { .hw = &gcc_gpll0_out_even.clkr.hw }, 192 }; 193 194 static const struct parent_map gcc_parent_map_4[] = { 195 { P_BI_TCXO, 0 }, 196 }; 197 198 static const struct clk_parent_data gcc_parent_data_4[] = { 199 { .index = DT_BI_TCXO }, 200 }; 201 202 static const struct parent_map gcc_parent_map_6[] = { 203 { P_PCIE_1_PHY_AUX_CLK, 0 }, 204 { P_BI_TCXO, 2 }, 205 }; 206 207 static const struct clk_parent_data gcc_parent_data_6[] = { 208 { .index = DT_PCIE_1_PHY_AUX }, 209 { .index = DT_BI_TCXO }, 210 }; 211 212 static const struct parent_map gcc_parent_map_8[] = { 213 { P_BI_TCXO, 0 }, 214 { P_GCC_GPLL0_OUT_MAIN, 1 }, 215 { P_GCC_GPLL7_OUT_MAIN, 2 }, 216 { P_GCC_GPLL0_OUT_EVEN, 6 }, 217 }; 218 219 static const struct clk_parent_data gcc_parent_data_8[] = { 220 { .index = DT_BI_TCXO }, 221 { .hw = &gcc_gpll0.clkr.hw }, 222 { .hw = &gcc_gpll7.clkr.hw }, 223 { .hw = &gcc_gpll0_out_even.clkr.hw }, 224 }; 225 226 static const struct parent_map gcc_parent_map_9[] = { 227 { P_BI_TCXO, 0 }, 228 { P_GCC_GPLL0_OUT_MAIN, 1 }, 229 { P_GCC_GPLL9_OUT_MAIN, 2 }, 230 { P_GCC_GPLL4_OUT_MAIN, 5 }, 231 { P_GCC_GPLL0_OUT_EVEN, 6 }, 232 }; 233 234 static const struct clk_parent_data gcc_parent_data_9[] = { 235 { .index = DT_BI_TCXO }, 236 { .hw = &gcc_gpll0.clkr.hw }, 237 { .hw = &gcc_gpll9.clkr.hw }, 238 { .hw = &gcc_gpll4.clkr.hw }, 239 { .hw = &gcc_gpll0_out_even.clkr.hw }, 240 }; 241 242 static const struct parent_map gcc_parent_map_10[] = { 243 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, 244 { P_BI_TCXO, 2 }, 245 }; 246 247 static const struct clk_parent_data gcc_parent_data_10[] = { 248 { .index = DT_UFS_PHY_RX_SYMBOL_0 }, 249 { .index = DT_BI_TCXO }, 250 }; 251 252 static const struct parent_map gcc_parent_map_11[] = { 253 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, 254 { P_BI_TCXO, 2 }, 255 }; 256 257 static const struct clk_parent_data gcc_parent_data_11[] = { 258 { .index = DT_UFS_PHY_RX_SYMBOL_1 }, 259 { .index = DT_BI_TCXO }, 260 }; 261 262 static const struct parent_map gcc_parent_map_12[] = { 263 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, 264 { P_BI_TCXO, 2 }, 265 }; 266 267 static const struct clk_parent_data gcc_parent_data_12[] = { 268 { .index = DT_UFS_PHY_TX_SYMBOL_0 }, 269 { .index = DT_BI_TCXO }, 270 }; 271 272 static const struct parent_map gcc_parent_map_13[] = { 273 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 274 { P_BI_TCXO, 2 }, 275 }; 276 277 static const struct clk_parent_data gcc_parent_data_13[] = { 278 { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE }, 279 { .index = DT_BI_TCXO }, 280 }; 281 282 static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { 283 .reg = 0x6b070, 284 .clkr = { 285 .hw.init = &(struct clk_init_data){ 286 .name = "gcc_pcie_0_pipe_clk_src", 287 .parent_data = &(const struct clk_parent_data){ 288 .index = DT_PCIE_0_PIPE, 289 }, 290 .num_parents = 1, 291 .ops = &clk_regmap_phy_mux_ops, 292 }, 293 }, 294 }; 295 296 static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = { 297 .reg = 0x8d094, 298 .shift = 0, 299 .width = 2, 300 .parent_map = gcc_parent_map_6, 301 .clkr = { 302 .hw.init = &(struct clk_init_data){ 303 .name = "gcc_pcie_1_phy_aux_clk_src", 304 .parent_data = gcc_parent_data_6, 305 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 306 .ops = &clk_regmap_mux_closest_ops, 307 }, 308 }, 309 }; 310 311 static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = { 312 .reg = 0x8d078, 313 .clkr = { 314 .hw.init = &(struct clk_init_data){ 315 .name = "gcc_pcie_1_pipe_clk_src", 316 .parent_data = &(const struct clk_parent_data){ 317 .index = DT_PCIE_1_PIPE, 318 }, 319 .num_parents = 1, 320 .ops = &clk_regmap_phy_mux_ops, 321 }, 322 }, 323 }; 324 325 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 326 .reg = 0x77064, 327 .shift = 0, 328 .width = 2, 329 .parent_map = gcc_parent_map_10, 330 .clkr = { 331 .hw.init = &(struct clk_init_data){ 332 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 333 .parent_data = gcc_parent_data_10, 334 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 335 .ops = &clk_regmap_mux_closest_ops, 336 }, 337 }, 338 }; 339 340 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 341 .reg = 0x770e0, 342 .shift = 0, 343 .width = 2, 344 .parent_map = gcc_parent_map_11, 345 .clkr = { 346 .hw.init = &(struct clk_init_data){ 347 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 348 .parent_data = gcc_parent_data_11, 349 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 350 .ops = &clk_regmap_mux_closest_ops, 351 }, 352 }, 353 }; 354 355 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 356 .reg = 0x77054, 357 .shift = 0, 358 .width = 2, 359 .parent_map = gcc_parent_map_12, 360 .clkr = { 361 .hw.init = &(struct clk_init_data){ 362 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 363 .parent_data = gcc_parent_data_12, 364 .num_parents = ARRAY_SIZE(gcc_parent_data_12), 365 .ops = &clk_regmap_mux_closest_ops, 366 }, 367 }, 368 }; 369 370 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 371 .reg = 0x3906c, 372 .shift = 0, 373 .width = 2, 374 .parent_map = gcc_parent_map_13, 375 .clkr = { 376 .hw.init = &(struct clk_init_data){ 377 .name = "gcc_usb3_prim_phy_pipe_clk_src", 378 .parent_data = gcc_parent_data_13, 379 .num_parents = ARRAY_SIZE(gcc_parent_data_13), 380 .ops = &clk_regmap_mux_closest_ops, 381 }, 382 }, 383 }; 384 385 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 386 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 387 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 388 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 389 { } 390 }; 391 392 static struct clk_rcg2 gcc_gp1_clk_src = { 393 .cmd_rcgr = 0x64004, 394 .mnd_width = 16, 395 .hid_width = 5, 396 .parent_map = gcc_parent_map_1, 397 .freq_tbl = ftbl_gcc_gp1_clk_src, 398 .clkr.hw.init = &(struct clk_init_data){ 399 .name = "gcc_gp1_clk_src", 400 .parent_data = gcc_parent_data_1, 401 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 402 .flags = CLK_SET_RATE_PARENT, 403 .ops = &clk_rcg2_ops, 404 }, 405 }; 406 407 static struct clk_rcg2 gcc_gp2_clk_src = { 408 .cmd_rcgr = 0x65004, 409 .mnd_width = 16, 410 .hid_width = 5, 411 .parent_map = gcc_parent_map_1, 412 .freq_tbl = ftbl_gcc_gp1_clk_src, 413 .clkr.hw.init = &(struct clk_init_data){ 414 .name = "gcc_gp2_clk_src", 415 .parent_data = gcc_parent_data_1, 416 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 417 .flags = CLK_SET_RATE_PARENT, 418 .ops = &clk_rcg2_ops, 419 }, 420 }; 421 422 static struct clk_rcg2 gcc_gp3_clk_src = { 423 .cmd_rcgr = 0x66004, 424 .mnd_width = 16, 425 .hid_width = 5, 426 .parent_map = gcc_parent_map_1, 427 .freq_tbl = ftbl_gcc_gp1_clk_src, 428 .clkr.hw.init = &(struct clk_init_data){ 429 .name = "gcc_gp3_clk_src", 430 .parent_data = gcc_parent_data_1, 431 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 432 .flags = CLK_SET_RATE_PARENT, 433 .ops = &clk_rcg2_ops, 434 }, 435 }; 436 437 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 438 F(19200000, P_BI_TCXO, 1, 0, 0), 439 { } 440 }; 441 442 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 443 .cmd_rcgr = 0x6b074, 444 .mnd_width = 16, 445 .hid_width = 5, 446 .parent_map = gcc_parent_map_2, 447 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 448 .clkr.hw.init = &(struct clk_init_data){ 449 .name = "gcc_pcie_0_aux_clk_src", 450 .parent_data = gcc_parent_data_2, 451 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 452 .flags = CLK_SET_RATE_PARENT, 453 .ops = &clk_rcg2_ops, 454 }, 455 }; 456 457 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 458 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 459 { } 460 }; 461 462 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 463 .cmd_rcgr = 0x6b058, 464 .mnd_width = 0, 465 .hid_width = 5, 466 .parent_map = gcc_parent_map_0, 467 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 468 .clkr.hw.init = &(struct clk_init_data){ 469 .name = "gcc_pcie_0_phy_rchng_clk_src", 470 .parent_data = gcc_parent_data_0, 471 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 472 .flags = CLK_SET_RATE_PARENT, 473 .ops = &clk_rcg2_ops, 474 }, 475 }; 476 477 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 478 .cmd_rcgr = 0x8d07c, 479 .mnd_width = 16, 480 .hid_width = 5, 481 .parent_map = gcc_parent_map_2, 482 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 483 .clkr.hw.init = &(struct clk_init_data){ 484 .name = "gcc_pcie_1_aux_clk_src", 485 .parent_data = gcc_parent_data_2, 486 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 487 .flags = CLK_SET_RATE_PARENT, 488 .ops = &clk_rcg2_ops, 489 }, 490 }; 491 492 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 493 .cmd_rcgr = 0x8d060, 494 .mnd_width = 0, 495 .hid_width = 5, 496 .parent_map = gcc_parent_map_0, 497 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 498 .clkr.hw.init = &(struct clk_init_data){ 499 .name = "gcc_pcie_1_phy_rchng_clk_src", 500 .parent_data = gcc_parent_data_0, 501 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 502 .flags = CLK_SET_RATE_PARENT, 503 .ops = &clk_rcg2_ops, 504 }, 505 }; 506 507 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 508 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 509 { } 510 }; 511 512 static struct clk_rcg2 gcc_pdm2_clk_src = { 513 .cmd_rcgr = 0x33010, 514 .mnd_width = 0, 515 .hid_width = 5, 516 .parent_map = gcc_parent_map_0, 517 .freq_tbl = ftbl_gcc_pdm2_clk_src, 518 .clkr.hw.init = &(struct clk_init_data){ 519 .name = "gcc_pdm2_clk_src", 520 .parent_data = gcc_parent_data_0, 521 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 522 .flags = CLK_SET_RATE_PARENT, 523 .ops = &clk_rcg2_ops, 524 }, 525 }; 526 527 static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = { 528 .cmd_rcgr = 0x17008, 529 .mnd_width = 0, 530 .hid_width = 5, 531 .parent_map = gcc_parent_map_0, 532 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 533 .clkr.hw.init = &(struct clk_init_data){ 534 .name = "gcc_qupv3_i2c_s0_clk_src", 535 .parent_data = gcc_parent_data_0, 536 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 537 .flags = CLK_SET_RATE_PARENT, 538 .ops = &clk_rcg2_ops, 539 }, 540 }; 541 542 static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = { 543 .cmd_rcgr = 0x17024, 544 .mnd_width = 0, 545 .hid_width = 5, 546 .parent_map = gcc_parent_map_0, 547 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 548 .clkr.hw.init = &(struct clk_init_data){ 549 .name = "gcc_qupv3_i2c_s1_clk_src", 550 .parent_data = gcc_parent_data_0, 551 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 552 .flags = CLK_SET_RATE_PARENT, 553 .ops = &clk_rcg2_ops, 554 }, 555 }; 556 557 static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = { 558 .cmd_rcgr = 0x17040, 559 .mnd_width = 0, 560 .hid_width = 5, 561 .parent_map = gcc_parent_map_0, 562 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 563 .clkr.hw.init = &(struct clk_init_data){ 564 .name = "gcc_qupv3_i2c_s2_clk_src", 565 .parent_data = gcc_parent_data_0, 566 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 567 .flags = CLK_SET_RATE_PARENT, 568 .ops = &clk_rcg2_ops, 569 }, 570 }; 571 572 static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = { 573 .cmd_rcgr = 0x1705c, 574 .mnd_width = 0, 575 .hid_width = 5, 576 .parent_map = gcc_parent_map_0, 577 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 578 .clkr.hw.init = &(struct clk_init_data){ 579 .name = "gcc_qupv3_i2c_s3_clk_src", 580 .parent_data = gcc_parent_data_0, 581 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 582 .flags = CLK_SET_RATE_PARENT, 583 .ops = &clk_rcg2_ops, 584 }, 585 }; 586 587 static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = { 588 .cmd_rcgr = 0x17078, 589 .mnd_width = 0, 590 .hid_width = 5, 591 .parent_map = gcc_parent_map_0, 592 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 593 .clkr.hw.init = &(struct clk_init_data){ 594 .name = "gcc_qupv3_i2c_s4_clk_src", 595 .parent_data = gcc_parent_data_0, 596 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 597 .flags = CLK_SET_RATE_PARENT, 598 .ops = &clk_rcg2_ops, 599 }, 600 }; 601 602 static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = { 603 .cmd_rcgr = 0x17094, 604 .mnd_width = 0, 605 .hid_width = 5, 606 .parent_map = gcc_parent_map_0, 607 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 608 .clkr.hw.init = &(struct clk_init_data){ 609 .name = "gcc_qupv3_i2c_s5_clk_src", 610 .parent_data = gcc_parent_data_0, 611 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 612 .flags = CLK_SET_RATE_PARENT, 613 .ops = &clk_rcg2_ops, 614 }, 615 }; 616 617 static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = { 618 .cmd_rcgr = 0x170b0, 619 .mnd_width = 0, 620 .hid_width = 5, 621 .parent_map = gcc_parent_map_0, 622 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 623 .clkr.hw.init = &(struct clk_init_data){ 624 .name = "gcc_qupv3_i2c_s6_clk_src", 625 .parent_data = gcc_parent_data_0, 626 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 627 .flags = CLK_SET_RATE_PARENT, 628 .ops = &clk_rcg2_ops, 629 }, 630 }; 631 632 static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = { 633 .cmd_rcgr = 0x170cc, 634 .mnd_width = 0, 635 .hid_width = 5, 636 .parent_map = gcc_parent_map_0, 637 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 638 .clkr.hw.init = &(struct clk_init_data){ 639 .name = "gcc_qupv3_i2c_s7_clk_src", 640 .parent_data = gcc_parent_data_0, 641 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 642 .flags = CLK_SET_RATE_PARENT, 643 .ops = &clk_rcg2_ops, 644 }, 645 }; 646 647 static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = { 648 .cmd_rcgr = 0x170e8, 649 .mnd_width = 0, 650 .hid_width = 5, 651 .parent_map = gcc_parent_map_0, 652 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 653 .clkr.hw.init = &(struct clk_init_data){ 654 .name = "gcc_qupv3_i2c_s8_clk_src", 655 .parent_data = gcc_parent_data_0, 656 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 657 .flags = CLK_SET_RATE_PARENT, 658 .ops = &clk_rcg2_ops, 659 }, 660 }; 661 662 static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = { 663 .cmd_rcgr = 0x17104, 664 .mnd_width = 0, 665 .hid_width = 5, 666 .parent_map = gcc_parent_map_0, 667 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 668 .clkr.hw.init = &(struct clk_init_data){ 669 .name = "gcc_qupv3_i2c_s9_clk_src", 670 .parent_data = gcc_parent_data_0, 671 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 672 .flags = CLK_SET_RATE_PARENT, 673 .ops = &clk_rcg2_ops, 674 }, 675 }; 676 677 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = { 678 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 679 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 680 F(19200000, P_BI_TCXO, 1, 0, 0), 681 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 682 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 683 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 684 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 685 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 686 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 687 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 688 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 689 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 690 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 691 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 692 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 693 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 694 { } 695 }; 696 697 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 698 .name = "gcc_qupv3_wrap1_s0_clk_src", 699 .parent_data = gcc_parent_data_0, 700 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 701 .flags = CLK_SET_RATE_PARENT, 702 .ops = &clk_rcg2_ops, 703 }; 704 705 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 706 .cmd_rcgr = 0x18010, 707 .mnd_width = 16, 708 .hid_width = 5, 709 .parent_map = gcc_parent_map_0, 710 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 711 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 712 }; 713 714 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 715 .name = "gcc_qupv3_wrap1_s1_clk_src", 716 .parent_data = gcc_parent_data_0, 717 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 718 .flags = CLK_SET_RATE_PARENT, 719 .ops = &clk_rcg2_ops, 720 }; 721 722 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 723 .cmd_rcgr = 0x18148, 724 .mnd_width = 16, 725 .hid_width = 5, 726 .parent_map = gcc_parent_map_0, 727 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 728 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 729 }; 730 731 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s2_clk_src[] = { 732 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 733 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 734 F(19200000, P_BI_TCXO, 1, 0, 0), 735 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 736 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 737 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 738 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 739 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 740 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 741 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 742 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 743 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 744 { } 745 }; 746 747 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 748 .name = "gcc_qupv3_wrap1_s2_clk_src", 749 .parent_data = gcc_parent_data_0, 750 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 751 .flags = CLK_SET_RATE_PARENT, 752 .ops = &clk_rcg2_ops, 753 }; 754 755 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 756 .cmd_rcgr = 0x18280, 757 .mnd_width = 16, 758 .hid_width = 5, 759 .parent_map = gcc_parent_map_0, 760 .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 761 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 762 }; 763 764 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 765 .name = "gcc_qupv3_wrap1_s3_clk_src", 766 .parent_data = gcc_parent_data_0, 767 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 768 .flags = CLK_SET_RATE_PARENT, 769 .ops = &clk_rcg2_ops, 770 }; 771 772 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 773 .cmd_rcgr = 0x183b8, 774 .mnd_width = 16, 775 .hid_width = 5, 776 .parent_map = gcc_parent_map_0, 777 .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 778 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 779 }; 780 781 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 782 .name = "gcc_qupv3_wrap1_s4_clk_src", 783 .parent_data = gcc_parent_data_0, 784 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 785 .flags = CLK_SET_RATE_PARENT, 786 .ops = &clk_rcg2_ops, 787 }; 788 789 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 790 .cmd_rcgr = 0x184f0, 791 .mnd_width = 16, 792 .hid_width = 5, 793 .parent_map = gcc_parent_map_0, 794 .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 795 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 796 }; 797 798 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 799 .name = "gcc_qupv3_wrap1_s5_clk_src", 800 .parent_data = gcc_parent_data_0, 801 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 802 .flags = CLK_SET_RATE_PARENT, 803 .ops = &clk_rcg2_ops, 804 }; 805 806 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 807 .cmd_rcgr = 0x18628, 808 .mnd_width = 16, 809 .hid_width = 5, 810 .parent_map = gcc_parent_map_0, 811 .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 812 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 813 }; 814 815 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 816 .name = "gcc_qupv3_wrap1_s6_clk_src", 817 .parent_data = gcc_parent_data_0, 818 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 819 .flags = CLK_SET_RATE_PARENT, 820 .ops = &clk_rcg2_ops, 821 }; 822 823 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 824 .cmd_rcgr = 0x18760, 825 .mnd_width = 16, 826 .hid_width = 5, 827 .parent_map = gcc_parent_map_0, 828 .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 829 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 830 }; 831 832 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 833 .name = "gcc_qupv3_wrap1_s7_clk_src", 834 .parent_data = gcc_parent_data_0, 835 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 836 .flags = CLK_SET_RATE_PARENT, 837 .ops = &clk_rcg2_ops, 838 }; 839 840 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 841 .cmd_rcgr = 0x18898, 842 .mnd_width = 16, 843 .hid_width = 5, 844 .parent_map = gcc_parent_map_0, 845 .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 846 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 847 }; 848 849 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 850 .name = "gcc_qupv3_wrap2_s0_clk_src", 851 .parent_data = gcc_parent_data_0, 852 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 853 .flags = CLK_SET_RATE_PARENT, 854 .ops = &clk_rcg2_ops, 855 }; 856 857 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 858 .cmd_rcgr = 0x1e010, 859 .mnd_width = 16, 860 .hid_width = 5, 861 .parent_map = gcc_parent_map_0, 862 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 863 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 864 }; 865 866 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 867 .name = "gcc_qupv3_wrap2_s1_clk_src", 868 .parent_data = gcc_parent_data_0, 869 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 870 .flags = CLK_SET_RATE_PARENT, 871 .ops = &clk_rcg2_ops, 872 }; 873 874 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 875 .cmd_rcgr = 0x1e148, 876 .mnd_width = 16, 877 .hid_width = 5, 878 .parent_map = gcc_parent_map_0, 879 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 880 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 881 }; 882 883 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 884 .name = "gcc_qupv3_wrap2_s2_clk_src", 885 .parent_data = gcc_parent_data_0, 886 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 887 .flags = CLK_SET_RATE_PARENT, 888 .ops = &clk_rcg2_ops, 889 }; 890 891 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 892 .cmd_rcgr = 0x1e280, 893 .mnd_width = 16, 894 .hid_width = 5, 895 .parent_map = gcc_parent_map_0, 896 .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 897 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 898 }; 899 900 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 901 .name = "gcc_qupv3_wrap2_s3_clk_src", 902 .parent_data = gcc_parent_data_0, 903 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 904 .flags = CLK_SET_RATE_PARENT, 905 .ops = &clk_rcg2_ops, 906 }; 907 908 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 909 .cmd_rcgr = 0x1e3b8, 910 .mnd_width = 16, 911 .hid_width = 5, 912 .parent_map = gcc_parent_map_0, 913 .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 914 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 915 }; 916 917 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 918 .name = "gcc_qupv3_wrap2_s4_clk_src", 919 .parent_data = gcc_parent_data_0, 920 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 921 .flags = CLK_SET_RATE_PARENT, 922 .ops = &clk_rcg2_ops, 923 }; 924 925 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 926 .cmd_rcgr = 0x1e4f0, 927 .mnd_width = 16, 928 .hid_width = 5, 929 .parent_map = gcc_parent_map_0, 930 .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 931 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 932 }; 933 934 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 935 .name = "gcc_qupv3_wrap2_s5_clk_src", 936 .parent_data = gcc_parent_data_0, 937 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 938 .flags = CLK_SET_RATE_PARENT, 939 .ops = &clk_rcg2_ops, 940 }; 941 942 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 943 .cmd_rcgr = 0x1e628, 944 .mnd_width = 16, 945 .hid_width = 5, 946 .parent_map = gcc_parent_map_0, 947 .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 948 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 949 }; 950 951 static const struct freq_tbl ftbl_gcc_qupv3_wrap2_s6_clk_src[] = { 952 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 953 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 954 F(19200000, P_BI_TCXO, 1, 0, 0), 955 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 956 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 957 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 958 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 959 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 960 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 961 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 962 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 963 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 964 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 965 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 966 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 967 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 968 F(125000000, P_GCC_GPLL0_OUT_MAIN, 1, 5, 24), 969 { } 970 }; 971 972 static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { 973 .name = "gcc_qupv3_wrap2_s6_clk_src", 974 .parent_data = gcc_parent_data_8, 975 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 976 .flags = CLK_SET_RATE_PARENT, 977 .ops = &clk_rcg2_ops, 978 }; 979 980 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { 981 .cmd_rcgr = 0x1e760, 982 .mnd_width = 16, 983 .hid_width = 5, 984 .parent_map = gcc_parent_map_8, 985 .freq_tbl = ftbl_gcc_qupv3_wrap2_s6_clk_src, 986 .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init, 987 }; 988 989 static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = { 990 .name = "gcc_qupv3_wrap2_s7_clk_src", 991 .parent_data = gcc_parent_data_0, 992 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 993 .flags = CLK_SET_RATE_PARENT, 994 .ops = &clk_rcg2_ops, 995 }; 996 997 static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = { 998 .cmd_rcgr = 0x1e898, 999 .mnd_width = 16, 1000 .hid_width = 5, 1001 .parent_map = gcc_parent_map_0, 1002 .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 1003 .clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init, 1004 }; 1005 1006 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1007 F(400000, P_BI_TCXO, 12, 1, 4), 1008 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1009 F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0), 1010 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 1011 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1012 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 1013 { } 1014 }; 1015 1016 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1017 .cmd_rcgr = 0x14018, 1018 .mnd_width = 8, 1019 .hid_width = 5, 1020 .parent_map = gcc_parent_map_9, 1021 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1022 .clkr.hw.init = &(struct clk_init_data){ 1023 .name = "gcc_sdcc2_apps_clk_src", 1024 .parent_data = gcc_parent_data_9, 1025 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 1026 .flags = CLK_SET_RATE_PARENT, 1027 .ops = &clk_rcg2_ops, 1028 }, 1029 }; 1030 1031 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 1032 F(400000, P_BI_TCXO, 12, 1, 4), 1033 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1034 F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0), 1035 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1036 { } 1037 }; 1038 1039 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 1040 .cmd_rcgr = 0x16018, 1041 .mnd_width = 8, 1042 .hid_width = 5, 1043 .parent_map = gcc_parent_map_0, 1044 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 1045 .clkr.hw.init = &(struct clk_init_data){ 1046 .name = "gcc_sdcc4_apps_clk_src", 1047 .parent_data = gcc_parent_data_0, 1048 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1049 .flags = CLK_SET_RATE_PARENT, 1050 .ops = &clk_rcg2_ops, 1051 }, 1052 }; 1053 1054 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1055 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1056 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1057 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 1058 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 1059 { } 1060 }; 1061 1062 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1063 .cmd_rcgr = 0x77030, 1064 .mnd_width = 8, 1065 .hid_width = 5, 1066 .parent_map = gcc_parent_map_0, 1067 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1068 .clkr.hw.init = &(struct clk_init_data){ 1069 .name = "gcc_ufs_phy_axi_clk_src", 1070 .parent_data = gcc_parent_data_0, 1071 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1072 .flags = CLK_SET_RATE_PARENT, 1073 .ops = &clk_rcg2_ops, 1074 }, 1075 }; 1076 1077 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1078 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1079 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 1080 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1081 { } 1082 }; 1083 1084 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1085 .cmd_rcgr = 0x77080, 1086 .mnd_width = 0, 1087 .hid_width = 5, 1088 .parent_map = gcc_parent_map_3, 1089 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1090 .clkr.hw.init = &(struct clk_init_data){ 1091 .name = "gcc_ufs_phy_ice_core_clk_src", 1092 .parent_data = gcc_parent_data_3, 1093 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1094 .flags = CLK_SET_RATE_PARENT, 1095 .ops = &clk_rcg2_ops, 1096 }, 1097 }; 1098 1099 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1100 F(9600000, P_BI_TCXO, 2, 0, 0), 1101 F(19200000, P_BI_TCXO, 1, 0, 0), 1102 { } 1103 }; 1104 1105 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1106 .cmd_rcgr = 0x770b4, 1107 .mnd_width = 0, 1108 .hid_width = 5, 1109 .parent_map = gcc_parent_map_4, 1110 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1111 .clkr.hw.init = &(struct clk_init_data){ 1112 .name = "gcc_ufs_phy_phy_aux_clk_src", 1113 .parent_data = gcc_parent_data_4, 1114 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1115 .flags = CLK_SET_RATE_PARENT, 1116 .ops = &clk_rcg2_ops, 1117 }, 1118 }; 1119 1120 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 1121 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1122 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 1123 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 1124 { } 1125 }; 1126 1127 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1128 .cmd_rcgr = 0x77098, 1129 .mnd_width = 0, 1130 .hid_width = 5, 1131 .parent_map = gcc_parent_map_0, 1132 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 1133 .clkr.hw.init = &(struct clk_init_data){ 1134 .name = "gcc_ufs_phy_unipro_core_clk_src", 1135 .parent_data = gcc_parent_data_0, 1136 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1137 .flags = CLK_SET_RATE_PARENT, 1138 .ops = &clk_rcg2_ops, 1139 }, 1140 }; 1141 1142 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1143 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 1144 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1145 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1146 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1147 { } 1148 }; 1149 1150 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1151 .cmd_rcgr = 0x3902c, 1152 .mnd_width = 8, 1153 .hid_width = 5, 1154 .parent_map = gcc_parent_map_0, 1155 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1156 .clkr.hw.init = &(struct clk_init_data){ 1157 .name = "gcc_usb30_prim_master_clk_src", 1158 .parent_data = gcc_parent_data_0, 1159 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1160 .flags = CLK_SET_RATE_PARENT, 1161 .ops = &clk_rcg2_ops, 1162 }, 1163 }; 1164 1165 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1166 .cmd_rcgr = 0x39044, 1167 .mnd_width = 0, 1168 .hid_width = 5, 1169 .parent_map = gcc_parent_map_0, 1170 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1171 .clkr.hw.init = &(struct clk_init_data){ 1172 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1173 .parent_data = gcc_parent_data_0, 1174 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1175 .flags = CLK_SET_RATE_PARENT, 1176 .ops = &clk_rcg2_ops, 1177 }, 1178 }; 1179 1180 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1181 .cmd_rcgr = 0x39070, 1182 .mnd_width = 0, 1183 .hid_width = 5, 1184 .parent_map = gcc_parent_map_2, 1185 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1186 .clkr.hw.init = &(struct clk_init_data){ 1187 .name = "gcc_usb3_prim_phy_aux_clk_src", 1188 .parent_data = gcc_parent_data_2, 1189 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1190 .flags = CLK_SET_RATE_PARENT, 1191 .ops = &clk_rcg2_ops, 1192 }, 1193 }; 1194 1195 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1196 .reg = 0x3905c, 1197 .shift = 0, 1198 .width = 4, 1199 .clkr.hw.init = &(struct clk_init_data) { 1200 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1201 .parent_hws = (const struct clk_hw*[]) { 1202 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1203 }, 1204 .num_parents = 1, 1205 .flags = CLK_SET_RATE_PARENT, 1206 .ops = &clk_regmap_div_ro_ops, 1207 }, 1208 }; 1209 1210 static struct clk_branch gcc_aggre_noc_pcie_axi_clk = { 1211 .halt_reg = 0x1003c, 1212 .halt_check = BRANCH_HALT_SKIP, 1213 .hwcg_reg = 0x1003c, 1214 .hwcg_bit = 1, 1215 .clkr = { 1216 .enable_reg = 0x52000, 1217 .enable_mask = BIT(12), 1218 .hw.init = &(struct clk_init_data){ 1219 .name = "gcc_aggre_noc_pcie_axi_clk", 1220 .ops = &clk_branch2_ops, 1221 }, 1222 }, 1223 }; 1224 1225 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1226 .halt_reg = 0x770e4, 1227 .halt_check = BRANCH_HALT_VOTED, 1228 .hwcg_reg = 0x770e4, 1229 .hwcg_bit = 1, 1230 .clkr = { 1231 .enable_reg = 0x770e4, 1232 .enable_mask = BIT(0), 1233 .hw.init = &(struct clk_init_data){ 1234 .name = "gcc_aggre_ufs_phy_axi_clk", 1235 .parent_hws = (const struct clk_hw*[]) { 1236 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1237 }, 1238 .num_parents = 1, 1239 .flags = CLK_SET_RATE_PARENT, 1240 .ops = &clk_branch2_ops, 1241 }, 1242 }, 1243 }; 1244 1245 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { 1246 .halt_reg = 0x770e4, 1247 .halt_check = BRANCH_HALT_VOTED, 1248 .hwcg_reg = 0x770e4, 1249 .hwcg_bit = 1, 1250 .clkr = { 1251 .enable_reg = 0x770e4, 1252 .enable_mask = BIT(1), 1253 .hw.init = &(struct clk_init_data){ 1254 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", 1255 .parent_hws = (const struct clk_hw*[]) { 1256 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1257 }, 1258 .num_parents = 1, 1259 .flags = CLK_SET_RATE_PARENT, 1260 .ops = &clk_branch2_ops, 1261 }, 1262 }, 1263 }; 1264 1265 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1266 .halt_reg = 0x3908c, 1267 .halt_check = BRANCH_HALT_VOTED, 1268 .hwcg_reg = 0x3908c, 1269 .hwcg_bit = 1, 1270 .clkr = { 1271 .enable_reg = 0x3908c, 1272 .enable_mask = BIT(0), 1273 .hw.init = &(struct clk_init_data){ 1274 .name = "gcc_aggre_usb3_prim_axi_clk", 1275 .parent_hws = (const struct clk_hw*[]) { 1276 &gcc_usb30_prim_master_clk_src.clkr.hw, 1277 }, 1278 .num_parents = 1, 1279 .flags = CLK_SET_RATE_PARENT, 1280 .ops = &clk_branch2_ops, 1281 }, 1282 }, 1283 }; 1284 1285 static struct clk_branch gcc_boot_rom_ahb_clk = { 1286 .halt_reg = 0x38004, 1287 .halt_check = BRANCH_HALT_VOTED, 1288 .hwcg_reg = 0x38004, 1289 .hwcg_bit = 1, 1290 .clkr = { 1291 .enable_reg = 0x52000, 1292 .enable_mask = BIT(10), 1293 .hw.init = &(struct clk_init_data){ 1294 .name = "gcc_boot_rom_ahb_clk", 1295 .ops = &clk_branch2_ops, 1296 }, 1297 }, 1298 }; 1299 1300 static struct clk_branch gcc_camera_hf_axi_clk = { 1301 .halt_reg = 0x26010, 1302 .halt_check = BRANCH_HALT_SKIP, 1303 .hwcg_reg = 0x26010, 1304 .hwcg_bit = 1, 1305 .clkr = { 1306 .enable_reg = 0x26010, 1307 .enable_mask = BIT(0), 1308 .hw.init = &(struct clk_init_data){ 1309 .name = "gcc_camera_hf_axi_clk", 1310 .ops = &clk_branch2_ops, 1311 }, 1312 }, 1313 }; 1314 1315 static struct clk_branch gcc_camera_sf_axi_clk = { 1316 .halt_reg = 0x2601c, 1317 .halt_check = BRANCH_HALT_SKIP, 1318 .hwcg_reg = 0x2601c, 1319 .hwcg_bit = 1, 1320 .clkr = { 1321 .enable_reg = 0x2601c, 1322 .enable_mask = BIT(0), 1323 .hw.init = &(struct clk_init_data){ 1324 .name = "gcc_camera_sf_axi_clk", 1325 .ops = &clk_branch2_ops, 1326 }, 1327 }, 1328 }; 1329 1330 static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = { 1331 .halt_reg = 0x10028, 1332 .halt_check = BRANCH_HALT_SKIP, 1333 .hwcg_reg = 0x10028, 1334 .hwcg_bit = 1, 1335 .clkr = { 1336 .enable_reg = 0x52000, 1337 .enable_mask = BIT(20), 1338 .hw.init = &(struct clk_init_data){ 1339 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk", 1340 .ops = &clk_branch2_ops, 1341 }, 1342 }, 1343 }; 1344 1345 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1346 .halt_reg = 0x39088, 1347 .halt_check = BRANCH_HALT_VOTED, 1348 .hwcg_reg = 0x39088, 1349 .hwcg_bit = 1, 1350 .clkr = { 1351 .enable_reg = 0x39088, 1352 .enable_mask = BIT(0), 1353 .hw.init = &(struct clk_init_data){ 1354 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1355 .parent_hws = (const struct clk_hw*[]) { 1356 &gcc_usb30_prim_master_clk_src.clkr.hw, 1357 }, 1358 .num_parents = 1, 1359 .flags = CLK_SET_RATE_PARENT, 1360 .ops = &clk_branch2_ops, 1361 }, 1362 }, 1363 }; 1364 1365 static struct clk_branch gcc_cnoc_pcie_sf_axi_clk = { 1366 .halt_reg = 0x10030, 1367 .halt_check = BRANCH_HALT_VOTED, 1368 .hwcg_reg = 0x10030, 1369 .hwcg_bit = 1, 1370 .clkr = { 1371 .enable_reg = 0x52008, 1372 .enable_mask = BIT(6), 1373 .hw.init = &(struct clk_init_data){ 1374 .name = "gcc_cnoc_pcie_sf_axi_clk", 1375 .ops = &clk_branch2_ops, 1376 }, 1377 }, 1378 }; 1379 1380 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1381 .halt_reg = 0x71154, 1382 .halt_check = BRANCH_HALT_SKIP, 1383 .hwcg_reg = 0x71154, 1384 .hwcg_bit = 1, 1385 .clkr = { 1386 .enable_reg = 0x71154, 1387 .enable_mask = BIT(0), 1388 .hw.init = &(struct clk_init_data){ 1389 .name = "gcc_ddrss_gpu_axi_clk", 1390 .ops = &clk_branch2_aon_ops, 1391 }, 1392 }, 1393 }; 1394 1395 static struct clk_branch gcc_ddrss_pcie_sf_qtb_clk = { 1396 .halt_reg = 0x1004c, 1397 .halt_check = BRANCH_HALT_SKIP, 1398 .hwcg_reg = 0x1004c, 1399 .hwcg_bit = 1, 1400 .clkr = { 1401 .enable_reg = 0x52000, 1402 .enable_mask = BIT(19), 1403 .hw.init = &(struct clk_init_data){ 1404 .name = "gcc_ddrss_pcie_sf_qtb_clk", 1405 .ops = &clk_branch2_ops, 1406 }, 1407 }, 1408 }; 1409 1410 static struct clk_branch gcc_disp_hf_axi_clk = { 1411 .halt_reg = 0x2700c, 1412 .halt_check = BRANCH_HALT_SKIP, 1413 .hwcg_reg = 0x2700c, 1414 .hwcg_bit = 1, 1415 .clkr = { 1416 .enable_reg = 0x2700c, 1417 .enable_mask = BIT(0), 1418 .hw.init = &(struct clk_init_data){ 1419 .name = "gcc_disp_hf_axi_clk", 1420 .ops = &clk_branch2_ops, 1421 }, 1422 }, 1423 }; 1424 1425 static struct clk_branch gcc_gp1_clk = { 1426 .halt_reg = 0x64000, 1427 .halt_check = BRANCH_HALT, 1428 .clkr = { 1429 .enable_reg = 0x64000, 1430 .enable_mask = BIT(0), 1431 .hw.init = &(struct clk_init_data){ 1432 .name = "gcc_gp1_clk", 1433 .parent_hws = (const struct clk_hw*[]) { 1434 &gcc_gp1_clk_src.clkr.hw, 1435 }, 1436 .num_parents = 1, 1437 .flags = CLK_SET_RATE_PARENT, 1438 .ops = &clk_branch2_ops, 1439 }, 1440 }, 1441 }; 1442 1443 static struct clk_branch gcc_gp2_clk = { 1444 .halt_reg = 0x65000, 1445 .halt_check = BRANCH_HALT, 1446 .clkr = { 1447 .enable_reg = 0x65000, 1448 .enable_mask = BIT(0), 1449 .hw.init = &(struct clk_init_data){ 1450 .name = "gcc_gp2_clk", 1451 .parent_hws = (const struct clk_hw*[]) { 1452 &gcc_gp2_clk_src.clkr.hw, 1453 }, 1454 .num_parents = 1, 1455 .flags = CLK_SET_RATE_PARENT, 1456 .ops = &clk_branch2_ops, 1457 }, 1458 }, 1459 }; 1460 1461 static struct clk_branch gcc_gp3_clk = { 1462 .halt_reg = 0x66000, 1463 .halt_check = BRANCH_HALT, 1464 .clkr = { 1465 .enable_reg = 0x66000, 1466 .enable_mask = BIT(0), 1467 .hw.init = &(struct clk_init_data){ 1468 .name = "gcc_gp3_clk", 1469 .parent_hws = (const struct clk_hw*[]) { 1470 &gcc_gp3_clk_src.clkr.hw, 1471 }, 1472 .num_parents = 1, 1473 .flags = CLK_SET_RATE_PARENT, 1474 .ops = &clk_branch2_ops, 1475 }, 1476 }, 1477 }; 1478 1479 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1480 .halt_check = BRANCH_HALT_DELAY, 1481 .clkr = { 1482 .enable_reg = 0x52000, 1483 .enable_mask = BIT(15), 1484 .hw.init = &(struct clk_init_data){ 1485 .name = "gcc_gpu_gpll0_clk_src", 1486 .parent_hws = (const struct clk_hw*[]) { 1487 &gcc_gpll0.clkr.hw, 1488 }, 1489 .num_parents = 1, 1490 .flags = CLK_SET_RATE_PARENT, 1491 .ops = &clk_branch2_ops, 1492 }, 1493 }, 1494 }; 1495 1496 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1497 .halt_check = BRANCH_HALT_DELAY, 1498 .clkr = { 1499 .enable_reg = 0x52000, 1500 .enable_mask = BIT(16), 1501 .hw.init = &(struct clk_init_data){ 1502 .name = "gcc_gpu_gpll0_div_clk_src", 1503 .parent_hws = (const struct clk_hw*[]) { 1504 &gcc_gpll0_out_even.clkr.hw, 1505 }, 1506 .num_parents = 1, 1507 .flags = CLK_SET_RATE_PARENT, 1508 .ops = &clk_branch2_ops, 1509 }, 1510 }, 1511 }; 1512 1513 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1514 .halt_reg = 0x71010, 1515 .halt_check = BRANCH_HALT_VOTED, 1516 .hwcg_reg = 0x71010, 1517 .hwcg_bit = 1, 1518 .clkr = { 1519 .enable_reg = 0x71010, 1520 .enable_mask = BIT(0), 1521 .hw.init = &(struct clk_init_data){ 1522 .name = "gcc_gpu_memnoc_gfx_clk", 1523 .ops = &clk_branch2_ops, 1524 }, 1525 }, 1526 }; 1527 1528 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1529 .halt_reg = 0x71018, 1530 .halt_check = BRANCH_HALT_DELAY, 1531 .clkr = { 1532 .enable_reg = 0x71018, 1533 .enable_mask = BIT(0), 1534 .hw.init = &(struct clk_init_data){ 1535 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1536 .ops = &clk_branch2_ops, 1537 }, 1538 }, 1539 }; 1540 1541 static struct clk_branch gcc_pcie_0_aux_clk = { 1542 .halt_reg = 0x6b03c, 1543 .halt_check = BRANCH_HALT_VOTED, 1544 .clkr = { 1545 .enable_reg = 0x52008, 1546 .enable_mask = BIT(3), 1547 .hw.init = &(struct clk_init_data){ 1548 .name = "gcc_pcie_0_aux_clk", 1549 .parent_hws = (const struct clk_hw*[]) { 1550 &gcc_pcie_0_aux_clk_src.clkr.hw, 1551 }, 1552 .num_parents = 1, 1553 .flags = CLK_SET_RATE_PARENT, 1554 .ops = &clk_branch2_ops, 1555 }, 1556 }, 1557 }; 1558 1559 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1560 .halt_reg = 0x6b038, 1561 .halt_check = BRANCH_HALT_VOTED, 1562 .hwcg_reg = 0x6b038, 1563 .hwcg_bit = 1, 1564 .clkr = { 1565 .enable_reg = 0x52008, 1566 .enable_mask = BIT(2), 1567 .hw.init = &(struct clk_init_data){ 1568 .name = "gcc_pcie_0_cfg_ahb_clk", 1569 .ops = &clk_branch2_ops, 1570 }, 1571 }, 1572 }; 1573 1574 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1575 .halt_reg = 0x6b02c, 1576 .halt_check = BRANCH_HALT_SKIP, 1577 .hwcg_reg = 0x6b02c, 1578 .hwcg_bit = 1, 1579 .clkr = { 1580 .enable_reg = 0x52008, 1581 .enable_mask = BIT(1), 1582 .hw.init = &(struct clk_init_data){ 1583 .name = "gcc_pcie_0_mstr_axi_clk", 1584 .ops = &clk_branch2_ops, 1585 }, 1586 }, 1587 }; 1588 1589 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 1590 .halt_reg = 0x6b054, 1591 .halt_check = BRANCH_HALT_VOTED, 1592 .clkr = { 1593 .enable_reg = 0x52000, 1594 .enable_mask = BIT(22), 1595 .hw.init = &(struct clk_init_data){ 1596 .name = "gcc_pcie_0_phy_rchng_clk", 1597 .parent_hws = (const struct clk_hw*[]) { 1598 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1599 }, 1600 .num_parents = 1, 1601 .flags = CLK_SET_RATE_PARENT, 1602 .ops = &clk_branch2_ops, 1603 }, 1604 }, 1605 }; 1606 1607 static struct clk_branch gcc_pcie_0_pipe_clk = { 1608 .halt_reg = 0x6b048, 1609 .halt_check = BRANCH_HALT_SKIP, 1610 .clkr = { 1611 .enable_reg = 0x52008, 1612 .enable_mask = BIT(4), 1613 .hw.init = &(struct clk_init_data){ 1614 .name = "gcc_pcie_0_pipe_clk", 1615 .parent_hws = (const struct clk_hw*[]) { 1616 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1617 }, 1618 .num_parents = 1, 1619 .flags = CLK_SET_RATE_PARENT, 1620 .ops = &clk_branch2_ops, 1621 }, 1622 }, 1623 }; 1624 1625 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1626 .halt_reg = 0x6b020, 1627 .halt_check = BRANCH_HALT_VOTED, 1628 .hwcg_reg = 0x6b020, 1629 .hwcg_bit = 1, 1630 .clkr = { 1631 .enable_reg = 0x52008, 1632 .enable_mask = BIT(0), 1633 .hw.init = &(struct clk_init_data){ 1634 .name = "gcc_pcie_0_slv_axi_clk", 1635 .ops = &clk_branch2_ops, 1636 }, 1637 }, 1638 }; 1639 1640 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1641 .halt_reg = 0x6b01c, 1642 .halt_check = BRANCH_HALT_VOTED, 1643 .clkr = { 1644 .enable_reg = 0x52008, 1645 .enable_mask = BIT(5), 1646 .hw.init = &(struct clk_init_data){ 1647 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1648 .ops = &clk_branch2_ops, 1649 }, 1650 }, 1651 }; 1652 1653 static struct clk_branch gcc_pcie_1_aux_clk = { 1654 .halt_reg = 0x8d038, 1655 .halt_check = BRANCH_HALT_VOTED, 1656 .clkr = { 1657 .enable_reg = 0x52000, 1658 .enable_mask = BIT(29), 1659 .hw.init = &(struct clk_init_data){ 1660 .name = "gcc_pcie_1_aux_clk", 1661 .parent_hws = (const struct clk_hw*[]) { 1662 &gcc_pcie_1_aux_clk_src.clkr.hw, 1663 }, 1664 .num_parents = 1, 1665 .flags = CLK_SET_RATE_PARENT, 1666 .ops = &clk_branch2_ops, 1667 }, 1668 }, 1669 }; 1670 1671 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1672 .halt_reg = 0x8d034, 1673 .halt_check = BRANCH_HALT_VOTED, 1674 .hwcg_reg = 0x8d034, 1675 .hwcg_bit = 1, 1676 .clkr = { 1677 .enable_reg = 0x52000, 1678 .enable_mask = BIT(28), 1679 .hw.init = &(struct clk_init_data){ 1680 .name = "gcc_pcie_1_cfg_ahb_clk", 1681 .ops = &clk_branch2_ops, 1682 }, 1683 }, 1684 }; 1685 1686 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1687 .halt_reg = 0x8d028, 1688 .halt_check = BRANCH_HALT_SKIP, 1689 .hwcg_reg = 0x8d028, 1690 .hwcg_bit = 1, 1691 .clkr = { 1692 .enable_reg = 0x52000, 1693 .enable_mask = BIT(27), 1694 .hw.init = &(struct clk_init_data){ 1695 .name = "gcc_pcie_1_mstr_axi_clk", 1696 .ops = &clk_branch2_ops, 1697 }, 1698 }, 1699 }; 1700 1701 static struct clk_branch gcc_pcie_1_phy_aux_clk = { 1702 .halt_reg = 0x8d044, 1703 .halt_check = BRANCH_HALT_VOTED, 1704 .clkr = { 1705 .enable_reg = 0x52000, 1706 .enable_mask = BIT(24), 1707 .hw.init = &(struct clk_init_data){ 1708 .name = "gcc_pcie_1_phy_aux_clk", 1709 .parent_hws = (const struct clk_hw*[]) { 1710 &gcc_pcie_1_phy_aux_clk_src.clkr.hw, 1711 }, 1712 .num_parents = 1, 1713 .flags = CLK_SET_RATE_PARENT, 1714 .ops = &clk_branch2_ops, 1715 }, 1716 }, 1717 }; 1718 1719 static struct clk_branch gcc_pcie_1_phy_rchng_clk = { 1720 .halt_reg = 0x8d05c, 1721 .halt_check = BRANCH_HALT_VOTED, 1722 .clkr = { 1723 .enable_reg = 0x52000, 1724 .enable_mask = BIT(23), 1725 .hw.init = &(struct clk_init_data){ 1726 .name = "gcc_pcie_1_phy_rchng_clk", 1727 .parent_hws = (const struct clk_hw*[]) { 1728 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 1729 }, 1730 .num_parents = 1, 1731 .flags = CLK_SET_RATE_PARENT, 1732 .ops = &clk_branch2_ops, 1733 }, 1734 }, 1735 }; 1736 1737 static struct clk_branch gcc_pcie_1_pipe_clk = { 1738 .halt_reg = 0x8d050, 1739 .halt_check = BRANCH_HALT_SKIP, 1740 .clkr = { 1741 .enable_reg = 0x52000, 1742 .enable_mask = BIT(30), 1743 .hw.init = &(struct clk_init_data){ 1744 .name = "gcc_pcie_1_pipe_clk", 1745 .parent_hws = (const struct clk_hw*[]) { 1746 &gcc_pcie_1_pipe_clk_src.clkr.hw, 1747 }, 1748 .num_parents = 1, 1749 .flags = CLK_SET_RATE_PARENT, 1750 .ops = &clk_branch2_ops, 1751 }, 1752 }, 1753 }; 1754 1755 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1756 .halt_reg = 0x8d01c, 1757 .halt_check = BRANCH_HALT_VOTED, 1758 .hwcg_reg = 0x8d01c, 1759 .hwcg_bit = 1, 1760 .clkr = { 1761 .enable_reg = 0x52000, 1762 .enable_mask = BIT(26), 1763 .hw.init = &(struct clk_init_data){ 1764 .name = "gcc_pcie_1_slv_axi_clk", 1765 .ops = &clk_branch2_ops, 1766 }, 1767 }, 1768 }; 1769 1770 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 1771 .halt_reg = 0x8d018, 1772 .halt_check = BRANCH_HALT_VOTED, 1773 .clkr = { 1774 .enable_reg = 0x52000, 1775 .enable_mask = BIT(25), 1776 .hw.init = &(struct clk_init_data){ 1777 .name = "gcc_pcie_1_slv_q2a_axi_clk", 1778 .ops = &clk_branch2_ops, 1779 }, 1780 }, 1781 }; 1782 1783 static struct clk_branch gcc_pdm2_clk = { 1784 .halt_reg = 0x3300c, 1785 .halt_check = BRANCH_HALT, 1786 .clkr = { 1787 .enable_reg = 0x3300c, 1788 .enable_mask = BIT(0), 1789 .hw.init = &(struct clk_init_data){ 1790 .name = "gcc_pdm2_clk", 1791 .parent_hws = (const struct clk_hw*[]) { 1792 &gcc_pdm2_clk_src.clkr.hw, 1793 }, 1794 .num_parents = 1, 1795 .flags = CLK_SET_RATE_PARENT, 1796 .ops = &clk_branch2_ops, 1797 }, 1798 }, 1799 }; 1800 1801 static struct clk_branch gcc_pdm_ahb_clk = { 1802 .halt_reg = 0x33004, 1803 .halt_check = BRANCH_HALT_VOTED, 1804 .hwcg_reg = 0x33004, 1805 .hwcg_bit = 1, 1806 .clkr = { 1807 .enable_reg = 0x33004, 1808 .enable_mask = BIT(0), 1809 .hw.init = &(struct clk_init_data){ 1810 .name = "gcc_pdm_ahb_clk", 1811 .ops = &clk_branch2_ops, 1812 }, 1813 }, 1814 }; 1815 1816 static struct clk_branch gcc_pdm_xo4_clk = { 1817 .halt_reg = 0x33008, 1818 .halt_check = BRANCH_HALT, 1819 .clkr = { 1820 .enable_reg = 0x33008, 1821 .enable_mask = BIT(0), 1822 .hw.init = &(struct clk_init_data){ 1823 .name = "gcc_pdm_xo4_clk", 1824 .ops = &clk_branch2_ops, 1825 }, 1826 }, 1827 }; 1828 1829 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 1830 .halt_reg = 0x26008, 1831 .halt_check = BRANCH_HALT_VOTED, 1832 .hwcg_reg = 0x26008, 1833 .hwcg_bit = 1, 1834 .clkr = { 1835 .enable_reg = 0x26008, 1836 .enable_mask = BIT(0), 1837 .hw.init = &(struct clk_init_data){ 1838 .name = "gcc_qmip_camera_nrt_ahb_clk", 1839 .ops = &clk_branch2_ops, 1840 }, 1841 }, 1842 }; 1843 1844 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 1845 .halt_reg = 0x2600c, 1846 .halt_check = BRANCH_HALT_VOTED, 1847 .hwcg_reg = 0x2600c, 1848 .hwcg_bit = 1, 1849 .clkr = { 1850 .enable_reg = 0x2600c, 1851 .enable_mask = BIT(0), 1852 .hw.init = &(struct clk_init_data){ 1853 .name = "gcc_qmip_camera_rt_ahb_clk", 1854 .ops = &clk_branch2_ops, 1855 }, 1856 }, 1857 }; 1858 1859 static struct clk_branch gcc_qmip_disp_ahb_clk = { 1860 .halt_reg = 0x27008, 1861 .halt_check = BRANCH_HALT_VOTED, 1862 .hwcg_reg = 0x27008, 1863 .hwcg_bit = 1, 1864 .clkr = { 1865 .enable_reg = 0x27008, 1866 .enable_mask = BIT(0), 1867 .hw.init = &(struct clk_init_data){ 1868 .name = "gcc_qmip_disp_ahb_clk", 1869 .ops = &clk_branch2_ops, 1870 }, 1871 }, 1872 }; 1873 1874 static struct clk_branch gcc_qmip_gpu_ahb_clk = { 1875 .halt_reg = 0x71008, 1876 .halt_check = BRANCH_HALT_VOTED, 1877 .hwcg_reg = 0x71008, 1878 .hwcg_bit = 1, 1879 .clkr = { 1880 .enable_reg = 0x71008, 1881 .enable_mask = BIT(0), 1882 .hw.init = &(struct clk_init_data){ 1883 .name = "gcc_qmip_gpu_ahb_clk", 1884 .ops = &clk_branch2_ops, 1885 }, 1886 }, 1887 }; 1888 1889 static struct clk_branch gcc_qmip_pcie_ahb_clk = { 1890 .halt_reg = 0x6b018, 1891 .halt_check = BRANCH_HALT_VOTED, 1892 .hwcg_reg = 0x6b018, 1893 .hwcg_bit = 1, 1894 .clkr = { 1895 .enable_reg = 0x52000, 1896 .enable_mask = BIT(11), 1897 .hw.init = &(struct clk_init_data){ 1898 .name = "gcc_qmip_pcie_ahb_clk", 1899 .ops = &clk_branch2_ops, 1900 }, 1901 }, 1902 }; 1903 1904 static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = { 1905 .halt_reg = 0x32014, 1906 .halt_check = BRANCH_HALT_VOTED, 1907 .hwcg_reg = 0x32014, 1908 .hwcg_bit = 1, 1909 .clkr = { 1910 .enable_reg = 0x32014, 1911 .enable_mask = BIT(0), 1912 .hw.init = &(struct clk_init_data){ 1913 .name = "gcc_qmip_video_cv_cpu_ahb_clk", 1914 .ops = &clk_branch2_ops, 1915 }, 1916 }, 1917 }; 1918 1919 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 1920 .halt_reg = 0x32008, 1921 .halt_check = BRANCH_HALT_VOTED, 1922 .hwcg_reg = 0x32008, 1923 .hwcg_bit = 1, 1924 .clkr = { 1925 .enable_reg = 0x32008, 1926 .enable_mask = BIT(0), 1927 .hw.init = &(struct clk_init_data){ 1928 .name = "gcc_qmip_video_cvp_ahb_clk", 1929 .ops = &clk_branch2_ops, 1930 }, 1931 }, 1932 }; 1933 1934 static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = { 1935 .halt_reg = 0x32010, 1936 .halt_check = BRANCH_HALT_VOTED, 1937 .hwcg_reg = 0x32010, 1938 .hwcg_bit = 1, 1939 .clkr = { 1940 .enable_reg = 0x32010, 1941 .enable_mask = BIT(0), 1942 .hw.init = &(struct clk_init_data){ 1943 .name = "gcc_qmip_video_v_cpu_ahb_clk", 1944 .ops = &clk_branch2_ops, 1945 }, 1946 }, 1947 }; 1948 1949 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 1950 .halt_reg = 0x3200c, 1951 .halt_check = BRANCH_HALT_VOTED, 1952 .hwcg_reg = 0x3200c, 1953 .hwcg_bit = 1, 1954 .clkr = { 1955 .enable_reg = 0x3200c, 1956 .enable_mask = BIT(0), 1957 .hw.init = &(struct clk_init_data){ 1958 .name = "gcc_qmip_video_vcodec_ahb_clk", 1959 .ops = &clk_branch2_ops, 1960 }, 1961 }, 1962 }; 1963 1964 static struct clk_branch gcc_qupv3_i2c_core_clk = { 1965 .halt_reg = 0x23144, 1966 .halt_check = BRANCH_HALT_VOTED, 1967 .clkr = { 1968 .enable_reg = 0x52008, 1969 .enable_mask = BIT(8), 1970 .hw.init = &(struct clk_init_data){ 1971 .name = "gcc_qupv3_i2c_core_clk", 1972 .ops = &clk_branch2_ops, 1973 }, 1974 }, 1975 }; 1976 1977 static struct clk_branch gcc_qupv3_i2c_s0_clk = { 1978 .halt_reg = 0x17004, 1979 .halt_check = BRANCH_HALT_VOTED, 1980 .clkr = { 1981 .enable_reg = 0x52008, 1982 .enable_mask = BIT(10), 1983 .hw.init = &(struct clk_init_data){ 1984 .name = "gcc_qupv3_i2c_s0_clk", 1985 .parent_hws = (const struct clk_hw*[]) { 1986 &gcc_qupv3_i2c_s0_clk_src.clkr.hw, 1987 }, 1988 .num_parents = 1, 1989 .flags = CLK_SET_RATE_PARENT, 1990 .ops = &clk_branch2_ops, 1991 }, 1992 }, 1993 }; 1994 1995 static struct clk_branch gcc_qupv3_i2c_s1_clk = { 1996 .halt_reg = 0x17020, 1997 .halt_check = BRANCH_HALT_VOTED, 1998 .clkr = { 1999 .enable_reg = 0x52008, 2000 .enable_mask = BIT(11), 2001 .hw.init = &(struct clk_init_data){ 2002 .name = "gcc_qupv3_i2c_s1_clk", 2003 .parent_hws = (const struct clk_hw*[]) { 2004 &gcc_qupv3_i2c_s1_clk_src.clkr.hw, 2005 }, 2006 .num_parents = 1, 2007 .flags = CLK_SET_RATE_PARENT, 2008 .ops = &clk_branch2_ops, 2009 }, 2010 }, 2011 }; 2012 2013 static struct clk_branch gcc_qupv3_i2c_s2_clk = { 2014 .halt_reg = 0x1703c, 2015 .halt_check = BRANCH_HALT_VOTED, 2016 .clkr = { 2017 .enable_reg = 0x52008, 2018 .enable_mask = BIT(12), 2019 .hw.init = &(struct clk_init_data){ 2020 .name = "gcc_qupv3_i2c_s2_clk", 2021 .parent_hws = (const struct clk_hw*[]) { 2022 &gcc_qupv3_i2c_s2_clk_src.clkr.hw, 2023 }, 2024 .num_parents = 1, 2025 .flags = CLK_SET_RATE_PARENT, 2026 .ops = &clk_branch2_ops, 2027 }, 2028 }, 2029 }; 2030 2031 static struct clk_branch gcc_qupv3_i2c_s3_clk = { 2032 .halt_reg = 0x17058, 2033 .halt_check = BRANCH_HALT_VOTED, 2034 .clkr = { 2035 .enable_reg = 0x52008, 2036 .enable_mask = BIT(13), 2037 .hw.init = &(struct clk_init_data){ 2038 .name = "gcc_qupv3_i2c_s3_clk", 2039 .parent_hws = (const struct clk_hw*[]) { 2040 &gcc_qupv3_i2c_s3_clk_src.clkr.hw, 2041 }, 2042 .num_parents = 1, 2043 .flags = CLK_SET_RATE_PARENT, 2044 .ops = &clk_branch2_ops, 2045 }, 2046 }, 2047 }; 2048 2049 static struct clk_branch gcc_qupv3_i2c_s4_clk = { 2050 .halt_reg = 0x17074, 2051 .halt_check = BRANCH_HALT_VOTED, 2052 .clkr = { 2053 .enable_reg = 0x52008, 2054 .enable_mask = BIT(14), 2055 .hw.init = &(struct clk_init_data){ 2056 .name = "gcc_qupv3_i2c_s4_clk", 2057 .parent_hws = (const struct clk_hw*[]) { 2058 &gcc_qupv3_i2c_s4_clk_src.clkr.hw, 2059 }, 2060 .num_parents = 1, 2061 .flags = CLK_SET_RATE_PARENT, 2062 .ops = &clk_branch2_ops, 2063 }, 2064 }, 2065 }; 2066 2067 static struct clk_branch gcc_qupv3_i2c_s5_clk = { 2068 .halt_reg = 0x17090, 2069 .halt_check = BRANCH_HALT_VOTED, 2070 .clkr = { 2071 .enable_reg = 0x52008, 2072 .enable_mask = BIT(15), 2073 .hw.init = &(struct clk_init_data){ 2074 .name = "gcc_qupv3_i2c_s5_clk", 2075 .parent_hws = (const struct clk_hw*[]) { 2076 &gcc_qupv3_i2c_s5_clk_src.clkr.hw, 2077 }, 2078 .num_parents = 1, 2079 .flags = CLK_SET_RATE_PARENT, 2080 .ops = &clk_branch2_ops, 2081 }, 2082 }, 2083 }; 2084 2085 static struct clk_branch gcc_qupv3_i2c_s6_clk = { 2086 .halt_reg = 0x170ac, 2087 .halt_check = BRANCH_HALT_VOTED, 2088 .clkr = { 2089 .enable_reg = 0x52008, 2090 .enable_mask = BIT(16), 2091 .hw.init = &(struct clk_init_data){ 2092 .name = "gcc_qupv3_i2c_s6_clk", 2093 .parent_hws = (const struct clk_hw*[]) { 2094 &gcc_qupv3_i2c_s6_clk_src.clkr.hw, 2095 }, 2096 .num_parents = 1, 2097 .flags = CLK_SET_RATE_PARENT, 2098 .ops = &clk_branch2_ops, 2099 }, 2100 }, 2101 }; 2102 2103 static struct clk_branch gcc_qupv3_i2c_s7_clk = { 2104 .halt_reg = 0x170c8, 2105 .halt_check = BRANCH_HALT_VOTED, 2106 .clkr = { 2107 .enable_reg = 0x52008, 2108 .enable_mask = BIT(17), 2109 .hw.init = &(struct clk_init_data){ 2110 .name = "gcc_qupv3_i2c_s7_clk", 2111 .parent_hws = (const struct clk_hw*[]) { 2112 &gcc_qupv3_i2c_s7_clk_src.clkr.hw, 2113 }, 2114 .num_parents = 1, 2115 .flags = CLK_SET_RATE_PARENT, 2116 .ops = &clk_branch2_ops, 2117 }, 2118 }, 2119 }; 2120 2121 static struct clk_branch gcc_qupv3_i2c_s8_clk = { 2122 .halt_reg = 0x170e4, 2123 .halt_check = BRANCH_HALT_VOTED, 2124 .clkr = { 2125 .enable_reg = 0x52010, 2126 .enable_mask = BIT(14), 2127 .hw.init = &(struct clk_init_data){ 2128 .name = "gcc_qupv3_i2c_s8_clk", 2129 .parent_hws = (const struct clk_hw*[]) { 2130 &gcc_qupv3_i2c_s8_clk_src.clkr.hw, 2131 }, 2132 .num_parents = 1, 2133 .flags = CLK_SET_RATE_PARENT, 2134 .ops = &clk_branch2_ops, 2135 }, 2136 }, 2137 }; 2138 2139 static struct clk_branch gcc_qupv3_i2c_s9_clk = { 2140 .halt_reg = 0x17100, 2141 .halt_check = BRANCH_HALT_VOTED, 2142 .clkr = { 2143 .enable_reg = 0x52010, 2144 .enable_mask = BIT(15), 2145 .hw.init = &(struct clk_init_data){ 2146 .name = "gcc_qupv3_i2c_s9_clk", 2147 .parent_hws = (const struct clk_hw*[]) { 2148 &gcc_qupv3_i2c_s9_clk_src.clkr.hw, 2149 }, 2150 .num_parents = 1, 2151 .flags = CLK_SET_RATE_PARENT, 2152 .ops = &clk_branch2_ops, 2153 }, 2154 }, 2155 }; 2156 2157 static struct clk_branch gcc_qupv3_i2c_s_ahb_clk = { 2158 .halt_reg = 0x23140, 2159 .halt_check = BRANCH_HALT_VOTED, 2160 .hwcg_reg = 0x23140, 2161 .hwcg_bit = 1, 2162 .clkr = { 2163 .enable_reg = 0x52008, 2164 .enable_mask = BIT(7), 2165 .hw.init = &(struct clk_init_data){ 2166 .name = "gcc_qupv3_i2c_s_ahb_clk", 2167 .ops = &clk_branch2_ops, 2168 }, 2169 }, 2170 }; 2171 2172 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2173 .halt_reg = 0x23294, 2174 .halt_check = BRANCH_HALT_VOTED, 2175 .clkr = { 2176 .enable_reg = 0x52008, 2177 .enable_mask = BIT(18), 2178 .hw.init = &(struct clk_init_data){ 2179 .name = "gcc_qupv3_wrap1_core_2x_clk", 2180 .ops = &clk_branch2_ops, 2181 }, 2182 }, 2183 }; 2184 2185 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2186 .halt_reg = 0x23284, 2187 .halt_check = BRANCH_HALT_VOTED, 2188 .clkr = { 2189 .enable_reg = 0x52008, 2190 .enable_mask = BIT(19), 2191 .hw.init = &(struct clk_init_data){ 2192 .name = "gcc_qupv3_wrap1_core_clk", 2193 .ops = &clk_branch2_ops, 2194 }, 2195 }, 2196 }; 2197 2198 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2199 .halt_reg = 0x18004, 2200 .halt_check = BRANCH_HALT_VOTED, 2201 .clkr = { 2202 .enable_reg = 0x52008, 2203 .enable_mask = BIT(22), 2204 .hw.init = &(struct clk_init_data){ 2205 .name = "gcc_qupv3_wrap1_s0_clk", 2206 .parent_hws = (const struct clk_hw*[]) { 2207 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2208 }, 2209 .num_parents = 1, 2210 .flags = CLK_SET_RATE_PARENT, 2211 .ops = &clk_branch2_ops, 2212 }, 2213 }, 2214 }; 2215 2216 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2217 .halt_reg = 0x1813c, 2218 .halt_check = BRANCH_HALT_VOTED, 2219 .clkr = { 2220 .enable_reg = 0x52008, 2221 .enable_mask = BIT(23), 2222 .hw.init = &(struct clk_init_data){ 2223 .name = "gcc_qupv3_wrap1_s1_clk", 2224 .parent_hws = (const struct clk_hw*[]) { 2225 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2226 }, 2227 .num_parents = 1, 2228 .flags = CLK_SET_RATE_PARENT, 2229 .ops = &clk_branch2_ops, 2230 }, 2231 }, 2232 }; 2233 2234 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2235 .halt_reg = 0x18274, 2236 .halt_check = BRANCH_HALT_VOTED, 2237 .clkr = { 2238 .enable_reg = 0x52008, 2239 .enable_mask = BIT(24), 2240 .hw.init = &(struct clk_init_data){ 2241 .name = "gcc_qupv3_wrap1_s2_clk", 2242 .parent_hws = (const struct clk_hw*[]) { 2243 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2244 }, 2245 .num_parents = 1, 2246 .flags = CLK_SET_RATE_PARENT, 2247 .ops = &clk_branch2_ops, 2248 }, 2249 }, 2250 }; 2251 2252 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2253 .halt_reg = 0x183ac, 2254 .halt_check = BRANCH_HALT_VOTED, 2255 .clkr = { 2256 .enable_reg = 0x52008, 2257 .enable_mask = BIT(25), 2258 .hw.init = &(struct clk_init_data){ 2259 .name = "gcc_qupv3_wrap1_s3_clk", 2260 .parent_hws = (const struct clk_hw*[]) { 2261 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2262 }, 2263 .num_parents = 1, 2264 .flags = CLK_SET_RATE_PARENT, 2265 .ops = &clk_branch2_ops, 2266 }, 2267 }, 2268 }; 2269 2270 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2271 .halt_reg = 0x184e4, 2272 .halt_check = BRANCH_HALT_VOTED, 2273 .clkr = { 2274 .enable_reg = 0x52008, 2275 .enable_mask = BIT(26), 2276 .hw.init = &(struct clk_init_data){ 2277 .name = "gcc_qupv3_wrap1_s4_clk", 2278 .parent_hws = (const struct clk_hw*[]) { 2279 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2280 }, 2281 .num_parents = 1, 2282 .flags = CLK_SET_RATE_PARENT, 2283 .ops = &clk_branch2_ops, 2284 }, 2285 }, 2286 }; 2287 2288 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2289 .halt_reg = 0x1861c, 2290 .halt_check = BRANCH_HALT_VOTED, 2291 .clkr = { 2292 .enable_reg = 0x52008, 2293 .enable_mask = BIT(27), 2294 .hw.init = &(struct clk_init_data){ 2295 .name = "gcc_qupv3_wrap1_s5_clk", 2296 .parent_hws = (const struct clk_hw*[]) { 2297 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2298 }, 2299 .num_parents = 1, 2300 .flags = CLK_SET_RATE_PARENT, 2301 .ops = &clk_branch2_ops, 2302 }, 2303 }, 2304 }; 2305 2306 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 2307 .halt_reg = 0x18754, 2308 .halt_check = BRANCH_HALT_VOTED, 2309 .clkr = { 2310 .enable_reg = 0x52008, 2311 .enable_mask = BIT(28), 2312 .hw.init = &(struct clk_init_data){ 2313 .name = "gcc_qupv3_wrap1_s6_clk", 2314 .parent_hws = (const struct clk_hw*[]) { 2315 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 2316 }, 2317 .num_parents = 1, 2318 .flags = CLK_SET_RATE_PARENT, 2319 .ops = &clk_branch2_ops, 2320 }, 2321 }, 2322 }; 2323 2324 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 2325 .halt_reg = 0x1888c, 2326 .halt_check = BRANCH_HALT_VOTED, 2327 .clkr = { 2328 .enable_reg = 0x52010, 2329 .enable_mask = BIT(16), 2330 .hw.init = &(struct clk_init_data){ 2331 .name = "gcc_qupv3_wrap1_s7_clk", 2332 .parent_hws = (const struct clk_hw*[]) { 2333 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 2334 }, 2335 .num_parents = 1, 2336 .flags = CLK_SET_RATE_PARENT, 2337 .ops = &clk_branch2_ops, 2338 }, 2339 }, 2340 }; 2341 2342 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 2343 .halt_reg = 0x23004, 2344 .halt_check = BRANCH_HALT_VOTED, 2345 .clkr = { 2346 .enable_reg = 0x52010, 2347 .enable_mask = BIT(3), 2348 .hw.init = &(struct clk_init_data){ 2349 .name = "gcc_qupv3_wrap2_core_2x_clk", 2350 .ops = &clk_branch2_ops, 2351 }, 2352 }, 2353 }; 2354 2355 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 2356 .halt_reg = 0x233d4, 2357 .halt_check = BRANCH_HALT_VOTED, 2358 .clkr = { 2359 .enable_reg = 0x52010, 2360 .enable_mask = BIT(0), 2361 .hw.init = &(struct clk_init_data){ 2362 .name = "gcc_qupv3_wrap2_core_clk", 2363 .ops = &clk_branch2_ops, 2364 }, 2365 }, 2366 }; 2367 2368 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 2369 .halt_reg = 0x1e004, 2370 .halt_check = BRANCH_HALT_VOTED, 2371 .clkr = { 2372 .enable_reg = 0x52010, 2373 .enable_mask = BIT(4), 2374 .hw.init = &(struct clk_init_data){ 2375 .name = "gcc_qupv3_wrap2_s0_clk", 2376 .parent_hws = (const struct clk_hw*[]) { 2377 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 2378 }, 2379 .num_parents = 1, 2380 .flags = CLK_SET_RATE_PARENT, 2381 .ops = &clk_branch2_ops, 2382 }, 2383 }, 2384 }; 2385 2386 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 2387 .halt_reg = 0x1e13c, 2388 .halt_check = BRANCH_HALT_VOTED, 2389 .clkr = { 2390 .enable_reg = 0x52010, 2391 .enable_mask = BIT(5), 2392 .hw.init = &(struct clk_init_data){ 2393 .name = "gcc_qupv3_wrap2_s1_clk", 2394 .parent_hws = (const struct clk_hw*[]) { 2395 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 2396 }, 2397 .num_parents = 1, 2398 .flags = CLK_SET_RATE_PARENT, 2399 .ops = &clk_branch2_ops, 2400 }, 2401 }, 2402 }; 2403 2404 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 2405 .halt_reg = 0x1e274, 2406 .halt_check = BRANCH_HALT_VOTED, 2407 .clkr = { 2408 .enable_reg = 0x52010, 2409 .enable_mask = BIT(6), 2410 .hw.init = &(struct clk_init_data){ 2411 .name = "gcc_qupv3_wrap2_s2_clk", 2412 .parent_hws = (const struct clk_hw*[]) { 2413 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 2414 }, 2415 .num_parents = 1, 2416 .flags = CLK_SET_RATE_PARENT, 2417 .ops = &clk_branch2_ops, 2418 }, 2419 }, 2420 }; 2421 2422 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 2423 .halt_reg = 0x1e3ac, 2424 .halt_check = BRANCH_HALT_VOTED, 2425 .clkr = { 2426 .enable_reg = 0x52010, 2427 .enable_mask = BIT(7), 2428 .hw.init = &(struct clk_init_data){ 2429 .name = "gcc_qupv3_wrap2_s3_clk", 2430 .parent_hws = (const struct clk_hw*[]) { 2431 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 2432 }, 2433 .num_parents = 1, 2434 .flags = CLK_SET_RATE_PARENT, 2435 .ops = &clk_branch2_ops, 2436 }, 2437 }, 2438 }; 2439 2440 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 2441 .halt_reg = 0x1e4e4, 2442 .halt_check = BRANCH_HALT_VOTED, 2443 .clkr = { 2444 .enable_reg = 0x52010, 2445 .enable_mask = BIT(8), 2446 .hw.init = &(struct clk_init_data){ 2447 .name = "gcc_qupv3_wrap2_s4_clk", 2448 .parent_hws = (const struct clk_hw*[]) { 2449 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 2450 }, 2451 .num_parents = 1, 2452 .flags = CLK_SET_RATE_PARENT, 2453 .ops = &clk_branch2_ops, 2454 }, 2455 }, 2456 }; 2457 2458 static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 2459 .halt_reg = 0x1e61c, 2460 .halt_check = BRANCH_HALT_VOTED, 2461 .clkr = { 2462 .enable_reg = 0x52010, 2463 .enable_mask = BIT(9), 2464 .hw.init = &(struct clk_init_data){ 2465 .name = "gcc_qupv3_wrap2_s5_clk", 2466 .parent_hws = (const struct clk_hw*[]) { 2467 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 2468 }, 2469 .num_parents = 1, 2470 .flags = CLK_SET_RATE_PARENT, 2471 .ops = &clk_branch2_ops, 2472 }, 2473 }, 2474 }; 2475 2476 static struct clk_branch gcc_qupv3_wrap2_s6_clk = { 2477 .halt_reg = 0x1e754, 2478 .halt_check = BRANCH_HALT_VOTED, 2479 .clkr = { 2480 .enable_reg = 0x52010, 2481 .enable_mask = BIT(10), 2482 .hw.init = &(struct clk_init_data){ 2483 .name = "gcc_qupv3_wrap2_s6_clk", 2484 .parent_hws = (const struct clk_hw*[]) { 2485 &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, 2486 }, 2487 .num_parents = 1, 2488 .flags = CLK_SET_RATE_PARENT, 2489 .ops = &clk_branch2_ops, 2490 }, 2491 }, 2492 }; 2493 2494 static struct clk_branch gcc_qupv3_wrap2_s7_clk = { 2495 .halt_reg = 0x1e88c, 2496 .halt_check = BRANCH_HALT_VOTED, 2497 .clkr = { 2498 .enable_reg = 0x52010, 2499 .enable_mask = BIT(17), 2500 .hw.init = &(struct clk_init_data){ 2501 .name = "gcc_qupv3_wrap2_s7_clk", 2502 .parent_hws = (const struct clk_hw*[]) { 2503 &gcc_qupv3_wrap2_s7_clk_src.clkr.hw, 2504 }, 2505 .num_parents = 1, 2506 .flags = CLK_SET_RATE_PARENT, 2507 .ops = &clk_branch2_ops, 2508 }, 2509 }, 2510 }; 2511 2512 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2513 .halt_reg = 0x2327c, 2514 .halt_check = BRANCH_HALT_VOTED, 2515 .hwcg_reg = 0x2327c, 2516 .hwcg_bit = 1, 2517 .clkr = { 2518 .enable_reg = 0x52008, 2519 .enable_mask = BIT(20), 2520 .hw.init = &(struct clk_init_data){ 2521 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2522 .ops = &clk_branch2_ops, 2523 }, 2524 }, 2525 }; 2526 2527 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2528 .halt_reg = 0x23280, 2529 .halt_check = BRANCH_HALT_VOTED, 2530 .hwcg_reg = 0x23280, 2531 .hwcg_bit = 1, 2532 .clkr = { 2533 .enable_reg = 0x52008, 2534 .enable_mask = BIT(21), 2535 .hw.init = &(struct clk_init_data){ 2536 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2537 .ops = &clk_branch2_ops, 2538 }, 2539 }, 2540 }; 2541 2542 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 2543 .halt_reg = 0x233cc, 2544 .halt_check = BRANCH_HALT_VOTED, 2545 .hwcg_reg = 0x233cc, 2546 .hwcg_bit = 1, 2547 .clkr = { 2548 .enable_reg = 0x52010, 2549 .enable_mask = BIT(2), 2550 .hw.init = &(struct clk_init_data){ 2551 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 2552 .ops = &clk_branch2_ops, 2553 }, 2554 }, 2555 }; 2556 2557 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 2558 .halt_reg = 0x233d0, 2559 .halt_check = BRANCH_HALT_VOTED, 2560 .hwcg_reg = 0x233d0, 2561 .hwcg_bit = 1, 2562 .clkr = { 2563 .enable_reg = 0x52010, 2564 .enable_mask = BIT(1), 2565 .hw.init = &(struct clk_init_data){ 2566 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 2567 .ops = &clk_branch2_ops, 2568 }, 2569 }, 2570 }; 2571 2572 static struct clk_branch gcc_sdcc2_ahb_clk = { 2573 .halt_reg = 0x14010, 2574 .halt_check = BRANCH_HALT, 2575 .clkr = { 2576 .enable_reg = 0x14010, 2577 .enable_mask = BIT(0), 2578 .hw.init = &(struct clk_init_data){ 2579 .name = "gcc_sdcc2_ahb_clk", 2580 .ops = &clk_branch2_ops, 2581 }, 2582 }, 2583 }; 2584 2585 static struct clk_branch gcc_sdcc2_apps_clk = { 2586 .halt_reg = 0x14004, 2587 .halt_check = BRANCH_HALT, 2588 .clkr = { 2589 .enable_reg = 0x14004, 2590 .enable_mask = BIT(0), 2591 .hw.init = &(struct clk_init_data){ 2592 .name = "gcc_sdcc2_apps_clk", 2593 .parent_hws = (const struct clk_hw*[]) { 2594 &gcc_sdcc2_apps_clk_src.clkr.hw, 2595 }, 2596 .num_parents = 1, 2597 .flags = CLK_SET_RATE_PARENT, 2598 .ops = &clk_branch2_ops, 2599 }, 2600 }, 2601 }; 2602 2603 static struct clk_branch gcc_sdcc4_ahb_clk = { 2604 .halt_reg = 0x16010, 2605 .halt_check = BRANCH_HALT, 2606 .clkr = { 2607 .enable_reg = 0x16010, 2608 .enable_mask = BIT(0), 2609 .hw.init = &(struct clk_init_data){ 2610 .name = "gcc_sdcc4_ahb_clk", 2611 .ops = &clk_branch2_ops, 2612 }, 2613 }, 2614 }; 2615 2616 static struct clk_branch gcc_sdcc4_apps_clk = { 2617 .halt_reg = 0x16004, 2618 .halt_check = BRANCH_HALT, 2619 .clkr = { 2620 .enable_reg = 0x16004, 2621 .enable_mask = BIT(0), 2622 .hw.init = &(struct clk_init_data){ 2623 .name = "gcc_sdcc4_apps_clk", 2624 .parent_hws = (const struct clk_hw*[]) { 2625 &gcc_sdcc4_apps_clk_src.clkr.hw, 2626 }, 2627 .num_parents = 1, 2628 .flags = CLK_SET_RATE_PARENT, 2629 .ops = &clk_branch2_ops, 2630 }, 2631 }, 2632 }; 2633 2634 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2635 .halt_reg = 0x77024, 2636 .halt_check = BRANCH_HALT_VOTED, 2637 .hwcg_reg = 0x77024, 2638 .hwcg_bit = 1, 2639 .clkr = { 2640 .enable_reg = 0x77024, 2641 .enable_mask = BIT(0), 2642 .hw.init = &(struct clk_init_data){ 2643 .name = "gcc_ufs_phy_ahb_clk", 2644 .ops = &clk_branch2_ops, 2645 }, 2646 }, 2647 }; 2648 2649 static struct clk_branch gcc_ufs_phy_axi_clk = { 2650 .halt_reg = 0x77018, 2651 .halt_check = BRANCH_HALT_VOTED, 2652 .hwcg_reg = 0x77018, 2653 .hwcg_bit = 1, 2654 .clkr = { 2655 .enable_reg = 0x77018, 2656 .enable_mask = BIT(0), 2657 .hw.init = &(struct clk_init_data){ 2658 .name = "gcc_ufs_phy_axi_clk", 2659 .parent_hws = (const struct clk_hw*[]) { 2660 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2661 }, 2662 .num_parents = 1, 2663 .flags = CLK_SET_RATE_PARENT, 2664 .ops = &clk_branch2_ops, 2665 }, 2666 }, 2667 }; 2668 2669 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { 2670 .halt_reg = 0x77018, 2671 .halt_check = BRANCH_HALT_VOTED, 2672 .hwcg_reg = 0x77018, 2673 .hwcg_bit = 1, 2674 .clkr = { 2675 .enable_reg = 0x77018, 2676 .enable_mask = BIT(1), 2677 .hw.init = &(struct clk_init_data){ 2678 .name = "gcc_ufs_phy_axi_hw_ctl_clk", 2679 .parent_hws = (const struct clk_hw*[]) { 2680 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2681 }, 2682 .num_parents = 1, 2683 .flags = CLK_SET_RATE_PARENT, 2684 .ops = &clk_branch2_ops, 2685 }, 2686 }, 2687 }; 2688 2689 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2690 .halt_reg = 0x77074, 2691 .halt_check = BRANCH_HALT_VOTED, 2692 .hwcg_reg = 0x77074, 2693 .hwcg_bit = 1, 2694 .clkr = { 2695 .enable_reg = 0x77074, 2696 .enable_mask = BIT(0), 2697 .hw.init = &(struct clk_init_data){ 2698 .name = "gcc_ufs_phy_ice_core_clk", 2699 .parent_hws = (const struct clk_hw*[]) { 2700 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2701 }, 2702 .num_parents = 1, 2703 .flags = CLK_SET_RATE_PARENT, 2704 .ops = &clk_branch2_ops, 2705 }, 2706 }, 2707 }; 2708 2709 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { 2710 .halt_reg = 0x77074, 2711 .halt_check = BRANCH_HALT_VOTED, 2712 .hwcg_reg = 0x77074, 2713 .hwcg_bit = 1, 2714 .clkr = { 2715 .enable_reg = 0x77074, 2716 .enable_mask = BIT(1), 2717 .hw.init = &(struct clk_init_data){ 2718 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", 2719 .parent_hws = (const struct clk_hw*[]) { 2720 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2721 }, 2722 .num_parents = 1, 2723 .flags = CLK_SET_RATE_PARENT, 2724 .ops = &clk_branch2_ops, 2725 }, 2726 }, 2727 }; 2728 2729 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2730 .halt_reg = 0x770b0, 2731 .halt_check = BRANCH_HALT_VOTED, 2732 .hwcg_reg = 0x770b0, 2733 .hwcg_bit = 1, 2734 .clkr = { 2735 .enable_reg = 0x770b0, 2736 .enable_mask = BIT(0), 2737 .hw.init = &(struct clk_init_data){ 2738 .name = "gcc_ufs_phy_phy_aux_clk", 2739 .parent_hws = (const struct clk_hw*[]) { 2740 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2741 }, 2742 .num_parents = 1, 2743 .flags = CLK_SET_RATE_PARENT, 2744 .ops = &clk_branch2_ops, 2745 }, 2746 }, 2747 }; 2748 2749 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { 2750 .halt_reg = 0x770b0, 2751 .halt_check = BRANCH_HALT_VOTED, 2752 .hwcg_reg = 0x770b0, 2753 .hwcg_bit = 1, 2754 .clkr = { 2755 .enable_reg = 0x770b0, 2756 .enable_mask = BIT(1), 2757 .hw.init = &(struct clk_init_data){ 2758 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", 2759 .parent_hws = (const struct clk_hw*[]) { 2760 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2761 }, 2762 .num_parents = 1, 2763 .flags = CLK_SET_RATE_PARENT, 2764 .ops = &clk_branch2_ops, 2765 }, 2766 }, 2767 }; 2768 2769 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2770 .halt_reg = 0x7702c, 2771 .halt_check = BRANCH_HALT_DELAY, 2772 .clkr = { 2773 .enable_reg = 0x7702c, 2774 .enable_mask = BIT(0), 2775 .hw.init = &(struct clk_init_data){ 2776 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2777 .parent_hws = (const struct clk_hw*[]) { 2778 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 2779 }, 2780 .num_parents = 1, 2781 .flags = CLK_SET_RATE_PARENT, 2782 .ops = &clk_branch2_ops, 2783 }, 2784 }, 2785 }; 2786 2787 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2788 .halt_reg = 0x770cc, 2789 .halt_check = BRANCH_HALT_DELAY, 2790 .clkr = { 2791 .enable_reg = 0x770cc, 2792 .enable_mask = BIT(0), 2793 .hw.init = &(struct clk_init_data){ 2794 .name = "gcc_ufs_phy_rx_symbol_1_clk", 2795 .parent_hws = (const struct clk_hw*[]) { 2796 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 2797 }, 2798 .num_parents = 1, 2799 .flags = CLK_SET_RATE_PARENT, 2800 .ops = &clk_branch2_ops, 2801 }, 2802 }, 2803 }; 2804 2805 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2806 .halt_reg = 0x77028, 2807 .halt_check = BRANCH_HALT_DELAY, 2808 .clkr = { 2809 .enable_reg = 0x77028, 2810 .enable_mask = BIT(0), 2811 .hw.init = &(struct clk_init_data){ 2812 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2813 .parent_hws = (const struct clk_hw*[]) { 2814 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 2815 }, 2816 .num_parents = 1, 2817 .flags = CLK_SET_RATE_PARENT, 2818 .ops = &clk_branch2_ops, 2819 }, 2820 }, 2821 }; 2822 2823 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2824 .halt_reg = 0x77068, 2825 .halt_check = BRANCH_HALT_VOTED, 2826 .hwcg_reg = 0x77068, 2827 .hwcg_bit = 1, 2828 .clkr = { 2829 .enable_reg = 0x77068, 2830 .enable_mask = BIT(0), 2831 .hw.init = &(struct clk_init_data){ 2832 .name = "gcc_ufs_phy_unipro_core_clk", 2833 .parent_hws = (const struct clk_hw*[]) { 2834 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2835 }, 2836 .num_parents = 1, 2837 .flags = CLK_SET_RATE_PARENT, 2838 .ops = &clk_branch2_ops, 2839 }, 2840 }, 2841 }; 2842 2843 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { 2844 .halt_reg = 0x77068, 2845 .halt_check = BRANCH_HALT_VOTED, 2846 .hwcg_reg = 0x77068, 2847 .hwcg_bit = 1, 2848 .clkr = { 2849 .enable_reg = 0x77068, 2850 .enable_mask = BIT(1), 2851 .hw.init = &(struct clk_init_data){ 2852 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", 2853 .parent_hws = (const struct clk_hw*[]) { 2854 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2855 }, 2856 .num_parents = 1, 2857 .flags = CLK_SET_RATE_PARENT, 2858 .ops = &clk_branch2_ops, 2859 }, 2860 }, 2861 }; 2862 2863 static struct clk_branch gcc_usb30_prim_master_clk = { 2864 .halt_reg = 0x39018, 2865 .halt_check = BRANCH_HALT, 2866 .clkr = { 2867 .enable_reg = 0x39018, 2868 .enable_mask = BIT(0), 2869 .hw.init = &(struct clk_init_data){ 2870 .name = "gcc_usb30_prim_master_clk", 2871 .parent_hws = (const struct clk_hw*[]) { 2872 &gcc_usb30_prim_master_clk_src.clkr.hw, 2873 }, 2874 .num_parents = 1, 2875 .flags = CLK_SET_RATE_PARENT, 2876 .ops = &clk_branch2_ops, 2877 }, 2878 }, 2879 }; 2880 2881 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2882 .halt_reg = 0x39028, 2883 .halt_check = BRANCH_HALT, 2884 .clkr = { 2885 .enable_reg = 0x39028, 2886 .enable_mask = BIT(0), 2887 .hw.init = &(struct clk_init_data){ 2888 .name = "gcc_usb30_prim_mock_utmi_clk", 2889 .parent_hws = (const struct clk_hw*[]) { 2890 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2891 }, 2892 .num_parents = 1, 2893 .flags = CLK_SET_RATE_PARENT, 2894 .ops = &clk_branch2_ops, 2895 }, 2896 }, 2897 }; 2898 2899 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2900 .halt_reg = 0x39024, 2901 .halt_check = BRANCH_HALT, 2902 .clkr = { 2903 .enable_reg = 0x39024, 2904 .enable_mask = BIT(0), 2905 .hw.init = &(struct clk_init_data){ 2906 .name = "gcc_usb30_prim_sleep_clk", 2907 .ops = &clk_branch2_ops, 2908 }, 2909 }, 2910 }; 2911 2912 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2913 .halt_reg = 0x39060, 2914 .halt_check = BRANCH_HALT, 2915 .clkr = { 2916 .enable_reg = 0x39060, 2917 .enable_mask = BIT(0), 2918 .hw.init = &(struct clk_init_data){ 2919 .name = "gcc_usb3_prim_phy_aux_clk", 2920 .parent_hws = (const struct clk_hw*[]) { 2921 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2922 }, 2923 .num_parents = 1, 2924 .flags = CLK_SET_RATE_PARENT, 2925 .ops = &clk_branch2_ops, 2926 }, 2927 }, 2928 }; 2929 2930 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2931 .halt_reg = 0x39064, 2932 .halt_check = BRANCH_HALT, 2933 .clkr = { 2934 .enable_reg = 0x39064, 2935 .enable_mask = BIT(0), 2936 .hw.init = &(struct clk_init_data){ 2937 .name = "gcc_usb3_prim_phy_com_aux_clk", 2938 .parent_hws = (const struct clk_hw*[]) { 2939 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2940 }, 2941 .num_parents = 1, 2942 .flags = CLK_SET_RATE_PARENT, 2943 .ops = &clk_branch2_ops, 2944 }, 2945 }, 2946 }; 2947 2948 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2949 .halt_reg = 0x39068, 2950 .halt_check = BRANCH_HALT_DELAY, 2951 .hwcg_reg = 0x39068, 2952 .hwcg_bit = 1, 2953 .clkr = { 2954 .enable_reg = 0x39068, 2955 .enable_mask = BIT(0), 2956 .hw.init = &(struct clk_init_data){ 2957 .name = "gcc_usb3_prim_phy_pipe_clk", 2958 .parent_hws = (const struct clk_hw*[]) { 2959 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 2960 }, 2961 .num_parents = 1, 2962 .flags = CLK_SET_RATE_PARENT, 2963 .ops = &clk_branch2_ops, 2964 }, 2965 }, 2966 }; 2967 2968 static struct clk_branch gcc_video_axi0_clk = { 2969 .halt_reg = 0x32018, 2970 .halt_check = BRANCH_HALT_SKIP, 2971 .hwcg_reg = 0x32018, 2972 .hwcg_bit = 1, 2973 .clkr = { 2974 .enable_reg = 0x32018, 2975 .enable_mask = BIT(0), 2976 .hw.init = &(struct clk_init_data){ 2977 .name = "gcc_video_axi0_clk", 2978 .ops = &clk_branch2_ops, 2979 }, 2980 }, 2981 }; 2982 2983 static struct clk_branch gcc_video_axi1_clk = { 2984 .halt_reg = 0x32024, 2985 .halt_check = BRANCH_HALT_SKIP, 2986 .hwcg_reg = 0x32024, 2987 .hwcg_bit = 1, 2988 .clkr = { 2989 .enable_reg = 0x32024, 2990 .enable_mask = BIT(0), 2991 .hw.init = &(struct clk_init_data){ 2992 .name = "gcc_video_axi1_clk", 2993 .ops = &clk_branch2_ops, 2994 }, 2995 }, 2996 }; 2997 2998 static struct gdsc pcie_0_gdsc = { 2999 .gdscr = 0x6b004, 3000 .pd = { 3001 .name = "pcie_0_gdsc", 3002 }, 3003 .pwrsts = PWRSTS_OFF_ON, 3004 .flags = POLL_CFG_GDSCR, 3005 }; 3006 3007 static struct gdsc pcie_0_phy_gdsc = { 3008 .gdscr = 0x6c000, 3009 .pd = { 3010 .name = "pcie_0_phy_gdsc", 3011 }, 3012 .pwrsts = PWRSTS_OFF_ON, 3013 .flags = POLL_CFG_GDSCR, 3014 }; 3015 3016 static struct gdsc pcie_1_gdsc = { 3017 .gdscr = 0x8d004, 3018 .pd = { 3019 .name = "pcie_1_gdsc", 3020 }, 3021 .pwrsts = PWRSTS_OFF_ON, 3022 .flags = POLL_CFG_GDSCR, 3023 }; 3024 3025 static struct gdsc pcie_1_phy_gdsc = { 3026 .gdscr = 0x8e000, 3027 .pd = { 3028 .name = "pcie_1_phy_gdsc", 3029 }, 3030 .pwrsts = PWRSTS_OFF_ON, 3031 .flags = POLL_CFG_GDSCR, 3032 }; 3033 3034 static struct gdsc ufs_phy_gdsc = { 3035 .gdscr = 0x77004, 3036 .pd = { 3037 .name = "ufs_phy_gdsc", 3038 }, 3039 .pwrsts = PWRSTS_OFF_ON, 3040 .flags = POLL_CFG_GDSCR, 3041 }; 3042 3043 static struct gdsc ufs_mem_phy_gdsc = { 3044 .gdscr = 0x9e000, 3045 .pd = { 3046 .name = "ufs_mem_phy_gdsc", 3047 }, 3048 .pwrsts = PWRSTS_OFF_ON, 3049 .flags = POLL_CFG_GDSCR, 3050 }; 3051 3052 static struct gdsc usb30_prim_gdsc = { 3053 .gdscr = 0x39004, 3054 .pd = { 3055 .name = "usb30_prim_gdsc", 3056 }, 3057 .pwrsts = PWRSTS_OFF_ON, 3058 .flags = POLL_CFG_GDSCR, 3059 }; 3060 3061 static struct gdsc usb3_phy_gdsc = { 3062 .gdscr = 0x50018, 3063 .pd = { 3064 .name = "usb3_phy_gdsc", 3065 }, 3066 .pwrsts = PWRSTS_OFF_ON, 3067 .flags = POLL_CFG_GDSCR, 3068 }; 3069 3070 static struct clk_regmap *gcc_sm8550_clocks[] = { 3071 [GCC_AGGRE_NOC_PCIE_AXI_CLK] = &gcc_aggre_noc_pcie_axi_clk.clkr, 3072 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 3073 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, 3074 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 3075 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3076 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 3077 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 3078 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr, 3079 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3080 [GCC_CNOC_PCIE_SF_AXI_CLK] = &gcc_cnoc_pcie_sf_axi_clk.clkr, 3081 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 3082 [GCC_DDRSS_PCIE_SF_QTB_CLK] = &gcc_ddrss_pcie_sf_qtb_clk.clkr, 3083 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3084 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3085 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3086 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3087 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3088 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3089 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3090 [GCC_GPLL0] = &gcc_gpll0.clkr, 3091 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 3092 [GCC_GPLL4] = &gcc_gpll4.clkr, 3093 [GCC_GPLL7] = &gcc_gpll7.clkr, 3094 [GCC_GPLL9] = &gcc_gpll9.clkr, 3095 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3096 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3097 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3098 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3099 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3100 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 3101 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3102 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3103 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 3104 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 3105 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3106 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 3107 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3108 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 3109 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 3110 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 3111 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 3112 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 3113 [GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr, 3114 [GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr, 3115 [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr, 3116 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 3117 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 3118 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr, 3119 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 3120 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 3121 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3122 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3123 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3124 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3125 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3126 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3127 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3128 [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr, 3129 [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr, 3130 [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr, 3131 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 3132 [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr, 3133 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3134 [GCC_QUPV3_I2C_CORE_CLK] = &gcc_qupv3_i2c_core_clk.clkr, 3135 [GCC_QUPV3_I2C_S0_CLK] = &gcc_qupv3_i2c_s0_clk.clkr, 3136 [GCC_QUPV3_I2C_S0_CLK_SRC] = &gcc_qupv3_i2c_s0_clk_src.clkr, 3137 [GCC_QUPV3_I2C_S1_CLK] = &gcc_qupv3_i2c_s1_clk.clkr, 3138 [GCC_QUPV3_I2C_S1_CLK_SRC] = &gcc_qupv3_i2c_s1_clk_src.clkr, 3139 [GCC_QUPV3_I2C_S2_CLK] = &gcc_qupv3_i2c_s2_clk.clkr, 3140 [GCC_QUPV3_I2C_S2_CLK_SRC] = &gcc_qupv3_i2c_s2_clk_src.clkr, 3141 [GCC_QUPV3_I2C_S3_CLK] = &gcc_qupv3_i2c_s3_clk.clkr, 3142 [GCC_QUPV3_I2C_S3_CLK_SRC] = &gcc_qupv3_i2c_s3_clk_src.clkr, 3143 [GCC_QUPV3_I2C_S4_CLK] = &gcc_qupv3_i2c_s4_clk.clkr, 3144 [GCC_QUPV3_I2C_S4_CLK_SRC] = &gcc_qupv3_i2c_s4_clk_src.clkr, 3145 [GCC_QUPV3_I2C_S5_CLK] = &gcc_qupv3_i2c_s5_clk.clkr, 3146 [GCC_QUPV3_I2C_S5_CLK_SRC] = &gcc_qupv3_i2c_s5_clk_src.clkr, 3147 [GCC_QUPV3_I2C_S6_CLK] = &gcc_qupv3_i2c_s6_clk.clkr, 3148 [GCC_QUPV3_I2C_S6_CLK_SRC] = &gcc_qupv3_i2c_s6_clk_src.clkr, 3149 [GCC_QUPV3_I2C_S7_CLK] = &gcc_qupv3_i2c_s7_clk.clkr, 3150 [GCC_QUPV3_I2C_S7_CLK_SRC] = &gcc_qupv3_i2c_s7_clk_src.clkr, 3151 [GCC_QUPV3_I2C_S8_CLK] = &gcc_qupv3_i2c_s8_clk.clkr, 3152 [GCC_QUPV3_I2C_S8_CLK_SRC] = &gcc_qupv3_i2c_s8_clk_src.clkr, 3153 [GCC_QUPV3_I2C_S9_CLK] = &gcc_qupv3_i2c_s9_clk.clkr, 3154 [GCC_QUPV3_I2C_S9_CLK_SRC] = &gcc_qupv3_i2c_s9_clk_src.clkr, 3155 [GCC_QUPV3_I2C_S_AHB_CLK] = &gcc_qupv3_i2c_s_ahb_clk.clkr, 3156 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3157 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3158 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3159 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3160 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3161 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3162 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3163 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3164 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3165 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3166 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3167 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3168 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3169 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3170 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 3171 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 3172 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 3173 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 3174 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 3175 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 3176 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 3177 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 3178 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 3179 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 3180 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 3181 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 3182 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 3183 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 3184 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 3185 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 3186 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 3187 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 3188 [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr, 3189 [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr, 3190 [GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr, 3191 [GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr, 3192 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3193 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3194 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 3195 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 3196 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3197 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3198 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3199 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3200 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3201 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 3202 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3203 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3204 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3205 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, 3206 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3207 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3208 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, 3209 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3210 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3211 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, 3212 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3213 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 3214 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3215 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 3216 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3217 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 3218 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3219 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 3220 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, 3221 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3222 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3223 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3224 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3225 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3226 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3227 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3228 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3229 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3230 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3231 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 3232 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3233 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 3234 }; 3235 3236 static const struct qcom_reset_map gcc_sm8550_resets[] = { 3237 [GCC_CAMERA_BCR] = { 0x26000 }, 3238 [GCC_DISPLAY_BCR] = { 0x27000 }, 3239 [GCC_GPU_BCR] = { 0x71000 }, 3240 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3241 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 3242 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 3243 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3244 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, 3245 [GCC_PCIE_1_BCR] = { 0x8d000 }, 3246 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, 3247 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, 3248 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 3249 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 }, 3250 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 3251 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, 3252 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, 3253 [GCC_PDM_BCR] = { 0x33000 }, 3254 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 3255 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, 3256 [GCC_QUPV3_WRAPPER_I2C_BCR] = { 0x17000 }, 3257 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3258 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3259 [GCC_SDCC2_BCR] = { 0x14000 }, 3260 [GCC_SDCC4_BCR] = { 0x16000 }, 3261 [GCC_UFS_PHY_BCR] = { 0x77000 }, 3262 [GCC_USB30_PRIM_BCR] = { 0x39000 }, 3263 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 3264 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 3265 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 3266 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 3267 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3268 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3269 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 3270 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 }, 3271 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32024, 2 }, 3272 [GCC_VIDEO_BCR] = { 0x32000 }, 3273 }; 3274 3275 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3276 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3277 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3278 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 3279 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3280 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3281 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3282 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 3283 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 3284 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 3285 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 3286 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 3287 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 3288 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 3289 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 3290 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src), 3291 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src), 3292 }; 3293 3294 static struct gdsc *gcc_sm8550_gdscs[] = { 3295 [PCIE_0_GDSC] = &pcie_0_gdsc, 3296 [PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc, 3297 [PCIE_1_GDSC] = &pcie_1_gdsc, 3298 [PCIE_1_PHY_GDSC] = &pcie_1_phy_gdsc, 3299 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3300 [UFS_MEM_PHY_GDSC] = &ufs_mem_phy_gdsc, 3301 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3302 [USB3_PHY_GDSC] = &usb3_phy_gdsc, 3303 }; 3304 3305 static const struct regmap_config gcc_sm8550_regmap_config = { 3306 .reg_bits = 32, 3307 .reg_stride = 4, 3308 .val_bits = 32, 3309 .max_register = 0x1f41f0, 3310 .fast_io = true, 3311 }; 3312 3313 static const struct qcom_cc_desc gcc_sm8550_desc = { 3314 .config = &gcc_sm8550_regmap_config, 3315 .clks = gcc_sm8550_clocks, 3316 .num_clks = ARRAY_SIZE(gcc_sm8550_clocks), 3317 .resets = gcc_sm8550_resets, 3318 .num_resets = ARRAY_SIZE(gcc_sm8550_resets), 3319 .gdscs = gcc_sm8550_gdscs, 3320 .num_gdscs = ARRAY_SIZE(gcc_sm8550_gdscs), 3321 }; 3322 3323 static const struct of_device_id gcc_sm8550_match_table[] = { 3324 { .compatible = "qcom,sm8550-gcc" }, 3325 { } 3326 }; 3327 MODULE_DEVICE_TABLE(of, gcc_sm8550_match_table); 3328 3329 static int gcc_sm8550_probe(struct platform_device *pdev) 3330 { 3331 struct regmap *regmap; 3332 int ret; 3333 3334 regmap = qcom_cc_map(pdev, &gcc_sm8550_desc); 3335 if (IS_ERR(regmap)) 3336 return PTR_ERR(regmap); 3337 3338 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3339 ARRAY_SIZE(gcc_dfs_clocks)); 3340 if (ret) 3341 return ret; 3342 3343 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ 3344 regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14)); 3345 3346 /* 3347 * Keep the critical clock always-On 3348 * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk, 3349 * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, 3350 * gcc_video_xo_clk 3351 */ 3352 regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); 3353 regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); 3354 regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); 3355 regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); 3356 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 3357 regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); 3358 regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); 3359 3360 /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ 3361 regmap_write(regmap, 0x52024, 0x0); 3362 3363 return qcom_cc_really_probe(pdev, &gcc_sm8550_desc, regmap); 3364 } 3365 3366 static struct platform_driver gcc_sm8550_driver = { 3367 .probe = gcc_sm8550_probe, 3368 .driver = { 3369 .name = "gcc-sm8550", 3370 .of_match_table = gcc_sm8550_match_table, 3371 }, 3372 }; 3373 3374 static int __init gcc_sm8550_init(void) 3375 { 3376 return platform_driver_register(&gcc_sm8550_driver); 3377 } 3378 subsys_initcall(gcc_sm8550_init); 3379 3380 static void __exit gcc_sm8550_exit(void) 3381 { 3382 platform_driver_unregister(&gcc_sm8550_driver); 3383 } 3384 module_exit(gcc_sm8550_exit); 3385 3386 MODULE_DESCRIPTION("QTI GCC SM8550 Driver"); 3387 MODULE_LICENSE("GPL"); 3388