1*955f2ea3SAbel Vesa // SPDX-License-Identifier: GPL-2.0-only 2*955f2ea3SAbel Vesa /* 3*955f2ea3SAbel Vesa * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4*955f2ea3SAbel Vesa * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 5*955f2ea3SAbel Vesa * Copyright (c) 2022, Linaro Limited 6*955f2ea3SAbel Vesa */ 7*955f2ea3SAbel Vesa 8*955f2ea3SAbel Vesa #include <linux/clk-provider.h> 9*955f2ea3SAbel Vesa #include <linux/module.h> 10*955f2ea3SAbel Vesa #include <linux/of_device.h> 11*955f2ea3SAbel Vesa #include <linux/regmap.h> 12*955f2ea3SAbel Vesa 13*955f2ea3SAbel Vesa #include <dt-bindings/clock/qcom,sm8550-gcc.h> 14*955f2ea3SAbel Vesa 15*955f2ea3SAbel Vesa #include "clk-alpha-pll.h" 16*955f2ea3SAbel Vesa #include "clk-branch.h" 17*955f2ea3SAbel Vesa #include "clk-rcg.h" 18*955f2ea3SAbel Vesa #include "clk-regmap.h" 19*955f2ea3SAbel Vesa #include "clk-regmap-divider.h" 20*955f2ea3SAbel Vesa #include "clk-regmap-mux.h" 21*955f2ea3SAbel Vesa #include "clk-regmap-phy-mux.h" 22*955f2ea3SAbel Vesa #include "gdsc.h" 23*955f2ea3SAbel Vesa #include "reset.h" 24*955f2ea3SAbel Vesa 25*955f2ea3SAbel Vesa enum { 26*955f2ea3SAbel Vesa DT_BI_TCXO, 27*955f2ea3SAbel Vesa DT_SLEEP_CLK, 28*955f2ea3SAbel Vesa DT_PCIE_0_PIPE, 29*955f2ea3SAbel Vesa DT_PCIE_1_PIPE, 30*955f2ea3SAbel Vesa DT_PCIE_1_PHY_AUX, 31*955f2ea3SAbel Vesa DT_UFS_PHY_RX_SYMBOL_0, 32*955f2ea3SAbel Vesa DT_UFS_PHY_RX_SYMBOL_1, 33*955f2ea3SAbel Vesa DT_UFS_PHY_TX_SYMBOL_0, 34*955f2ea3SAbel Vesa DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE, 35*955f2ea3SAbel Vesa }; 36*955f2ea3SAbel Vesa 37*955f2ea3SAbel Vesa enum { 38*955f2ea3SAbel Vesa P_BI_TCXO, 39*955f2ea3SAbel Vesa P_GCC_GPLL0_OUT_EVEN, 40*955f2ea3SAbel Vesa P_GCC_GPLL0_OUT_MAIN, 41*955f2ea3SAbel Vesa P_GCC_GPLL4_OUT_MAIN, 42*955f2ea3SAbel Vesa P_GCC_GPLL7_OUT_MAIN, 43*955f2ea3SAbel Vesa P_GCC_GPLL9_OUT_MAIN, 44*955f2ea3SAbel Vesa P_PCIE_0_PIPE_CLK, 45*955f2ea3SAbel Vesa P_PCIE_1_PHY_AUX_CLK, 46*955f2ea3SAbel Vesa P_PCIE_1_PIPE_CLK, 47*955f2ea3SAbel Vesa P_SLEEP_CLK, 48*955f2ea3SAbel Vesa P_UFS_PHY_RX_SYMBOL_0_CLK, 49*955f2ea3SAbel Vesa P_UFS_PHY_RX_SYMBOL_1_CLK, 50*955f2ea3SAbel Vesa P_UFS_PHY_TX_SYMBOL_0_CLK, 51*955f2ea3SAbel Vesa P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 52*955f2ea3SAbel Vesa }; 53*955f2ea3SAbel Vesa 54*955f2ea3SAbel Vesa static struct clk_alpha_pll gcc_gpll0 = { 55*955f2ea3SAbel Vesa .offset = 0x0, 56*955f2ea3SAbel Vesa .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 57*955f2ea3SAbel Vesa .clkr = { 58*955f2ea3SAbel Vesa .enable_reg = 0x52018, 59*955f2ea3SAbel Vesa .enable_mask = BIT(0), 60*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 61*955f2ea3SAbel Vesa .name = "gcc_gpll0", 62*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 63*955f2ea3SAbel Vesa .index = DT_BI_TCXO, 64*955f2ea3SAbel Vesa }, 65*955f2ea3SAbel Vesa .num_parents = 1, 66*955f2ea3SAbel Vesa .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 67*955f2ea3SAbel Vesa }, 68*955f2ea3SAbel Vesa }, 69*955f2ea3SAbel Vesa }; 70*955f2ea3SAbel Vesa 71*955f2ea3SAbel Vesa static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 72*955f2ea3SAbel Vesa { 0x1, 2 }, 73*955f2ea3SAbel Vesa { } 74*955f2ea3SAbel Vesa }; 75*955f2ea3SAbel Vesa 76*955f2ea3SAbel Vesa static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 77*955f2ea3SAbel Vesa .offset = 0x0, 78*955f2ea3SAbel Vesa .post_div_shift = 10, 79*955f2ea3SAbel Vesa .post_div_table = post_div_table_gcc_gpll0_out_even, 80*955f2ea3SAbel Vesa .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 81*955f2ea3SAbel Vesa .width = 4, 82*955f2ea3SAbel Vesa .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 83*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 84*955f2ea3SAbel Vesa .name = "gcc_gpll0_out_even", 85*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 86*955f2ea3SAbel Vesa .hw = &gcc_gpll0.clkr.hw, 87*955f2ea3SAbel Vesa }, 88*955f2ea3SAbel Vesa .num_parents = 1, 89*955f2ea3SAbel Vesa .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 90*955f2ea3SAbel Vesa }, 91*955f2ea3SAbel Vesa }; 92*955f2ea3SAbel Vesa 93*955f2ea3SAbel Vesa static struct clk_alpha_pll gcc_gpll4 = { 94*955f2ea3SAbel Vesa .offset = 0x4000, 95*955f2ea3SAbel Vesa .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 96*955f2ea3SAbel Vesa .clkr = { 97*955f2ea3SAbel Vesa .enable_reg = 0x52018, 98*955f2ea3SAbel Vesa .enable_mask = BIT(4), 99*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 100*955f2ea3SAbel Vesa .name = "gcc_gpll4", 101*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 102*955f2ea3SAbel Vesa .index = DT_BI_TCXO, 103*955f2ea3SAbel Vesa }, 104*955f2ea3SAbel Vesa .num_parents = 1, 105*955f2ea3SAbel Vesa .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 106*955f2ea3SAbel Vesa }, 107*955f2ea3SAbel Vesa }, 108*955f2ea3SAbel Vesa }; 109*955f2ea3SAbel Vesa 110*955f2ea3SAbel Vesa static struct clk_alpha_pll gcc_gpll7 = { 111*955f2ea3SAbel Vesa .offset = 0x7000, 112*955f2ea3SAbel Vesa .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 113*955f2ea3SAbel Vesa .clkr = { 114*955f2ea3SAbel Vesa .enable_reg = 0x52018, 115*955f2ea3SAbel Vesa .enable_mask = BIT(7), 116*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 117*955f2ea3SAbel Vesa .name = "gcc_gpll7", 118*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 119*955f2ea3SAbel Vesa .index = DT_BI_TCXO, 120*955f2ea3SAbel Vesa }, 121*955f2ea3SAbel Vesa .num_parents = 1, 122*955f2ea3SAbel Vesa .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 123*955f2ea3SAbel Vesa }, 124*955f2ea3SAbel Vesa }, 125*955f2ea3SAbel Vesa }; 126*955f2ea3SAbel Vesa 127*955f2ea3SAbel Vesa static struct clk_alpha_pll gcc_gpll9 = { 128*955f2ea3SAbel Vesa .offset = 0x9000, 129*955f2ea3SAbel Vesa .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 130*955f2ea3SAbel Vesa .clkr = { 131*955f2ea3SAbel Vesa .enable_reg = 0x52018, 132*955f2ea3SAbel Vesa .enable_mask = BIT(9), 133*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 134*955f2ea3SAbel Vesa .name = "gcc_gpll9", 135*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 136*955f2ea3SAbel Vesa .index = DT_BI_TCXO, 137*955f2ea3SAbel Vesa }, 138*955f2ea3SAbel Vesa .num_parents = 1, 139*955f2ea3SAbel Vesa .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 140*955f2ea3SAbel Vesa }, 141*955f2ea3SAbel Vesa }, 142*955f2ea3SAbel Vesa }; 143*955f2ea3SAbel Vesa 144*955f2ea3SAbel Vesa static const struct parent_map gcc_parent_map_0[] = { 145*955f2ea3SAbel Vesa { P_BI_TCXO, 0 }, 146*955f2ea3SAbel Vesa { P_GCC_GPLL0_OUT_MAIN, 1 }, 147*955f2ea3SAbel Vesa { P_GCC_GPLL0_OUT_EVEN, 6 }, 148*955f2ea3SAbel Vesa }; 149*955f2ea3SAbel Vesa 150*955f2ea3SAbel Vesa static const struct clk_parent_data gcc_parent_data_0[] = { 151*955f2ea3SAbel Vesa { .index = DT_BI_TCXO }, 152*955f2ea3SAbel Vesa { .hw = &gcc_gpll0.clkr.hw }, 153*955f2ea3SAbel Vesa { .hw = &gcc_gpll0_out_even.clkr.hw }, 154*955f2ea3SAbel Vesa }; 155*955f2ea3SAbel Vesa 156*955f2ea3SAbel Vesa static const struct parent_map gcc_parent_map_1[] = { 157*955f2ea3SAbel Vesa { P_BI_TCXO, 0 }, 158*955f2ea3SAbel Vesa { P_GCC_GPLL0_OUT_MAIN, 1 }, 159*955f2ea3SAbel Vesa { P_SLEEP_CLK, 5 }, 160*955f2ea3SAbel Vesa { P_GCC_GPLL0_OUT_EVEN, 6 }, 161*955f2ea3SAbel Vesa }; 162*955f2ea3SAbel Vesa 163*955f2ea3SAbel Vesa static const struct clk_parent_data gcc_parent_data_1[] = { 164*955f2ea3SAbel Vesa { .index = DT_BI_TCXO }, 165*955f2ea3SAbel Vesa { .hw = &gcc_gpll0.clkr.hw }, 166*955f2ea3SAbel Vesa { .index = DT_SLEEP_CLK }, 167*955f2ea3SAbel Vesa { .hw = &gcc_gpll0_out_even.clkr.hw }, 168*955f2ea3SAbel Vesa }; 169*955f2ea3SAbel Vesa 170*955f2ea3SAbel Vesa static const struct parent_map gcc_parent_map_2[] = { 171*955f2ea3SAbel Vesa { P_BI_TCXO, 0 }, 172*955f2ea3SAbel Vesa { P_SLEEP_CLK, 5 }, 173*955f2ea3SAbel Vesa }; 174*955f2ea3SAbel Vesa 175*955f2ea3SAbel Vesa static const struct clk_parent_data gcc_parent_data_2[] = { 176*955f2ea3SAbel Vesa { .index = DT_BI_TCXO }, 177*955f2ea3SAbel Vesa { .index = DT_SLEEP_CLK }, 178*955f2ea3SAbel Vesa }; 179*955f2ea3SAbel Vesa 180*955f2ea3SAbel Vesa static const struct parent_map gcc_parent_map_3[] = { 181*955f2ea3SAbel Vesa { P_BI_TCXO, 0 }, 182*955f2ea3SAbel Vesa { P_GCC_GPLL0_OUT_MAIN, 1 }, 183*955f2ea3SAbel Vesa { P_GCC_GPLL4_OUT_MAIN, 5 }, 184*955f2ea3SAbel Vesa { P_GCC_GPLL0_OUT_EVEN, 6 }, 185*955f2ea3SAbel Vesa }; 186*955f2ea3SAbel Vesa 187*955f2ea3SAbel Vesa static const struct clk_parent_data gcc_parent_data_3[] = { 188*955f2ea3SAbel Vesa { .index = DT_BI_TCXO }, 189*955f2ea3SAbel Vesa { .hw = &gcc_gpll0.clkr.hw }, 190*955f2ea3SAbel Vesa { .hw = &gcc_gpll4.clkr.hw }, 191*955f2ea3SAbel Vesa { .hw = &gcc_gpll0_out_even.clkr.hw }, 192*955f2ea3SAbel Vesa }; 193*955f2ea3SAbel Vesa 194*955f2ea3SAbel Vesa static const struct parent_map gcc_parent_map_4[] = { 195*955f2ea3SAbel Vesa { P_BI_TCXO, 0 }, 196*955f2ea3SAbel Vesa }; 197*955f2ea3SAbel Vesa 198*955f2ea3SAbel Vesa static const struct clk_parent_data gcc_parent_data_4[] = { 199*955f2ea3SAbel Vesa { .index = DT_BI_TCXO }, 200*955f2ea3SAbel Vesa }; 201*955f2ea3SAbel Vesa 202*955f2ea3SAbel Vesa static const struct parent_map gcc_parent_map_6[] = { 203*955f2ea3SAbel Vesa { P_PCIE_1_PHY_AUX_CLK, 0 }, 204*955f2ea3SAbel Vesa { P_BI_TCXO, 2 }, 205*955f2ea3SAbel Vesa }; 206*955f2ea3SAbel Vesa 207*955f2ea3SAbel Vesa static const struct clk_parent_data gcc_parent_data_6[] = { 208*955f2ea3SAbel Vesa { .index = DT_PCIE_1_PHY_AUX }, 209*955f2ea3SAbel Vesa { .index = DT_BI_TCXO }, 210*955f2ea3SAbel Vesa }; 211*955f2ea3SAbel Vesa 212*955f2ea3SAbel Vesa static const struct parent_map gcc_parent_map_8[] = { 213*955f2ea3SAbel Vesa { P_BI_TCXO, 0 }, 214*955f2ea3SAbel Vesa { P_GCC_GPLL0_OUT_MAIN, 1 }, 215*955f2ea3SAbel Vesa { P_GCC_GPLL7_OUT_MAIN, 2 }, 216*955f2ea3SAbel Vesa { P_GCC_GPLL0_OUT_EVEN, 6 }, 217*955f2ea3SAbel Vesa }; 218*955f2ea3SAbel Vesa 219*955f2ea3SAbel Vesa static const struct clk_parent_data gcc_parent_data_8[] = { 220*955f2ea3SAbel Vesa { .index = DT_BI_TCXO }, 221*955f2ea3SAbel Vesa { .hw = &gcc_gpll0.clkr.hw }, 222*955f2ea3SAbel Vesa { .hw = &gcc_gpll7.clkr.hw }, 223*955f2ea3SAbel Vesa { .hw = &gcc_gpll0_out_even.clkr.hw }, 224*955f2ea3SAbel Vesa }; 225*955f2ea3SAbel Vesa 226*955f2ea3SAbel Vesa static const struct parent_map gcc_parent_map_9[] = { 227*955f2ea3SAbel Vesa { P_BI_TCXO, 0 }, 228*955f2ea3SAbel Vesa { P_GCC_GPLL0_OUT_MAIN, 1 }, 229*955f2ea3SAbel Vesa { P_GCC_GPLL9_OUT_MAIN, 2 }, 230*955f2ea3SAbel Vesa { P_GCC_GPLL4_OUT_MAIN, 5 }, 231*955f2ea3SAbel Vesa { P_GCC_GPLL0_OUT_EVEN, 6 }, 232*955f2ea3SAbel Vesa }; 233*955f2ea3SAbel Vesa 234*955f2ea3SAbel Vesa static const struct clk_parent_data gcc_parent_data_9[] = { 235*955f2ea3SAbel Vesa { .index = DT_BI_TCXO }, 236*955f2ea3SAbel Vesa { .hw = &gcc_gpll0.clkr.hw }, 237*955f2ea3SAbel Vesa { .hw = &gcc_gpll9.clkr.hw }, 238*955f2ea3SAbel Vesa { .hw = &gcc_gpll4.clkr.hw }, 239*955f2ea3SAbel Vesa { .hw = &gcc_gpll0_out_even.clkr.hw }, 240*955f2ea3SAbel Vesa }; 241*955f2ea3SAbel Vesa 242*955f2ea3SAbel Vesa static const struct parent_map gcc_parent_map_10[] = { 243*955f2ea3SAbel Vesa { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, 244*955f2ea3SAbel Vesa { P_BI_TCXO, 2 }, 245*955f2ea3SAbel Vesa }; 246*955f2ea3SAbel Vesa 247*955f2ea3SAbel Vesa static const struct clk_parent_data gcc_parent_data_10[] = { 248*955f2ea3SAbel Vesa { .index = DT_UFS_PHY_RX_SYMBOL_0 }, 249*955f2ea3SAbel Vesa { .index = DT_BI_TCXO }, 250*955f2ea3SAbel Vesa }; 251*955f2ea3SAbel Vesa 252*955f2ea3SAbel Vesa static const struct parent_map gcc_parent_map_11[] = { 253*955f2ea3SAbel Vesa { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, 254*955f2ea3SAbel Vesa { P_BI_TCXO, 2 }, 255*955f2ea3SAbel Vesa }; 256*955f2ea3SAbel Vesa 257*955f2ea3SAbel Vesa static const struct clk_parent_data gcc_parent_data_11[] = { 258*955f2ea3SAbel Vesa { .index = DT_UFS_PHY_RX_SYMBOL_1 }, 259*955f2ea3SAbel Vesa { .index = DT_BI_TCXO }, 260*955f2ea3SAbel Vesa }; 261*955f2ea3SAbel Vesa 262*955f2ea3SAbel Vesa static const struct parent_map gcc_parent_map_12[] = { 263*955f2ea3SAbel Vesa { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, 264*955f2ea3SAbel Vesa { P_BI_TCXO, 2 }, 265*955f2ea3SAbel Vesa }; 266*955f2ea3SAbel Vesa 267*955f2ea3SAbel Vesa static const struct clk_parent_data gcc_parent_data_12[] = { 268*955f2ea3SAbel Vesa { .index = DT_UFS_PHY_TX_SYMBOL_0 }, 269*955f2ea3SAbel Vesa { .index = DT_BI_TCXO }, 270*955f2ea3SAbel Vesa }; 271*955f2ea3SAbel Vesa 272*955f2ea3SAbel Vesa static const struct parent_map gcc_parent_map_13[] = { 273*955f2ea3SAbel Vesa { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 274*955f2ea3SAbel Vesa { P_BI_TCXO, 2 }, 275*955f2ea3SAbel Vesa }; 276*955f2ea3SAbel Vesa 277*955f2ea3SAbel Vesa static const struct clk_parent_data gcc_parent_data_13[] = { 278*955f2ea3SAbel Vesa { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE }, 279*955f2ea3SAbel Vesa { .index = DT_BI_TCXO }, 280*955f2ea3SAbel Vesa }; 281*955f2ea3SAbel Vesa 282*955f2ea3SAbel Vesa static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { 283*955f2ea3SAbel Vesa .reg = 0x6b070, 284*955f2ea3SAbel Vesa .clkr = { 285*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 286*955f2ea3SAbel Vesa .name = "gcc_pcie_0_pipe_clk_src", 287*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 288*955f2ea3SAbel Vesa .index = DT_PCIE_0_PIPE, 289*955f2ea3SAbel Vesa }, 290*955f2ea3SAbel Vesa .num_parents = 1, 291*955f2ea3SAbel Vesa .ops = &clk_regmap_phy_mux_ops, 292*955f2ea3SAbel Vesa }, 293*955f2ea3SAbel Vesa }, 294*955f2ea3SAbel Vesa }; 295*955f2ea3SAbel Vesa 296*955f2ea3SAbel Vesa static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = { 297*955f2ea3SAbel Vesa .reg = 0x8d094, 298*955f2ea3SAbel Vesa .shift = 0, 299*955f2ea3SAbel Vesa .width = 2, 300*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_6, 301*955f2ea3SAbel Vesa .clkr = { 302*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 303*955f2ea3SAbel Vesa .name = "gcc_pcie_1_phy_aux_clk_src", 304*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_6, 305*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_6), 306*955f2ea3SAbel Vesa .ops = &clk_regmap_mux_closest_ops, 307*955f2ea3SAbel Vesa }, 308*955f2ea3SAbel Vesa }, 309*955f2ea3SAbel Vesa }; 310*955f2ea3SAbel Vesa 311*955f2ea3SAbel Vesa static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = { 312*955f2ea3SAbel Vesa .reg = 0x8d078, 313*955f2ea3SAbel Vesa .clkr = { 314*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 315*955f2ea3SAbel Vesa .name = "gcc_pcie_1_pipe_clk_src", 316*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 317*955f2ea3SAbel Vesa .index = DT_PCIE_1_PIPE, 318*955f2ea3SAbel Vesa }, 319*955f2ea3SAbel Vesa .num_parents = 1, 320*955f2ea3SAbel Vesa .ops = &clk_regmap_phy_mux_ops, 321*955f2ea3SAbel Vesa }, 322*955f2ea3SAbel Vesa }, 323*955f2ea3SAbel Vesa }; 324*955f2ea3SAbel Vesa 325*955f2ea3SAbel Vesa static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 326*955f2ea3SAbel Vesa .reg = 0x77064, 327*955f2ea3SAbel Vesa .shift = 0, 328*955f2ea3SAbel Vesa .width = 2, 329*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_10, 330*955f2ea3SAbel Vesa .clkr = { 331*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 332*955f2ea3SAbel Vesa .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 333*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_10, 334*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_10), 335*955f2ea3SAbel Vesa .ops = &clk_regmap_mux_closest_ops, 336*955f2ea3SAbel Vesa }, 337*955f2ea3SAbel Vesa }, 338*955f2ea3SAbel Vesa }; 339*955f2ea3SAbel Vesa 340*955f2ea3SAbel Vesa static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 341*955f2ea3SAbel Vesa .reg = 0x770e0, 342*955f2ea3SAbel Vesa .shift = 0, 343*955f2ea3SAbel Vesa .width = 2, 344*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_11, 345*955f2ea3SAbel Vesa .clkr = { 346*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 347*955f2ea3SAbel Vesa .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 348*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_11, 349*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_11), 350*955f2ea3SAbel Vesa .ops = &clk_regmap_mux_closest_ops, 351*955f2ea3SAbel Vesa }, 352*955f2ea3SAbel Vesa }, 353*955f2ea3SAbel Vesa }; 354*955f2ea3SAbel Vesa 355*955f2ea3SAbel Vesa static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 356*955f2ea3SAbel Vesa .reg = 0x77054, 357*955f2ea3SAbel Vesa .shift = 0, 358*955f2ea3SAbel Vesa .width = 2, 359*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_12, 360*955f2ea3SAbel Vesa .clkr = { 361*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 362*955f2ea3SAbel Vesa .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 363*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_12, 364*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_12), 365*955f2ea3SAbel Vesa .ops = &clk_regmap_mux_closest_ops, 366*955f2ea3SAbel Vesa }, 367*955f2ea3SAbel Vesa }, 368*955f2ea3SAbel Vesa }; 369*955f2ea3SAbel Vesa 370*955f2ea3SAbel Vesa static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 371*955f2ea3SAbel Vesa .reg = 0x3906c, 372*955f2ea3SAbel Vesa .shift = 0, 373*955f2ea3SAbel Vesa .width = 2, 374*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_13, 375*955f2ea3SAbel Vesa .clkr = { 376*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 377*955f2ea3SAbel Vesa .name = "gcc_usb3_prim_phy_pipe_clk_src", 378*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_13, 379*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_13), 380*955f2ea3SAbel Vesa .ops = &clk_regmap_mux_closest_ops, 381*955f2ea3SAbel Vesa }, 382*955f2ea3SAbel Vesa }, 383*955f2ea3SAbel Vesa }; 384*955f2ea3SAbel Vesa 385*955f2ea3SAbel Vesa static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 386*955f2ea3SAbel Vesa F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 387*955f2ea3SAbel Vesa F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 388*955f2ea3SAbel Vesa F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 389*955f2ea3SAbel Vesa { } 390*955f2ea3SAbel Vesa }; 391*955f2ea3SAbel Vesa 392*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_gp1_clk_src = { 393*955f2ea3SAbel Vesa .cmd_rcgr = 0x64004, 394*955f2ea3SAbel Vesa .mnd_width = 16, 395*955f2ea3SAbel Vesa .hid_width = 5, 396*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_1, 397*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_gp1_clk_src, 398*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 399*955f2ea3SAbel Vesa .name = "gcc_gp1_clk_src", 400*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_1, 401*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_1), 402*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 403*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 404*955f2ea3SAbel Vesa }, 405*955f2ea3SAbel Vesa }; 406*955f2ea3SAbel Vesa 407*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_gp2_clk_src = { 408*955f2ea3SAbel Vesa .cmd_rcgr = 0x65004, 409*955f2ea3SAbel Vesa .mnd_width = 16, 410*955f2ea3SAbel Vesa .hid_width = 5, 411*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_1, 412*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_gp1_clk_src, 413*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 414*955f2ea3SAbel Vesa .name = "gcc_gp2_clk_src", 415*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_1, 416*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_1), 417*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 418*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 419*955f2ea3SAbel Vesa }, 420*955f2ea3SAbel Vesa }; 421*955f2ea3SAbel Vesa 422*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_gp3_clk_src = { 423*955f2ea3SAbel Vesa .cmd_rcgr = 0x66004, 424*955f2ea3SAbel Vesa .mnd_width = 16, 425*955f2ea3SAbel Vesa .hid_width = 5, 426*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_1, 427*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_gp1_clk_src, 428*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 429*955f2ea3SAbel Vesa .name = "gcc_gp3_clk_src", 430*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_1, 431*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_1), 432*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 433*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 434*955f2ea3SAbel Vesa }, 435*955f2ea3SAbel Vesa }; 436*955f2ea3SAbel Vesa 437*955f2ea3SAbel Vesa static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 438*955f2ea3SAbel Vesa F(19200000, P_BI_TCXO, 1, 0, 0), 439*955f2ea3SAbel Vesa { } 440*955f2ea3SAbel Vesa }; 441*955f2ea3SAbel Vesa 442*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 443*955f2ea3SAbel Vesa .cmd_rcgr = 0x6b074, 444*955f2ea3SAbel Vesa .mnd_width = 16, 445*955f2ea3SAbel Vesa .hid_width = 5, 446*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_2, 447*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 448*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 449*955f2ea3SAbel Vesa .name = "gcc_pcie_0_aux_clk_src", 450*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_2, 451*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_2), 452*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 453*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 454*955f2ea3SAbel Vesa }, 455*955f2ea3SAbel Vesa }; 456*955f2ea3SAbel Vesa 457*955f2ea3SAbel Vesa static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 458*955f2ea3SAbel Vesa F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 459*955f2ea3SAbel Vesa { } 460*955f2ea3SAbel Vesa }; 461*955f2ea3SAbel Vesa 462*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 463*955f2ea3SAbel Vesa .cmd_rcgr = 0x6b058, 464*955f2ea3SAbel Vesa .mnd_width = 0, 465*955f2ea3SAbel Vesa .hid_width = 5, 466*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 467*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 468*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 469*955f2ea3SAbel Vesa .name = "gcc_pcie_0_phy_rchng_clk_src", 470*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 471*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 472*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 473*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 474*955f2ea3SAbel Vesa }, 475*955f2ea3SAbel Vesa }; 476*955f2ea3SAbel Vesa 477*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 478*955f2ea3SAbel Vesa .cmd_rcgr = 0x8d07c, 479*955f2ea3SAbel Vesa .mnd_width = 16, 480*955f2ea3SAbel Vesa .hid_width = 5, 481*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_2, 482*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 483*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 484*955f2ea3SAbel Vesa .name = "gcc_pcie_1_aux_clk_src", 485*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_2, 486*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_2), 487*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 488*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 489*955f2ea3SAbel Vesa }, 490*955f2ea3SAbel Vesa }; 491*955f2ea3SAbel Vesa 492*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 493*955f2ea3SAbel Vesa .cmd_rcgr = 0x8d060, 494*955f2ea3SAbel Vesa .mnd_width = 0, 495*955f2ea3SAbel Vesa .hid_width = 5, 496*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 497*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 498*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 499*955f2ea3SAbel Vesa .name = "gcc_pcie_1_phy_rchng_clk_src", 500*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 501*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 502*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 503*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 504*955f2ea3SAbel Vesa }, 505*955f2ea3SAbel Vesa }; 506*955f2ea3SAbel Vesa 507*955f2ea3SAbel Vesa static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 508*955f2ea3SAbel Vesa F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 509*955f2ea3SAbel Vesa { } 510*955f2ea3SAbel Vesa }; 511*955f2ea3SAbel Vesa 512*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_pdm2_clk_src = { 513*955f2ea3SAbel Vesa .cmd_rcgr = 0x33010, 514*955f2ea3SAbel Vesa .mnd_width = 0, 515*955f2ea3SAbel Vesa .hid_width = 5, 516*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 517*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_pdm2_clk_src, 518*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 519*955f2ea3SAbel Vesa .name = "gcc_pdm2_clk_src", 520*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 521*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 522*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 523*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 524*955f2ea3SAbel Vesa }, 525*955f2ea3SAbel Vesa }; 526*955f2ea3SAbel Vesa 527*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = { 528*955f2ea3SAbel Vesa .cmd_rcgr = 0x17008, 529*955f2ea3SAbel Vesa .mnd_width = 0, 530*955f2ea3SAbel Vesa .hid_width = 5, 531*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 532*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 533*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 534*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s0_clk_src", 535*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 536*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 537*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 538*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 539*955f2ea3SAbel Vesa }, 540*955f2ea3SAbel Vesa }; 541*955f2ea3SAbel Vesa 542*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = { 543*955f2ea3SAbel Vesa .cmd_rcgr = 0x17024, 544*955f2ea3SAbel Vesa .mnd_width = 0, 545*955f2ea3SAbel Vesa .hid_width = 5, 546*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 547*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 548*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 549*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s1_clk_src", 550*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 551*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 552*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 553*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 554*955f2ea3SAbel Vesa }, 555*955f2ea3SAbel Vesa }; 556*955f2ea3SAbel Vesa 557*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = { 558*955f2ea3SAbel Vesa .cmd_rcgr = 0x17040, 559*955f2ea3SAbel Vesa .mnd_width = 0, 560*955f2ea3SAbel Vesa .hid_width = 5, 561*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 562*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 563*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 564*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s2_clk_src", 565*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 566*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 567*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 568*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 569*955f2ea3SAbel Vesa }, 570*955f2ea3SAbel Vesa }; 571*955f2ea3SAbel Vesa 572*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = { 573*955f2ea3SAbel Vesa .cmd_rcgr = 0x1705c, 574*955f2ea3SAbel Vesa .mnd_width = 0, 575*955f2ea3SAbel Vesa .hid_width = 5, 576*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 577*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 578*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 579*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s3_clk_src", 580*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 581*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 582*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 583*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 584*955f2ea3SAbel Vesa }, 585*955f2ea3SAbel Vesa }; 586*955f2ea3SAbel Vesa 587*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = { 588*955f2ea3SAbel Vesa .cmd_rcgr = 0x17078, 589*955f2ea3SAbel Vesa .mnd_width = 0, 590*955f2ea3SAbel Vesa .hid_width = 5, 591*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 592*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 593*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 594*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s4_clk_src", 595*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 596*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 597*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 598*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 599*955f2ea3SAbel Vesa }, 600*955f2ea3SAbel Vesa }; 601*955f2ea3SAbel Vesa 602*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = { 603*955f2ea3SAbel Vesa .cmd_rcgr = 0x17094, 604*955f2ea3SAbel Vesa .mnd_width = 0, 605*955f2ea3SAbel Vesa .hid_width = 5, 606*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 607*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 608*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 609*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s5_clk_src", 610*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 611*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 612*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 613*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 614*955f2ea3SAbel Vesa }, 615*955f2ea3SAbel Vesa }; 616*955f2ea3SAbel Vesa 617*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = { 618*955f2ea3SAbel Vesa .cmd_rcgr = 0x170b0, 619*955f2ea3SAbel Vesa .mnd_width = 0, 620*955f2ea3SAbel Vesa .hid_width = 5, 621*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 622*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 623*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 624*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s6_clk_src", 625*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 626*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 627*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 628*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 629*955f2ea3SAbel Vesa }, 630*955f2ea3SAbel Vesa }; 631*955f2ea3SAbel Vesa 632*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = { 633*955f2ea3SAbel Vesa .cmd_rcgr = 0x170cc, 634*955f2ea3SAbel Vesa .mnd_width = 0, 635*955f2ea3SAbel Vesa .hid_width = 5, 636*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 637*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 638*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 639*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s7_clk_src", 640*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 641*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 642*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 643*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 644*955f2ea3SAbel Vesa }, 645*955f2ea3SAbel Vesa }; 646*955f2ea3SAbel Vesa 647*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = { 648*955f2ea3SAbel Vesa .cmd_rcgr = 0x170e8, 649*955f2ea3SAbel Vesa .mnd_width = 0, 650*955f2ea3SAbel Vesa .hid_width = 5, 651*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 652*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 653*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 654*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s8_clk_src", 655*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 656*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 657*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 658*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 659*955f2ea3SAbel Vesa }, 660*955f2ea3SAbel Vesa }; 661*955f2ea3SAbel Vesa 662*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = { 663*955f2ea3SAbel Vesa .cmd_rcgr = 0x17104, 664*955f2ea3SAbel Vesa .mnd_width = 0, 665*955f2ea3SAbel Vesa .hid_width = 5, 666*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 667*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 668*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 669*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s9_clk_src", 670*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 671*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 672*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 673*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 674*955f2ea3SAbel Vesa }, 675*955f2ea3SAbel Vesa }; 676*955f2ea3SAbel Vesa 677*955f2ea3SAbel Vesa static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = { 678*955f2ea3SAbel Vesa F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 679*955f2ea3SAbel Vesa F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 680*955f2ea3SAbel Vesa F(19200000, P_BI_TCXO, 1, 0, 0), 681*955f2ea3SAbel Vesa F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 682*955f2ea3SAbel Vesa F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 683*955f2ea3SAbel Vesa F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 684*955f2ea3SAbel Vesa F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 685*955f2ea3SAbel Vesa F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 686*955f2ea3SAbel Vesa F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 687*955f2ea3SAbel Vesa F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 688*955f2ea3SAbel Vesa F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 689*955f2ea3SAbel Vesa F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 690*955f2ea3SAbel Vesa F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 691*955f2ea3SAbel Vesa F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 692*955f2ea3SAbel Vesa F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 693*955f2ea3SAbel Vesa F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 694*955f2ea3SAbel Vesa { } 695*955f2ea3SAbel Vesa }; 696*955f2ea3SAbel Vesa 697*955f2ea3SAbel Vesa static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 698*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap1_s0_clk_src", 699*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 700*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 701*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 702*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 703*955f2ea3SAbel Vesa }; 704*955f2ea3SAbel Vesa 705*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 706*955f2ea3SAbel Vesa .cmd_rcgr = 0x18010, 707*955f2ea3SAbel Vesa .mnd_width = 16, 708*955f2ea3SAbel Vesa .hid_width = 5, 709*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 710*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 711*955f2ea3SAbel Vesa .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 712*955f2ea3SAbel Vesa }; 713*955f2ea3SAbel Vesa 714*955f2ea3SAbel Vesa static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 715*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap1_s1_clk_src", 716*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 717*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 718*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 719*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 720*955f2ea3SAbel Vesa }; 721*955f2ea3SAbel Vesa 722*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 723*955f2ea3SAbel Vesa .cmd_rcgr = 0x18148, 724*955f2ea3SAbel Vesa .mnd_width = 16, 725*955f2ea3SAbel Vesa .hid_width = 5, 726*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 727*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 728*955f2ea3SAbel Vesa .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 729*955f2ea3SAbel Vesa }; 730*955f2ea3SAbel Vesa 731*955f2ea3SAbel Vesa static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s2_clk_src[] = { 732*955f2ea3SAbel Vesa F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 733*955f2ea3SAbel Vesa F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 734*955f2ea3SAbel Vesa F(19200000, P_BI_TCXO, 1, 0, 0), 735*955f2ea3SAbel Vesa F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 736*955f2ea3SAbel Vesa F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 737*955f2ea3SAbel Vesa F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 738*955f2ea3SAbel Vesa F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 739*955f2ea3SAbel Vesa F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 740*955f2ea3SAbel Vesa F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 741*955f2ea3SAbel Vesa F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 742*955f2ea3SAbel Vesa F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 743*955f2ea3SAbel Vesa F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 744*955f2ea3SAbel Vesa { } 745*955f2ea3SAbel Vesa }; 746*955f2ea3SAbel Vesa 747*955f2ea3SAbel Vesa static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 748*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap1_s2_clk_src", 749*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 750*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 751*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 752*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 753*955f2ea3SAbel Vesa }; 754*955f2ea3SAbel Vesa 755*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 756*955f2ea3SAbel Vesa .cmd_rcgr = 0x18280, 757*955f2ea3SAbel Vesa .mnd_width = 16, 758*955f2ea3SAbel Vesa .hid_width = 5, 759*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 760*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 761*955f2ea3SAbel Vesa .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 762*955f2ea3SAbel Vesa }; 763*955f2ea3SAbel Vesa 764*955f2ea3SAbel Vesa static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 765*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap1_s3_clk_src", 766*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 767*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 768*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 769*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 770*955f2ea3SAbel Vesa }; 771*955f2ea3SAbel Vesa 772*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 773*955f2ea3SAbel Vesa .cmd_rcgr = 0x183b8, 774*955f2ea3SAbel Vesa .mnd_width = 16, 775*955f2ea3SAbel Vesa .hid_width = 5, 776*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 777*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 778*955f2ea3SAbel Vesa .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 779*955f2ea3SAbel Vesa }; 780*955f2ea3SAbel Vesa 781*955f2ea3SAbel Vesa static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 782*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap1_s4_clk_src", 783*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 784*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 785*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 786*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 787*955f2ea3SAbel Vesa }; 788*955f2ea3SAbel Vesa 789*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 790*955f2ea3SAbel Vesa .cmd_rcgr = 0x184f0, 791*955f2ea3SAbel Vesa .mnd_width = 16, 792*955f2ea3SAbel Vesa .hid_width = 5, 793*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 794*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 795*955f2ea3SAbel Vesa .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 796*955f2ea3SAbel Vesa }; 797*955f2ea3SAbel Vesa 798*955f2ea3SAbel Vesa static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 799*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap1_s5_clk_src", 800*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 801*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 802*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 803*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 804*955f2ea3SAbel Vesa }; 805*955f2ea3SAbel Vesa 806*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 807*955f2ea3SAbel Vesa .cmd_rcgr = 0x18628, 808*955f2ea3SAbel Vesa .mnd_width = 16, 809*955f2ea3SAbel Vesa .hid_width = 5, 810*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 811*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 812*955f2ea3SAbel Vesa .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 813*955f2ea3SAbel Vesa }; 814*955f2ea3SAbel Vesa 815*955f2ea3SAbel Vesa static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 816*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap1_s6_clk_src", 817*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 818*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 819*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 820*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 821*955f2ea3SAbel Vesa }; 822*955f2ea3SAbel Vesa 823*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 824*955f2ea3SAbel Vesa .cmd_rcgr = 0x18760, 825*955f2ea3SAbel Vesa .mnd_width = 16, 826*955f2ea3SAbel Vesa .hid_width = 5, 827*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 828*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 829*955f2ea3SAbel Vesa .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 830*955f2ea3SAbel Vesa }; 831*955f2ea3SAbel Vesa 832*955f2ea3SAbel Vesa static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 833*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap1_s7_clk_src", 834*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 835*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 836*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 837*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 838*955f2ea3SAbel Vesa }; 839*955f2ea3SAbel Vesa 840*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 841*955f2ea3SAbel Vesa .cmd_rcgr = 0x18898, 842*955f2ea3SAbel Vesa .mnd_width = 16, 843*955f2ea3SAbel Vesa .hid_width = 5, 844*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 845*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 846*955f2ea3SAbel Vesa .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 847*955f2ea3SAbel Vesa }; 848*955f2ea3SAbel Vesa 849*955f2ea3SAbel Vesa static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 850*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap2_s0_clk_src", 851*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 852*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 853*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 854*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 855*955f2ea3SAbel Vesa }; 856*955f2ea3SAbel Vesa 857*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 858*955f2ea3SAbel Vesa .cmd_rcgr = 0x1e010, 859*955f2ea3SAbel Vesa .mnd_width = 16, 860*955f2ea3SAbel Vesa .hid_width = 5, 861*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 862*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 863*955f2ea3SAbel Vesa .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 864*955f2ea3SAbel Vesa }; 865*955f2ea3SAbel Vesa 866*955f2ea3SAbel Vesa static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 867*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap2_s1_clk_src", 868*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 869*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 870*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 871*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 872*955f2ea3SAbel Vesa }; 873*955f2ea3SAbel Vesa 874*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 875*955f2ea3SAbel Vesa .cmd_rcgr = 0x1e148, 876*955f2ea3SAbel Vesa .mnd_width = 16, 877*955f2ea3SAbel Vesa .hid_width = 5, 878*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 879*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 880*955f2ea3SAbel Vesa .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 881*955f2ea3SAbel Vesa }; 882*955f2ea3SAbel Vesa 883*955f2ea3SAbel Vesa static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 884*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap2_s2_clk_src", 885*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 886*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 887*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 888*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 889*955f2ea3SAbel Vesa }; 890*955f2ea3SAbel Vesa 891*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 892*955f2ea3SAbel Vesa .cmd_rcgr = 0x1e280, 893*955f2ea3SAbel Vesa .mnd_width = 16, 894*955f2ea3SAbel Vesa .hid_width = 5, 895*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 896*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 897*955f2ea3SAbel Vesa .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 898*955f2ea3SAbel Vesa }; 899*955f2ea3SAbel Vesa 900*955f2ea3SAbel Vesa static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 901*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap2_s3_clk_src", 902*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 903*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 904*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 905*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 906*955f2ea3SAbel Vesa }; 907*955f2ea3SAbel Vesa 908*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 909*955f2ea3SAbel Vesa .cmd_rcgr = 0x1e3b8, 910*955f2ea3SAbel Vesa .mnd_width = 16, 911*955f2ea3SAbel Vesa .hid_width = 5, 912*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 913*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 914*955f2ea3SAbel Vesa .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 915*955f2ea3SAbel Vesa }; 916*955f2ea3SAbel Vesa 917*955f2ea3SAbel Vesa static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 918*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap2_s4_clk_src", 919*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 920*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 921*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 922*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 923*955f2ea3SAbel Vesa }; 924*955f2ea3SAbel Vesa 925*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 926*955f2ea3SAbel Vesa .cmd_rcgr = 0x1e4f0, 927*955f2ea3SAbel Vesa .mnd_width = 16, 928*955f2ea3SAbel Vesa .hid_width = 5, 929*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 930*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 931*955f2ea3SAbel Vesa .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 932*955f2ea3SAbel Vesa }; 933*955f2ea3SAbel Vesa 934*955f2ea3SAbel Vesa static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 935*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap2_s5_clk_src", 936*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 937*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 938*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 939*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 940*955f2ea3SAbel Vesa }; 941*955f2ea3SAbel Vesa 942*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 943*955f2ea3SAbel Vesa .cmd_rcgr = 0x1e628, 944*955f2ea3SAbel Vesa .mnd_width = 16, 945*955f2ea3SAbel Vesa .hid_width = 5, 946*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 947*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 948*955f2ea3SAbel Vesa .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 949*955f2ea3SAbel Vesa }; 950*955f2ea3SAbel Vesa 951*955f2ea3SAbel Vesa static const struct freq_tbl ftbl_gcc_qupv3_wrap2_s6_clk_src[] = { 952*955f2ea3SAbel Vesa F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 953*955f2ea3SAbel Vesa F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 954*955f2ea3SAbel Vesa F(19200000, P_BI_TCXO, 1, 0, 0), 955*955f2ea3SAbel Vesa F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 956*955f2ea3SAbel Vesa F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 957*955f2ea3SAbel Vesa F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 958*955f2ea3SAbel Vesa F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 959*955f2ea3SAbel Vesa F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 960*955f2ea3SAbel Vesa F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 961*955f2ea3SAbel Vesa F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 962*955f2ea3SAbel Vesa F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 963*955f2ea3SAbel Vesa F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 964*955f2ea3SAbel Vesa F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 965*955f2ea3SAbel Vesa F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 966*955f2ea3SAbel Vesa F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 967*955f2ea3SAbel Vesa F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 968*955f2ea3SAbel Vesa F(125000000, P_GCC_GPLL0_OUT_MAIN, 1, 5, 24), 969*955f2ea3SAbel Vesa { } 970*955f2ea3SAbel Vesa }; 971*955f2ea3SAbel Vesa 972*955f2ea3SAbel Vesa static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { 973*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap2_s6_clk_src", 974*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_8, 975*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_8), 976*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 977*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 978*955f2ea3SAbel Vesa }; 979*955f2ea3SAbel Vesa 980*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { 981*955f2ea3SAbel Vesa .cmd_rcgr = 0x1e760, 982*955f2ea3SAbel Vesa .mnd_width = 16, 983*955f2ea3SAbel Vesa .hid_width = 5, 984*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_8, 985*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_qupv3_wrap2_s6_clk_src, 986*955f2ea3SAbel Vesa .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init, 987*955f2ea3SAbel Vesa }; 988*955f2ea3SAbel Vesa 989*955f2ea3SAbel Vesa static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = { 990*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap2_s7_clk_src", 991*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 992*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 993*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 994*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 995*955f2ea3SAbel Vesa }; 996*955f2ea3SAbel Vesa 997*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = { 998*955f2ea3SAbel Vesa .cmd_rcgr = 0x1e898, 999*955f2ea3SAbel Vesa .mnd_width = 16, 1000*955f2ea3SAbel Vesa .hid_width = 5, 1001*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 1002*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src, 1003*955f2ea3SAbel Vesa .clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init, 1004*955f2ea3SAbel Vesa }; 1005*955f2ea3SAbel Vesa 1006*955f2ea3SAbel Vesa static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1007*955f2ea3SAbel Vesa F(400000, P_BI_TCXO, 12, 1, 4), 1008*955f2ea3SAbel Vesa F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1009*955f2ea3SAbel Vesa F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0), 1010*955f2ea3SAbel Vesa F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 1011*955f2ea3SAbel Vesa F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1012*955f2ea3SAbel Vesa F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 1013*955f2ea3SAbel Vesa { } 1014*955f2ea3SAbel Vesa }; 1015*955f2ea3SAbel Vesa 1016*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1017*955f2ea3SAbel Vesa .cmd_rcgr = 0x14018, 1018*955f2ea3SAbel Vesa .mnd_width = 8, 1019*955f2ea3SAbel Vesa .hid_width = 5, 1020*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_9, 1021*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1022*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 1023*955f2ea3SAbel Vesa .name = "gcc_sdcc2_apps_clk_src", 1024*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_9, 1025*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_9), 1026*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1027*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 1028*955f2ea3SAbel Vesa }, 1029*955f2ea3SAbel Vesa }; 1030*955f2ea3SAbel Vesa 1031*955f2ea3SAbel Vesa static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 1032*955f2ea3SAbel Vesa F(400000, P_BI_TCXO, 12, 1, 4), 1033*955f2ea3SAbel Vesa F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1034*955f2ea3SAbel Vesa F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0), 1035*955f2ea3SAbel Vesa F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1036*955f2ea3SAbel Vesa { } 1037*955f2ea3SAbel Vesa }; 1038*955f2ea3SAbel Vesa 1039*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 1040*955f2ea3SAbel Vesa .cmd_rcgr = 0x16018, 1041*955f2ea3SAbel Vesa .mnd_width = 8, 1042*955f2ea3SAbel Vesa .hid_width = 5, 1043*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 1044*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 1045*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 1046*955f2ea3SAbel Vesa .name = "gcc_sdcc4_apps_clk_src", 1047*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 1048*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1049*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1050*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 1051*955f2ea3SAbel Vesa }, 1052*955f2ea3SAbel Vesa }; 1053*955f2ea3SAbel Vesa 1054*955f2ea3SAbel Vesa static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1055*955f2ea3SAbel Vesa F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1056*955f2ea3SAbel Vesa F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1057*955f2ea3SAbel Vesa F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 1058*955f2ea3SAbel Vesa F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 1059*955f2ea3SAbel Vesa { } 1060*955f2ea3SAbel Vesa }; 1061*955f2ea3SAbel Vesa 1062*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1063*955f2ea3SAbel Vesa .cmd_rcgr = 0x77030, 1064*955f2ea3SAbel Vesa .mnd_width = 8, 1065*955f2ea3SAbel Vesa .hid_width = 5, 1066*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 1067*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1068*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 1069*955f2ea3SAbel Vesa .name = "gcc_ufs_phy_axi_clk_src", 1070*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 1071*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1072*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1073*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 1074*955f2ea3SAbel Vesa }, 1075*955f2ea3SAbel Vesa }; 1076*955f2ea3SAbel Vesa 1077*955f2ea3SAbel Vesa static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1078*955f2ea3SAbel Vesa F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1079*955f2ea3SAbel Vesa F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 1080*955f2ea3SAbel Vesa F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1081*955f2ea3SAbel Vesa { } 1082*955f2ea3SAbel Vesa }; 1083*955f2ea3SAbel Vesa 1084*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1085*955f2ea3SAbel Vesa .cmd_rcgr = 0x77080, 1086*955f2ea3SAbel Vesa .mnd_width = 0, 1087*955f2ea3SAbel Vesa .hid_width = 5, 1088*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_3, 1089*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1090*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 1091*955f2ea3SAbel Vesa .name = "gcc_ufs_phy_ice_core_clk_src", 1092*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_3, 1093*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1094*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1095*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 1096*955f2ea3SAbel Vesa }, 1097*955f2ea3SAbel Vesa }; 1098*955f2ea3SAbel Vesa 1099*955f2ea3SAbel Vesa static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1100*955f2ea3SAbel Vesa F(9600000, P_BI_TCXO, 2, 0, 0), 1101*955f2ea3SAbel Vesa F(19200000, P_BI_TCXO, 1, 0, 0), 1102*955f2ea3SAbel Vesa { } 1103*955f2ea3SAbel Vesa }; 1104*955f2ea3SAbel Vesa 1105*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1106*955f2ea3SAbel Vesa .cmd_rcgr = 0x770b4, 1107*955f2ea3SAbel Vesa .mnd_width = 0, 1108*955f2ea3SAbel Vesa .hid_width = 5, 1109*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_4, 1110*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1111*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 1112*955f2ea3SAbel Vesa .name = "gcc_ufs_phy_phy_aux_clk_src", 1113*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_4, 1114*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1115*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1116*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 1117*955f2ea3SAbel Vesa }, 1118*955f2ea3SAbel Vesa }; 1119*955f2ea3SAbel Vesa 1120*955f2ea3SAbel Vesa static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 1121*955f2ea3SAbel Vesa F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1122*955f2ea3SAbel Vesa F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 1123*955f2ea3SAbel Vesa F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 1124*955f2ea3SAbel Vesa { } 1125*955f2ea3SAbel Vesa }; 1126*955f2ea3SAbel Vesa 1127*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1128*955f2ea3SAbel Vesa .cmd_rcgr = 0x77098, 1129*955f2ea3SAbel Vesa .mnd_width = 0, 1130*955f2ea3SAbel Vesa .hid_width = 5, 1131*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 1132*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 1133*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 1134*955f2ea3SAbel Vesa .name = "gcc_ufs_phy_unipro_core_clk_src", 1135*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 1136*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1137*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1138*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 1139*955f2ea3SAbel Vesa }, 1140*955f2ea3SAbel Vesa }; 1141*955f2ea3SAbel Vesa 1142*955f2ea3SAbel Vesa static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1143*955f2ea3SAbel Vesa F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 1144*955f2ea3SAbel Vesa F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1145*955f2ea3SAbel Vesa F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1146*955f2ea3SAbel Vesa F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1147*955f2ea3SAbel Vesa { } 1148*955f2ea3SAbel Vesa }; 1149*955f2ea3SAbel Vesa 1150*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1151*955f2ea3SAbel Vesa .cmd_rcgr = 0x3902c, 1152*955f2ea3SAbel Vesa .mnd_width = 8, 1153*955f2ea3SAbel Vesa .hid_width = 5, 1154*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 1155*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1156*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 1157*955f2ea3SAbel Vesa .name = "gcc_usb30_prim_master_clk_src", 1158*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 1159*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1160*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1161*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 1162*955f2ea3SAbel Vesa }, 1163*955f2ea3SAbel Vesa }; 1164*955f2ea3SAbel Vesa 1165*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1166*955f2ea3SAbel Vesa .cmd_rcgr = 0x39044, 1167*955f2ea3SAbel Vesa .mnd_width = 0, 1168*955f2ea3SAbel Vesa .hid_width = 5, 1169*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_0, 1170*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1171*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 1172*955f2ea3SAbel Vesa .name = "gcc_usb30_prim_mock_utmi_clk_src", 1173*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_0, 1174*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1175*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1176*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 1177*955f2ea3SAbel Vesa }, 1178*955f2ea3SAbel Vesa }; 1179*955f2ea3SAbel Vesa 1180*955f2ea3SAbel Vesa static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1181*955f2ea3SAbel Vesa .cmd_rcgr = 0x39070, 1182*955f2ea3SAbel Vesa .mnd_width = 0, 1183*955f2ea3SAbel Vesa .hid_width = 5, 1184*955f2ea3SAbel Vesa .parent_map = gcc_parent_map_2, 1185*955f2ea3SAbel Vesa .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1186*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data){ 1187*955f2ea3SAbel Vesa .name = "gcc_usb3_prim_phy_aux_clk_src", 1188*955f2ea3SAbel Vesa .parent_data = gcc_parent_data_2, 1189*955f2ea3SAbel Vesa .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1190*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1191*955f2ea3SAbel Vesa .ops = &clk_rcg2_ops, 1192*955f2ea3SAbel Vesa }, 1193*955f2ea3SAbel Vesa }; 1194*955f2ea3SAbel Vesa 1195*955f2ea3SAbel Vesa static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1196*955f2ea3SAbel Vesa .reg = 0x3905c, 1197*955f2ea3SAbel Vesa .shift = 0, 1198*955f2ea3SAbel Vesa .width = 4, 1199*955f2ea3SAbel Vesa .clkr.hw.init = &(struct clk_init_data) { 1200*955f2ea3SAbel Vesa .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1201*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 1202*955f2ea3SAbel Vesa .hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1203*955f2ea3SAbel Vesa }, 1204*955f2ea3SAbel Vesa .num_parents = 1, 1205*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1206*955f2ea3SAbel Vesa .ops = &clk_regmap_div_ro_ops, 1207*955f2ea3SAbel Vesa }, 1208*955f2ea3SAbel Vesa }; 1209*955f2ea3SAbel Vesa 1210*955f2ea3SAbel Vesa static struct clk_branch gcc_aggre_noc_pcie_axi_clk = { 1211*955f2ea3SAbel Vesa .halt_reg = 0x1003c, 1212*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_SKIP, 1213*955f2ea3SAbel Vesa .hwcg_reg = 0x1003c, 1214*955f2ea3SAbel Vesa .hwcg_bit = 1, 1215*955f2ea3SAbel Vesa .clkr = { 1216*955f2ea3SAbel Vesa .enable_reg = 0x52000, 1217*955f2ea3SAbel Vesa .enable_mask = BIT(12), 1218*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1219*955f2ea3SAbel Vesa .name = "gcc_aggre_noc_pcie_axi_clk", 1220*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1221*955f2ea3SAbel Vesa }, 1222*955f2ea3SAbel Vesa }, 1223*955f2ea3SAbel Vesa }; 1224*955f2ea3SAbel Vesa 1225*955f2ea3SAbel Vesa static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1226*955f2ea3SAbel Vesa .halt_reg = 0x770e4, 1227*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1228*955f2ea3SAbel Vesa .hwcg_reg = 0x770e4, 1229*955f2ea3SAbel Vesa .hwcg_bit = 1, 1230*955f2ea3SAbel Vesa .clkr = { 1231*955f2ea3SAbel Vesa .enable_reg = 0x770e4, 1232*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1233*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1234*955f2ea3SAbel Vesa .name = "gcc_aggre_ufs_phy_axi_clk", 1235*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 1236*955f2ea3SAbel Vesa .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 1237*955f2ea3SAbel Vesa }, 1238*955f2ea3SAbel Vesa .num_parents = 1, 1239*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1240*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1241*955f2ea3SAbel Vesa }, 1242*955f2ea3SAbel Vesa }, 1243*955f2ea3SAbel Vesa }; 1244*955f2ea3SAbel Vesa 1245*955f2ea3SAbel Vesa static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { 1246*955f2ea3SAbel Vesa .halt_reg = 0x770e4, 1247*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1248*955f2ea3SAbel Vesa .hwcg_reg = 0x770e4, 1249*955f2ea3SAbel Vesa .hwcg_bit = 1, 1250*955f2ea3SAbel Vesa .clkr = { 1251*955f2ea3SAbel Vesa .enable_reg = 0x770e4, 1252*955f2ea3SAbel Vesa .enable_mask = BIT(1), 1253*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1254*955f2ea3SAbel Vesa .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", 1255*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 1256*955f2ea3SAbel Vesa .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 1257*955f2ea3SAbel Vesa }, 1258*955f2ea3SAbel Vesa .num_parents = 1, 1259*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1260*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1261*955f2ea3SAbel Vesa }, 1262*955f2ea3SAbel Vesa }, 1263*955f2ea3SAbel Vesa }; 1264*955f2ea3SAbel Vesa 1265*955f2ea3SAbel Vesa static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1266*955f2ea3SAbel Vesa .halt_reg = 0x3908c, 1267*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1268*955f2ea3SAbel Vesa .hwcg_reg = 0x3908c, 1269*955f2ea3SAbel Vesa .hwcg_bit = 1, 1270*955f2ea3SAbel Vesa .clkr = { 1271*955f2ea3SAbel Vesa .enable_reg = 0x3908c, 1272*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1273*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1274*955f2ea3SAbel Vesa .name = "gcc_aggre_usb3_prim_axi_clk", 1275*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 1276*955f2ea3SAbel Vesa .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 1277*955f2ea3SAbel Vesa }, 1278*955f2ea3SAbel Vesa .num_parents = 1, 1279*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1280*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1281*955f2ea3SAbel Vesa }, 1282*955f2ea3SAbel Vesa }, 1283*955f2ea3SAbel Vesa }; 1284*955f2ea3SAbel Vesa 1285*955f2ea3SAbel Vesa static struct clk_branch gcc_boot_rom_ahb_clk = { 1286*955f2ea3SAbel Vesa .halt_reg = 0x38004, 1287*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1288*955f2ea3SAbel Vesa .hwcg_reg = 0x38004, 1289*955f2ea3SAbel Vesa .hwcg_bit = 1, 1290*955f2ea3SAbel Vesa .clkr = { 1291*955f2ea3SAbel Vesa .enable_reg = 0x52000, 1292*955f2ea3SAbel Vesa .enable_mask = BIT(10), 1293*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1294*955f2ea3SAbel Vesa .name = "gcc_boot_rom_ahb_clk", 1295*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1296*955f2ea3SAbel Vesa }, 1297*955f2ea3SAbel Vesa }, 1298*955f2ea3SAbel Vesa }; 1299*955f2ea3SAbel Vesa 1300*955f2ea3SAbel Vesa static struct clk_branch gcc_camera_hf_axi_clk = { 1301*955f2ea3SAbel Vesa .halt_reg = 0x26010, 1302*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_SKIP, 1303*955f2ea3SAbel Vesa .hwcg_reg = 0x26010, 1304*955f2ea3SAbel Vesa .hwcg_bit = 1, 1305*955f2ea3SAbel Vesa .clkr = { 1306*955f2ea3SAbel Vesa .enable_reg = 0x26010, 1307*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1308*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1309*955f2ea3SAbel Vesa .name = "gcc_camera_hf_axi_clk", 1310*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1311*955f2ea3SAbel Vesa }, 1312*955f2ea3SAbel Vesa }, 1313*955f2ea3SAbel Vesa }; 1314*955f2ea3SAbel Vesa 1315*955f2ea3SAbel Vesa static struct clk_branch gcc_camera_sf_axi_clk = { 1316*955f2ea3SAbel Vesa .halt_reg = 0x2601c, 1317*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_SKIP, 1318*955f2ea3SAbel Vesa .hwcg_reg = 0x2601c, 1319*955f2ea3SAbel Vesa .hwcg_bit = 1, 1320*955f2ea3SAbel Vesa .clkr = { 1321*955f2ea3SAbel Vesa .enable_reg = 0x2601c, 1322*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1323*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1324*955f2ea3SAbel Vesa .name = "gcc_camera_sf_axi_clk", 1325*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1326*955f2ea3SAbel Vesa }, 1327*955f2ea3SAbel Vesa }, 1328*955f2ea3SAbel Vesa }; 1329*955f2ea3SAbel Vesa 1330*955f2ea3SAbel Vesa static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = { 1331*955f2ea3SAbel Vesa .halt_reg = 0x10028, 1332*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_SKIP, 1333*955f2ea3SAbel Vesa .hwcg_reg = 0x10028, 1334*955f2ea3SAbel Vesa .hwcg_bit = 1, 1335*955f2ea3SAbel Vesa .clkr = { 1336*955f2ea3SAbel Vesa .enable_reg = 0x52000, 1337*955f2ea3SAbel Vesa .enable_mask = BIT(20), 1338*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1339*955f2ea3SAbel Vesa .name = "gcc_cfg_noc_pcie_anoc_ahb_clk", 1340*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1341*955f2ea3SAbel Vesa }, 1342*955f2ea3SAbel Vesa }, 1343*955f2ea3SAbel Vesa }; 1344*955f2ea3SAbel Vesa 1345*955f2ea3SAbel Vesa static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1346*955f2ea3SAbel Vesa .halt_reg = 0x39088, 1347*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1348*955f2ea3SAbel Vesa .hwcg_reg = 0x39088, 1349*955f2ea3SAbel Vesa .hwcg_bit = 1, 1350*955f2ea3SAbel Vesa .clkr = { 1351*955f2ea3SAbel Vesa .enable_reg = 0x39088, 1352*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1353*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1354*955f2ea3SAbel Vesa .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1355*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 1356*955f2ea3SAbel Vesa .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 1357*955f2ea3SAbel Vesa }, 1358*955f2ea3SAbel Vesa .num_parents = 1, 1359*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1360*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1361*955f2ea3SAbel Vesa }, 1362*955f2ea3SAbel Vesa }, 1363*955f2ea3SAbel Vesa }; 1364*955f2ea3SAbel Vesa 1365*955f2ea3SAbel Vesa static struct clk_branch gcc_cnoc_pcie_sf_axi_clk = { 1366*955f2ea3SAbel Vesa .halt_reg = 0x10030, 1367*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1368*955f2ea3SAbel Vesa .hwcg_reg = 0x10030, 1369*955f2ea3SAbel Vesa .hwcg_bit = 1, 1370*955f2ea3SAbel Vesa .clkr = { 1371*955f2ea3SAbel Vesa .enable_reg = 0x52008, 1372*955f2ea3SAbel Vesa .enable_mask = BIT(6), 1373*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1374*955f2ea3SAbel Vesa .name = "gcc_cnoc_pcie_sf_axi_clk", 1375*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1376*955f2ea3SAbel Vesa }, 1377*955f2ea3SAbel Vesa }, 1378*955f2ea3SAbel Vesa }; 1379*955f2ea3SAbel Vesa 1380*955f2ea3SAbel Vesa static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1381*955f2ea3SAbel Vesa .halt_reg = 0x71154, 1382*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_SKIP, 1383*955f2ea3SAbel Vesa .hwcg_reg = 0x71154, 1384*955f2ea3SAbel Vesa .hwcg_bit = 1, 1385*955f2ea3SAbel Vesa .clkr = { 1386*955f2ea3SAbel Vesa .enable_reg = 0x71154, 1387*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1388*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1389*955f2ea3SAbel Vesa .name = "gcc_ddrss_gpu_axi_clk", 1390*955f2ea3SAbel Vesa .ops = &clk_branch2_aon_ops, 1391*955f2ea3SAbel Vesa }, 1392*955f2ea3SAbel Vesa }, 1393*955f2ea3SAbel Vesa }; 1394*955f2ea3SAbel Vesa 1395*955f2ea3SAbel Vesa static struct clk_branch gcc_ddrss_pcie_sf_qtb_clk = { 1396*955f2ea3SAbel Vesa .halt_reg = 0x1004c, 1397*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_SKIP, 1398*955f2ea3SAbel Vesa .hwcg_reg = 0x1004c, 1399*955f2ea3SAbel Vesa .hwcg_bit = 1, 1400*955f2ea3SAbel Vesa .clkr = { 1401*955f2ea3SAbel Vesa .enable_reg = 0x52000, 1402*955f2ea3SAbel Vesa .enable_mask = BIT(19), 1403*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1404*955f2ea3SAbel Vesa .name = "gcc_ddrss_pcie_sf_qtb_clk", 1405*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1406*955f2ea3SAbel Vesa }, 1407*955f2ea3SAbel Vesa }, 1408*955f2ea3SAbel Vesa }; 1409*955f2ea3SAbel Vesa 1410*955f2ea3SAbel Vesa static struct clk_branch gcc_disp_hf_axi_clk = { 1411*955f2ea3SAbel Vesa .halt_reg = 0x2700c, 1412*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_SKIP, 1413*955f2ea3SAbel Vesa .hwcg_reg = 0x2700c, 1414*955f2ea3SAbel Vesa .hwcg_bit = 1, 1415*955f2ea3SAbel Vesa .clkr = { 1416*955f2ea3SAbel Vesa .enable_reg = 0x2700c, 1417*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1418*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1419*955f2ea3SAbel Vesa .name = "gcc_disp_hf_axi_clk", 1420*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1421*955f2ea3SAbel Vesa }, 1422*955f2ea3SAbel Vesa }, 1423*955f2ea3SAbel Vesa }; 1424*955f2ea3SAbel Vesa 1425*955f2ea3SAbel Vesa static struct clk_branch gcc_gp1_clk = { 1426*955f2ea3SAbel Vesa .halt_reg = 0x64000, 1427*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT, 1428*955f2ea3SAbel Vesa .clkr = { 1429*955f2ea3SAbel Vesa .enable_reg = 0x64000, 1430*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1431*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1432*955f2ea3SAbel Vesa .name = "gcc_gp1_clk", 1433*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 1434*955f2ea3SAbel Vesa .hw = &gcc_gp1_clk_src.clkr.hw, 1435*955f2ea3SAbel Vesa }, 1436*955f2ea3SAbel Vesa .num_parents = 1, 1437*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1438*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1439*955f2ea3SAbel Vesa }, 1440*955f2ea3SAbel Vesa }, 1441*955f2ea3SAbel Vesa }; 1442*955f2ea3SAbel Vesa 1443*955f2ea3SAbel Vesa static struct clk_branch gcc_gp2_clk = { 1444*955f2ea3SAbel Vesa .halt_reg = 0x65000, 1445*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT, 1446*955f2ea3SAbel Vesa .clkr = { 1447*955f2ea3SAbel Vesa .enable_reg = 0x65000, 1448*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1449*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1450*955f2ea3SAbel Vesa .name = "gcc_gp2_clk", 1451*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 1452*955f2ea3SAbel Vesa .hw = &gcc_gp2_clk_src.clkr.hw, 1453*955f2ea3SAbel Vesa }, 1454*955f2ea3SAbel Vesa .num_parents = 1, 1455*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1456*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1457*955f2ea3SAbel Vesa }, 1458*955f2ea3SAbel Vesa }, 1459*955f2ea3SAbel Vesa }; 1460*955f2ea3SAbel Vesa 1461*955f2ea3SAbel Vesa static struct clk_branch gcc_gp3_clk = { 1462*955f2ea3SAbel Vesa .halt_reg = 0x66000, 1463*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT, 1464*955f2ea3SAbel Vesa .clkr = { 1465*955f2ea3SAbel Vesa .enable_reg = 0x66000, 1466*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1467*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1468*955f2ea3SAbel Vesa .name = "gcc_gp3_clk", 1469*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 1470*955f2ea3SAbel Vesa .hw = &gcc_gp3_clk_src.clkr.hw, 1471*955f2ea3SAbel Vesa }, 1472*955f2ea3SAbel Vesa .num_parents = 1, 1473*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1474*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1475*955f2ea3SAbel Vesa }, 1476*955f2ea3SAbel Vesa }, 1477*955f2ea3SAbel Vesa }; 1478*955f2ea3SAbel Vesa 1479*955f2ea3SAbel Vesa static struct clk_branch gcc_gpu_gpll0_clk_src = { 1480*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_DELAY, 1481*955f2ea3SAbel Vesa .clkr = { 1482*955f2ea3SAbel Vesa .enable_reg = 0x52000, 1483*955f2ea3SAbel Vesa .enable_mask = BIT(15), 1484*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1485*955f2ea3SAbel Vesa .name = "gcc_gpu_gpll0_clk_src", 1486*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 1487*955f2ea3SAbel Vesa .hw = &gcc_gpll0.clkr.hw, 1488*955f2ea3SAbel Vesa }, 1489*955f2ea3SAbel Vesa .num_parents = 1, 1490*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1491*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1492*955f2ea3SAbel Vesa }, 1493*955f2ea3SAbel Vesa }, 1494*955f2ea3SAbel Vesa }; 1495*955f2ea3SAbel Vesa 1496*955f2ea3SAbel Vesa static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1497*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_DELAY, 1498*955f2ea3SAbel Vesa .clkr = { 1499*955f2ea3SAbel Vesa .enable_reg = 0x52000, 1500*955f2ea3SAbel Vesa .enable_mask = BIT(16), 1501*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1502*955f2ea3SAbel Vesa .name = "gcc_gpu_gpll0_div_clk_src", 1503*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 1504*955f2ea3SAbel Vesa .hw = &gcc_gpll0_out_even.clkr.hw, 1505*955f2ea3SAbel Vesa }, 1506*955f2ea3SAbel Vesa .num_parents = 1, 1507*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1508*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1509*955f2ea3SAbel Vesa }, 1510*955f2ea3SAbel Vesa }, 1511*955f2ea3SAbel Vesa }; 1512*955f2ea3SAbel Vesa 1513*955f2ea3SAbel Vesa static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1514*955f2ea3SAbel Vesa .halt_reg = 0x71010, 1515*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1516*955f2ea3SAbel Vesa .hwcg_reg = 0x71010, 1517*955f2ea3SAbel Vesa .hwcg_bit = 1, 1518*955f2ea3SAbel Vesa .clkr = { 1519*955f2ea3SAbel Vesa .enable_reg = 0x71010, 1520*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1521*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1522*955f2ea3SAbel Vesa .name = "gcc_gpu_memnoc_gfx_clk", 1523*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1524*955f2ea3SAbel Vesa }, 1525*955f2ea3SAbel Vesa }, 1526*955f2ea3SAbel Vesa }; 1527*955f2ea3SAbel Vesa 1528*955f2ea3SAbel Vesa static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1529*955f2ea3SAbel Vesa .halt_reg = 0x71018, 1530*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_DELAY, 1531*955f2ea3SAbel Vesa .clkr = { 1532*955f2ea3SAbel Vesa .enable_reg = 0x71018, 1533*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1534*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1535*955f2ea3SAbel Vesa .name = "gcc_gpu_snoc_dvm_gfx_clk", 1536*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1537*955f2ea3SAbel Vesa }, 1538*955f2ea3SAbel Vesa }, 1539*955f2ea3SAbel Vesa }; 1540*955f2ea3SAbel Vesa 1541*955f2ea3SAbel Vesa static struct clk_branch gcc_pcie_0_aux_clk = { 1542*955f2ea3SAbel Vesa .halt_reg = 0x6b03c, 1543*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1544*955f2ea3SAbel Vesa .clkr = { 1545*955f2ea3SAbel Vesa .enable_reg = 0x52008, 1546*955f2ea3SAbel Vesa .enable_mask = BIT(3), 1547*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1548*955f2ea3SAbel Vesa .name = "gcc_pcie_0_aux_clk", 1549*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 1550*955f2ea3SAbel Vesa .hw = &gcc_pcie_0_aux_clk_src.clkr.hw, 1551*955f2ea3SAbel Vesa }, 1552*955f2ea3SAbel Vesa .num_parents = 1, 1553*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1554*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1555*955f2ea3SAbel Vesa }, 1556*955f2ea3SAbel Vesa }, 1557*955f2ea3SAbel Vesa }; 1558*955f2ea3SAbel Vesa 1559*955f2ea3SAbel Vesa static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1560*955f2ea3SAbel Vesa .halt_reg = 0x6b038, 1561*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1562*955f2ea3SAbel Vesa .hwcg_reg = 0x6b038, 1563*955f2ea3SAbel Vesa .hwcg_bit = 1, 1564*955f2ea3SAbel Vesa .clkr = { 1565*955f2ea3SAbel Vesa .enable_reg = 0x52008, 1566*955f2ea3SAbel Vesa .enable_mask = BIT(2), 1567*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1568*955f2ea3SAbel Vesa .name = "gcc_pcie_0_cfg_ahb_clk", 1569*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1570*955f2ea3SAbel Vesa }, 1571*955f2ea3SAbel Vesa }, 1572*955f2ea3SAbel Vesa }; 1573*955f2ea3SAbel Vesa 1574*955f2ea3SAbel Vesa static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1575*955f2ea3SAbel Vesa .halt_reg = 0x6b02c, 1576*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_SKIP, 1577*955f2ea3SAbel Vesa .hwcg_reg = 0x6b02c, 1578*955f2ea3SAbel Vesa .hwcg_bit = 1, 1579*955f2ea3SAbel Vesa .clkr = { 1580*955f2ea3SAbel Vesa .enable_reg = 0x52008, 1581*955f2ea3SAbel Vesa .enable_mask = BIT(1), 1582*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1583*955f2ea3SAbel Vesa .name = "gcc_pcie_0_mstr_axi_clk", 1584*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1585*955f2ea3SAbel Vesa }, 1586*955f2ea3SAbel Vesa }, 1587*955f2ea3SAbel Vesa }; 1588*955f2ea3SAbel Vesa 1589*955f2ea3SAbel Vesa static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 1590*955f2ea3SAbel Vesa .halt_reg = 0x6b054, 1591*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1592*955f2ea3SAbel Vesa .clkr = { 1593*955f2ea3SAbel Vesa .enable_reg = 0x52000, 1594*955f2ea3SAbel Vesa .enable_mask = BIT(22), 1595*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1596*955f2ea3SAbel Vesa .name = "gcc_pcie_0_phy_rchng_clk", 1597*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 1598*955f2ea3SAbel Vesa .hw = &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1599*955f2ea3SAbel Vesa }, 1600*955f2ea3SAbel Vesa .num_parents = 1, 1601*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1602*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1603*955f2ea3SAbel Vesa }, 1604*955f2ea3SAbel Vesa }, 1605*955f2ea3SAbel Vesa }; 1606*955f2ea3SAbel Vesa 1607*955f2ea3SAbel Vesa static struct clk_branch gcc_pcie_0_pipe_clk = { 1608*955f2ea3SAbel Vesa .halt_reg = 0x6b048, 1609*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_SKIP, 1610*955f2ea3SAbel Vesa .clkr = { 1611*955f2ea3SAbel Vesa .enable_reg = 0x52008, 1612*955f2ea3SAbel Vesa .enable_mask = BIT(4), 1613*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1614*955f2ea3SAbel Vesa .name = "gcc_pcie_0_pipe_clk", 1615*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 1616*955f2ea3SAbel Vesa .hw = &gcc_pcie_0_pipe_clk_src.clkr.hw, 1617*955f2ea3SAbel Vesa }, 1618*955f2ea3SAbel Vesa .num_parents = 1, 1619*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1620*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1621*955f2ea3SAbel Vesa }, 1622*955f2ea3SAbel Vesa }, 1623*955f2ea3SAbel Vesa }; 1624*955f2ea3SAbel Vesa 1625*955f2ea3SAbel Vesa static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1626*955f2ea3SAbel Vesa .halt_reg = 0x6b020, 1627*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1628*955f2ea3SAbel Vesa .hwcg_reg = 0x6b020, 1629*955f2ea3SAbel Vesa .hwcg_bit = 1, 1630*955f2ea3SAbel Vesa .clkr = { 1631*955f2ea3SAbel Vesa .enable_reg = 0x52008, 1632*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1633*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1634*955f2ea3SAbel Vesa .name = "gcc_pcie_0_slv_axi_clk", 1635*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1636*955f2ea3SAbel Vesa }, 1637*955f2ea3SAbel Vesa }, 1638*955f2ea3SAbel Vesa }; 1639*955f2ea3SAbel Vesa 1640*955f2ea3SAbel Vesa static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1641*955f2ea3SAbel Vesa .halt_reg = 0x6b01c, 1642*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1643*955f2ea3SAbel Vesa .clkr = { 1644*955f2ea3SAbel Vesa .enable_reg = 0x52008, 1645*955f2ea3SAbel Vesa .enable_mask = BIT(5), 1646*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1647*955f2ea3SAbel Vesa .name = "gcc_pcie_0_slv_q2a_axi_clk", 1648*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1649*955f2ea3SAbel Vesa }, 1650*955f2ea3SAbel Vesa }, 1651*955f2ea3SAbel Vesa }; 1652*955f2ea3SAbel Vesa 1653*955f2ea3SAbel Vesa static struct clk_branch gcc_pcie_1_aux_clk = { 1654*955f2ea3SAbel Vesa .halt_reg = 0x8d038, 1655*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1656*955f2ea3SAbel Vesa .clkr = { 1657*955f2ea3SAbel Vesa .enable_reg = 0x52000, 1658*955f2ea3SAbel Vesa .enable_mask = BIT(29), 1659*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1660*955f2ea3SAbel Vesa .name = "gcc_pcie_1_aux_clk", 1661*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 1662*955f2ea3SAbel Vesa .hw = &gcc_pcie_1_aux_clk_src.clkr.hw, 1663*955f2ea3SAbel Vesa }, 1664*955f2ea3SAbel Vesa .num_parents = 1, 1665*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1666*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1667*955f2ea3SAbel Vesa }, 1668*955f2ea3SAbel Vesa }, 1669*955f2ea3SAbel Vesa }; 1670*955f2ea3SAbel Vesa 1671*955f2ea3SAbel Vesa static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1672*955f2ea3SAbel Vesa .halt_reg = 0x8d034, 1673*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1674*955f2ea3SAbel Vesa .hwcg_reg = 0x8d034, 1675*955f2ea3SAbel Vesa .hwcg_bit = 1, 1676*955f2ea3SAbel Vesa .clkr = { 1677*955f2ea3SAbel Vesa .enable_reg = 0x52000, 1678*955f2ea3SAbel Vesa .enable_mask = BIT(28), 1679*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1680*955f2ea3SAbel Vesa .name = "gcc_pcie_1_cfg_ahb_clk", 1681*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1682*955f2ea3SAbel Vesa }, 1683*955f2ea3SAbel Vesa }, 1684*955f2ea3SAbel Vesa }; 1685*955f2ea3SAbel Vesa 1686*955f2ea3SAbel Vesa static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1687*955f2ea3SAbel Vesa .halt_reg = 0x8d028, 1688*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_SKIP, 1689*955f2ea3SAbel Vesa .hwcg_reg = 0x8d028, 1690*955f2ea3SAbel Vesa .hwcg_bit = 1, 1691*955f2ea3SAbel Vesa .clkr = { 1692*955f2ea3SAbel Vesa .enable_reg = 0x52000, 1693*955f2ea3SAbel Vesa .enable_mask = BIT(27), 1694*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1695*955f2ea3SAbel Vesa .name = "gcc_pcie_1_mstr_axi_clk", 1696*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1697*955f2ea3SAbel Vesa }, 1698*955f2ea3SAbel Vesa }, 1699*955f2ea3SAbel Vesa }; 1700*955f2ea3SAbel Vesa 1701*955f2ea3SAbel Vesa static struct clk_branch gcc_pcie_1_phy_aux_clk = { 1702*955f2ea3SAbel Vesa .halt_reg = 0x8d044, 1703*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1704*955f2ea3SAbel Vesa .clkr = { 1705*955f2ea3SAbel Vesa .enable_reg = 0x52000, 1706*955f2ea3SAbel Vesa .enable_mask = BIT(24), 1707*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1708*955f2ea3SAbel Vesa .name = "gcc_pcie_1_phy_aux_clk", 1709*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 1710*955f2ea3SAbel Vesa .hw = &gcc_pcie_1_phy_aux_clk_src.clkr.hw, 1711*955f2ea3SAbel Vesa }, 1712*955f2ea3SAbel Vesa .num_parents = 1, 1713*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1714*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1715*955f2ea3SAbel Vesa }, 1716*955f2ea3SAbel Vesa }, 1717*955f2ea3SAbel Vesa }; 1718*955f2ea3SAbel Vesa 1719*955f2ea3SAbel Vesa static struct clk_branch gcc_pcie_1_phy_rchng_clk = { 1720*955f2ea3SAbel Vesa .halt_reg = 0x8d05c, 1721*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1722*955f2ea3SAbel Vesa .clkr = { 1723*955f2ea3SAbel Vesa .enable_reg = 0x52000, 1724*955f2ea3SAbel Vesa .enable_mask = BIT(23), 1725*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1726*955f2ea3SAbel Vesa .name = "gcc_pcie_1_phy_rchng_clk", 1727*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 1728*955f2ea3SAbel Vesa .hw = &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 1729*955f2ea3SAbel Vesa }, 1730*955f2ea3SAbel Vesa .num_parents = 1, 1731*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1732*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1733*955f2ea3SAbel Vesa }, 1734*955f2ea3SAbel Vesa }, 1735*955f2ea3SAbel Vesa }; 1736*955f2ea3SAbel Vesa 1737*955f2ea3SAbel Vesa static struct clk_branch gcc_pcie_1_pipe_clk = { 1738*955f2ea3SAbel Vesa .halt_reg = 0x8d050, 1739*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_SKIP, 1740*955f2ea3SAbel Vesa .clkr = { 1741*955f2ea3SAbel Vesa .enable_reg = 0x52000, 1742*955f2ea3SAbel Vesa .enable_mask = BIT(30), 1743*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1744*955f2ea3SAbel Vesa .name = "gcc_pcie_1_pipe_clk", 1745*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 1746*955f2ea3SAbel Vesa .hw = &gcc_pcie_1_pipe_clk_src.clkr.hw, 1747*955f2ea3SAbel Vesa }, 1748*955f2ea3SAbel Vesa .num_parents = 1, 1749*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1750*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1751*955f2ea3SAbel Vesa }, 1752*955f2ea3SAbel Vesa }, 1753*955f2ea3SAbel Vesa }; 1754*955f2ea3SAbel Vesa 1755*955f2ea3SAbel Vesa static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1756*955f2ea3SAbel Vesa .halt_reg = 0x8d01c, 1757*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1758*955f2ea3SAbel Vesa .hwcg_reg = 0x8d01c, 1759*955f2ea3SAbel Vesa .hwcg_bit = 1, 1760*955f2ea3SAbel Vesa .clkr = { 1761*955f2ea3SAbel Vesa .enable_reg = 0x52000, 1762*955f2ea3SAbel Vesa .enable_mask = BIT(26), 1763*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1764*955f2ea3SAbel Vesa .name = "gcc_pcie_1_slv_axi_clk", 1765*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1766*955f2ea3SAbel Vesa }, 1767*955f2ea3SAbel Vesa }, 1768*955f2ea3SAbel Vesa }; 1769*955f2ea3SAbel Vesa 1770*955f2ea3SAbel Vesa static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 1771*955f2ea3SAbel Vesa .halt_reg = 0x8d018, 1772*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1773*955f2ea3SAbel Vesa .clkr = { 1774*955f2ea3SAbel Vesa .enable_reg = 0x52000, 1775*955f2ea3SAbel Vesa .enable_mask = BIT(25), 1776*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1777*955f2ea3SAbel Vesa .name = "gcc_pcie_1_slv_q2a_axi_clk", 1778*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1779*955f2ea3SAbel Vesa }, 1780*955f2ea3SAbel Vesa }, 1781*955f2ea3SAbel Vesa }; 1782*955f2ea3SAbel Vesa 1783*955f2ea3SAbel Vesa static struct clk_branch gcc_pdm2_clk = { 1784*955f2ea3SAbel Vesa .halt_reg = 0x3300c, 1785*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT, 1786*955f2ea3SAbel Vesa .clkr = { 1787*955f2ea3SAbel Vesa .enable_reg = 0x3300c, 1788*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1789*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1790*955f2ea3SAbel Vesa .name = "gcc_pdm2_clk", 1791*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 1792*955f2ea3SAbel Vesa .hw = &gcc_pdm2_clk_src.clkr.hw, 1793*955f2ea3SAbel Vesa }, 1794*955f2ea3SAbel Vesa .num_parents = 1, 1795*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1796*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1797*955f2ea3SAbel Vesa }, 1798*955f2ea3SAbel Vesa }, 1799*955f2ea3SAbel Vesa }; 1800*955f2ea3SAbel Vesa 1801*955f2ea3SAbel Vesa static struct clk_branch gcc_pdm_ahb_clk = { 1802*955f2ea3SAbel Vesa .halt_reg = 0x33004, 1803*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1804*955f2ea3SAbel Vesa .hwcg_reg = 0x33004, 1805*955f2ea3SAbel Vesa .hwcg_bit = 1, 1806*955f2ea3SAbel Vesa .clkr = { 1807*955f2ea3SAbel Vesa .enable_reg = 0x33004, 1808*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1809*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1810*955f2ea3SAbel Vesa .name = "gcc_pdm_ahb_clk", 1811*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1812*955f2ea3SAbel Vesa }, 1813*955f2ea3SAbel Vesa }, 1814*955f2ea3SAbel Vesa }; 1815*955f2ea3SAbel Vesa 1816*955f2ea3SAbel Vesa static struct clk_branch gcc_pdm_xo4_clk = { 1817*955f2ea3SAbel Vesa .halt_reg = 0x33008, 1818*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT, 1819*955f2ea3SAbel Vesa .clkr = { 1820*955f2ea3SAbel Vesa .enable_reg = 0x33008, 1821*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1822*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1823*955f2ea3SAbel Vesa .name = "gcc_pdm_xo4_clk", 1824*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1825*955f2ea3SAbel Vesa }, 1826*955f2ea3SAbel Vesa }, 1827*955f2ea3SAbel Vesa }; 1828*955f2ea3SAbel Vesa 1829*955f2ea3SAbel Vesa static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 1830*955f2ea3SAbel Vesa .halt_reg = 0x26008, 1831*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1832*955f2ea3SAbel Vesa .hwcg_reg = 0x26008, 1833*955f2ea3SAbel Vesa .hwcg_bit = 1, 1834*955f2ea3SAbel Vesa .clkr = { 1835*955f2ea3SAbel Vesa .enable_reg = 0x26008, 1836*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1837*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1838*955f2ea3SAbel Vesa .name = "gcc_qmip_camera_nrt_ahb_clk", 1839*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1840*955f2ea3SAbel Vesa }, 1841*955f2ea3SAbel Vesa }, 1842*955f2ea3SAbel Vesa }; 1843*955f2ea3SAbel Vesa 1844*955f2ea3SAbel Vesa static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 1845*955f2ea3SAbel Vesa .halt_reg = 0x2600c, 1846*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1847*955f2ea3SAbel Vesa .hwcg_reg = 0x2600c, 1848*955f2ea3SAbel Vesa .hwcg_bit = 1, 1849*955f2ea3SAbel Vesa .clkr = { 1850*955f2ea3SAbel Vesa .enable_reg = 0x2600c, 1851*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1852*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1853*955f2ea3SAbel Vesa .name = "gcc_qmip_camera_rt_ahb_clk", 1854*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1855*955f2ea3SAbel Vesa }, 1856*955f2ea3SAbel Vesa }, 1857*955f2ea3SAbel Vesa }; 1858*955f2ea3SAbel Vesa 1859*955f2ea3SAbel Vesa static struct clk_branch gcc_qmip_disp_ahb_clk = { 1860*955f2ea3SAbel Vesa .halt_reg = 0x27008, 1861*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1862*955f2ea3SAbel Vesa .hwcg_reg = 0x27008, 1863*955f2ea3SAbel Vesa .hwcg_bit = 1, 1864*955f2ea3SAbel Vesa .clkr = { 1865*955f2ea3SAbel Vesa .enable_reg = 0x27008, 1866*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1867*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1868*955f2ea3SAbel Vesa .name = "gcc_qmip_disp_ahb_clk", 1869*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1870*955f2ea3SAbel Vesa }, 1871*955f2ea3SAbel Vesa }, 1872*955f2ea3SAbel Vesa }; 1873*955f2ea3SAbel Vesa 1874*955f2ea3SAbel Vesa static struct clk_branch gcc_qmip_gpu_ahb_clk = { 1875*955f2ea3SAbel Vesa .halt_reg = 0x71008, 1876*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1877*955f2ea3SAbel Vesa .hwcg_reg = 0x71008, 1878*955f2ea3SAbel Vesa .hwcg_bit = 1, 1879*955f2ea3SAbel Vesa .clkr = { 1880*955f2ea3SAbel Vesa .enable_reg = 0x71008, 1881*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1882*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1883*955f2ea3SAbel Vesa .name = "gcc_qmip_gpu_ahb_clk", 1884*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1885*955f2ea3SAbel Vesa }, 1886*955f2ea3SAbel Vesa }, 1887*955f2ea3SAbel Vesa }; 1888*955f2ea3SAbel Vesa 1889*955f2ea3SAbel Vesa static struct clk_branch gcc_qmip_pcie_ahb_clk = { 1890*955f2ea3SAbel Vesa .halt_reg = 0x6b018, 1891*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1892*955f2ea3SAbel Vesa .hwcg_reg = 0x6b018, 1893*955f2ea3SAbel Vesa .hwcg_bit = 1, 1894*955f2ea3SAbel Vesa .clkr = { 1895*955f2ea3SAbel Vesa .enable_reg = 0x52000, 1896*955f2ea3SAbel Vesa .enable_mask = BIT(11), 1897*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1898*955f2ea3SAbel Vesa .name = "gcc_qmip_pcie_ahb_clk", 1899*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1900*955f2ea3SAbel Vesa }, 1901*955f2ea3SAbel Vesa }, 1902*955f2ea3SAbel Vesa }; 1903*955f2ea3SAbel Vesa 1904*955f2ea3SAbel Vesa static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = { 1905*955f2ea3SAbel Vesa .halt_reg = 0x32014, 1906*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1907*955f2ea3SAbel Vesa .hwcg_reg = 0x32014, 1908*955f2ea3SAbel Vesa .hwcg_bit = 1, 1909*955f2ea3SAbel Vesa .clkr = { 1910*955f2ea3SAbel Vesa .enable_reg = 0x32014, 1911*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1912*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1913*955f2ea3SAbel Vesa .name = "gcc_qmip_video_cv_cpu_ahb_clk", 1914*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1915*955f2ea3SAbel Vesa }, 1916*955f2ea3SAbel Vesa }, 1917*955f2ea3SAbel Vesa }; 1918*955f2ea3SAbel Vesa 1919*955f2ea3SAbel Vesa static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 1920*955f2ea3SAbel Vesa .halt_reg = 0x32008, 1921*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1922*955f2ea3SAbel Vesa .hwcg_reg = 0x32008, 1923*955f2ea3SAbel Vesa .hwcg_bit = 1, 1924*955f2ea3SAbel Vesa .clkr = { 1925*955f2ea3SAbel Vesa .enable_reg = 0x32008, 1926*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1927*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1928*955f2ea3SAbel Vesa .name = "gcc_qmip_video_cvp_ahb_clk", 1929*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1930*955f2ea3SAbel Vesa }, 1931*955f2ea3SAbel Vesa }, 1932*955f2ea3SAbel Vesa }; 1933*955f2ea3SAbel Vesa 1934*955f2ea3SAbel Vesa static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = { 1935*955f2ea3SAbel Vesa .halt_reg = 0x32010, 1936*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1937*955f2ea3SAbel Vesa .hwcg_reg = 0x32010, 1938*955f2ea3SAbel Vesa .hwcg_bit = 1, 1939*955f2ea3SAbel Vesa .clkr = { 1940*955f2ea3SAbel Vesa .enable_reg = 0x32010, 1941*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1942*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1943*955f2ea3SAbel Vesa .name = "gcc_qmip_video_v_cpu_ahb_clk", 1944*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1945*955f2ea3SAbel Vesa }, 1946*955f2ea3SAbel Vesa }, 1947*955f2ea3SAbel Vesa }; 1948*955f2ea3SAbel Vesa 1949*955f2ea3SAbel Vesa static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 1950*955f2ea3SAbel Vesa .halt_reg = 0x3200c, 1951*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1952*955f2ea3SAbel Vesa .hwcg_reg = 0x3200c, 1953*955f2ea3SAbel Vesa .hwcg_bit = 1, 1954*955f2ea3SAbel Vesa .clkr = { 1955*955f2ea3SAbel Vesa .enable_reg = 0x3200c, 1956*955f2ea3SAbel Vesa .enable_mask = BIT(0), 1957*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1958*955f2ea3SAbel Vesa .name = "gcc_qmip_video_vcodec_ahb_clk", 1959*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1960*955f2ea3SAbel Vesa }, 1961*955f2ea3SAbel Vesa }, 1962*955f2ea3SAbel Vesa }; 1963*955f2ea3SAbel Vesa 1964*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_i2c_core_clk = { 1965*955f2ea3SAbel Vesa .halt_reg = 0x23144, 1966*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1967*955f2ea3SAbel Vesa .clkr = { 1968*955f2ea3SAbel Vesa .enable_reg = 0x52008, 1969*955f2ea3SAbel Vesa .enable_mask = BIT(8), 1970*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1971*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_core_clk", 1972*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1973*955f2ea3SAbel Vesa }, 1974*955f2ea3SAbel Vesa }, 1975*955f2ea3SAbel Vesa }; 1976*955f2ea3SAbel Vesa 1977*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_i2c_s0_clk = { 1978*955f2ea3SAbel Vesa .halt_reg = 0x17004, 1979*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1980*955f2ea3SAbel Vesa .clkr = { 1981*955f2ea3SAbel Vesa .enable_reg = 0x52008, 1982*955f2ea3SAbel Vesa .enable_mask = BIT(10), 1983*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 1984*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s0_clk", 1985*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 1986*955f2ea3SAbel Vesa .hw = &gcc_qupv3_i2c_s0_clk_src.clkr.hw, 1987*955f2ea3SAbel Vesa }, 1988*955f2ea3SAbel Vesa .num_parents = 1, 1989*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 1990*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 1991*955f2ea3SAbel Vesa }, 1992*955f2ea3SAbel Vesa }, 1993*955f2ea3SAbel Vesa }; 1994*955f2ea3SAbel Vesa 1995*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_i2c_s1_clk = { 1996*955f2ea3SAbel Vesa .halt_reg = 0x17020, 1997*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 1998*955f2ea3SAbel Vesa .clkr = { 1999*955f2ea3SAbel Vesa .enable_reg = 0x52008, 2000*955f2ea3SAbel Vesa .enable_mask = BIT(11), 2001*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2002*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s1_clk", 2003*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2004*955f2ea3SAbel Vesa .hw = &gcc_qupv3_i2c_s1_clk_src.clkr.hw, 2005*955f2ea3SAbel Vesa }, 2006*955f2ea3SAbel Vesa .num_parents = 1, 2007*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2008*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2009*955f2ea3SAbel Vesa }, 2010*955f2ea3SAbel Vesa }, 2011*955f2ea3SAbel Vesa }; 2012*955f2ea3SAbel Vesa 2013*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_i2c_s2_clk = { 2014*955f2ea3SAbel Vesa .halt_reg = 0x1703c, 2015*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2016*955f2ea3SAbel Vesa .clkr = { 2017*955f2ea3SAbel Vesa .enable_reg = 0x52008, 2018*955f2ea3SAbel Vesa .enable_mask = BIT(12), 2019*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2020*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s2_clk", 2021*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2022*955f2ea3SAbel Vesa .hw = &gcc_qupv3_i2c_s2_clk_src.clkr.hw, 2023*955f2ea3SAbel Vesa }, 2024*955f2ea3SAbel Vesa .num_parents = 1, 2025*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2026*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2027*955f2ea3SAbel Vesa }, 2028*955f2ea3SAbel Vesa }, 2029*955f2ea3SAbel Vesa }; 2030*955f2ea3SAbel Vesa 2031*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_i2c_s3_clk = { 2032*955f2ea3SAbel Vesa .halt_reg = 0x17058, 2033*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2034*955f2ea3SAbel Vesa .clkr = { 2035*955f2ea3SAbel Vesa .enable_reg = 0x52008, 2036*955f2ea3SAbel Vesa .enable_mask = BIT(13), 2037*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2038*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s3_clk", 2039*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2040*955f2ea3SAbel Vesa .hw = &gcc_qupv3_i2c_s3_clk_src.clkr.hw, 2041*955f2ea3SAbel Vesa }, 2042*955f2ea3SAbel Vesa .num_parents = 1, 2043*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2044*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2045*955f2ea3SAbel Vesa }, 2046*955f2ea3SAbel Vesa }, 2047*955f2ea3SAbel Vesa }; 2048*955f2ea3SAbel Vesa 2049*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_i2c_s4_clk = { 2050*955f2ea3SAbel Vesa .halt_reg = 0x17074, 2051*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2052*955f2ea3SAbel Vesa .clkr = { 2053*955f2ea3SAbel Vesa .enable_reg = 0x52008, 2054*955f2ea3SAbel Vesa .enable_mask = BIT(14), 2055*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2056*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s4_clk", 2057*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2058*955f2ea3SAbel Vesa .hw = &gcc_qupv3_i2c_s4_clk_src.clkr.hw, 2059*955f2ea3SAbel Vesa }, 2060*955f2ea3SAbel Vesa .num_parents = 1, 2061*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2062*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2063*955f2ea3SAbel Vesa }, 2064*955f2ea3SAbel Vesa }, 2065*955f2ea3SAbel Vesa }; 2066*955f2ea3SAbel Vesa 2067*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_i2c_s5_clk = { 2068*955f2ea3SAbel Vesa .halt_reg = 0x17090, 2069*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2070*955f2ea3SAbel Vesa .clkr = { 2071*955f2ea3SAbel Vesa .enable_reg = 0x52008, 2072*955f2ea3SAbel Vesa .enable_mask = BIT(15), 2073*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2074*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s5_clk", 2075*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2076*955f2ea3SAbel Vesa .hw = &gcc_qupv3_i2c_s5_clk_src.clkr.hw, 2077*955f2ea3SAbel Vesa }, 2078*955f2ea3SAbel Vesa .num_parents = 1, 2079*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2080*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2081*955f2ea3SAbel Vesa }, 2082*955f2ea3SAbel Vesa }, 2083*955f2ea3SAbel Vesa }; 2084*955f2ea3SAbel Vesa 2085*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_i2c_s6_clk = { 2086*955f2ea3SAbel Vesa .halt_reg = 0x170ac, 2087*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2088*955f2ea3SAbel Vesa .clkr = { 2089*955f2ea3SAbel Vesa .enable_reg = 0x52008, 2090*955f2ea3SAbel Vesa .enable_mask = BIT(16), 2091*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2092*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s6_clk", 2093*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2094*955f2ea3SAbel Vesa .hw = &gcc_qupv3_i2c_s6_clk_src.clkr.hw, 2095*955f2ea3SAbel Vesa }, 2096*955f2ea3SAbel Vesa .num_parents = 1, 2097*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2098*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2099*955f2ea3SAbel Vesa }, 2100*955f2ea3SAbel Vesa }, 2101*955f2ea3SAbel Vesa }; 2102*955f2ea3SAbel Vesa 2103*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_i2c_s7_clk = { 2104*955f2ea3SAbel Vesa .halt_reg = 0x170c8, 2105*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2106*955f2ea3SAbel Vesa .clkr = { 2107*955f2ea3SAbel Vesa .enable_reg = 0x52008, 2108*955f2ea3SAbel Vesa .enable_mask = BIT(17), 2109*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2110*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s7_clk", 2111*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2112*955f2ea3SAbel Vesa .hw = &gcc_qupv3_i2c_s7_clk_src.clkr.hw, 2113*955f2ea3SAbel Vesa }, 2114*955f2ea3SAbel Vesa .num_parents = 1, 2115*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2116*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2117*955f2ea3SAbel Vesa }, 2118*955f2ea3SAbel Vesa }, 2119*955f2ea3SAbel Vesa }; 2120*955f2ea3SAbel Vesa 2121*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_i2c_s8_clk = { 2122*955f2ea3SAbel Vesa .halt_reg = 0x170e4, 2123*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2124*955f2ea3SAbel Vesa .clkr = { 2125*955f2ea3SAbel Vesa .enable_reg = 0x52010, 2126*955f2ea3SAbel Vesa .enable_mask = BIT(14), 2127*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2128*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s8_clk", 2129*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2130*955f2ea3SAbel Vesa .hw = &gcc_qupv3_i2c_s8_clk_src.clkr.hw, 2131*955f2ea3SAbel Vesa }, 2132*955f2ea3SAbel Vesa .num_parents = 1, 2133*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2134*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2135*955f2ea3SAbel Vesa }, 2136*955f2ea3SAbel Vesa }, 2137*955f2ea3SAbel Vesa }; 2138*955f2ea3SAbel Vesa 2139*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_i2c_s9_clk = { 2140*955f2ea3SAbel Vesa .halt_reg = 0x17100, 2141*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2142*955f2ea3SAbel Vesa .clkr = { 2143*955f2ea3SAbel Vesa .enable_reg = 0x52010, 2144*955f2ea3SAbel Vesa .enable_mask = BIT(15), 2145*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2146*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s9_clk", 2147*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2148*955f2ea3SAbel Vesa .hw = &gcc_qupv3_i2c_s9_clk_src.clkr.hw, 2149*955f2ea3SAbel Vesa }, 2150*955f2ea3SAbel Vesa .num_parents = 1, 2151*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2152*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2153*955f2ea3SAbel Vesa }, 2154*955f2ea3SAbel Vesa }, 2155*955f2ea3SAbel Vesa }; 2156*955f2ea3SAbel Vesa 2157*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_i2c_s_ahb_clk = { 2158*955f2ea3SAbel Vesa .halt_reg = 0x23140, 2159*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2160*955f2ea3SAbel Vesa .hwcg_reg = 0x23140, 2161*955f2ea3SAbel Vesa .hwcg_bit = 1, 2162*955f2ea3SAbel Vesa .clkr = { 2163*955f2ea3SAbel Vesa .enable_reg = 0x52008, 2164*955f2ea3SAbel Vesa .enable_mask = BIT(7), 2165*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2166*955f2ea3SAbel Vesa .name = "gcc_qupv3_i2c_s_ahb_clk", 2167*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2168*955f2ea3SAbel Vesa }, 2169*955f2ea3SAbel Vesa }, 2170*955f2ea3SAbel Vesa }; 2171*955f2ea3SAbel Vesa 2172*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2173*955f2ea3SAbel Vesa .halt_reg = 0x23294, 2174*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2175*955f2ea3SAbel Vesa .clkr = { 2176*955f2ea3SAbel Vesa .enable_reg = 0x52008, 2177*955f2ea3SAbel Vesa .enable_mask = BIT(18), 2178*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2179*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap1_core_2x_clk", 2180*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2181*955f2ea3SAbel Vesa }, 2182*955f2ea3SAbel Vesa }, 2183*955f2ea3SAbel Vesa }; 2184*955f2ea3SAbel Vesa 2185*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2186*955f2ea3SAbel Vesa .halt_reg = 0x23284, 2187*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2188*955f2ea3SAbel Vesa .clkr = { 2189*955f2ea3SAbel Vesa .enable_reg = 0x52008, 2190*955f2ea3SAbel Vesa .enable_mask = BIT(19), 2191*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2192*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap1_core_clk", 2193*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2194*955f2ea3SAbel Vesa }, 2195*955f2ea3SAbel Vesa }, 2196*955f2ea3SAbel Vesa }; 2197*955f2ea3SAbel Vesa 2198*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2199*955f2ea3SAbel Vesa .halt_reg = 0x18004, 2200*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2201*955f2ea3SAbel Vesa .clkr = { 2202*955f2ea3SAbel Vesa .enable_reg = 0x52008, 2203*955f2ea3SAbel Vesa .enable_mask = BIT(22), 2204*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2205*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap1_s0_clk", 2206*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2207*955f2ea3SAbel Vesa .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2208*955f2ea3SAbel Vesa }, 2209*955f2ea3SAbel Vesa .num_parents = 1, 2210*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2211*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2212*955f2ea3SAbel Vesa }, 2213*955f2ea3SAbel Vesa }, 2214*955f2ea3SAbel Vesa }; 2215*955f2ea3SAbel Vesa 2216*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2217*955f2ea3SAbel Vesa .halt_reg = 0x1813c, 2218*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2219*955f2ea3SAbel Vesa .clkr = { 2220*955f2ea3SAbel Vesa .enable_reg = 0x52008, 2221*955f2ea3SAbel Vesa .enable_mask = BIT(23), 2222*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2223*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap1_s1_clk", 2224*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2225*955f2ea3SAbel Vesa .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2226*955f2ea3SAbel Vesa }, 2227*955f2ea3SAbel Vesa .num_parents = 1, 2228*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2229*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2230*955f2ea3SAbel Vesa }, 2231*955f2ea3SAbel Vesa }, 2232*955f2ea3SAbel Vesa }; 2233*955f2ea3SAbel Vesa 2234*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2235*955f2ea3SAbel Vesa .halt_reg = 0x18274, 2236*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2237*955f2ea3SAbel Vesa .clkr = { 2238*955f2ea3SAbel Vesa .enable_reg = 0x52008, 2239*955f2ea3SAbel Vesa .enable_mask = BIT(24), 2240*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2241*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap1_s2_clk", 2242*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2243*955f2ea3SAbel Vesa .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2244*955f2ea3SAbel Vesa }, 2245*955f2ea3SAbel Vesa .num_parents = 1, 2246*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2247*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2248*955f2ea3SAbel Vesa }, 2249*955f2ea3SAbel Vesa }, 2250*955f2ea3SAbel Vesa }; 2251*955f2ea3SAbel Vesa 2252*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2253*955f2ea3SAbel Vesa .halt_reg = 0x183ac, 2254*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2255*955f2ea3SAbel Vesa .clkr = { 2256*955f2ea3SAbel Vesa .enable_reg = 0x52008, 2257*955f2ea3SAbel Vesa .enable_mask = BIT(25), 2258*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2259*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap1_s3_clk", 2260*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2261*955f2ea3SAbel Vesa .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2262*955f2ea3SAbel Vesa }, 2263*955f2ea3SAbel Vesa .num_parents = 1, 2264*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2265*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2266*955f2ea3SAbel Vesa }, 2267*955f2ea3SAbel Vesa }, 2268*955f2ea3SAbel Vesa }; 2269*955f2ea3SAbel Vesa 2270*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2271*955f2ea3SAbel Vesa .halt_reg = 0x184e4, 2272*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2273*955f2ea3SAbel Vesa .clkr = { 2274*955f2ea3SAbel Vesa .enable_reg = 0x52008, 2275*955f2ea3SAbel Vesa .enable_mask = BIT(26), 2276*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2277*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap1_s4_clk", 2278*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2279*955f2ea3SAbel Vesa .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2280*955f2ea3SAbel Vesa }, 2281*955f2ea3SAbel Vesa .num_parents = 1, 2282*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2283*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2284*955f2ea3SAbel Vesa }, 2285*955f2ea3SAbel Vesa }, 2286*955f2ea3SAbel Vesa }; 2287*955f2ea3SAbel Vesa 2288*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2289*955f2ea3SAbel Vesa .halt_reg = 0x1861c, 2290*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2291*955f2ea3SAbel Vesa .clkr = { 2292*955f2ea3SAbel Vesa .enable_reg = 0x52008, 2293*955f2ea3SAbel Vesa .enable_mask = BIT(27), 2294*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2295*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap1_s5_clk", 2296*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2297*955f2ea3SAbel Vesa .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2298*955f2ea3SAbel Vesa }, 2299*955f2ea3SAbel Vesa .num_parents = 1, 2300*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2301*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2302*955f2ea3SAbel Vesa }, 2303*955f2ea3SAbel Vesa }, 2304*955f2ea3SAbel Vesa }; 2305*955f2ea3SAbel Vesa 2306*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 2307*955f2ea3SAbel Vesa .halt_reg = 0x18754, 2308*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2309*955f2ea3SAbel Vesa .clkr = { 2310*955f2ea3SAbel Vesa .enable_reg = 0x52008, 2311*955f2ea3SAbel Vesa .enable_mask = BIT(28), 2312*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2313*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap1_s6_clk", 2314*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2315*955f2ea3SAbel Vesa .hw = &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 2316*955f2ea3SAbel Vesa }, 2317*955f2ea3SAbel Vesa .num_parents = 1, 2318*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2319*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2320*955f2ea3SAbel Vesa }, 2321*955f2ea3SAbel Vesa }, 2322*955f2ea3SAbel Vesa }; 2323*955f2ea3SAbel Vesa 2324*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 2325*955f2ea3SAbel Vesa .halt_reg = 0x1888c, 2326*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2327*955f2ea3SAbel Vesa .clkr = { 2328*955f2ea3SAbel Vesa .enable_reg = 0x52010, 2329*955f2ea3SAbel Vesa .enable_mask = BIT(16), 2330*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2331*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap1_s7_clk", 2332*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2333*955f2ea3SAbel Vesa .hw = &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 2334*955f2ea3SAbel Vesa }, 2335*955f2ea3SAbel Vesa .num_parents = 1, 2336*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2337*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2338*955f2ea3SAbel Vesa }, 2339*955f2ea3SAbel Vesa }, 2340*955f2ea3SAbel Vesa }; 2341*955f2ea3SAbel Vesa 2342*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 2343*955f2ea3SAbel Vesa .halt_reg = 0x23004, 2344*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2345*955f2ea3SAbel Vesa .clkr = { 2346*955f2ea3SAbel Vesa .enable_reg = 0x52010, 2347*955f2ea3SAbel Vesa .enable_mask = BIT(3), 2348*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2349*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap2_core_2x_clk", 2350*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2351*955f2ea3SAbel Vesa }, 2352*955f2ea3SAbel Vesa }, 2353*955f2ea3SAbel Vesa }; 2354*955f2ea3SAbel Vesa 2355*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap2_core_clk = { 2356*955f2ea3SAbel Vesa .halt_reg = 0x233d4, 2357*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2358*955f2ea3SAbel Vesa .clkr = { 2359*955f2ea3SAbel Vesa .enable_reg = 0x52010, 2360*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2361*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2362*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap2_core_clk", 2363*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2364*955f2ea3SAbel Vesa }, 2365*955f2ea3SAbel Vesa }, 2366*955f2ea3SAbel Vesa }; 2367*955f2ea3SAbel Vesa 2368*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 2369*955f2ea3SAbel Vesa .halt_reg = 0x1e004, 2370*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2371*955f2ea3SAbel Vesa .clkr = { 2372*955f2ea3SAbel Vesa .enable_reg = 0x52010, 2373*955f2ea3SAbel Vesa .enable_mask = BIT(4), 2374*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2375*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap2_s0_clk", 2376*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2377*955f2ea3SAbel Vesa .hw = &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 2378*955f2ea3SAbel Vesa }, 2379*955f2ea3SAbel Vesa .num_parents = 1, 2380*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2381*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2382*955f2ea3SAbel Vesa }, 2383*955f2ea3SAbel Vesa }, 2384*955f2ea3SAbel Vesa }; 2385*955f2ea3SAbel Vesa 2386*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 2387*955f2ea3SAbel Vesa .halt_reg = 0x1e13c, 2388*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2389*955f2ea3SAbel Vesa .clkr = { 2390*955f2ea3SAbel Vesa .enable_reg = 0x52010, 2391*955f2ea3SAbel Vesa .enable_mask = BIT(5), 2392*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2393*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap2_s1_clk", 2394*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2395*955f2ea3SAbel Vesa .hw = &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 2396*955f2ea3SAbel Vesa }, 2397*955f2ea3SAbel Vesa .num_parents = 1, 2398*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2399*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2400*955f2ea3SAbel Vesa }, 2401*955f2ea3SAbel Vesa }, 2402*955f2ea3SAbel Vesa }; 2403*955f2ea3SAbel Vesa 2404*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 2405*955f2ea3SAbel Vesa .halt_reg = 0x1e274, 2406*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2407*955f2ea3SAbel Vesa .clkr = { 2408*955f2ea3SAbel Vesa .enable_reg = 0x52010, 2409*955f2ea3SAbel Vesa .enable_mask = BIT(6), 2410*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2411*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap2_s2_clk", 2412*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2413*955f2ea3SAbel Vesa .hw = &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 2414*955f2ea3SAbel Vesa }, 2415*955f2ea3SAbel Vesa .num_parents = 1, 2416*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2417*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2418*955f2ea3SAbel Vesa }, 2419*955f2ea3SAbel Vesa }, 2420*955f2ea3SAbel Vesa }; 2421*955f2ea3SAbel Vesa 2422*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 2423*955f2ea3SAbel Vesa .halt_reg = 0x1e3ac, 2424*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2425*955f2ea3SAbel Vesa .clkr = { 2426*955f2ea3SAbel Vesa .enable_reg = 0x52010, 2427*955f2ea3SAbel Vesa .enable_mask = BIT(7), 2428*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2429*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap2_s3_clk", 2430*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2431*955f2ea3SAbel Vesa .hw = &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 2432*955f2ea3SAbel Vesa }, 2433*955f2ea3SAbel Vesa .num_parents = 1, 2434*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2435*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2436*955f2ea3SAbel Vesa }, 2437*955f2ea3SAbel Vesa }, 2438*955f2ea3SAbel Vesa }; 2439*955f2ea3SAbel Vesa 2440*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 2441*955f2ea3SAbel Vesa .halt_reg = 0x1e4e4, 2442*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2443*955f2ea3SAbel Vesa .clkr = { 2444*955f2ea3SAbel Vesa .enable_reg = 0x52010, 2445*955f2ea3SAbel Vesa .enable_mask = BIT(8), 2446*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2447*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap2_s4_clk", 2448*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2449*955f2ea3SAbel Vesa .hw = &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 2450*955f2ea3SAbel Vesa }, 2451*955f2ea3SAbel Vesa .num_parents = 1, 2452*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2453*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2454*955f2ea3SAbel Vesa }, 2455*955f2ea3SAbel Vesa }, 2456*955f2ea3SAbel Vesa }; 2457*955f2ea3SAbel Vesa 2458*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 2459*955f2ea3SAbel Vesa .halt_reg = 0x1e61c, 2460*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2461*955f2ea3SAbel Vesa .clkr = { 2462*955f2ea3SAbel Vesa .enable_reg = 0x52010, 2463*955f2ea3SAbel Vesa .enable_mask = BIT(9), 2464*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2465*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap2_s5_clk", 2466*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2467*955f2ea3SAbel Vesa .hw = &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 2468*955f2ea3SAbel Vesa }, 2469*955f2ea3SAbel Vesa .num_parents = 1, 2470*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2471*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2472*955f2ea3SAbel Vesa }, 2473*955f2ea3SAbel Vesa }, 2474*955f2ea3SAbel Vesa }; 2475*955f2ea3SAbel Vesa 2476*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap2_s6_clk = { 2477*955f2ea3SAbel Vesa .halt_reg = 0x1e754, 2478*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2479*955f2ea3SAbel Vesa .clkr = { 2480*955f2ea3SAbel Vesa .enable_reg = 0x52010, 2481*955f2ea3SAbel Vesa .enable_mask = BIT(10), 2482*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2483*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap2_s6_clk", 2484*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2485*955f2ea3SAbel Vesa .hw = &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, 2486*955f2ea3SAbel Vesa }, 2487*955f2ea3SAbel Vesa .num_parents = 1, 2488*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2489*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2490*955f2ea3SAbel Vesa }, 2491*955f2ea3SAbel Vesa }, 2492*955f2ea3SAbel Vesa }; 2493*955f2ea3SAbel Vesa 2494*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap2_s7_clk = { 2495*955f2ea3SAbel Vesa .halt_reg = 0x1e88c, 2496*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2497*955f2ea3SAbel Vesa .clkr = { 2498*955f2ea3SAbel Vesa .enable_reg = 0x52010, 2499*955f2ea3SAbel Vesa .enable_mask = BIT(17), 2500*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2501*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap2_s7_clk", 2502*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2503*955f2ea3SAbel Vesa .hw = &gcc_qupv3_wrap2_s7_clk_src.clkr.hw, 2504*955f2ea3SAbel Vesa }, 2505*955f2ea3SAbel Vesa .num_parents = 1, 2506*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2507*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2508*955f2ea3SAbel Vesa }, 2509*955f2ea3SAbel Vesa }, 2510*955f2ea3SAbel Vesa }; 2511*955f2ea3SAbel Vesa 2512*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2513*955f2ea3SAbel Vesa .halt_reg = 0x2327c, 2514*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2515*955f2ea3SAbel Vesa .hwcg_reg = 0x2327c, 2516*955f2ea3SAbel Vesa .hwcg_bit = 1, 2517*955f2ea3SAbel Vesa .clkr = { 2518*955f2ea3SAbel Vesa .enable_reg = 0x52008, 2519*955f2ea3SAbel Vesa .enable_mask = BIT(20), 2520*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2521*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2522*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2523*955f2ea3SAbel Vesa }, 2524*955f2ea3SAbel Vesa }, 2525*955f2ea3SAbel Vesa }; 2526*955f2ea3SAbel Vesa 2527*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2528*955f2ea3SAbel Vesa .halt_reg = 0x23280, 2529*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2530*955f2ea3SAbel Vesa .hwcg_reg = 0x23280, 2531*955f2ea3SAbel Vesa .hwcg_bit = 1, 2532*955f2ea3SAbel Vesa .clkr = { 2533*955f2ea3SAbel Vesa .enable_reg = 0x52008, 2534*955f2ea3SAbel Vesa .enable_mask = BIT(21), 2535*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2536*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2537*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2538*955f2ea3SAbel Vesa }, 2539*955f2ea3SAbel Vesa }, 2540*955f2ea3SAbel Vesa }; 2541*955f2ea3SAbel Vesa 2542*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 2543*955f2ea3SAbel Vesa .halt_reg = 0x233cc, 2544*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2545*955f2ea3SAbel Vesa .hwcg_reg = 0x233cc, 2546*955f2ea3SAbel Vesa .hwcg_bit = 1, 2547*955f2ea3SAbel Vesa .clkr = { 2548*955f2ea3SAbel Vesa .enable_reg = 0x52010, 2549*955f2ea3SAbel Vesa .enable_mask = BIT(2), 2550*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2551*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap_2_m_ahb_clk", 2552*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2553*955f2ea3SAbel Vesa }, 2554*955f2ea3SAbel Vesa }, 2555*955f2ea3SAbel Vesa }; 2556*955f2ea3SAbel Vesa 2557*955f2ea3SAbel Vesa static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 2558*955f2ea3SAbel Vesa .halt_reg = 0x233d0, 2559*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2560*955f2ea3SAbel Vesa .hwcg_reg = 0x233d0, 2561*955f2ea3SAbel Vesa .hwcg_bit = 1, 2562*955f2ea3SAbel Vesa .clkr = { 2563*955f2ea3SAbel Vesa .enable_reg = 0x52010, 2564*955f2ea3SAbel Vesa .enable_mask = BIT(1), 2565*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2566*955f2ea3SAbel Vesa .name = "gcc_qupv3_wrap_2_s_ahb_clk", 2567*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2568*955f2ea3SAbel Vesa }, 2569*955f2ea3SAbel Vesa }, 2570*955f2ea3SAbel Vesa }; 2571*955f2ea3SAbel Vesa 2572*955f2ea3SAbel Vesa static struct clk_branch gcc_sdcc2_ahb_clk = { 2573*955f2ea3SAbel Vesa .halt_reg = 0x14010, 2574*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT, 2575*955f2ea3SAbel Vesa .clkr = { 2576*955f2ea3SAbel Vesa .enable_reg = 0x14010, 2577*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2578*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2579*955f2ea3SAbel Vesa .name = "gcc_sdcc2_ahb_clk", 2580*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2581*955f2ea3SAbel Vesa }, 2582*955f2ea3SAbel Vesa }, 2583*955f2ea3SAbel Vesa }; 2584*955f2ea3SAbel Vesa 2585*955f2ea3SAbel Vesa static struct clk_branch gcc_sdcc2_apps_clk = { 2586*955f2ea3SAbel Vesa .halt_reg = 0x14004, 2587*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT, 2588*955f2ea3SAbel Vesa .clkr = { 2589*955f2ea3SAbel Vesa .enable_reg = 0x14004, 2590*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2591*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2592*955f2ea3SAbel Vesa .name = "gcc_sdcc2_apps_clk", 2593*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2594*955f2ea3SAbel Vesa .hw = &gcc_sdcc2_apps_clk_src.clkr.hw, 2595*955f2ea3SAbel Vesa }, 2596*955f2ea3SAbel Vesa .num_parents = 1, 2597*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2598*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2599*955f2ea3SAbel Vesa }, 2600*955f2ea3SAbel Vesa }, 2601*955f2ea3SAbel Vesa }; 2602*955f2ea3SAbel Vesa 2603*955f2ea3SAbel Vesa static struct clk_branch gcc_sdcc4_ahb_clk = { 2604*955f2ea3SAbel Vesa .halt_reg = 0x16010, 2605*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT, 2606*955f2ea3SAbel Vesa .clkr = { 2607*955f2ea3SAbel Vesa .enable_reg = 0x16010, 2608*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2609*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2610*955f2ea3SAbel Vesa .name = "gcc_sdcc4_ahb_clk", 2611*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2612*955f2ea3SAbel Vesa }, 2613*955f2ea3SAbel Vesa }, 2614*955f2ea3SAbel Vesa }; 2615*955f2ea3SAbel Vesa 2616*955f2ea3SAbel Vesa static struct clk_branch gcc_sdcc4_apps_clk = { 2617*955f2ea3SAbel Vesa .halt_reg = 0x16004, 2618*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT, 2619*955f2ea3SAbel Vesa .clkr = { 2620*955f2ea3SAbel Vesa .enable_reg = 0x16004, 2621*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2622*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2623*955f2ea3SAbel Vesa .name = "gcc_sdcc4_apps_clk", 2624*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2625*955f2ea3SAbel Vesa .hw = &gcc_sdcc4_apps_clk_src.clkr.hw, 2626*955f2ea3SAbel Vesa }, 2627*955f2ea3SAbel Vesa .num_parents = 1, 2628*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2629*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2630*955f2ea3SAbel Vesa }, 2631*955f2ea3SAbel Vesa }, 2632*955f2ea3SAbel Vesa }; 2633*955f2ea3SAbel Vesa 2634*955f2ea3SAbel Vesa static struct clk_branch gcc_ufs_phy_ahb_clk = { 2635*955f2ea3SAbel Vesa .halt_reg = 0x77024, 2636*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2637*955f2ea3SAbel Vesa .hwcg_reg = 0x77024, 2638*955f2ea3SAbel Vesa .hwcg_bit = 1, 2639*955f2ea3SAbel Vesa .clkr = { 2640*955f2ea3SAbel Vesa .enable_reg = 0x77024, 2641*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2642*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2643*955f2ea3SAbel Vesa .name = "gcc_ufs_phy_ahb_clk", 2644*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2645*955f2ea3SAbel Vesa }, 2646*955f2ea3SAbel Vesa }, 2647*955f2ea3SAbel Vesa }; 2648*955f2ea3SAbel Vesa 2649*955f2ea3SAbel Vesa static struct clk_branch gcc_ufs_phy_axi_clk = { 2650*955f2ea3SAbel Vesa .halt_reg = 0x77018, 2651*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2652*955f2ea3SAbel Vesa .hwcg_reg = 0x77018, 2653*955f2ea3SAbel Vesa .hwcg_bit = 1, 2654*955f2ea3SAbel Vesa .clkr = { 2655*955f2ea3SAbel Vesa .enable_reg = 0x77018, 2656*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2657*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2658*955f2ea3SAbel Vesa .name = "gcc_ufs_phy_axi_clk", 2659*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2660*955f2ea3SAbel Vesa .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 2661*955f2ea3SAbel Vesa }, 2662*955f2ea3SAbel Vesa .num_parents = 1, 2663*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2664*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2665*955f2ea3SAbel Vesa }, 2666*955f2ea3SAbel Vesa }, 2667*955f2ea3SAbel Vesa }; 2668*955f2ea3SAbel Vesa 2669*955f2ea3SAbel Vesa static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { 2670*955f2ea3SAbel Vesa .halt_reg = 0x77018, 2671*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2672*955f2ea3SAbel Vesa .hwcg_reg = 0x77018, 2673*955f2ea3SAbel Vesa .hwcg_bit = 1, 2674*955f2ea3SAbel Vesa .clkr = { 2675*955f2ea3SAbel Vesa .enable_reg = 0x77018, 2676*955f2ea3SAbel Vesa .enable_mask = BIT(1), 2677*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2678*955f2ea3SAbel Vesa .name = "gcc_ufs_phy_axi_hw_ctl_clk", 2679*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2680*955f2ea3SAbel Vesa .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 2681*955f2ea3SAbel Vesa }, 2682*955f2ea3SAbel Vesa .num_parents = 1, 2683*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2684*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2685*955f2ea3SAbel Vesa }, 2686*955f2ea3SAbel Vesa }, 2687*955f2ea3SAbel Vesa }; 2688*955f2ea3SAbel Vesa 2689*955f2ea3SAbel Vesa static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2690*955f2ea3SAbel Vesa .halt_reg = 0x77074, 2691*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2692*955f2ea3SAbel Vesa .hwcg_reg = 0x77074, 2693*955f2ea3SAbel Vesa .hwcg_bit = 1, 2694*955f2ea3SAbel Vesa .clkr = { 2695*955f2ea3SAbel Vesa .enable_reg = 0x77074, 2696*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2697*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2698*955f2ea3SAbel Vesa .name = "gcc_ufs_phy_ice_core_clk", 2699*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2700*955f2ea3SAbel Vesa .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2701*955f2ea3SAbel Vesa }, 2702*955f2ea3SAbel Vesa .num_parents = 1, 2703*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2704*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2705*955f2ea3SAbel Vesa }, 2706*955f2ea3SAbel Vesa }, 2707*955f2ea3SAbel Vesa }; 2708*955f2ea3SAbel Vesa 2709*955f2ea3SAbel Vesa static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { 2710*955f2ea3SAbel Vesa .halt_reg = 0x77074, 2711*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2712*955f2ea3SAbel Vesa .hwcg_reg = 0x77074, 2713*955f2ea3SAbel Vesa .hwcg_bit = 1, 2714*955f2ea3SAbel Vesa .clkr = { 2715*955f2ea3SAbel Vesa .enable_reg = 0x77074, 2716*955f2ea3SAbel Vesa .enable_mask = BIT(1), 2717*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2718*955f2ea3SAbel Vesa .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", 2719*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2720*955f2ea3SAbel Vesa .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2721*955f2ea3SAbel Vesa }, 2722*955f2ea3SAbel Vesa .num_parents = 1, 2723*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2724*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2725*955f2ea3SAbel Vesa }, 2726*955f2ea3SAbel Vesa }, 2727*955f2ea3SAbel Vesa }; 2728*955f2ea3SAbel Vesa 2729*955f2ea3SAbel Vesa static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2730*955f2ea3SAbel Vesa .halt_reg = 0x770b0, 2731*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2732*955f2ea3SAbel Vesa .hwcg_reg = 0x770b0, 2733*955f2ea3SAbel Vesa .hwcg_bit = 1, 2734*955f2ea3SAbel Vesa .clkr = { 2735*955f2ea3SAbel Vesa .enable_reg = 0x770b0, 2736*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2737*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2738*955f2ea3SAbel Vesa .name = "gcc_ufs_phy_phy_aux_clk", 2739*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2740*955f2ea3SAbel Vesa .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2741*955f2ea3SAbel Vesa }, 2742*955f2ea3SAbel Vesa .num_parents = 1, 2743*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2744*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2745*955f2ea3SAbel Vesa }, 2746*955f2ea3SAbel Vesa }, 2747*955f2ea3SAbel Vesa }; 2748*955f2ea3SAbel Vesa 2749*955f2ea3SAbel Vesa static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { 2750*955f2ea3SAbel Vesa .halt_reg = 0x770b0, 2751*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2752*955f2ea3SAbel Vesa .hwcg_reg = 0x770b0, 2753*955f2ea3SAbel Vesa .hwcg_bit = 1, 2754*955f2ea3SAbel Vesa .clkr = { 2755*955f2ea3SAbel Vesa .enable_reg = 0x770b0, 2756*955f2ea3SAbel Vesa .enable_mask = BIT(1), 2757*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2758*955f2ea3SAbel Vesa .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", 2759*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2760*955f2ea3SAbel Vesa .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2761*955f2ea3SAbel Vesa }, 2762*955f2ea3SAbel Vesa .num_parents = 1, 2763*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2764*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2765*955f2ea3SAbel Vesa }, 2766*955f2ea3SAbel Vesa }, 2767*955f2ea3SAbel Vesa }; 2768*955f2ea3SAbel Vesa 2769*955f2ea3SAbel Vesa static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2770*955f2ea3SAbel Vesa .halt_reg = 0x7702c, 2771*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_DELAY, 2772*955f2ea3SAbel Vesa .clkr = { 2773*955f2ea3SAbel Vesa .enable_reg = 0x7702c, 2774*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2775*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2776*955f2ea3SAbel Vesa .name = "gcc_ufs_phy_rx_symbol_0_clk", 2777*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2778*955f2ea3SAbel Vesa .hw = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 2779*955f2ea3SAbel Vesa }, 2780*955f2ea3SAbel Vesa .num_parents = 1, 2781*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2782*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2783*955f2ea3SAbel Vesa }, 2784*955f2ea3SAbel Vesa }, 2785*955f2ea3SAbel Vesa }; 2786*955f2ea3SAbel Vesa 2787*955f2ea3SAbel Vesa static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2788*955f2ea3SAbel Vesa .halt_reg = 0x770cc, 2789*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_DELAY, 2790*955f2ea3SAbel Vesa .clkr = { 2791*955f2ea3SAbel Vesa .enable_reg = 0x770cc, 2792*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2793*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2794*955f2ea3SAbel Vesa .name = "gcc_ufs_phy_rx_symbol_1_clk", 2795*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2796*955f2ea3SAbel Vesa .hw = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 2797*955f2ea3SAbel Vesa }, 2798*955f2ea3SAbel Vesa .num_parents = 1, 2799*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2800*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2801*955f2ea3SAbel Vesa }, 2802*955f2ea3SAbel Vesa }, 2803*955f2ea3SAbel Vesa }; 2804*955f2ea3SAbel Vesa 2805*955f2ea3SAbel Vesa static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2806*955f2ea3SAbel Vesa .halt_reg = 0x77028, 2807*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_DELAY, 2808*955f2ea3SAbel Vesa .clkr = { 2809*955f2ea3SAbel Vesa .enable_reg = 0x77028, 2810*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2811*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2812*955f2ea3SAbel Vesa .name = "gcc_ufs_phy_tx_symbol_0_clk", 2813*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2814*955f2ea3SAbel Vesa .hw = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 2815*955f2ea3SAbel Vesa }, 2816*955f2ea3SAbel Vesa .num_parents = 1, 2817*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2818*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2819*955f2ea3SAbel Vesa }, 2820*955f2ea3SAbel Vesa }, 2821*955f2ea3SAbel Vesa }; 2822*955f2ea3SAbel Vesa 2823*955f2ea3SAbel Vesa static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2824*955f2ea3SAbel Vesa .halt_reg = 0x77068, 2825*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2826*955f2ea3SAbel Vesa .hwcg_reg = 0x77068, 2827*955f2ea3SAbel Vesa .hwcg_bit = 1, 2828*955f2ea3SAbel Vesa .clkr = { 2829*955f2ea3SAbel Vesa .enable_reg = 0x77068, 2830*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2831*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2832*955f2ea3SAbel Vesa .name = "gcc_ufs_phy_unipro_core_clk", 2833*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2834*955f2ea3SAbel Vesa .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2835*955f2ea3SAbel Vesa }, 2836*955f2ea3SAbel Vesa .num_parents = 1, 2837*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2838*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2839*955f2ea3SAbel Vesa }, 2840*955f2ea3SAbel Vesa }, 2841*955f2ea3SAbel Vesa }; 2842*955f2ea3SAbel Vesa 2843*955f2ea3SAbel Vesa static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { 2844*955f2ea3SAbel Vesa .halt_reg = 0x77068, 2845*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_VOTED, 2846*955f2ea3SAbel Vesa .hwcg_reg = 0x77068, 2847*955f2ea3SAbel Vesa .hwcg_bit = 1, 2848*955f2ea3SAbel Vesa .clkr = { 2849*955f2ea3SAbel Vesa .enable_reg = 0x77068, 2850*955f2ea3SAbel Vesa .enable_mask = BIT(1), 2851*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2852*955f2ea3SAbel Vesa .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", 2853*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2854*955f2ea3SAbel Vesa .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2855*955f2ea3SAbel Vesa }, 2856*955f2ea3SAbel Vesa .num_parents = 1, 2857*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2858*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2859*955f2ea3SAbel Vesa }, 2860*955f2ea3SAbel Vesa }, 2861*955f2ea3SAbel Vesa }; 2862*955f2ea3SAbel Vesa 2863*955f2ea3SAbel Vesa static struct clk_branch gcc_usb30_prim_master_clk = { 2864*955f2ea3SAbel Vesa .halt_reg = 0x39018, 2865*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT, 2866*955f2ea3SAbel Vesa .clkr = { 2867*955f2ea3SAbel Vesa .enable_reg = 0x39018, 2868*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2869*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2870*955f2ea3SAbel Vesa .name = "gcc_usb30_prim_master_clk", 2871*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2872*955f2ea3SAbel Vesa .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 2873*955f2ea3SAbel Vesa }, 2874*955f2ea3SAbel Vesa .num_parents = 1, 2875*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2876*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2877*955f2ea3SAbel Vesa }, 2878*955f2ea3SAbel Vesa }, 2879*955f2ea3SAbel Vesa }; 2880*955f2ea3SAbel Vesa 2881*955f2ea3SAbel Vesa static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2882*955f2ea3SAbel Vesa .halt_reg = 0x39028, 2883*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT, 2884*955f2ea3SAbel Vesa .clkr = { 2885*955f2ea3SAbel Vesa .enable_reg = 0x39028, 2886*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2887*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2888*955f2ea3SAbel Vesa .name = "gcc_usb30_prim_mock_utmi_clk", 2889*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2890*955f2ea3SAbel Vesa .hw = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2891*955f2ea3SAbel Vesa }, 2892*955f2ea3SAbel Vesa .num_parents = 1, 2893*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2894*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2895*955f2ea3SAbel Vesa }, 2896*955f2ea3SAbel Vesa }, 2897*955f2ea3SAbel Vesa }; 2898*955f2ea3SAbel Vesa 2899*955f2ea3SAbel Vesa static struct clk_branch gcc_usb30_prim_sleep_clk = { 2900*955f2ea3SAbel Vesa .halt_reg = 0x39024, 2901*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT, 2902*955f2ea3SAbel Vesa .clkr = { 2903*955f2ea3SAbel Vesa .enable_reg = 0x39024, 2904*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2905*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2906*955f2ea3SAbel Vesa .name = "gcc_usb30_prim_sleep_clk", 2907*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2908*955f2ea3SAbel Vesa }, 2909*955f2ea3SAbel Vesa }, 2910*955f2ea3SAbel Vesa }; 2911*955f2ea3SAbel Vesa 2912*955f2ea3SAbel Vesa static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2913*955f2ea3SAbel Vesa .halt_reg = 0x39060, 2914*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT, 2915*955f2ea3SAbel Vesa .clkr = { 2916*955f2ea3SAbel Vesa .enable_reg = 0x39060, 2917*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2918*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2919*955f2ea3SAbel Vesa .name = "gcc_usb3_prim_phy_aux_clk", 2920*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2921*955f2ea3SAbel Vesa .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2922*955f2ea3SAbel Vesa }, 2923*955f2ea3SAbel Vesa .num_parents = 1, 2924*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2925*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2926*955f2ea3SAbel Vesa }, 2927*955f2ea3SAbel Vesa }, 2928*955f2ea3SAbel Vesa }; 2929*955f2ea3SAbel Vesa 2930*955f2ea3SAbel Vesa static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2931*955f2ea3SAbel Vesa .halt_reg = 0x39064, 2932*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT, 2933*955f2ea3SAbel Vesa .clkr = { 2934*955f2ea3SAbel Vesa .enable_reg = 0x39064, 2935*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2936*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2937*955f2ea3SAbel Vesa .name = "gcc_usb3_prim_phy_com_aux_clk", 2938*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2939*955f2ea3SAbel Vesa .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2940*955f2ea3SAbel Vesa }, 2941*955f2ea3SAbel Vesa .num_parents = 1, 2942*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2943*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2944*955f2ea3SAbel Vesa }, 2945*955f2ea3SAbel Vesa }, 2946*955f2ea3SAbel Vesa }; 2947*955f2ea3SAbel Vesa 2948*955f2ea3SAbel Vesa static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2949*955f2ea3SAbel Vesa .halt_reg = 0x39068, 2950*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_DELAY, 2951*955f2ea3SAbel Vesa .hwcg_reg = 0x39068, 2952*955f2ea3SAbel Vesa .hwcg_bit = 1, 2953*955f2ea3SAbel Vesa .clkr = { 2954*955f2ea3SAbel Vesa .enable_reg = 0x39068, 2955*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2956*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2957*955f2ea3SAbel Vesa .name = "gcc_usb3_prim_phy_pipe_clk", 2958*955f2ea3SAbel Vesa .parent_data = &(const struct clk_parent_data){ 2959*955f2ea3SAbel Vesa .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 2960*955f2ea3SAbel Vesa }, 2961*955f2ea3SAbel Vesa .num_parents = 1, 2962*955f2ea3SAbel Vesa .flags = CLK_SET_RATE_PARENT, 2963*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2964*955f2ea3SAbel Vesa }, 2965*955f2ea3SAbel Vesa }, 2966*955f2ea3SAbel Vesa }; 2967*955f2ea3SAbel Vesa 2968*955f2ea3SAbel Vesa static struct clk_branch gcc_video_axi0_clk = { 2969*955f2ea3SAbel Vesa .halt_reg = 0x32018, 2970*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_SKIP, 2971*955f2ea3SAbel Vesa .hwcg_reg = 0x32018, 2972*955f2ea3SAbel Vesa .hwcg_bit = 1, 2973*955f2ea3SAbel Vesa .clkr = { 2974*955f2ea3SAbel Vesa .enable_reg = 0x32018, 2975*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2976*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2977*955f2ea3SAbel Vesa .name = "gcc_video_axi0_clk", 2978*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2979*955f2ea3SAbel Vesa }, 2980*955f2ea3SAbel Vesa }, 2981*955f2ea3SAbel Vesa }; 2982*955f2ea3SAbel Vesa 2983*955f2ea3SAbel Vesa static struct clk_branch gcc_video_axi1_clk = { 2984*955f2ea3SAbel Vesa .halt_reg = 0x32024, 2985*955f2ea3SAbel Vesa .halt_check = BRANCH_HALT_SKIP, 2986*955f2ea3SAbel Vesa .hwcg_reg = 0x32024, 2987*955f2ea3SAbel Vesa .hwcg_bit = 1, 2988*955f2ea3SAbel Vesa .clkr = { 2989*955f2ea3SAbel Vesa .enable_reg = 0x32024, 2990*955f2ea3SAbel Vesa .enable_mask = BIT(0), 2991*955f2ea3SAbel Vesa .hw.init = &(struct clk_init_data){ 2992*955f2ea3SAbel Vesa .name = "gcc_video_axi1_clk", 2993*955f2ea3SAbel Vesa .ops = &clk_branch2_ops, 2994*955f2ea3SAbel Vesa }, 2995*955f2ea3SAbel Vesa }, 2996*955f2ea3SAbel Vesa }; 2997*955f2ea3SAbel Vesa 2998*955f2ea3SAbel Vesa static struct gdsc pcie_0_gdsc = { 2999*955f2ea3SAbel Vesa .gdscr = 0x6b004, 3000*955f2ea3SAbel Vesa .pd = { 3001*955f2ea3SAbel Vesa .name = "pcie_0_gdsc", 3002*955f2ea3SAbel Vesa }, 3003*955f2ea3SAbel Vesa .pwrsts = PWRSTS_OFF_ON, 3004*955f2ea3SAbel Vesa .flags = POLL_CFG_GDSCR, 3005*955f2ea3SAbel Vesa }; 3006*955f2ea3SAbel Vesa 3007*955f2ea3SAbel Vesa static struct gdsc pcie_0_phy_gdsc = { 3008*955f2ea3SAbel Vesa .gdscr = 0x6c000, 3009*955f2ea3SAbel Vesa .pd = { 3010*955f2ea3SAbel Vesa .name = "pcie_0_phy_gdsc", 3011*955f2ea3SAbel Vesa }, 3012*955f2ea3SAbel Vesa .pwrsts = PWRSTS_OFF_ON, 3013*955f2ea3SAbel Vesa .flags = POLL_CFG_GDSCR, 3014*955f2ea3SAbel Vesa }; 3015*955f2ea3SAbel Vesa 3016*955f2ea3SAbel Vesa static struct gdsc pcie_1_gdsc = { 3017*955f2ea3SAbel Vesa .gdscr = 0x8d004, 3018*955f2ea3SAbel Vesa .pd = { 3019*955f2ea3SAbel Vesa .name = "pcie_1_gdsc", 3020*955f2ea3SAbel Vesa }, 3021*955f2ea3SAbel Vesa .pwrsts = PWRSTS_OFF_ON, 3022*955f2ea3SAbel Vesa .flags = POLL_CFG_GDSCR, 3023*955f2ea3SAbel Vesa }; 3024*955f2ea3SAbel Vesa 3025*955f2ea3SAbel Vesa static struct gdsc pcie_1_phy_gdsc = { 3026*955f2ea3SAbel Vesa .gdscr = 0x8e000, 3027*955f2ea3SAbel Vesa .pd = { 3028*955f2ea3SAbel Vesa .name = "pcie_1_phy_gdsc", 3029*955f2ea3SAbel Vesa }, 3030*955f2ea3SAbel Vesa .pwrsts = PWRSTS_OFF_ON, 3031*955f2ea3SAbel Vesa .flags = POLL_CFG_GDSCR, 3032*955f2ea3SAbel Vesa }; 3033*955f2ea3SAbel Vesa 3034*955f2ea3SAbel Vesa static struct gdsc ufs_phy_gdsc = { 3035*955f2ea3SAbel Vesa .gdscr = 0x77004, 3036*955f2ea3SAbel Vesa .pd = { 3037*955f2ea3SAbel Vesa .name = "ufs_phy_gdsc", 3038*955f2ea3SAbel Vesa }, 3039*955f2ea3SAbel Vesa .pwrsts = PWRSTS_OFF_ON, 3040*955f2ea3SAbel Vesa .flags = POLL_CFG_GDSCR, 3041*955f2ea3SAbel Vesa }; 3042*955f2ea3SAbel Vesa 3043*955f2ea3SAbel Vesa static struct gdsc ufs_mem_phy_gdsc = { 3044*955f2ea3SAbel Vesa .gdscr = 0x9e000, 3045*955f2ea3SAbel Vesa .pd = { 3046*955f2ea3SAbel Vesa .name = "ufs_mem_phy_gdsc", 3047*955f2ea3SAbel Vesa }, 3048*955f2ea3SAbel Vesa .pwrsts = PWRSTS_OFF_ON, 3049*955f2ea3SAbel Vesa .flags = POLL_CFG_GDSCR, 3050*955f2ea3SAbel Vesa }; 3051*955f2ea3SAbel Vesa 3052*955f2ea3SAbel Vesa static struct gdsc usb30_prim_gdsc = { 3053*955f2ea3SAbel Vesa .gdscr = 0x39004, 3054*955f2ea3SAbel Vesa .pd = { 3055*955f2ea3SAbel Vesa .name = "usb30_prim_gdsc", 3056*955f2ea3SAbel Vesa }, 3057*955f2ea3SAbel Vesa .pwrsts = PWRSTS_OFF_ON, 3058*955f2ea3SAbel Vesa .flags = POLL_CFG_GDSCR, 3059*955f2ea3SAbel Vesa }; 3060*955f2ea3SAbel Vesa 3061*955f2ea3SAbel Vesa static struct gdsc usb3_phy_gdsc = { 3062*955f2ea3SAbel Vesa .gdscr = 0x50018, 3063*955f2ea3SAbel Vesa .pd = { 3064*955f2ea3SAbel Vesa .name = "usb3_phy_gdsc", 3065*955f2ea3SAbel Vesa }, 3066*955f2ea3SAbel Vesa .pwrsts = PWRSTS_OFF_ON, 3067*955f2ea3SAbel Vesa .flags = POLL_CFG_GDSCR, 3068*955f2ea3SAbel Vesa }; 3069*955f2ea3SAbel Vesa 3070*955f2ea3SAbel Vesa static struct clk_regmap *gcc_sm8550_clocks[] = { 3071*955f2ea3SAbel Vesa [GCC_AGGRE_NOC_PCIE_AXI_CLK] = &gcc_aggre_noc_pcie_axi_clk.clkr, 3072*955f2ea3SAbel Vesa [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 3073*955f2ea3SAbel Vesa [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, 3074*955f2ea3SAbel Vesa [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 3075*955f2ea3SAbel Vesa [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3076*955f2ea3SAbel Vesa [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 3077*955f2ea3SAbel Vesa [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 3078*955f2ea3SAbel Vesa [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr, 3079*955f2ea3SAbel Vesa [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3080*955f2ea3SAbel Vesa [GCC_CNOC_PCIE_SF_AXI_CLK] = &gcc_cnoc_pcie_sf_axi_clk.clkr, 3081*955f2ea3SAbel Vesa [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 3082*955f2ea3SAbel Vesa [GCC_DDRSS_PCIE_SF_QTB_CLK] = &gcc_ddrss_pcie_sf_qtb_clk.clkr, 3083*955f2ea3SAbel Vesa [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3084*955f2ea3SAbel Vesa [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3085*955f2ea3SAbel Vesa [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3086*955f2ea3SAbel Vesa [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3087*955f2ea3SAbel Vesa [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3088*955f2ea3SAbel Vesa [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3089*955f2ea3SAbel Vesa [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3090*955f2ea3SAbel Vesa [GCC_GPLL0] = &gcc_gpll0.clkr, 3091*955f2ea3SAbel Vesa [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 3092*955f2ea3SAbel Vesa [GCC_GPLL4] = &gcc_gpll4.clkr, 3093*955f2ea3SAbel Vesa [GCC_GPLL7] = &gcc_gpll7.clkr, 3094*955f2ea3SAbel Vesa [GCC_GPLL9] = &gcc_gpll9.clkr, 3095*955f2ea3SAbel Vesa [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3096*955f2ea3SAbel Vesa [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3097*955f2ea3SAbel Vesa [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3098*955f2ea3SAbel Vesa [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3099*955f2ea3SAbel Vesa [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3100*955f2ea3SAbel Vesa [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 3101*955f2ea3SAbel Vesa [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3102*955f2ea3SAbel Vesa [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3103*955f2ea3SAbel Vesa [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 3104*955f2ea3SAbel Vesa [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 3105*955f2ea3SAbel Vesa [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3106*955f2ea3SAbel Vesa [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 3107*955f2ea3SAbel Vesa [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3108*955f2ea3SAbel Vesa [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 3109*955f2ea3SAbel Vesa [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 3110*955f2ea3SAbel Vesa [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 3111*955f2ea3SAbel Vesa [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 3112*955f2ea3SAbel Vesa [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 3113*955f2ea3SAbel Vesa [GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr, 3114*955f2ea3SAbel Vesa [GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr, 3115*955f2ea3SAbel Vesa [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr, 3116*955f2ea3SAbel Vesa [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 3117*955f2ea3SAbel Vesa [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 3118*955f2ea3SAbel Vesa [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr, 3119*955f2ea3SAbel Vesa [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 3120*955f2ea3SAbel Vesa [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 3121*955f2ea3SAbel Vesa [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3122*955f2ea3SAbel Vesa [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3123*955f2ea3SAbel Vesa [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3124*955f2ea3SAbel Vesa [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3125*955f2ea3SAbel Vesa [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3126*955f2ea3SAbel Vesa [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3127*955f2ea3SAbel Vesa [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3128*955f2ea3SAbel Vesa [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr, 3129*955f2ea3SAbel Vesa [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr, 3130*955f2ea3SAbel Vesa [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr, 3131*955f2ea3SAbel Vesa [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 3132*955f2ea3SAbel Vesa [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr, 3133*955f2ea3SAbel Vesa [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3134*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_CORE_CLK] = &gcc_qupv3_i2c_core_clk.clkr, 3135*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S0_CLK] = &gcc_qupv3_i2c_s0_clk.clkr, 3136*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S0_CLK_SRC] = &gcc_qupv3_i2c_s0_clk_src.clkr, 3137*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S1_CLK] = &gcc_qupv3_i2c_s1_clk.clkr, 3138*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S1_CLK_SRC] = &gcc_qupv3_i2c_s1_clk_src.clkr, 3139*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S2_CLK] = &gcc_qupv3_i2c_s2_clk.clkr, 3140*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S2_CLK_SRC] = &gcc_qupv3_i2c_s2_clk_src.clkr, 3141*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S3_CLK] = &gcc_qupv3_i2c_s3_clk.clkr, 3142*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S3_CLK_SRC] = &gcc_qupv3_i2c_s3_clk_src.clkr, 3143*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S4_CLK] = &gcc_qupv3_i2c_s4_clk.clkr, 3144*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S4_CLK_SRC] = &gcc_qupv3_i2c_s4_clk_src.clkr, 3145*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S5_CLK] = &gcc_qupv3_i2c_s5_clk.clkr, 3146*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S5_CLK_SRC] = &gcc_qupv3_i2c_s5_clk_src.clkr, 3147*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S6_CLK] = &gcc_qupv3_i2c_s6_clk.clkr, 3148*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S6_CLK_SRC] = &gcc_qupv3_i2c_s6_clk_src.clkr, 3149*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S7_CLK] = &gcc_qupv3_i2c_s7_clk.clkr, 3150*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S7_CLK_SRC] = &gcc_qupv3_i2c_s7_clk_src.clkr, 3151*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S8_CLK] = &gcc_qupv3_i2c_s8_clk.clkr, 3152*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S8_CLK_SRC] = &gcc_qupv3_i2c_s8_clk_src.clkr, 3153*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S9_CLK] = &gcc_qupv3_i2c_s9_clk.clkr, 3154*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S9_CLK_SRC] = &gcc_qupv3_i2c_s9_clk_src.clkr, 3155*955f2ea3SAbel Vesa [GCC_QUPV3_I2C_S_AHB_CLK] = &gcc_qupv3_i2c_s_ahb_clk.clkr, 3156*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3157*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3158*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3159*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3160*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3161*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3162*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3163*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3164*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3165*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3166*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3167*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3168*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3169*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3170*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 3171*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 3172*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 3173*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 3174*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 3175*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 3176*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 3177*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 3178*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 3179*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 3180*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 3181*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 3182*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 3183*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 3184*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 3185*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 3186*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 3187*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 3188*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr, 3189*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr, 3190*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr, 3191*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr, 3192*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3193*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3194*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 3195*955f2ea3SAbel Vesa [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 3196*955f2ea3SAbel Vesa [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3197*955f2ea3SAbel Vesa [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3198*955f2ea3SAbel Vesa [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3199*955f2ea3SAbel Vesa [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3200*955f2ea3SAbel Vesa [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3201*955f2ea3SAbel Vesa [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 3202*955f2ea3SAbel Vesa [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3203*955f2ea3SAbel Vesa [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3204*955f2ea3SAbel Vesa [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3205*955f2ea3SAbel Vesa [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, 3206*955f2ea3SAbel Vesa [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3207*955f2ea3SAbel Vesa [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3208*955f2ea3SAbel Vesa [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, 3209*955f2ea3SAbel Vesa [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3210*955f2ea3SAbel Vesa [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3211*955f2ea3SAbel Vesa [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, 3212*955f2ea3SAbel Vesa [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3213*955f2ea3SAbel Vesa [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 3214*955f2ea3SAbel Vesa [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3215*955f2ea3SAbel Vesa [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 3216*955f2ea3SAbel Vesa [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3217*955f2ea3SAbel Vesa [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 3218*955f2ea3SAbel Vesa [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3219*955f2ea3SAbel Vesa [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 3220*955f2ea3SAbel Vesa [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, 3221*955f2ea3SAbel Vesa [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3222*955f2ea3SAbel Vesa [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3223*955f2ea3SAbel Vesa [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3224*955f2ea3SAbel Vesa [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3225*955f2ea3SAbel Vesa [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3226*955f2ea3SAbel Vesa [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3227*955f2ea3SAbel Vesa [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3228*955f2ea3SAbel Vesa [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3229*955f2ea3SAbel Vesa [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3230*955f2ea3SAbel Vesa [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3231*955f2ea3SAbel Vesa [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 3232*955f2ea3SAbel Vesa [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3233*955f2ea3SAbel Vesa [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 3234*955f2ea3SAbel Vesa }; 3235*955f2ea3SAbel Vesa 3236*955f2ea3SAbel Vesa static const struct qcom_reset_map gcc_sm8550_resets[] = { 3237*955f2ea3SAbel Vesa [GCC_CAMERA_BCR] = { 0x26000 }, 3238*955f2ea3SAbel Vesa [GCC_DISPLAY_BCR] = { 0x27000 }, 3239*955f2ea3SAbel Vesa [GCC_GPU_BCR] = { 0x71000 }, 3240*955f2ea3SAbel Vesa [GCC_PCIE_0_BCR] = { 0x6b000 }, 3241*955f2ea3SAbel Vesa [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 3242*955f2ea3SAbel Vesa [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 3243*955f2ea3SAbel Vesa [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3244*955f2ea3SAbel Vesa [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, 3245*955f2ea3SAbel Vesa [GCC_PCIE_1_BCR] = { 0x8d000 }, 3246*955f2ea3SAbel Vesa [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, 3247*955f2ea3SAbel Vesa [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, 3248*955f2ea3SAbel Vesa [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 3249*955f2ea3SAbel Vesa [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 }, 3250*955f2ea3SAbel Vesa [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 3251*955f2ea3SAbel Vesa [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, 3252*955f2ea3SAbel Vesa [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, 3253*955f2ea3SAbel Vesa [GCC_PDM_BCR] = { 0x33000 }, 3254*955f2ea3SAbel Vesa [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 3255*955f2ea3SAbel Vesa [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, 3256*955f2ea3SAbel Vesa [GCC_QUPV3_WRAPPER_I2C_BCR] = { 0x17000 }, 3257*955f2ea3SAbel Vesa [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3258*955f2ea3SAbel Vesa [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3259*955f2ea3SAbel Vesa [GCC_SDCC2_BCR] = { 0x14000 }, 3260*955f2ea3SAbel Vesa [GCC_SDCC4_BCR] = { 0x16000 }, 3261*955f2ea3SAbel Vesa [GCC_UFS_PHY_BCR] = { 0x77000 }, 3262*955f2ea3SAbel Vesa [GCC_USB30_PRIM_BCR] = { 0x39000 }, 3263*955f2ea3SAbel Vesa [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 3264*955f2ea3SAbel Vesa [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 3265*955f2ea3SAbel Vesa [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 3266*955f2ea3SAbel Vesa [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 3267*955f2ea3SAbel Vesa [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3268*955f2ea3SAbel Vesa [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3269*955f2ea3SAbel Vesa [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 3270*955f2ea3SAbel Vesa [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 }, 3271*955f2ea3SAbel Vesa [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32024, 2 }, 3272*955f2ea3SAbel Vesa [GCC_VIDEO_BCR] = { 0x32000 }, 3273*955f2ea3SAbel Vesa }; 3274*955f2ea3SAbel Vesa 3275*955f2ea3SAbel Vesa static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3276*955f2ea3SAbel Vesa DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3277*955f2ea3SAbel Vesa DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3278*955f2ea3SAbel Vesa DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 3279*955f2ea3SAbel Vesa DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3280*955f2ea3SAbel Vesa DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3281*955f2ea3SAbel Vesa DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3282*955f2ea3SAbel Vesa DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 3283*955f2ea3SAbel Vesa DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 3284*955f2ea3SAbel Vesa DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 3285*955f2ea3SAbel Vesa DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 3286*955f2ea3SAbel Vesa DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 3287*955f2ea3SAbel Vesa DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 3288*955f2ea3SAbel Vesa DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 3289*955f2ea3SAbel Vesa DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 3290*955f2ea3SAbel Vesa DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src), 3291*955f2ea3SAbel Vesa DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src), 3292*955f2ea3SAbel Vesa }; 3293*955f2ea3SAbel Vesa 3294*955f2ea3SAbel Vesa static struct gdsc *gcc_sm8550_gdscs[] = { 3295*955f2ea3SAbel Vesa [PCIE_0_GDSC] = &pcie_0_gdsc, 3296*955f2ea3SAbel Vesa [PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc, 3297*955f2ea3SAbel Vesa [PCIE_1_GDSC] = &pcie_1_gdsc, 3298*955f2ea3SAbel Vesa [PCIE_1_PHY_GDSC] = &pcie_1_phy_gdsc, 3299*955f2ea3SAbel Vesa [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3300*955f2ea3SAbel Vesa [UFS_MEM_PHY_GDSC] = &ufs_mem_phy_gdsc, 3301*955f2ea3SAbel Vesa [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3302*955f2ea3SAbel Vesa [USB3_PHY_GDSC] = &usb3_phy_gdsc, 3303*955f2ea3SAbel Vesa }; 3304*955f2ea3SAbel Vesa 3305*955f2ea3SAbel Vesa static const struct regmap_config gcc_sm8550_regmap_config = { 3306*955f2ea3SAbel Vesa .reg_bits = 32, 3307*955f2ea3SAbel Vesa .reg_stride = 4, 3308*955f2ea3SAbel Vesa .val_bits = 32, 3309*955f2ea3SAbel Vesa .max_register = 0x1f41f0, 3310*955f2ea3SAbel Vesa .fast_io = true, 3311*955f2ea3SAbel Vesa }; 3312*955f2ea3SAbel Vesa 3313*955f2ea3SAbel Vesa static const struct qcom_cc_desc gcc_sm8550_desc = { 3314*955f2ea3SAbel Vesa .config = &gcc_sm8550_regmap_config, 3315*955f2ea3SAbel Vesa .clks = gcc_sm8550_clocks, 3316*955f2ea3SAbel Vesa .num_clks = ARRAY_SIZE(gcc_sm8550_clocks), 3317*955f2ea3SAbel Vesa .resets = gcc_sm8550_resets, 3318*955f2ea3SAbel Vesa .num_resets = ARRAY_SIZE(gcc_sm8550_resets), 3319*955f2ea3SAbel Vesa .gdscs = gcc_sm8550_gdscs, 3320*955f2ea3SAbel Vesa .num_gdscs = ARRAY_SIZE(gcc_sm8550_gdscs), 3321*955f2ea3SAbel Vesa }; 3322*955f2ea3SAbel Vesa 3323*955f2ea3SAbel Vesa static const struct of_device_id gcc_sm8550_match_table[] = { 3324*955f2ea3SAbel Vesa { .compatible = "qcom,sm8550-gcc" }, 3325*955f2ea3SAbel Vesa { } 3326*955f2ea3SAbel Vesa }; 3327*955f2ea3SAbel Vesa MODULE_DEVICE_TABLE(of, gcc_sm8550_match_table); 3328*955f2ea3SAbel Vesa 3329*955f2ea3SAbel Vesa static int gcc_sm8550_probe(struct platform_device *pdev) 3330*955f2ea3SAbel Vesa { 3331*955f2ea3SAbel Vesa struct regmap *regmap; 3332*955f2ea3SAbel Vesa int ret; 3333*955f2ea3SAbel Vesa 3334*955f2ea3SAbel Vesa regmap = qcom_cc_map(pdev, &gcc_sm8550_desc); 3335*955f2ea3SAbel Vesa if (IS_ERR(regmap)) 3336*955f2ea3SAbel Vesa return PTR_ERR(regmap); 3337*955f2ea3SAbel Vesa 3338*955f2ea3SAbel Vesa ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3339*955f2ea3SAbel Vesa ARRAY_SIZE(gcc_dfs_clocks)); 3340*955f2ea3SAbel Vesa if (ret) 3341*955f2ea3SAbel Vesa return ret; 3342*955f2ea3SAbel Vesa 3343*955f2ea3SAbel Vesa /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ 3344*955f2ea3SAbel Vesa regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14)); 3345*955f2ea3SAbel Vesa 3346*955f2ea3SAbel Vesa /* 3347*955f2ea3SAbel Vesa * Keep the critical clock always-On 3348*955f2ea3SAbel Vesa * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk, 3349*955f2ea3SAbel Vesa * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, 3350*955f2ea3SAbel Vesa * gcc_video_xo_clk 3351*955f2ea3SAbel Vesa */ 3352*955f2ea3SAbel Vesa regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); 3353*955f2ea3SAbel Vesa regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); 3354*955f2ea3SAbel Vesa regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); 3355*955f2ea3SAbel Vesa regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); 3356*955f2ea3SAbel Vesa regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 3357*955f2ea3SAbel Vesa regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); 3358*955f2ea3SAbel Vesa regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); 3359*955f2ea3SAbel Vesa 3360*955f2ea3SAbel Vesa /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ 3361*955f2ea3SAbel Vesa regmap_write(regmap, 0x52024, 0x0); 3362*955f2ea3SAbel Vesa 3363*955f2ea3SAbel Vesa return qcom_cc_really_probe(pdev, &gcc_sm8550_desc, regmap); 3364*955f2ea3SAbel Vesa } 3365*955f2ea3SAbel Vesa 3366*955f2ea3SAbel Vesa static struct platform_driver gcc_sm8550_driver = { 3367*955f2ea3SAbel Vesa .probe = gcc_sm8550_probe, 3368*955f2ea3SAbel Vesa .driver = { 3369*955f2ea3SAbel Vesa .name = "gcc-sm8550", 3370*955f2ea3SAbel Vesa .of_match_table = gcc_sm8550_match_table, 3371*955f2ea3SAbel Vesa }, 3372*955f2ea3SAbel Vesa }; 3373*955f2ea3SAbel Vesa 3374*955f2ea3SAbel Vesa static int __init gcc_sm8550_init(void) 3375*955f2ea3SAbel Vesa { 3376*955f2ea3SAbel Vesa return platform_driver_register(&gcc_sm8550_driver); 3377*955f2ea3SAbel Vesa } 3378*955f2ea3SAbel Vesa subsys_initcall(gcc_sm8550_init); 3379*955f2ea3SAbel Vesa 3380*955f2ea3SAbel Vesa static void __exit gcc_sm8550_exit(void) 3381*955f2ea3SAbel Vesa { 3382*955f2ea3SAbel Vesa platform_driver_unregister(&gcc_sm8550_driver); 3383*955f2ea3SAbel Vesa } 3384*955f2ea3SAbel Vesa module_exit(gcc_sm8550_exit); 3385*955f2ea3SAbel Vesa 3386*955f2ea3SAbel Vesa MODULE_DESCRIPTION("QTI GCC SM8550 Driver"); 3387*955f2ea3SAbel Vesa MODULE_LICENSE("GPL"); 3388