1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, Linaro Limited 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/module.h> 9 #include <linux/of_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,gcc-sm8450.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "clk-regmap-divider.h" 19 #include "clk-regmap-mux.h" 20 #include "clk-regmap-phy-mux.h" 21 #include "gdsc.h" 22 #include "reset.h" 23 24 enum { 25 P_BI_TCXO, 26 P_GCC_GPLL0_OUT_EVEN, 27 P_GCC_GPLL0_OUT_MAIN, 28 P_GCC_GPLL4_OUT_MAIN, 29 P_GCC_GPLL9_OUT_MAIN, 30 P_PCIE_1_PHY_AUX_CLK, 31 P_SLEEP_CLK, 32 P_UFS_PHY_RX_SYMBOL_0_CLK, 33 P_UFS_PHY_RX_SYMBOL_1_CLK, 34 P_UFS_PHY_TX_SYMBOL_0_CLK, 35 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 36 }; 37 38 static struct clk_alpha_pll gcc_gpll0 = { 39 .offset = 0x0, 40 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 41 .clkr = { 42 .enable_reg = 0x62018, 43 .enable_mask = BIT(0), 44 .hw.init = &(struct clk_init_data){ 45 .name = "gcc_gpll0", 46 .parent_data = &(const struct clk_parent_data){ 47 .fw_name = "bi_tcxo", 48 }, 49 .num_parents = 1, 50 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 51 }, 52 }, 53 }; 54 55 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 56 { 0x1, 2 }, 57 { } 58 }; 59 60 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 61 .offset = 0x0, 62 .post_div_shift = 10, 63 .post_div_table = post_div_table_gcc_gpll0_out_even, 64 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 65 .width = 4, 66 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 67 .clkr.hw.init = &(struct clk_init_data){ 68 .name = "gcc_gpll0_out_even", 69 .parent_hws = (const struct clk_hw*[]) { 70 &gcc_gpll0.clkr.hw, 71 }, 72 .num_parents = 1, 73 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 74 }, 75 }; 76 77 static struct clk_alpha_pll gcc_gpll4 = { 78 .offset = 0x4000, 79 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 80 .clkr = { 81 .enable_reg = 0x62018, 82 .enable_mask = BIT(4), 83 .hw.init = &(struct clk_init_data){ 84 .name = "gcc_gpll4", 85 .parent_data = &(const struct clk_parent_data){ 86 .fw_name = "bi_tcxo", 87 }, 88 .num_parents = 1, 89 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 90 }, 91 }, 92 }; 93 94 static struct clk_alpha_pll gcc_gpll9 = { 95 .offset = 0x9000, 96 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 97 .clkr = { 98 .enable_reg = 0x62018, 99 .enable_mask = BIT(9), 100 .hw.init = &(struct clk_init_data){ 101 .name = "gcc_gpll9", 102 .parent_data = &(const struct clk_parent_data){ 103 .fw_name = "bi_tcxo", 104 }, 105 .num_parents = 1, 106 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 107 }, 108 }, 109 }; 110 111 static const struct parent_map gcc_parent_map_0[] = { 112 { P_BI_TCXO, 0 }, 113 { P_GCC_GPLL0_OUT_MAIN, 1 }, 114 { P_GCC_GPLL0_OUT_EVEN, 6 }, 115 }; 116 117 static const struct clk_parent_data gcc_parent_data_0[] = { 118 { .fw_name = "bi_tcxo" }, 119 { .hw = &gcc_gpll0.clkr.hw }, 120 { .hw = &gcc_gpll0_out_even.clkr.hw }, 121 }; 122 123 static const struct parent_map gcc_parent_map_1[] = { 124 { P_BI_TCXO, 0 }, 125 { P_GCC_GPLL0_OUT_MAIN, 1 }, 126 { P_SLEEP_CLK, 5 }, 127 { P_GCC_GPLL0_OUT_EVEN, 6 }, 128 }; 129 130 static const struct clk_parent_data gcc_parent_data_1[] = { 131 { .fw_name = "bi_tcxo" }, 132 { .hw = &gcc_gpll0.clkr.hw }, 133 { .fw_name = "sleep_clk" }, 134 { .hw = &gcc_gpll0_out_even.clkr.hw }, 135 }; 136 137 static const struct parent_map gcc_parent_map_2[] = { 138 { P_BI_TCXO, 0 }, 139 { P_SLEEP_CLK, 5 }, 140 }; 141 142 static const struct clk_parent_data gcc_parent_data_2[] = { 143 { .fw_name = "bi_tcxo" }, 144 { .fw_name = "sleep_clk" }, 145 }; 146 147 static const struct parent_map gcc_parent_map_3[] = { 148 { P_BI_TCXO, 0 }, 149 }; 150 151 static const struct clk_parent_data gcc_parent_data_3[] = { 152 { .fw_name = "bi_tcxo" }, 153 }; 154 155 static const struct parent_map gcc_parent_map_5[] = { 156 { P_PCIE_1_PHY_AUX_CLK, 0 }, 157 { P_BI_TCXO, 2 }, 158 }; 159 160 static const struct clk_parent_data gcc_parent_data_5[] = { 161 { .fw_name = "pcie_1_phy_aux_clk" }, 162 { .fw_name = "bi_tcxo" }, 163 }; 164 165 static const struct parent_map gcc_parent_map_7[] = { 166 { P_BI_TCXO, 0 }, 167 { P_GCC_GPLL0_OUT_MAIN, 1 }, 168 { P_GCC_GPLL9_OUT_MAIN, 2 }, 169 { P_GCC_GPLL4_OUT_MAIN, 5 }, 170 { P_GCC_GPLL0_OUT_EVEN, 6 }, 171 }; 172 173 static const struct clk_parent_data gcc_parent_data_7[] = { 174 { .fw_name = "bi_tcxo" }, 175 { .hw = &gcc_gpll0.clkr.hw }, 176 { .hw = &gcc_gpll9.clkr.hw }, 177 { .hw = &gcc_gpll4.clkr.hw }, 178 { .hw = &gcc_gpll0_out_even.clkr.hw }, 179 }; 180 181 static const struct parent_map gcc_parent_map_8[] = { 182 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, 183 { P_BI_TCXO, 2 }, 184 }; 185 186 static const struct clk_parent_data gcc_parent_data_8[] = { 187 { .fw_name = "ufs_phy_rx_symbol_0_clk" }, 188 { .fw_name = "bi_tcxo" }, 189 }; 190 191 static const struct parent_map gcc_parent_map_9[] = { 192 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, 193 { P_BI_TCXO, 2 }, 194 }; 195 196 static const struct clk_parent_data gcc_parent_data_9[] = { 197 { .fw_name = "ufs_phy_rx_symbol_1_clk" }, 198 { .fw_name = "bi_tcxo" }, 199 }; 200 201 static const struct parent_map gcc_parent_map_10[] = { 202 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, 203 { P_BI_TCXO, 2 }, 204 }; 205 206 static const struct clk_parent_data gcc_parent_data_10[] = { 207 { .fw_name = "ufs_phy_tx_symbol_0_clk" }, 208 { .fw_name = "bi_tcxo" }, 209 }; 210 211 static const struct parent_map gcc_parent_map_11[] = { 212 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 213 { P_BI_TCXO, 2 }, 214 }; 215 216 static const struct clk_parent_data gcc_parent_data_11[] = { 217 { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" }, 218 { .fw_name = "bi_tcxo" }, 219 }; 220 221 static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { 222 .reg = 0x7b060, 223 .clkr = { 224 .hw.init = &(struct clk_init_data){ 225 .name = "gcc_pcie_0_pipe_clk_src", 226 .parent_data = &(const struct clk_parent_data){ 227 .fw_name = "pcie_0_pipe_clk", 228 }, 229 .num_parents = 1, 230 .ops = &clk_regmap_phy_mux_ops, 231 }, 232 }, 233 }; 234 235 static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = { 236 .reg = 0x9d080, 237 .shift = 0, 238 .width = 2, 239 .parent_map = gcc_parent_map_5, 240 .clkr = { 241 .hw.init = &(struct clk_init_data){ 242 .name = "gcc_pcie_1_phy_aux_clk_src", 243 .parent_data = gcc_parent_data_5, 244 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 245 .ops = &clk_regmap_mux_closest_ops, 246 }, 247 }, 248 }; 249 250 static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = { 251 .reg = 0x9d064, 252 .clkr = { 253 .hw.init = &(struct clk_init_data){ 254 .name = "gcc_pcie_1_pipe_clk_src", 255 .parent_data = &(const struct clk_parent_data){ 256 .fw_name = "pcie_1_pipe_clk", 257 }, 258 .num_parents = 1, 259 .ops = &clk_regmap_phy_mux_ops, 260 }, 261 }, 262 }; 263 264 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 265 .reg = 0x87060, 266 .shift = 0, 267 .width = 2, 268 .parent_map = gcc_parent_map_8, 269 .clkr = { 270 .hw.init = &(struct clk_init_data){ 271 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 272 .parent_data = gcc_parent_data_8, 273 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 274 .ops = &clk_regmap_mux_closest_ops, 275 }, 276 }, 277 }; 278 279 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 280 .reg = 0x870d0, 281 .shift = 0, 282 .width = 2, 283 .parent_map = gcc_parent_map_9, 284 .clkr = { 285 .hw.init = &(struct clk_init_data){ 286 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 287 .parent_data = gcc_parent_data_9, 288 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 289 .ops = &clk_regmap_mux_closest_ops, 290 }, 291 }, 292 }; 293 294 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 295 .reg = 0x87050, 296 .shift = 0, 297 .width = 2, 298 .parent_map = gcc_parent_map_10, 299 .clkr = { 300 .hw.init = &(struct clk_init_data){ 301 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 302 .parent_data = gcc_parent_data_10, 303 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 304 .ops = &clk_regmap_mux_closest_ops, 305 }, 306 }, 307 }; 308 309 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 310 .reg = 0x49068, 311 .shift = 0, 312 .width = 2, 313 .parent_map = gcc_parent_map_11, 314 .clkr = { 315 .hw.init = &(struct clk_init_data){ 316 .name = "gcc_usb3_prim_phy_pipe_clk_src", 317 .parent_data = gcc_parent_data_11, 318 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 319 .ops = &clk_regmap_mux_closest_ops, 320 }, 321 }, 322 }; 323 324 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 325 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 326 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 327 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 328 { } 329 }; 330 331 static struct clk_rcg2 gcc_gp1_clk_src = { 332 .cmd_rcgr = 0x74004, 333 .mnd_width = 8, 334 .hid_width = 5, 335 .parent_map = gcc_parent_map_1, 336 .freq_tbl = ftbl_gcc_gp1_clk_src, 337 .hw_clk_ctrl = true, 338 .clkr.hw.init = &(struct clk_init_data){ 339 .name = "gcc_gp1_clk_src", 340 .parent_data = gcc_parent_data_1, 341 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 342 .flags = CLK_SET_RATE_PARENT, 343 .ops = &clk_rcg2_ops, 344 }, 345 }; 346 347 static struct clk_rcg2 gcc_gp2_clk_src = { 348 .cmd_rcgr = 0x75004, 349 .mnd_width = 8, 350 .hid_width = 5, 351 .parent_map = gcc_parent_map_1, 352 .freq_tbl = ftbl_gcc_gp1_clk_src, 353 .hw_clk_ctrl = true, 354 .clkr.hw.init = &(struct clk_init_data){ 355 .name = "gcc_gp2_clk_src", 356 .parent_data = gcc_parent_data_1, 357 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 358 .flags = CLK_SET_RATE_PARENT, 359 .ops = &clk_rcg2_ops, 360 }, 361 }; 362 363 static struct clk_rcg2 gcc_gp3_clk_src = { 364 .cmd_rcgr = 0x76004, 365 .mnd_width = 8, 366 .hid_width = 5, 367 .parent_map = gcc_parent_map_1, 368 .freq_tbl = ftbl_gcc_gp1_clk_src, 369 .hw_clk_ctrl = true, 370 .clkr.hw.init = &(struct clk_init_data){ 371 .name = "gcc_gp3_clk_src", 372 .parent_data = gcc_parent_data_1, 373 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 374 .flags = CLK_SET_RATE_PARENT, 375 .ops = &clk_rcg2_ops, 376 }, 377 }; 378 379 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 380 F(19200000, P_BI_TCXO, 1, 0, 0), 381 { } 382 }; 383 384 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 385 .cmd_rcgr = 0x7b064, 386 .mnd_width = 16, 387 .hid_width = 5, 388 .parent_map = gcc_parent_map_2, 389 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 390 .hw_clk_ctrl = true, 391 .clkr.hw.init = &(struct clk_init_data){ 392 .name = "gcc_pcie_0_aux_clk_src", 393 .parent_data = gcc_parent_data_2, 394 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 395 .flags = CLK_SET_RATE_PARENT, 396 .ops = &clk_rcg2_ops, 397 }, 398 }; 399 400 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 401 F(19200000, P_BI_TCXO, 1, 0, 0), 402 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 403 { } 404 }; 405 406 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 407 .cmd_rcgr = 0x7b048, 408 .mnd_width = 0, 409 .hid_width = 5, 410 .parent_map = gcc_parent_map_0, 411 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 412 .hw_clk_ctrl = true, 413 .clkr.hw.init = &(struct clk_init_data){ 414 .name = "gcc_pcie_0_phy_rchng_clk_src", 415 .parent_data = gcc_parent_data_0, 416 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 417 .flags = CLK_SET_RATE_PARENT, 418 .ops = &clk_rcg2_ops, 419 }, 420 }; 421 422 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 423 .cmd_rcgr = 0x9d068, 424 .mnd_width = 16, 425 .hid_width = 5, 426 .parent_map = gcc_parent_map_2, 427 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 428 .hw_clk_ctrl = true, 429 .clkr.hw.init = &(struct clk_init_data){ 430 .name = "gcc_pcie_1_aux_clk_src", 431 .parent_data = gcc_parent_data_2, 432 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 433 .flags = CLK_SET_RATE_PARENT, 434 .ops = &clk_rcg2_ops, 435 }, 436 }; 437 438 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 439 .cmd_rcgr = 0x9d04c, 440 .mnd_width = 0, 441 .hid_width = 5, 442 .parent_map = gcc_parent_map_0, 443 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 444 .hw_clk_ctrl = true, 445 .clkr.hw.init = &(struct clk_init_data){ 446 .name = "gcc_pcie_1_phy_rchng_clk_src", 447 .parent_data = gcc_parent_data_0, 448 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 449 .flags = CLK_SET_RATE_PARENT, 450 .ops = &clk_rcg2_ops, 451 }, 452 }; 453 454 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 455 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 456 { } 457 }; 458 459 static struct clk_rcg2 gcc_pdm2_clk_src = { 460 .cmd_rcgr = 0x43010, 461 .mnd_width = 0, 462 .hid_width = 5, 463 .parent_map = gcc_parent_map_0, 464 .freq_tbl = ftbl_gcc_pdm2_clk_src, 465 .hw_clk_ctrl = true, 466 .clkr.hw.init = &(struct clk_init_data){ 467 .name = "gcc_pdm2_clk_src", 468 .parent_data = gcc_parent_data_0, 469 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 470 .flags = CLK_SET_RATE_PARENT, 471 .ops = &clk_rcg2_ops, 472 }, 473 }; 474 475 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 476 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 477 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 478 F(19200000, P_BI_TCXO, 1, 0, 0), 479 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 480 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 481 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 482 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 483 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 484 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 485 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 486 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 487 { } 488 }; 489 490 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 491 .name = "gcc_qupv3_wrap0_s0_clk_src", 492 .parent_data = gcc_parent_data_0, 493 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 494 .flags = CLK_SET_RATE_PARENT, 495 .ops = &clk_rcg2_ops, 496 }; 497 498 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 499 .cmd_rcgr = 0x27014, 500 .mnd_width = 16, 501 .hid_width = 5, 502 .parent_map = gcc_parent_map_0, 503 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 504 .hw_clk_ctrl = true, 505 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 506 }; 507 508 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 509 .name = "gcc_qupv3_wrap0_s1_clk_src", 510 .parent_data = gcc_parent_data_0, 511 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 512 .flags = CLK_SET_RATE_PARENT, 513 .ops = &clk_rcg2_ops, 514 }; 515 516 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 517 .cmd_rcgr = 0x27148, 518 .mnd_width = 16, 519 .hid_width = 5, 520 .parent_map = gcc_parent_map_0, 521 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 522 .hw_clk_ctrl = true, 523 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 524 }; 525 526 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 527 .name = "gcc_qupv3_wrap0_s2_clk_src", 528 .parent_data = gcc_parent_data_0, 529 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 530 .flags = CLK_SET_RATE_PARENT, 531 .ops = &clk_rcg2_ops, 532 }; 533 534 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 535 .cmd_rcgr = 0x2727c, 536 .mnd_width = 16, 537 .hid_width = 5, 538 .parent_map = gcc_parent_map_0, 539 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 540 .hw_clk_ctrl = true, 541 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 542 }; 543 544 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 545 .name = "gcc_qupv3_wrap0_s3_clk_src", 546 .parent_data = gcc_parent_data_0, 547 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 548 .flags = CLK_SET_RATE_PARENT, 549 .ops = &clk_rcg2_ops, 550 }; 551 552 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 553 .cmd_rcgr = 0x273b0, 554 .mnd_width = 16, 555 .hid_width = 5, 556 .parent_map = gcc_parent_map_0, 557 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 558 .hw_clk_ctrl = true, 559 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 560 }; 561 562 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 563 .name = "gcc_qupv3_wrap0_s4_clk_src", 564 .parent_data = gcc_parent_data_0, 565 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 566 .flags = CLK_SET_RATE_PARENT, 567 .ops = &clk_rcg2_ops, 568 }; 569 570 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 571 .cmd_rcgr = 0x274e4, 572 .mnd_width = 16, 573 .hid_width = 5, 574 .parent_map = gcc_parent_map_0, 575 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 576 .hw_clk_ctrl = true, 577 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 578 }; 579 580 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] = { 581 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 582 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 583 F(19200000, P_BI_TCXO, 1, 0, 0), 584 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 585 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 586 F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0), 587 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 588 F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0), 589 { } 590 }; 591 592 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 593 .name = "gcc_qupv3_wrap0_s5_clk_src", 594 .parent_data = gcc_parent_data_0, 595 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 596 .flags = CLK_SET_RATE_PARENT, 597 .ops = &clk_rcg2_ops, 598 }; 599 600 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 601 .cmd_rcgr = 0x27618, 602 .mnd_width = 16, 603 .hid_width = 5, 604 .parent_map = gcc_parent_map_0, 605 .freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src, 606 .hw_clk_ctrl = true, 607 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 608 }; 609 610 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 611 .name = "gcc_qupv3_wrap0_s6_clk_src", 612 .parent_data = gcc_parent_data_0, 613 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 614 .flags = CLK_SET_RATE_PARENT, 615 .ops = &clk_rcg2_ops, 616 }; 617 618 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 619 .cmd_rcgr = 0x2774c, 620 .mnd_width = 16, 621 .hid_width = 5, 622 .parent_map = gcc_parent_map_0, 623 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 624 .hw_clk_ctrl = true, 625 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 626 }; 627 628 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 629 .name = "gcc_qupv3_wrap0_s7_clk_src", 630 .parent_data = gcc_parent_data_0, 631 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 632 .flags = CLK_SET_RATE_PARENT, 633 .ops = &clk_rcg2_ops, 634 }; 635 636 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 637 .cmd_rcgr = 0x27880, 638 .mnd_width = 16, 639 .hid_width = 5, 640 .parent_map = gcc_parent_map_0, 641 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 642 .hw_clk_ctrl = true, 643 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 644 }; 645 646 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = { 647 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 648 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 649 F(19200000, P_BI_TCXO, 1, 0, 0), 650 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 651 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 652 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 653 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 654 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 655 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 656 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 657 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 658 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 659 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 660 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 661 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 662 { } 663 }; 664 665 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 666 .name = "gcc_qupv3_wrap1_s0_clk_src", 667 .parent_data = gcc_parent_data_0, 668 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 669 .flags = CLK_SET_RATE_PARENT, 670 .ops = &clk_rcg2_ops, 671 }; 672 673 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 674 .cmd_rcgr = 0x28014, 675 .mnd_width = 16, 676 .hid_width = 5, 677 .parent_map = gcc_parent_map_0, 678 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 679 .hw_clk_ctrl = true, 680 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 681 }; 682 683 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 684 .name = "gcc_qupv3_wrap1_s1_clk_src", 685 .parent_data = gcc_parent_data_0, 686 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 687 .flags = CLK_SET_RATE_PARENT, 688 .ops = &clk_rcg2_ops, 689 }; 690 691 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 692 .cmd_rcgr = 0x28148, 693 .mnd_width = 16, 694 .hid_width = 5, 695 .parent_map = gcc_parent_map_0, 696 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 697 .hw_clk_ctrl = true, 698 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 699 }; 700 701 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 702 .name = "gcc_qupv3_wrap1_s2_clk_src", 703 .parent_data = gcc_parent_data_0, 704 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 705 .flags = CLK_SET_RATE_PARENT, 706 .ops = &clk_rcg2_ops, 707 }; 708 709 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 710 .cmd_rcgr = 0x2827c, 711 .mnd_width = 16, 712 .hid_width = 5, 713 .parent_map = gcc_parent_map_0, 714 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 715 .hw_clk_ctrl = true, 716 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 717 }; 718 719 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 720 .name = "gcc_qupv3_wrap1_s3_clk_src", 721 .parent_data = gcc_parent_data_0, 722 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 723 .flags = CLK_SET_RATE_PARENT, 724 .ops = &clk_rcg2_ops, 725 }; 726 727 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 728 .cmd_rcgr = 0x283b0, 729 .mnd_width = 16, 730 .hid_width = 5, 731 .parent_map = gcc_parent_map_0, 732 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 733 .hw_clk_ctrl = true, 734 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 735 }; 736 737 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 738 .name = "gcc_qupv3_wrap1_s4_clk_src", 739 .parent_data = gcc_parent_data_0, 740 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 741 .flags = CLK_SET_RATE_PARENT, 742 .ops = &clk_rcg2_ops, 743 }; 744 745 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 746 .cmd_rcgr = 0x284e4, 747 .mnd_width = 16, 748 .hid_width = 5, 749 .parent_map = gcc_parent_map_0, 750 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 751 .hw_clk_ctrl = true, 752 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 753 }; 754 755 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 756 .name = "gcc_qupv3_wrap1_s5_clk_src", 757 .parent_data = gcc_parent_data_0, 758 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 759 .flags = CLK_SET_RATE_PARENT, 760 .ops = &clk_rcg2_ops, 761 }; 762 763 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 764 .cmd_rcgr = 0x28618, 765 .mnd_width = 16, 766 .hid_width = 5, 767 .parent_map = gcc_parent_map_0, 768 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 769 .hw_clk_ctrl = true, 770 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 771 }; 772 773 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 774 .name = "gcc_qupv3_wrap1_s6_clk_src", 775 .parent_data = gcc_parent_data_0, 776 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 777 .flags = CLK_SET_RATE_PARENT, 778 .ops = &clk_rcg2_ops, 779 }; 780 781 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 782 .cmd_rcgr = 0x2874c, 783 .mnd_width = 16, 784 .hid_width = 5, 785 .parent_map = gcc_parent_map_0, 786 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 787 .hw_clk_ctrl = true, 788 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 789 }; 790 791 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 792 .name = "gcc_qupv3_wrap2_s0_clk_src", 793 .parent_data = gcc_parent_data_0, 794 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 795 .flags = CLK_SET_RATE_PARENT, 796 .ops = &clk_rcg2_ops, 797 }; 798 799 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 800 .cmd_rcgr = 0x2e014, 801 .mnd_width = 16, 802 .hid_width = 5, 803 .parent_map = gcc_parent_map_0, 804 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 805 .hw_clk_ctrl = true, 806 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 807 }; 808 809 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 810 .name = "gcc_qupv3_wrap2_s1_clk_src", 811 .parent_data = gcc_parent_data_0, 812 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 813 .flags = CLK_SET_RATE_PARENT, 814 .ops = &clk_rcg2_ops, 815 }; 816 817 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 818 .cmd_rcgr = 0x2e148, 819 .mnd_width = 16, 820 .hid_width = 5, 821 .parent_map = gcc_parent_map_0, 822 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 823 .hw_clk_ctrl = true, 824 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 825 }; 826 827 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 828 .name = "gcc_qupv3_wrap2_s2_clk_src", 829 .parent_data = gcc_parent_data_0, 830 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 831 .flags = CLK_SET_RATE_PARENT, 832 .ops = &clk_rcg2_ops, 833 }; 834 835 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 836 .cmd_rcgr = 0x2e27c, 837 .mnd_width = 16, 838 .hid_width = 5, 839 .parent_map = gcc_parent_map_0, 840 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 841 .hw_clk_ctrl = true, 842 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 843 }; 844 845 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 846 .name = "gcc_qupv3_wrap2_s3_clk_src", 847 .parent_data = gcc_parent_data_0, 848 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 849 .flags = CLK_SET_RATE_PARENT, 850 .ops = &clk_rcg2_ops, 851 }; 852 853 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 854 .cmd_rcgr = 0x2e3b0, 855 .mnd_width = 16, 856 .hid_width = 5, 857 .parent_map = gcc_parent_map_0, 858 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 859 .hw_clk_ctrl = true, 860 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 861 }; 862 863 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 864 .name = "gcc_qupv3_wrap2_s4_clk_src", 865 .parent_data = gcc_parent_data_0, 866 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 867 .flags = CLK_SET_RATE_PARENT, 868 .ops = &clk_rcg2_ops, 869 }; 870 871 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 872 .cmd_rcgr = 0x2e4e4, 873 .mnd_width = 16, 874 .hid_width = 5, 875 .parent_map = gcc_parent_map_0, 876 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 877 .hw_clk_ctrl = true, 878 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 879 }; 880 881 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 882 .name = "gcc_qupv3_wrap2_s5_clk_src", 883 .parent_data = gcc_parent_data_0, 884 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 885 .flags = CLK_SET_RATE_PARENT, 886 .ops = &clk_rcg2_ops, 887 }; 888 889 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 890 .cmd_rcgr = 0x2e618, 891 .mnd_width = 16, 892 .hid_width = 5, 893 .parent_map = gcc_parent_map_0, 894 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 895 .hw_clk_ctrl = true, 896 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 897 }; 898 899 static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { 900 .name = "gcc_qupv3_wrap2_s6_clk_src", 901 .parent_data = gcc_parent_data_0, 902 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 903 .flags = CLK_SET_RATE_PARENT, 904 .ops = &clk_rcg2_ops, 905 }; 906 907 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { 908 .cmd_rcgr = 0x2e74c, 909 .mnd_width = 16, 910 .hid_width = 5, 911 .parent_map = gcc_parent_map_0, 912 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 913 .hw_clk_ctrl = true, 914 .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init, 915 }; 916 917 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 918 F(400000, P_BI_TCXO, 12, 1, 4), 919 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 920 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 921 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 922 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 923 { } 924 }; 925 926 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 927 .cmd_rcgr = 0x24014, 928 .mnd_width = 8, 929 .hid_width = 5, 930 .parent_map = gcc_parent_map_7, 931 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 932 .hw_clk_ctrl = true, 933 .clkr.hw.init = &(struct clk_init_data){ 934 .name = "gcc_sdcc2_apps_clk_src", 935 .parent_data = gcc_parent_data_7, 936 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 937 .flags = CLK_SET_RATE_PARENT, 938 .ops = &clk_rcg2_floor_ops, 939 }, 940 }; 941 942 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 943 F(400000, P_BI_TCXO, 12, 1, 4), 944 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 945 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 946 { } 947 }; 948 949 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 950 .cmd_rcgr = 0x26014, 951 .mnd_width = 8, 952 .hid_width = 5, 953 .parent_map = gcc_parent_map_0, 954 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 955 .hw_clk_ctrl = true, 956 .clkr.hw.init = &(struct clk_init_data){ 957 .name = "gcc_sdcc4_apps_clk_src", 958 .parent_data = gcc_parent_data_0, 959 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 960 .flags = CLK_SET_RATE_PARENT, 961 .ops = &clk_rcg2_floor_ops, 962 }, 963 }; 964 965 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 966 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 967 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 968 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 969 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 970 { } 971 }; 972 973 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 974 .cmd_rcgr = 0x8702c, 975 .mnd_width = 8, 976 .hid_width = 5, 977 .parent_map = gcc_parent_map_0, 978 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 979 .hw_clk_ctrl = true, 980 .clkr.hw.init = &(struct clk_init_data){ 981 .name = "gcc_ufs_phy_axi_clk_src", 982 .parent_data = gcc_parent_data_0, 983 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 984 .flags = CLK_SET_RATE_PARENT, 985 .ops = &clk_rcg2_ops, 986 }, 987 }; 988 989 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 990 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 991 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 992 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 993 { } 994 }; 995 996 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 997 .cmd_rcgr = 0x87074, 998 .mnd_width = 0, 999 .hid_width = 5, 1000 .parent_map = gcc_parent_map_0, 1001 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1002 .hw_clk_ctrl = true, 1003 .clkr.hw.init = &(struct clk_init_data){ 1004 .name = "gcc_ufs_phy_ice_core_clk_src", 1005 .parent_data = gcc_parent_data_0, 1006 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1007 .flags = CLK_SET_RATE_PARENT, 1008 .ops = &clk_rcg2_ops, 1009 }, 1010 }; 1011 1012 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1013 F(9600000, P_BI_TCXO, 2, 0, 0), 1014 F(19200000, P_BI_TCXO, 1, 0, 0), 1015 { } 1016 }; 1017 1018 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1019 .cmd_rcgr = 0x870a8, 1020 .mnd_width = 0, 1021 .hid_width = 5, 1022 .parent_map = gcc_parent_map_3, 1023 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1024 .hw_clk_ctrl = true, 1025 .clkr.hw.init = &(struct clk_init_data){ 1026 .name = "gcc_ufs_phy_phy_aux_clk_src", 1027 .parent_data = gcc_parent_data_3, 1028 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1029 .flags = CLK_SET_RATE_PARENT, 1030 .ops = &clk_rcg2_ops, 1031 }, 1032 }; 1033 1034 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1035 .cmd_rcgr = 0x8708c, 1036 .mnd_width = 0, 1037 .hid_width = 5, 1038 .parent_map = gcc_parent_map_0, 1039 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1040 .hw_clk_ctrl = true, 1041 .clkr.hw.init = &(struct clk_init_data){ 1042 .name = "gcc_ufs_phy_unipro_core_clk_src", 1043 .parent_data = gcc_parent_data_0, 1044 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1045 .flags = CLK_SET_RATE_PARENT, 1046 .ops = &clk_rcg2_ops, 1047 }, 1048 }; 1049 1050 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1051 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 1052 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1053 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1054 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1055 { } 1056 }; 1057 1058 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1059 .cmd_rcgr = 0x49028, 1060 .mnd_width = 8, 1061 .hid_width = 5, 1062 .parent_map = gcc_parent_map_0, 1063 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1064 .hw_clk_ctrl = true, 1065 .clkr.hw.init = &(struct clk_init_data){ 1066 .name = "gcc_usb30_prim_master_clk_src", 1067 .parent_data = gcc_parent_data_0, 1068 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1069 .flags = CLK_SET_RATE_PARENT, 1070 .ops = &clk_rcg2_ops, 1071 }, 1072 }; 1073 1074 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1075 .cmd_rcgr = 0x49040, 1076 .mnd_width = 0, 1077 .hid_width = 5, 1078 .parent_map = gcc_parent_map_0, 1079 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1080 .hw_clk_ctrl = true, 1081 .clkr.hw.init = &(struct clk_init_data){ 1082 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1083 .parent_data = gcc_parent_data_0, 1084 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1085 .flags = CLK_SET_RATE_PARENT, 1086 .ops = &clk_rcg2_ops, 1087 }, 1088 }; 1089 1090 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1091 .cmd_rcgr = 0x4906c, 1092 .mnd_width = 0, 1093 .hid_width = 5, 1094 .parent_map = gcc_parent_map_2, 1095 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1096 .hw_clk_ctrl = true, 1097 .clkr.hw.init = &(struct clk_init_data){ 1098 .name = "gcc_usb3_prim_phy_aux_clk_src", 1099 .parent_data = gcc_parent_data_2, 1100 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1101 .flags = CLK_SET_RATE_PARENT, 1102 .ops = &clk_rcg2_ops, 1103 }, 1104 }; 1105 1106 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1107 .reg = 0x49058, 1108 .shift = 0, 1109 .width = 4, 1110 .clkr.hw.init = &(struct clk_init_data) { 1111 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1112 .parent_hws = (const struct clk_hw*[]) { 1113 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1114 }, 1115 .num_parents = 1, 1116 .flags = CLK_SET_RATE_PARENT, 1117 .ops = &clk_regmap_div_ro_ops, 1118 }, 1119 }; 1120 1121 static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = { 1122 .halt_reg = 0x7b08c, 1123 .halt_check = BRANCH_HALT_SKIP, 1124 .hwcg_reg = 0x7b08c, 1125 .hwcg_bit = 1, 1126 .clkr = { 1127 .enable_reg = 0x62000, 1128 .enable_mask = BIT(12), 1129 .hw.init = &(struct clk_init_data){ 1130 .name = "gcc_aggre_noc_pcie_0_axi_clk", 1131 .ops = &clk_branch2_ops, 1132 }, 1133 }, 1134 }; 1135 1136 static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = { 1137 .halt_reg = 0x9d098, 1138 .halt_check = BRANCH_HALT_SKIP, 1139 .hwcg_reg = 0x9d098, 1140 .hwcg_bit = 1, 1141 .clkr = { 1142 .enable_reg = 0x62000, 1143 .enable_mask = BIT(11), 1144 .hw.init = &(struct clk_init_data){ 1145 .name = "gcc_aggre_noc_pcie_1_axi_clk", 1146 .ops = &clk_branch2_ops, 1147 }, 1148 }, 1149 }; 1150 1151 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1152 .halt_reg = 0x870d4, 1153 .halt_check = BRANCH_HALT_VOTED, 1154 .hwcg_reg = 0x870d4, 1155 .hwcg_bit = 1, 1156 .clkr = { 1157 .enable_reg = 0x870d4, 1158 .enable_mask = BIT(0), 1159 .hw.init = &(struct clk_init_data){ 1160 .name = "gcc_aggre_ufs_phy_axi_clk", 1161 .parent_hws = (const struct clk_hw*[]) { 1162 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1163 }, 1164 .num_parents = 1, 1165 .flags = CLK_SET_RATE_PARENT, 1166 .ops = &clk_branch2_ops, 1167 }, 1168 }, 1169 }; 1170 1171 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { 1172 .halt_reg = 0x870d4, 1173 .halt_check = BRANCH_HALT_VOTED, 1174 .hwcg_reg = 0x870d4, 1175 .hwcg_bit = 1, 1176 .clkr = { 1177 .enable_reg = 0x870d4, 1178 .enable_mask = BIT(1), 1179 .hw.init = &(struct clk_init_data){ 1180 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", 1181 .parent_hws = (const struct clk_hw*[]) { 1182 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1183 }, 1184 .num_parents = 1, 1185 .flags = CLK_SET_RATE_PARENT, 1186 .ops = &clk_branch2_ops, 1187 }, 1188 }, 1189 }; 1190 1191 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1192 .halt_reg = 0x49088, 1193 .halt_check = BRANCH_HALT_VOTED, 1194 .hwcg_reg = 0x49088, 1195 .hwcg_bit = 1, 1196 .clkr = { 1197 .enable_reg = 0x49088, 1198 .enable_mask = BIT(0), 1199 .hw.init = &(struct clk_init_data){ 1200 .name = "gcc_aggre_usb3_prim_axi_clk", 1201 .parent_hws = (const struct clk_hw*[]) { 1202 &gcc_usb30_prim_master_clk_src.clkr.hw, 1203 }, 1204 .num_parents = 1, 1205 .flags = CLK_SET_RATE_PARENT, 1206 .ops = &clk_branch2_ops, 1207 }, 1208 }, 1209 }; 1210 1211 static struct clk_branch gcc_boot_rom_ahb_clk = { 1212 .halt_reg = 0x48004, 1213 .halt_check = BRANCH_HALT_VOTED, 1214 .hwcg_reg = 0x48004, 1215 .hwcg_bit = 1, 1216 .clkr = { 1217 .enable_reg = 0x62000, 1218 .enable_mask = BIT(10), 1219 .hw.init = &(struct clk_init_data){ 1220 .name = "gcc_boot_rom_ahb_clk", 1221 .ops = &clk_branch2_ops, 1222 }, 1223 }, 1224 }; 1225 1226 static struct clk_branch gcc_camera_hf_axi_clk = { 1227 .halt_reg = 0x36010, 1228 .halt_check = BRANCH_HALT_SKIP, 1229 .hwcg_reg = 0x36010, 1230 .hwcg_bit = 1, 1231 .clkr = { 1232 .enable_reg = 0x36010, 1233 .enable_mask = BIT(0), 1234 .hw.init = &(struct clk_init_data){ 1235 .name = "gcc_camera_hf_axi_clk", 1236 .ops = &clk_branch2_ops, 1237 }, 1238 }, 1239 }; 1240 1241 static struct clk_branch gcc_camera_sf_axi_clk = { 1242 .halt_reg = 0x36018, 1243 .halt_check = BRANCH_HALT_SKIP, 1244 .hwcg_reg = 0x36018, 1245 .hwcg_bit = 1, 1246 .clkr = { 1247 .enable_reg = 0x36018, 1248 .enable_mask = BIT(0), 1249 .hw.init = &(struct clk_init_data){ 1250 .name = "gcc_camera_sf_axi_clk", 1251 .ops = &clk_branch2_ops, 1252 }, 1253 }, 1254 }; 1255 1256 static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = { 1257 .halt_reg = 0x20030, 1258 .halt_check = BRANCH_HALT_VOTED, 1259 .hwcg_reg = 0x20030, 1260 .hwcg_bit = 1, 1261 .clkr = { 1262 .enable_reg = 0x62000, 1263 .enable_mask = BIT(20), 1264 .hw.init = &(struct clk_init_data){ 1265 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk", 1266 .ops = &clk_branch2_ops, 1267 }, 1268 }, 1269 }; 1270 1271 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1272 .halt_reg = 0x49084, 1273 .halt_check = BRANCH_HALT_VOTED, 1274 .hwcg_reg = 0x49084, 1275 .hwcg_bit = 1, 1276 .clkr = { 1277 .enable_reg = 0x49084, 1278 .enable_mask = BIT(0), 1279 .hw.init = &(struct clk_init_data){ 1280 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1281 .parent_hws = (const struct clk_hw*[]) { 1282 &gcc_usb30_prim_master_clk_src.clkr.hw, 1283 }, 1284 .num_parents = 1, 1285 .flags = CLK_SET_RATE_PARENT, 1286 .ops = &clk_branch2_ops, 1287 }, 1288 }, 1289 }; 1290 1291 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1292 .halt_reg = 0x81154, 1293 .halt_check = BRANCH_HALT_SKIP, 1294 .hwcg_reg = 0x81154, 1295 .hwcg_bit = 1, 1296 .clkr = { 1297 .enable_reg = 0x81154, 1298 .enable_mask = BIT(0), 1299 .hw.init = &(struct clk_init_data){ 1300 .name = "gcc_ddrss_gpu_axi_clk", 1301 .ops = &clk_branch2_aon_ops, 1302 }, 1303 }, 1304 }; 1305 1306 static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = { 1307 .halt_reg = 0x9d094, 1308 .halt_check = BRANCH_HALT_SKIP, 1309 .hwcg_reg = 0x9d094, 1310 .hwcg_bit = 1, 1311 .clkr = { 1312 .enable_reg = 0x62000, 1313 .enable_mask = BIT(19), 1314 .hw.init = &(struct clk_init_data){ 1315 .name = "gcc_ddrss_pcie_sf_tbu_clk", 1316 .ops = &clk_branch2_ops, 1317 }, 1318 }, 1319 }; 1320 1321 static struct clk_branch gcc_disp_hf_axi_clk = { 1322 .halt_reg = 0x3700c, 1323 .halt_check = BRANCH_HALT_SKIP, 1324 .hwcg_reg = 0x3700c, 1325 .hwcg_bit = 1, 1326 .clkr = { 1327 .enable_reg = 0x3700c, 1328 .enable_mask = BIT(0), 1329 .hw.init = &(struct clk_init_data){ 1330 .name = "gcc_disp_hf_axi_clk", 1331 .ops = &clk_branch2_ops, 1332 }, 1333 }, 1334 }; 1335 1336 static struct clk_branch gcc_disp_sf_axi_clk = { 1337 .halt_reg = 0x37014, 1338 .halt_check = BRANCH_HALT_SKIP, 1339 .hwcg_reg = 0x37014, 1340 .hwcg_bit = 1, 1341 .clkr = { 1342 .enable_reg = 0x37014, 1343 .enable_mask = BIT(0), 1344 .hw.init = &(struct clk_init_data){ 1345 .name = "gcc_disp_sf_axi_clk", 1346 .ops = &clk_branch2_ops, 1347 }, 1348 }, 1349 }; 1350 1351 static struct clk_branch gcc_eusb3_0_clkref_en = { 1352 .halt_reg = 0x9c00c, 1353 .halt_check = BRANCH_HALT, 1354 .clkr = { 1355 .enable_reg = 0x9c00c, 1356 .enable_mask = BIT(0), 1357 .hw.init = &(struct clk_init_data){ 1358 .name = "gcc_eusb3_0_clkref_en", 1359 .ops = &clk_branch2_ops, 1360 }, 1361 }, 1362 }; 1363 1364 static struct clk_branch gcc_gp1_clk = { 1365 .halt_reg = 0x74000, 1366 .halt_check = BRANCH_HALT, 1367 .clkr = { 1368 .enable_reg = 0x74000, 1369 .enable_mask = BIT(0), 1370 .hw.init = &(struct clk_init_data){ 1371 .name = "gcc_gp1_clk", 1372 .parent_hws = (const struct clk_hw*[]) { 1373 &gcc_gp1_clk_src.clkr.hw, 1374 }, 1375 .num_parents = 1, 1376 .flags = CLK_SET_RATE_PARENT, 1377 .ops = &clk_branch2_ops, 1378 }, 1379 }, 1380 }; 1381 1382 static struct clk_branch gcc_gp2_clk = { 1383 .halt_reg = 0x75000, 1384 .halt_check = BRANCH_HALT, 1385 .clkr = { 1386 .enable_reg = 0x75000, 1387 .enable_mask = BIT(0), 1388 .hw.init = &(struct clk_init_data){ 1389 .name = "gcc_gp2_clk", 1390 .parent_hws = (const struct clk_hw*[]) { 1391 &gcc_gp2_clk_src.clkr.hw, 1392 }, 1393 .num_parents = 1, 1394 .flags = CLK_SET_RATE_PARENT, 1395 .ops = &clk_branch2_ops, 1396 }, 1397 }, 1398 }; 1399 1400 static struct clk_branch gcc_gp3_clk = { 1401 .halt_reg = 0x76000, 1402 .halt_check = BRANCH_HALT, 1403 .clkr = { 1404 .enable_reg = 0x76000, 1405 .enable_mask = BIT(0), 1406 .hw.init = &(struct clk_init_data){ 1407 .name = "gcc_gp3_clk", 1408 .parent_hws = (const struct clk_hw*[]) { 1409 &gcc_gp3_clk_src.clkr.hw, 1410 }, 1411 .num_parents = 1, 1412 .flags = CLK_SET_RATE_PARENT, 1413 .ops = &clk_branch2_ops, 1414 }, 1415 }, 1416 }; 1417 1418 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1419 .halt_check = BRANCH_HALT_DELAY, 1420 .clkr = { 1421 .enable_reg = 0x62000, 1422 .enable_mask = BIT(15), 1423 .hw.init = &(struct clk_init_data){ 1424 .name = "gcc_gpu_gpll0_clk_src", 1425 .parent_hws = (const struct clk_hw*[]) { 1426 &gcc_gpll0.clkr.hw, 1427 }, 1428 .num_parents = 1, 1429 .flags = CLK_SET_RATE_PARENT, 1430 .ops = &clk_branch2_ops, 1431 }, 1432 }, 1433 }; 1434 1435 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1436 .halt_check = BRANCH_HALT_DELAY, 1437 .clkr = { 1438 .enable_reg = 0x62000, 1439 .enable_mask = BIT(16), 1440 .hw.init = &(struct clk_init_data){ 1441 .name = "gcc_gpu_gpll0_div_clk_src", 1442 .parent_hws = (const struct clk_hw*[]) { 1443 &gcc_gpll0_out_even.clkr.hw, 1444 }, 1445 .num_parents = 1, 1446 .flags = CLK_SET_RATE_PARENT, 1447 .ops = &clk_branch2_ops, 1448 }, 1449 }, 1450 }; 1451 1452 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1453 .halt_reg = 0x81010, 1454 .halt_check = BRANCH_HALT_VOTED, 1455 .hwcg_reg = 0x81010, 1456 .hwcg_bit = 1, 1457 .clkr = { 1458 .enable_reg = 0x81010, 1459 .enable_mask = BIT(0), 1460 .hw.init = &(struct clk_init_data){ 1461 .name = "gcc_gpu_memnoc_gfx_clk", 1462 .ops = &clk_branch2_ops, 1463 }, 1464 }, 1465 }; 1466 1467 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1468 .halt_reg = 0x81018, 1469 .halt_check = BRANCH_HALT_DELAY, 1470 .clkr = { 1471 .enable_reg = 0x81018, 1472 .enable_mask = BIT(0), 1473 .hw.init = &(struct clk_init_data){ 1474 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1475 .ops = &clk_branch2_ops, 1476 }, 1477 }, 1478 }; 1479 1480 static struct clk_branch gcc_pcie_0_aux_clk = { 1481 .halt_reg = 0x7b034, 1482 .halt_check = BRANCH_HALT_VOTED, 1483 .clkr = { 1484 .enable_reg = 0x62008, 1485 .enable_mask = BIT(3), 1486 .hw.init = &(struct clk_init_data){ 1487 .name = "gcc_pcie_0_aux_clk", 1488 .parent_hws = (const struct clk_hw*[]) { 1489 &gcc_pcie_0_aux_clk_src.clkr.hw, 1490 }, 1491 .num_parents = 1, 1492 .flags = CLK_SET_RATE_PARENT, 1493 .ops = &clk_branch2_ops, 1494 }, 1495 }, 1496 }; 1497 1498 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1499 .halt_reg = 0x7b030, 1500 .halt_check = BRANCH_HALT_VOTED, 1501 .hwcg_reg = 0x7b030, 1502 .hwcg_bit = 1, 1503 .clkr = { 1504 .enable_reg = 0x62008, 1505 .enable_mask = BIT(2), 1506 .hw.init = &(struct clk_init_data){ 1507 .name = "gcc_pcie_0_cfg_ahb_clk", 1508 .ops = &clk_branch2_ops, 1509 }, 1510 }, 1511 }; 1512 1513 static struct clk_branch gcc_pcie_0_clkref_en = { 1514 .halt_reg = 0x9c004, 1515 .halt_check = BRANCH_HALT, 1516 .clkr = { 1517 .enable_reg = 0x9c004, 1518 .enable_mask = BIT(0), 1519 .hw.init = &(struct clk_init_data){ 1520 .name = "gcc_pcie_0_clkref_en", 1521 .ops = &clk_branch2_ops, 1522 }, 1523 }, 1524 }; 1525 1526 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1527 .halt_reg = 0x7b028, 1528 .halt_check = BRANCH_HALT_SKIP, 1529 .clkr = { 1530 .enable_reg = 0x62008, 1531 .enable_mask = BIT(1), 1532 .hw.init = &(struct clk_init_data){ 1533 .name = "gcc_pcie_0_mstr_axi_clk", 1534 .ops = &clk_branch2_ops, 1535 }, 1536 }, 1537 }; 1538 1539 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 1540 .halt_reg = 0x7b044, 1541 .halt_check = BRANCH_HALT_VOTED, 1542 .clkr = { 1543 .enable_reg = 0x62000, 1544 .enable_mask = BIT(22), 1545 .hw.init = &(struct clk_init_data){ 1546 .name = "gcc_pcie_0_phy_rchng_clk", 1547 .parent_hws = (const struct clk_hw*[]) { 1548 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1549 }, 1550 .num_parents = 1, 1551 .flags = CLK_SET_RATE_PARENT, 1552 .ops = &clk_branch2_ops, 1553 }, 1554 }, 1555 }; 1556 1557 static struct clk_branch gcc_pcie_0_pipe_clk = { 1558 .halt_reg = 0x7b03c, 1559 .halt_check = BRANCH_HALT_SKIP, 1560 .clkr = { 1561 .enable_reg = 0x62008, 1562 .enable_mask = BIT(4), 1563 .hw.init = &(struct clk_init_data){ 1564 .name = "gcc_pcie_0_pipe_clk", 1565 .parent_hws = (const struct clk_hw*[]) { 1566 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1567 }, 1568 .num_parents = 1, 1569 .flags = CLK_SET_RATE_PARENT, 1570 .ops = &clk_branch2_ops, 1571 }, 1572 }, 1573 }; 1574 1575 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1576 .halt_reg = 0x7b020, 1577 .halt_check = BRANCH_HALT_VOTED, 1578 .hwcg_reg = 0x7b020, 1579 .hwcg_bit = 1, 1580 .clkr = { 1581 .enable_reg = 0x62008, 1582 .enable_mask = BIT(0), 1583 .hw.init = &(struct clk_init_data){ 1584 .name = "gcc_pcie_0_slv_axi_clk", 1585 .ops = &clk_branch2_ops, 1586 }, 1587 }, 1588 }; 1589 1590 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1591 .halt_reg = 0x7b01c, 1592 .halt_check = BRANCH_HALT_VOTED, 1593 .clkr = { 1594 .enable_reg = 0x62008, 1595 .enable_mask = BIT(5), 1596 .hw.init = &(struct clk_init_data){ 1597 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1598 .ops = &clk_branch2_ops, 1599 }, 1600 }, 1601 }; 1602 1603 static struct clk_branch gcc_pcie_1_aux_clk = { 1604 .halt_reg = 0x9d030, 1605 .halt_check = BRANCH_HALT_VOTED, 1606 .clkr = { 1607 .enable_reg = 0x62000, 1608 .enable_mask = BIT(29), 1609 .hw.init = &(struct clk_init_data){ 1610 .name = "gcc_pcie_1_aux_clk", 1611 .parent_hws = (const struct clk_hw*[]) { 1612 &gcc_pcie_1_aux_clk_src.clkr.hw, 1613 }, 1614 .num_parents = 1, 1615 .flags = CLK_SET_RATE_PARENT, 1616 .ops = &clk_branch2_ops, 1617 }, 1618 }, 1619 }; 1620 1621 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1622 .halt_reg = 0x9d02c, 1623 .halt_check = BRANCH_HALT_VOTED, 1624 .hwcg_reg = 0x9d02c, 1625 .hwcg_bit = 1, 1626 .clkr = { 1627 .enable_reg = 0x62000, 1628 .enable_mask = BIT(28), 1629 .hw.init = &(struct clk_init_data){ 1630 .name = "gcc_pcie_1_cfg_ahb_clk", 1631 .ops = &clk_branch2_ops, 1632 }, 1633 }, 1634 }; 1635 1636 static struct clk_branch gcc_pcie_1_clkref_en = { 1637 .halt_reg = 0x9c008, 1638 .halt_check = BRANCH_HALT, 1639 .clkr = { 1640 .enable_reg = 0x9c008, 1641 .enable_mask = BIT(0), 1642 .hw.init = &(struct clk_init_data){ 1643 .name = "gcc_pcie_1_clkref_en", 1644 .ops = &clk_branch2_ops, 1645 }, 1646 }, 1647 }; 1648 1649 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1650 .halt_reg = 0x9d024, 1651 .halt_check = BRANCH_HALT_SKIP, 1652 .clkr = { 1653 .enable_reg = 0x62000, 1654 .enable_mask = BIT(27), 1655 .hw.init = &(struct clk_init_data){ 1656 .name = "gcc_pcie_1_mstr_axi_clk", 1657 .ops = &clk_branch2_ops, 1658 }, 1659 }, 1660 }; 1661 1662 static struct clk_branch gcc_pcie_1_phy_aux_clk = { 1663 .halt_reg = 0x9d038, 1664 .halt_check = BRANCH_HALT_VOTED, 1665 .clkr = { 1666 .enable_reg = 0x62000, 1667 .enable_mask = BIT(24), 1668 .hw.init = &(struct clk_init_data){ 1669 .name = "gcc_pcie_1_phy_aux_clk", 1670 .parent_hws = (const struct clk_hw*[]) { 1671 &gcc_pcie_1_phy_aux_clk_src.clkr.hw, 1672 }, 1673 .num_parents = 1, 1674 .flags = CLK_SET_RATE_PARENT, 1675 .ops = &clk_branch2_ops, 1676 }, 1677 }, 1678 }; 1679 1680 static struct clk_branch gcc_pcie_1_phy_rchng_clk = { 1681 .halt_reg = 0x9d048, 1682 .halt_check = BRANCH_HALT_VOTED, 1683 .clkr = { 1684 .enable_reg = 0x62000, 1685 .enable_mask = BIT(23), 1686 .hw.init = &(struct clk_init_data){ 1687 .name = "gcc_pcie_1_phy_rchng_clk", 1688 .parent_hws = (const struct clk_hw*[]) { 1689 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 1690 }, 1691 .num_parents = 1, 1692 .flags = CLK_SET_RATE_PARENT, 1693 .ops = &clk_branch2_ops, 1694 }, 1695 }, 1696 }; 1697 1698 static struct clk_branch gcc_pcie_1_pipe_clk = { 1699 .halt_reg = 0x9d040, 1700 .halt_check = BRANCH_HALT_SKIP, 1701 .clkr = { 1702 .enable_reg = 0x62000, 1703 .enable_mask = BIT(30), 1704 .hw.init = &(struct clk_init_data){ 1705 .name = "gcc_pcie_1_pipe_clk", 1706 .parent_hws = (const struct clk_hw*[]) { 1707 &gcc_pcie_1_pipe_clk_src.clkr.hw, 1708 }, 1709 .num_parents = 1, 1710 .flags = CLK_SET_RATE_PARENT, 1711 .ops = &clk_branch2_ops, 1712 }, 1713 }, 1714 }; 1715 1716 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1717 .halt_reg = 0x9d01c, 1718 .halt_check = BRANCH_HALT_VOTED, 1719 .hwcg_reg = 0x9d01c, 1720 .hwcg_bit = 1, 1721 .clkr = { 1722 .enable_reg = 0x62000, 1723 .enable_mask = BIT(26), 1724 .hw.init = &(struct clk_init_data){ 1725 .name = "gcc_pcie_1_slv_axi_clk", 1726 .ops = &clk_branch2_ops, 1727 }, 1728 }, 1729 }; 1730 1731 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 1732 .halt_reg = 0x9d018, 1733 .halt_check = BRANCH_HALT_VOTED, 1734 .clkr = { 1735 .enable_reg = 0x62000, 1736 .enable_mask = BIT(25), 1737 .hw.init = &(struct clk_init_data){ 1738 .name = "gcc_pcie_1_slv_q2a_axi_clk", 1739 .ops = &clk_branch2_ops, 1740 }, 1741 }, 1742 }; 1743 1744 static struct clk_branch gcc_pdm2_clk = { 1745 .halt_reg = 0x4300c, 1746 .halt_check = BRANCH_HALT, 1747 .clkr = { 1748 .enable_reg = 0x4300c, 1749 .enable_mask = BIT(0), 1750 .hw.init = &(struct clk_init_data){ 1751 .name = "gcc_pdm2_clk", 1752 .parent_hws = (const struct clk_hw*[]) { 1753 &gcc_pdm2_clk_src.clkr.hw, 1754 }, 1755 .num_parents = 1, 1756 .flags = CLK_SET_RATE_PARENT, 1757 .ops = &clk_branch2_ops, 1758 }, 1759 }, 1760 }; 1761 1762 static struct clk_branch gcc_pdm_ahb_clk = { 1763 .halt_reg = 0x43004, 1764 .halt_check = BRANCH_HALT_VOTED, 1765 .hwcg_reg = 0x43004, 1766 .hwcg_bit = 1, 1767 .clkr = { 1768 .enable_reg = 0x43004, 1769 .enable_mask = BIT(0), 1770 .hw.init = &(struct clk_init_data){ 1771 .name = "gcc_pdm_ahb_clk", 1772 .ops = &clk_branch2_ops, 1773 }, 1774 }, 1775 }; 1776 1777 static struct clk_branch gcc_pdm_xo4_clk = { 1778 .halt_reg = 0x43008, 1779 .halt_check = BRANCH_HALT, 1780 .clkr = { 1781 .enable_reg = 0x43008, 1782 .enable_mask = BIT(0), 1783 .hw.init = &(struct clk_init_data){ 1784 .name = "gcc_pdm_xo4_clk", 1785 .ops = &clk_branch2_ops, 1786 }, 1787 }, 1788 }; 1789 1790 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 1791 .halt_reg = 0x36008, 1792 .halt_check = BRANCH_HALT_VOTED, 1793 .hwcg_reg = 0x36008, 1794 .hwcg_bit = 1, 1795 .clkr = { 1796 .enable_reg = 0x36008, 1797 .enable_mask = BIT(0), 1798 .hw.init = &(struct clk_init_data){ 1799 .name = "gcc_qmip_camera_nrt_ahb_clk", 1800 .ops = &clk_branch2_ops, 1801 }, 1802 }, 1803 }; 1804 1805 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 1806 .halt_reg = 0x3600c, 1807 .halt_check = BRANCH_HALT_VOTED, 1808 .hwcg_reg = 0x3600c, 1809 .hwcg_bit = 1, 1810 .clkr = { 1811 .enable_reg = 0x3600c, 1812 .enable_mask = BIT(0), 1813 .hw.init = &(struct clk_init_data){ 1814 .name = "gcc_qmip_camera_rt_ahb_clk", 1815 .ops = &clk_branch2_ops, 1816 }, 1817 }, 1818 }; 1819 1820 static struct clk_branch gcc_qmip_disp_ahb_clk = { 1821 .halt_reg = 0x37008, 1822 .halt_check = BRANCH_HALT_VOTED, 1823 .hwcg_reg = 0x37008, 1824 .hwcg_bit = 1, 1825 .clkr = { 1826 .enable_reg = 0x37008, 1827 .enable_mask = BIT(0), 1828 .hw.init = &(struct clk_init_data){ 1829 .name = "gcc_qmip_disp_ahb_clk", 1830 .ops = &clk_branch2_ops, 1831 }, 1832 }, 1833 }; 1834 1835 static struct clk_branch gcc_qmip_gpu_ahb_clk = { 1836 .halt_reg = 0x81008, 1837 .halt_check = BRANCH_HALT_VOTED, 1838 .hwcg_reg = 0x81008, 1839 .hwcg_bit = 1, 1840 .clkr = { 1841 .enable_reg = 0x81008, 1842 .enable_mask = BIT(0), 1843 .hw.init = &(struct clk_init_data){ 1844 .name = "gcc_qmip_gpu_ahb_clk", 1845 .ops = &clk_branch2_ops, 1846 }, 1847 }, 1848 }; 1849 1850 static struct clk_branch gcc_qmip_pcie_ahb_clk = { 1851 .halt_reg = 0x7b018, 1852 .halt_check = BRANCH_HALT_VOTED, 1853 .hwcg_reg = 0x7b018, 1854 .hwcg_bit = 1, 1855 .clkr = { 1856 .enable_reg = 0x7b018, 1857 .enable_mask = BIT(0), 1858 .hw.init = &(struct clk_init_data){ 1859 .name = "gcc_qmip_pcie_ahb_clk", 1860 .ops = &clk_branch2_ops, 1861 }, 1862 }, 1863 }; 1864 1865 static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = { 1866 .halt_reg = 0x42014, 1867 .halt_check = BRANCH_HALT_VOTED, 1868 .hwcg_reg = 0x42014, 1869 .hwcg_bit = 1, 1870 .clkr = { 1871 .enable_reg = 0x42014, 1872 .enable_mask = BIT(0), 1873 .hw.init = &(struct clk_init_data){ 1874 .name = "gcc_qmip_video_cv_cpu_ahb_clk", 1875 .ops = &clk_branch2_ops, 1876 }, 1877 }, 1878 }; 1879 1880 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 1881 .halt_reg = 0x42008, 1882 .halt_check = BRANCH_HALT_VOTED, 1883 .hwcg_reg = 0x42008, 1884 .hwcg_bit = 1, 1885 .clkr = { 1886 .enable_reg = 0x42008, 1887 .enable_mask = BIT(0), 1888 .hw.init = &(struct clk_init_data){ 1889 .name = "gcc_qmip_video_cvp_ahb_clk", 1890 .ops = &clk_branch2_ops, 1891 }, 1892 }, 1893 }; 1894 1895 static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = { 1896 .halt_reg = 0x42010, 1897 .halt_check = BRANCH_HALT_VOTED, 1898 .hwcg_reg = 0x42010, 1899 .hwcg_bit = 1, 1900 .clkr = { 1901 .enable_reg = 0x42010, 1902 .enable_mask = BIT(0), 1903 .hw.init = &(struct clk_init_data){ 1904 .name = "gcc_qmip_video_v_cpu_ahb_clk", 1905 .ops = &clk_branch2_ops, 1906 }, 1907 }, 1908 }; 1909 1910 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 1911 .halt_reg = 0x4200c, 1912 .halt_check = BRANCH_HALT_VOTED, 1913 .hwcg_reg = 0x4200c, 1914 .hwcg_bit = 1, 1915 .clkr = { 1916 .enable_reg = 0x4200c, 1917 .enable_mask = BIT(0), 1918 .hw.init = &(struct clk_init_data){ 1919 .name = "gcc_qmip_video_vcodec_ahb_clk", 1920 .ops = &clk_branch2_ops, 1921 }, 1922 }, 1923 }; 1924 1925 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 1926 .halt_reg = 0x3300c, 1927 .halt_check = BRANCH_HALT_VOTED, 1928 .clkr = { 1929 .enable_reg = 0x62008, 1930 .enable_mask = BIT(9), 1931 .hw.init = &(struct clk_init_data){ 1932 .name = "gcc_qupv3_wrap0_core_2x_clk", 1933 .ops = &clk_branch2_ops, 1934 }, 1935 }, 1936 }; 1937 1938 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 1939 .halt_reg = 0x33000, 1940 .halt_check = BRANCH_HALT_VOTED, 1941 .clkr = { 1942 .enable_reg = 0x62008, 1943 .enable_mask = BIT(8), 1944 .hw.init = &(struct clk_init_data){ 1945 .name = "gcc_qupv3_wrap0_core_clk", 1946 .ops = &clk_branch2_ops, 1947 }, 1948 }, 1949 }; 1950 1951 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 1952 .halt_reg = 0x2700c, 1953 .halt_check = BRANCH_HALT_VOTED, 1954 .clkr = { 1955 .enable_reg = 0x62008, 1956 .enable_mask = BIT(10), 1957 .hw.init = &(struct clk_init_data){ 1958 .name = "gcc_qupv3_wrap0_s0_clk", 1959 .parent_hws = (const struct clk_hw*[]) { 1960 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 1961 }, 1962 .num_parents = 1, 1963 .flags = CLK_SET_RATE_PARENT, 1964 .ops = &clk_branch2_ops, 1965 }, 1966 }, 1967 }; 1968 1969 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 1970 .halt_reg = 0x27140, 1971 .halt_check = BRANCH_HALT_VOTED, 1972 .clkr = { 1973 .enable_reg = 0x62008, 1974 .enable_mask = BIT(11), 1975 .hw.init = &(struct clk_init_data){ 1976 .name = "gcc_qupv3_wrap0_s1_clk", 1977 .parent_hws = (const struct clk_hw*[]) { 1978 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 1979 }, 1980 .num_parents = 1, 1981 .flags = CLK_SET_RATE_PARENT, 1982 .ops = &clk_branch2_ops, 1983 }, 1984 }, 1985 }; 1986 1987 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 1988 .halt_reg = 0x27274, 1989 .halt_check = BRANCH_HALT_VOTED, 1990 .clkr = { 1991 .enable_reg = 0x62008, 1992 .enable_mask = BIT(12), 1993 .hw.init = &(struct clk_init_data){ 1994 .name = "gcc_qupv3_wrap0_s2_clk", 1995 .parent_hws = (const struct clk_hw*[]) { 1996 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 1997 }, 1998 .num_parents = 1, 1999 .flags = CLK_SET_RATE_PARENT, 2000 .ops = &clk_branch2_ops, 2001 }, 2002 }, 2003 }; 2004 2005 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2006 .halt_reg = 0x273a8, 2007 .halt_check = BRANCH_HALT_VOTED, 2008 .clkr = { 2009 .enable_reg = 0x62008, 2010 .enable_mask = BIT(13), 2011 .hw.init = &(struct clk_init_data){ 2012 .name = "gcc_qupv3_wrap0_s3_clk", 2013 .parent_hws = (const struct clk_hw*[]) { 2014 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2015 }, 2016 .num_parents = 1, 2017 .flags = CLK_SET_RATE_PARENT, 2018 .ops = &clk_branch2_ops, 2019 }, 2020 }, 2021 }; 2022 2023 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2024 .halt_reg = 0x274dc, 2025 .halt_check = BRANCH_HALT_VOTED, 2026 .clkr = { 2027 .enable_reg = 0x62008, 2028 .enable_mask = BIT(14), 2029 .hw.init = &(struct clk_init_data){ 2030 .name = "gcc_qupv3_wrap0_s4_clk", 2031 .parent_hws = (const struct clk_hw*[]) { 2032 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2033 }, 2034 .num_parents = 1, 2035 .flags = CLK_SET_RATE_PARENT, 2036 .ops = &clk_branch2_ops, 2037 }, 2038 }, 2039 }; 2040 2041 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2042 .halt_reg = 0x27610, 2043 .halt_check = BRANCH_HALT_VOTED, 2044 .clkr = { 2045 .enable_reg = 0x62008, 2046 .enable_mask = BIT(15), 2047 .hw.init = &(struct clk_init_data){ 2048 .name = "gcc_qupv3_wrap0_s5_clk", 2049 .parent_hws = (const struct clk_hw*[]) { 2050 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2051 }, 2052 .num_parents = 1, 2053 .flags = CLK_SET_RATE_PARENT, 2054 .ops = &clk_branch2_ops, 2055 }, 2056 }, 2057 }; 2058 2059 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 2060 .halt_reg = 0x27744, 2061 .halt_check = BRANCH_HALT_VOTED, 2062 .clkr = { 2063 .enable_reg = 0x62008, 2064 .enable_mask = BIT(16), 2065 .hw.init = &(struct clk_init_data){ 2066 .name = "gcc_qupv3_wrap0_s6_clk", 2067 .parent_hws = (const struct clk_hw*[]) { 2068 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 2069 }, 2070 .num_parents = 1, 2071 .flags = CLK_SET_RATE_PARENT, 2072 .ops = &clk_branch2_ops, 2073 }, 2074 }, 2075 }; 2076 2077 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 2078 .halt_reg = 0x27878, 2079 .halt_check = BRANCH_HALT_VOTED, 2080 .clkr = { 2081 .enable_reg = 0x62008, 2082 .enable_mask = BIT(17), 2083 .hw.init = &(struct clk_init_data){ 2084 .name = "gcc_qupv3_wrap0_s7_clk", 2085 .parent_hws = (const struct clk_hw*[]) { 2086 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 2087 }, 2088 .num_parents = 1, 2089 .flags = CLK_SET_RATE_PARENT, 2090 .ops = &clk_branch2_ops, 2091 }, 2092 }, 2093 }; 2094 2095 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2096 .halt_reg = 0x3314c, 2097 .halt_check = BRANCH_HALT_VOTED, 2098 .clkr = { 2099 .enable_reg = 0x62008, 2100 .enable_mask = BIT(18), 2101 .hw.init = &(struct clk_init_data){ 2102 .name = "gcc_qupv3_wrap1_core_2x_clk", 2103 .ops = &clk_branch2_ops, 2104 }, 2105 }, 2106 }; 2107 2108 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2109 .halt_reg = 0x33140, 2110 .halt_check = BRANCH_HALT_VOTED, 2111 .clkr = { 2112 .enable_reg = 0x62008, 2113 .enable_mask = BIT(19), 2114 .hw.init = &(struct clk_init_data){ 2115 .name = "gcc_qupv3_wrap1_core_clk", 2116 .ops = &clk_branch2_ops, 2117 }, 2118 }, 2119 }; 2120 2121 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2122 .halt_reg = 0x2800c, 2123 .halt_check = BRANCH_HALT_VOTED, 2124 .clkr = { 2125 .enable_reg = 0x62008, 2126 .enable_mask = BIT(22), 2127 .hw.init = &(struct clk_init_data){ 2128 .name = "gcc_qupv3_wrap1_s0_clk", 2129 .parent_hws = (const struct clk_hw*[]) { 2130 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2131 }, 2132 .num_parents = 1, 2133 .flags = CLK_SET_RATE_PARENT, 2134 .ops = &clk_branch2_ops, 2135 }, 2136 }, 2137 }; 2138 2139 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2140 .halt_reg = 0x28140, 2141 .halt_check = BRANCH_HALT_VOTED, 2142 .clkr = { 2143 .enable_reg = 0x62008, 2144 .enable_mask = BIT(23), 2145 .hw.init = &(struct clk_init_data){ 2146 .name = "gcc_qupv3_wrap1_s1_clk", 2147 .parent_hws = (const struct clk_hw*[]) { 2148 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2149 }, 2150 .num_parents = 1, 2151 .flags = CLK_SET_RATE_PARENT, 2152 .ops = &clk_branch2_ops, 2153 }, 2154 }, 2155 }; 2156 2157 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2158 .halt_reg = 0x28274, 2159 .halt_check = BRANCH_HALT_VOTED, 2160 .clkr = { 2161 .enable_reg = 0x62008, 2162 .enable_mask = BIT(24), 2163 .hw.init = &(struct clk_init_data){ 2164 .name = "gcc_qupv3_wrap1_s2_clk", 2165 .parent_hws = (const struct clk_hw*[]) { 2166 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2167 }, 2168 .num_parents = 1, 2169 .flags = CLK_SET_RATE_PARENT, 2170 .ops = &clk_branch2_ops, 2171 }, 2172 }, 2173 }; 2174 2175 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2176 .halt_reg = 0x283a8, 2177 .halt_check = BRANCH_HALT_VOTED, 2178 .clkr = { 2179 .enable_reg = 0x62008, 2180 .enable_mask = BIT(25), 2181 .hw.init = &(struct clk_init_data){ 2182 .name = "gcc_qupv3_wrap1_s3_clk", 2183 .parent_hws = (const struct clk_hw*[]) { 2184 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2185 }, 2186 .num_parents = 1, 2187 .flags = CLK_SET_RATE_PARENT, 2188 .ops = &clk_branch2_ops, 2189 }, 2190 }, 2191 }; 2192 2193 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2194 .halt_reg = 0x284dc, 2195 .halt_check = BRANCH_HALT_VOTED, 2196 .clkr = { 2197 .enable_reg = 0x62008, 2198 .enable_mask = BIT(26), 2199 .hw.init = &(struct clk_init_data){ 2200 .name = "gcc_qupv3_wrap1_s4_clk", 2201 .parent_hws = (const struct clk_hw*[]) { 2202 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2203 }, 2204 .num_parents = 1, 2205 .flags = CLK_SET_RATE_PARENT, 2206 .ops = &clk_branch2_ops, 2207 }, 2208 }, 2209 }; 2210 2211 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2212 .halt_reg = 0x28610, 2213 .halt_check = BRANCH_HALT_VOTED, 2214 .clkr = { 2215 .enable_reg = 0x62008, 2216 .enable_mask = BIT(27), 2217 .hw.init = &(struct clk_init_data){ 2218 .name = "gcc_qupv3_wrap1_s5_clk", 2219 .parent_hws = (const struct clk_hw*[]) { 2220 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2221 }, 2222 .num_parents = 1, 2223 .flags = CLK_SET_RATE_PARENT, 2224 .ops = &clk_branch2_ops, 2225 }, 2226 }, 2227 }; 2228 2229 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 2230 .halt_reg = 0x28744, 2231 .halt_check = BRANCH_HALT_VOTED, 2232 .clkr = { 2233 .enable_reg = 0x62008, 2234 .enable_mask = BIT(28), 2235 .hw.init = &(struct clk_init_data){ 2236 .name = "gcc_qupv3_wrap1_s6_clk", 2237 .parent_hws = (const struct clk_hw*[]) { 2238 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 2239 }, 2240 .num_parents = 1, 2241 .flags = CLK_SET_RATE_PARENT, 2242 .ops = &clk_branch2_ops, 2243 }, 2244 }, 2245 }; 2246 2247 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 2248 .halt_reg = 0x3328c, 2249 .halt_check = BRANCH_HALT_VOTED, 2250 .clkr = { 2251 .enable_reg = 0x62010, 2252 .enable_mask = BIT(3), 2253 .hw.init = &(struct clk_init_data){ 2254 .name = "gcc_qupv3_wrap2_core_2x_clk", 2255 .ops = &clk_branch2_ops, 2256 }, 2257 }, 2258 }; 2259 2260 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 2261 .halt_reg = 0x33280, 2262 .halt_check = BRANCH_HALT_VOTED, 2263 .clkr = { 2264 .enable_reg = 0x62010, 2265 .enable_mask = BIT(0), 2266 .hw.init = &(struct clk_init_data){ 2267 .name = "gcc_qupv3_wrap2_core_clk", 2268 .ops = &clk_branch2_ops, 2269 }, 2270 }, 2271 }; 2272 2273 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 2274 .halt_reg = 0x2e00c, 2275 .halt_check = BRANCH_HALT_VOTED, 2276 .clkr = { 2277 .enable_reg = 0x62010, 2278 .enable_mask = BIT(4), 2279 .hw.init = &(struct clk_init_data){ 2280 .name = "gcc_qupv3_wrap2_s0_clk", 2281 .parent_hws = (const struct clk_hw*[]) { 2282 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 2283 }, 2284 .num_parents = 1, 2285 .flags = CLK_SET_RATE_PARENT, 2286 .ops = &clk_branch2_ops, 2287 }, 2288 }, 2289 }; 2290 2291 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 2292 .halt_reg = 0x2e140, 2293 .halt_check = BRANCH_HALT_VOTED, 2294 .clkr = { 2295 .enable_reg = 0x62010, 2296 .enable_mask = BIT(5), 2297 .hw.init = &(struct clk_init_data){ 2298 .name = "gcc_qupv3_wrap2_s1_clk", 2299 .parent_hws = (const struct clk_hw*[]) { 2300 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 2301 }, 2302 .num_parents = 1, 2303 .flags = CLK_SET_RATE_PARENT, 2304 .ops = &clk_branch2_ops, 2305 }, 2306 }, 2307 }; 2308 2309 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 2310 .halt_reg = 0x2e274, 2311 .halt_check = BRANCH_HALT_VOTED, 2312 .clkr = { 2313 .enable_reg = 0x62010, 2314 .enable_mask = BIT(6), 2315 .hw.init = &(struct clk_init_data){ 2316 .name = "gcc_qupv3_wrap2_s2_clk", 2317 .parent_hws = (const struct clk_hw*[]) { 2318 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 2319 }, 2320 .num_parents = 1, 2321 .flags = CLK_SET_RATE_PARENT, 2322 .ops = &clk_branch2_ops, 2323 }, 2324 }, 2325 }; 2326 2327 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 2328 .halt_reg = 0x2e3a8, 2329 .halt_check = BRANCH_HALT_VOTED, 2330 .clkr = { 2331 .enable_reg = 0x62010, 2332 .enable_mask = BIT(7), 2333 .hw.init = &(struct clk_init_data){ 2334 .name = "gcc_qupv3_wrap2_s3_clk", 2335 .parent_hws = (const struct clk_hw*[]) { 2336 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 2337 }, 2338 .num_parents = 1, 2339 .flags = CLK_SET_RATE_PARENT, 2340 .ops = &clk_branch2_ops, 2341 }, 2342 }, 2343 }; 2344 2345 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 2346 .halt_reg = 0x2e4dc, 2347 .halt_check = BRANCH_HALT_VOTED, 2348 .clkr = { 2349 .enable_reg = 0x62010, 2350 .enable_mask = BIT(8), 2351 .hw.init = &(struct clk_init_data){ 2352 .name = "gcc_qupv3_wrap2_s4_clk", 2353 .parent_hws = (const struct clk_hw*[]) { 2354 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 2355 }, 2356 .num_parents = 1, 2357 .flags = CLK_SET_RATE_PARENT, 2358 .ops = &clk_branch2_ops, 2359 }, 2360 }, 2361 }; 2362 2363 static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 2364 .halt_reg = 0x2e610, 2365 .halt_check = BRANCH_HALT_VOTED, 2366 .clkr = { 2367 .enable_reg = 0x62010, 2368 .enable_mask = BIT(9), 2369 .hw.init = &(struct clk_init_data){ 2370 .name = "gcc_qupv3_wrap2_s5_clk", 2371 .parent_hws = (const struct clk_hw*[]) { 2372 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 2373 }, 2374 .num_parents = 1, 2375 .flags = CLK_SET_RATE_PARENT, 2376 .ops = &clk_branch2_ops, 2377 }, 2378 }, 2379 }; 2380 2381 static struct clk_branch gcc_qupv3_wrap2_s6_clk = { 2382 .halt_reg = 0x2e744, 2383 .halt_check = BRANCH_HALT_VOTED, 2384 .clkr = { 2385 .enable_reg = 0x62010, 2386 .enable_mask = BIT(10), 2387 .hw.init = &(struct clk_init_data){ 2388 .name = "gcc_qupv3_wrap2_s6_clk", 2389 .parent_hws = (const struct clk_hw*[]) { 2390 &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, 2391 }, 2392 .num_parents = 1, 2393 .flags = CLK_SET_RATE_PARENT, 2394 .ops = &clk_branch2_ops, 2395 }, 2396 }, 2397 }; 2398 2399 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2400 .halt_reg = 0x27004, 2401 .halt_check = BRANCH_HALT_VOTED, 2402 .hwcg_reg = 0x27004, 2403 .hwcg_bit = 1, 2404 .clkr = { 2405 .enable_reg = 0x62008, 2406 .enable_mask = BIT(6), 2407 .hw.init = &(struct clk_init_data){ 2408 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2409 .ops = &clk_branch2_ops, 2410 }, 2411 }, 2412 }; 2413 2414 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2415 .halt_reg = 0x27008, 2416 .halt_check = BRANCH_HALT_VOTED, 2417 .hwcg_reg = 0x27008, 2418 .hwcg_bit = 1, 2419 .clkr = { 2420 .enable_reg = 0x62008, 2421 .enable_mask = BIT(7), 2422 .hw.init = &(struct clk_init_data){ 2423 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2424 .ops = &clk_branch2_ops, 2425 }, 2426 }, 2427 }; 2428 2429 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2430 .halt_reg = 0x28004, 2431 .halt_check = BRANCH_HALT_VOTED, 2432 .hwcg_reg = 0x28004, 2433 .hwcg_bit = 1, 2434 .clkr = { 2435 .enable_reg = 0x62008, 2436 .enable_mask = BIT(20), 2437 .hw.init = &(struct clk_init_data){ 2438 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2439 .ops = &clk_branch2_ops, 2440 }, 2441 }, 2442 }; 2443 2444 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2445 .halt_reg = 0x28008, 2446 .halt_check = BRANCH_HALT_VOTED, 2447 .hwcg_reg = 0x28008, 2448 .hwcg_bit = 1, 2449 .clkr = { 2450 .enable_reg = 0x62008, 2451 .enable_mask = BIT(21), 2452 .hw.init = &(struct clk_init_data){ 2453 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2454 .ops = &clk_branch2_ops, 2455 }, 2456 }, 2457 }; 2458 2459 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 2460 .halt_reg = 0x2e004, 2461 .halt_check = BRANCH_HALT_VOTED, 2462 .hwcg_reg = 0x2e004, 2463 .hwcg_bit = 1, 2464 .clkr = { 2465 .enable_reg = 0x62010, 2466 .enable_mask = BIT(2), 2467 .hw.init = &(struct clk_init_data){ 2468 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 2469 .ops = &clk_branch2_ops, 2470 }, 2471 }, 2472 }; 2473 2474 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 2475 .halt_reg = 0x2e008, 2476 .halt_check = BRANCH_HALT_VOTED, 2477 .hwcg_reg = 0x2e008, 2478 .hwcg_bit = 1, 2479 .clkr = { 2480 .enable_reg = 0x62010, 2481 .enable_mask = BIT(1), 2482 .hw.init = &(struct clk_init_data){ 2483 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 2484 .ops = &clk_branch2_ops, 2485 }, 2486 }, 2487 }; 2488 2489 static struct clk_branch gcc_sdcc2_ahb_clk = { 2490 .halt_reg = 0x2400c, 2491 .halt_check = BRANCH_HALT, 2492 .clkr = { 2493 .enable_reg = 0x2400c, 2494 .enable_mask = BIT(0), 2495 .hw.init = &(struct clk_init_data){ 2496 .name = "gcc_sdcc2_ahb_clk", 2497 .ops = &clk_branch2_ops, 2498 }, 2499 }, 2500 }; 2501 2502 static struct clk_branch gcc_sdcc2_apps_clk = { 2503 .halt_reg = 0x24004, 2504 .halt_check = BRANCH_HALT, 2505 .clkr = { 2506 .enable_reg = 0x24004, 2507 .enable_mask = BIT(0), 2508 .hw.init = &(struct clk_init_data){ 2509 .name = "gcc_sdcc2_apps_clk", 2510 .parent_hws = (const struct clk_hw*[]) { 2511 &gcc_sdcc2_apps_clk_src.clkr.hw, 2512 }, 2513 .num_parents = 1, 2514 .flags = CLK_SET_RATE_PARENT, 2515 .ops = &clk_branch2_ops, 2516 }, 2517 }, 2518 }; 2519 2520 static struct clk_branch gcc_sdcc2_at_clk = { 2521 .halt_reg = 0x24010, 2522 .halt_check = BRANCH_HALT_VOTED, 2523 .hwcg_reg = 0x24010, 2524 .hwcg_bit = 1, 2525 .clkr = { 2526 .enable_reg = 0x24010, 2527 .enable_mask = BIT(0), 2528 .hw.init = &(struct clk_init_data){ 2529 .name = "gcc_sdcc2_at_clk", 2530 .ops = &clk_branch2_ops, 2531 }, 2532 }, 2533 }; 2534 2535 static struct clk_branch gcc_sdcc4_ahb_clk = { 2536 .halt_reg = 0x2600c, 2537 .halt_check = BRANCH_HALT, 2538 .clkr = { 2539 .enable_reg = 0x2600c, 2540 .enable_mask = BIT(0), 2541 .hw.init = &(struct clk_init_data){ 2542 .name = "gcc_sdcc4_ahb_clk", 2543 .ops = &clk_branch2_ops, 2544 }, 2545 }, 2546 }; 2547 2548 static struct clk_branch gcc_sdcc4_apps_clk = { 2549 .halt_reg = 0x26004, 2550 .halt_check = BRANCH_HALT, 2551 .clkr = { 2552 .enable_reg = 0x26004, 2553 .enable_mask = BIT(0), 2554 .hw.init = &(struct clk_init_data){ 2555 .name = "gcc_sdcc4_apps_clk", 2556 .parent_hws = (const struct clk_hw*[]) { 2557 &gcc_sdcc4_apps_clk_src.clkr.hw, 2558 }, 2559 .num_parents = 1, 2560 .flags = CLK_SET_RATE_PARENT, 2561 .ops = &clk_branch2_ops, 2562 }, 2563 }, 2564 }; 2565 2566 static struct clk_branch gcc_sdcc4_at_clk = { 2567 .halt_reg = 0x26010, 2568 .halt_check = BRANCH_HALT_VOTED, 2569 .hwcg_reg = 0x26010, 2570 .hwcg_bit = 1, 2571 .clkr = { 2572 .enable_reg = 0x26010, 2573 .enable_mask = BIT(0), 2574 .hw.init = &(struct clk_init_data){ 2575 .name = "gcc_sdcc4_at_clk", 2576 .ops = &clk_branch2_ops, 2577 }, 2578 }, 2579 }; 2580 2581 static struct clk_branch gcc_ufs_0_clkref_en = { 2582 .halt_reg = 0x9c000, 2583 .halt_check = BRANCH_HALT, 2584 .clkr = { 2585 .enable_reg = 0x9c000, 2586 .enable_mask = BIT(0), 2587 .hw.init = &(struct clk_init_data){ 2588 .name = "gcc_ufs_0_clkref_en", 2589 .ops = &clk_branch2_ops, 2590 }, 2591 }, 2592 }; 2593 2594 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2595 .halt_reg = 0x87020, 2596 .halt_check = BRANCH_HALT_VOTED, 2597 .hwcg_reg = 0x87020, 2598 .hwcg_bit = 1, 2599 .clkr = { 2600 .enable_reg = 0x87020, 2601 .enable_mask = BIT(0), 2602 .hw.init = &(struct clk_init_data){ 2603 .name = "gcc_ufs_phy_ahb_clk", 2604 .ops = &clk_branch2_ops, 2605 }, 2606 }, 2607 }; 2608 2609 static struct clk_branch gcc_ufs_phy_axi_clk = { 2610 .halt_reg = 0x87018, 2611 .halt_check = BRANCH_HALT_VOTED, 2612 .hwcg_reg = 0x87018, 2613 .hwcg_bit = 1, 2614 .clkr = { 2615 .enable_reg = 0x87018, 2616 .enable_mask = BIT(0), 2617 .hw.init = &(struct clk_init_data){ 2618 .name = "gcc_ufs_phy_axi_clk", 2619 .parent_hws = (const struct clk_hw*[]) { 2620 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2621 }, 2622 .num_parents = 1, 2623 .flags = CLK_SET_RATE_PARENT, 2624 .ops = &clk_branch2_ops, 2625 }, 2626 }, 2627 }; 2628 2629 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { 2630 .halt_reg = 0x87018, 2631 .halt_check = BRANCH_HALT_VOTED, 2632 .hwcg_reg = 0x87018, 2633 .hwcg_bit = 1, 2634 .clkr = { 2635 .enable_reg = 0x87018, 2636 .enable_mask = BIT(1), 2637 .hw.init = &(struct clk_init_data){ 2638 .name = "gcc_ufs_phy_axi_hw_ctl_clk", 2639 .parent_hws = (const struct clk_hw*[]) { 2640 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2641 }, 2642 .num_parents = 1, 2643 .flags = CLK_SET_RATE_PARENT, 2644 .ops = &clk_branch2_ops, 2645 }, 2646 }, 2647 }; 2648 2649 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2650 .halt_reg = 0x8706c, 2651 .halt_check = BRANCH_HALT_VOTED, 2652 .hwcg_reg = 0x8706c, 2653 .hwcg_bit = 1, 2654 .clkr = { 2655 .enable_reg = 0x8706c, 2656 .enable_mask = BIT(0), 2657 .hw.init = &(struct clk_init_data){ 2658 .name = "gcc_ufs_phy_ice_core_clk", 2659 .parent_hws = (const struct clk_hw*[]) { 2660 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2661 }, 2662 .num_parents = 1, 2663 .flags = CLK_SET_RATE_PARENT, 2664 .ops = &clk_branch2_ops, 2665 }, 2666 }, 2667 }; 2668 2669 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { 2670 .halt_reg = 0x8706c, 2671 .halt_check = BRANCH_HALT_VOTED, 2672 .hwcg_reg = 0x8706c, 2673 .hwcg_bit = 1, 2674 .clkr = { 2675 .enable_reg = 0x8706c, 2676 .enable_mask = BIT(1), 2677 .hw.init = &(struct clk_init_data){ 2678 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", 2679 .parent_hws = (const struct clk_hw*[]) { 2680 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2681 }, 2682 .num_parents = 1, 2683 .flags = CLK_SET_RATE_PARENT, 2684 .ops = &clk_branch2_ops, 2685 }, 2686 }, 2687 }; 2688 2689 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2690 .halt_reg = 0x870a4, 2691 .halt_check = BRANCH_HALT_VOTED, 2692 .hwcg_reg = 0x870a4, 2693 .hwcg_bit = 1, 2694 .clkr = { 2695 .enable_reg = 0x870a4, 2696 .enable_mask = BIT(0), 2697 .hw.init = &(struct clk_init_data){ 2698 .name = "gcc_ufs_phy_phy_aux_clk", 2699 .parent_hws = (const struct clk_hw*[]) { 2700 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2701 }, 2702 .num_parents = 1, 2703 .flags = CLK_SET_RATE_PARENT, 2704 .ops = &clk_branch2_ops, 2705 }, 2706 }, 2707 }; 2708 2709 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { 2710 .halt_reg = 0x870a4, 2711 .halt_check = BRANCH_HALT_VOTED, 2712 .hwcg_reg = 0x870a4, 2713 .hwcg_bit = 1, 2714 .clkr = { 2715 .enable_reg = 0x870a4, 2716 .enable_mask = BIT(1), 2717 .hw.init = &(struct clk_init_data){ 2718 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", 2719 .parent_hws = (const struct clk_hw*[]) { 2720 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2721 }, 2722 .num_parents = 1, 2723 .flags = CLK_SET_RATE_PARENT, 2724 .ops = &clk_branch2_ops, 2725 }, 2726 }, 2727 }; 2728 2729 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2730 .halt_reg = 0x87028, 2731 .halt_check = BRANCH_HALT_DELAY, 2732 .clkr = { 2733 .enable_reg = 0x87028, 2734 .enable_mask = BIT(0), 2735 .hw.init = &(struct clk_init_data){ 2736 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2737 .parent_hws = (const struct clk_hw*[]) { 2738 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 2739 }, 2740 .num_parents = 1, 2741 .flags = CLK_SET_RATE_PARENT, 2742 .ops = &clk_branch2_ops, 2743 }, 2744 }, 2745 }; 2746 2747 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2748 .halt_reg = 0x870c0, 2749 .halt_check = BRANCH_HALT_DELAY, 2750 .clkr = { 2751 .enable_reg = 0x870c0, 2752 .enable_mask = BIT(0), 2753 .hw.init = &(struct clk_init_data){ 2754 .name = "gcc_ufs_phy_rx_symbol_1_clk", 2755 .parent_hws = (const struct clk_hw*[]) { 2756 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 2757 }, 2758 .num_parents = 1, 2759 .flags = CLK_SET_RATE_PARENT, 2760 .ops = &clk_branch2_ops, 2761 }, 2762 }, 2763 }; 2764 2765 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2766 .halt_reg = 0x87024, 2767 .halt_check = BRANCH_HALT_DELAY, 2768 .clkr = { 2769 .enable_reg = 0x87024, 2770 .enable_mask = BIT(0), 2771 .hw.init = &(struct clk_init_data){ 2772 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2773 .parent_hws = (const struct clk_hw*[]) { 2774 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 2775 }, 2776 .num_parents = 1, 2777 .flags = CLK_SET_RATE_PARENT, 2778 .ops = &clk_branch2_ops, 2779 }, 2780 }, 2781 }; 2782 2783 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2784 .halt_reg = 0x87064, 2785 .halt_check = BRANCH_HALT_VOTED, 2786 .hwcg_reg = 0x87064, 2787 .hwcg_bit = 1, 2788 .clkr = { 2789 .enable_reg = 0x87064, 2790 .enable_mask = BIT(0), 2791 .hw.init = &(struct clk_init_data){ 2792 .name = "gcc_ufs_phy_unipro_core_clk", 2793 .parent_hws = (const struct clk_hw*[]) { 2794 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2795 }, 2796 .num_parents = 1, 2797 .flags = CLK_SET_RATE_PARENT, 2798 .ops = &clk_branch2_ops, 2799 }, 2800 }, 2801 }; 2802 2803 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { 2804 .halt_reg = 0x87064, 2805 .halt_check = BRANCH_HALT_VOTED, 2806 .hwcg_reg = 0x87064, 2807 .hwcg_bit = 1, 2808 .clkr = { 2809 .enable_reg = 0x87064, 2810 .enable_mask = BIT(1), 2811 .hw.init = &(struct clk_init_data){ 2812 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", 2813 .parent_hws = (const struct clk_hw*[]) { 2814 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2815 }, 2816 .num_parents = 1, 2817 .flags = CLK_SET_RATE_PARENT, 2818 .ops = &clk_branch2_ops, 2819 }, 2820 }, 2821 }; 2822 2823 static struct clk_branch gcc_usb30_prim_master_clk = { 2824 .halt_reg = 0x49018, 2825 .halt_check = BRANCH_HALT, 2826 .clkr = { 2827 .enable_reg = 0x49018, 2828 .enable_mask = BIT(0), 2829 .hw.init = &(struct clk_init_data){ 2830 .name = "gcc_usb30_prim_master_clk", 2831 .parent_hws = (const struct clk_hw*[]) { 2832 &gcc_usb30_prim_master_clk_src.clkr.hw, 2833 }, 2834 .num_parents = 1, 2835 .flags = CLK_SET_RATE_PARENT, 2836 .ops = &clk_branch2_ops, 2837 }, 2838 }, 2839 }; 2840 2841 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2842 .halt_reg = 0x49024, 2843 .halt_check = BRANCH_HALT, 2844 .clkr = { 2845 .enable_reg = 0x49024, 2846 .enable_mask = BIT(0), 2847 .hw.init = &(struct clk_init_data){ 2848 .name = "gcc_usb30_prim_mock_utmi_clk", 2849 .parent_hws = (const struct clk_hw*[]) { 2850 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2851 }, 2852 .num_parents = 1, 2853 .flags = CLK_SET_RATE_PARENT, 2854 .ops = &clk_branch2_ops, 2855 }, 2856 }, 2857 }; 2858 2859 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2860 .halt_reg = 0x49020, 2861 .halt_check = BRANCH_HALT, 2862 .clkr = { 2863 .enable_reg = 0x49020, 2864 .enable_mask = BIT(0), 2865 .hw.init = &(struct clk_init_data){ 2866 .name = "gcc_usb30_prim_sleep_clk", 2867 .ops = &clk_branch2_ops, 2868 }, 2869 }, 2870 }; 2871 2872 static struct clk_branch gcc_usb3_0_clkref_en = { 2873 .halt_reg = 0x9c010, 2874 .halt_check = BRANCH_HALT, 2875 .clkr = { 2876 .enable_reg = 0x9c010, 2877 .enable_mask = BIT(0), 2878 .hw.init = &(struct clk_init_data){ 2879 .name = "gcc_usb3_0_clkref_en", 2880 .ops = &clk_branch2_ops, 2881 }, 2882 }, 2883 }; 2884 2885 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2886 .halt_reg = 0x4905c, 2887 .halt_check = BRANCH_HALT, 2888 .clkr = { 2889 .enable_reg = 0x4905c, 2890 .enable_mask = BIT(0), 2891 .hw.init = &(struct clk_init_data){ 2892 .name = "gcc_usb3_prim_phy_aux_clk", 2893 .parent_hws = (const struct clk_hw*[]) { 2894 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2895 }, 2896 .num_parents = 1, 2897 .flags = CLK_SET_RATE_PARENT, 2898 .ops = &clk_branch2_ops, 2899 }, 2900 }, 2901 }; 2902 2903 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2904 .halt_reg = 0x49060, 2905 .halt_check = BRANCH_HALT, 2906 .clkr = { 2907 .enable_reg = 0x49060, 2908 .enable_mask = BIT(0), 2909 .hw.init = &(struct clk_init_data){ 2910 .name = "gcc_usb3_prim_phy_com_aux_clk", 2911 .parent_hws = (const struct clk_hw*[]) { 2912 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2913 }, 2914 .num_parents = 1, 2915 .flags = CLK_SET_RATE_PARENT, 2916 .ops = &clk_branch2_ops, 2917 }, 2918 }, 2919 }; 2920 2921 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2922 .halt_reg = 0x49064, 2923 .halt_check = BRANCH_HALT_DELAY, 2924 .hwcg_reg = 0x49064, 2925 .hwcg_bit = 1, 2926 .clkr = { 2927 .enable_reg = 0x49064, 2928 .enable_mask = BIT(0), 2929 .hw.init = &(struct clk_init_data){ 2930 .name = "gcc_usb3_prim_phy_pipe_clk", 2931 .parent_hws = (const struct clk_hw*[]) { 2932 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 2933 }, 2934 .num_parents = 1, 2935 .flags = CLK_SET_RATE_PARENT, 2936 .ops = &clk_branch2_ops, 2937 }, 2938 }, 2939 }; 2940 2941 static struct clk_branch gcc_video_axi0_clk = { 2942 .halt_reg = 0x42018, 2943 .halt_check = BRANCH_HALT_SKIP, 2944 .hwcg_reg = 0x42018, 2945 .hwcg_bit = 1, 2946 .clkr = { 2947 .enable_reg = 0x42018, 2948 .enable_mask = BIT(0), 2949 .hw.init = &(struct clk_init_data){ 2950 .name = "gcc_video_axi0_clk", 2951 .ops = &clk_branch2_ops, 2952 }, 2953 }, 2954 }; 2955 2956 static struct clk_branch gcc_video_axi1_clk = { 2957 .halt_reg = 0x42020, 2958 .halt_check = BRANCH_HALT_SKIP, 2959 .hwcg_reg = 0x42020, 2960 .hwcg_bit = 1, 2961 .clkr = { 2962 .enable_reg = 0x42020, 2963 .enable_mask = BIT(0), 2964 .hw.init = &(struct clk_init_data){ 2965 .name = "gcc_video_axi1_clk", 2966 .ops = &clk_branch2_ops, 2967 }, 2968 }, 2969 }; 2970 2971 static struct gdsc pcie_0_gdsc = { 2972 .gdscr = 0x7b004, 2973 .pd = { 2974 .name = "pcie_0_gdsc", 2975 }, 2976 .pwrsts = PWRSTS_OFF_ON, 2977 }; 2978 2979 static struct gdsc pcie_1_gdsc = { 2980 .gdscr = 0x9d004, 2981 .pd = { 2982 .name = "pcie_1_gdsc", 2983 }, 2984 .pwrsts = PWRSTS_OFF_ON, 2985 }; 2986 2987 static struct gdsc ufs_phy_gdsc = { 2988 .gdscr = 0x87004, 2989 .pd = { 2990 .name = "ufs_phy_gdsc", 2991 }, 2992 .pwrsts = PWRSTS_OFF_ON, 2993 }; 2994 2995 static struct gdsc usb30_prim_gdsc = { 2996 .gdscr = 0x49004, 2997 .pd = { 2998 .name = "usb30_prim_gdsc", 2999 }, 3000 .pwrsts = PWRSTS_OFF_ON, 3001 }; 3002 3003 static struct clk_regmap *gcc_sm8450_clocks[] = { 3004 [GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr, 3005 [GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr, 3006 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 3007 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, 3008 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 3009 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3010 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 3011 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 3012 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr, 3013 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3014 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 3015 [GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr, 3016 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3017 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, 3018 [GCC_EUSB3_0_CLKREF_EN] = &gcc_eusb3_0_clkref_en.clkr, 3019 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3020 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3021 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3022 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3023 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3024 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3025 [GCC_GPLL0] = &gcc_gpll0.clkr, 3026 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 3027 [GCC_GPLL4] = &gcc_gpll4.clkr, 3028 [GCC_GPLL9] = &gcc_gpll9.clkr, 3029 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3030 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3031 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3032 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3033 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3034 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 3035 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3036 [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr, 3037 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3038 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 3039 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 3040 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3041 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 3042 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3043 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 3044 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 3045 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 3046 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 3047 [GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr, 3048 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 3049 [GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr, 3050 [GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr, 3051 [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr, 3052 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 3053 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 3054 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr, 3055 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 3056 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 3057 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3058 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3059 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3060 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3061 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3062 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3063 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3064 [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr, 3065 [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr, 3066 [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr, 3067 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 3068 [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr, 3069 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3070 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 3071 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 3072 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3073 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3074 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3075 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3076 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3077 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3078 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3079 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3080 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3081 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3082 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3083 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3084 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 3085 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 3086 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 3087 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 3088 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3089 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3090 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3091 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3092 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3093 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3094 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3095 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3096 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3097 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3098 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3099 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3100 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3101 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3102 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 3103 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 3104 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 3105 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 3106 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 3107 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 3108 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 3109 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 3110 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 3111 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 3112 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 3113 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 3114 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 3115 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 3116 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 3117 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 3118 [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr, 3119 [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr, 3120 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3121 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3122 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3123 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3124 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 3125 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 3126 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3127 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3128 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3129 [GCC_SDCC2_AT_CLK] = &gcc_sdcc2_at_clk.clkr, 3130 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3131 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3132 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 3133 [GCC_SDCC4_AT_CLK] = &gcc_sdcc4_at_clk.clkr, 3134 [GCC_UFS_0_CLKREF_EN] = &gcc_ufs_0_clkref_en.clkr, 3135 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3136 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3137 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3138 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, 3139 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3140 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3141 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, 3142 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3143 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3144 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, 3145 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3146 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 3147 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3148 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 3149 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3150 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 3151 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3152 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 3153 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, 3154 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3155 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3156 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3157 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3158 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3159 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3160 [GCC_USB3_0_CLKREF_EN] = &gcc_usb3_0_clkref_en.clkr, 3161 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3162 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3163 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3164 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3165 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 3166 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3167 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 3168 }; 3169 3170 static const struct qcom_reset_map gcc_sm8450_resets[] = { 3171 [GCC_CAMERA_BCR] = { 0x36000 }, 3172 [GCC_DISPLAY_BCR] = { 0x37000 }, 3173 [GCC_GPU_BCR] = { 0x81000 }, 3174 [GCC_PCIE_0_BCR] = { 0x7b000 }, 3175 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x7c014 }, 3176 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x7c020 }, 3177 [GCC_PCIE_0_PHY_BCR] = { 0x7c01c }, 3178 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x7c028 }, 3179 [GCC_PCIE_1_BCR] = { 0x9d000 }, 3180 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x9e014 }, 3181 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x9e020 }, 3182 [GCC_PCIE_1_PHY_BCR] = { 0x9e01c }, 3183 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 }, 3184 [GCC_PCIE_PHY_BCR] = { 0x7f000 }, 3185 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c }, 3186 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 }, 3187 [GCC_PDM_BCR] = { 0x43000 }, 3188 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 }, 3189 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 }, 3190 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x2e000 }, 3191 [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 }, 3192 [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 }, 3193 [GCC_SDCC2_BCR] = { 0x24000 }, 3194 [GCC_SDCC4_BCR] = { 0x26000 }, 3195 [GCC_UFS_PHY_BCR] = { 0x87000 }, 3196 [GCC_USB30_PRIM_BCR] = { 0x49000 }, 3197 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 }, 3198 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 }, 3199 [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 }, 3200 [GCC_USB3_PHY_SEC_BCR] = { 0x6000c }, 3201 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 }, 3202 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 }, 3203 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 }, 3204 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x42018, 2 }, 3205 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x42020, 2 }, 3206 [GCC_VIDEO_BCR] = { 0x42000 }, 3207 }; 3208 3209 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3210 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3211 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3212 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3213 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3214 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3215 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3216 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 3217 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 3218 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3219 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3220 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 3221 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3222 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3223 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3224 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 3225 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 3226 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 3227 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 3228 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 3229 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 3230 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 3231 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src), 3232 }; 3233 3234 static struct gdsc *gcc_sm8450_gdscs[] = { 3235 [PCIE_0_GDSC] = &pcie_0_gdsc, 3236 [PCIE_1_GDSC] = &pcie_1_gdsc, 3237 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3238 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3239 }; 3240 3241 static const struct regmap_config gcc_sm8450_regmap_config = { 3242 .reg_bits = 32, 3243 .reg_stride = 4, 3244 .val_bits = 32, 3245 .max_register = 0x1f1030, 3246 .fast_io = true, 3247 }; 3248 3249 static const struct qcom_cc_desc gcc_sm8450_desc = { 3250 .config = &gcc_sm8450_regmap_config, 3251 .clks = gcc_sm8450_clocks, 3252 .num_clks = ARRAY_SIZE(gcc_sm8450_clocks), 3253 .resets = gcc_sm8450_resets, 3254 .num_resets = ARRAY_SIZE(gcc_sm8450_resets), 3255 .gdscs = gcc_sm8450_gdscs, 3256 .num_gdscs = ARRAY_SIZE(gcc_sm8450_gdscs), 3257 }; 3258 3259 static const struct of_device_id gcc_sm8450_match_table[] = { 3260 { .compatible = "qcom,gcc-sm8450" }, 3261 { } 3262 }; 3263 MODULE_DEVICE_TABLE(of, gcc_sm8450_match_table); 3264 3265 static int gcc_sm8450_probe(struct platform_device *pdev) 3266 { 3267 struct regmap *regmap; 3268 int ret; 3269 3270 regmap = qcom_cc_map(pdev, &gcc_sm8450_desc); 3271 if (IS_ERR(regmap)) 3272 return PTR_ERR(regmap); 3273 3274 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3275 ARRAY_SIZE(gcc_dfs_clocks)); 3276 if (ret) 3277 return ret; 3278 3279 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ 3280 regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14)); 3281 3282 /* 3283 * Keep the critical clock always-On 3284 * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk, 3285 * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, 3286 * gcc_video_xo_clk 3287 */ 3288 regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0)); 3289 regmap_update_bits(regmap, 0x36020, BIT(0), BIT(0)); 3290 regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0)); 3291 regmap_update_bits(regmap, 0x3701c, BIT(0), BIT(0)); 3292 regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0)); 3293 regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0)); 3294 regmap_update_bits(regmap, 0x42028, BIT(0), BIT(0)); 3295 3296 return qcom_cc_really_probe(pdev, &gcc_sm8450_desc, regmap); 3297 } 3298 3299 static struct platform_driver gcc_sm8450_driver = { 3300 .probe = gcc_sm8450_probe, 3301 .driver = { 3302 .name = "gcc-sm8450", 3303 .of_match_table = gcc_sm8450_match_table, 3304 }, 3305 }; 3306 3307 static int __init gcc_sm8450_init(void) 3308 { 3309 return platform_driver_register(&gcc_sm8450_driver); 3310 } 3311 subsys_initcall(gcc_sm8450_init); 3312 3313 static void __exit gcc_sm8450_exit(void) 3314 { 3315 platform_driver_unregister(&gcc_sm8450_driver); 3316 } 3317 module_exit(gcc_sm8450_exit); 3318 3319 MODULE_DESCRIPTION("QTI GCC SM8450 Driver"); 3320 MODULE_LICENSE("GPL v2"); 3321