1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, Linaro Limited 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/module.h> 9 #include <linux/of_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,gcc-sm8450.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "clk-regmap-divider.h" 19 #include "clk-regmap-mux.h" 20 #include "gdsc.h" 21 #include "reset.h" 22 23 enum { 24 P_BI_TCXO, 25 P_GCC_GPLL0_OUT_EVEN, 26 P_GCC_GPLL0_OUT_MAIN, 27 P_GCC_GPLL4_OUT_MAIN, 28 P_GCC_GPLL9_OUT_MAIN, 29 P_PCIE_0_PIPE_CLK, 30 P_PCIE_1_PHY_AUX_CLK, 31 P_PCIE_1_PIPE_CLK, 32 P_SLEEP_CLK, 33 P_UFS_PHY_RX_SYMBOL_0_CLK, 34 P_UFS_PHY_RX_SYMBOL_1_CLK, 35 P_UFS_PHY_TX_SYMBOL_0_CLK, 36 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 37 }; 38 39 static struct clk_alpha_pll gcc_gpll0 = { 40 .offset = 0x0, 41 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 42 .clkr = { 43 .enable_reg = 0x62018, 44 .enable_mask = BIT(0), 45 .hw.init = &(struct clk_init_data){ 46 .name = "gcc_gpll0", 47 .parent_data = &(const struct clk_parent_data){ 48 .fw_name = "bi_tcxo", 49 }, 50 .num_parents = 1, 51 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 52 }, 53 }, 54 }; 55 56 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 57 { 0x1, 2 }, 58 { } 59 }; 60 61 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 62 .offset = 0x0, 63 .post_div_shift = 10, 64 .post_div_table = post_div_table_gcc_gpll0_out_even, 65 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 66 .width = 4, 67 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 68 .clkr.hw.init = &(struct clk_init_data){ 69 .name = "gcc_gpll0_out_even", 70 .parent_data = &(const struct clk_parent_data){ 71 .hw = &gcc_gpll0.clkr.hw, 72 }, 73 .num_parents = 1, 74 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 75 }, 76 }; 77 78 static struct clk_alpha_pll gcc_gpll4 = { 79 .offset = 0x4000, 80 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 81 .clkr = { 82 .enable_reg = 0x62018, 83 .enable_mask = BIT(4), 84 .hw.init = &(struct clk_init_data){ 85 .name = "gcc_gpll4", 86 .parent_data = &(const struct clk_parent_data){ 87 .fw_name = "bi_tcxo", 88 }, 89 .num_parents = 1, 90 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 91 }, 92 }, 93 }; 94 95 static struct clk_alpha_pll gcc_gpll9 = { 96 .offset = 0x9000, 97 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 98 .clkr = { 99 .enable_reg = 0x62018, 100 .enable_mask = BIT(9), 101 .hw.init = &(struct clk_init_data){ 102 .name = "gcc_gpll9", 103 .parent_data = &(const struct clk_parent_data){ 104 .fw_name = "bi_tcxo", 105 }, 106 .num_parents = 1, 107 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 108 }, 109 }, 110 }; 111 112 static const struct parent_map gcc_parent_map_0[] = { 113 { P_BI_TCXO, 0 }, 114 { P_GCC_GPLL0_OUT_MAIN, 1 }, 115 { P_GCC_GPLL0_OUT_EVEN, 6 }, 116 }; 117 118 static const struct clk_parent_data gcc_parent_data_0[] = { 119 { .fw_name = "bi_tcxo" }, 120 { .hw = &gcc_gpll0.clkr.hw }, 121 { .hw = &gcc_gpll0_out_even.clkr.hw }, 122 }; 123 124 static const struct parent_map gcc_parent_map_1[] = { 125 { P_BI_TCXO, 0 }, 126 { P_GCC_GPLL0_OUT_MAIN, 1 }, 127 { P_SLEEP_CLK, 5 }, 128 { P_GCC_GPLL0_OUT_EVEN, 6 }, 129 }; 130 131 static const struct clk_parent_data gcc_parent_data_1[] = { 132 { .fw_name = "bi_tcxo" }, 133 { .hw = &gcc_gpll0.clkr.hw }, 134 { .fw_name = "sleep_clk" }, 135 { .hw = &gcc_gpll0_out_even.clkr.hw }, 136 }; 137 138 static const struct parent_map gcc_parent_map_2[] = { 139 { P_BI_TCXO, 0 }, 140 { P_SLEEP_CLK, 5 }, 141 }; 142 143 static const struct clk_parent_data gcc_parent_data_2[] = { 144 { .fw_name = "bi_tcxo" }, 145 { .fw_name = "sleep_clk" }, 146 }; 147 148 static const struct parent_map gcc_parent_map_3[] = { 149 { P_BI_TCXO, 0 }, 150 }; 151 152 static const struct clk_parent_data gcc_parent_data_3[] = { 153 { .fw_name = "bi_tcxo" }, 154 }; 155 156 static const struct parent_map gcc_parent_map_4[] = { 157 { P_PCIE_0_PIPE_CLK, 0 }, 158 { P_BI_TCXO, 2 }, 159 }; 160 161 static const struct clk_parent_data gcc_parent_data_4[] = { 162 { .fw_name = "pcie_0_pipe_clk", }, 163 { .fw_name = "bi_tcxo", }, 164 }; 165 166 static const struct parent_map gcc_parent_map_5[] = { 167 { P_PCIE_1_PHY_AUX_CLK, 0 }, 168 { P_BI_TCXO, 2 }, 169 }; 170 171 static const struct clk_parent_data gcc_parent_data_5[] = { 172 { .fw_name = "pcie_1_phy_aux_clk" }, 173 { .fw_name = "bi_tcxo" }, 174 }; 175 176 static const struct parent_map gcc_parent_map_6[] = { 177 { P_PCIE_1_PIPE_CLK, 0 }, 178 { P_BI_TCXO, 2 }, 179 }; 180 181 static const struct clk_parent_data gcc_parent_data_6[] = { 182 { .fw_name = "pcie_1_pipe_clk" }, 183 { .fw_name = "bi_tcxo" }, 184 }; 185 186 static const struct parent_map gcc_parent_map_7[] = { 187 { P_BI_TCXO, 0 }, 188 { P_GCC_GPLL0_OUT_MAIN, 1 }, 189 { P_GCC_GPLL9_OUT_MAIN, 2 }, 190 { P_GCC_GPLL4_OUT_MAIN, 5 }, 191 { P_GCC_GPLL0_OUT_EVEN, 6 }, 192 }; 193 194 static const struct clk_parent_data gcc_parent_data_7[] = { 195 { .fw_name = "bi_tcxo" }, 196 { .hw = &gcc_gpll0.clkr.hw }, 197 { .hw = &gcc_gpll9.clkr.hw }, 198 { .hw = &gcc_gpll4.clkr.hw }, 199 { .hw = &gcc_gpll0_out_even.clkr.hw }, 200 }; 201 202 static const struct parent_map gcc_parent_map_8[] = { 203 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, 204 { P_BI_TCXO, 2 }, 205 }; 206 207 static const struct clk_parent_data gcc_parent_data_8[] = { 208 { .fw_name = "ufs_phy_rx_symbol_0_clk" }, 209 { .fw_name = "bi_tcxo" }, 210 }; 211 212 static const struct parent_map gcc_parent_map_9[] = { 213 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, 214 { P_BI_TCXO, 2 }, 215 }; 216 217 static const struct clk_parent_data gcc_parent_data_9[] = { 218 { .fw_name = "ufs_phy_rx_symbol_1_clk" }, 219 { .fw_name = "bi_tcxo" }, 220 }; 221 222 static const struct parent_map gcc_parent_map_10[] = { 223 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, 224 { P_BI_TCXO, 2 }, 225 }; 226 227 static const struct clk_parent_data gcc_parent_data_10[] = { 228 { .fw_name = "ufs_phy_tx_symbol_0_clk" }, 229 { .fw_name = "bi_tcxo" }, 230 }; 231 232 static const struct parent_map gcc_parent_map_11[] = { 233 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 234 { P_BI_TCXO, 2 }, 235 }; 236 237 static const struct clk_parent_data gcc_parent_data_11[] = { 238 { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" }, 239 { .fw_name = "bi_tcxo" }, 240 }; 241 242 static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { 243 .reg = 0x7b060, 244 .shift = 0, 245 .width = 2, 246 .parent_map = gcc_parent_map_4, 247 .clkr = { 248 .hw.init = &(struct clk_init_data){ 249 .name = "gcc_pcie_0_pipe_clk_src", 250 .parent_data = gcc_parent_data_4, 251 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 252 .ops = &clk_regmap_mux_closest_ops, 253 }, 254 }, 255 }; 256 257 static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = { 258 .reg = 0x9d080, 259 .shift = 0, 260 .width = 2, 261 .parent_map = gcc_parent_map_5, 262 .clkr = { 263 .hw.init = &(struct clk_init_data){ 264 .name = "gcc_pcie_1_phy_aux_clk_src", 265 .parent_data = gcc_parent_data_5, 266 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 267 .ops = &clk_regmap_mux_closest_ops, 268 }, 269 }, 270 }; 271 272 static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { 273 .reg = 0x9d064, 274 .shift = 0, 275 .width = 2, 276 .parent_map = gcc_parent_map_6, 277 .clkr = { 278 .hw.init = &(struct clk_init_data){ 279 .name = "gcc_pcie_1_pipe_clk_src", 280 .parent_data = gcc_parent_data_6, 281 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 282 .ops = &clk_regmap_mux_closest_ops, 283 }, 284 }, 285 }; 286 287 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 288 .reg = 0x87060, 289 .shift = 0, 290 .width = 2, 291 .parent_map = gcc_parent_map_8, 292 .clkr = { 293 .hw.init = &(struct clk_init_data){ 294 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 295 .parent_data = gcc_parent_data_8, 296 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 297 .ops = &clk_regmap_mux_closest_ops, 298 }, 299 }, 300 }; 301 302 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 303 .reg = 0x870d0, 304 .shift = 0, 305 .width = 2, 306 .parent_map = gcc_parent_map_9, 307 .clkr = { 308 .hw.init = &(struct clk_init_data){ 309 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 310 .parent_data = gcc_parent_data_9, 311 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 312 .ops = &clk_regmap_mux_closest_ops, 313 }, 314 }, 315 }; 316 317 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 318 .reg = 0x87050, 319 .shift = 0, 320 .width = 2, 321 .parent_map = gcc_parent_map_10, 322 .clkr = { 323 .hw.init = &(struct clk_init_data){ 324 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 325 .parent_data = gcc_parent_data_10, 326 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 327 .ops = &clk_regmap_mux_closest_ops, 328 }, 329 }, 330 }; 331 332 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 333 .reg = 0x49068, 334 .shift = 0, 335 .width = 2, 336 .parent_map = gcc_parent_map_11, 337 .clkr = { 338 .hw.init = &(struct clk_init_data){ 339 .name = "gcc_usb3_prim_phy_pipe_clk_src", 340 .parent_data = gcc_parent_data_11, 341 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 342 .ops = &clk_regmap_mux_closest_ops, 343 }, 344 }, 345 }; 346 347 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 348 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 349 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 350 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 351 { } 352 }; 353 354 static struct clk_rcg2 gcc_gp1_clk_src = { 355 .cmd_rcgr = 0x74004, 356 .mnd_width = 8, 357 .hid_width = 5, 358 .parent_map = gcc_parent_map_1, 359 .freq_tbl = ftbl_gcc_gp1_clk_src, 360 .clkr.hw.init = &(struct clk_init_data){ 361 .name = "gcc_gp1_clk_src", 362 .parent_data = gcc_parent_data_1, 363 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 364 .flags = CLK_SET_RATE_PARENT, 365 .ops = &clk_rcg2_ops, 366 }, 367 }; 368 369 static struct clk_rcg2 gcc_gp2_clk_src = { 370 .cmd_rcgr = 0x75004, 371 .mnd_width = 8, 372 .hid_width = 5, 373 .parent_map = gcc_parent_map_1, 374 .freq_tbl = ftbl_gcc_gp1_clk_src, 375 .clkr.hw.init = &(struct clk_init_data){ 376 .name = "gcc_gp2_clk_src", 377 .parent_data = gcc_parent_data_1, 378 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 379 .flags = CLK_SET_RATE_PARENT, 380 .ops = &clk_rcg2_ops, 381 }, 382 }; 383 384 static struct clk_rcg2 gcc_gp3_clk_src = { 385 .cmd_rcgr = 0x76004, 386 .mnd_width = 8, 387 .hid_width = 5, 388 .parent_map = gcc_parent_map_1, 389 .freq_tbl = ftbl_gcc_gp1_clk_src, 390 .clkr.hw.init = &(struct clk_init_data){ 391 .name = "gcc_gp3_clk_src", 392 .parent_data = gcc_parent_data_1, 393 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 394 .flags = CLK_SET_RATE_PARENT, 395 .ops = &clk_rcg2_ops, 396 }, 397 }; 398 399 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 400 F(19200000, P_BI_TCXO, 1, 0, 0), 401 { } 402 }; 403 404 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 405 .cmd_rcgr = 0x7b064, 406 .mnd_width = 16, 407 .hid_width = 5, 408 .parent_map = gcc_parent_map_2, 409 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 410 .clkr.hw.init = &(struct clk_init_data){ 411 .name = "gcc_pcie_0_aux_clk_src", 412 .parent_data = gcc_parent_data_2, 413 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 414 .flags = CLK_SET_RATE_PARENT, 415 .ops = &clk_rcg2_ops, 416 }, 417 }; 418 419 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 420 F(19200000, P_BI_TCXO, 1, 0, 0), 421 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 422 { } 423 }; 424 425 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 426 .cmd_rcgr = 0x7b048, 427 .mnd_width = 0, 428 .hid_width = 5, 429 .parent_map = gcc_parent_map_0, 430 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 431 .clkr.hw.init = &(struct clk_init_data){ 432 .name = "gcc_pcie_0_phy_rchng_clk_src", 433 .parent_data = gcc_parent_data_0, 434 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 435 .flags = CLK_SET_RATE_PARENT, 436 .ops = &clk_rcg2_ops, 437 }, 438 }; 439 440 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 441 .cmd_rcgr = 0x9d068, 442 .mnd_width = 16, 443 .hid_width = 5, 444 .parent_map = gcc_parent_map_2, 445 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 446 .clkr.hw.init = &(struct clk_init_data){ 447 .name = "gcc_pcie_1_aux_clk_src", 448 .parent_data = gcc_parent_data_2, 449 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 450 .flags = CLK_SET_RATE_PARENT, 451 .ops = &clk_rcg2_ops, 452 }, 453 }; 454 455 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 456 .cmd_rcgr = 0x9d04c, 457 .mnd_width = 0, 458 .hid_width = 5, 459 .parent_map = gcc_parent_map_0, 460 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 461 .clkr.hw.init = &(struct clk_init_data){ 462 .name = "gcc_pcie_1_phy_rchng_clk_src", 463 .parent_data = gcc_parent_data_0, 464 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 465 .flags = CLK_SET_RATE_PARENT, 466 .ops = &clk_rcg2_ops, 467 }, 468 }; 469 470 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 471 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 472 { } 473 }; 474 475 static struct clk_rcg2 gcc_pdm2_clk_src = { 476 .cmd_rcgr = 0x43010, 477 .mnd_width = 0, 478 .hid_width = 5, 479 .parent_map = gcc_parent_map_0, 480 .freq_tbl = ftbl_gcc_pdm2_clk_src, 481 .clkr.hw.init = &(struct clk_init_data){ 482 .name = "gcc_pdm2_clk_src", 483 .parent_data = gcc_parent_data_0, 484 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 485 .flags = CLK_SET_RATE_PARENT, 486 .ops = &clk_rcg2_ops, 487 }, 488 }; 489 490 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 491 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 492 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 493 F(19200000, P_BI_TCXO, 1, 0, 0), 494 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 495 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 496 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 497 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 498 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 499 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 500 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 501 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 502 { } 503 }; 504 505 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 506 .name = "gcc_qupv3_wrap0_s0_clk_src", 507 .parent_data = gcc_parent_data_0, 508 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 509 .flags = CLK_SET_RATE_PARENT, 510 .ops = &clk_rcg2_ops, 511 }; 512 513 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 514 .cmd_rcgr = 0x27014, 515 .mnd_width = 16, 516 .hid_width = 5, 517 .parent_map = gcc_parent_map_0, 518 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 519 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 520 }; 521 522 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 523 .name = "gcc_qupv3_wrap0_s1_clk_src", 524 .parent_data = gcc_parent_data_0, 525 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 526 .flags = CLK_SET_RATE_PARENT, 527 .ops = &clk_rcg2_ops, 528 }; 529 530 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 531 .cmd_rcgr = 0x27148, 532 .mnd_width = 16, 533 .hid_width = 5, 534 .parent_map = gcc_parent_map_0, 535 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 536 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 537 }; 538 539 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 540 .name = "gcc_qupv3_wrap0_s2_clk_src", 541 .parent_data = gcc_parent_data_0, 542 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 543 .flags = CLK_SET_RATE_PARENT, 544 .ops = &clk_rcg2_ops, 545 }; 546 547 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 548 .cmd_rcgr = 0x2727c, 549 .mnd_width = 16, 550 .hid_width = 5, 551 .parent_map = gcc_parent_map_0, 552 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 553 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 554 }; 555 556 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 557 .name = "gcc_qupv3_wrap0_s3_clk_src", 558 .parent_data = gcc_parent_data_0, 559 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 560 .flags = CLK_SET_RATE_PARENT, 561 .ops = &clk_rcg2_ops, 562 }; 563 564 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 565 .cmd_rcgr = 0x273b0, 566 .mnd_width = 16, 567 .hid_width = 5, 568 .parent_map = gcc_parent_map_0, 569 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 570 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 571 }; 572 573 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 574 .name = "gcc_qupv3_wrap0_s4_clk_src", 575 .parent_data = gcc_parent_data_0, 576 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 577 .flags = CLK_SET_RATE_PARENT, 578 .ops = &clk_rcg2_ops, 579 }; 580 581 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 582 .cmd_rcgr = 0x274e4, 583 .mnd_width = 16, 584 .hid_width = 5, 585 .parent_map = gcc_parent_map_0, 586 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 587 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 588 }; 589 590 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] = { 591 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 592 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 593 F(19200000, P_BI_TCXO, 1, 0, 0), 594 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 595 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 596 F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0), 597 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 598 F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0), 599 { } 600 }; 601 602 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 603 .name = "gcc_qupv3_wrap0_s5_clk_src", 604 .parent_data = gcc_parent_data_0, 605 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 606 .flags = CLK_SET_RATE_PARENT, 607 .ops = &clk_rcg2_ops, 608 }; 609 610 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 611 .cmd_rcgr = 0x27618, 612 .mnd_width = 16, 613 .hid_width = 5, 614 .parent_map = gcc_parent_map_0, 615 .freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src, 616 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 617 }; 618 619 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 620 .name = "gcc_qupv3_wrap0_s6_clk_src", 621 .parent_data = gcc_parent_data_0, 622 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 623 .flags = CLK_SET_RATE_PARENT, 624 .ops = &clk_rcg2_ops, 625 }; 626 627 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 628 .cmd_rcgr = 0x2774c, 629 .mnd_width = 16, 630 .hid_width = 5, 631 .parent_map = gcc_parent_map_0, 632 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 633 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 634 }; 635 636 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 637 .name = "gcc_qupv3_wrap0_s7_clk_src", 638 .parent_data = gcc_parent_data_0, 639 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 640 .flags = CLK_SET_RATE_PARENT, 641 .ops = &clk_rcg2_ops, 642 }; 643 644 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 645 .cmd_rcgr = 0x27880, 646 .mnd_width = 16, 647 .hid_width = 5, 648 .parent_map = gcc_parent_map_0, 649 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 650 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 651 }; 652 653 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = { 654 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 655 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 656 F(19200000, P_BI_TCXO, 1, 0, 0), 657 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 658 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 659 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 660 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 661 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 662 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 663 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 664 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 665 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 666 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 667 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 668 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 669 { } 670 }; 671 672 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 673 .name = "gcc_qupv3_wrap1_s0_clk_src", 674 .parent_data = gcc_parent_data_0, 675 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 676 .flags = CLK_SET_RATE_PARENT, 677 .ops = &clk_rcg2_ops, 678 }; 679 680 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 681 .cmd_rcgr = 0x28014, 682 .mnd_width = 16, 683 .hid_width = 5, 684 .parent_map = gcc_parent_map_0, 685 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 686 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 687 }; 688 689 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 690 .name = "gcc_qupv3_wrap1_s1_clk_src", 691 .parent_data = gcc_parent_data_0, 692 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 693 .flags = CLK_SET_RATE_PARENT, 694 .ops = &clk_rcg2_ops, 695 }; 696 697 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 698 .cmd_rcgr = 0x28148, 699 .mnd_width = 16, 700 .hid_width = 5, 701 .parent_map = gcc_parent_map_0, 702 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 703 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 704 }; 705 706 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 707 .name = "gcc_qupv3_wrap1_s2_clk_src", 708 .parent_data = gcc_parent_data_0, 709 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 710 .flags = CLK_SET_RATE_PARENT, 711 .ops = &clk_rcg2_ops, 712 }; 713 714 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 715 .cmd_rcgr = 0x2827c, 716 .mnd_width = 16, 717 .hid_width = 5, 718 .parent_map = gcc_parent_map_0, 719 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 720 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 721 }; 722 723 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 724 .name = "gcc_qupv3_wrap1_s3_clk_src", 725 .parent_data = gcc_parent_data_0, 726 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 727 .flags = CLK_SET_RATE_PARENT, 728 .ops = &clk_rcg2_ops, 729 }; 730 731 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 732 .cmd_rcgr = 0x283b0, 733 .mnd_width = 16, 734 .hid_width = 5, 735 .parent_map = gcc_parent_map_0, 736 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 737 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 738 }; 739 740 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 741 .name = "gcc_qupv3_wrap1_s4_clk_src", 742 .parent_data = gcc_parent_data_0, 743 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 744 .flags = CLK_SET_RATE_PARENT, 745 .ops = &clk_rcg2_ops, 746 }; 747 748 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 749 .cmd_rcgr = 0x284e4, 750 .mnd_width = 16, 751 .hid_width = 5, 752 .parent_map = gcc_parent_map_0, 753 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 754 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 755 }; 756 757 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 758 .name = "gcc_qupv3_wrap1_s5_clk_src", 759 .parent_data = gcc_parent_data_0, 760 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 761 .flags = CLK_SET_RATE_PARENT, 762 .ops = &clk_rcg2_ops, 763 }; 764 765 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 766 .cmd_rcgr = 0x28618, 767 .mnd_width = 16, 768 .hid_width = 5, 769 .parent_map = gcc_parent_map_0, 770 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 771 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 772 }; 773 774 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 775 .name = "gcc_qupv3_wrap1_s6_clk_src", 776 .parent_data = gcc_parent_data_0, 777 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 778 .flags = CLK_SET_RATE_PARENT, 779 .ops = &clk_rcg2_ops, 780 }; 781 782 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 783 .cmd_rcgr = 0x2874c, 784 .mnd_width = 16, 785 .hid_width = 5, 786 .parent_map = gcc_parent_map_0, 787 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 788 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 789 }; 790 791 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 792 .name = "gcc_qupv3_wrap2_s0_clk_src", 793 .parent_data = gcc_parent_data_0, 794 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 795 .flags = CLK_SET_RATE_PARENT, 796 .ops = &clk_rcg2_ops, 797 }; 798 799 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 800 .cmd_rcgr = 0x2e014, 801 .mnd_width = 16, 802 .hid_width = 5, 803 .parent_map = gcc_parent_map_0, 804 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 805 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 806 }; 807 808 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 809 .name = "gcc_qupv3_wrap2_s1_clk_src", 810 .parent_data = gcc_parent_data_0, 811 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 812 .flags = CLK_SET_RATE_PARENT, 813 .ops = &clk_rcg2_ops, 814 }; 815 816 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 817 .cmd_rcgr = 0x2e148, 818 .mnd_width = 16, 819 .hid_width = 5, 820 .parent_map = gcc_parent_map_0, 821 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 822 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 823 }; 824 825 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 826 .name = "gcc_qupv3_wrap2_s2_clk_src", 827 .parent_data = gcc_parent_data_0, 828 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 829 .flags = CLK_SET_RATE_PARENT, 830 .ops = &clk_rcg2_ops, 831 }; 832 833 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 834 .cmd_rcgr = 0x2e27c, 835 .mnd_width = 16, 836 .hid_width = 5, 837 .parent_map = gcc_parent_map_0, 838 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 839 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 840 }; 841 842 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 843 .name = "gcc_qupv3_wrap2_s3_clk_src", 844 .parent_data = gcc_parent_data_0, 845 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 846 .flags = CLK_SET_RATE_PARENT, 847 .ops = &clk_rcg2_ops, 848 }; 849 850 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 851 .cmd_rcgr = 0x2e3b0, 852 .mnd_width = 16, 853 .hid_width = 5, 854 .parent_map = gcc_parent_map_0, 855 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 856 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 857 }; 858 859 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 860 .name = "gcc_qupv3_wrap2_s4_clk_src", 861 .parent_data = gcc_parent_data_0, 862 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 863 .flags = CLK_SET_RATE_PARENT, 864 .ops = &clk_rcg2_ops, 865 }; 866 867 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 868 .cmd_rcgr = 0x2e4e4, 869 .mnd_width = 16, 870 .hid_width = 5, 871 .parent_map = gcc_parent_map_0, 872 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 873 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 874 }; 875 876 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 877 .name = "gcc_qupv3_wrap2_s5_clk_src", 878 .parent_data = gcc_parent_data_0, 879 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 880 .flags = CLK_SET_RATE_PARENT, 881 .ops = &clk_rcg2_ops, 882 }; 883 884 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 885 .cmd_rcgr = 0x2e618, 886 .mnd_width = 16, 887 .hid_width = 5, 888 .parent_map = gcc_parent_map_0, 889 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 890 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 891 }; 892 893 static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { 894 .name = "gcc_qupv3_wrap2_s6_clk_src", 895 .parent_data = gcc_parent_data_0, 896 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 897 .flags = CLK_SET_RATE_PARENT, 898 .ops = &clk_rcg2_ops, 899 }; 900 901 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { 902 .cmd_rcgr = 0x2e74c, 903 .mnd_width = 16, 904 .hid_width = 5, 905 .parent_map = gcc_parent_map_0, 906 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 907 .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init, 908 }; 909 910 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 911 F(400000, P_BI_TCXO, 12, 1, 4), 912 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 913 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 914 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 915 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 916 { } 917 }; 918 919 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 920 .cmd_rcgr = 0x24014, 921 .mnd_width = 8, 922 .hid_width = 5, 923 .parent_map = gcc_parent_map_7, 924 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 925 .clkr.hw.init = &(struct clk_init_data){ 926 .name = "gcc_sdcc2_apps_clk_src", 927 .parent_data = gcc_parent_data_7, 928 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 929 .flags = CLK_SET_RATE_PARENT, 930 .ops = &clk_rcg2_ops, 931 }, 932 }; 933 934 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 935 F(400000, P_BI_TCXO, 12, 1, 4), 936 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 937 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 938 { } 939 }; 940 941 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 942 .cmd_rcgr = 0x26014, 943 .mnd_width = 8, 944 .hid_width = 5, 945 .parent_map = gcc_parent_map_0, 946 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 947 .clkr.hw.init = &(struct clk_init_data){ 948 .name = "gcc_sdcc4_apps_clk_src", 949 .parent_data = gcc_parent_data_0, 950 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 951 .flags = CLK_SET_RATE_PARENT, 952 .ops = &clk_rcg2_ops, 953 }, 954 }; 955 956 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 957 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 958 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 959 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 960 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 961 { } 962 }; 963 964 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 965 .cmd_rcgr = 0x8702c, 966 .mnd_width = 8, 967 .hid_width = 5, 968 .parent_map = gcc_parent_map_0, 969 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 970 .clkr.hw.init = &(struct clk_init_data){ 971 .name = "gcc_ufs_phy_axi_clk_src", 972 .parent_data = gcc_parent_data_0, 973 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 974 .flags = CLK_SET_RATE_PARENT, 975 .ops = &clk_rcg2_ops, 976 }, 977 }; 978 979 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 980 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 981 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 982 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 983 { } 984 }; 985 986 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 987 .cmd_rcgr = 0x87074, 988 .mnd_width = 0, 989 .hid_width = 5, 990 .parent_map = gcc_parent_map_0, 991 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 992 .clkr.hw.init = &(struct clk_init_data){ 993 .name = "gcc_ufs_phy_ice_core_clk_src", 994 .parent_data = gcc_parent_data_0, 995 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 996 .flags = CLK_SET_RATE_PARENT, 997 .ops = &clk_rcg2_ops, 998 }, 999 }; 1000 1001 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1002 F(9600000, P_BI_TCXO, 2, 0, 0), 1003 F(19200000, P_BI_TCXO, 1, 0, 0), 1004 { } 1005 }; 1006 1007 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1008 .cmd_rcgr = 0x870a8, 1009 .mnd_width = 0, 1010 .hid_width = 5, 1011 .parent_map = gcc_parent_map_3, 1012 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1013 .clkr.hw.init = &(struct clk_init_data){ 1014 .name = "gcc_ufs_phy_phy_aux_clk_src", 1015 .parent_data = gcc_parent_data_3, 1016 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1017 .flags = CLK_SET_RATE_PARENT, 1018 .ops = &clk_rcg2_ops, 1019 }, 1020 }; 1021 1022 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1023 .cmd_rcgr = 0x8708c, 1024 .mnd_width = 0, 1025 .hid_width = 5, 1026 .parent_map = gcc_parent_map_0, 1027 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1028 .clkr.hw.init = &(struct clk_init_data){ 1029 .name = "gcc_ufs_phy_unipro_core_clk_src", 1030 .parent_data = gcc_parent_data_0, 1031 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1032 .flags = CLK_SET_RATE_PARENT, 1033 .ops = &clk_rcg2_ops, 1034 }, 1035 }; 1036 1037 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1038 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 1039 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1040 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1041 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1042 { } 1043 }; 1044 1045 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1046 .cmd_rcgr = 0x49028, 1047 .mnd_width = 8, 1048 .hid_width = 5, 1049 .parent_map = gcc_parent_map_0, 1050 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1051 .clkr.hw.init = &(struct clk_init_data){ 1052 .name = "gcc_usb30_prim_master_clk_src", 1053 .parent_data = gcc_parent_data_0, 1054 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1055 .flags = CLK_SET_RATE_PARENT, 1056 .ops = &clk_rcg2_ops, 1057 }, 1058 }; 1059 1060 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1061 .cmd_rcgr = 0x49040, 1062 .mnd_width = 0, 1063 .hid_width = 5, 1064 .parent_map = gcc_parent_map_0, 1065 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1066 .clkr.hw.init = &(struct clk_init_data){ 1067 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1068 .parent_data = gcc_parent_data_0, 1069 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1070 .flags = CLK_SET_RATE_PARENT, 1071 .ops = &clk_rcg2_ops, 1072 }, 1073 }; 1074 1075 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1076 .cmd_rcgr = 0x4906c, 1077 .mnd_width = 0, 1078 .hid_width = 5, 1079 .parent_map = gcc_parent_map_2, 1080 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1081 .clkr.hw.init = &(struct clk_init_data){ 1082 .name = "gcc_usb3_prim_phy_aux_clk_src", 1083 .parent_data = gcc_parent_data_2, 1084 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1085 .flags = CLK_SET_RATE_PARENT, 1086 .ops = &clk_rcg2_ops, 1087 }, 1088 }; 1089 1090 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1091 .reg = 0x49058, 1092 .shift = 0, 1093 .width = 4, 1094 .clkr.hw.init = &(struct clk_init_data) { 1095 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1096 .parent_data = &(const struct clk_parent_data){ 1097 .hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1098 }, 1099 .num_parents = 1, 1100 .flags = CLK_SET_RATE_PARENT, 1101 .ops = &clk_regmap_div_ro_ops, 1102 }, 1103 }; 1104 1105 static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = { 1106 .halt_reg = 0x7b08c, 1107 .halt_check = BRANCH_HALT_SKIP, 1108 .hwcg_reg = 0x7b08c, 1109 .hwcg_bit = 1, 1110 .clkr = { 1111 .enable_reg = 0x62000, 1112 .enable_mask = BIT(12), 1113 .hw.init = &(struct clk_init_data){ 1114 .name = "gcc_aggre_noc_pcie_0_axi_clk", 1115 .ops = &clk_branch2_ops, 1116 }, 1117 }, 1118 }; 1119 1120 static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = { 1121 .halt_reg = 0x9d098, 1122 .halt_check = BRANCH_HALT_SKIP, 1123 .hwcg_reg = 0x9d098, 1124 .hwcg_bit = 1, 1125 .clkr = { 1126 .enable_reg = 0x62000, 1127 .enable_mask = BIT(11), 1128 .hw.init = &(struct clk_init_data){ 1129 .name = "gcc_aggre_noc_pcie_1_axi_clk", 1130 .ops = &clk_branch2_ops, 1131 }, 1132 }, 1133 }; 1134 1135 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1136 .halt_reg = 0x870d4, 1137 .halt_check = BRANCH_HALT_VOTED, 1138 .hwcg_reg = 0x870d4, 1139 .hwcg_bit = 1, 1140 .clkr = { 1141 .enable_reg = 0x870d4, 1142 .enable_mask = BIT(0), 1143 .hw.init = &(struct clk_init_data){ 1144 .name = "gcc_aggre_ufs_phy_axi_clk", 1145 .parent_data = &(const struct clk_parent_data){ 1146 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 1147 }, 1148 .num_parents = 1, 1149 .flags = CLK_SET_RATE_PARENT, 1150 .ops = &clk_branch2_ops, 1151 }, 1152 }, 1153 }; 1154 1155 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { 1156 .halt_reg = 0x870d4, 1157 .halt_check = BRANCH_HALT_VOTED, 1158 .hwcg_reg = 0x870d4, 1159 .hwcg_bit = 1, 1160 .clkr = { 1161 .enable_reg = 0x870d4, 1162 .enable_mask = BIT(1), 1163 .hw.init = &(struct clk_init_data){ 1164 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", 1165 .parent_data = &(const struct clk_parent_data){ 1166 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 1167 }, 1168 .num_parents = 1, 1169 .flags = CLK_SET_RATE_PARENT, 1170 .ops = &clk_branch2_ops, 1171 }, 1172 }, 1173 }; 1174 1175 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1176 .halt_reg = 0x49088, 1177 .halt_check = BRANCH_HALT_VOTED, 1178 .hwcg_reg = 0x49088, 1179 .hwcg_bit = 1, 1180 .clkr = { 1181 .enable_reg = 0x49088, 1182 .enable_mask = BIT(0), 1183 .hw.init = &(struct clk_init_data){ 1184 .name = "gcc_aggre_usb3_prim_axi_clk", 1185 .parent_data = &(const struct clk_parent_data){ 1186 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 1187 }, 1188 .num_parents = 1, 1189 .flags = CLK_SET_RATE_PARENT, 1190 .ops = &clk_branch2_ops, 1191 }, 1192 }, 1193 }; 1194 1195 static struct clk_branch gcc_boot_rom_ahb_clk = { 1196 .halt_reg = 0x48004, 1197 .halt_check = BRANCH_HALT_VOTED, 1198 .hwcg_reg = 0x48004, 1199 .hwcg_bit = 1, 1200 .clkr = { 1201 .enable_reg = 0x62000, 1202 .enable_mask = BIT(10), 1203 .hw.init = &(struct clk_init_data){ 1204 .name = "gcc_boot_rom_ahb_clk", 1205 .ops = &clk_branch2_ops, 1206 }, 1207 }, 1208 }; 1209 1210 static struct clk_branch gcc_camera_hf_axi_clk = { 1211 .halt_reg = 0x36010, 1212 .halt_check = BRANCH_HALT_SKIP, 1213 .hwcg_reg = 0x36010, 1214 .hwcg_bit = 1, 1215 .clkr = { 1216 .enable_reg = 0x36010, 1217 .enable_mask = BIT(0), 1218 .hw.init = &(struct clk_init_data){ 1219 .name = "gcc_camera_hf_axi_clk", 1220 .ops = &clk_branch2_ops, 1221 }, 1222 }, 1223 }; 1224 1225 static struct clk_branch gcc_camera_sf_axi_clk = { 1226 .halt_reg = 0x36018, 1227 .halt_check = BRANCH_HALT_SKIP, 1228 .hwcg_reg = 0x36018, 1229 .hwcg_bit = 1, 1230 .clkr = { 1231 .enable_reg = 0x36018, 1232 .enable_mask = BIT(0), 1233 .hw.init = &(struct clk_init_data){ 1234 .name = "gcc_camera_sf_axi_clk", 1235 .ops = &clk_branch2_ops, 1236 }, 1237 }, 1238 }; 1239 1240 static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = { 1241 .halt_reg = 0x20030, 1242 .halt_check = BRANCH_HALT_VOTED, 1243 .hwcg_reg = 0x20030, 1244 .hwcg_bit = 1, 1245 .clkr = { 1246 .enable_reg = 0x62000, 1247 .enable_mask = BIT(20), 1248 .hw.init = &(struct clk_init_data){ 1249 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk", 1250 .ops = &clk_branch2_ops, 1251 }, 1252 }, 1253 }; 1254 1255 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1256 .halt_reg = 0x49084, 1257 .halt_check = BRANCH_HALT_VOTED, 1258 .hwcg_reg = 0x49084, 1259 .hwcg_bit = 1, 1260 .clkr = { 1261 .enable_reg = 0x49084, 1262 .enable_mask = BIT(0), 1263 .hw.init = &(struct clk_init_data){ 1264 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1265 .parent_data = &(const struct clk_parent_data){ 1266 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 1267 }, 1268 .num_parents = 1, 1269 .flags = CLK_SET_RATE_PARENT, 1270 .ops = &clk_branch2_ops, 1271 }, 1272 }, 1273 }; 1274 1275 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1276 .halt_reg = 0x81154, 1277 .halt_check = BRANCH_HALT_SKIP, 1278 .hwcg_reg = 0x81154, 1279 .hwcg_bit = 1, 1280 .clkr = { 1281 .enable_reg = 0x81154, 1282 .enable_mask = BIT(0), 1283 .hw.init = &(struct clk_init_data){ 1284 .name = "gcc_ddrss_gpu_axi_clk", 1285 .ops = &clk_branch2_aon_ops, 1286 }, 1287 }, 1288 }; 1289 1290 static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = { 1291 .halt_reg = 0x9d094, 1292 .halt_check = BRANCH_HALT_SKIP, 1293 .hwcg_reg = 0x9d094, 1294 .hwcg_bit = 1, 1295 .clkr = { 1296 .enable_reg = 0x62000, 1297 .enable_mask = BIT(19), 1298 .hw.init = &(struct clk_init_data){ 1299 .name = "gcc_ddrss_pcie_sf_tbu_clk", 1300 .ops = &clk_branch2_ops, 1301 }, 1302 }, 1303 }; 1304 1305 static struct clk_branch gcc_disp_hf_axi_clk = { 1306 .halt_reg = 0x3700c, 1307 .halt_check = BRANCH_HALT_SKIP, 1308 .hwcg_reg = 0x3700c, 1309 .hwcg_bit = 1, 1310 .clkr = { 1311 .enable_reg = 0x3700c, 1312 .enable_mask = BIT(0), 1313 .hw.init = &(struct clk_init_data){ 1314 .name = "gcc_disp_hf_axi_clk", 1315 .ops = &clk_branch2_ops, 1316 }, 1317 }, 1318 }; 1319 1320 static struct clk_branch gcc_disp_sf_axi_clk = { 1321 .halt_reg = 0x37014, 1322 .halt_check = BRANCH_HALT_SKIP, 1323 .hwcg_reg = 0x37014, 1324 .hwcg_bit = 1, 1325 .clkr = { 1326 .enable_reg = 0x37014, 1327 .enable_mask = BIT(0), 1328 .hw.init = &(struct clk_init_data){ 1329 .name = "gcc_disp_sf_axi_clk", 1330 .ops = &clk_branch2_ops, 1331 }, 1332 }, 1333 }; 1334 1335 static struct clk_branch gcc_eusb3_0_clkref_en = { 1336 .halt_reg = 0x9c00c, 1337 .halt_check = BRANCH_HALT, 1338 .clkr = { 1339 .enable_reg = 0x9c00c, 1340 .enable_mask = BIT(0), 1341 .hw.init = &(struct clk_init_data){ 1342 .name = "gcc_eusb3_0_clkref_en", 1343 .ops = &clk_branch2_ops, 1344 }, 1345 }, 1346 }; 1347 1348 static struct clk_branch gcc_gp1_clk = { 1349 .halt_reg = 0x74000, 1350 .halt_check = BRANCH_HALT, 1351 .clkr = { 1352 .enable_reg = 0x74000, 1353 .enable_mask = BIT(0), 1354 .hw.init = &(struct clk_init_data){ 1355 .name = "gcc_gp1_clk", 1356 .parent_data = &(const struct clk_parent_data){ 1357 .hw = &gcc_gp1_clk_src.clkr.hw, 1358 }, 1359 .num_parents = 1, 1360 .flags = CLK_SET_RATE_PARENT, 1361 .ops = &clk_branch2_ops, 1362 }, 1363 }, 1364 }; 1365 1366 static struct clk_branch gcc_gp2_clk = { 1367 .halt_reg = 0x75000, 1368 .halt_check = BRANCH_HALT, 1369 .clkr = { 1370 .enable_reg = 0x75000, 1371 .enable_mask = BIT(0), 1372 .hw.init = &(struct clk_init_data){ 1373 .name = "gcc_gp2_clk", 1374 .parent_data = &(const struct clk_parent_data){ 1375 .hw = &gcc_gp2_clk_src.clkr.hw, 1376 }, 1377 .num_parents = 1, 1378 .flags = CLK_SET_RATE_PARENT, 1379 .ops = &clk_branch2_ops, 1380 }, 1381 }, 1382 }; 1383 1384 static struct clk_branch gcc_gp3_clk = { 1385 .halt_reg = 0x76000, 1386 .halt_check = BRANCH_HALT, 1387 .clkr = { 1388 .enable_reg = 0x76000, 1389 .enable_mask = BIT(0), 1390 .hw.init = &(struct clk_init_data){ 1391 .name = "gcc_gp3_clk", 1392 .parent_data = &(const struct clk_parent_data){ 1393 .hw = &gcc_gp3_clk_src.clkr.hw, 1394 }, 1395 .num_parents = 1, 1396 .flags = CLK_SET_RATE_PARENT, 1397 .ops = &clk_branch2_ops, 1398 }, 1399 }, 1400 }; 1401 1402 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1403 .halt_check = BRANCH_HALT_DELAY, 1404 .clkr = { 1405 .enable_reg = 0x62000, 1406 .enable_mask = BIT(15), 1407 .hw.init = &(struct clk_init_data){ 1408 .name = "gcc_gpu_gpll0_clk_src", 1409 .parent_data = &(const struct clk_parent_data){ 1410 .hw = &gcc_gpll0.clkr.hw, 1411 }, 1412 .num_parents = 1, 1413 .flags = CLK_SET_RATE_PARENT, 1414 .ops = &clk_branch2_ops, 1415 }, 1416 }, 1417 }; 1418 1419 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1420 .halt_check = BRANCH_HALT_DELAY, 1421 .clkr = { 1422 .enable_reg = 0x62000, 1423 .enable_mask = BIT(16), 1424 .hw.init = &(struct clk_init_data){ 1425 .name = "gcc_gpu_gpll0_div_clk_src", 1426 .parent_data = &(const struct clk_parent_data){ 1427 .hw = &gcc_gpll0_out_even.clkr.hw, 1428 }, 1429 .num_parents = 1, 1430 .flags = CLK_SET_RATE_PARENT, 1431 .ops = &clk_branch2_ops, 1432 }, 1433 }, 1434 }; 1435 1436 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1437 .halt_reg = 0x81010, 1438 .halt_check = BRANCH_HALT_VOTED, 1439 .hwcg_reg = 0x81010, 1440 .hwcg_bit = 1, 1441 .clkr = { 1442 .enable_reg = 0x81010, 1443 .enable_mask = BIT(0), 1444 .hw.init = &(struct clk_init_data){ 1445 .name = "gcc_gpu_memnoc_gfx_clk", 1446 .ops = &clk_branch2_ops, 1447 }, 1448 }, 1449 }; 1450 1451 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1452 .halt_reg = 0x81018, 1453 .halt_check = BRANCH_HALT_DELAY, 1454 .clkr = { 1455 .enable_reg = 0x81018, 1456 .enable_mask = BIT(0), 1457 .hw.init = &(struct clk_init_data){ 1458 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1459 .ops = &clk_branch2_ops, 1460 }, 1461 }, 1462 }; 1463 1464 static struct clk_branch gcc_pcie_0_aux_clk = { 1465 .halt_reg = 0x7b034, 1466 .halt_check = BRANCH_HALT_VOTED, 1467 .clkr = { 1468 .enable_reg = 0x62008, 1469 .enable_mask = BIT(3), 1470 .hw.init = &(struct clk_init_data){ 1471 .name = "gcc_pcie_0_aux_clk", 1472 .parent_data = &(const struct clk_parent_data){ 1473 .hw = &gcc_pcie_0_aux_clk_src.clkr.hw, 1474 }, 1475 .num_parents = 1, 1476 .flags = CLK_SET_RATE_PARENT, 1477 .ops = &clk_branch2_ops, 1478 }, 1479 }, 1480 }; 1481 1482 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1483 .halt_reg = 0x7b030, 1484 .halt_check = BRANCH_HALT_VOTED, 1485 .hwcg_reg = 0x7b030, 1486 .hwcg_bit = 1, 1487 .clkr = { 1488 .enable_reg = 0x62008, 1489 .enable_mask = BIT(2), 1490 .hw.init = &(struct clk_init_data){ 1491 .name = "gcc_pcie_0_cfg_ahb_clk", 1492 .ops = &clk_branch2_ops, 1493 }, 1494 }, 1495 }; 1496 1497 static struct clk_branch gcc_pcie_0_clkref_en = { 1498 .halt_reg = 0x9c004, 1499 .halt_check = BRANCH_HALT, 1500 .clkr = { 1501 .enable_reg = 0x9c004, 1502 .enable_mask = BIT(0), 1503 .hw.init = &(struct clk_init_data){ 1504 .name = "gcc_pcie_0_clkref_en", 1505 .ops = &clk_branch2_ops, 1506 }, 1507 }, 1508 }; 1509 1510 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1511 .halt_reg = 0x7b028, 1512 .halt_check = BRANCH_HALT_SKIP, 1513 .clkr = { 1514 .enable_reg = 0x62008, 1515 .enable_mask = BIT(1), 1516 .hw.init = &(struct clk_init_data){ 1517 .name = "gcc_pcie_0_mstr_axi_clk", 1518 .ops = &clk_branch2_ops, 1519 }, 1520 }, 1521 }; 1522 1523 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 1524 .halt_reg = 0x7b044, 1525 .halt_check = BRANCH_HALT_VOTED, 1526 .clkr = { 1527 .enable_reg = 0x62000, 1528 .enable_mask = BIT(22), 1529 .hw.init = &(struct clk_init_data){ 1530 .name = "gcc_pcie_0_phy_rchng_clk", 1531 .parent_data = &(const struct clk_parent_data){ 1532 .hw = &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1533 }, 1534 .num_parents = 1, 1535 .flags = CLK_SET_RATE_PARENT, 1536 .ops = &clk_branch2_ops, 1537 }, 1538 }, 1539 }; 1540 1541 static struct clk_branch gcc_pcie_0_pipe_clk = { 1542 .halt_reg = 0x7b03c, 1543 .halt_check = BRANCH_HALT_SKIP, 1544 .clkr = { 1545 .enable_reg = 0x62008, 1546 .enable_mask = BIT(4), 1547 .hw.init = &(struct clk_init_data){ 1548 .name = "gcc_pcie_0_pipe_clk", 1549 .parent_data = &(const struct clk_parent_data){ 1550 .hw = &gcc_pcie_0_pipe_clk_src.clkr.hw, 1551 }, 1552 .num_parents = 1, 1553 .flags = CLK_SET_RATE_PARENT, 1554 .ops = &clk_branch2_ops, 1555 }, 1556 }, 1557 }; 1558 1559 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1560 .halt_reg = 0x7b020, 1561 .halt_check = BRANCH_HALT_VOTED, 1562 .hwcg_reg = 0x7b020, 1563 .hwcg_bit = 1, 1564 .clkr = { 1565 .enable_reg = 0x62008, 1566 .enable_mask = BIT(0), 1567 .hw.init = &(struct clk_init_data){ 1568 .name = "gcc_pcie_0_slv_axi_clk", 1569 .ops = &clk_branch2_ops, 1570 }, 1571 }, 1572 }; 1573 1574 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1575 .halt_reg = 0x7b01c, 1576 .halt_check = BRANCH_HALT_VOTED, 1577 .clkr = { 1578 .enable_reg = 0x62008, 1579 .enable_mask = BIT(5), 1580 .hw.init = &(struct clk_init_data){ 1581 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1582 .ops = &clk_branch2_ops, 1583 }, 1584 }, 1585 }; 1586 1587 static struct clk_branch gcc_pcie_1_aux_clk = { 1588 .halt_reg = 0x9d030, 1589 .halt_check = BRANCH_HALT_VOTED, 1590 .clkr = { 1591 .enable_reg = 0x62000, 1592 .enable_mask = BIT(29), 1593 .hw.init = &(struct clk_init_data){ 1594 .name = "gcc_pcie_1_aux_clk", 1595 .parent_data = &(const struct clk_parent_data){ 1596 .hw = &gcc_pcie_1_aux_clk_src.clkr.hw, 1597 }, 1598 .num_parents = 1, 1599 .flags = CLK_SET_RATE_PARENT, 1600 .ops = &clk_branch2_ops, 1601 }, 1602 }, 1603 }; 1604 1605 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1606 .halt_reg = 0x9d02c, 1607 .halt_check = BRANCH_HALT_VOTED, 1608 .hwcg_reg = 0x9d02c, 1609 .hwcg_bit = 1, 1610 .clkr = { 1611 .enable_reg = 0x62000, 1612 .enable_mask = BIT(28), 1613 .hw.init = &(struct clk_init_data){ 1614 .name = "gcc_pcie_1_cfg_ahb_clk", 1615 .ops = &clk_branch2_ops, 1616 }, 1617 }, 1618 }; 1619 1620 static struct clk_branch gcc_pcie_1_clkref_en = { 1621 .halt_reg = 0x9c008, 1622 .halt_check = BRANCH_HALT, 1623 .clkr = { 1624 .enable_reg = 0x9c008, 1625 .enable_mask = BIT(0), 1626 .hw.init = &(struct clk_init_data){ 1627 .name = "gcc_pcie_1_clkref_en", 1628 .ops = &clk_branch2_ops, 1629 }, 1630 }, 1631 }; 1632 1633 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1634 .halt_reg = 0x9d024, 1635 .halt_check = BRANCH_HALT_SKIP, 1636 .clkr = { 1637 .enable_reg = 0x62000, 1638 .enable_mask = BIT(27), 1639 .hw.init = &(struct clk_init_data){ 1640 .name = "gcc_pcie_1_mstr_axi_clk", 1641 .ops = &clk_branch2_ops, 1642 }, 1643 }, 1644 }; 1645 1646 static struct clk_branch gcc_pcie_1_phy_aux_clk = { 1647 .halt_reg = 0x9d038, 1648 .halt_check = BRANCH_HALT_VOTED, 1649 .clkr = { 1650 .enable_reg = 0x62000, 1651 .enable_mask = BIT(24), 1652 .hw.init = &(struct clk_init_data){ 1653 .name = "gcc_pcie_1_phy_aux_clk", 1654 .parent_data = &(const struct clk_parent_data){ 1655 .hw = &gcc_pcie_1_phy_aux_clk_src.clkr.hw, 1656 }, 1657 .num_parents = 1, 1658 .flags = CLK_SET_RATE_PARENT, 1659 .ops = &clk_branch2_ops, 1660 }, 1661 }, 1662 }; 1663 1664 static struct clk_branch gcc_pcie_1_phy_rchng_clk = { 1665 .halt_reg = 0x9d048, 1666 .halt_check = BRANCH_HALT_VOTED, 1667 .clkr = { 1668 .enable_reg = 0x62000, 1669 .enable_mask = BIT(23), 1670 .hw.init = &(struct clk_init_data){ 1671 .name = "gcc_pcie_1_phy_rchng_clk", 1672 .parent_data = &(const struct clk_parent_data){ 1673 .hw = &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 1674 }, 1675 .num_parents = 1, 1676 .flags = CLK_SET_RATE_PARENT, 1677 .ops = &clk_branch2_ops, 1678 }, 1679 }, 1680 }; 1681 1682 static struct clk_branch gcc_pcie_1_pipe_clk = { 1683 .halt_reg = 0x9d040, 1684 .halt_check = BRANCH_HALT_SKIP, 1685 .clkr = { 1686 .enable_reg = 0x62000, 1687 .enable_mask = BIT(30), 1688 .hw.init = &(struct clk_init_data){ 1689 .name = "gcc_pcie_1_pipe_clk", 1690 .parent_data = &(const struct clk_parent_data){ 1691 .hw = &gcc_pcie_1_pipe_clk_src.clkr.hw, 1692 }, 1693 .num_parents = 1, 1694 .flags = CLK_SET_RATE_PARENT, 1695 .ops = &clk_branch2_ops, 1696 }, 1697 }, 1698 }; 1699 1700 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1701 .halt_reg = 0x9d01c, 1702 .halt_check = BRANCH_HALT_VOTED, 1703 .hwcg_reg = 0x9d01c, 1704 .hwcg_bit = 1, 1705 .clkr = { 1706 .enable_reg = 0x62000, 1707 .enable_mask = BIT(26), 1708 .hw.init = &(struct clk_init_data){ 1709 .name = "gcc_pcie_1_slv_axi_clk", 1710 .ops = &clk_branch2_ops, 1711 }, 1712 }, 1713 }; 1714 1715 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 1716 .halt_reg = 0x9d018, 1717 .halt_check = BRANCH_HALT_VOTED, 1718 .clkr = { 1719 .enable_reg = 0x62000, 1720 .enable_mask = BIT(25), 1721 .hw.init = &(struct clk_init_data){ 1722 .name = "gcc_pcie_1_slv_q2a_axi_clk", 1723 .ops = &clk_branch2_ops, 1724 }, 1725 }, 1726 }; 1727 1728 static struct clk_branch gcc_pdm2_clk = { 1729 .halt_reg = 0x4300c, 1730 .halt_check = BRANCH_HALT, 1731 .clkr = { 1732 .enable_reg = 0x4300c, 1733 .enable_mask = BIT(0), 1734 .hw.init = &(struct clk_init_data){ 1735 .name = "gcc_pdm2_clk", 1736 .parent_data = &(const struct clk_parent_data){ 1737 .hw = &gcc_pdm2_clk_src.clkr.hw, 1738 }, 1739 .num_parents = 1, 1740 .flags = CLK_SET_RATE_PARENT, 1741 .ops = &clk_branch2_ops, 1742 }, 1743 }, 1744 }; 1745 1746 static struct clk_branch gcc_pdm_ahb_clk = { 1747 .halt_reg = 0x43004, 1748 .halt_check = BRANCH_HALT_VOTED, 1749 .hwcg_reg = 0x43004, 1750 .hwcg_bit = 1, 1751 .clkr = { 1752 .enable_reg = 0x43004, 1753 .enable_mask = BIT(0), 1754 .hw.init = &(struct clk_init_data){ 1755 .name = "gcc_pdm_ahb_clk", 1756 .ops = &clk_branch2_ops, 1757 }, 1758 }, 1759 }; 1760 1761 static struct clk_branch gcc_pdm_xo4_clk = { 1762 .halt_reg = 0x43008, 1763 .halt_check = BRANCH_HALT, 1764 .clkr = { 1765 .enable_reg = 0x43008, 1766 .enable_mask = BIT(0), 1767 .hw.init = &(struct clk_init_data){ 1768 .name = "gcc_pdm_xo4_clk", 1769 .ops = &clk_branch2_ops, 1770 }, 1771 }, 1772 }; 1773 1774 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 1775 .halt_reg = 0x36008, 1776 .halt_check = BRANCH_HALT_VOTED, 1777 .hwcg_reg = 0x36008, 1778 .hwcg_bit = 1, 1779 .clkr = { 1780 .enable_reg = 0x36008, 1781 .enable_mask = BIT(0), 1782 .hw.init = &(struct clk_init_data){ 1783 .name = "gcc_qmip_camera_nrt_ahb_clk", 1784 .ops = &clk_branch2_ops, 1785 }, 1786 }, 1787 }; 1788 1789 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 1790 .halt_reg = 0x3600c, 1791 .halt_check = BRANCH_HALT_VOTED, 1792 .hwcg_reg = 0x3600c, 1793 .hwcg_bit = 1, 1794 .clkr = { 1795 .enable_reg = 0x3600c, 1796 .enable_mask = BIT(0), 1797 .hw.init = &(struct clk_init_data){ 1798 .name = "gcc_qmip_camera_rt_ahb_clk", 1799 .ops = &clk_branch2_ops, 1800 }, 1801 }, 1802 }; 1803 1804 static struct clk_branch gcc_qmip_disp_ahb_clk = { 1805 .halt_reg = 0x37008, 1806 .halt_check = BRANCH_HALT_VOTED, 1807 .hwcg_reg = 0x37008, 1808 .hwcg_bit = 1, 1809 .clkr = { 1810 .enable_reg = 0x37008, 1811 .enable_mask = BIT(0), 1812 .hw.init = &(struct clk_init_data){ 1813 .name = "gcc_qmip_disp_ahb_clk", 1814 .ops = &clk_branch2_ops, 1815 }, 1816 }, 1817 }; 1818 1819 static struct clk_branch gcc_qmip_gpu_ahb_clk = { 1820 .halt_reg = 0x81008, 1821 .halt_check = BRANCH_HALT_VOTED, 1822 .hwcg_reg = 0x81008, 1823 .hwcg_bit = 1, 1824 .clkr = { 1825 .enable_reg = 0x81008, 1826 .enable_mask = BIT(0), 1827 .hw.init = &(struct clk_init_data){ 1828 .name = "gcc_qmip_gpu_ahb_clk", 1829 .ops = &clk_branch2_ops, 1830 }, 1831 }, 1832 }; 1833 1834 static struct clk_branch gcc_qmip_pcie_ahb_clk = { 1835 .halt_reg = 0x7b018, 1836 .halt_check = BRANCH_HALT_VOTED, 1837 .hwcg_reg = 0x7b018, 1838 .hwcg_bit = 1, 1839 .clkr = { 1840 .enable_reg = 0x7b018, 1841 .enable_mask = BIT(0), 1842 .hw.init = &(struct clk_init_data){ 1843 .name = "gcc_qmip_pcie_ahb_clk", 1844 .ops = &clk_branch2_ops, 1845 }, 1846 }, 1847 }; 1848 1849 static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = { 1850 .halt_reg = 0x42014, 1851 .halt_check = BRANCH_HALT_VOTED, 1852 .hwcg_reg = 0x42014, 1853 .hwcg_bit = 1, 1854 .clkr = { 1855 .enable_reg = 0x42014, 1856 .enable_mask = BIT(0), 1857 .hw.init = &(struct clk_init_data){ 1858 .name = "gcc_qmip_video_cv_cpu_ahb_clk", 1859 .ops = &clk_branch2_ops, 1860 }, 1861 }, 1862 }; 1863 1864 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 1865 .halt_reg = 0x42008, 1866 .halt_check = BRANCH_HALT_VOTED, 1867 .hwcg_reg = 0x42008, 1868 .hwcg_bit = 1, 1869 .clkr = { 1870 .enable_reg = 0x42008, 1871 .enable_mask = BIT(0), 1872 .hw.init = &(struct clk_init_data){ 1873 .name = "gcc_qmip_video_cvp_ahb_clk", 1874 .ops = &clk_branch2_ops, 1875 }, 1876 }, 1877 }; 1878 1879 static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = { 1880 .halt_reg = 0x42010, 1881 .halt_check = BRANCH_HALT_VOTED, 1882 .hwcg_reg = 0x42010, 1883 .hwcg_bit = 1, 1884 .clkr = { 1885 .enable_reg = 0x42010, 1886 .enable_mask = BIT(0), 1887 .hw.init = &(struct clk_init_data){ 1888 .name = "gcc_qmip_video_v_cpu_ahb_clk", 1889 .ops = &clk_branch2_ops, 1890 }, 1891 }, 1892 }; 1893 1894 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 1895 .halt_reg = 0x4200c, 1896 .halt_check = BRANCH_HALT_VOTED, 1897 .hwcg_reg = 0x4200c, 1898 .hwcg_bit = 1, 1899 .clkr = { 1900 .enable_reg = 0x4200c, 1901 .enable_mask = BIT(0), 1902 .hw.init = &(struct clk_init_data){ 1903 .name = "gcc_qmip_video_vcodec_ahb_clk", 1904 .ops = &clk_branch2_ops, 1905 }, 1906 }, 1907 }; 1908 1909 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 1910 .halt_reg = 0x3300c, 1911 .halt_check = BRANCH_HALT_VOTED, 1912 .clkr = { 1913 .enable_reg = 0x62008, 1914 .enable_mask = BIT(9), 1915 .hw.init = &(struct clk_init_data){ 1916 .name = "gcc_qupv3_wrap0_core_2x_clk", 1917 .ops = &clk_branch2_ops, 1918 }, 1919 }, 1920 }; 1921 1922 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 1923 .halt_reg = 0x33000, 1924 .halt_check = BRANCH_HALT_VOTED, 1925 .clkr = { 1926 .enable_reg = 0x62008, 1927 .enable_mask = BIT(8), 1928 .hw.init = &(struct clk_init_data){ 1929 .name = "gcc_qupv3_wrap0_core_clk", 1930 .ops = &clk_branch2_ops, 1931 }, 1932 }, 1933 }; 1934 1935 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 1936 .halt_reg = 0x2700c, 1937 .halt_check = BRANCH_HALT_VOTED, 1938 .clkr = { 1939 .enable_reg = 0x62008, 1940 .enable_mask = BIT(10), 1941 .hw.init = &(struct clk_init_data){ 1942 .name = "gcc_qupv3_wrap0_s0_clk", 1943 .parent_data = &(const struct clk_parent_data){ 1944 .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 1945 }, 1946 .num_parents = 1, 1947 .flags = CLK_SET_RATE_PARENT, 1948 .ops = &clk_branch2_ops, 1949 }, 1950 }, 1951 }; 1952 1953 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 1954 .halt_reg = 0x27140, 1955 .halt_check = BRANCH_HALT_VOTED, 1956 .clkr = { 1957 .enable_reg = 0x62008, 1958 .enable_mask = BIT(11), 1959 .hw.init = &(struct clk_init_data){ 1960 .name = "gcc_qupv3_wrap0_s1_clk", 1961 .parent_data = &(const struct clk_parent_data){ 1962 .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 1963 }, 1964 .num_parents = 1, 1965 .flags = CLK_SET_RATE_PARENT, 1966 .ops = &clk_branch2_ops, 1967 }, 1968 }, 1969 }; 1970 1971 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 1972 .halt_reg = 0x27274, 1973 .halt_check = BRANCH_HALT_VOTED, 1974 .clkr = { 1975 .enable_reg = 0x62008, 1976 .enable_mask = BIT(12), 1977 .hw.init = &(struct clk_init_data){ 1978 .name = "gcc_qupv3_wrap0_s2_clk", 1979 .parent_data = &(const struct clk_parent_data){ 1980 .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 1981 }, 1982 .num_parents = 1, 1983 .flags = CLK_SET_RATE_PARENT, 1984 .ops = &clk_branch2_ops, 1985 }, 1986 }, 1987 }; 1988 1989 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 1990 .halt_reg = 0x273a8, 1991 .halt_check = BRANCH_HALT_VOTED, 1992 .clkr = { 1993 .enable_reg = 0x62008, 1994 .enable_mask = BIT(13), 1995 .hw.init = &(struct clk_init_data){ 1996 .name = "gcc_qupv3_wrap0_s3_clk", 1997 .parent_data = &(const struct clk_parent_data){ 1998 .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 1999 }, 2000 .num_parents = 1, 2001 .flags = CLK_SET_RATE_PARENT, 2002 .ops = &clk_branch2_ops, 2003 }, 2004 }, 2005 }; 2006 2007 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2008 .halt_reg = 0x274dc, 2009 .halt_check = BRANCH_HALT_VOTED, 2010 .clkr = { 2011 .enable_reg = 0x62008, 2012 .enable_mask = BIT(14), 2013 .hw.init = &(struct clk_init_data){ 2014 .name = "gcc_qupv3_wrap0_s4_clk", 2015 .parent_data = &(const struct clk_parent_data){ 2016 .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2017 }, 2018 .num_parents = 1, 2019 .flags = CLK_SET_RATE_PARENT, 2020 .ops = &clk_branch2_ops, 2021 }, 2022 }, 2023 }; 2024 2025 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2026 .halt_reg = 0x27610, 2027 .halt_check = BRANCH_HALT_VOTED, 2028 .clkr = { 2029 .enable_reg = 0x62008, 2030 .enable_mask = BIT(15), 2031 .hw.init = &(struct clk_init_data){ 2032 .name = "gcc_qupv3_wrap0_s5_clk", 2033 .parent_data = &(const struct clk_parent_data){ 2034 .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2035 }, 2036 .num_parents = 1, 2037 .flags = CLK_SET_RATE_PARENT, 2038 .ops = &clk_branch2_ops, 2039 }, 2040 }, 2041 }; 2042 2043 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 2044 .halt_reg = 0x27744, 2045 .halt_check = BRANCH_HALT_VOTED, 2046 .clkr = { 2047 .enable_reg = 0x62008, 2048 .enable_mask = BIT(16), 2049 .hw.init = &(struct clk_init_data){ 2050 .name = "gcc_qupv3_wrap0_s6_clk", 2051 .parent_data = &(const struct clk_parent_data){ 2052 .hw = &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 2053 }, 2054 .num_parents = 1, 2055 .flags = CLK_SET_RATE_PARENT, 2056 .ops = &clk_branch2_ops, 2057 }, 2058 }, 2059 }; 2060 2061 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 2062 .halt_reg = 0x27878, 2063 .halt_check = BRANCH_HALT_VOTED, 2064 .clkr = { 2065 .enable_reg = 0x62008, 2066 .enable_mask = BIT(17), 2067 .hw.init = &(struct clk_init_data){ 2068 .name = "gcc_qupv3_wrap0_s7_clk", 2069 .parent_data = &(const struct clk_parent_data){ 2070 .hw = &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 2071 }, 2072 .num_parents = 1, 2073 .flags = CLK_SET_RATE_PARENT, 2074 .ops = &clk_branch2_ops, 2075 }, 2076 }, 2077 }; 2078 2079 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2080 .halt_reg = 0x3314c, 2081 .halt_check = BRANCH_HALT_VOTED, 2082 .clkr = { 2083 .enable_reg = 0x62008, 2084 .enable_mask = BIT(18), 2085 .hw.init = &(struct clk_init_data){ 2086 .name = "gcc_qupv3_wrap1_core_2x_clk", 2087 .ops = &clk_branch2_ops, 2088 }, 2089 }, 2090 }; 2091 2092 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2093 .halt_reg = 0x33140, 2094 .halt_check = BRANCH_HALT_VOTED, 2095 .clkr = { 2096 .enable_reg = 0x62008, 2097 .enable_mask = BIT(19), 2098 .hw.init = &(struct clk_init_data){ 2099 .name = "gcc_qupv3_wrap1_core_clk", 2100 .ops = &clk_branch2_ops, 2101 }, 2102 }, 2103 }; 2104 2105 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2106 .halt_reg = 0x2800c, 2107 .halt_check = BRANCH_HALT_VOTED, 2108 .clkr = { 2109 .enable_reg = 0x62008, 2110 .enable_mask = BIT(22), 2111 .hw.init = &(struct clk_init_data){ 2112 .name = "gcc_qupv3_wrap1_s0_clk", 2113 .parent_data = &(const struct clk_parent_data){ 2114 .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2115 }, 2116 .num_parents = 1, 2117 .flags = CLK_SET_RATE_PARENT, 2118 .ops = &clk_branch2_ops, 2119 }, 2120 }, 2121 }; 2122 2123 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2124 .halt_reg = 0x28140, 2125 .halt_check = BRANCH_HALT_VOTED, 2126 .clkr = { 2127 .enable_reg = 0x62008, 2128 .enable_mask = BIT(23), 2129 .hw.init = &(struct clk_init_data){ 2130 .name = "gcc_qupv3_wrap1_s1_clk", 2131 .parent_data = &(const struct clk_parent_data){ 2132 .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2133 }, 2134 .num_parents = 1, 2135 .flags = CLK_SET_RATE_PARENT, 2136 .ops = &clk_branch2_ops, 2137 }, 2138 }, 2139 }; 2140 2141 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2142 .halt_reg = 0x28274, 2143 .halt_check = BRANCH_HALT_VOTED, 2144 .clkr = { 2145 .enable_reg = 0x62008, 2146 .enable_mask = BIT(24), 2147 .hw.init = &(struct clk_init_data){ 2148 .name = "gcc_qupv3_wrap1_s2_clk", 2149 .parent_data = &(const struct clk_parent_data){ 2150 .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2151 }, 2152 .num_parents = 1, 2153 .flags = CLK_SET_RATE_PARENT, 2154 .ops = &clk_branch2_ops, 2155 }, 2156 }, 2157 }; 2158 2159 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2160 .halt_reg = 0x283a8, 2161 .halt_check = BRANCH_HALT_VOTED, 2162 .clkr = { 2163 .enable_reg = 0x62008, 2164 .enable_mask = BIT(25), 2165 .hw.init = &(struct clk_init_data){ 2166 .name = "gcc_qupv3_wrap1_s3_clk", 2167 .parent_data = &(const struct clk_parent_data){ 2168 .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2169 }, 2170 .num_parents = 1, 2171 .flags = CLK_SET_RATE_PARENT, 2172 .ops = &clk_branch2_ops, 2173 }, 2174 }, 2175 }; 2176 2177 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2178 .halt_reg = 0x284dc, 2179 .halt_check = BRANCH_HALT_VOTED, 2180 .clkr = { 2181 .enable_reg = 0x62008, 2182 .enable_mask = BIT(26), 2183 .hw.init = &(struct clk_init_data){ 2184 .name = "gcc_qupv3_wrap1_s4_clk", 2185 .parent_data = &(const struct clk_parent_data){ 2186 .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2187 }, 2188 .num_parents = 1, 2189 .flags = CLK_SET_RATE_PARENT, 2190 .ops = &clk_branch2_ops, 2191 }, 2192 }, 2193 }; 2194 2195 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2196 .halt_reg = 0x28610, 2197 .halt_check = BRANCH_HALT_VOTED, 2198 .clkr = { 2199 .enable_reg = 0x62008, 2200 .enable_mask = BIT(27), 2201 .hw.init = &(struct clk_init_data){ 2202 .name = "gcc_qupv3_wrap1_s5_clk", 2203 .parent_data = &(const struct clk_parent_data){ 2204 .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2205 }, 2206 .num_parents = 1, 2207 .flags = CLK_SET_RATE_PARENT, 2208 .ops = &clk_branch2_ops, 2209 }, 2210 }, 2211 }; 2212 2213 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 2214 .halt_reg = 0x28744, 2215 .halt_check = BRANCH_HALT_VOTED, 2216 .clkr = { 2217 .enable_reg = 0x62008, 2218 .enable_mask = BIT(28), 2219 .hw.init = &(struct clk_init_data){ 2220 .name = "gcc_qupv3_wrap1_s6_clk", 2221 .parent_data = &(const struct clk_parent_data){ 2222 .hw = &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 2223 }, 2224 .num_parents = 1, 2225 .flags = CLK_SET_RATE_PARENT, 2226 .ops = &clk_branch2_ops, 2227 }, 2228 }, 2229 }; 2230 2231 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 2232 .halt_reg = 0x3328c, 2233 .halt_check = BRANCH_HALT_VOTED, 2234 .clkr = { 2235 .enable_reg = 0x62010, 2236 .enable_mask = BIT(3), 2237 .hw.init = &(struct clk_init_data){ 2238 .name = "gcc_qupv3_wrap2_core_2x_clk", 2239 .ops = &clk_branch2_ops, 2240 }, 2241 }, 2242 }; 2243 2244 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 2245 .halt_reg = 0x33280, 2246 .halt_check = BRANCH_HALT_VOTED, 2247 .clkr = { 2248 .enable_reg = 0x62010, 2249 .enable_mask = BIT(0), 2250 .hw.init = &(struct clk_init_data){ 2251 .name = "gcc_qupv3_wrap2_core_clk", 2252 .ops = &clk_branch2_ops, 2253 }, 2254 }, 2255 }; 2256 2257 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 2258 .halt_reg = 0x2e00c, 2259 .halt_check = BRANCH_HALT_VOTED, 2260 .clkr = { 2261 .enable_reg = 0x62010, 2262 .enable_mask = BIT(4), 2263 .hw.init = &(struct clk_init_data){ 2264 .name = "gcc_qupv3_wrap2_s0_clk", 2265 .parent_data = &(const struct clk_parent_data){ 2266 .hw = &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 2267 }, 2268 .num_parents = 1, 2269 .flags = CLK_SET_RATE_PARENT, 2270 .ops = &clk_branch2_ops, 2271 }, 2272 }, 2273 }; 2274 2275 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 2276 .halt_reg = 0x2e140, 2277 .halt_check = BRANCH_HALT_VOTED, 2278 .clkr = { 2279 .enable_reg = 0x62010, 2280 .enable_mask = BIT(5), 2281 .hw.init = &(struct clk_init_data){ 2282 .name = "gcc_qupv3_wrap2_s1_clk", 2283 .parent_data = &(const struct clk_parent_data){ 2284 .hw = &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 2285 }, 2286 .num_parents = 1, 2287 .flags = CLK_SET_RATE_PARENT, 2288 .ops = &clk_branch2_ops, 2289 }, 2290 }, 2291 }; 2292 2293 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 2294 .halt_reg = 0x2e274, 2295 .halt_check = BRANCH_HALT_VOTED, 2296 .clkr = { 2297 .enable_reg = 0x62010, 2298 .enable_mask = BIT(6), 2299 .hw.init = &(struct clk_init_data){ 2300 .name = "gcc_qupv3_wrap2_s2_clk", 2301 .parent_data = &(const struct clk_parent_data){ 2302 .hw = &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 2303 }, 2304 .num_parents = 1, 2305 .flags = CLK_SET_RATE_PARENT, 2306 .ops = &clk_branch2_ops, 2307 }, 2308 }, 2309 }; 2310 2311 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 2312 .halt_reg = 0x2e3a8, 2313 .halt_check = BRANCH_HALT_VOTED, 2314 .clkr = { 2315 .enable_reg = 0x62010, 2316 .enable_mask = BIT(7), 2317 .hw.init = &(struct clk_init_data){ 2318 .name = "gcc_qupv3_wrap2_s3_clk", 2319 .parent_data = &(const struct clk_parent_data){ 2320 .hw = &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 2321 }, 2322 .num_parents = 1, 2323 .flags = CLK_SET_RATE_PARENT, 2324 .ops = &clk_branch2_ops, 2325 }, 2326 }, 2327 }; 2328 2329 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 2330 .halt_reg = 0x2e4dc, 2331 .halt_check = BRANCH_HALT_VOTED, 2332 .clkr = { 2333 .enable_reg = 0x62010, 2334 .enable_mask = BIT(8), 2335 .hw.init = &(struct clk_init_data){ 2336 .name = "gcc_qupv3_wrap2_s4_clk", 2337 .parent_data = &(const struct clk_parent_data){ 2338 .hw = &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 2339 }, 2340 .num_parents = 1, 2341 .flags = CLK_SET_RATE_PARENT, 2342 .ops = &clk_branch2_ops, 2343 }, 2344 }, 2345 }; 2346 2347 static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 2348 .halt_reg = 0x2e610, 2349 .halt_check = BRANCH_HALT_VOTED, 2350 .clkr = { 2351 .enable_reg = 0x62010, 2352 .enable_mask = BIT(9), 2353 .hw.init = &(struct clk_init_data){ 2354 .name = "gcc_qupv3_wrap2_s5_clk", 2355 .parent_data = &(const struct clk_parent_data){ 2356 .hw = &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 2357 }, 2358 .num_parents = 1, 2359 .flags = CLK_SET_RATE_PARENT, 2360 .ops = &clk_branch2_ops, 2361 }, 2362 }, 2363 }; 2364 2365 static struct clk_branch gcc_qupv3_wrap2_s6_clk = { 2366 .halt_reg = 0x2e744, 2367 .halt_check = BRANCH_HALT_VOTED, 2368 .clkr = { 2369 .enable_reg = 0x62010, 2370 .enable_mask = BIT(10), 2371 .hw.init = &(struct clk_init_data){ 2372 .name = "gcc_qupv3_wrap2_s6_clk", 2373 .parent_data = &(const struct clk_parent_data){ 2374 .hw = &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, 2375 }, 2376 .num_parents = 1, 2377 .flags = CLK_SET_RATE_PARENT, 2378 .ops = &clk_branch2_ops, 2379 }, 2380 }, 2381 }; 2382 2383 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2384 .halt_reg = 0x27004, 2385 .halt_check = BRANCH_HALT_VOTED, 2386 .hwcg_reg = 0x27004, 2387 .hwcg_bit = 1, 2388 .clkr = { 2389 .enable_reg = 0x62008, 2390 .enable_mask = BIT(6), 2391 .hw.init = &(struct clk_init_data){ 2392 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2393 .ops = &clk_branch2_ops, 2394 }, 2395 }, 2396 }; 2397 2398 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2399 .halt_reg = 0x27008, 2400 .halt_check = BRANCH_HALT_VOTED, 2401 .hwcg_reg = 0x27008, 2402 .hwcg_bit = 1, 2403 .clkr = { 2404 .enable_reg = 0x62008, 2405 .enable_mask = BIT(7), 2406 .hw.init = &(struct clk_init_data){ 2407 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2408 .ops = &clk_branch2_ops, 2409 }, 2410 }, 2411 }; 2412 2413 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2414 .halt_reg = 0x28004, 2415 .halt_check = BRANCH_HALT_VOTED, 2416 .hwcg_reg = 0x28004, 2417 .hwcg_bit = 1, 2418 .clkr = { 2419 .enable_reg = 0x62008, 2420 .enable_mask = BIT(20), 2421 .hw.init = &(struct clk_init_data){ 2422 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2423 .ops = &clk_branch2_ops, 2424 }, 2425 }, 2426 }; 2427 2428 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2429 .halt_reg = 0x28008, 2430 .halt_check = BRANCH_HALT_VOTED, 2431 .hwcg_reg = 0x28008, 2432 .hwcg_bit = 1, 2433 .clkr = { 2434 .enable_reg = 0x62008, 2435 .enable_mask = BIT(21), 2436 .hw.init = &(struct clk_init_data){ 2437 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2438 .ops = &clk_branch2_ops, 2439 }, 2440 }, 2441 }; 2442 2443 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 2444 .halt_reg = 0x2e004, 2445 .halt_check = BRANCH_HALT_VOTED, 2446 .hwcg_reg = 0x2e004, 2447 .hwcg_bit = 1, 2448 .clkr = { 2449 .enable_reg = 0x62010, 2450 .enable_mask = BIT(2), 2451 .hw.init = &(struct clk_init_data){ 2452 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 2453 .ops = &clk_branch2_ops, 2454 }, 2455 }, 2456 }; 2457 2458 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 2459 .halt_reg = 0x2e008, 2460 .halt_check = BRANCH_HALT_VOTED, 2461 .hwcg_reg = 0x2e008, 2462 .hwcg_bit = 1, 2463 .clkr = { 2464 .enable_reg = 0x62010, 2465 .enable_mask = BIT(1), 2466 .hw.init = &(struct clk_init_data){ 2467 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 2468 .ops = &clk_branch2_ops, 2469 }, 2470 }, 2471 }; 2472 2473 static struct clk_branch gcc_sdcc2_ahb_clk = { 2474 .halt_reg = 0x2400c, 2475 .halt_check = BRANCH_HALT, 2476 .clkr = { 2477 .enable_reg = 0x2400c, 2478 .enable_mask = BIT(0), 2479 .hw.init = &(struct clk_init_data){ 2480 .name = "gcc_sdcc2_ahb_clk", 2481 .ops = &clk_branch2_ops, 2482 }, 2483 }, 2484 }; 2485 2486 static struct clk_branch gcc_sdcc2_apps_clk = { 2487 .halt_reg = 0x24004, 2488 .halt_check = BRANCH_HALT, 2489 .clkr = { 2490 .enable_reg = 0x24004, 2491 .enable_mask = BIT(0), 2492 .hw.init = &(struct clk_init_data){ 2493 .name = "gcc_sdcc2_apps_clk", 2494 .parent_data = &(const struct clk_parent_data){ 2495 .hw = &gcc_sdcc2_apps_clk_src.clkr.hw, 2496 }, 2497 .num_parents = 1, 2498 .flags = CLK_SET_RATE_PARENT, 2499 .ops = &clk_branch2_ops, 2500 }, 2501 }, 2502 }; 2503 2504 static struct clk_branch gcc_sdcc2_at_clk = { 2505 .halt_reg = 0x24010, 2506 .halt_check = BRANCH_HALT_VOTED, 2507 .hwcg_reg = 0x24010, 2508 .hwcg_bit = 1, 2509 .clkr = { 2510 .enable_reg = 0x24010, 2511 .enable_mask = BIT(0), 2512 .hw.init = &(struct clk_init_data){ 2513 .name = "gcc_sdcc2_at_clk", 2514 .ops = &clk_branch2_ops, 2515 }, 2516 }, 2517 }; 2518 2519 static struct clk_branch gcc_sdcc4_ahb_clk = { 2520 .halt_reg = 0x2600c, 2521 .halt_check = BRANCH_HALT, 2522 .clkr = { 2523 .enable_reg = 0x2600c, 2524 .enable_mask = BIT(0), 2525 .hw.init = &(struct clk_init_data){ 2526 .name = "gcc_sdcc4_ahb_clk", 2527 .ops = &clk_branch2_ops, 2528 }, 2529 }, 2530 }; 2531 2532 static struct clk_branch gcc_sdcc4_apps_clk = { 2533 .halt_reg = 0x26004, 2534 .halt_check = BRANCH_HALT, 2535 .clkr = { 2536 .enable_reg = 0x26004, 2537 .enable_mask = BIT(0), 2538 .hw.init = &(struct clk_init_data){ 2539 .name = "gcc_sdcc4_apps_clk", 2540 .parent_data = &(const struct clk_parent_data){ 2541 .hw = &gcc_sdcc4_apps_clk_src.clkr.hw, 2542 }, 2543 .num_parents = 1, 2544 .flags = CLK_SET_RATE_PARENT, 2545 .ops = &clk_branch2_ops, 2546 }, 2547 }, 2548 }; 2549 2550 static struct clk_branch gcc_sdcc4_at_clk = { 2551 .halt_reg = 0x26010, 2552 .halt_check = BRANCH_HALT_VOTED, 2553 .hwcg_reg = 0x26010, 2554 .hwcg_bit = 1, 2555 .clkr = { 2556 .enable_reg = 0x26010, 2557 .enable_mask = BIT(0), 2558 .hw.init = &(struct clk_init_data){ 2559 .name = "gcc_sdcc4_at_clk", 2560 .ops = &clk_branch2_ops, 2561 }, 2562 }, 2563 }; 2564 2565 static struct clk_branch gcc_ufs_0_clkref_en = { 2566 .halt_reg = 0x9c000, 2567 .halt_check = BRANCH_HALT, 2568 .clkr = { 2569 .enable_reg = 0x9c000, 2570 .enable_mask = BIT(0), 2571 .hw.init = &(struct clk_init_data){ 2572 .name = "gcc_ufs_0_clkref_en", 2573 .ops = &clk_branch2_ops, 2574 }, 2575 }, 2576 }; 2577 2578 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2579 .halt_reg = 0x87020, 2580 .halt_check = BRANCH_HALT_VOTED, 2581 .hwcg_reg = 0x87020, 2582 .hwcg_bit = 1, 2583 .clkr = { 2584 .enable_reg = 0x87020, 2585 .enable_mask = BIT(0), 2586 .hw.init = &(struct clk_init_data){ 2587 .name = "gcc_ufs_phy_ahb_clk", 2588 .ops = &clk_branch2_ops, 2589 }, 2590 }, 2591 }; 2592 2593 static struct clk_branch gcc_ufs_phy_axi_clk = { 2594 .halt_reg = 0x87018, 2595 .halt_check = BRANCH_HALT_VOTED, 2596 .hwcg_reg = 0x87018, 2597 .hwcg_bit = 1, 2598 .clkr = { 2599 .enable_reg = 0x87018, 2600 .enable_mask = BIT(0), 2601 .hw.init = &(struct clk_init_data){ 2602 .name = "gcc_ufs_phy_axi_clk", 2603 .parent_data = &(const struct clk_parent_data){ 2604 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 2605 }, 2606 .num_parents = 1, 2607 .flags = CLK_SET_RATE_PARENT, 2608 .ops = &clk_branch2_ops, 2609 }, 2610 }, 2611 }; 2612 2613 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { 2614 .halt_reg = 0x87018, 2615 .halt_check = BRANCH_HALT_VOTED, 2616 .hwcg_reg = 0x87018, 2617 .hwcg_bit = 1, 2618 .clkr = { 2619 .enable_reg = 0x87018, 2620 .enable_mask = BIT(1), 2621 .hw.init = &(struct clk_init_data){ 2622 .name = "gcc_ufs_phy_axi_hw_ctl_clk", 2623 .parent_data = &(const struct clk_parent_data){ 2624 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 2625 }, 2626 .num_parents = 1, 2627 .flags = CLK_SET_RATE_PARENT, 2628 .ops = &clk_branch2_ops, 2629 }, 2630 }, 2631 }; 2632 2633 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2634 .halt_reg = 0x8706c, 2635 .halt_check = BRANCH_HALT_VOTED, 2636 .hwcg_reg = 0x8706c, 2637 .hwcg_bit = 1, 2638 .clkr = { 2639 .enable_reg = 0x8706c, 2640 .enable_mask = BIT(0), 2641 .hw.init = &(struct clk_init_data){ 2642 .name = "gcc_ufs_phy_ice_core_clk", 2643 .parent_data = &(const struct clk_parent_data){ 2644 .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2645 }, 2646 .num_parents = 1, 2647 .flags = CLK_SET_RATE_PARENT, 2648 .ops = &clk_branch2_ops, 2649 }, 2650 }, 2651 }; 2652 2653 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { 2654 .halt_reg = 0x8706c, 2655 .halt_check = BRANCH_HALT_VOTED, 2656 .hwcg_reg = 0x8706c, 2657 .hwcg_bit = 1, 2658 .clkr = { 2659 .enable_reg = 0x8706c, 2660 .enable_mask = BIT(1), 2661 .hw.init = &(struct clk_init_data){ 2662 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", 2663 .parent_data = &(const struct clk_parent_data){ 2664 .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2665 }, 2666 .num_parents = 1, 2667 .flags = CLK_SET_RATE_PARENT, 2668 .ops = &clk_branch2_ops, 2669 }, 2670 }, 2671 }; 2672 2673 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2674 .halt_reg = 0x870a4, 2675 .halt_check = BRANCH_HALT_VOTED, 2676 .hwcg_reg = 0x870a4, 2677 .hwcg_bit = 1, 2678 .clkr = { 2679 .enable_reg = 0x870a4, 2680 .enable_mask = BIT(0), 2681 .hw.init = &(struct clk_init_data){ 2682 .name = "gcc_ufs_phy_phy_aux_clk", 2683 .parent_data = &(const struct clk_parent_data){ 2684 .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2685 }, 2686 .num_parents = 1, 2687 .flags = CLK_SET_RATE_PARENT, 2688 .ops = &clk_branch2_ops, 2689 }, 2690 }, 2691 }; 2692 2693 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { 2694 .halt_reg = 0x870a4, 2695 .halt_check = BRANCH_HALT_VOTED, 2696 .hwcg_reg = 0x870a4, 2697 .hwcg_bit = 1, 2698 .clkr = { 2699 .enable_reg = 0x870a4, 2700 .enable_mask = BIT(1), 2701 .hw.init = &(struct clk_init_data){ 2702 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", 2703 .parent_data = &(const struct clk_parent_data){ 2704 .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2705 }, 2706 .num_parents = 1, 2707 .flags = CLK_SET_RATE_PARENT, 2708 .ops = &clk_branch2_ops, 2709 }, 2710 }, 2711 }; 2712 2713 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2714 .halt_reg = 0x87028, 2715 .halt_check = BRANCH_HALT_DELAY, 2716 .clkr = { 2717 .enable_reg = 0x87028, 2718 .enable_mask = BIT(0), 2719 .hw.init = &(struct clk_init_data){ 2720 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2721 .parent_data = &(const struct clk_parent_data){ 2722 .hw = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 2723 }, 2724 .num_parents = 1, 2725 .flags = CLK_SET_RATE_PARENT, 2726 .ops = &clk_branch2_ops, 2727 }, 2728 }, 2729 }; 2730 2731 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2732 .halt_reg = 0x870c0, 2733 .halt_check = BRANCH_HALT_DELAY, 2734 .clkr = { 2735 .enable_reg = 0x870c0, 2736 .enable_mask = BIT(0), 2737 .hw.init = &(struct clk_init_data){ 2738 .name = "gcc_ufs_phy_rx_symbol_1_clk", 2739 .parent_data = &(const struct clk_parent_data){ 2740 .hw = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 2741 }, 2742 .num_parents = 1, 2743 .flags = CLK_SET_RATE_PARENT, 2744 .ops = &clk_branch2_ops, 2745 }, 2746 }, 2747 }; 2748 2749 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2750 .halt_reg = 0x87024, 2751 .halt_check = BRANCH_HALT_DELAY, 2752 .clkr = { 2753 .enable_reg = 0x87024, 2754 .enable_mask = BIT(0), 2755 .hw.init = &(struct clk_init_data){ 2756 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2757 .parent_data = &(const struct clk_parent_data){ 2758 .hw = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 2759 }, 2760 .num_parents = 1, 2761 .flags = CLK_SET_RATE_PARENT, 2762 .ops = &clk_branch2_ops, 2763 }, 2764 }, 2765 }; 2766 2767 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2768 .halt_reg = 0x87064, 2769 .halt_check = BRANCH_HALT_VOTED, 2770 .hwcg_reg = 0x87064, 2771 .hwcg_bit = 1, 2772 .clkr = { 2773 .enable_reg = 0x87064, 2774 .enable_mask = BIT(0), 2775 .hw.init = &(struct clk_init_data){ 2776 .name = "gcc_ufs_phy_unipro_core_clk", 2777 .parent_data = &(const struct clk_parent_data){ 2778 .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2779 }, 2780 .num_parents = 1, 2781 .flags = CLK_SET_RATE_PARENT, 2782 .ops = &clk_branch2_ops, 2783 }, 2784 }, 2785 }; 2786 2787 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { 2788 .halt_reg = 0x87064, 2789 .halt_check = BRANCH_HALT_VOTED, 2790 .hwcg_reg = 0x87064, 2791 .hwcg_bit = 1, 2792 .clkr = { 2793 .enable_reg = 0x87064, 2794 .enable_mask = BIT(1), 2795 .hw.init = &(struct clk_init_data){ 2796 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", 2797 .parent_data = &(const struct clk_parent_data){ 2798 .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2799 }, 2800 .num_parents = 1, 2801 .flags = CLK_SET_RATE_PARENT, 2802 .ops = &clk_branch2_ops, 2803 }, 2804 }, 2805 }; 2806 2807 static struct clk_branch gcc_usb30_prim_master_clk = { 2808 .halt_reg = 0x49018, 2809 .halt_check = BRANCH_HALT, 2810 .clkr = { 2811 .enable_reg = 0x49018, 2812 .enable_mask = BIT(0), 2813 .hw.init = &(struct clk_init_data){ 2814 .name = "gcc_usb30_prim_master_clk", 2815 .parent_data = &(const struct clk_parent_data){ 2816 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 2817 }, 2818 .num_parents = 1, 2819 .flags = CLK_SET_RATE_PARENT, 2820 .ops = &clk_branch2_ops, 2821 }, 2822 }, 2823 }; 2824 2825 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2826 .halt_reg = 0x49024, 2827 .halt_check = BRANCH_HALT, 2828 .clkr = { 2829 .enable_reg = 0x49024, 2830 .enable_mask = BIT(0), 2831 .hw.init = &(struct clk_init_data){ 2832 .name = "gcc_usb30_prim_mock_utmi_clk", 2833 .parent_data = &(const struct clk_parent_data){ 2834 .hw = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2835 }, 2836 .num_parents = 1, 2837 .flags = CLK_SET_RATE_PARENT, 2838 .ops = &clk_branch2_ops, 2839 }, 2840 }, 2841 }; 2842 2843 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2844 .halt_reg = 0x49020, 2845 .halt_check = BRANCH_HALT, 2846 .clkr = { 2847 .enable_reg = 0x49020, 2848 .enable_mask = BIT(0), 2849 .hw.init = &(struct clk_init_data){ 2850 .name = "gcc_usb30_prim_sleep_clk", 2851 .ops = &clk_branch2_ops, 2852 }, 2853 }, 2854 }; 2855 2856 static struct clk_branch gcc_usb3_0_clkref_en = { 2857 .halt_reg = 0x9c010, 2858 .halt_check = BRANCH_HALT, 2859 .clkr = { 2860 .enable_reg = 0x9c010, 2861 .enable_mask = BIT(0), 2862 .hw.init = &(struct clk_init_data){ 2863 .name = "gcc_usb3_0_clkref_en", 2864 .ops = &clk_branch2_ops, 2865 }, 2866 }, 2867 }; 2868 2869 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2870 .halt_reg = 0x4905c, 2871 .halt_check = BRANCH_HALT, 2872 .clkr = { 2873 .enable_reg = 0x4905c, 2874 .enable_mask = BIT(0), 2875 .hw.init = &(struct clk_init_data){ 2876 .name = "gcc_usb3_prim_phy_aux_clk", 2877 .parent_data = &(const struct clk_parent_data){ 2878 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2879 }, 2880 .num_parents = 1, 2881 .flags = CLK_SET_RATE_PARENT, 2882 .ops = &clk_branch2_ops, 2883 }, 2884 }, 2885 }; 2886 2887 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2888 .halt_reg = 0x49060, 2889 .halt_check = BRANCH_HALT, 2890 .clkr = { 2891 .enable_reg = 0x49060, 2892 .enable_mask = BIT(0), 2893 .hw.init = &(struct clk_init_data){ 2894 .name = "gcc_usb3_prim_phy_com_aux_clk", 2895 .parent_data = &(const struct clk_parent_data){ 2896 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2897 }, 2898 .num_parents = 1, 2899 .flags = CLK_SET_RATE_PARENT, 2900 .ops = &clk_branch2_ops, 2901 }, 2902 }, 2903 }; 2904 2905 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2906 .halt_reg = 0x49064, 2907 .halt_check = BRANCH_HALT_DELAY, 2908 .hwcg_reg = 0x49064, 2909 .hwcg_bit = 1, 2910 .clkr = { 2911 .enable_reg = 0x49064, 2912 .enable_mask = BIT(0), 2913 .hw.init = &(struct clk_init_data){ 2914 .name = "gcc_usb3_prim_phy_pipe_clk", 2915 .parent_data = &(const struct clk_parent_data){ 2916 .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 2917 }, 2918 .num_parents = 1, 2919 .flags = CLK_SET_RATE_PARENT, 2920 .ops = &clk_branch2_ops, 2921 }, 2922 }, 2923 }; 2924 2925 static struct clk_branch gcc_video_axi0_clk = { 2926 .halt_reg = 0x42018, 2927 .halt_check = BRANCH_HALT_SKIP, 2928 .hwcg_reg = 0x42018, 2929 .hwcg_bit = 1, 2930 .clkr = { 2931 .enable_reg = 0x42018, 2932 .enable_mask = BIT(0), 2933 .hw.init = &(struct clk_init_data){ 2934 .name = "gcc_video_axi0_clk", 2935 .ops = &clk_branch2_ops, 2936 }, 2937 }, 2938 }; 2939 2940 static struct clk_branch gcc_video_axi1_clk = { 2941 .halt_reg = 0x42020, 2942 .halt_check = BRANCH_HALT_SKIP, 2943 .hwcg_reg = 0x42020, 2944 .hwcg_bit = 1, 2945 .clkr = { 2946 .enable_reg = 0x42020, 2947 .enable_mask = BIT(0), 2948 .hw.init = &(struct clk_init_data){ 2949 .name = "gcc_video_axi1_clk", 2950 .ops = &clk_branch2_ops, 2951 }, 2952 }, 2953 }; 2954 2955 static struct gdsc pcie_0_gdsc = { 2956 .gdscr = 0x7b004, 2957 .pd = { 2958 .name = "pcie_0_gdsc", 2959 }, 2960 .pwrsts = PWRSTS_OFF_ON, 2961 }; 2962 2963 static struct gdsc pcie_1_gdsc = { 2964 .gdscr = 0x9d004, 2965 .pd = { 2966 .name = "pcie_1_gdsc", 2967 }, 2968 .pwrsts = PWRSTS_OFF_ON, 2969 }; 2970 2971 static struct gdsc ufs_phy_gdsc = { 2972 .gdscr = 0x87004, 2973 .pd = { 2974 .name = "ufs_phy_gdsc", 2975 }, 2976 .pwrsts = PWRSTS_OFF_ON, 2977 }; 2978 2979 static struct gdsc usb30_prim_gdsc = { 2980 .gdscr = 0x49004, 2981 .pd = { 2982 .name = "usb30_prim_gdsc", 2983 }, 2984 .pwrsts = PWRSTS_OFF_ON, 2985 }; 2986 2987 static struct clk_regmap *gcc_sm8450_clocks[] = { 2988 [GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr, 2989 [GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr, 2990 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 2991 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, 2992 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 2993 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2994 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 2995 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 2996 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr, 2997 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2998 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 2999 [GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr, 3000 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3001 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, 3002 [GCC_EUSB3_0_CLKREF_EN] = &gcc_eusb3_0_clkref_en.clkr, 3003 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3004 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3005 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3006 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3007 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3008 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3009 [GCC_GPLL0] = &gcc_gpll0.clkr, 3010 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 3011 [GCC_GPLL4] = &gcc_gpll4.clkr, 3012 [GCC_GPLL9] = &gcc_gpll9.clkr, 3013 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3014 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3015 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3016 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3017 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3018 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 3019 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3020 [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr, 3021 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3022 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 3023 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 3024 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3025 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 3026 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3027 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 3028 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 3029 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 3030 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 3031 [GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr, 3032 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 3033 [GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr, 3034 [GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr, 3035 [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr, 3036 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 3037 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 3038 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr, 3039 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 3040 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 3041 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3042 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3043 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3044 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3045 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3046 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3047 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3048 [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr, 3049 [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr, 3050 [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr, 3051 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 3052 [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr, 3053 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3054 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 3055 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 3056 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3057 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3058 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3059 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3060 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3061 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3062 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3063 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3064 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3065 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3066 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3067 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3068 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 3069 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 3070 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 3071 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 3072 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3073 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3074 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3075 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3076 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3077 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3078 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3079 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3080 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3081 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3082 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3083 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3084 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3085 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3086 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 3087 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 3088 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 3089 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 3090 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 3091 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 3092 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 3093 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 3094 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 3095 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 3096 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 3097 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 3098 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 3099 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 3100 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 3101 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 3102 [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr, 3103 [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr, 3104 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3105 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3106 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3107 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3108 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 3109 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 3110 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3111 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3112 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3113 [GCC_SDCC2_AT_CLK] = &gcc_sdcc2_at_clk.clkr, 3114 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3115 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3116 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 3117 [GCC_SDCC4_AT_CLK] = &gcc_sdcc4_at_clk.clkr, 3118 [GCC_UFS_0_CLKREF_EN] = &gcc_ufs_0_clkref_en.clkr, 3119 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3120 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3121 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3122 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, 3123 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3124 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3125 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, 3126 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3127 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3128 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, 3129 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3130 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 3131 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3132 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 3133 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3134 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 3135 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3136 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 3137 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, 3138 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3139 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3140 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3141 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3142 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3143 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3144 [GCC_USB3_0_CLKREF_EN] = &gcc_usb3_0_clkref_en.clkr, 3145 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3146 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3147 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3148 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3149 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 3150 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3151 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 3152 }; 3153 3154 static const struct qcom_reset_map gcc_sm8450_resets[] = { 3155 [GCC_CAMERA_BCR] = { 0x36000 }, 3156 [GCC_DISPLAY_BCR] = { 0x37000 }, 3157 [GCC_GPU_BCR] = { 0x81000 }, 3158 [GCC_PCIE_0_BCR] = { 0x7b000 }, 3159 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x7c014 }, 3160 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x7c020 }, 3161 [GCC_PCIE_0_PHY_BCR] = { 0x7c01c }, 3162 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x7c028 }, 3163 [GCC_PCIE_1_BCR] = { 0x9d000 }, 3164 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x9e014 }, 3165 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x9e020 }, 3166 [GCC_PCIE_1_PHY_BCR] = { 0x9e01c }, 3167 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 }, 3168 [GCC_PCIE_PHY_BCR] = { 0x7f000 }, 3169 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c }, 3170 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 }, 3171 [GCC_PDM_BCR] = { 0x43000 }, 3172 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 }, 3173 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 }, 3174 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x2e000 }, 3175 [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 }, 3176 [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 }, 3177 [GCC_SDCC2_BCR] = { 0x24000 }, 3178 [GCC_SDCC4_BCR] = { 0x26000 }, 3179 [GCC_UFS_PHY_BCR] = { 0x87000 }, 3180 [GCC_USB30_PRIM_BCR] = { 0x49000 }, 3181 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 }, 3182 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 }, 3183 [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 }, 3184 [GCC_USB3_PHY_SEC_BCR] = { 0x6000c }, 3185 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 }, 3186 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 }, 3187 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 }, 3188 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x42018, 2 }, 3189 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x42020, 2 }, 3190 [GCC_VIDEO_BCR] = { 0x42000 }, 3191 }; 3192 3193 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3194 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3195 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3196 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3197 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3198 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3199 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3200 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 3201 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 3202 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3203 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3204 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 3205 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3206 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3207 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3208 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 3209 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 3210 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 3211 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 3212 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 3213 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 3214 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 3215 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src), 3216 }; 3217 3218 static struct gdsc *gcc_sm8450_gdscs[] = { 3219 [PCIE_0_GDSC] = &pcie_0_gdsc, 3220 [PCIE_1_GDSC] = &pcie_1_gdsc, 3221 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3222 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3223 }; 3224 3225 static const struct regmap_config gcc_sm8450_regmap_config = { 3226 .reg_bits = 32, 3227 .reg_stride = 4, 3228 .val_bits = 32, 3229 .max_register = 0x1f1030, 3230 .fast_io = true, 3231 }; 3232 3233 static const struct qcom_cc_desc gcc_sm8450_desc = { 3234 .config = &gcc_sm8450_regmap_config, 3235 .clks = gcc_sm8450_clocks, 3236 .num_clks = ARRAY_SIZE(gcc_sm8450_clocks), 3237 .resets = gcc_sm8450_resets, 3238 .num_resets = ARRAY_SIZE(gcc_sm8450_resets), 3239 .gdscs = gcc_sm8450_gdscs, 3240 .num_gdscs = ARRAY_SIZE(gcc_sm8450_gdscs), 3241 }; 3242 3243 static const struct of_device_id gcc_sm8450_match_table[] = { 3244 { .compatible = "qcom,gcc-sm8450" }, 3245 { } 3246 }; 3247 MODULE_DEVICE_TABLE(of, gcc_sm8450_match_table); 3248 3249 static int gcc_sm8450_probe(struct platform_device *pdev) 3250 { 3251 struct regmap *regmap; 3252 int ret; 3253 3254 regmap = qcom_cc_map(pdev, &gcc_sm8450_desc); 3255 if (IS_ERR(regmap)) 3256 return PTR_ERR(regmap); 3257 3258 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3259 ARRAY_SIZE(gcc_dfs_clocks)); 3260 if (ret) 3261 return ret; 3262 3263 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ 3264 regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14)); 3265 3266 /* 3267 * Keep the critical clock always-On 3268 * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk, 3269 * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, 3270 * gcc_video_xo_clk 3271 */ 3272 regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0)); 3273 regmap_update_bits(regmap, 0x36020, BIT(0), BIT(0)); 3274 regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0)); 3275 regmap_update_bits(regmap, 0x3701c, BIT(0), BIT(0)); 3276 regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0)); 3277 regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0)); 3278 regmap_update_bits(regmap, 0x42028, BIT(0), BIT(0)); 3279 3280 return qcom_cc_really_probe(pdev, &gcc_sm8450_desc, regmap); 3281 } 3282 3283 static struct platform_driver gcc_sm8450_driver = { 3284 .probe = gcc_sm8450_probe, 3285 .driver = { 3286 .name = "gcc-sm8450", 3287 .of_match_table = gcc_sm8450_match_table, 3288 }, 3289 }; 3290 3291 static int __init gcc_sm8450_init(void) 3292 { 3293 return platform_driver_register(&gcc_sm8450_driver); 3294 } 3295 subsys_initcall(gcc_sm8450_init); 3296 3297 static void __exit gcc_sm8450_exit(void) 3298 { 3299 platform_driver_unregister(&gcc_sm8450_driver); 3300 } 3301 module_exit(gcc_sm8450_exit); 3302 3303 MODULE_DESCRIPTION("QTI GCC SM8450 Driver"); 3304 MODULE_LICENSE("GPL v2"); 3305