1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, Linaro Limited 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/module.h> 9 #include <linux/of_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,gcc-sm8450.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "clk-regmap-divider.h" 19 #include "clk-regmap-mux.h" 20 #include "clk-regmap-phy-mux.h" 21 #include "gdsc.h" 22 #include "reset.h" 23 24 enum { 25 P_BI_TCXO, 26 P_GCC_GPLL0_OUT_EVEN, 27 P_GCC_GPLL0_OUT_MAIN, 28 P_GCC_GPLL4_OUT_MAIN, 29 P_GCC_GPLL9_OUT_MAIN, 30 P_PCIE_1_PHY_AUX_CLK, 31 P_SLEEP_CLK, 32 P_UFS_PHY_RX_SYMBOL_0_CLK, 33 P_UFS_PHY_RX_SYMBOL_1_CLK, 34 P_UFS_PHY_TX_SYMBOL_0_CLK, 35 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 36 }; 37 38 static struct clk_alpha_pll gcc_gpll0 = { 39 .offset = 0x0, 40 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 41 .clkr = { 42 .enable_reg = 0x62018, 43 .enable_mask = BIT(0), 44 .hw.init = &(struct clk_init_data){ 45 .name = "gcc_gpll0", 46 .parent_data = &(const struct clk_parent_data){ 47 .fw_name = "bi_tcxo", 48 }, 49 .num_parents = 1, 50 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 51 }, 52 }, 53 }; 54 55 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 56 { 0x1, 2 }, 57 { } 58 }; 59 60 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 61 .offset = 0x0, 62 .post_div_shift = 10, 63 .post_div_table = post_div_table_gcc_gpll0_out_even, 64 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 65 .width = 4, 66 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 67 .clkr.hw.init = &(struct clk_init_data){ 68 .name = "gcc_gpll0_out_even", 69 .parent_data = &(const struct clk_parent_data){ 70 .hw = &gcc_gpll0.clkr.hw, 71 }, 72 .num_parents = 1, 73 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 74 }, 75 }; 76 77 static struct clk_alpha_pll gcc_gpll4 = { 78 .offset = 0x4000, 79 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 80 .clkr = { 81 .enable_reg = 0x62018, 82 .enable_mask = BIT(4), 83 .hw.init = &(struct clk_init_data){ 84 .name = "gcc_gpll4", 85 .parent_data = &(const struct clk_parent_data){ 86 .fw_name = "bi_tcxo", 87 }, 88 .num_parents = 1, 89 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 90 }, 91 }, 92 }; 93 94 static struct clk_alpha_pll gcc_gpll9 = { 95 .offset = 0x9000, 96 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 97 .clkr = { 98 .enable_reg = 0x62018, 99 .enable_mask = BIT(9), 100 .hw.init = &(struct clk_init_data){ 101 .name = "gcc_gpll9", 102 .parent_data = &(const struct clk_parent_data){ 103 .fw_name = "bi_tcxo", 104 }, 105 .num_parents = 1, 106 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 107 }, 108 }, 109 }; 110 111 static const struct parent_map gcc_parent_map_0[] = { 112 { P_BI_TCXO, 0 }, 113 { P_GCC_GPLL0_OUT_MAIN, 1 }, 114 { P_GCC_GPLL0_OUT_EVEN, 6 }, 115 }; 116 117 static const struct clk_parent_data gcc_parent_data_0[] = { 118 { .fw_name = "bi_tcxo" }, 119 { .hw = &gcc_gpll0.clkr.hw }, 120 { .hw = &gcc_gpll0_out_even.clkr.hw }, 121 }; 122 123 static const struct parent_map gcc_parent_map_1[] = { 124 { P_BI_TCXO, 0 }, 125 { P_GCC_GPLL0_OUT_MAIN, 1 }, 126 { P_SLEEP_CLK, 5 }, 127 { P_GCC_GPLL0_OUT_EVEN, 6 }, 128 }; 129 130 static const struct clk_parent_data gcc_parent_data_1[] = { 131 { .fw_name = "bi_tcxo" }, 132 { .hw = &gcc_gpll0.clkr.hw }, 133 { .fw_name = "sleep_clk" }, 134 { .hw = &gcc_gpll0_out_even.clkr.hw }, 135 }; 136 137 static const struct parent_map gcc_parent_map_2[] = { 138 { P_BI_TCXO, 0 }, 139 { P_SLEEP_CLK, 5 }, 140 }; 141 142 static const struct clk_parent_data gcc_parent_data_2[] = { 143 { .fw_name = "bi_tcxo" }, 144 { .fw_name = "sleep_clk" }, 145 }; 146 147 static const struct parent_map gcc_parent_map_3[] = { 148 { P_BI_TCXO, 0 }, 149 }; 150 151 static const struct clk_parent_data gcc_parent_data_3[] = { 152 { .fw_name = "bi_tcxo" }, 153 }; 154 155 static const struct parent_map gcc_parent_map_5[] = { 156 { P_PCIE_1_PHY_AUX_CLK, 0 }, 157 { P_BI_TCXO, 2 }, 158 }; 159 160 static const struct clk_parent_data gcc_parent_data_5[] = { 161 { .fw_name = "pcie_1_phy_aux_clk" }, 162 { .fw_name = "bi_tcxo" }, 163 }; 164 165 static const struct parent_map gcc_parent_map_7[] = { 166 { P_BI_TCXO, 0 }, 167 { P_GCC_GPLL0_OUT_MAIN, 1 }, 168 { P_GCC_GPLL9_OUT_MAIN, 2 }, 169 { P_GCC_GPLL4_OUT_MAIN, 5 }, 170 { P_GCC_GPLL0_OUT_EVEN, 6 }, 171 }; 172 173 static const struct clk_parent_data gcc_parent_data_7[] = { 174 { .fw_name = "bi_tcxo" }, 175 { .hw = &gcc_gpll0.clkr.hw }, 176 { .hw = &gcc_gpll9.clkr.hw }, 177 { .hw = &gcc_gpll4.clkr.hw }, 178 { .hw = &gcc_gpll0_out_even.clkr.hw }, 179 }; 180 181 static const struct parent_map gcc_parent_map_8[] = { 182 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, 183 { P_BI_TCXO, 2 }, 184 }; 185 186 static const struct clk_parent_data gcc_parent_data_8[] = { 187 { .fw_name = "ufs_phy_rx_symbol_0_clk" }, 188 { .fw_name = "bi_tcxo" }, 189 }; 190 191 static const struct parent_map gcc_parent_map_9[] = { 192 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, 193 { P_BI_TCXO, 2 }, 194 }; 195 196 static const struct clk_parent_data gcc_parent_data_9[] = { 197 { .fw_name = "ufs_phy_rx_symbol_1_clk" }, 198 { .fw_name = "bi_tcxo" }, 199 }; 200 201 static const struct parent_map gcc_parent_map_10[] = { 202 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, 203 { P_BI_TCXO, 2 }, 204 }; 205 206 static const struct clk_parent_data gcc_parent_data_10[] = { 207 { .fw_name = "ufs_phy_tx_symbol_0_clk" }, 208 { .fw_name = "bi_tcxo" }, 209 }; 210 211 static const struct parent_map gcc_parent_map_11[] = { 212 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 213 { P_BI_TCXO, 2 }, 214 }; 215 216 static const struct clk_parent_data gcc_parent_data_11[] = { 217 { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" }, 218 { .fw_name = "bi_tcxo" }, 219 }; 220 221 static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { 222 .reg = 0x7b060, 223 .clkr = { 224 .hw.init = &(struct clk_init_data){ 225 .name = "gcc_pcie_0_pipe_clk_src", 226 .parent_data = &(const struct clk_parent_data){ 227 .fw_name = "pcie_0_pipe_clk", 228 }, 229 .num_parents = 1, 230 .ops = &clk_regmap_phy_mux_ops, 231 }, 232 }, 233 }; 234 235 static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = { 236 .reg = 0x9d080, 237 .shift = 0, 238 .width = 2, 239 .parent_map = gcc_parent_map_5, 240 .clkr = { 241 .hw.init = &(struct clk_init_data){ 242 .name = "gcc_pcie_1_phy_aux_clk_src", 243 .parent_data = gcc_parent_data_5, 244 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 245 .ops = &clk_regmap_mux_closest_ops, 246 }, 247 }, 248 }; 249 250 static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = { 251 .reg = 0x9d064, 252 .clkr = { 253 .hw.init = &(struct clk_init_data){ 254 .name = "gcc_pcie_1_pipe_clk_src", 255 .parent_data = &(const struct clk_parent_data){ 256 .fw_name = "pcie_1_pipe_clk", 257 }, 258 .num_parents = 1, 259 .ops = &clk_regmap_phy_mux_ops, 260 }, 261 }, 262 }; 263 264 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 265 .reg = 0x87060, 266 .shift = 0, 267 .width = 2, 268 .parent_map = gcc_parent_map_8, 269 .clkr = { 270 .hw.init = &(struct clk_init_data){ 271 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 272 .parent_data = gcc_parent_data_8, 273 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 274 .ops = &clk_regmap_mux_closest_ops, 275 }, 276 }, 277 }; 278 279 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 280 .reg = 0x870d0, 281 .shift = 0, 282 .width = 2, 283 .parent_map = gcc_parent_map_9, 284 .clkr = { 285 .hw.init = &(struct clk_init_data){ 286 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 287 .parent_data = gcc_parent_data_9, 288 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 289 .ops = &clk_regmap_mux_closest_ops, 290 }, 291 }, 292 }; 293 294 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 295 .reg = 0x87050, 296 .shift = 0, 297 .width = 2, 298 .parent_map = gcc_parent_map_10, 299 .clkr = { 300 .hw.init = &(struct clk_init_data){ 301 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 302 .parent_data = gcc_parent_data_10, 303 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 304 .ops = &clk_regmap_mux_closest_ops, 305 }, 306 }, 307 }; 308 309 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 310 .reg = 0x49068, 311 .shift = 0, 312 .width = 2, 313 .parent_map = gcc_parent_map_11, 314 .clkr = { 315 .hw.init = &(struct clk_init_data){ 316 .name = "gcc_usb3_prim_phy_pipe_clk_src", 317 .parent_data = gcc_parent_data_11, 318 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 319 .ops = &clk_regmap_mux_closest_ops, 320 }, 321 }, 322 }; 323 324 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 325 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 326 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 327 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 328 { } 329 }; 330 331 static struct clk_rcg2 gcc_gp1_clk_src = { 332 .cmd_rcgr = 0x74004, 333 .mnd_width = 8, 334 .hid_width = 5, 335 .parent_map = gcc_parent_map_1, 336 .freq_tbl = ftbl_gcc_gp1_clk_src, 337 .clkr.hw.init = &(struct clk_init_data){ 338 .name = "gcc_gp1_clk_src", 339 .parent_data = gcc_parent_data_1, 340 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 341 .flags = CLK_SET_RATE_PARENT, 342 .ops = &clk_rcg2_ops, 343 }, 344 }; 345 346 static struct clk_rcg2 gcc_gp2_clk_src = { 347 .cmd_rcgr = 0x75004, 348 .mnd_width = 8, 349 .hid_width = 5, 350 .parent_map = gcc_parent_map_1, 351 .freq_tbl = ftbl_gcc_gp1_clk_src, 352 .clkr.hw.init = &(struct clk_init_data){ 353 .name = "gcc_gp2_clk_src", 354 .parent_data = gcc_parent_data_1, 355 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 356 .flags = CLK_SET_RATE_PARENT, 357 .ops = &clk_rcg2_ops, 358 }, 359 }; 360 361 static struct clk_rcg2 gcc_gp3_clk_src = { 362 .cmd_rcgr = 0x76004, 363 .mnd_width = 8, 364 .hid_width = 5, 365 .parent_map = gcc_parent_map_1, 366 .freq_tbl = ftbl_gcc_gp1_clk_src, 367 .clkr.hw.init = &(struct clk_init_data){ 368 .name = "gcc_gp3_clk_src", 369 .parent_data = gcc_parent_data_1, 370 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 371 .flags = CLK_SET_RATE_PARENT, 372 .ops = &clk_rcg2_ops, 373 }, 374 }; 375 376 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 377 F(19200000, P_BI_TCXO, 1, 0, 0), 378 { } 379 }; 380 381 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 382 .cmd_rcgr = 0x7b064, 383 .mnd_width = 16, 384 .hid_width = 5, 385 .parent_map = gcc_parent_map_2, 386 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 387 .clkr.hw.init = &(struct clk_init_data){ 388 .name = "gcc_pcie_0_aux_clk_src", 389 .parent_data = gcc_parent_data_2, 390 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 391 .flags = CLK_SET_RATE_PARENT, 392 .ops = &clk_rcg2_ops, 393 }, 394 }; 395 396 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 397 F(19200000, P_BI_TCXO, 1, 0, 0), 398 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 399 { } 400 }; 401 402 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 403 .cmd_rcgr = 0x7b048, 404 .mnd_width = 0, 405 .hid_width = 5, 406 .parent_map = gcc_parent_map_0, 407 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 408 .clkr.hw.init = &(struct clk_init_data){ 409 .name = "gcc_pcie_0_phy_rchng_clk_src", 410 .parent_data = gcc_parent_data_0, 411 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 412 .flags = CLK_SET_RATE_PARENT, 413 .ops = &clk_rcg2_ops, 414 }, 415 }; 416 417 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 418 .cmd_rcgr = 0x9d068, 419 .mnd_width = 16, 420 .hid_width = 5, 421 .parent_map = gcc_parent_map_2, 422 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 423 .clkr.hw.init = &(struct clk_init_data){ 424 .name = "gcc_pcie_1_aux_clk_src", 425 .parent_data = gcc_parent_data_2, 426 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 427 .flags = CLK_SET_RATE_PARENT, 428 .ops = &clk_rcg2_ops, 429 }, 430 }; 431 432 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 433 .cmd_rcgr = 0x9d04c, 434 .mnd_width = 0, 435 .hid_width = 5, 436 .parent_map = gcc_parent_map_0, 437 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 438 .clkr.hw.init = &(struct clk_init_data){ 439 .name = "gcc_pcie_1_phy_rchng_clk_src", 440 .parent_data = gcc_parent_data_0, 441 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 442 .flags = CLK_SET_RATE_PARENT, 443 .ops = &clk_rcg2_ops, 444 }, 445 }; 446 447 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 448 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 449 { } 450 }; 451 452 static struct clk_rcg2 gcc_pdm2_clk_src = { 453 .cmd_rcgr = 0x43010, 454 .mnd_width = 0, 455 .hid_width = 5, 456 .parent_map = gcc_parent_map_0, 457 .freq_tbl = ftbl_gcc_pdm2_clk_src, 458 .clkr.hw.init = &(struct clk_init_data){ 459 .name = "gcc_pdm2_clk_src", 460 .parent_data = gcc_parent_data_0, 461 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 462 .flags = CLK_SET_RATE_PARENT, 463 .ops = &clk_rcg2_ops, 464 }, 465 }; 466 467 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 468 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 469 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 470 F(19200000, P_BI_TCXO, 1, 0, 0), 471 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 472 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 473 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 474 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 475 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 476 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 477 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 478 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 479 { } 480 }; 481 482 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 483 .name = "gcc_qupv3_wrap0_s0_clk_src", 484 .parent_data = gcc_parent_data_0, 485 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 486 .flags = CLK_SET_RATE_PARENT, 487 .ops = &clk_rcg2_ops, 488 }; 489 490 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 491 .cmd_rcgr = 0x27014, 492 .mnd_width = 16, 493 .hid_width = 5, 494 .parent_map = gcc_parent_map_0, 495 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 496 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 497 }; 498 499 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 500 .name = "gcc_qupv3_wrap0_s1_clk_src", 501 .parent_data = gcc_parent_data_0, 502 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 503 .flags = CLK_SET_RATE_PARENT, 504 .ops = &clk_rcg2_ops, 505 }; 506 507 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 508 .cmd_rcgr = 0x27148, 509 .mnd_width = 16, 510 .hid_width = 5, 511 .parent_map = gcc_parent_map_0, 512 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 513 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 514 }; 515 516 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 517 .name = "gcc_qupv3_wrap0_s2_clk_src", 518 .parent_data = gcc_parent_data_0, 519 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 520 .flags = CLK_SET_RATE_PARENT, 521 .ops = &clk_rcg2_ops, 522 }; 523 524 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 525 .cmd_rcgr = 0x2727c, 526 .mnd_width = 16, 527 .hid_width = 5, 528 .parent_map = gcc_parent_map_0, 529 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 530 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 531 }; 532 533 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 534 .name = "gcc_qupv3_wrap0_s3_clk_src", 535 .parent_data = gcc_parent_data_0, 536 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 537 .flags = CLK_SET_RATE_PARENT, 538 .ops = &clk_rcg2_ops, 539 }; 540 541 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 542 .cmd_rcgr = 0x273b0, 543 .mnd_width = 16, 544 .hid_width = 5, 545 .parent_map = gcc_parent_map_0, 546 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 547 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 548 }; 549 550 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 551 .name = "gcc_qupv3_wrap0_s4_clk_src", 552 .parent_data = gcc_parent_data_0, 553 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 554 .flags = CLK_SET_RATE_PARENT, 555 .ops = &clk_rcg2_ops, 556 }; 557 558 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 559 .cmd_rcgr = 0x274e4, 560 .mnd_width = 16, 561 .hid_width = 5, 562 .parent_map = gcc_parent_map_0, 563 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 564 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 565 }; 566 567 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] = { 568 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 569 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 570 F(19200000, P_BI_TCXO, 1, 0, 0), 571 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 572 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 573 F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0), 574 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 575 F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0), 576 { } 577 }; 578 579 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 580 .name = "gcc_qupv3_wrap0_s5_clk_src", 581 .parent_data = gcc_parent_data_0, 582 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 583 .flags = CLK_SET_RATE_PARENT, 584 .ops = &clk_rcg2_ops, 585 }; 586 587 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 588 .cmd_rcgr = 0x27618, 589 .mnd_width = 16, 590 .hid_width = 5, 591 .parent_map = gcc_parent_map_0, 592 .freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src, 593 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 594 }; 595 596 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 597 .name = "gcc_qupv3_wrap0_s6_clk_src", 598 .parent_data = gcc_parent_data_0, 599 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 600 .flags = CLK_SET_RATE_PARENT, 601 .ops = &clk_rcg2_ops, 602 }; 603 604 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 605 .cmd_rcgr = 0x2774c, 606 .mnd_width = 16, 607 .hid_width = 5, 608 .parent_map = gcc_parent_map_0, 609 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 610 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 611 }; 612 613 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 614 .name = "gcc_qupv3_wrap0_s7_clk_src", 615 .parent_data = gcc_parent_data_0, 616 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 617 .flags = CLK_SET_RATE_PARENT, 618 .ops = &clk_rcg2_ops, 619 }; 620 621 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 622 .cmd_rcgr = 0x27880, 623 .mnd_width = 16, 624 .hid_width = 5, 625 .parent_map = gcc_parent_map_0, 626 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 627 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 628 }; 629 630 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = { 631 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 632 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 633 F(19200000, P_BI_TCXO, 1, 0, 0), 634 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 635 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 636 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 637 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 638 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 639 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 640 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 641 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 642 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 643 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 644 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 645 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 646 { } 647 }; 648 649 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 650 .name = "gcc_qupv3_wrap1_s0_clk_src", 651 .parent_data = gcc_parent_data_0, 652 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 653 .flags = CLK_SET_RATE_PARENT, 654 .ops = &clk_rcg2_ops, 655 }; 656 657 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 658 .cmd_rcgr = 0x28014, 659 .mnd_width = 16, 660 .hid_width = 5, 661 .parent_map = gcc_parent_map_0, 662 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 663 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 664 }; 665 666 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 667 .name = "gcc_qupv3_wrap1_s1_clk_src", 668 .parent_data = gcc_parent_data_0, 669 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 670 .flags = CLK_SET_RATE_PARENT, 671 .ops = &clk_rcg2_ops, 672 }; 673 674 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 675 .cmd_rcgr = 0x28148, 676 .mnd_width = 16, 677 .hid_width = 5, 678 .parent_map = gcc_parent_map_0, 679 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 680 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 681 }; 682 683 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 684 .name = "gcc_qupv3_wrap1_s2_clk_src", 685 .parent_data = gcc_parent_data_0, 686 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 687 .flags = CLK_SET_RATE_PARENT, 688 .ops = &clk_rcg2_ops, 689 }; 690 691 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 692 .cmd_rcgr = 0x2827c, 693 .mnd_width = 16, 694 .hid_width = 5, 695 .parent_map = gcc_parent_map_0, 696 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 697 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 698 }; 699 700 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 701 .name = "gcc_qupv3_wrap1_s3_clk_src", 702 .parent_data = gcc_parent_data_0, 703 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 704 .flags = CLK_SET_RATE_PARENT, 705 .ops = &clk_rcg2_ops, 706 }; 707 708 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 709 .cmd_rcgr = 0x283b0, 710 .mnd_width = 16, 711 .hid_width = 5, 712 .parent_map = gcc_parent_map_0, 713 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 714 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 715 }; 716 717 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 718 .name = "gcc_qupv3_wrap1_s4_clk_src", 719 .parent_data = gcc_parent_data_0, 720 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 721 .flags = CLK_SET_RATE_PARENT, 722 .ops = &clk_rcg2_ops, 723 }; 724 725 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 726 .cmd_rcgr = 0x284e4, 727 .mnd_width = 16, 728 .hid_width = 5, 729 .parent_map = gcc_parent_map_0, 730 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 731 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 732 }; 733 734 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 735 .name = "gcc_qupv3_wrap1_s5_clk_src", 736 .parent_data = gcc_parent_data_0, 737 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 738 .flags = CLK_SET_RATE_PARENT, 739 .ops = &clk_rcg2_ops, 740 }; 741 742 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 743 .cmd_rcgr = 0x28618, 744 .mnd_width = 16, 745 .hid_width = 5, 746 .parent_map = gcc_parent_map_0, 747 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 748 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 749 }; 750 751 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 752 .name = "gcc_qupv3_wrap1_s6_clk_src", 753 .parent_data = gcc_parent_data_0, 754 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 755 .flags = CLK_SET_RATE_PARENT, 756 .ops = &clk_rcg2_ops, 757 }; 758 759 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 760 .cmd_rcgr = 0x2874c, 761 .mnd_width = 16, 762 .hid_width = 5, 763 .parent_map = gcc_parent_map_0, 764 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 765 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 766 }; 767 768 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 769 .name = "gcc_qupv3_wrap2_s0_clk_src", 770 .parent_data = gcc_parent_data_0, 771 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 772 .flags = CLK_SET_RATE_PARENT, 773 .ops = &clk_rcg2_ops, 774 }; 775 776 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 777 .cmd_rcgr = 0x2e014, 778 .mnd_width = 16, 779 .hid_width = 5, 780 .parent_map = gcc_parent_map_0, 781 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 782 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 783 }; 784 785 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 786 .name = "gcc_qupv3_wrap2_s1_clk_src", 787 .parent_data = gcc_parent_data_0, 788 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 789 .flags = CLK_SET_RATE_PARENT, 790 .ops = &clk_rcg2_ops, 791 }; 792 793 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 794 .cmd_rcgr = 0x2e148, 795 .mnd_width = 16, 796 .hid_width = 5, 797 .parent_map = gcc_parent_map_0, 798 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 799 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 800 }; 801 802 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 803 .name = "gcc_qupv3_wrap2_s2_clk_src", 804 .parent_data = gcc_parent_data_0, 805 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 806 .flags = CLK_SET_RATE_PARENT, 807 .ops = &clk_rcg2_ops, 808 }; 809 810 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 811 .cmd_rcgr = 0x2e27c, 812 .mnd_width = 16, 813 .hid_width = 5, 814 .parent_map = gcc_parent_map_0, 815 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 816 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 817 }; 818 819 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 820 .name = "gcc_qupv3_wrap2_s3_clk_src", 821 .parent_data = gcc_parent_data_0, 822 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 823 .flags = CLK_SET_RATE_PARENT, 824 .ops = &clk_rcg2_ops, 825 }; 826 827 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 828 .cmd_rcgr = 0x2e3b0, 829 .mnd_width = 16, 830 .hid_width = 5, 831 .parent_map = gcc_parent_map_0, 832 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 833 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 834 }; 835 836 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 837 .name = "gcc_qupv3_wrap2_s4_clk_src", 838 .parent_data = gcc_parent_data_0, 839 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 840 .flags = CLK_SET_RATE_PARENT, 841 .ops = &clk_rcg2_ops, 842 }; 843 844 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 845 .cmd_rcgr = 0x2e4e4, 846 .mnd_width = 16, 847 .hid_width = 5, 848 .parent_map = gcc_parent_map_0, 849 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 850 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 851 }; 852 853 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 854 .name = "gcc_qupv3_wrap2_s5_clk_src", 855 .parent_data = gcc_parent_data_0, 856 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 857 .flags = CLK_SET_RATE_PARENT, 858 .ops = &clk_rcg2_ops, 859 }; 860 861 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 862 .cmd_rcgr = 0x2e618, 863 .mnd_width = 16, 864 .hid_width = 5, 865 .parent_map = gcc_parent_map_0, 866 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 867 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 868 }; 869 870 static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { 871 .name = "gcc_qupv3_wrap2_s6_clk_src", 872 .parent_data = gcc_parent_data_0, 873 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 874 .flags = CLK_SET_RATE_PARENT, 875 .ops = &clk_rcg2_ops, 876 }; 877 878 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { 879 .cmd_rcgr = 0x2e74c, 880 .mnd_width = 16, 881 .hid_width = 5, 882 .parent_map = gcc_parent_map_0, 883 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 884 .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init, 885 }; 886 887 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 888 F(400000, P_BI_TCXO, 12, 1, 4), 889 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 890 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 891 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 892 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 893 { } 894 }; 895 896 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 897 .cmd_rcgr = 0x24014, 898 .mnd_width = 8, 899 .hid_width = 5, 900 .parent_map = gcc_parent_map_7, 901 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 902 .clkr.hw.init = &(struct clk_init_data){ 903 .name = "gcc_sdcc2_apps_clk_src", 904 .parent_data = gcc_parent_data_7, 905 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 906 .flags = CLK_SET_RATE_PARENT, 907 .ops = &clk_rcg2_ops, 908 }, 909 }; 910 911 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 912 F(400000, P_BI_TCXO, 12, 1, 4), 913 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 914 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 915 { } 916 }; 917 918 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 919 .cmd_rcgr = 0x26014, 920 .mnd_width = 8, 921 .hid_width = 5, 922 .parent_map = gcc_parent_map_0, 923 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 924 .clkr.hw.init = &(struct clk_init_data){ 925 .name = "gcc_sdcc4_apps_clk_src", 926 .parent_data = gcc_parent_data_0, 927 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 928 .flags = CLK_SET_RATE_PARENT, 929 .ops = &clk_rcg2_ops, 930 }, 931 }; 932 933 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 934 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 935 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 936 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 937 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 938 { } 939 }; 940 941 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 942 .cmd_rcgr = 0x8702c, 943 .mnd_width = 8, 944 .hid_width = 5, 945 .parent_map = gcc_parent_map_0, 946 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 947 .clkr.hw.init = &(struct clk_init_data){ 948 .name = "gcc_ufs_phy_axi_clk_src", 949 .parent_data = gcc_parent_data_0, 950 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 951 .flags = CLK_SET_RATE_PARENT, 952 .ops = &clk_rcg2_ops, 953 }, 954 }; 955 956 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 957 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 958 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 959 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 960 { } 961 }; 962 963 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 964 .cmd_rcgr = 0x87074, 965 .mnd_width = 0, 966 .hid_width = 5, 967 .parent_map = gcc_parent_map_0, 968 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 969 .clkr.hw.init = &(struct clk_init_data){ 970 .name = "gcc_ufs_phy_ice_core_clk_src", 971 .parent_data = gcc_parent_data_0, 972 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 973 .flags = CLK_SET_RATE_PARENT, 974 .ops = &clk_rcg2_ops, 975 }, 976 }; 977 978 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 979 F(9600000, P_BI_TCXO, 2, 0, 0), 980 F(19200000, P_BI_TCXO, 1, 0, 0), 981 { } 982 }; 983 984 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 985 .cmd_rcgr = 0x870a8, 986 .mnd_width = 0, 987 .hid_width = 5, 988 .parent_map = gcc_parent_map_3, 989 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 990 .clkr.hw.init = &(struct clk_init_data){ 991 .name = "gcc_ufs_phy_phy_aux_clk_src", 992 .parent_data = gcc_parent_data_3, 993 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 994 .flags = CLK_SET_RATE_PARENT, 995 .ops = &clk_rcg2_ops, 996 }, 997 }; 998 999 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1000 .cmd_rcgr = 0x8708c, 1001 .mnd_width = 0, 1002 .hid_width = 5, 1003 .parent_map = gcc_parent_map_0, 1004 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1005 .clkr.hw.init = &(struct clk_init_data){ 1006 .name = "gcc_ufs_phy_unipro_core_clk_src", 1007 .parent_data = gcc_parent_data_0, 1008 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1009 .flags = CLK_SET_RATE_PARENT, 1010 .ops = &clk_rcg2_ops, 1011 }, 1012 }; 1013 1014 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1015 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 1016 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1017 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1018 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1019 { } 1020 }; 1021 1022 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1023 .cmd_rcgr = 0x49028, 1024 .mnd_width = 8, 1025 .hid_width = 5, 1026 .parent_map = gcc_parent_map_0, 1027 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1028 .clkr.hw.init = &(struct clk_init_data){ 1029 .name = "gcc_usb30_prim_master_clk_src", 1030 .parent_data = gcc_parent_data_0, 1031 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1032 .flags = CLK_SET_RATE_PARENT, 1033 .ops = &clk_rcg2_ops, 1034 }, 1035 }; 1036 1037 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1038 .cmd_rcgr = 0x49040, 1039 .mnd_width = 0, 1040 .hid_width = 5, 1041 .parent_map = gcc_parent_map_0, 1042 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1043 .clkr.hw.init = &(struct clk_init_data){ 1044 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1045 .parent_data = gcc_parent_data_0, 1046 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1047 .flags = CLK_SET_RATE_PARENT, 1048 .ops = &clk_rcg2_ops, 1049 }, 1050 }; 1051 1052 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1053 .cmd_rcgr = 0x4906c, 1054 .mnd_width = 0, 1055 .hid_width = 5, 1056 .parent_map = gcc_parent_map_2, 1057 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1058 .clkr.hw.init = &(struct clk_init_data){ 1059 .name = "gcc_usb3_prim_phy_aux_clk_src", 1060 .parent_data = gcc_parent_data_2, 1061 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1062 .flags = CLK_SET_RATE_PARENT, 1063 .ops = &clk_rcg2_ops, 1064 }, 1065 }; 1066 1067 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1068 .reg = 0x49058, 1069 .shift = 0, 1070 .width = 4, 1071 .clkr.hw.init = &(struct clk_init_data) { 1072 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1073 .parent_data = &(const struct clk_parent_data){ 1074 .hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1075 }, 1076 .num_parents = 1, 1077 .flags = CLK_SET_RATE_PARENT, 1078 .ops = &clk_regmap_div_ro_ops, 1079 }, 1080 }; 1081 1082 static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = { 1083 .halt_reg = 0x7b08c, 1084 .halt_check = BRANCH_HALT_SKIP, 1085 .hwcg_reg = 0x7b08c, 1086 .hwcg_bit = 1, 1087 .clkr = { 1088 .enable_reg = 0x62000, 1089 .enable_mask = BIT(12), 1090 .hw.init = &(struct clk_init_data){ 1091 .name = "gcc_aggre_noc_pcie_0_axi_clk", 1092 .ops = &clk_branch2_ops, 1093 }, 1094 }, 1095 }; 1096 1097 static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = { 1098 .halt_reg = 0x9d098, 1099 .halt_check = BRANCH_HALT_SKIP, 1100 .hwcg_reg = 0x9d098, 1101 .hwcg_bit = 1, 1102 .clkr = { 1103 .enable_reg = 0x62000, 1104 .enable_mask = BIT(11), 1105 .hw.init = &(struct clk_init_data){ 1106 .name = "gcc_aggre_noc_pcie_1_axi_clk", 1107 .ops = &clk_branch2_ops, 1108 }, 1109 }, 1110 }; 1111 1112 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1113 .halt_reg = 0x870d4, 1114 .halt_check = BRANCH_HALT_VOTED, 1115 .hwcg_reg = 0x870d4, 1116 .hwcg_bit = 1, 1117 .clkr = { 1118 .enable_reg = 0x870d4, 1119 .enable_mask = BIT(0), 1120 .hw.init = &(struct clk_init_data){ 1121 .name = "gcc_aggre_ufs_phy_axi_clk", 1122 .parent_data = &(const struct clk_parent_data){ 1123 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 1124 }, 1125 .num_parents = 1, 1126 .flags = CLK_SET_RATE_PARENT, 1127 .ops = &clk_branch2_ops, 1128 }, 1129 }, 1130 }; 1131 1132 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { 1133 .halt_reg = 0x870d4, 1134 .halt_check = BRANCH_HALT_VOTED, 1135 .hwcg_reg = 0x870d4, 1136 .hwcg_bit = 1, 1137 .clkr = { 1138 .enable_reg = 0x870d4, 1139 .enable_mask = BIT(1), 1140 .hw.init = &(struct clk_init_data){ 1141 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", 1142 .parent_data = &(const struct clk_parent_data){ 1143 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 1144 }, 1145 .num_parents = 1, 1146 .flags = CLK_SET_RATE_PARENT, 1147 .ops = &clk_branch2_ops, 1148 }, 1149 }, 1150 }; 1151 1152 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1153 .halt_reg = 0x49088, 1154 .halt_check = BRANCH_HALT_VOTED, 1155 .hwcg_reg = 0x49088, 1156 .hwcg_bit = 1, 1157 .clkr = { 1158 .enable_reg = 0x49088, 1159 .enable_mask = BIT(0), 1160 .hw.init = &(struct clk_init_data){ 1161 .name = "gcc_aggre_usb3_prim_axi_clk", 1162 .parent_data = &(const struct clk_parent_data){ 1163 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 1164 }, 1165 .num_parents = 1, 1166 .flags = CLK_SET_RATE_PARENT, 1167 .ops = &clk_branch2_ops, 1168 }, 1169 }, 1170 }; 1171 1172 static struct clk_branch gcc_boot_rom_ahb_clk = { 1173 .halt_reg = 0x48004, 1174 .halt_check = BRANCH_HALT_VOTED, 1175 .hwcg_reg = 0x48004, 1176 .hwcg_bit = 1, 1177 .clkr = { 1178 .enable_reg = 0x62000, 1179 .enable_mask = BIT(10), 1180 .hw.init = &(struct clk_init_data){ 1181 .name = "gcc_boot_rom_ahb_clk", 1182 .ops = &clk_branch2_ops, 1183 }, 1184 }, 1185 }; 1186 1187 static struct clk_branch gcc_camera_hf_axi_clk = { 1188 .halt_reg = 0x36010, 1189 .halt_check = BRANCH_HALT_SKIP, 1190 .hwcg_reg = 0x36010, 1191 .hwcg_bit = 1, 1192 .clkr = { 1193 .enable_reg = 0x36010, 1194 .enable_mask = BIT(0), 1195 .hw.init = &(struct clk_init_data){ 1196 .name = "gcc_camera_hf_axi_clk", 1197 .ops = &clk_branch2_ops, 1198 }, 1199 }, 1200 }; 1201 1202 static struct clk_branch gcc_camera_sf_axi_clk = { 1203 .halt_reg = 0x36018, 1204 .halt_check = BRANCH_HALT_SKIP, 1205 .hwcg_reg = 0x36018, 1206 .hwcg_bit = 1, 1207 .clkr = { 1208 .enable_reg = 0x36018, 1209 .enable_mask = BIT(0), 1210 .hw.init = &(struct clk_init_data){ 1211 .name = "gcc_camera_sf_axi_clk", 1212 .ops = &clk_branch2_ops, 1213 }, 1214 }, 1215 }; 1216 1217 static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = { 1218 .halt_reg = 0x20030, 1219 .halt_check = BRANCH_HALT_VOTED, 1220 .hwcg_reg = 0x20030, 1221 .hwcg_bit = 1, 1222 .clkr = { 1223 .enable_reg = 0x62000, 1224 .enable_mask = BIT(20), 1225 .hw.init = &(struct clk_init_data){ 1226 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk", 1227 .ops = &clk_branch2_ops, 1228 }, 1229 }, 1230 }; 1231 1232 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1233 .halt_reg = 0x49084, 1234 .halt_check = BRANCH_HALT_VOTED, 1235 .hwcg_reg = 0x49084, 1236 .hwcg_bit = 1, 1237 .clkr = { 1238 .enable_reg = 0x49084, 1239 .enable_mask = BIT(0), 1240 .hw.init = &(struct clk_init_data){ 1241 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1242 .parent_data = &(const struct clk_parent_data){ 1243 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 1244 }, 1245 .num_parents = 1, 1246 .flags = CLK_SET_RATE_PARENT, 1247 .ops = &clk_branch2_ops, 1248 }, 1249 }, 1250 }; 1251 1252 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1253 .halt_reg = 0x81154, 1254 .halt_check = BRANCH_HALT_SKIP, 1255 .hwcg_reg = 0x81154, 1256 .hwcg_bit = 1, 1257 .clkr = { 1258 .enable_reg = 0x81154, 1259 .enable_mask = BIT(0), 1260 .hw.init = &(struct clk_init_data){ 1261 .name = "gcc_ddrss_gpu_axi_clk", 1262 .ops = &clk_branch2_aon_ops, 1263 }, 1264 }, 1265 }; 1266 1267 static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = { 1268 .halt_reg = 0x9d094, 1269 .halt_check = BRANCH_HALT_SKIP, 1270 .hwcg_reg = 0x9d094, 1271 .hwcg_bit = 1, 1272 .clkr = { 1273 .enable_reg = 0x62000, 1274 .enable_mask = BIT(19), 1275 .hw.init = &(struct clk_init_data){ 1276 .name = "gcc_ddrss_pcie_sf_tbu_clk", 1277 .ops = &clk_branch2_ops, 1278 }, 1279 }, 1280 }; 1281 1282 static struct clk_branch gcc_disp_hf_axi_clk = { 1283 .halt_reg = 0x3700c, 1284 .halt_check = BRANCH_HALT_SKIP, 1285 .hwcg_reg = 0x3700c, 1286 .hwcg_bit = 1, 1287 .clkr = { 1288 .enable_reg = 0x3700c, 1289 .enable_mask = BIT(0), 1290 .hw.init = &(struct clk_init_data){ 1291 .name = "gcc_disp_hf_axi_clk", 1292 .ops = &clk_branch2_ops, 1293 }, 1294 }, 1295 }; 1296 1297 static struct clk_branch gcc_disp_sf_axi_clk = { 1298 .halt_reg = 0x37014, 1299 .halt_check = BRANCH_HALT_SKIP, 1300 .hwcg_reg = 0x37014, 1301 .hwcg_bit = 1, 1302 .clkr = { 1303 .enable_reg = 0x37014, 1304 .enable_mask = BIT(0), 1305 .hw.init = &(struct clk_init_data){ 1306 .name = "gcc_disp_sf_axi_clk", 1307 .ops = &clk_branch2_ops, 1308 }, 1309 }, 1310 }; 1311 1312 static struct clk_branch gcc_eusb3_0_clkref_en = { 1313 .halt_reg = 0x9c00c, 1314 .halt_check = BRANCH_HALT, 1315 .clkr = { 1316 .enable_reg = 0x9c00c, 1317 .enable_mask = BIT(0), 1318 .hw.init = &(struct clk_init_data){ 1319 .name = "gcc_eusb3_0_clkref_en", 1320 .ops = &clk_branch2_ops, 1321 }, 1322 }, 1323 }; 1324 1325 static struct clk_branch gcc_gp1_clk = { 1326 .halt_reg = 0x74000, 1327 .halt_check = BRANCH_HALT, 1328 .clkr = { 1329 .enable_reg = 0x74000, 1330 .enable_mask = BIT(0), 1331 .hw.init = &(struct clk_init_data){ 1332 .name = "gcc_gp1_clk", 1333 .parent_data = &(const struct clk_parent_data){ 1334 .hw = &gcc_gp1_clk_src.clkr.hw, 1335 }, 1336 .num_parents = 1, 1337 .flags = CLK_SET_RATE_PARENT, 1338 .ops = &clk_branch2_ops, 1339 }, 1340 }, 1341 }; 1342 1343 static struct clk_branch gcc_gp2_clk = { 1344 .halt_reg = 0x75000, 1345 .halt_check = BRANCH_HALT, 1346 .clkr = { 1347 .enable_reg = 0x75000, 1348 .enable_mask = BIT(0), 1349 .hw.init = &(struct clk_init_data){ 1350 .name = "gcc_gp2_clk", 1351 .parent_data = &(const struct clk_parent_data){ 1352 .hw = &gcc_gp2_clk_src.clkr.hw, 1353 }, 1354 .num_parents = 1, 1355 .flags = CLK_SET_RATE_PARENT, 1356 .ops = &clk_branch2_ops, 1357 }, 1358 }, 1359 }; 1360 1361 static struct clk_branch gcc_gp3_clk = { 1362 .halt_reg = 0x76000, 1363 .halt_check = BRANCH_HALT, 1364 .clkr = { 1365 .enable_reg = 0x76000, 1366 .enable_mask = BIT(0), 1367 .hw.init = &(struct clk_init_data){ 1368 .name = "gcc_gp3_clk", 1369 .parent_data = &(const struct clk_parent_data){ 1370 .hw = &gcc_gp3_clk_src.clkr.hw, 1371 }, 1372 .num_parents = 1, 1373 .flags = CLK_SET_RATE_PARENT, 1374 .ops = &clk_branch2_ops, 1375 }, 1376 }, 1377 }; 1378 1379 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1380 .halt_check = BRANCH_HALT_DELAY, 1381 .clkr = { 1382 .enable_reg = 0x62000, 1383 .enable_mask = BIT(15), 1384 .hw.init = &(struct clk_init_data){ 1385 .name = "gcc_gpu_gpll0_clk_src", 1386 .parent_data = &(const struct clk_parent_data){ 1387 .hw = &gcc_gpll0.clkr.hw, 1388 }, 1389 .num_parents = 1, 1390 .flags = CLK_SET_RATE_PARENT, 1391 .ops = &clk_branch2_ops, 1392 }, 1393 }, 1394 }; 1395 1396 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1397 .halt_check = BRANCH_HALT_DELAY, 1398 .clkr = { 1399 .enable_reg = 0x62000, 1400 .enable_mask = BIT(16), 1401 .hw.init = &(struct clk_init_data){ 1402 .name = "gcc_gpu_gpll0_div_clk_src", 1403 .parent_data = &(const struct clk_parent_data){ 1404 .hw = &gcc_gpll0_out_even.clkr.hw, 1405 }, 1406 .num_parents = 1, 1407 .flags = CLK_SET_RATE_PARENT, 1408 .ops = &clk_branch2_ops, 1409 }, 1410 }, 1411 }; 1412 1413 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1414 .halt_reg = 0x81010, 1415 .halt_check = BRANCH_HALT_VOTED, 1416 .hwcg_reg = 0x81010, 1417 .hwcg_bit = 1, 1418 .clkr = { 1419 .enable_reg = 0x81010, 1420 .enable_mask = BIT(0), 1421 .hw.init = &(struct clk_init_data){ 1422 .name = "gcc_gpu_memnoc_gfx_clk", 1423 .ops = &clk_branch2_ops, 1424 }, 1425 }, 1426 }; 1427 1428 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1429 .halt_reg = 0x81018, 1430 .halt_check = BRANCH_HALT_DELAY, 1431 .clkr = { 1432 .enable_reg = 0x81018, 1433 .enable_mask = BIT(0), 1434 .hw.init = &(struct clk_init_data){ 1435 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1436 .ops = &clk_branch2_ops, 1437 }, 1438 }, 1439 }; 1440 1441 static struct clk_branch gcc_pcie_0_aux_clk = { 1442 .halt_reg = 0x7b034, 1443 .halt_check = BRANCH_HALT_VOTED, 1444 .clkr = { 1445 .enable_reg = 0x62008, 1446 .enable_mask = BIT(3), 1447 .hw.init = &(struct clk_init_data){ 1448 .name = "gcc_pcie_0_aux_clk", 1449 .parent_data = &(const struct clk_parent_data){ 1450 .hw = &gcc_pcie_0_aux_clk_src.clkr.hw, 1451 }, 1452 .num_parents = 1, 1453 .flags = CLK_SET_RATE_PARENT, 1454 .ops = &clk_branch2_ops, 1455 }, 1456 }, 1457 }; 1458 1459 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1460 .halt_reg = 0x7b030, 1461 .halt_check = BRANCH_HALT_VOTED, 1462 .hwcg_reg = 0x7b030, 1463 .hwcg_bit = 1, 1464 .clkr = { 1465 .enable_reg = 0x62008, 1466 .enable_mask = BIT(2), 1467 .hw.init = &(struct clk_init_data){ 1468 .name = "gcc_pcie_0_cfg_ahb_clk", 1469 .ops = &clk_branch2_ops, 1470 }, 1471 }, 1472 }; 1473 1474 static struct clk_branch gcc_pcie_0_clkref_en = { 1475 .halt_reg = 0x9c004, 1476 .halt_check = BRANCH_HALT, 1477 .clkr = { 1478 .enable_reg = 0x9c004, 1479 .enable_mask = BIT(0), 1480 .hw.init = &(struct clk_init_data){ 1481 .name = "gcc_pcie_0_clkref_en", 1482 .ops = &clk_branch2_ops, 1483 }, 1484 }, 1485 }; 1486 1487 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1488 .halt_reg = 0x7b028, 1489 .halt_check = BRANCH_HALT_SKIP, 1490 .clkr = { 1491 .enable_reg = 0x62008, 1492 .enable_mask = BIT(1), 1493 .hw.init = &(struct clk_init_data){ 1494 .name = "gcc_pcie_0_mstr_axi_clk", 1495 .ops = &clk_branch2_ops, 1496 }, 1497 }, 1498 }; 1499 1500 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 1501 .halt_reg = 0x7b044, 1502 .halt_check = BRANCH_HALT_VOTED, 1503 .clkr = { 1504 .enable_reg = 0x62000, 1505 .enable_mask = BIT(22), 1506 .hw.init = &(struct clk_init_data){ 1507 .name = "gcc_pcie_0_phy_rchng_clk", 1508 .parent_data = &(const struct clk_parent_data){ 1509 .hw = &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1510 }, 1511 .num_parents = 1, 1512 .flags = CLK_SET_RATE_PARENT, 1513 .ops = &clk_branch2_ops, 1514 }, 1515 }, 1516 }; 1517 1518 static struct clk_branch gcc_pcie_0_pipe_clk = { 1519 .halt_reg = 0x7b03c, 1520 .halt_check = BRANCH_HALT_SKIP, 1521 .clkr = { 1522 .enable_reg = 0x62008, 1523 .enable_mask = BIT(4), 1524 .hw.init = &(struct clk_init_data){ 1525 .name = "gcc_pcie_0_pipe_clk", 1526 .parent_data = &(const struct clk_parent_data){ 1527 .hw = &gcc_pcie_0_pipe_clk_src.clkr.hw, 1528 }, 1529 .num_parents = 1, 1530 .flags = CLK_SET_RATE_PARENT, 1531 .ops = &clk_branch2_ops, 1532 }, 1533 }, 1534 }; 1535 1536 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1537 .halt_reg = 0x7b020, 1538 .halt_check = BRANCH_HALT_VOTED, 1539 .hwcg_reg = 0x7b020, 1540 .hwcg_bit = 1, 1541 .clkr = { 1542 .enable_reg = 0x62008, 1543 .enable_mask = BIT(0), 1544 .hw.init = &(struct clk_init_data){ 1545 .name = "gcc_pcie_0_slv_axi_clk", 1546 .ops = &clk_branch2_ops, 1547 }, 1548 }, 1549 }; 1550 1551 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1552 .halt_reg = 0x7b01c, 1553 .halt_check = BRANCH_HALT_VOTED, 1554 .clkr = { 1555 .enable_reg = 0x62008, 1556 .enable_mask = BIT(5), 1557 .hw.init = &(struct clk_init_data){ 1558 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1559 .ops = &clk_branch2_ops, 1560 }, 1561 }, 1562 }; 1563 1564 static struct clk_branch gcc_pcie_1_aux_clk = { 1565 .halt_reg = 0x9d030, 1566 .halt_check = BRANCH_HALT_VOTED, 1567 .clkr = { 1568 .enable_reg = 0x62000, 1569 .enable_mask = BIT(29), 1570 .hw.init = &(struct clk_init_data){ 1571 .name = "gcc_pcie_1_aux_clk", 1572 .parent_data = &(const struct clk_parent_data){ 1573 .hw = &gcc_pcie_1_aux_clk_src.clkr.hw, 1574 }, 1575 .num_parents = 1, 1576 .flags = CLK_SET_RATE_PARENT, 1577 .ops = &clk_branch2_ops, 1578 }, 1579 }, 1580 }; 1581 1582 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1583 .halt_reg = 0x9d02c, 1584 .halt_check = BRANCH_HALT_VOTED, 1585 .hwcg_reg = 0x9d02c, 1586 .hwcg_bit = 1, 1587 .clkr = { 1588 .enable_reg = 0x62000, 1589 .enable_mask = BIT(28), 1590 .hw.init = &(struct clk_init_data){ 1591 .name = "gcc_pcie_1_cfg_ahb_clk", 1592 .ops = &clk_branch2_ops, 1593 }, 1594 }, 1595 }; 1596 1597 static struct clk_branch gcc_pcie_1_clkref_en = { 1598 .halt_reg = 0x9c008, 1599 .halt_check = BRANCH_HALT, 1600 .clkr = { 1601 .enable_reg = 0x9c008, 1602 .enable_mask = BIT(0), 1603 .hw.init = &(struct clk_init_data){ 1604 .name = "gcc_pcie_1_clkref_en", 1605 .ops = &clk_branch2_ops, 1606 }, 1607 }, 1608 }; 1609 1610 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1611 .halt_reg = 0x9d024, 1612 .halt_check = BRANCH_HALT_SKIP, 1613 .clkr = { 1614 .enable_reg = 0x62000, 1615 .enable_mask = BIT(27), 1616 .hw.init = &(struct clk_init_data){ 1617 .name = "gcc_pcie_1_mstr_axi_clk", 1618 .ops = &clk_branch2_ops, 1619 }, 1620 }, 1621 }; 1622 1623 static struct clk_branch gcc_pcie_1_phy_aux_clk = { 1624 .halt_reg = 0x9d038, 1625 .halt_check = BRANCH_HALT_VOTED, 1626 .clkr = { 1627 .enable_reg = 0x62000, 1628 .enable_mask = BIT(24), 1629 .hw.init = &(struct clk_init_data){ 1630 .name = "gcc_pcie_1_phy_aux_clk", 1631 .parent_data = &(const struct clk_parent_data){ 1632 .hw = &gcc_pcie_1_phy_aux_clk_src.clkr.hw, 1633 }, 1634 .num_parents = 1, 1635 .flags = CLK_SET_RATE_PARENT, 1636 .ops = &clk_branch2_ops, 1637 }, 1638 }, 1639 }; 1640 1641 static struct clk_branch gcc_pcie_1_phy_rchng_clk = { 1642 .halt_reg = 0x9d048, 1643 .halt_check = BRANCH_HALT_VOTED, 1644 .clkr = { 1645 .enable_reg = 0x62000, 1646 .enable_mask = BIT(23), 1647 .hw.init = &(struct clk_init_data){ 1648 .name = "gcc_pcie_1_phy_rchng_clk", 1649 .parent_data = &(const struct clk_parent_data){ 1650 .hw = &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 1651 }, 1652 .num_parents = 1, 1653 .flags = CLK_SET_RATE_PARENT, 1654 .ops = &clk_branch2_ops, 1655 }, 1656 }, 1657 }; 1658 1659 static struct clk_branch gcc_pcie_1_pipe_clk = { 1660 .halt_reg = 0x9d040, 1661 .halt_check = BRANCH_HALT_SKIP, 1662 .clkr = { 1663 .enable_reg = 0x62000, 1664 .enable_mask = BIT(30), 1665 .hw.init = &(struct clk_init_data){ 1666 .name = "gcc_pcie_1_pipe_clk", 1667 .parent_data = &(const struct clk_parent_data){ 1668 .hw = &gcc_pcie_1_pipe_clk_src.clkr.hw, 1669 }, 1670 .num_parents = 1, 1671 .flags = CLK_SET_RATE_PARENT, 1672 .ops = &clk_branch2_ops, 1673 }, 1674 }, 1675 }; 1676 1677 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1678 .halt_reg = 0x9d01c, 1679 .halt_check = BRANCH_HALT_VOTED, 1680 .hwcg_reg = 0x9d01c, 1681 .hwcg_bit = 1, 1682 .clkr = { 1683 .enable_reg = 0x62000, 1684 .enable_mask = BIT(26), 1685 .hw.init = &(struct clk_init_data){ 1686 .name = "gcc_pcie_1_slv_axi_clk", 1687 .ops = &clk_branch2_ops, 1688 }, 1689 }, 1690 }; 1691 1692 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 1693 .halt_reg = 0x9d018, 1694 .halt_check = BRANCH_HALT_VOTED, 1695 .clkr = { 1696 .enable_reg = 0x62000, 1697 .enable_mask = BIT(25), 1698 .hw.init = &(struct clk_init_data){ 1699 .name = "gcc_pcie_1_slv_q2a_axi_clk", 1700 .ops = &clk_branch2_ops, 1701 }, 1702 }, 1703 }; 1704 1705 static struct clk_branch gcc_pdm2_clk = { 1706 .halt_reg = 0x4300c, 1707 .halt_check = BRANCH_HALT, 1708 .clkr = { 1709 .enable_reg = 0x4300c, 1710 .enable_mask = BIT(0), 1711 .hw.init = &(struct clk_init_data){ 1712 .name = "gcc_pdm2_clk", 1713 .parent_data = &(const struct clk_parent_data){ 1714 .hw = &gcc_pdm2_clk_src.clkr.hw, 1715 }, 1716 .num_parents = 1, 1717 .flags = CLK_SET_RATE_PARENT, 1718 .ops = &clk_branch2_ops, 1719 }, 1720 }, 1721 }; 1722 1723 static struct clk_branch gcc_pdm_ahb_clk = { 1724 .halt_reg = 0x43004, 1725 .halt_check = BRANCH_HALT_VOTED, 1726 .hwcg_reg = 0x43004, 1727 .hwcg_bit = 1, 1728 .clkr = { 1729 .enable_reg = 0x43004, 1730 .enable_mask = BIT(0), 1731 .hw.init = &(struct clk_init_data){ 1732 .name = "gcc_pdm_ahb_clk", 1733 .ops = &clk_branch2_ops, 1734 }, 1735 }, 1736 }; 1737 1738 static struct clk_branch gcc_pdm_xo4_clk = { 1739 .halt_reg = 0x43008, 1740 .halt_check = BRANCH_HALT, 1741 .clkr = { 1742 .enable_reg = 0x43008, 1743 .enable_mask = BIT(0), 1744 .hw.init = &(struct clk_init_data){ 1745 .name = "gcc_pdm_xo4_clk", 1746 .ops = &clk_branch2_ops, 1747 }, 1748 }, 1749 }; 1750 1751 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 1752 .halt_reg = 0x36008, 1753 .halt_check = BRANCH_HALT_VOTED, 1754 .hwcg_reg = 0x36008, 1755 .hwcg_bit = 1, 1756 .clkr = { 1757 .enable_reg = 0x36008, 1758 .enable_mask = BIT(0), 1759 .hw.init = &(struct clk_init_data){ 1760 .name = "gcc_qmip_camera_nrt_ahb_clk", 1761 .ops = &clk_branch2_ops, 1762 }, 1763 }, 1764 }; 1765 1766 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 1767 .halt_reg = 0x3600c, 1768 .halt_check = BRANCH_HALT_VOTED, 1769 .hwcg_reg = 0x3600c, 1770 .hwcg_bit = 1, 1771 .clkr = { 1772 .enable_reg = 0x3600c, 1773 .enable_mask = BIT(0), 1774 .hw.init = &(struct clk_init_data){ 1775 .name = "gcc_qmip_camera_rt_ahb_clk", 1776 .ops = &clk_branch2_ops, 1777 }, 1778 }, 1779 }; 1780 1781 static struct clk_branch gcc_qmip_disp_ahb_clk = { 1782 .halt_reg = 0x37008, 1783 .halt_check = BRANCH_HALT_VOTED, 1784 .hwcg_reg = 0x37008, 1785 .hwcg_bit = 1, 1786 .clkr = { 1787 .enable_reg = 0x37008, 1788 .enable_mask = BIT(0), 1789 .hw.init = &(struct clk_init_data){ 1790 .name = "gcc_qmip_disp_ahb_clk", 1791 .ops = &clk_branch2_ops, 1792 }, 1793 }, 1794 }; 1795 1796 static struct clk_branch gcc_qmip_gpu_ahb_clk = { 1797 .halt_reg = 0x81008, 1798 .halt_check = BRANCH_HALT_VOTED, 1799 .hwcg_reg = 0x81008, 1800 .hwcg_bit = 1, 1801 .clkr = { 1802 .enable_reg = 0x81008, 1803 .enable_mask = BIT(0), 1804 .hw.init = &(struct clk_init_data){ 1805 .name = "gcc_qmip_gpu_ahb_clk", 1806 .ops = &clk_branch2_ops, 1807 }, 1808 }, 1809 }; 1810 1811 static struct clk_branch gcc_qmip_pcie_ahb_clk = { 1812 .halt_reg = 0x7b018, 1813 .halt_check = BRANCH_HALT_VOTED, 1814 .hwcg_reg = 0x7b018, 1815 .hwcg_bit = 1, 1816 .clkr = { 1817 .enable_reg = 0x7b018, 1818 .enable_mask = BIT(0), 1819 .hw.init = &(struct clk_init_data){ 1820 .name = "gcc_qmip_pcie_ahb_clk", 1821 .ops = &clk_branch2_ops, 1822 }, 1823 }, 1824 }; 1825 1826 static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = { 1827 .halt_reg = 0x42014, 1828 .halt_check = BRANCH_HALT_VOTED, 1829 .hwcg_reg = 0x42014, 1830 .hwcg_bit = 1, 1831 .clkr = { 1832 .enable_reg = 0x42014, 1833 .enable_mask = BIT(0), 1834 .hw.init = &(struct clk_init_data){ 1835 .name = "gcc_qmip_video_cv_cpu_ahb_clk", 1836 .ops = &clk_branch2_ops, 1837 }, 1838 }, 1839 }; 1840 1841 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 1842 .halt_reg = 0x42008, 1843 .halt_check = BRANCH_HALT_VOTED, 1844 .hwcg_reg = 0x42008, 1845 .hwcg_bit = 1, 1846 .clkr = { 1847 .enable_reg = 0x42008, 1848 .enable_mask = BIT(0), 1849 .hw.init = &(struct clk_init_data){ 1850 .name = "gcc_qmip_video_cvp_ahb_clk", 1851 .ops = &clk_branch2_ops, 1852 }, 1853 }, 1854 }; 1855 1856 static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = { 1857 .halt_reg = 0x42010, 1858 .halt_check = BRANCH_HALT_VOTED, 1859 .hwcg_reg = 0x42010, 1860 .hwcg_bit = 1, 1861 .clkr = { 1862 .enable_reg = 0x42010, 1863 .enable_mask = BIT(0), 1864 .hw.init = &(struct clk_init_data){ 1865 .name = "gcc_qmip_video_v_cpu_ahb_clk", 1866 .ops = &clk_branch2_ops, 1867 }, 1868 }, 1869 }; 1870 1871 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 1872 .halt_reg = 0x4200c, 1873 .halt_check = BRANCH_HALT_VOTED, 1874 .hwcg_reg = 0x4200c, 1875 .hwcg_bit = 1, 1876 .clkr = { 1877 .enable_reg = 0x4200c, 1878 .enable_mask = BIT(0), 1879 .hw.init = &(struct clk_init_data){ 1880 .name = "gcc_qmip_video_vcodec_ahb_clk", 1881 .ops = &clk_branch2_ops, 1882 }, 1883 }, 1884 }; 1885 1886 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 1887 .halt_reg = 0x3300c, 1888 .halt_check = BRANCH_HALT_VOTED, 1889 .clkr = { 1890 .enable_reg = 0x62008, 1891 .enable_mask = BIT(9), 1892 .hw.init = &(struct clk_init_data){ 1893 .name = "gcc_qupv3_wrap0_core_2x_clk", 1894 .ops = &clk_branch2_ops, 1895 }, 1896 }, 1897 }; 1898 1899 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 1900 .halt_reg = 0x33000, 1901 .halt_check = BRANCH_HALT_VOTED, 1902 .clkr = { 1903 .enable_reg = 0x62008, 1904 .enable_mask = BIT(8), 1905 .hw.init = &(struct clk_init_data){ 1906 .name = "gcc_qupv3_wrap0_core_clk", 1907 .ops = &clk_branch2_ops, 1908 }, 1909 }, 1910 }; 1911 1912 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 1913 .halt_reg = 0x2700c, 1914 .halt_check = BRANCH_HALT_VOTED, 1915 .clkr = { 1916 .enable_reg = 0x62008, 1917 .enable_mask = BIT(10), 1918 .hw.init = &(struct clk_init_data){ 1919 .name = "gcc_qupv3_wrap0_s0_clk", 1920 .parent_data = &(const struct clk_parent_data){ 1921 .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 1922 }, 1923 .num_parents = 1, 1924 .flags = CLK_SET_RATE_PARENT, 1925 .ops = &clk_branch2_ops, 1926 }, 1927 }, 1928 }; 1929 1930 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 1931 .halt_reg = 0x27140, 1932 .halt_check = BRANCH_HALT_VOTED, 1933 .clkr = { 1934 .enable_reg = 0x62008, 1935 .enable_mask = BIT(11), 1936 .hw.init = &(struct clk_init_data){ 1937 .name = "gcc_qupv3_wrap0_s1_clk", 1938 .parent_data = &(const struct clk_parent_data){ 1939 .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 1940 }, 1941 .num_parents = 1, 1942 .flags = CLK_SET_RATE_PARENT, 1943 .ops = &clk_branch2_ops, 1944 }, 1945 }, 1946 }; 1947 1948 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 1949 .halt_reg = 0x27274, 1950 .halt_check = BRANCH_HALT_VOTED, 1951 .clkr = { 1952 .enable_reg = 0x62008, 1953 .enable_mask = BIT(12), 1954 .hw.init = &(struct clk_init_data){ 1955 .name = "gcc_qupv3_wrap0_s2_clk", 1956 .parent_data = &(const struct clk_parent_data){ 1957 .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 1958 }, 1959 .num_parents = 1, 1960 .flags = CLK_SET_RATE_PARENT, 1961 .ops = &clk_branch2_ops, 1962 }, 1963 }, 1964 }; 1965 1966 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 1967 .halt_reg = 0x273a8, 1968 .halt_check = BRANCH_HALT_VOTED, 1969 .clkr = { 1970 .enable_reg = 0x62008, 1971 .enable_mask = BIT(13), 1972 .hw.init = &(struct clk_init_data){ 1973 .name = "gcc_qupv3_wrap0_s3_clk", 1974 .parent_data = &(const struct clk_parent_data){ 1975 .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 1976 }, 1977 .num_parents = 1, 1978 .flags = CLK_SET_RATE_PARENT, 1979 .ops = &clk_branch2_ops, 1980 }, 1981 }, 1982 }; 1983 1984 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 1985 .halt_reg = 0x274dc, 1986 .halt_check = BRANCH_HALT_VOTED, 1987 .clkr = { 1988 .enable_reg = 0x62008, 1989 .enable_mask = BIT(14), 1990 .hw.init = &(struct clk_init_data){ 1991 .name = "gcc_qupv3_wrap0_s4_clk", 1992 .parent_data = &(const struct clk_parent_data){ 1993 .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 1994 }, 1995 .num_parents = 1, 1996 .flags = CLK_SET_RATE_PARENT, 1997 .ops = &clk_branch2_ops, 1998 }, 1999 }, 2000 }; 2001 2002 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2003 .halt_reg = 0x27610, 2004 .halt_check = BRANCH_HALT_VOTED, 2005 .clkr = { 2006 .enable_reg = 0x62008, 2007 .enable_mask = BIT(15), 2008 .hw.init = &(struct clk_init_data){ 2009 .name = "gcc_qupv3_wrap0_s5_clk", 2010 .parent_data = &(const struct clk_parent_data){ 2011 .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2012 }, 2013 .num_parents = 1, 2014 .flags = CLK_SET_RATE_PARENT, 2015 .ops = &clk_branch2_ops, 2016 }, 2017 }, 2018 }; 2019 2020 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 2021 .halt_reg = 0x27744, 2022 .halt_check = BRANCH_HALT_VOTED, 2023 .clkr = { 2024 .enable_reg = 0x62008, 2025 .enable_mask = BIT(16), 2026 .hw.init = &(struct clk_init_data){ 2027 .name = "gcc_qupv3_wrap0_s6_clk", 2028 .parent_data = &(const struct clk_parent_data){ 2029 .hw = &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 2030 }, 2031 .num_parents = 1, 2032 .flags = CLK_SET_RATE_PARENT, 2033 .ops = &clk_branch2_ops, 2034 }, 2035 }, 2036 }; 2037 2038 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 2039 .halt_reg = 0x27878, 2040 .halt_check = BRANCH_HALT_VOTED, 2041 .clkr = { 2042 .enable_reg = 0x62008, 2043 .enable_mask = BIT(17), 2044 .hw.init = &(struct clk_init_data){ 2045 .name = "gcc_qupv3_wrap0_s7_clk", 2046 .parent_data = &(const struct clk_parent_data){ 2047 .hw = &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 2048 }, 2049 .num_parents = 1, 2050 .flags = CLK_SET_RATE_PARENT, 2051 .ops = &clk_branch2_ops, 2052 }, 2053 }, 2054 }; 2055 2056 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2057 .halt_reg = 0x3314c, 2058 .halt_check = BRANCH_HALT_VOTED, 2059 .clkr = { 2060 .enable_reg = 0x62008, 2061 .enable_mask = BIT(18), 2062 .hw.init = &(struct clk_init_data){ 2063 .name = "gcc_qupv3_wrap1_core_2x_clk", 2064 .ops = &clk_branch2_ops, 2065 }, 2066 }, 2067 }; 2068 2069 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2070 .halt_reg = 0x33140, 2071 .halt_check = BRANCH_HALT_VOTED, 2072 .clkr = { 2073 .enable_reg = 0x62008, 2074 .enable_mask = BIT(19), 2075 .hw.init = &(struct clk_init_data){ 2076 .name = "gcc_qupv3_wrap1_core_clk", 2077 .ops = &clk_branch2_ops, 2078 }, 2079 }, 2080 }; 2081 2082 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2083 .halt_reg = 0x2800c, 2084 .halt_check = BRANCH_HALT_VOTED, 2085 .clkr = { 2086 .enable_reg = 0x62008, 2087 .enable_mask = BIT(22), 2088 .hw.init = &(struct clk_init_data){ 2089 .name = "gcc_qupv3_wrap1_s0_clk", 2090 .parent_data = &(const struct clk_parent_data){ 2091 .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2092 }, 2093 .num_parents = 1, 2094 .flags = CLK_SET_RATE_PARENT, 2095 .ops = &clk_branch2_ops, 2096 }, 2097 }, 2098 }; 2099 2100 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2101 .halt_reg = 0x28140, 2102 .halt_check = BRANCH_HALT_VOTED, 2103 .clkr = { 2104 .enable_reg = 0x62008, 2105 .enable_mask = BIT(23), 2106 .hw.init = &(struct clk_init_data){ 2107 .name = "gcc_qupv3_wrap1_s1_clk", 2108 .parent_data = &(const struct clk_parent_data){ 2109 .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2110 }, 2111 .num_parents = 1, 2112 .flags = CLK_SET_RATE_PARENT, 2113 .ops = &clk_branch2_ops, 2114 }, 2115 }, 2116 }; 2117 2118 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2119 .halt_reg = 0x28274, 2120 .halt_check = BRANCH_HALT_VOTED, 2121 .clkr = { 2122 .enable_reg = 0x62008, 2123 .enable_mask = BIT(24), 2124 .hw.init = &(struct clk_init_data){ 2125 .name = "gcc_qupv3_wrap1_s2_clk", 2126 .parent_data = &(const struct clk_parent_data){ 2127 .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2128 }, 2129 .num_parents = 1, 2130 .flags = CLK_SET_RATE_PARENT, 2131 .ops = &clk_branch2_ops, 2132 }, 2133 }, 2134 }; 2135 2136 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2137 .halt_reg = 0x283a8, 2138 .halt_check = BRANCH_HALT_VOTED, 2139 .clkr = { 2140 .enable_reg = 0x62008, 2141 .enable_mask = BIT(25), 2142 .hw.init = &(struct clk_init_data){ 2143 .name = "gcc_qupv3_wrap1_s3_clk", 2144 .parent_data = &(const struct clk_parent_data){ 2145 .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2146 }, 2147 .num_parents = 1, 2148 .flags = CLK_SET_RATE_PARENT, 2149 .ops = &clk_branch2_ops, 2150 }, 2151 }, 2152 }; 2153 2154 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2155 .halt_reg = 0x284dc, 2156 .halt_check = BRANCH_HALT_VOTED, 2157 .clkr = { 2158 .enable_reg = 0x62008, 2159 .enable_mask = BIT(26), 2160 .hw.init = &(struct clk_init_data){ 2161 .name = "gcc_qupv3_wrap1_s4_clk", 2162 .parent_data = &(const struct clk_parent_data){ 2163 .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2164 }, 2165 .num_parents = 1, 2166 .flags = CLK_SET_RATE_PARENT, 2167 .ops = &clk_branch2_ops, 2168 }, 2169 }, 2170 }; 2171 2172 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2173 .halt_reg = 0x28610, 2174 .halt_check = BRANCH_HALT_VOTED, 2175 .clkr = { 2176 .enable_reg = 0x62008, 2177 .enable_mask = BIT(27), 2178 .hw.init = &(struct clk_init_data){ 2179 .name = "gcc_qupv3_wrap1_s5_clk", 2180 .parent_data = &(const struct clk_parent_data){ 2181 .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2182 }, 2183 .num_parents = 1, 2184 .flags = CLK_SET_RATE_PARENT, 2185 .ops = &clk_branch2_ops, 2186 }, 2187 }, 2188 }; 2189 2190 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 2191 .halt_reg = 0x28744, 2192 .halt_check = BRANCH_HALT_VOTED, 2193 .clkr = { 2194 .enable_reg = 0x62008, 2195 .enable_mask = BIT(28), 2196 .hw.init = &(struct clk_init_data){ 2197 .name = "gcc_qupv3_wrap1_s6_clk", 2198 .parent_data = &(const struct clk_parent_data){ 2199 .hw = &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 2200 }, 2201 .num_parents = 1, 2202 .flags = CLK_SET_RATE_PARENT, 2203 .ops = &clk_branch2_ops, 2204 }, 2205 }, 2206 }; 2207 2208 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 2209 .halt_reg = 0x3328c, 2210 .halt_check = BRANCH_HALT_VOTED, 2211 .clkr = { 2212 .enable_reg = 0x62010, 2213 .enable_mask = BIT(3), 2214 .hw.init = &(struct clk_init_data){ 2215 .name = "gcc_qupv3_wrap2_core_2x_clk", 2216 .ops = &clk_branch2_ops, 2217 }, 2218 }, 2219 }; 2220 2221 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 2222 .halt_reg = 0x33280, 2223 .halt_check = BRANCH_HALT_VOTED, 2224 .clkr = { 2225 .enable_reg = 0x62010, 2226 .enable_mask = BIT(0), 2227 .hw.init = &(struct clk_init_data){ 2228 .name = "gcc_qupv3_wrap2_core_clk", 2229 .ops = &clk_branch2_ops, 2230 }, 2231 }, 2232 }; 2233 2234 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 2235 .halt_reg = 0x2e00c, 2236 .halt_check = BRANCH_HALT_VOTED, 2237 .clkr = { 2238 .enable_reg = 0x62010, 2239 .enable_mask = BIT(4), 2240 .hw.init = &(struct clk_init_data){ 2241 .name = "gcc_qupv3_wrap2_s0_clk", 2242 .parent_data = &(const struct clk_parent_data){ 2243 .hw = &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 2244 }, 2245 .num_parents = 1, 2246 .flags = CLK_SET_RATE_PARENT, 2247 .ops = &clk_branch2_ops, 2248 }, 2249 }, 2250 }; 2251 2252 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 2253 .halt_reg = 0x2e140, 2254 .halt_check = BRANCH_HALT_VOTED, 2255 .clkr = { 2256 .enable_reg = 0x62010, 2257 .enable_mask = BIT(5), 2258 .hw.init = &(struct clk_init_data){ 2259 .name = "gcc_qupv3_wrap2_s1_clk", 2260 .parent_data = &(const struct clk_parent_data){ 2261 .hw = &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 2262 }, 2263 .num_parents = 1, 2264 .flags = CLK_SET_RATE_PARENT, 2265 .ops = &clk_branch2_ops, 2266 }, 2267 }, 2268 }; 2269 2270 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 2271 .halt_reg = 0x2e274, 2272 .halt_check = BRANCH_HALT_VOTED, 2273 .clkr = { 2274 .enable_reg = 0x62010, 2275 .enable_mask = BIT(6), 2276 .hw.init = &(struct clk_init_data){ 2277 .name = "gcc_qupv3_wrap2_s2_clk", 2278 .parent_data = &(const struct clk_parent_data){ 2279 .hw = &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 2280 }, 2281 .num_parents = 1, 2282 .flags = CLK_SET_RATE_PARENT, 2283 .ops = &clk_branch2_ops, 2284 }, 2285 }, 2286 }; 2287 2288 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 2289 .halt_reg = 0x2e3a8, 2290 .halt_check = BRANCH_HALT_VOTED, 2291 .clkr = { 2292 .enable_reg = 0x62010, 2293 .enable_mask = BIT(7), 2294 .hw.init = &(struct clk_init_data){ 2295 .name = "gcc_qupv3_wrap2_s3_clk", 2296 .parent_data = &(const struct clk_parent_data){ 2297 .hw = &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 2298 }, 2299 .num_parents = 1, 2300 .flags = CLK_SET_RATE_PARENT, 2301 .ops = &clk_branch2_ops, 2302 }, 2303 }, 2304 }; 2305 2306 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 2307 .halt_reg = 0x2e4dc, 2308 .halt_check = BRANCH_HALT_VOTED, 2309 .clkr = { 2310 .enable_reg = 0x62010, 2311 .enable_mask = BIT(8), 2312 .hw.init = &(struct clk_init_data){ 2313 .name = "gcc_qupv3_wrap2_s4_clk", 2314 .parent_data = &(const struct clk_parent_data){ 2315 .hw = &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 2316 }, 2317 .num_parents = 1, 2318 .flags = CLK_SET_RATE_PARENT, 2319 .ops = &clk_branch2_ops, 2320 }, 2321 }, 2322 }; 2323 2324 static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 2325 .halt_reg = 0x2e610, 2326 .halt_check = BRANCH_HALT_VOTED, 2327 .clkr = { 2328 .enable_reg = 0x62010, 2329 .enable_mask = BIT(9), 2330 .hw.init = &(struct clk_init_data){ 2331 .name = "gcc_qupv3_wrap2_s5_clk", 2332 .parent_data = &(const struct clk_parent_data){ 2333 .hw = &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 2334 }, 2335 .num_parents = 1, 2336 .flags = CLK_SET_RATE_PARENT, 2337 .ops = &clk_branch2_ops, 2338 }, 2339 }, 2340 }; 2341 2342 static struct clk_branch gcc_qupv3_wrap2_s6_clk = { 2343 .halt_reg = 0x2e744, 2344 .halt_check = BRANCH_HALT_VOTED, 2345 .clkr = { 2346 .enable_reg = 0x62010, 2347 .enable_mask = BIT(10), 2348 .hw.init = &(struct clk_init_data){ 2349 .name = "gcc_qupv3_wrap2_s6_clk", 2350 .parent_data = &(const struct clk_parent_data){ 2351 .hw = &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, 2352 }, 2353 .num_parents = 1, 2354 .flags = CLK_SET_RATE_PARENT, 2355 .ops = &clk_branch2_ops, 2356 }, 2357 }, 2358 }; 2359 2360 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2361 .halt_reg = 0x27004, 2362 .halt_check = BRANCH_HALT_VOTED, 2363 .hwcg_reg = 0x27004, 2364 .hwcg_bit = 1, 2365 .clkr = { 2366 .enable_reg = 0x62008, 2367 .enable_mask = BIT(6), 2368 .hw.init = &(struct clk_init_data){ 2369 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2370 .ops = &clk_branch2_ops, 2371 }, 2372 }, 2373 }; 2374 2375 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2376 .halt_reg = 0x27008, 2377 .halt_check = BRANCH_HALT_VOTED, 2378 .hwcg_reg = 0x27008, 2379 .hwcg_bit = 1, 2380 .clkr = { 2381 .enable_reg = 0x62008, 2382 .enable_mask = BIT(7), 2383 .hw.init = &(struct clk_init_data){ 2384 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2385 .ops = &clk_branch2_ops, 2386 }, 2387 }, 2388 }; 2389 2390 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2391 .halt_reg = 0x28004, 2392 .halt_check = BRANCH_HALT_VOTED, 2393 .hwcg_reg = 0x28004, 2394 .hwcg_bit = 1, 2395 .clkr = { 2396 .enable_reg = 0x62008, 2397 .enable_mask = BIT(20), 2398 .hw.init = &(struct clk_init_data){ 2399 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2400 .ops = &clk_branch2_ops, 2401 }, 2402 }, 2403 }; 2404 2405 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2406 .halt_reg = 0x28008, 2407 .halt_check = BRANCH_HALT_VOTED, 2408 .hwcg_reg = 0x28008, 2409 .hwcg_bit = 1, 2410 .clkr = { 2411 .enable_reg = 0x62008, 2412 .enable_mask = BIT(21), 2413 .hw.init = &(struct clk_init_data){ 2414 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2415 .ops = &clk_branch2_ops, 2416 }, 2417 }, 2418 }; 2419 2420 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 2421 .halt_reg = 0x2e004, 2422 .halt_check = BRANCH_HALT_VOTED, 2423 .hwcg_reg = 0x2e004, 2424 .hwcg_bit = 1, 2425 .clkr = { 2426 .enable_reg = 0x62010, 2427 .enable_mask = BIT(2), 2428 .hw.init = &(struct clk_init_data){ 2429 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 2430 .ops = &clk_branch2_ops, 2431 }, 2432 }, 2433 }; 2434 2435 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 2436 .halt_reg = 0x2e008, 2437 .halt_check = BRANCH_HALT_VOTED, 2438 .hwcg_reg = 0x2e008, 2439 .hwcg_bit = 1, 2440 .clkr = { 2441 .enable_reg = 0x62010, 2442 .enable_mask = BIT(1), 2443 .hw.init = &(struct clk_init_data){ 2444 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 2445 .ops = &clk_branch2_ops, 2446 }, 2447 }, 2448 }; 2449 2450 static struct clk_branch gcc_sdcc2_ahb_clk = { 2451 .halt_reg = 0x2400c, 2452 .halt_check = BRANCH_HALT, 2453 .clkr = { 2454 .enable_reg = 0x2400c, 2455 .enable_mask = BIT(0), 2456 .hw.init = &(struct clk_init_data){ 2457 .name = "gcc_sdcc2_ahb_clk", 2458 .ops = &clk_branch2_ops, 2459 }, 2460 }, 2461 }; 2462 2463 static struct clk_branch gcc_sdcc2_apps_clk = { 2464 .halt_reg = 0x24004, 2465 .halt_check = BRANCH_HALT, 2466 .clkr = { 2467 .enable_reg = 0x24004, 2468 .enable_mask = BIT(0), 2469 .hw.init = &(struct clk_init_data){ 2470 .name = "gcc_sdcc2_apps_clk", 2471 .parent_data = &(const struct clk_parent_data){ 2472 .hw = &gcc_sdcc2_apps_clk_src.clkr.hw, 2473 }, 2474 .num_parents = 1, 2475 .flags = CLK_SET_RATE_PARENT, 2476 .ops = &clk_branch2_ops, 2477 }, 2478 }, 2479 }; 2480 2481 static struct clk_branch gcc_sdcc2_at_clk = { 2482 .halt_reg = 0x24010, 2483 .halt_check = BRANCH_HALT_VOTED, 2484 .hwcg_reg = 0x24010, 2485 .hwcg_bit = 1, 2486 .clkr = { 2487 .enable_reg = 0x24010, 2488 .enable_mask = BIT(0), 2489 .hw.init = &(struct clk_init_data){ 2490 .name = "gcc_sdcc2_at_clk", 2491 .ops = &clk_branch2_ops, 2492 }, 2493 }, 2494 }; 2495 2496 static struct clk_branch gcc_sdcc4_ahb_clk = { 2497 .halt_reg = 0x2600c, 2498 .halt_check = BRANCH_HALT, 2499 .clkr = { 2500 .enable_reg = 0x2600c, 2501 .enable_mask = BIT(0), 2502 .hw.init = &(struct clk_init_data){ 2503 .name = "gcc_sdcc4_ahb_clk", 2504 .ops = &clk_branch2_ops, 2505 }, 2506 }, 2507 }; 2508 2509 static struct clk_branch gcc_sdcc4_apps_clk = { 2510 .halt_reg = 0x26004, 2511 .halt_check = BRANCH_HALT, 2512 .clkr = { 2513 .enable_reg = 0x26004, 2514 .enable_mask = BIT(0), 2515 .hw.init = &(struct clk_init_data){ 2516 .name = "gcc_sdcc4_apps_clk", 2517 .parent_data = &(const struct clk_parent_data){ 2518 .hw = &gcc_sdcc4_apps_clk_src.clkr.hw, 2519 }, 2520 .num_parents = 1, 2521 .flags = CLK_SET_RATE_PARENT, 2522 .ops = &clk_branch2_ops, 2523 }, 2524 }, 2525 }; 2526 2527 static struct clk_branch gcc_sdcc4_at_clk = { 2528 .halt_reg = 0x26010, 2529 .halt_check = BRANCH_HALT_VOTED, 2530 .hwcg_reg = 0x26010, 2531 .hwcg_bit = 1, 2532 .clkr = { 2533 .enable_reg = 0x26010, 2534 .enable_mask = BIT(0), 2535 .hw.init = &(struct clk_init_data){ 2536 .name = "gcc_sdcc4_at_clk", 2537 .ops = &clk_branch2_ops, 2538 }, 2539 }, 2540 }; 2541 2542 static struct clk_branch gcc_ufs_0_clkref_en = { 2543 .halt_reg = 0x9c000, 2544 .halt_check = BRANCH_HALT, 2545 .clkr = { 2546 .enable_reg = 0x9c000, 2547 .enable_mask = BIT(0), 2548 .hw.init = &(struct clk_init_data){ 2549 .name = "gcc_ufs_0_clkref_en", 2550 .ops = &clk_branch2_ops, 2551 }, 2552 }, 2553 }; 2554 2555 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2556 .halt_reg = 0x87020, 2557 .halt_check = BRANCH_HALT_VOTED, 2558 .hwcg_reg = 0x87020, 2559 .hwcg_bit = 1, 2560 .clkr = { 2561 .enable_reg = 0x87020, 2562 .enable_mask = BIT(0), 2563 .hw.init = &(struct clk_init_data){ 2564 .name = "gcc_ufs_phy_ahb_clk", 2565 .ops = &clk_branch2_ops, 2566 }, 2567 }, 2568 }; 2569 2570 static struct clk_branch gcc_ufs_phy_axi_clk = { 2571 .halt_reg = 0x87018, 2572 .halt_check = BRANCH_HALT_VOTED, 2573 .hwcg_reg = 0x87018, 2574 .hwcg_bit = 1, 2575 .clkr = { 2576 .enable_reg = 0x87018, 2577 .enable_mask = BIT(0), 2578 .hw.init = &(struct clk_init_data){ 2579 .name = "gcc_ufs_phy_axi_clk", 2580 .parent_data = &(const struct clk_parent_data){ 2581 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 2582 }, 2583 .num_parents = 1, 2584 .flags = CLK_SET_RATE_PARENT, 2585 .ops = &clk_branch2_ops, 2586 }, 2587 }, 2588 }; 2589 2590 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { 2591 .halt_reg = 0x87018, 2592 .halt_check = BRANCH_HALT_VOTED, 2593 .hwcg_reg = 0x87018, 2594 .hwcg_bit = 1, 2595 .clkr = { 2596 .enable_reg = 0x87018, 2597 .enable_mask = BIT(1), 2598 .hw.init = &(struct clk_init_data){ 2599 .name = "gcc_ufs_phy_axi_hw_ctl_clk", 2600 .parent_data = &(const struct clk_parent_data){ 2601 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 2602 }, 2603 .num_parents = 1, 2604 .flags = CLK_SET_RATE_PARENT, 2605 .ops = &clk_branch2_ops, 2606 }, 2607 }, 2608 }; 2609 2610 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2611 .halt_reg = 0x8706c, 2612 .halt_check = BRANCH_HALT_VOTED, 2613 .hwcg_reg = 0x8706c, 2614 .hwcg_bit = 1, 2615 .clkr = { 2616 .enable_reg = 0x8706c, 2617 .enable_mask = BIT(0), 2618 .hw.init = &(struct clk_init_data){ 2619 .name = "gcc_ufs_phy_ice_core_clk", 2620 .parent_data = &(const struct clk_parent_data){ 2621 .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2622 }, 2623 .num_parents = 1, 2624 .flags = CLK_SET_RATE_PARENT, 2625 .ops = &clk_branch2_ops, 2626 }, 2627 }, 2628 }; 2629 2630 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { 2631 .halt_reg = 0x8706c, 2632 .halt_check = BRANCH_HALT_VOTED, 2633 .hwcg_reg = 0x8706c, 2634 .hwcg_bit = 1, 2635 .clkr = { 2636 .enable_reg = 0x8706c, 2637 .enable_mask = BIT(1), 2638 .hw.init = &(struct clk_init_data){ 2639 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", 2640 .parent_data = &(const struct clk_parent_data){ 2641 .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2642 }, 2643 .num_parents = 1, 2644 .flags = CLK_SET_RATE_PARENT, 2645 .ops = &clk_branch2_ops, 2646 }, 2647 }, 2648 }; 2649 2650 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2651 .halt_reg = 0x870a4, 2652 .halt_check = BRANCH_HALT_VOTED, 2653 .hwcg_reg = 0x870a4, 2654 .hwcg_bit = 1, 2655 .clkr = { 2656 .enable_reg = 0x870a4, 2657 .enable_mask = BIT(0), 2658 .hw.init = &(struct clk_init_data){ 2659 .name = "gcc_ufs_phy_phy_aux_clk", 2660 .parent_data = &(const struct clk_parent_data){ 2661 .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2662 }, 2663 .num_parents = 1, 2664 .flags = CLK_SET_RATE_PARENT, 2665 .ops = &clk_branch2_ops, 2666 }, 2667 }, 2668 }; 2669 2670 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { 2671 .halt_reg = 0x870a4, 2672 .halt_check = BRANCH_HALT_VOTED, 2673 .hwcg_reg = 0x870a4, 2674 .hwcg_bit = 1, 2675 .clkr = { 2676 .enable_reg = 0x870a4, 2677 .enable_mask = BIT(1), 2678 .hw.init = &(struct clk_init_data){ 2679 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", 2680 .parent_data = &(const struct clk_parent_data){ 2681 .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2682 }, 2683 .num_parents = 1, 2684 .flags = CLK_SET_RATE_PARENT, 2685 .ops = &clk_branch2_ops, 2686 }, 2687 }, 2688 }; 2689 2690 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2691 .halt_reg = 0x87028, 2692 .halt_check = BRANCH_HALT_DELAY, 2693 .clkr = { 2694 .enable_reg = 0x87028, 2695 .enable_mask = BIT(0), 2696 .hw.init = &(struct clk_init_data){ 2697 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2698 .parent_data = &(const struct clk_parent_data){ 2699 .hw = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 2700 }, 2701 .num_parents = 1, 2702 .flags = CLK_SET_RATE_PARENT, 2703 .ops = &clk_branch2_ops, 2704 }, 2705 }, 2706 }; 2707 2708 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2709 .halt_reg = 0x870c0, 2710 .halt_check = BRANCH_HALT_DELAY, 2711 .clkr = { 2712 .enable_reg = 0x870c0, 2713 .enable_mask = BIT(0), 2714 .hw.init = &(struct clk_init_data){ 2715 .name = "gcc_ufs_phy_rx_symbol_1_clk", 2716 .parent_data = &(const struct clk_parent_data){ 2717 .hw = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 2718 }, 2719 .num_parents = 1, 2720 .flags = CLK_SET_RATE_PARENT, 2721 .ops = &clk_branch2_ops, 2722 }, 2723 }, 2724 }; 2725 2726 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2727 .halt_reg = 0x87024, 2728 .halt_check = BRANCH_HALT_DELAY, 2729 .clkr = { 2730 .enable_reg = 0x87024, 2731 .enable_mask = BIT(0), 2732 .hw.init = &(struct clk_init_data){ 2733 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2734 .parent_data = &(const struct clk_parent_data){ 2735 .hw = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 2736 }, 2737 .num_parents = 1, 2738 .flags = CLK_SET_RATE_PARENT, 2739 .ops = &clk_branch2_ops, 2740 }, 2741 }, 2742 }; 2743 2744 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2745 .halt_reg = 0x87064, 2746 .halt_check = BRANCH_HALT_VOTED, 2747 .hwcg_reg = 0x87064, 2748 .hwcg_bit = 1, 2749 .clkr = { 2750 .enable_reg = 0x87064, 2751 .enable_mask = BIT(0), 2752 .hw.init = &(struct clk_init_data){ 2753 .name = "gcc_ufs_phy_unipro_core_clk", 2754 .parent_data = &(const struct clk_parent_data){ 2755 .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2756 }, 2757 .num_parents = 1, 2758 .flags = CLK_SET_RATE_PARENT, 2759 .ops = &clk_branch2_ops, 2760 }, 2761 }, 2762 }; 2763 2764 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { 2765 .halt_reg = 0x87064, 2766 .halt_check = BRANCH_HALT_VOTED, 2767 .hwcg_reg = 0x87064, 2768 .hwcg_bit = 1, 2769 .clkr = { 2770 .enable_reg = 0x87064, 2771 .enable_mask = BIT(1), 2772 .hw.init = &(struct clk_init_data){ 2773 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", 2774 .parent_data = &(const struct clk_parent_data){ 2775 .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2776 }, 2777 .num_parents = 1, 2778 .flags = CLK_SET_RATE_PARENT, 2779 .ops = &clk_branch2_ops, 2780 }, 2781 }, 2782 }; 2783 2784 static struct clk_branch gcc_usb30_prim_master_clk = { 2785 .halt_reg = 0x49018, 2786 .halt_check = BRANCH_HALT, 2787 .clkr = { 2788 .enable_reg = 0x49018, 2789 .enable_mask = BIT(0), 2790 .hw.init = &(struct clk_init_data){ 2791 .name = "gcc_usb30_prim_master_clk", 2792 .parent_data = &(const struct clk_parent_data){ 2793 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 2794 }, 2795 .num_parents = 1, 2796 .flags = CLK_SET_RATE_PARENT, 2797 .ops = &clk_branch2_ops, 2798 }, 2799 }, 2800 }; 2801 2802 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2803 .halt_reg = 0x49024, 2804 .halt_check = BRANCH_HALT, 2805 .clkr = { 2806 .enable_reg = 0x49024, 2807 .enable_mask = BIT(0), 2808 .hw.init = &(struct clk_init_data){ 2809 .name = "gcc_usb30_prim_mock_utmi_clk", 2810 .parent_data = &(const struct clk_parent_data){ 2811 .hw = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2812 }, 2813 .num_parents = 1, 2814 .flags = CLK_SET_RATE_PARENT, 2815 .ops = &clk_branch2_ops, 2816 }, 2817 }, 2818 }; 2819 2820 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2821 .halt_reg = 0x49020, 2822 .halt_check = BRANCH_HALT, 2823 .clkr = { 2824 .enable_reg = 0x49020, 2825 .enable_mask = BIT(0), 2826 .hw.init = &(struct clk_init_data){ 2827 .name = "gcc_usb30_prim_sleep_clk", 2828 .ops = &clk_branch2_ops, 2829 }, 2830 }, 2831 }; 2832 2833 static struct clk_branch gcc_usb3_0_clkref_en = { 2834 .halt_reg = 0x9c010, 2835 .halt_check = BRANCH_HALT, 2836 .clkr = { 2837 .enable_reg = 0x9c010, 2838 .enable_mask = BIT(0), 2839 .hw.init = &(struct clk_init_data){ 2840 .name = "gcc_usb3_0_clkref_en", 2841 .ops = &clk_branch2_ops, 2842 }, 2843 }, 2844 }; 2845 2846 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2847 .halt_reg = 0x4905c, 2848 .halt_check = BRANCH_HALT, 2849 .clkr = { 2850 .enable_reg = 0x4905c, 2851 .enable_mask = BIT(0), 2852 .hw.init = &(struct clk_init_data){ 2853 .name = "gcc_usb3_prim_phy_aux_clk", 2854 .parent_data = &(const struct clk_parent_data){ 2855 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2856 }, 2857 .num_parents = 1, 2858 .flags = CLK_SET_RATE_PARENT, 2859 .ops = &clk_branch2_ops, 2860 }, 2861 }, 2862 }; 2863 2864 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2865 .halt_reg = 0x49060, 2866 .halt_check = BRANCH_HALT, 2867 .clkr = { 2868 .enable_reg = 0x49060, 2869 .enable_mask = BIT(0), 2870 .hw.init = &(struct clk_init_data){ 2871 .name = "gcc_usb3_prim_phy_com_aux_clk", 2872 .parent_data = &(const struct clk_parent_data){ 2873 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2874 }, 2875 .num_parents = 1, 2876 .flags = CLK_SET_RATE_PARENT, 2877 .ops = &clk_branch2_ops, 2878 }, 2879 }, 2880 }; 2881 2882 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2883 .halt_reg = 0x49064, 2884 .halt_check = BRANCH_HALT_DELAY, 2885 .hwcg_reg = 0x49064, 2886 .hwcg_bit = 1, 2887 .clkr = { 2888 .enable_reg = 0x49064, 2889 .enable_mask = BIT(0), 2890 .hw.init = &(struct clk_init_data){ 2891 .name = "gcc_usb3_prim_phy_pipe_clk", 2892 .parent_data = &(const struct clk_parent_data){ 2893 .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 2894 }, 2895 .num_parents = 1, 2896 .flags = CLK_SET_RATE_PARENT, 2897 .ops = &clk_branch2_ops, 2898 }, 2899 }, 2900 }; 2901 2902 static struct clk_branch gcc_video_axi0_clk = { 2903 .halt_reg = 0x42018, 2904 .halt_check = BRANCH_HALT_SKIP, 2905 .hwcg_reg = 0x42018, 2906 .hwcg_bit = 1, 2907 .clkr = { 2908 .enable_reg = 0x42018, 2909 .enable_mask = BIT(0), 2910 .hw.init = &(struct clk_init_data){ 2911 .name = "gcc_video_axi0_clk", 2912 .ops = &clk_branch2_ops, 2913 }, 2914 }, 2915 }; 2916 2917 static struct clk_branch gcc_video_axi1_clk = { 2918 .halt_reg = 0x42020, 2919 .halt_check = BRANCH_HALT_SKIP, 2920 .hwcg_reg = 0x42020, 2921 .hwcg_bit = 1, 2922 .clkr = { 2923 .enable_reg = 0x42020, 2924 .enable_mask = BIT(0), 2925 .hw.init = &(struct clk_init_data){ 2926 .name = "gcc_video_axi1_clk", 2927 .ops = &clk_branch2_ops, 2928 }, 2929 }, 2930 }; 2931 2932 static struct gdsc pcie_0_gdsc = { 2933 .gdscr = 0x7b004, 2934 .pd = { 2935 .name = "pcie_0_gdsc", 2936 }, 2937 .pwrsts = PWRSTS_OFF_ON, 2938 }; 2939 2940 static struct gdsc pcie_1_gdsc = { 2941 .gdscr = 0x9d004, 2942 .pd = { 2943 .name = "pcie_1_gdsc", 2944 }, 2945 .pwrsts = PWRSTS_OFF_ON, 2946 }; 2947 2948 static struct gdsc ufs_phy_gdsc = { 2949 .gdscr = 0x87004, 2950 .pd = { 2951 .name = "ufs_phy_gdsc", 2952 }, 2953 .pwrsts = PWRSTS_OFF_ON, 2954 }; 2955 2956 static struct gdsc usb30_prim_gdsc = { 2957 .gdscr = 0x49004, 2958 .pd = { 2959 .name = "usb30_prim_gdsc", 2960 }, 2961 .pwrsts = PWRSTS_OFF_ON, 2962 }; 2963 2964 static struct clk_regmap *gcc_sm8450_clocks[] = { 2965 [GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr, 2966 [GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr, 2967 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 2968 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, 2969 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 2970 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2971 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 2972 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 2973 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr, 2974 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2975 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 2976 [GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr, 2977 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 2978 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, 2979 [GCC_EUSB3_0_CLKREF_EN] = &gcc_eusb3_0_clkref_en.clkr, 2980 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2981 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2982 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2983 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2984 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2985 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2986 [GCC_GPLL0] = &gcc_gpll0.clkr, 2987 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 2988 [GCC_GPLL4] = &gcc_gpll4.clkr, 2989 [GCC_GPLL9] = &gcc_gpll9.clkr, 2990 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 2991 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 2992 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 2993 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 2994 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2995 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 2996 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2997 [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr, 2998 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2999 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 3000 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 3001 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3002 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 3003 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3004 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 3005 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 3006 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 3007 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 3008 [GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr, 3009 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 3010 [GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr, 3011 [GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr, 3012 [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr, 3013 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 3014 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 3015 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr, 3016 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 3017 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 3018 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3019 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3020 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3021 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3022 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3023 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3024 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3025 [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr, 3026 [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr, 3027 [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr, 3028 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 3029 [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr, 3030 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3031 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 3032 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 3033 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3034 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3035 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3036 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3037 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3038 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3039 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3040 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3041 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3042 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3043 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3044 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3045 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 3046 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 3047 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 3048 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 3049 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3050 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3051 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3052 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3053 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3054 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3055 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3056 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3057 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3058 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3059 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3060 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3061 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3062 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3063 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 3064 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 3065 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 3066 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 3067 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 3068 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 3069 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 3070 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 3071 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 3072 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 3073 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 3074 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 3075 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 3076 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 3077 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 3078 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 3079 [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr, 3080 [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr, 3081 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3082 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3083 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3084 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3085 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 3086 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 3087 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3088 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3089 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3090 [GCC_SDCC2_AT_CLK] = &gcc_sdcc2_at_clk.clkr, 3091 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3092 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3093 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 3094 [GCC_SDCC4_AT_CLK] = &gcc_sdcc4_at_clk.clkr, 3095 [GCC_UFS_0_CLKREF_EN] = &gcc_ufs_0_clkref_en.clkr, 3096 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3097 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3098 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3099 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, 3100 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3101 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3102 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, 3103 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3104 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3105 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, 3106 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3107 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 3108 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3109 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 3110 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3111 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 3112 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3113 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 3114 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, 3115 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3116 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3117 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3118 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3119 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3120 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3121 [GCC_USB3_0_CLKREF_EN] = &gcc_usb3_0_clkref_en.clkr, 3122 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3123 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3124 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3125 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3126 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 3127 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3128 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 3129 }; 3130 3131 static const struct qcom_reset_map gcc_sm8450_resets[] = { 3132 [GCC_CAMERA_BCR] = { 0x36000 }, 3133 [GCC_DISPLAY_BCR] = { 0x37000 }, 3134 [GCC_GPU_BCR] = { 0x81000 }, 3135 [GCC_PCIE_0_BCR] = { 0x7b000 }, 3136 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x7c014 }, 3137 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x7c020 }, 3138 [GCC_PCIE_0_PHY_BCR] = { 0x7c01c }, 3139 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x7c028 }, 3140 [GCC_PCIE_1_BCR] = { 0x9d000 }, 3141 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x9e014 }, 3142 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x9e020 }, 3143 [GCC_PCIE_1_PHY_BCR] = { 0x9e01c }, 3144 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 }, 3145 [GCC_PCIE_PHY_BCR] = { 0x7f000 }, 3146 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c }, 3147 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 }, 3148 [GCC_PDM_BCR] = { 0x43000 }, 3149 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 }, 3150 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 }, 3151 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x2e000 }, 3152 [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 }, 3153 [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 }, 3154 [GCC_SDCC2_BCR] = { 0x24000 }, 3155 [GCC_SDCC4_BCR] = { 0x26000 }, 3156 [GCC_UFS_PHY_BCR] = { 0x87000 }, 3157 [GCC_USB30_PRIM_BCR] = { 0x49000 }, 3158 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 }, 3159 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 }, 3160 [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 }, 3161 [GCC_USB3_PHY_SEC_BCR] = { 0x6000c }, 3162 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 }, 3163 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 }, 3164 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 }, 3165 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x42018, 2 }, 3166 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x42020, 2 }, 3167 [GCC_VIDEO_BCR] = { 0x42000 }, 3168 }; 3169 3170 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3171 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3172 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3173 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3174 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3175 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3176 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3177 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 3178 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 3179 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3180 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3181 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 3182 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3183 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3184 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3185 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 3186 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 3187 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 3188 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 3189 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 3190 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 3191 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 3192 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src), 3193 }; 3194 3195 static struct gdsc *gcc_sm8450_gdscs[] = { 3196 [PCIE_0_GDSC] = &pcie_0_gdsc, 3197 [PCIE_1_GDSC] = &pcie_1_gdsc, 3198 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3199 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3200 }; 3201 3202 static const struct regmap_config gcc_sm8450_regmap_config = { 3203 .reg_bits = 32, 3204 .reg_stride = 4, 3205 .val_bits = 32, 3206 .max_register = 0x1f1030, 3207 .fast_io = true, 3208 }; 3209 3210 static const struct qcom_cc_desc gcc_sm8450_desc = { 3211 .config = &gcc_sm8450_regmap_config, 3212 .clks = gcc_sm8450_clocks, 3213 .num_clks = ARRAY_SIZE(gcc_sm8450_clocks), 3214 .resets = gcc_sm8450_resets, 3215 .num_resets = ARRAY_SIZE(gcc_sm8450_resets), 3216 .gdscs = gcc_sm8450_gdscs, 3217 .num_gdscs = ARRAY_SIZE(gcc_sm8450_gdscs), 3218 }; 3219 3220 static const struct of_device_id gcc_sm8450_match_table[] = { 3221 { .compatible = "qcom,gcc-sm8450" }, 3222 { } 3223 }; 3224 MODULE_DEVICE_TABLE(of, gcc_sm8450_match_table); 3225 3226 static int gcc_sm8450_probe(struct platform_device *pdev) 3227 { 3228 struct regmap *regmap; 3229 int ret; 3230 3231 regmap = qcom_cc_map(pdev, &gcc_sm8450_desc); 3232 if (IS_ERR(regmap)) 3233 return PTR_ERR(regmap); 3234 3235 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3236 ARRAY_SIZE(gcc_dfs_clocks)); 3237 if (ret) 3238 return ret; 3239 3240 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ 3241 regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14)); 3242 3243 /* 3244 * Keep the critical clock always-On 3245 * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk, 3246 * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, 3247 * gcc_video_xo_clk 3248 */ 3249 regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0)); 3250 regmap_update_bits(regmap, 0x36020, BIT(0), BIT(0)); 3251 regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0)); 3252 regmap_update_bits(regmap, 0x3701c, BIT(0), BIT(0)); 3253 regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0)); 3254 regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0)); 3255 regmap_update_bits(regmap, 0x42028, BIT(0), BIT(0)); 3256 3257 return qcom_cc_really_probe(pdev, &gcc_sm8450_desc, regmap); 3258 } 3259 3260 static struct platform_driver gcc_sm8450_driver = { 3261 .probe = gcc_sm8450_probe, 3262 .driver = { 3263 .name = "gcc-sm8450", 3264 .of_match_table = gcc_sm8450_match_table, 3265 }, 3266 }; 3267 3268 static int __init gcc_sm8450_init(void) 3269 { 3270 return platform_driver_register(&gcc_sm8450_driver); 3271 } 3272 subsys_initcall(gcc_sm8450_init); 3273 3274 static void __exit gcc_sm8450_exit(void) 3275 { 3276 platform_driver_unregister(&gcc_sm8450_driver); 3277 } 3278 module_exit(gcc_sm8450_exit); 3279 3280 MODULE_DESCRIPTION("QTI GCC SM8450 Driver"); 3281 MODULE_LICENSE("GPL v2"); 3282