1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/err.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of_device.h> 11 #include <linux/of.h> 12 #include <linux/regmap.h> 13 14 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 15 16 #include "clk-alpha-pll.h" 17 #include "clk-branch.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "clk-regmap-divider.h" 21 #include "common.h" 22 #include "gdsc.h" 23 #include "reset.h" 24 25 enum { 26 P_BI_TCXO, 27 P_AUD_REF_CLK, 28 P_GPLL0_OUT_EVEN, 29 P_GPLL0_OUT_MAIN, 30 P_GPLL4_OUT_MAIN, 31 P_GPLL9_OUT_MAIN, 32 P_SLEEP_CLK, 33 }; 34 35 static struct clk_alpha_pll gpll0 = { 36 .offset = 0x0, 37 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 38 .clkr = { 39 .enable_reg = 0x52018, 40 .enable_mask = BIT(0), 41 .hw.init = &(struct clk_init_data){ 42 .name = "gpll0", 43 .parent_data = &(const struct clk_parent_data){ 44 .fw_name = "bi_tcxo", 45 }, 46 .num_parents = 1, 47 .ops = &clk_alpha_pll_fixed_lucid_ops, 48 }, 49 }, 50 }; 51 52 static const struct clk_div_table post_div_table_gpll0_out_even[] = { 53 { 0x1, 2 }, 54 { } 55 }; 56 57 static struct clk_alpha_pll_postdiv gpll0_out_even = { 58 .offset = 0x0, 59 .post_div_shift = 8, 60 .post_div_table = post_div_table_gpll0_out_even, 61 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even), 62 .width = 4, 63 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 64 .clkr.hw.init = &(struct clk_init_data){ 65 .name = "gpll0_out_even", 66 .parent_hws = (const struct clk_hw*[]){ 67 &gpll0.clkr.hw, 68 }, 69 .num_parents = 1, 70 .ops = &clk_alpha_pll_postdiv_lucid_ops, 71 }, 72 }; 73 74 static struct clk_alpha_pll gpll4 = { 75 .offset = 0x76000, 76 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 77 .clkr = { 78 .enable_reg = 0x52018, 79 .enable_mask = BIT(4), 80 .hw.init = &(struct clk_init_data){ 81 .name = "gpll4", 82 .parent_data = &(const struct clk_parent_data){ 83 .fw_name = "bi_tcxo", 84 }, 85 .num_parents = 1, 86 .ops = &clk_alpha_pll_fixed_lucid_ops, 87 }, 88 }, 89 }; 90 91 static struct clk_alpha_pll gpll9 = { 92 .offset = 0x1c000, 93 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 94 .clkr = { 95 .enable_reg = 0x52018, 96 .enable_mask = BIT(9), 97 .hw.init = &(struct clk_init_data){ 98 .name = "gpll9", 99 .parent_data = &(const struct clk_parent_data){ 100 .fw_name = "bi_tcxo", 101 }, 102 .num_parents = 1, 103 .ops = &clk_alpha_pll_fixed_lucid_ops, 104 }, 105 }, 106 }; 107 108 static const struct parent_map gcc_parent_map_0[] = { 109 { P_BI_TCXO, 0 }, 110 { P_GPLL0_OUT_MAIN, 1 }, 111 { P_GPLL0_OUT_EVEN, 6 }, 112 }; 113 114 static const struct clk_parent_data gcc_parent_data_0[] = { 115 { .fw_name = "bi_tcxo" }, 116 { .hw = &gpll0.clkr.hw }, 117 { .hw = &gpll0_out_even.clkr.hw }, 118 }; 119 120 static const struct clk_parent_data gcc_parent_data_0_ao[] = { 121 { .fw_name = "bi_tcxo_ao" }, 122 { .hw = &gpll0.clkr.hw }, 123 { .hw = &gpll0_out_even.clkr.hw }, 124 }; 125 126 static const struct parent_map gcc_parent_map_1[] = { 127 { P_BI_TCXO, 0 }, 128 { P_GPLL0_OUT_MAIN, 1 }, 129 { P_SLEEP_CLK, 5 }, 130 { P_GPLL0_OUT_EVEN, 6 }, 131 }; 132 133 static const struct clk_parent_data gcc_parent_data_1[] = { 134 { .fw_name = "bi_tcxo" }, 135 { .hw = &gpll0.clkr.hw }, 136 { .fw_name = "sleep_clk" }, 137 { .hw = &gpll0_out_even.clkr.hw }, 138 }; 139 140 static const struct parent_map gcc_parent_map_2[] = { 141 { P_BI_TCXO, 0 }, 142 { P_SLEEP_CLK, 5 }, 143 }; 144 145 static const struct clk_parent_data gcc_parent_data_2[] = { 146 { .fw_name = "bi_tcxo" }, 147 { .fw_name = "sleep_clk" }, 148 }; 149 150 static const struct parent_map gcc_parent_map_3[] = { 151 { P_BI_TCXO, 0 }, 152 }; 153 154 static const struct clk_parent_data gcc_parent_data_3[] = { 155 { .fw_name = "bi_tcxo" }, 156 }; 157 158 static const struct parent_map gcc_parent_map_4[] = { 159 { P_BI_TCXO, 0 }, 160 { P_GPLL0_OUT_MAIN, 1 }, 161 { P_GPLL9_OUT_MAIN, 2 }, 162 { P_GPLL4_OUT_MAIN, 5 }, 163 { P_GPLL0_OUT_EVEN, 6 }, 164 }; 165 166 static const struct clk_parent_data gcc_parent_data_4[] = { 167 { .fw_name = "bi_tcxo" }, 168 { .hw = &gpll0.clkr.hw }, 169 { .hw = &gpll9.clkr.hw }, 170 { .hw = &gpll4.clkr.hw }, 171 { .hw = &gpll0_out_even.clkr.hw }, 172 }; 173 174 static const struct parent_map gcc_parent_map_5[] = { 175 { P_BI_TCXO, 0 }, 176 { P_GPLL0_OUT_MAIN, 1 }, 177 { P_AUD_REF_CLK, 2 }, 178 { P_GPLL0_OUT_EVEN, 6 }, 179 }; 180 181 static const struct clk_parent_data gcc_parent_data_5[] = { 182 { .fw_name = "bi_tcxo" }, 183 { .hw = &gpll0.clkr.hw }, 184 { .fw_name = "aud_ref_clk" }, 185 { .hw = &gpll0_out_even.clkr.hw }, 186 }; 187 188 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { 189 F(19200000, P_BI_TCXO, 1, 0, 0), 190 { } 191 }; 192 193 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 194 .cmd_rcgr = 0x48010, 195 .mnd_width = 0, 196 .hid_width = 5, 197 .parent_map = gcc_parent_map_0, 198 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, 199 .clkr.hw.init = &(struct clk_init_data){ 200 .name = "gcc_cpuss_ahb_clk_src", 201 .parent_data = gcc_parent_data_0_ao, 202 .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao), 203 .flags = CLK_SET_RATE_PARENT, 204 .ops = &clk_rcg2_ops, 205 }, 206 }; 207 208 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 209 F(19200000, P_BI_TCXO, 1, 0, 0), 210 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 211 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 212 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 213 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 214 { } 215 }; 216 217 static struct clk_rcg2 gcc_gp1_clk_src = { 218 .cmd_rcgr = 0x64004, 219 .mnd_width = 8, 220 .hid_width = 5, 221 .parent_map = gcc_parent_map_1, 222 .freq_tbl = ftbl_gcc_gp1_clk_src, 223 .clkr.hw.init = &(struct clk_init_data){ 224 .name = "gcc_gp1_clk_src", 225 .parent_data = gcc_parent_data_1, 226 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 227 .ops = &clk_rcg2_ops, 228 }, 229 }; 230 231 static struct clk_rcg2 gcc_gp2_clk_src = { 232 .cmd_rcgr = 0x65004, 233 .mnd_width = 8, 234 .hid_width = 5, 235 .parent_map = gcc_parent_map_1, 236 .freq_tbl = ftbl_gcc_gp1_clk_src, 237 .clkr.hw.init = &(struct clk_init_data){ 238 .name = "gcc_gp2_clk_src", 239 .parent_data = gcc_parent_data_1, 240 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 241 .ops = &clk_rcg2_ops, 242 }, 243 }; 244 245 static struct clk_rcg2 gcc_gp3_clk_src = { 246 .cmd_rcgr = 0x66004, 247 .mnd_width = 8, 248 .hid_width = 5, 249 .parent_map = gcc_parent_map_1, 250 .freq_tbl = ftbl_gcc_gp1_clk_src, 251 .clkr.hw.init = &(struct clk_init_data){ 252 .name = "gcc_gp3_clk_src", 253 .parent_data = gcc_parent_data_1, 254 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 255 .ops = &clk_rcg2_ops, 256 }, 257 }; 258 259 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 260 F(9600000, P_BI_TCXO, 2, 0, 0), 261 F(19200000, P_BI_TCXO, 1, 0, 0), 262 { } 263 }; 264 265 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 266 .cmd_rcgr = 0x6b038, 267 .mnd_width = 16, 268 .hid_width = 5, 269 .parent_map = gcc_parent_map_2, 270 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 271 .clkr.hw.init = &(struct clk_init_data){ 272 .name = "gcc_pcie_0_aux_clk_src", 273 .parent_data = gcc_parent_data_2, 274 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 275 .ops = &clk_rcg2_ops, 276 }, 277 }; 278 279 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 280 .cmd_rcgr = 0x8d038, 281 .mnd_width = 16, 282 .hid_width = 5, 283 .parent_map = gcc_parent_map_2, 284 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 285 .clkr.hw.init = &(struct clk_init_data){ 286 .name = "gcc_pcie_1_aux_clk_src", 287 .parent_data = gcc_parent_data_2, 288 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 289 .ops = &clk_rcg2_ops, 290 }, 291 }; 292 293 static struct clk_rcg2 gcc_pcie_2_aux_clk_src = { 294 .cmd_rcgr = 0x6038, 295 .mnd_width = 16, 296 .hid_width = 5, 297 .parent_map = gcc_parent_map_2, 298 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 299 .clkr.hw.init = &(struct clk_init_data){ 300 .name = "gcc_pcie_2_aux_clk_src", 301 .parent_data = gcc_parent_data_2, 302 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 303 .ops = &clk_rcg2_ops, 304 }, 305 }; 306 307 static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { 308 F(19200000, P_BI_TCXO, 1, 0, 0), 309 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 310 { } 311 }; 312 313 static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { 314 .cmd_rcgr = 0x6f014, 315 .mnd_width = 0, 316 .hid_width = 5, 317 .parent_map = gcc_parent_map_0, 318 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, 319 .clkr.hw.init = &(struct clk_init_data){ 320 .name = "gcc_pcie_phy_refgen_clk_src", 321 .parent_data = gcc_parent_data_0_ao, 322 .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao), 323 .ops = &clk_rcg2_ops, 324 }, 325 }; 326 327 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 328 F(9600000, P_BI_TCXO, 2, 0, 0), 329 F(19200000, P_BI_TCXO, 1, 0, 0), 330 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 331 { } 332 }; 333 334 static struct clk_rcg2 gcc_pdm2_clk_src = { 335 .cmd_rcgr = 0x33010, 336 .mnd_width = 0, 337 .hid_width = 5, 338 .parent_map = gcc_parent_map_0, 339 .freq_tbl = ftbl_gcc_pdm2_clk_src, 340 .clkr.hw.init = &(struct clk_init_data){ 341 .name = "gcc_pdm2_clk_src", 342 .parent_data = gcc_parent_data_0, 343 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 344 .ops = &clk_rcg2_ops, 345 }, 346 }; 347 348 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 349 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 350 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 351 F(19200000, P_BI_TCXO, 1, 0, 0), 352 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 353 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 354 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 355 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 356 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 357 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 358 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 359 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 360 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 361 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), 362 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), 363 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), 364 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), 365 { } 366 }; 367 368 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 369 .name = "gcc_qupv3_wrap0_s0_clk_src", 370 .parent_data = gcc_parent_data_0, 371 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 372 .ops = &clk_rcg2_ops, 373 }; 374 375 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 376 .cmd_rcgr = 0x17010, 377 .mnd_width = 16, 378 .hid_width = 5, 379 .parent_map = gcc_parent_map_0, 380 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 381 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 382 }; 383 384 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 385 .name = "gcc_qupv3_wrap0_s1_clk_src", 386 .parent_data = gcc_parent_data_0, 387 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 388 .ops = &clk_rcg2_ops, 389 }; 390 391 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 392 .cmd_rcgr = 0x17140, 393 .mnd_width = 16, 394 .hid_width = 5, 395 .parent_map = gcc_parent_map_0, 396 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 397 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 398 }; 399 400 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = { 401 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 402 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 403 F(19200000, P_BI_TCXO, 1, 0, 0), 404 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 405 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 406 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 407 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 408 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 409 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 410 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 411 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 412 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 413 { } 414 }; 415 416 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 417 .name = "gcc_qupv3_wrap0_s2_clk_src", 418 .parent_data = gcc_parent_data_0, 419 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 420 .ops = &clk_rcg2_ops, 421 }; 422 423 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 424 .cmd_rcgr = 0x17270, 425 .mnd_width = 16, 426 .hid_width = 5, 427 .parent_map = gcc_parent_map_0, 428 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 429 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 430 }; 431 432 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 433 .name = "gcc_qupv3_wrap0_s3_clk_src", 434 .parent_data = gcc_parent_data_0, 435 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 436 .ops = &clk_rcg2_ops, 437 }; 438 439 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 440 .cmd_rcgr = 0x173a0, 441 .mnd_width = 16, 442 .hid_width = 5, 443 .parent_map = gcc_parent_map_0, 444 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 445 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 446 }; 447 448 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 449 .name = "gcc_qupv3_wrap0_s4_clk_src", 450 .parent_data = gcc_parent_data_0, 451 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 452 .ops = &clk_rcg2_ops, 453 }; 454 455 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 456 .cmd_rcgr = 0x174d0, 457 .mnd_width = 16, 458 .hid_width = 5, 459 .parent_map = gcc_parent_map_0, 460 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 461 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 462 }; 463 464 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 465 .name = "gcc_qupv3_wrap0_s5_clk_src", 466 .parent_data = gcc_parent_data_0, 467 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 468 .ops = &clk_rcg2_ops, 469 }; 470 471 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 472 .cmd_rcgr = 0x17600, 473 .mnd_width = 16, 474 .hid_width = 5, 475 .parent_map = gcc_parent_map_0, 476 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 477 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 478 }; 479 480 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 481 .name = "gcc_qupv3_wrap0_s6_clk_src", 482 .parent_data = gcc_parent_data_0, 483 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 484 .ops = &clk_rcg2_ops, 485 }; 486 487 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 488 .cmd_rcgr = 0x17730, 489 .mnd_width = 16, 490 .hid_width = 5, 491 .parent_map = gcc_parent_map_0, 492 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 493 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 494 }; 495 496 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 497 .name = "gcc_qupv3_wrap0_s7_clk_src", 498 .parent_data = gcc_parent_data_0, 499 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 500 .ops = &clk_rcg2_ops, 501 }; 502 503 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 504 .cmd_rcgr = 0x17860, 505 .mnd_width = 16, 506 .hid_width = 5, 507 .parent_map = gcc_parent_map_0, 508 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 509 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 510 }; 511 512 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 513 .name = "gcc_qupv3_wrap1_s0_clk_src", 514 .parent_data = gcc_parent_data_0, 515 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 516 .ops = &clk_rcg2_ops, 517 }; 518 519 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 520 .cmd_rcgr = 0x18010, 521 .mnd_width = 16, 522 .hid_width = 5, 523 .parent_map = gcc_parent_map_0, 524 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 525 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 526 }; 527 528 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 529 .name = "gcc_qupv3_wrap1_s1_clk_src", 530 .parent_data = gcc_parent_data_0, 531 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 532 .ops = &clk_rcg2_ops, 533 }; 534 535 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 536 .cmd_rcgr = 0x18140, 537 .mnd_width = 16, 538 .hid_width = 5, 539 .parent_map = gcc_parent_map_0, 540 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 541 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 542 }; 543 544 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 545 .name = "gcc_qupv3_wrap1_s2_clk_src", 546 .parent_data = gcc_parent_data_0, 547 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 548 .ops = &clk_rcg2_ops, 549 }; 550 551 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 552 .cmd_rcgr = 0x18270, 553 .mnd_width = 16, 554 .hid_width = 5, 555 .parent_map = gcc_parent_map_0, 556 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 557 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 558 }; 559 560 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 561 .name = "gcc_qupv3_wrap1_s3_clk_src", 562 .parent_data = gcc_parent_data_0, 563 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 564 .ops = &clk_rcg2_ops, 565 }; 566 567 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 568 .cmd_rcgr = 0x183a0, 569 .mnd_width = 16, 570 .hid_width = 5, 571 .parent_map = gcc_parent_map_0, 572 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 573 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 574 }; 575 576 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 577 .name = "gcc_qupv3_wrap1_s4_clk_src", 578 .parent_data = gcc_parent_data_0, 579 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 580 .ops = &clk_rcg2_ops, 581 }; 582 583 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 584 .cmd_rcgr = 0x184d0, 585 .mnd_width = 16, 586 .hid_width = 5, 587 .parent_map = gcc_parent_map_0, 588 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 589 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 590 }; 591 592 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 593 .name = "gcc_qupv3_wrap1_s5_clk_src", 594 .parent_data = gcc_parent_data_0, 595 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 596 .ops = &clk_rcg2_ops, 597 }; 598 599 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 600 .cmd_rcgr = 0x18600, 601 .mnd_width = 16, 602 .hid_width = 5, 603 .parent_map = gcc_parent_map_0, 604 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 605 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 606 }; 607 608 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 609 .name = "gcc_qupv3_wrap2_s0_clk_src", 610 .parent_data = gcc_parent_data_0, 611 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 612 .ops = &clk_rcg2_ops, 613 }; 614 615 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 616 .cmd_rcgr = 0x1e010, 617 .mnd_width = 16, 618 .hid_width = 5, 619 .parent_map = gcc_parent_map_0, 620 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 621 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 622 }; 623 624 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 625 .name = "gcc_qupv3_wrap2_s1_clk_src", 626 .parent_data = gcc_parent_data_0, 627 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 628 .ops = &clk_rcg2_ops, 629 }; 630 631 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 632 .cmd_rcgr = 0x1e140, 633 .mnd_width = 16, 634 .hid_width = 5, 635 .parent_map = gcc_parent_map_0, 636 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 637 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 638 }; 639 640 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 641 .name = "gcc_qupv3_wrap2_s2_clk_src", 642 .parent_data = gcc_parent_data_0, 643 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 644 .ops = &clk_rcg2_ops, 645 }; 646 647 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 648 .cmd_rcgr = 0x1e270, 649 .mnd_width = 16, 650 .hid_width = 5, 651 .parent_map = gcc_parent_map_0, 652 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 653 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 654 }; 655 656 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 657 .name = "gcc_qupv3_wrap2_s3_clk_src", 658 .parent_data = gcc_parent_data_0, 659 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 660 .ops = &clk_rcg2_ops, 661 }; 662 663 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 664 .cmd_rcgr = 0x1e3a0, 665 .mnd_width = 16, 666 .hid_width = 5, 667 .parent_map = gcc_parent_map_0, 668 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 669 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 670 }; 671 672 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 673 .name = "gcc_qupv3_wrap2_s4_clk_src", 674 .parent_data = gcc_parent_data_0, 675 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 676 .ops = &clk_rcg2_ops, 677 }; 678 679 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 680 .cmd_rcgr = 0x1e4d0, 681 .mnd_width = 16, 682 .hid_width = 5, 683 .parent_map = gcc_parent_map_0, 684 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 685 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 686 }; 687 688 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 689 .name = "gcc_qupv3_wrap2_s5_clk_src", 690 .parent_data = gcc_parent_data_0, 691 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 692 .ops = &clk_rcg2_ops, 693 }; 694 695 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 696 .cmd_rcgr = 0x1e600, 697 .mnd_width = 16, 698 .hid_width = 5, 699 .parent_map = gcc_parent_map_0, 700 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 701 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 702 }; 703 704 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 705 F(400000, P_BI_TCXO, 12, 1, 4), 706 F(19200000, P_BI_TCXO, 1, 0, 0), 707 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 708 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 709 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 710 F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0), 711 { } 712 }; 713 714 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 715 .cmd_rcgr = 0x1400c, 716 .mnd_width = 8, 717 .hid_width = 5, 718 .parent_map = gcc_parent_map_4, 719 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 720 .clkr.hw.init = &(struct clk_init_data){ 721 .name = "gcc_sdcc2_apps_clk_src", 722 .parent_data = gcc_parent_data_4, 723 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 724 .ops = &clk_rcg2_floor_ops, 725 }, 726 }; 727 728 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 729 F(400000, P_BI_TCXO, 12, 1, 4), 730 F(19200000, P_BI_TCXO, 1, 0, 0), 731 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 732 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 733 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 734 { } 735 }; 736 737 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 738 .cmd_rcgr = 0x1600c, 739 .mnd_width = 8, 740 .hid_width = 5, 741 .parent_map = gcc_parent_map_0, 742 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 743 .clkr.hw.init = &(struct clk_init_data){ 744 .name = "gcc_sdcc4_apps_clk_src", 745 .parent_data = gcc_parent_data_0, 746 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 747 .ops = &clk_rcg2_floor_ops, 748 }, 749 }; 750 751 static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { 752 F(105495, P_BI_TCXO, 2, 1, 91), 753 { } 754 }; 755 756 static struct clk_rcg2 gcc_tsif_ref_clk_src = { 757 .cmd_rcgr = 0x36010, 758 .mnd_width = 8, 759 .hid_width = 5, 760 .parent_map = gcc_parent_map_5, 761 .freq_tbl = ftbl_gcc_tsif_ref_clk_src, 762 .clkr.hw.init = &(struct clk_init_data){ 763 .name = "gcc_tsif_ref_clk_src", 764 .parent_data = gcc_parent_data_5, 765 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 766 .ops = &clk_rcg2_ops, 767 }, 768 }; 769 770 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { 771 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 772 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 773 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 774 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 775 { } 776 }; 777 778 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { 779 .cmd_rcgr = 0x75024, 780 .mnd_width = 8, 781 .hid_width = 5, 782 .parent_map = gcc_parent_map_0, 783 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, 784 .clkr.hw.init = &(struct clk_init_data){ 785 .name = "gcc_ufs_card_axi_clk_src", 786 .parent_data = gcc_parent_data_0, 787 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 788 .ops = &clk_rcg2_ops, 789 }, 790 }; 791 792 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { 793 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 794 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 795 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 796 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 797 { } 798 }; 799 800 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { 801 .cmd_rcgr = 0x7506c, 802 .mnd_width = 0, 803 .hid_width = 5, 804 .parent_map = gcc_parent_map_0, 805 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 806 .clkr.hw.init = &(struct clk_init_data){ 807 .name = "gcc_ufs_card_ice_core_clk_src", 808 .parent_data = gcc_parent_data_0, 809 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 810 .ops = &clk_rcg2_ops, 811 }, 812 }; 813 814 static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = { 815 F(19200000, P_BI_TCXO, 1, 0, 0), 816 { } 817 }; 818 819 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { 820 .cmd_rcgr = 0x750a0, 821 .mnd_width = 0, 822 .hid_width = 5, 823 .parent_map = gcc_parent_map_3, 824 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 825 .clkr.hw.init = &(struct clk_init_data){ 826 .name = "gcc_ufs_card_phy_aux_clk_src", 827 .parent_data = gcc_parent_data_3, 828 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 829 .ops = &clk_rcg2_ops, 830 }, 831 }; 832 833 static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { 834 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 835 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 836 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 837 { } 838 }; 839 840 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { 841 .cmd_rcgr = 0x75084, 842 .mnd_width = 0, 843 .hid_width = 5, 844 .parent_map = gcc_parent_map_0, 845 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, 846 .clkr.hw.init = &(struct clk_init_data){ 847 .name = "gcc_ufs_card_unipro_core_clk_src", 848 .parent_data = gcc_parent_data_0, 849 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 850 .ops = &clk_rcg2_ops, 851 }, 852 }; 853 854 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 855 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 856 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 857 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 858 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 859 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 860 { } 861 }; 862 863 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 864 .cmd_rcgr = 0x77024, 865 .mnd_width = 8, 866 .hid_width = 5, 867 .parent_map = gcc_parent_map_0, 868 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 869 .clkr.hw.init = &(struct clk_init_data){ 870 .name = "gcc_ufs_phy_axi_clk_src", 871 .parent_data = gcc_parent_data_0, 872 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 873 .ops = &clk_rcg2_ops, 874 }, 875 }; 876 877 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 878 .cmd_rcgr = 0x7706c, 879 .mnd_width = 0, 880 .hid_width = 5, 881 .parent_map = gcc_parent_map_0, 882 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 883 .clkr.hw.init = &(struct clk_init_data){ 884 .name = "gcc_ufs_phy_ice_core_clk_src", 885 .parent_data = gcc_parent_data_0, 886 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 887 .ops = &clk_rcg2_ops, 888 }, 889 }; 890 891 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 892 .cmd_rcgr = 0x770a0, 893 .mnd_width = 0, 894 .hid_width = 5, 895 .parent_map = gcc_parent_map_3, 896 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 897 .clkr.hw.init = &(struct clk_init_data){ 898 .name = "gcc_ufs_phy_phy_aux_clk_src", 899 .parent_data = gcc_parent_data_3, 900 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 901 .ops = &clk_rcg2_ops, 902 }, 903 }; 904 905 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 906 .cmd_rcgr = 0x77084, 907 .mnd_width = 0, 908 .hid_width = 5, 909 .parent_map = gcc_parent_map_0, 910 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 911 .clkr.hw.init = &(struct clk_init_data){ 912 .name = "gcc_ufs_phy_unipro_core_clk_src", 913 .parent_data = gcc_parent_data_0, 914 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 915 .ops = &clk_rcg2_ops, 916 }, 917 }; 918 919 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 920 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), 921 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), 922 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 923 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 924 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 925 { } 926 }; 927 928 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 929 .cmd_rcgr = 0xf020, 930 .mnd_width = 8, 931 .hid_width = 5, 932 .parent_map = gcc_parent_map_0, 933 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 934 .clkr.hw.init = &(struct clk_init_data){ 935 .name = "gcc_usb30_prim_master_clk_src", 936 .parent_data = gcc_parent_data_0, 937 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 938 .ops = &clk_rcg2_ops, 939 }, 940 }; 941 942 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 943 .cmd_rcgr = 0xf038, 944 .mnd_width = 0, 945 .hid_width = 5, 946 .parent_map = gcc_parent_map_0, 947 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 948 .clkr.hw.init = &(struct clk_init_data){ 949 .name = "gcc_usb30_prim_mock_utmi_clk_src", 950 .parent_data = gcc_parent_data_0, 951 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 952 .ops = &clk_rcg2_ops, 953 }, 954 }; 955 956 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { 957 .cmd_rcgr = 0x10020, 958 .mnd_width = 8, 959 .hid_width = 5, 960 .parent_map = gcc_parent_map_0, 961 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 962 .clkr.hw.init = &(struct clk_init_data){ 963 .name = "gcc_usb30_sec_master_clk_src", 964 .parent_data = gcc_parent_data_0, 965 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 966 .ops = &clk_rcg2_ops, 967 }, 968 }; 969 970 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { 971 .cmd_rcgr = 0x10038, 972 .mnd_width = 0, 973 .hid_width = 5, 974 .parent_map = gcc_parent_map_0, 975 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 976 .clkr.hw.init = &(struct clk_init_data){ 977 .name = "gcc_usb30_sec_mock_utmi_clk_src", 978 .parent_data = gcc_parent_data_0, 979 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 980 .ops = &clk_rcg2_ops, 981 }, 982 }; 983 984 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 985 .cmd_rcgr = 0xf064, 986 .mnd_width = 0, 987 .hid_width = 5, 988 .parent_map = gcc_parent_map_2, 989 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 990 .clkr.hw.init = &(struct clk_init_data){ 991 .name = "gcc_usb3_prim_phy_aux_clk_src", 992 .parent_data = gcc_parent_data_2, 993 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 994 .ops = &clk_rcg2_ops, 995 }, 996 }; 997 998 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { 999 .cmd_rcgr = 0x10064, 1000 .mnd_width = 0, 1001 .hid_width = 5, 1002 .parent_map = gcc_parent_map_2, 1003 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 1004 .clkr.hw.init = &(struct clk_init_data){ 1005 .name = "gcc_usb3_sec_phy_aux_clk_src", 1006 .parent_data = gcc_parent_data_2, 1007 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1008 .ops = &clk_rcg2_ops, 1009 }, 1010 }; 1011 1012 static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = { 1013 .reg = 0x48028, 1014 .shift = 0, 1015 .width = 4, 1016 .clkr.hw.init = &(struct clk_init_data) { 1017 .name = "gcc_cpuss_ahb_postdiv_clk_src", 1018 .parent_hws = (const struct clk_hw*[]){ 1019 &gcc_cpuss_ahb_clk_src.clkr.hw, 1020 }, 1021 .num_parents = 1, 1022 .flags = CLK_SET_RATE_PARENT, 1023 .ops = &clk_regmap_div_ro_ops, 1024 }, 1025 }; 1026 1027 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1028 .reg = 0xf050, 1029 .shift = 0, 1030 .width = 2, 1031 .clkr.hw.init = &(struct clk_init_data) { 1032 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1033 .parent_hws = (const struct clk_hw*[]){ 1034 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1035 }, 1036 .num_parents = 1, 1037 .flags = CLK_SET_RATE_PARENT, 1038 .ops = &clk_regmap_div_ro_ops, 1039 }, 1040 }; 1041 1042 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = { 1043 .reg = 0x10050, 1044 .shift = 0, 1045 .width = 2, 1046 .clkr.hw.init = &(struct clk_init_data) { 1047 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src", 1048 .parent_hws = (const struct clk_hw*[]){ 1049 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, 1050 }, 1051 .num_parents = 1, 1052 .flags = CLK_SET_RATE_PARENT, 1053 .ops = &clk_regmap_div_ro_ops, 1054 }, 1055 }; 1056 1057 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { 1058 .halt_reg = 0x9000c, 1059 .halt_check = BRANCH_HALT_VOTED, 1060 .clkr = { 1061 .enable_reg = 0x9000c, 1062 .enable_mask = BIT(0), 1063 .hw.init = &(struct clk_init_data){ 1064 .name = "gcc_aggre_noc_pcie_tbu_clk", 1065 .ops = &clk_branch2_ops, 1066 }, 1067 }, 1068 }; 1069 1070 static struct clk_branch gcc_aggre_ufs_card_axi_clk = { 1071 .halt_reg = 0x750cc, 1072 .halt_check = BRANCH_HALT_VOTED, 1073 .hwcg_reg = 0x750cc, 1074 .hwcg_bit = 1, 1075 .clkr = { 1076 .enable_reg = 0x750cc, 1077 .enable_mask = BIT(0), 1078 .hw.init = &(struct clk_init_data){ 1079 .name = "gcc_aggre_ufs_card_axi_clk", 1080 .parent_hws = (const struct clk_hw*[]){ 1081 &gcc_ufs_card_axi_clk_src.clkr.hw, 1082 }, 1083 .num_parents = 1, 1084 .flags = CLK_SET_RATE_PARENT, 1085 .ops = &clk_branch2_ops, 1086 }, 1087 }, 1088 }; 1089 1090 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1091 .halt_reg = 0x770cc, 1092 .halt_check = BRANCH_HALT_VOTED, 1093 .hwcg_reg = 0x770cc, 1094 .hwcg_bit = 1, 1095 .clkr = { 1096 .enable_reg = 0x770cc, 1097 .enable_mask = BIT(0), 1098 .hw.init = &(struct clk_init_data){ 1099 .name = "gcc_aggre_ufs_phy_axi_clk", 1100 .parent_hws = (const struct clk_hw*[]){ 1101 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1102 }, 1103 .num_parents = 1, 1104 .flags = CLK_SET_RATE_PARENT, 1105 .ops = &clk_branch2_ops, 1106 }, 1107 }, 1108 }; 1109 1110 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1111 .halt_reg = 0xf080, 1112 .halt_check = BRANCH_HALT_VOTED, 1113 .clkr = { 1114 .enable_reg = 0xf080, 1115 .enable_mask = BIT(0), 1116 .hw.init = &(struct clk_init_data){ 1117 .name = "gcc_aggre_usb3_prim_axi_clk", 1118 .parent_hws = (const struct clk_hw*[]){ 1119 &gcc_usb30_prim_master_clk_src.clkr.hw, 1120 }, 1121 .num_parents = 1, 1122 .flags = CLK_SET_RATE_PARENT, 1123 .ops = &clk_branch2_ops, 1124 }, 1125 }, 1126 }; 1127 1128 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { 1129 .halt_reg = 0x10080, 1130 .halt_check = BRANCH_HALT_VOTED, 1131 .clkr = { 1132 .enable_reg = 0x10080, 1133 .enable_mask = BIT(0), 1134 .hw.init = &(struct clk_init_data){ 1135 .name = "gcc_aggre_usb3_sec_axi_clk", 1136 .parent_hws = (const struct clk_hw*[]){ 1137 &gcc_usb30_sec_master_clk_src.clkr.hw, 1138 }, 1139 .num_parents = 1, 1140 .flags = CLK_SET_RATE_PARENT, 1141 .ops = &clk_branch2_ops, 1142 }, 1143 }, 1144 }; 1145 1146 static struct clk_branch gcc_boot_rom_ahb_clk = { 1147 .halt_reg = 0x38004, 1148 .halt_check = BRANCH_HALT_VOTED, 1149 .hwcg_reg = 0x38004, 1150 .hwcg_bit = 1, 1151 .clkr = { 1152 .enable_reg = 0x52000, 1153 .enable_mask = BIT(10), 1154 .hw.init = &(struct clk_init_data){ 1155 .name = "gcc_boot_rom_ahb_clk", 1156 .ops = &clk_branch2_ops, 1157 }, 1158 }, 1159 }; 1160 1161 static struct clk_branch gcc_camera_hf_axi_clk = { 1162 .halt_reg = 0xb02c, 1163 .halt_check = BRANCH_HALT_VOTED, 1164 .clkr = { 1165 .enable_reg = 0xb02c, 1166 .enable_mask = BIT(0), 1167 .hw.init = &(struct clk_init_data){ 1168 .name = "gcc_camera_hf_axi_clk", 1169 .ops = &clk_branch2_ops, 1170 }, 1171 }, 1172 }; 1173 1174 static struct clk_branch gcc_camera_sf_axi_clk = { 1175 .halt_reg = 0xb030, 1176 .halt_check = BRANCH_HALT_VOTED, 1177 .clkr = { 1178 .enable_reg = 0xb030, 1179 .enable_mask = BIT(0), 1180 .hw.init = &(struct clk_init_data){ 1181 .name = "gcc_camera_sf_axi_clk", 1182 .ops = &clk_branch2_ops, 1183 }, 1184 }, 1185 }; 1186 1187 static struct clk_branch gcc_camera_xo_clk = { 1188 .halt_reg = 0xb040, 1189 .halt_check = BRANCH_HALT, 1190 .clkr = { 1191 .enable_reg = 0xb040, 1192 .enable_mask = BIT(0), 1193 .hw.init = &(struct clk_init_data){ 1194 .name = "gcc_camera_xo_clk", 1195 .ops = &clk_branch2_ops, 1196 }, 1197 }, 1198 }; 1199 1200 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1201 .halt_reg = 0xf07c, 1202 .halt_check = BRANCH_HALT_VOTED, 1203 .clkr = { 1204 .enable_reg = 0xf07c, 1205 .enable_mask = BIT(0), 1206 .hw.init = &(struct clk_init_data){ 1207 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1208 .parent_hws = (const struct clk_hw*[]){ 1209 &gcc_usb30_prim_master_clk_src.clkr.hw, 1210 }, 1211 .num_parents = 1, 1212 .flags = CLK_SET_RATE_PARENT, 1213 .ops = &clk_branch2_ops, 1214 }, 1215 }, 1216 }; 1217 1218 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { 1219 .halt_reg = 0x1007c, 1220 .halt_check = BRANCH_HALT_VOTED, 1221 .clkr = { 1222 .enable_reg = 0x1007c, 1223 .enable_mask = BIT(0), 1224 .hw.init = &(struct clk_init_data){ 1225 .name = "gcc_cfg_noc_usb3_sec_axi_clk", 1226 .parent_hws = (const struct clk_hw*[]){ 1227 &gcc_usb30_sec_master_clk_src.clkr.hw, 1228 }, 1229 .num_parents = 1, 1230 .flags = CLK_SET_RATE_PARENT, 1231 .ops = &clk_branch2_ops, 1232 }, 1233 }, 1234 }; 1235 1236 static struct clk_branch gcc_cpuss_ahb_clk = { 1237 .halt_reg = 0x48000, 1238 .halt_check = BRANCH_HALT_VOTED, 1239 .clkr = { 1240 .enable_reg = 0x52000, 1241 .enable_mask = BIT(21), 1242 .hw.init = &(struct clk_init_data){ 1243 .name = "gcc_cpuss_ahb_clk", 1244 .parent_hws = (const struct clk_hw*[]){ 1245 &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, 1246 }, 1247 .num_parents = 1, 1248 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 1249 .ops = &clk_branch2_ops, 1250 }, 1251 }, 1252 }; 1253 1254 static struct clk_branch gcc_cpuss_rbcpr_clk = { 1255 .halt_reg = 0x48004, 1256 .halt_check = BRANCH_HALT, 1257 .clkr = { 1258 .enable_reg = 0x48004, 1259 .enable_mask = BIT(0), 1260 .hw.init = &(struct clk_init_data){ 1261 .name = "gcc_cpuss_rbcpr_clk", 1262 .ops = &clk_branch2_ops, 1263 }, 1264 }, 1265 }; 1266 1267 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1268 .halt_reg = 0x71154, 1269 .halt_check = BRANCH_HALT_VOTED, 1270 .clkr = { 1271 .enable_reg = 0x71154, 1272 .enable_mask = BIT(0), 1273 .hw.init = &(struct clk_init_data){ 1274 .name = "gcc_ddrss_gpu_axi_clk", 1275 .ops = &clk_branch2_ops, 1276 }, 1277 }, 1278 }; 1279 1280 static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = { 1281 .halt_reg = 0x8d058, 1282 .halt_check = BRANCH_HALT_VOTED, 1283 .clkr = { 1284 .enable_reg = 0x8d058, 1285 .enable_mask = BIT(0), 1286 .hw.init = &(struct clk_init_data){ 1287 .name = "gcc_ddrss_pcie_sf_tbu_clk", 1288 .ops = &clk_branch2_ops, 1289 }, 1290 }, 1291 }; 1292 1293 static struct clk_branch gcc_disp_hf_axi_clk = { 1294 .halt_reg = 0xb034, 1295 .halt_check = BRANCH_HALT_VOTED, 1296 .clkr = { 1297 .enable_reg = 0xb034, 1298 .enable_mask = BIT(0), 1299 .hw.init = &(struct clk_init_data){ 1300 .name = "gcc_disp_hf_axi_clk", 1301 .ops = &clk_branch2_ops, 1302 }, 1303 }, 1304 }; 1305 1306 static struct clk_branch gcc_disp_sf_axi_clk = { 1307 .halt_reg = 0xb038, 1308 .halt_check = BRANCH_HALT_VOTED, 1309 .clkr = { 1310 .enable_reg = 0xb038, 1311 .enable_mask = BIT(0), 1312 .hw.init = &(struct clk_init_data){ 1313 .name = "gcc_disp_sf_axi_clk", 1314 .ops = &clk_branch2_ops, 1315 }, 1316 }, 1317 }; 1318 1319 static struct clk_branch gcc_disp_xo_clk = { 1320 .halt_reg = 0xb044, 1321 .halt_check = BRANCH_HALT, 1322 .clkr = { 1323 .enable_reg = 0xb044, 1324 .enable_mask = BIT(0), 1325 .hw.init = &(struct clk_init_data){ 1326 .name = "gcc_disp_xo_clk", 1327 .ops = &clk_branch2_ops, 1328 }, 1329 }, 1330 }; 1331 1332 static struct clk_branch gcc_gp1_clk = { 1333 .halt_reg = 0x64000, 1334 .halt_check = BRANCH_HALT, 1335 .clkr = { 1336 .enable_reg = 0x64000, 1337 .enable_mask = BIT(0), 1338 .hw.init = &(struct clk_init_data){ 1339 .name = "gcc_gp1_clk", 1340 .parent_hws = (const struct clk_hw*[]){ 1341 &gcc_gp1_clk_src.clkr.hw, 1342 }, 1343 .num_parents = 1, 1344 .flags = CLK_SET_RATE_PARENT, 1345 .ops = &clk_branch2_ops, 1346 }, 1347 }, 1348 }; 1349 1350 static struct clk_branch gcc_gp2_clk = { 1351 .halt_reg = 0x65000, 1352 .halt_check = BRANCH_HALT, 1353 .clkr = { 1354 .enable_reg = 0x65000, 1355 .enable_mask = BIT(0), 1356 .hw.init = &(struct clk_init_data){ 1357 .name = "gcc_gp2_clk", 1358 .parent_hws = (const struct clk_hw*[]){ 1359 &gcc_gp2_clk_src.clkr.hw, 1360 }, 1361 .num_parents = 1, 1362 .flags = CLK_SET_RATE_PARENT, 1363 .ops = &clk_branch2_ops, 1364 }, 1365 }, 1366 }; 1367 1368 static struct clk_branch gcc_gp3_clk = { 1369 .halt_reg = 0x66000, 1370 .halt_check = BRANCH_HALT, 1371 .clkr = { 1372 .enable_reg = 0x66000, 1373 .enable_mask = BIT(0), 1374 .hw.init = &(struct clk_init_data){ 1375 .name = "gcc_gp3_clk", 1376 .parent_hws = (const struct clk_hw*[]){ 1377 &gcc_gp3_clk_src.clkr.hw, 1378 }, 1379 .num_parents = 1, 1380 .flags = CLK_SET_RATE_PARENT, 1381 .ops = &clk_branch2_ops, 1382 }, 1383 }, 1384 }; 1385 1386 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1387 .halt_check = BRANCH_HALT_DELAY, 1388 .clkr = { 1389 .enable_reg = 0x52000, 1390 .enable_mask = BIT(15), 1391 .hw.init = &(struct clk_init_data){ 1392 .name = "gcc_gpu_gpll0_clk_src", 1393 .parent_hws = (const struct clk_hw*[]){ 1394 &gpll0.clkr.hw, 1395 }, 1396 .num_parents = 1, 1397 .flags = CLK_SET_RATE_PARENT, 1398 .ops = &clk_branch2_ops, 1399 }, 1400 }, 1401 }; 1402 1403 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1404 .halt_check = BRANCH_HALT_DELAY, 1405 .clkr = { 1406 .enable_reg = 0x52000, 1407 .enable_mask = BIT(16), 1408 .hw.init = &(struct clk_init_data){ 1409 .name = "gcc_gpu_gpll0_div_clk_src", 1410 .parent_hws = (const struct clk_hw*[]){ 1411 &gpll0_out_even.clkr.hw, 1412 }, 1413 .num_parents = 1, 1414 .flags = CLK_SET_RATE_PARENT, 1415 .ops = &clk_branch2_ops, 1416 }, 1417 }, 1418 }; 1419 1420 static struct clk_branch gcc_gpu_iref_en = { 1421 .halt_reg = 0x8c014, 1422 .halt_check = BRANCH_HALT, 1423 .clkr = { 1424 .enable_reg = 0x8c014, 1425 .enable_mask = BIT(0), 1426 .hw.init = &(struct clk_init_data){ 1427 .name = "gcc_gpu_iref_en", 1428 .ops = &clk_branch2_ops, 1429 }, 1430 }, 1431 }; 1432 1433 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1434 .halt_reg = 0x7100c, 1435 .halt_check = BRANCH_HALT_VOTED, 1436 .clkr = { 1437 .enable_reg = 0x7100c, 1438 .enable_mask = BIT(0), 1439 .hw.init = &(struct clk_init_data){ 1440 .name = "gcc_gpu_memnoc_gfx_clk", 1441 .ops = &clk_branch2_ops, 1442 }, 1443 }, 1444 }; 1445 1446 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1447 .halt_reg = 0x71018, 1448 .halt_check = BRANCH_HALT, 1449 .clkr = { 1450 .enable_reg = 0x71018, 1451 .enable_mask = BIT(0), 1452 .hw.init = &(struct clk_init_data){ 1453 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1454 .ops = &clk_branch2_ops, 1455 }, 1456 }, 1457 }; 1458 1459 static struct clk_branch gcc_npu_axi_clk = { 1460 .halt_reg = 0x4d008, 1461 .halt_check = BRANCH_HALT_VOTED, 1462 .clkr = { 1463 .enable_reg = 0x4d008, 1464 .enable_mask = BIT(0), 1465 .hw.init = &(struct clk_init_data){ 1466 .name = "gcc_npu_axi_clk", 1467 .ops = &clk_branch2_ops, 1468 }, 1469 }, 1470 }; 1471 1472 static struct clk_branch gcc_npu_bwmon_axi_clk = { 1473 .halt_reg = 0x73008, 1474 .halt_check = BRANCH_HALT_VOTED, 1475 .clkr = { 1476 .enable_reg = 0x73008, 1477 .enable_mask = BIT(0), 1478 .hw.init = &(struct clk_init_data){ 1479 .name = "gcc_npu_bwmon_axi_clk", 1480 .ops = &clk_branch2_ops, 1481 }, 1482 }, 1483 }; 1484 1485 static struct clk_branch gcc_npu_bwmon_cfg_ahb_clk = { 1486 .halt_reg = 0x73004, 1487 .halt_check = BRANCH_HALT, 1488 .clkr = { 1489 .enable_reg = 0x73004, 1490 .enable_mask = BIT(0), 1491 .hw.init = &(struct clk_init_data){ 1492 .name = "gcc_npu_bwmon_cfg_ahb_clk", 1493 .ops = &clk_branch2_ops, 1494 }, 1495 }, 1496 }; 1497 1498 static struct clk_branch gcc_npu_cfg_ahb_clk = { 1499 .halt_reg = 0x4d004, 1500 .halt_check = BRANCH_HALT, 1501 .hwcg_reg = 0x4d004, 1502 .hwcg_bit = 1, 1503 .clkr = { 1504 .enable_reg = 0x4d004, 1505 .enable_mask = BIT(0), 1506 .hw.init = &(struct clk_init_data){ 1507 .name = "gcc_npu_cfg_ahb_clk", 1508 .ops = &clk_branch2_ops, 1509 }, 1510 }, 1511 }; 1512 1513 static struct clk_branch gcc_npu_dma_clk = { 1514 .halt_reg = 0x4d00c, 1515 .halt_check = BRANCH_HALT_VOTED, 1516 .clkr = { 1517 .enable_reg = 0x4d00c, 1518 .enable_mask = BIT(0), 1519 .hw.init = &(struct clk_init_data){ 1520 .name = "gcc_npu_dma_clk", 1521 .ops = &clk_branch2_ops, 1522 }, 1523 }, 1524 }; 1525 1526 static struct clk_branch gcc_npu_gpll0_clk_src = { 1527 .halt_check = BRANCH_HALT_DELAY, 1528 .clkr = { 1529 .enable_reg = 0x52000, 1530 .enable_mask = BIT(18), 1531 .hw.init = &(struct clk_init_data){ 1532 .name = "gcc_npu_gpll0_clk_src", 1533 .parent_hws = (const struct clk_hw*[]){ 1534 &gpll0.clkr.hw, 1535 }, 1536 .num_parents = 1, 1537 .flags = CLK_SET_RATE_PARENT, 1538 .ops = &clk_branch2_ops, 1539 }, 1540 }, 1541 }; 1542 1543 static struct clk_branch gcc_npu_gpll0_div_clk_src = { 1544 .halt_check = BRANCH_HALT_DELAY, 1545 .clkr = { 1546 .enable_reg = 0x52000, 1547 .enable_mask = BIT(19), 1548 .hw.init = &(struct clk_init_data){ 1549 .name = "gcc_npu_gpll0_div_clk_src", 1550 .parent_hws = (const struct clk_hw*[]){ 1551 &gpll0_out_even.clkr.hw, 1552 }, 1553 .num_parents = 1, 1554 .flags = CLK_SET_RATE_PARENT, 1555 .ops = &clk_branch2_ops, 1556 }, 1557 }, 1558 }; 1559 1560 static struct clk_branch gcc_pcie0_phy_refgen_clk = { 1561 .halt_reg = 0x6f02c, 1562 .halt_check = BRANCH_HALT, 1563 .clkr = { 1564 .enable_reg = 0x6f02c, 1565 .enable_mask = BIT(0), 1566 .hw.init = &(struct clk_init_data){ 1567 .name = "gcc_pcie0_phy_refgen_clk", 1568 .parent_hws = (const struct clk_hw*[]){ 1569 &gcc_pcie_phy_refgen_clk_src.clkr.hw, 1570 }, 1571 .num_parents = 1, 1572 .flags = CLK_SET_RATE_PARENT, 1573 .ops = &clk_branch2_ops, 1574 }, 1575 }, 1576 }; 1577 1578 static struct clk_branch gcc_pcie1_phy_refgen_clk = { 1579 .halt_reg = 0x6f030, 1580 .halt_check = BRANCH_HALT, 1581 .clkr = { 1582 .enable_reg = 0x6f030, 1583 .enable_mask = BIT(0), 1584 .hw.init = &(struct clk_init_data){ 1585 .name = "gcc_pcie1_phy_refgen_clk", 1586 .parent_hws = (const struct clk_hw*[]){ 1587 &gcc_pcie_phy_refgen_clk_src.clkr.hw, 1588 }, 1589 .num_parents = 1, 1590 .flags = CLK_SET_RATE_PARENT, 1591 .ops = &clk_branch2_ops, 1592 }, 1593 }, 1594 }; 1595 1596 static struct clk_branch gcc_pcie2_phy_refgen_clk = { 1597 .halt_reg = 0x6f034, 1598 .halt_check = BRANCH_HALT, 1599 .clkr = { 1600 .enable_reg = 0x6f034, 1601 .enable_mask = BIT(0), 1602 .hw.init = &(struct clk_init_data){ 1603 .name = "gcc_pcie2_phy_refgen_clk", 1604 .parent_hws = (const struct clk_hw*[]){ 1605 &gcc_pcie_phy_refgen_clk_src.clkr.hw, 1606 }, 1607 .num_parents = 1, 1608 .flags = CLK_SET_RATE_PARENT, 1609 .ops = &clk_branch2_ops, 1610 }, 1611 }, 1612 }; 1613 1614 static struct clk_branch gcc_pcie_0_aux_clk = { 1615 .halt_reg = 0x6b028, 1616 .halt_check = BRANCH_HALT_VOTED, 1617 .clkr = { 1618 .enable_reg = 0x52008, 1619 .enable_mask = BIT(3), 1620 .hw.init = &(struct clk_init_data){ 1621 .name = "gcc_pcie_0_aux_clk", 1622 .parent_hws = (const struct clk_hw*[]){ 1623 &gcc_pcie_0_aux_clk_src.clkr.hw, 1624 }, 1625 .num_parents = 1, 1626 .flags = CLK_SET_RATE_PARENT, 1627 .ops = &clk_branch2_ops, 1628 }, 1629 }, 1630 }; 1631 1632 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1633 .halt_reg = 0x6b024, 1634 .halt_check = BRANCH_HALT_VOTED, 1635 .hwcg_reg = 0x6b024, 1636 .hwcg_bit = 1, 1637 .clkr = { 1638 .enable_reg = 0x52008, 1639 .enable_mask = BIT(2), 1640 .hw.init = &(struct clk_init_data){ 1641 .name = "gcc_pcie_0_cfg_ahb_clk", 1642 .ops = &clk_branch2_ops, 1643 }, 1644 }, 1645 }; 1646 1647 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1648 .halt_reg = 0x6b01c, 1649 .halt_check = BRANCH_HALT_VOTED, 1650 .clkr = { 1651 .enable_reg = 0x52008, 1652 .enable_mask = BIT(1), 1653 .hw.init = &(struct clk_init_data){ 1654 .name = "gcc_pcie_0_mstr_axi_clk", 1655 .ops = &clk_branch2_ops, 1656 }, 1657 }, 1658 }; 1659 1660 static struct clk_branch gcc_pcie_0_pipe_clk = { 1661 .halt_reg = 0x6b02c, 1662 .halt_check = BRANCH_HALT_SKIP, 1663 .clkr = { 1664 .enable_reg = 0x52008, 1665 .enable_mask = BIT(4), 1666 .hw.init = &(struct clk_init_data){ 1667 .name = "gcc_pcie_0_pipe_clk", 1668 .ops = &clk_branch2_ops, 1669 }, 1670 }, 1671 }; 1672 1673 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1674 .halt_reg = 0x6b014, 1675 .halt_check = BRANCH_HALT_VOTED, 1676 .hwcg_reg = 0x6b014, 1677 .hwcg_bit = 1, 1678 .clkr = { 1679 .enable_reg = 0x52008, 1680 .enable_mask = BIT(0), 1681 .hw.init = &(struct clk_init_data){ 1682 .name = "gcc_pcie_0_slv_axi_clk", 1683 .ops = &clk_branch2_ops, 1684 }, 1685 }, 1686 }; 1687 1688 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1689 .halt_reg = 0x6b010, 1690 .halt_check = BRANCH_HALT_VOTED, 1691 .clkr = { 1692 .enable_reg = 0x52008, 1693 .enable_mask = BIT(5), 1694 .hw.init = &(struct clk_init_data){ 1695 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1696 .ops = &clk_branch2_ops, 1697 }, 1698 }, 1699 }; 1700 1701 static struct clk_branch gcc_pcie_1_aux_clk = { 1702 .halt_reg = 0x8d028, 1703 .halt_check = BRANCH_HALT_VOTED, 1704 .clkr = { 1705 .enable_reg = 0x52000, 1706 .enable_mask = BIT(29), 1707 .hw.init = &(struct clk_init_data){ 1708 .name = "gcc_pcie_1_aux_clk", 1709 .parent_hws = (const struct clk_hw*[]){ 1710 &gcc_pcie_1_aux_clk_src.clkr.hw, 1711 }, 1712 .num_parents = 1, 1713 .flags = CLK_SET_RATE_PARENT, 1714 .ops = &clk_branch2_ops, 1715 }, 1716 }, 1717 }; 1718 1719 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1720 .halt_reg = 0x8d024, 1721 .halt_check = BRANCH_HALT_VOTED, 1722 .hwcg_reg = 0x8d024, 1723 .hwcg_bit = 1, 1724 .clkr = { 1725 .enable_reg = 0x52000, 1726 .enable_mask = BIT(28), 1727 .hw.init = &(struct clk_init_data){ 1728 .name = "gcc_pcie_1_cfg_ahb_clk", 1729 .ops = &clk_branch2_ops, 1730 }, 1731 }, 1732 }; 1733 1734 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1735 .halt_reg = 0x8d01c, 1736 .halt_check = BRANCH_HALT_VOTED, 1737 .clkr = { 1738 .enable_reg = 0x52000, 1739 .enable_mask = BIT(27), 1740 .hw.init = &(struct clk_init_data){ 1741 .name = "gcc_pcie_1_mstr_axi_clk", 1742 .ops = &clk_branch2_ops, 1743 }, 1744 }, 1745 }; 1746 1747 static struct clk_branch gcc_pcie_1_pipe_clk = { 1748 .halt_reg = 0x8d02c, 1749 .halt_check = BRANCH_HALT_SKIP, 1750 .clkr = { 1751 .enable_reg = 0x52000, 1752 .enable_mask = BIT(30), 1753 .hw.init = &(struct clk_init_data){ 1754 .name = "gcc_pcie_1_pipe_clk", 1755 .ops = &clk_branch2_ops, 1756 }, 1757 }, 1758 }; 1759 1760 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1761 .halt_reg = 0x8d014, 1762 .halt_check = BRANCH_HALT_VOTED, 1763 .hwcg_reg = 0x8d014, 1764 .hwcg_bit = 1, 1765 .clkr = { 1766 .enable_reg = 0x52000, 1767 .enable_mask = BIT(26), 1768 .hw.init = &(struct clk_init_data){ 1769 .name = "gcc_pcie_1_slv_axi_clk", 1770 .ops = &clk_branch2_ops, 1771 }, 1772 }, 1773 }; 1774 1775 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 1776 .halt_reg = 0x8d010, 1777 .halt_check = BRANCH_HALT_VOTED, 1778 .clkr = { 1779 .enable_reg = 0x52000, 1780 .enable_mask = BIT(25), 1781 .hw.init = &(struct clk_init_data){ 1782 .name = "gcc_pcie_1_slv_q2a_axi_clk", 1783 .ops = &clk_branch2_ops, 1784 }, 1785 }, 1786 }; 1787 1788 static struct clk_branch gcc_pcie_2_aux_clk = { 1789 .halt_reg = 0x6028, 1790 .halt_check = BRANCH_HALT_VOTED, 1791 .clkr = { 1792 .enable_reg = 0x52010, 1793 .enable_mask = BIT(14), 1794 .hw.init = &(struct clk_init_data){ 1795 .name = "gcc_pcie_2_aux_clk", 1796 .parent_hws = (const struct clk_hw*[]){ 1797 &gcc_pcie_2_aux_clk_src.clkr.hw, 1798 }, 1799 .num_parents = 1, 1800 .flags = CLK_SET_RATE_PARENT, 1801 .ops = &clk_branch2_ops, 1802 }, 1803 }, 1804 }; 1805 1806 static struct clk_branch gcc_pcie_2_cfg_ahb_clk = { 1807 .halt_reg = 0x6024, 1808 .halt_check = BRANCH_HALT_VOTED, 1809 .hwcg_reg = 0x6024, 1810 .hwcg_bit = 1, 1811 .clkr = { 1812 .enable_reg = 0x52010, 1813 .enable_mask = BIT(13), 1814 .hw.init = &(struct clk_init_data){ 1815 .name = "gcc_pcie_2_cfg_ahb_clk", 1816 .ops = &clk_branch2_ops, 1817 }, 1818 }, 1819 }; 1820 1821 static struct clk_branch gcc_pcie_2_mstr_axi_clk = { 1822 .halt_reg = 0x601c, 1823 .halt_check = BRANCH_HALT_VOTED, 1824 .clkr = { 1825 .enable_reg = 0x52010, 1826 .enable_mask = BIT(12), 1827 .hw.init = &(struct clk_init_data){ 1828 .name = "gcc_pcie_2_mstr_axi_clk", 1829 .ops = &clk_branch2_ops, 1830 }, 1831 }, 1832 }; 1833 1834 static struct clk_branch gcc_pcie_2_pipe_clk = { 1835 .halt_reg = 0x602c, 1836 .halt_check = BRANCH_HALT_SKIP, 1837 .clkr = { 1838 .enable_reg = 0x52010, 1839 .enable_mask = BIT(15), 1840 .hw.init = &(struct clk_init_data){ 1841 .name = "gcc_pcie_2_pipe_clk", 1842 .ops = &clk_branch2_ops, 1843 }, 1844 }, 1845 }; 1846 1847 static struct clk_branch gcc_pcie_2_slv_axi_clk = { 1848 .halt_reg = 0x6014, 1849 .halt_check = BRANCH_HALT_VOTED, 1850 .hwcg_reg = 0x6014, 1851 .hwcg_bit = 1, 1852 .clkr = { 1853 .enable_reg = 0x52010, 1854 .enable_mask = BIT(11), 1855 .hw.init = &(struct clk_init_data){ 1856 .name = "gcc_pcie_2_slv_axi_clk", 1857 .ops = &clk_branch2_ops, 1858 }, 1859 }, 1860 }; 1861 1862 static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = { 1863 .halt_reg = 0x6010, 1864 .halt_check = BRANCH_HALT_VOTED, 1865 .clkr = { 1866 .enable_reg = 0x52010, 1867 .enable_mask = BIT(10), 1868 .hw.init = &(struct clk_init_data){ 1869 .name = "gcc_pcie_2_slv_q2a_axi_clk", 1870 .ops = &clk_branch2_ops, 1871 }, 1872 }, 1873 }; 1874 1875 static struct clk_branch gcc_pcie_mdm_clkref_en = { 1876 .halt_reg = 0x8c00c, 1877 .halt_check = BRANCH_HALT, 1878 .clkr = { 1879 .enable_reg = 0x8c00c, 1880 .enable_mask = BIT(0), 1881 .hw.init = &(struct clk_init_data){ 1882 .name = "gcc_pcie_mdm_clkref_en", 1883 .ops = &clk_branch2_ops, 1884 }, 1885 }, 1886 }; 1887 1888 static struct clk_branch gcc_pcie_phy_aux_clk = { 1889 .halt_reg = 0x6f004, 1890 .halt_check = BRANCH_HALT, 1891 .clkr = { 1892 .enable_reg = 0x6f004, 1893 .enable_mask = BIT(0), 1894 .hw.init = &(struct clk_init_data){ 1895 .name = "gcc_pcie_phy_aux_clk", 1896 .parent_hws = (const struct clk_hw*[]){ 1897 &gcc_pcie_0_aux_clk_src.clkr.hw, 1898 }, 1899 .num_parents = 1, 1900 .flags = CLK_SET_RATE_PARENT, 1901 .ops = &clk_branch2_ops, 1902 }, 1903 }, 1904 }; 1905 1906 static struct clk_branch gcc_pcie_wifi_clkref_en = { 1907 .halt_reg = 0x8c004, 1908 .halt_check = BRANCH_HALT, 1909 .clkr = { 1910 .enable_reg = 0x8c004, 1911 .enable_mask = BIT(0), 1912 .hw.init = &(struct clk_init_data){ 1913 .name = "gcc_pcie_wifi_clkref_en", 1914 .ops = &clk_branch2_ops, 1915 }, 1916 }, 1917 }; 1918 1919 static struct clk_branch gcc_pcie_wigig_clkref_en = { 1920 .halt_reg = 0x8c008, 1921 .halt_check = BRANCH_HALT, 1922 .clkr = { 1923 .enable_reg = 0x8c008, 1924 .enable_mask = BIT(0), 1925 .hw.init = &(struct clk_init_data){ 1926 .name = "gcc_pcie_wigig_clkref_en", 1927 .ops = &clk_branch2_ops, 1928 }, 1929 }, 1930 }; 1931 1932 static struct clk_branch gcc_pdm2_clk = { 1933 .halt_reg = 0x3300c, 1934 .halt_check = BRANCH_HALT, 1935 .clkr = { 1936 .enable_reg = 0x3300c, 1937 .enable_mask = BIT(0), 1938 .hw.init = &(struct clk_init_data){ 1939 .name = "gcc_pdm2_clk", 1940 .parent_hws = (const struct clk_hw*[]){ 1941 &gcc_pdm2_clk_src.clkr.hw, 1942 }, 1943 .num_parents = 1, 1944 .flags = CLK_SET_RATE_PARENT, 1945 .ops = &clk_branch2_ops, 1946 }, 1947 }, 1948 }; 1949 1950 static struct clk_branch gcc_pdm_ahb_clk = { 1951 .halt_reg = 0x33004, 1952 .halt_check = BRANCH_HALT, 1953 .hwcg_reg = 0x33004, 1954 .hwcg_bit = 1, 1955 .clkr = { 1956 .enable_reg = 0x33004, 1957 .enable_mask = BIT(0), 1958 .hw.init = &(struct clk_init_data){ 1959 .name = "gcc_pdm_ahb_clk", 1960 .ops = &clk_branch2_ops, 1961 }, 1962 }, 1963 }; 1964 1965 static struct clk_branch gcc_pdm_xo4_clk = { 1966 .halt_reg = 0x33008, 1967 .halt_check = BRANCH_HALT, 1968 .clkr = { 1969 .enable_reg = 0x33008, 1970 .enable_mask = BIT(0), 1971 .hw.init = &(struct clk_init_data){ 1972 .name = "gcc_pdm_xo4_clk", 1973 .ops = &clk_branch2_ops, 1974 }, 1975 }, 1976 }; 1977 1978 static struct clk_branch gcc_prng_ahb_clk = { 1979 .halt_reg = 0x34004, 1980 .halt_check = BRANCH_HALT_VOTED, 1981 .clkr = { 1982 .enable_reg = 0x52000, 1983 .enable_mask = BIT(13), 1984 .hw.init = &(struct clk_init_data){ 1985 .name = "gcc_prng_ahb_clk", 1986 .ops = &clk_branch2_ops, 1987 }, 1988 }, 1989 }; 1990 1991 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 1992 .halt_reg = 0xb018, 1993 .halt_check = BRANCH_HALT_VOTED, 1994 .hwcg_reg = 0xb018, 1995 .hwcg_bit = 1, 1996 .clkr = { 1997 .enable_reg = 0xb018, 1998 .enable_mask = BIT(0), 1999 .hw.init = &(struct clk_init_data){ 2000 .name = "gcc_qmip_camera_nrt_ahb_clk", 2001 .ops = &clk_branch2_ops, 2002 }, 2003 }, 2004 }; 2005 2006 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2007 .halt_reg = 0xb01c, 2008 .halt_check = BRANCH_HALT_VOTED, 2009 .hwcg_reg = 0xb01c, 2010 .hwcg_bit = 1, 2011 .clkr = { 2012 .enable_reg = 0xb01c, 2013 .enable_mask = BIT(0), 2014 .hw.init = &(struct clk_init_data){ 2015 .name = "gcc_qmip_camera_rt_ahb_clk", 2016 .ops = &clk_branch2_ops, 2017 }, 2018 }, 2019 }; 2020 2021 static struct clk_branch gcc_qmip_disp_ahb_clk = { 2022 .halt_reg = 0xb020, 2023 .halt_check = BRANCH_HALT_VOTED, 2024 .hwcg_reg = 0xb020, 2025 .hwcg_bit = 1, 2026 .clkr = { 2027 .enable_reg = 0xb020, 2028 .enable_mask = BIT(0), 2029 .hw.init = &(struct clk_init_data){ 2030 .name = "gcc_qmip_disp_ahb_clk", 2031 .ops = &clk_branch2_ops, 2032 }, 2033 }, 2034 }; 2035 2036 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 2037 .halt_reg = 0xb010, 2038 .halt_check = BRANCH_HALT_VOTED, 2039 .hwcg_reg = 0xb010, 2040 .hwcg_bit = 1, 2041 .clkr = { 2042 .enable_reg = 0xb010, 2043 .enable_mask = BIT(0), 2044 .hw.init = &(struct clk_init_data){ 2045 .name = "gcc_qmip_video_cvp_ahb_clk", 2046 .ops = &clk_branch2_ops, 2047 }, 2048 }, 2049 }; 2050 2051 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2052 .halt_reg = 0xb014, 2053 .halt_check = BRANCH_HALT_VOTED, 2054 .hwcg_reg = 0xb014, 2055 .hwcg_bit = 1, 2056 .clkr = { 2057 .enable_reg = 0xb014, 2058 .enable_mask = BIT(0), 2059 .hw.init = &(struct clk_init_data){ 2060 .name = "gcc_qmip_video_vcodec_ahb_clk", 2061 .ops = &clk_branch2_ops, 2062 }, 2063 }, 2064 }; 2065 2066 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2067 .halt_reg = 0x23008, 2068 .halt_check = BRANCH_HALT_VOTED, 2069 .clkr = { 2070 .enable_reg = 0x52008, 2071 .enable_mask = BIT(9), 2072 .hw.init = &(struct clk_init_data){ 2073 .name = "gcc_qupv3_wrap0_core_2x_clk", 2074 .ops = &clk_branch2_ops, 2075 }, 2076 }, 2077 }; 2078 2079 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2080 .halt_reg = 0x23000, 2081 .halt_check = BRANCH_HALT_VOTED, 2082 .clkr = { 2083 .enable_reg = 0x52008, 2084 .enable_mask = BIT(8), 2085 .hw.init = &(struct clk_init_data){ 2086 .name = "gcc_qupv3_wrap0_core_clk", 2087 .ops = &clk_branch2_ops, 2088 }, 2089 }, 2090 }; 2091 2092 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2093 .halt_reg = 0x1700c, 2094 .halt_check = BRANCH_HALT_VOTED, 2095 .clkr = { 2096 .enable_reg = 0x52008, 2097 .enable_mask = BIT(10), 2098 .hw.init = &(struct clk_init_data){ 2099 .name = "gcc_qupv3_wrap0_s0_clk", 2100 .parent_hws = (const struct clk_hw*[]){ 2101 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 2102 }, 2103 .num_parents = 1, 2104 .flags = CLK_SET_RATE_PARENT, 2105 .ops = &clk_branch2_ops, 2106 }, 2107 }, 2108 }; 2109 2110 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2111 .halt_reg = 0x1713c, 2112 .halt_check = BRANCH_HALT_VOTED, 2113 .clkr = { 2114 .enable_reg = 0x52008, 2115 .enable_mask = BIT(11), 2116 .hw.init = &(struct clk_init_data){ 2117 .name = "gcc_qupv3_wrap0_s1_clk", 2118 .parent_hws = (const struct clk_hw*[]){ 2119 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 2120 }, 2121 .num_parents = 1, 2122 .flags = CLK_SET_RATE_PARENT, 2123 .ops = &clk_branch2_ops, 2124 }, 2125 }, 2126 }; 2127 2128 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2129 .halt_reg = 0x1726c, 2130 .halt_check = BRANCH_HALT_VOTED, 2131 .clkr = { 2132 .enable_reg = 0x52008, 2133 .enable_mask = BIT(12), 2134 .hw.init = &(struct clk_init_data){ 2135 .name = "gcc_qupv3_wrap0_s2_clk", 2136 .parent_hws = (const struct clk_hw*[]){ 2137 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2138 }, 2139 .num_parents = 1, 2140 .flags = CLK_SET_RATE_PARENT, 2141 .ops = &clk_branch2_ops, 2142 }, 2143 }, 2144 }; 2145 2146 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2147 .halt_reg = 0x1739c, 2148 .halt_check = BRANCH_HALT_VOTED, 2149 .clkr = { 2150 .enable_reg = 0x52008, 2151 .enable_mask = BIT(13), 2152 .hw.init = &(struct clk_init_data){ 2153 .name = "gcc_qupv3_wrap0_s3_clk", 2154 .parent_hws = (const struct clk_hw*[]){ 2155 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2156 }, 2157 .num_parents = 1, 2158 .flags = CLK_SET_RATE_PARENT, 2159 .ops = &clk_branch2_ops, 2160 }, 2161 }, 2162 }; 2163 2164 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2165 .halt_reg = 0x174cc, 2166 .halt_check = BRANCH_HALT_VOTED, 2167 .clkr = { 2168 .enable_reg = 0x52008, 2169 .enable_mask = BIT(14), 2170 .hw.init = &(struct clk_init_data){ 2171 .name = "gcc_qupv3_wrap0_s4_clk", 2172 .parent_hws = (const struct clk_hw*[]){ 2173 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2174 }, 2175 .num_parents = 1, 2176 .flags = CLK_SET_RATE_PARENT, 2177 .ops = &clk_branch2_ops, 2178 }, 2179 }, 2180 }; 2181 2182 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2183 .halt_reg = 0x175fc, 2184 .halt_check = BRANCH_HALT_VOTED, 2185 .clkr = { 2186 .enable_reg = 0x52008, 2187 .enable_mask = BIT(15), 2188 .hw.init = &(struct clk_init_data){ 2189 .name = "gcc_qupv3_wrap0_s5_clk", 2190 .parent_hws = (const struct clk_hw*[]){ 2191 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2192 }, 2193 .num_parents = 1, 2194 .flags = CLK_SET_RATE_PARENT, 2195 .ops = &clk_branch2_ops, 2196 }, 2197 }, 2198 }; 2199 2200 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 2201 .halt_reg = 0x1772c, 2202 .halt_check = BRANCH_HALT_VOTED, 2203 .clkr = { 2204 .enable_reg = 0x52008, 2205 .enable_mask = BIT(16), 2206 .hw.init = &(struct clk_init_data){ 2207 .name = "gcc_qupv3_wrap0_s6_clk", 2208 .parent_hws = (const struct clk_hw*[]){ 2209 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 2210 }, 2211 .num_parents = 1, 2212 .flags = CLK_SET_RATE_PARENT, 2213 .ops = &clk_branch2_ops, 2214 }, 2215 }, 2216 }; 2217 2218 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 2219 .halt_reg = 0x1785c, 2220 .halt_check = BRANCH_HALT_VOTED, 2221 .clkr = { 2222 .enable_reg = 0x52008, 2223 .enable_mask = BIT(17), 2224 .hw.init = &(struct clk_init_data){ 2225 .name = "gcc_qupv3_wrap0_s7_clk", 2226 .parent_hws = (const struct clk_hw*[]){ 2227 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 2228 }, 2229 .num_parents = 1, 2230 .flags = CLK_SET_RATE_PARENT, 2231 .ops = &clk_branch2_ops, 2232 }, 2233 }, 2234 }; 2235 2236 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2237 .halt_reg = 0x23140, 2238 .halt_check = BRANCH_HALT_VOTED, 2239 .clkr = { 2240 .enable_reg = 0x52008, 2241 .enable_mask = BIT(18), 2242 .hw.init = &(struct clk_init_data){ 2243 .name = "gcc_qupv3_wrap1_core_2x_clk", 2244 .ops = &clk_branch2_ops, 2245 }, 2246 }, 2247 }; 2248 2249 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2250 .halt_reg = 0x23138, 2251 .halt_check = BRANCH_HALT_VOTED, 2252 .clkr = { 2253 .enable_reg = 0x52008, 2254 .enable_mask = BIT(19), 2255 .hw.init = &(struct clk_init_data){ 2256 .name = "gcc_qupv3_wrap1_core_clk", 2257 .ops = &clk_branch2_ops, 2258 }, 2259 }, 2260 }; 2261 2262 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2263 .halt_reg = 0x1800c, 2264 .halt_check = BRANCH_HALT_VOTED, 2265 .clkr = { 2266 .enable_reg = 0x52008, 2267 .enable_mask = BIT(22), 2268 .hw.init = &(struct clk_init_data){ 2269 .name = "gcc_qupv3_wrap1_s0_clk", 2270 .parent_hws = (const struct clk_hw*[]){ 2271 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2272 }, 2273 .num_parents = 1, 2274 .flags = CLK_SET_RATE_PARENT, 2275 .ops = &clk_branch2_ops, 2276 }, 2277 }, 2278 }; 2279 2280 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2281 .halt_reg = 0x1813c, 2282 .halt_check = BRANCH_HALT_VOTED, 2283 .clkr = { 2284 .enable_reg = 0x52008, 2285 .enable_mask = BIT(23), 2286 .hw.init = &(struct clk_init_data){ 2287 .name = "gcc_qupv3_wrap1_s1_clk", 2288 .parent_hws = (const struct clk_hw*[]){ 2289 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2290 }, 2291 .num_parents = 1, 2292 .flags = CLK_SET_RATE_PARENT, 2293 .ops = &clk_branch2_ops, 2294 }, 2295 }, 2296 }; 2297 2298 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2299 .halt_reg = 0x1826c, 2300 .halt_check = BRANCH_HALT_VOTED, 2301 .clkr = { 2302 .enable_reg = 0x52008, 2303 .enable_mask = BIT(24), 2304 .hw.init = &(struct clk_init_data){ 2305 .name = "gcc_qupv3_wrap1_s2_clk", 2306 .parent_hws = (const struct clk_hw*[]){ 2307 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2308 }, 2309 .num_parents = 1, 2310 .flags = CLK_SET_RATE_PARENT, 2311 .ops = &clk_branch2_ops, 2312 }, 2313 }, 2314 }; 2315 2316 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2317 .halt_reg = 0x1839c, 2318 .halt_check = BRANCH_HALT_VOTED, 2319 .clkr = { 2320 .enable_reg = 0x52008, 2321 .enable_mask = BIT(25), 2322 .hw.init = &(struct clk_init_data){ 2323 .name = "gcc_qupv3_wrap1_s3_clk", 2324 .parent_hws = (const struct clk_hw*[]){ 2325 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2326 }, 2327 .num_parents = 1, 2328 .flags = CLK_SET_RATE_PARENT, 2329 .ops = &clk_branch2_ops, 2330 }, 2331 }, 2332 }; 2333 2334 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2335 .halt_reg = 0x184cc, 2336 .halt_check = BRANCH_HALT_VOTED, 2337 .clkr = { 2338 .enable_reg = 0x52008, 2339 .enable_mask = BIT(26), 2340 .hw.init = &(struct clk_init_data){ 2341 .name = "gcc_qupv3_wrap1_s4_clk", 2342 .parent_hws = (const struct clk_hw*[]){ 2343 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2344 }, 2345 .num_parents = 1, 2346 .flags = CLK_SET_RATE_PARENT, 2347 .ops = &clk_branch2_ops, 2348 }, 2349 }, 2350 }; 2351 2352 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2353 .halt_reg = 0x185fc, 2354 .halt_check = BRANCH_HALT_VOTED, 2355 .clkr = { 2356 .enable_reg = 0x52008, 2357 .enable_mask = BIT(27), 2358 .hw.init = &(struct clk_init_data){ 2359 .name = "gcc_qupv3_wrap1_s5_clk", 2360 .parent_hws = (const struct clk_hw*[]){ 2361 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2362 }, 2363 .num_parents = 1, 2364 .flags = CLK_SET_RATE_PARENT, 2365 .ops = &clk_branch2_ops, 2366 }, 2367 }, 2368 }; 2369 2370 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 2371 .halt_reg = 0x23278, 2372 .halt_check = BRANCH_HALT_VOTED, 2373 .clkr = { 2374 .enable_reg = 0x52010, 2375 .enable_mask = BIT(3), 2376 .hw.init = &(struct clk_init_data){ 2377 .name = "gcc_qupv3_wrap2_core_2x_clk", 2378 .ops = &clk_branch2_ops, 2379 }, 2380 }, 2381 }; 2382 2383 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 2384 .halt_reg = 0x23270, 2385 .halt_check = BRANCH_HALT_VOTED, 2386 .clkr = { 2387 .enable_reg = 0x52010, 2388 .enable_mask = BIT(0), 2389 .hw.init = &(struct clk_init_data){ 2390 .name = "gcc_qupv3_wrap2_core_clk", 2391 .ops = &clk_branch2_ops, 2392 }, 2393 }, 2394 }; 2395 2396 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 2397 .halt_reg = 0x1e00c, 2398 .halt_check = BRANCH_HALT_VOTED, 2399 .clkr = { 2400 .enable_reg = 0x52010, 2401 .enable_mask = BIT(4), 2402 .hw.init = &(struct clk_init_data){ 2403 .name = "gcc_qupv3_wrap2_s0_clk", 2404 .parent_hws = (const struct clk_hw*[]){ 2405 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 2406 }, 2407 .num_parents = 1, 2408 .flags = CLK_SET_RATE_PARENT, 2409 .ops = &clk_branch2_ops, 2410 }, 2411 }, 2412 }; 2413 2414 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 2415 .halt_reg = 0x1e13c, 2416 .halt_check = BRANCH_HALT_VOTED, 2417 .clkr = { 2418 .enable_reg = 0x52010, 2419 .enable_mask = BIT(5), 2420 .hw.init = &(struct clk_init_data){ 2421 .name = "gcc_qupv3_wrap2_s1_clk", 2422 .parent_hws = (const struct clk_hw*[]){ 2423 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 2424 }, 2425 .num_parents = 1, 2426 .flags = CLK_SET_RATE_PARENT, 2427 .ops = &clk_branch2_ops, 2428 }, 2429 }, 2430 }; 2431 2432 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 2433 .halt_reg = 0x1e26c, 2434 .halt_check = BRANCH_HALT_VOTED, 2435 .clkr = { 2436 .enable_reg = 0x52010, 2437 .enable_mask = BIT(6), 2438 .hw.init = &(struct clk_init_data){ 2439 .name = "gcc_qupv3_wrap2_s2_clk", 2440 .parent_hws = (const struct clk_hw*[]){ 2441 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 2442 }, 2443 .num_parents = 1, 2444 .flags = CLK_SET_RATE_PARENT, 2445 .ops = &clk_branch2_ops, 2446 }, 2447 }, 2448 }; 2449 2450 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 2451 .halt_reg = 0x1e39c, 2452 .halt_check = BRANCH_HALT_VOTED, 2453 .clkr = { 2454 .enable_reg = 0x52010, 2455 .enable_mask = BIT(7), 2456 .hw.init = &(struct clk_init_data){ 2457 .name = "gcc_qupv3_wrap2_s3_clk", 2458 .parent_hws = (const struct clk_hw*[]){ 2459 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 2460 }, 2461 .num_parents = 1, 2462 .flags = CLK_SET_RATE_PARENT, 2463 .ops = &clk_branch2_ops, 2464 }, 2465 }, 2466 }; 2467 2468 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 2469 .halt_reg = 0x1e4cc, 2470 .halt_check = BRANCH_HALT_VOTED, 2471 .clkr = { 2472 .enable_reg = 0x52010, 2473 .enable_mask = BIT(8), 2474 .hw.init = &(struct clk_init_data){ 2475 .name = "gcc_qupv3_wrap2_s4_clk", 2476 .parent_hws = (const struct clk_hw*[]){ 2477 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 2478 }, 2479 .num_parents = 1, 2480 .flags = CLK_SET_RATE_PARENT, 2481 .ops = &clk_branch2_ops, 2482 }, 2483 }, 2484 }; 2485 2486 static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 2487 .halt_reg = 0x1e5fc, 2488 .halt_check = BRANCH_HALT_VOTED, 2489 .clkr = { 2490 .enable_reg = 0x52010, 2491 .enable_mask = BIT(9), 2492 .hw.init = &(struct clk_init_data){ 2493 .name = "gcc_qupv3_wrap2_s5_clk", 2494 .parent_hws = (const struct clk_hw*[]){ 2495 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 2496 }, 2497 .num_parents = 1, 2498 .flags = CLK_SET_RATE_PARENT, 2499 .ops = &clk_branch2_ops, 2500 }, 2501 }, 2502 }; 2503 2504 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2505 .halt_reg = 0x17004, 2506 .halt_check = BRANCH_HALT_VOTED, 2507 .clkr = { 2508 .enable_reg = 0x52008, 2509 .enable_mask = BIT(6), 2510 .hw.init = &(struct clk_init_data){ 2511 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2512 .ops = &clk_branch2_ops, 2513 }, 2514 }, 2515 }; 2516 2517 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2518 .halt_reg = 0x17008, 2519 .halt_check = BRANCH_HALT_VOTED, 2520 .hwcg_reg = 0x17008, 2521 .hwcg_bit = 1, 2522 .clkr = { 2523 .enable_reg = 0x52008, 2524 .enable_mask = BIT(7), 2525 .hw.init = &(struct clk_init_data){ 2526 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2527 .ops = &clk_branch2_ops, 2528 }, 2529 }, 2530 }; 2531 2532 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2533 .halt_reg = 0x18004, 2534 .halt_check = BRANCH_HALT_VOTED, 2535 .clkr = { 2536 .enable_reg = 0x52008, 2537 .enable_mask = BIT(20), 2538 .hw.init = &(struct clk_init_data){ 2539 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2540 .ops = &clk_branch2_ops, 2541 }, 2542 }, 2543 }; 2544 2545 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2546 .halt_reg = 0x18008, 2547 .halt_check = BRANCH_HALT_VOTED, 2548 .hwcg_reg = 0x18008, 2549 .hwcg_bit = 1, 2550 .clkr = { 2551 .enable_reg = 0x52008, 2552 .enable_mask = BIT(21), 2553 .hw.init = &(struct clk_init_data){ 2554 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2555 .ops = &clk_branch2_ops, 2556 }, 2557 }, 2558 }; 2559 2560 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 2561 .halt_reg = 0x1e004, 2562 .halt_check = BRANCH_HALT_VOTED, 2563 .clkr = { 2564 .enable_reg = 0x52010, 2565 .enable_mask = BIT(2), 2566 .hw.init = &(struct clk_init_data){ 2567 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 2568 .ops = &clk_branch2_ops, 2569 }, 2570 }, 2571 }; 2572 2573 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 2574 .halt_reg = 0x1e008, 2575 .halt_check = BRANCH_HALT_VOTED, 2576 .hwcg_reg = 0x1e008, 2577 .hwcg_bit = 1, 2578 .clkr = { 2579 .enable_reg = 0x52010, 2580 .enable_mask = BIT(1), 2581 .hw.init = &(struct clk_init_data){ 2582 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 2583 .ops = &clk_branch2_ops, 2584 }, 2585 }, 2586 }; 2587 2588 static struct clk_branch gcc_sdcc2_ahb_clk = { 2589 .halt_reg = 0x14008, 2590 .halt_check = BRANCH_HALT, 2591 .clkr = { 2592 .enable_reg = 0x14008, 2593 .enable_mask = BIT(0), 2594 .hw.init = &(struct clk_init_data){ 2595 .name = "gcc_sdcc2_ahb_clk", 2596 .ops = &clk_branch2_ops, 2597 }, 2598 }, 2599 }; 2600 2601 static struct clk_branch gcc_sdcc2_apps_clk = { 2602 .halt_reg = 0x14004, 2603 .halt_check = BRANCH_HALT, 2604 .clkr = { 2605 .enable_reg = 0x14004, 2606 .enable_mask = BIT(0), 2607 .hw.init = &(struct clk_init_data){ 2608 .name = "gcc_sdcc2_apps_clk", 2609 .parent_hws = (const struct clk_hw*[]){ 2610 &gcc_sdcc2_apps_clk_src.clkr.hw, 2611 }, 2612 .num_parents = 1, 2613 .flags = CLK_SET_RATE_PARENT, 2614 .ops = &clk_branch2_ops, 2615 }, 2616 }, 2617 }; 2618 2619 static struct clk_branch gcc_sdcc4_ahb_clk = { 2620 .halt_reg = 0x16008, 2621 .halt_check = BRANCH_HALT, 2622 .clkr = { 2623 .enable_reg = 0x16008, 2624 .enable_mask = BIT(0), 2625 .hw.init = &(struct clk_init_data){ 2626 .name = "gcc_sdcc4_ahb_clk", 2627 .ops = &clk_branch2_ops, 2628 }, 2629 }, 2630 }; 2631 2632 static struct clk_branch gcc_sdcc4_apps_clk = { 2633 .halt_reg = 0x16004, 2634 .halt_check = BRANCH_HALT, 2635 .clkr = { 2636 .enable_reg = 0x16004, 2637 .enable_mask = BIT(0), 2638 .hw.init = &(struct clk_init_data){ 2639 .name = "gcc_sdcc4_apps_clk", 2640 .parent_hws = (const struct clk_hw*[]){ 2641 &gcc_sdcc4_apps_clk_src.clkr.hw, 2642 }, 2643 .num_parents = 1, 2644 .flags = CLK_SET_RATE_PARENT, 2645 .ops = &clk_branch2_ops, 2646 }, 2647 }, 2648 }; 2649 2650 static struct clk_branch gcc_tsif_ahb_clk = { 2651 .halt_reg = 0x36004, 2652 .halt_check = BRANCH_HALT_VOTED, 2653 .clkr = { 2654 .enable_reg = 0x36004, 2655 .enable_mask = BIT(0), 2656 .hw.init = &(struct clk_init_data){ 2657 .name = "gcc_tsif_ahb_clk", 2658 .ops = &clk_branch2_ops, 2659 }, 2660 }, 2661 }; 2662 2663 static struct clk_branch gcc_tsif_inactivity_timers_clk = { 2664 .halt_reg = 0x3600c, 2665 .halt_check = BRANCH_HALT, 2666 .clkr = { 2667 .enable_reg = 0x3600c, 2668 .enable_mask = BIT(0), 2669 .hw.init = &(struct clk_init_data){ 2670 .name = "gcc_tsif_inactivity_timers_clk", 2671 .ops = &clk_branch2_ops, 2672 }, 2673 }, 2674 }; 2675 2676 static struct clk_branch gcc_tsif_ref_clk = { 2677 .halt_reg = 0x36008, 2678 .halt_check = BRANCH_HALT, 2679 .clkr = { 2680 .enable_reg = 0x36008, 2681 .enable_mask = BIT(0), 2682 .hw.init = &(struct clk_init_data){ 2683 .name = "gcc_tsif_ref_clk", 2684 .parent_hws = (const struct clk_hw*[]){ 2685 &gcc_tsif_ref_clk_src.clkr.hw, 2686 }, 2687 .num_parents = 1, 2688 .flags = CLK_SET_RATE_PARENT, 2689 .ops = &clk_branch2_ops, 2690 }, 2691 }, 2692 }; 2693 2694 static struct clk_branch gcc_ufs_1x_clkref_en = { 2695 .halt_reg = 0x8c000, 2696 .halt_check = BRANCH_HALT, 2697 .clkr = { 2698 .enable_reg = 0x8c000, 2699 .enable_mask = BIT(0), 2700 .hw.init = &(struct clk_init_data){ 2701 .name = "gcc_ufs_1x_clkref_en", 2702 .ops = &clk_branch2_ops, 2703 }, 2704 }, 2705 }; 2706 2707 static struct clk_branch gcc_ufs_card_ahb_clk = { 2708 .halt_reg = 0x75018, 2709 .halt_check = BRANCH_HALT_VOTED, 2710 .hwcg_reg = 0x75018, 2711 .hwcg_bit = 1, 2712 .clkr = { 2713 .enable_reg = 0x75018, 2714 .enable_mask = BIT(0), 2715 .hw.init = &(struct clk_init_data){ 2716 .name = "gcc_ufs_card_ahb_clk", 2717 .ops = &clk_branch2_ops, 2718 }, 2719 }, 2720 }; 2721 2722 static struct clk_branch gcc_ufs_card_axi_clk = { 2723 .halt_reg = 0x75010, 2724 .halt_check = BRANCH_HALT, 2725 .hwcg_reg = 0x75010, 2726 .hwcg_bit = 1, 2727 .clkr = { 2728 .enable_reg = 0x75010, 2729 .enable_mask = BIT(0), 2730 .hw.init = &(struct clk_init_data){ 2731 .name = "gcc_ufs_card_axi_clk", 2732 .parent_hws = (const struct clk_hw*[]){ 2733 &gcc_ufs_card_axi_clk_src.clkr.hw, 2734 }, 2735 .num_parents = 1, 2736 .flags = CLK_SET_RATE_PARENT, 2737 .ops = &clk_branch2_ops, 2738 }, 2739 }, 2740 }; 2741 2742 static struct clk_branch gcc_ufs_card_ice_core_clk = { 2743 .halt_reg = 0x75064, 2744 .halt_check = BRANCH_HALT_VOTED, 2745 .hwcg_reg = 0x75064, 2746 .hwcg_bit = 1, 2747 .clkr = { 2748 .enable_reg = 0x75064, 2749 .enable_mask = BIT(0), 2750 .hw.init = &(struct clk_init_data){ 2751 .name = "gcc_ufs_card_ice_core_clk", 2752 .parent_hws = (const struct clk_hw*[]){ 2753 &gcc_ufs_card_ice_core_clk_src.clkr.hw, 2754 }, 2755 .num_parents = 1, 2756 .flags = CLK_SET_RATE_PARENT, 2757 .ops = &clk_branch2_ops, 2758 }, 2759 }, 2760 }; 2761 2762 static struct clk_branch gcc_ufs_card_phy_aux_clk = { 2763 .halt_reg = 0x7509c, 2764 .halt_check = BRANCH_HALT, 2765 .hwcg_reg = 0x7509c, 2766 .hwcg_bit = 1, 2767 .clkr = { 2768 .enable_reg = 0x7509c, 2769 .enable_mask = BIT(0), 2770 .hw.init = &(struct clk_init_data){ 2771 .name = "gcc_ufs_card_phy_aux_clk", 2772 .parent_hws = (const struct clk_hw*[]){ 2773 &gcc_ufs_card_phy_aux_clk_src.clkr.hw, 2774 }, 2775 .num_parents = 1, 2776 .flags = CLK_SET_RATE_PARENT, 2777 .ops = &clk_branch2_ops, 2778 }, 2779 }, 2780 }; 2781 2782 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { 2783 .halt_reg = 0x75020, 2784 .halt_check = BRANCH_HALT_DELAY, 2785 .clkr = { 2786 .enable_reg = 0x75020, 2787 .enable_mask = BIT(0), 2788 .hw.init = &(struct clk_init_data){ 2789 .name = "gcc_ufs_card_rx_symbol_0_clk", 2790 .ops = &clk_branch2_ops, 2791 }, 2792 }, 2793 }; 2794 2795 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { 2796 .halt_reg = 0x750b8, 2797 .halt_check = BRANCH_HALT_DELAY, 2798 .clkr = { 2799 .enable_reg = 0x750b8, 2800 .enable_mask = BIT(0), 2801 .hw.init = &(struct clk_init_data){ 2802 .name = "gcc_ufs_card_rx_symbol_1_clk", 2803 .ops = &clk_branch2_ops, 2804 }, 2805 }, 2806 }; 2807 2808 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { 2809 .halt_reg = 0x7501c, 2810 .halt_check = BRANCH_HALT_DELAY, 2811 .clkr = { 2812 .enable_reg = 0x7501c, 2813 .enable_mask = BIT(0), 2814 .hw.init = &(struct clk_init_data){ 2815 .name = "gcc_ufs_card_tx_symbol_0_clk", 2816 .ops = &clk_branch2_ops, 2817 }, 2818 }, 2819 }; 2820 2821 static struct clk_branch gcc_ufs_card_unipro_core_clk = { 2822 .halt_reg = 0x7505c, 2823 .halt_check = BRANCH_HALT, 2824 .hwcg_reg = 0x7505c, 2825 .hwcg_bit = 1, 2826 .clkr = { 2827 .enable_reg = 0x7505c, 2828 .enable_mask = BIT(0), 2829 .hw.init = &(struct clk_init_data){ 2830 .name = "gcc_ufs_card_unipro_core_clk", 2831 .parent_hws = (const struct clk_hw*[]){ 2832 &gcc_ufs_card_unipro_core_clk_src.clkr.hw, 2833 }, 2834 .num_parents = 1, 2835 .flags = CLK_SET_RATE_PARENT, 2836 .ops = &clk_branch2_ops, 2837 }, 2838 }, 2839 }; 2840 2841 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2842 .halt_reg = 0x77018, 2843 .halt_check = BRANCH_HALT_VOTED, 2844 .hwcg_reg = 0x77018, 2845 .hwcg_bit = 1, 2846 .clkr = { 2847 .enable_reg = 0x77018, 2848 .enable_mask = BIT(0), 2849 .hw.init = &(struct clk_init_data){ 2850 .name = "gcc_ufs_phy_ahb_clk", 2851 .ops = &clk_branch2_ops, 2852 }, 2853 }, 2854 }; 2855 2856 static struct clk_branch gcc_ufs_phy_axi_clk = { 2857 .halt_reg = 0x77010, 2858 .halt_check = BRANCH_HALT, 2859 .hwcg_reg = 0x77010, 2860 .hwcg_bit = 1, 2861 .clkr = { 2862 .enable_reg = 0x77010, 2863 .enable_mask = BIT(0), 2864 .hw.init = &(struct clk_init_data){ 2865 .name = "gcc_ufs_phy_axi_clk", 2866 .parent_hws = (const struct clk_hw*[]){ 2867 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2868 }, 2869 .num_parents = 1, 2870 .flags = CLK_SET_RATE_PARENT, 2871 .ops = &clk_branch2_ops, 2872 }, 2873 }, 2874 }; 2875 2876 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2877 .halt_reg = 0x77064, 2878 .halt_check = BRANCH_HALT_VOTED, 2879 .hwcg_reg = 0x77064, 2880 .hwcg_bit = 1, 2881 .clkr = { 2882 .enable_reg = 0x77064, 2883 .enable_mask = BIT(0), 2884 .hw.init = &(struct clk_init_data){ 2885 .name = "gcc_ufs_phy_ice_core_clk", 2886 .parent_hws = (const struct clk_hw*[]){ 2887 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2888 }, 2889 .num_parents = 1, 2890 .flags = CLK_SET_RATE_PARENT, 2891 .ops = &clk_branch2_ops, 2892 }, 2893 }, 2894 }; 2895 2896 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2897 .halt_reg = 0x7709c, 2898 .halt_check = BRANCH_HALT, 2899 .hwcg_reg = 0x7709c, 2900 .hwcg_bit = 1, 2901 .clkr = { 2902 .enable_reg = 0x7709c, 2903 .enable_mask = BIT(0), 2904 .hw.init = &(struct clk_init_data){ 2905 .name = "gcc_ufs_phy_phy_aux_clk", 2906 .parent_hws = (const struct clk_hw*[]){ 2907 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2908 }, 2909 .num_parents = 1, 2910 .flags = CLK_SET_RATE_PARENT, 2911 .ops = &clk_branch2_ops, 2912 }, 2913 }, 2914 }; 2915 2916 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2917 .halt_reg = 0x77020, 2918 .halt_check = BRANCH_HALT_DELAY, 2919 .clkr = { 2920 .enable_reg = 0x77020, 2921 .enable_mask = BIT(0), 2922 .hw.init = &(struct clk_init_data){ 2923 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2924 .ops = &clk_branch2_ops, 2925 }, 2926 }, 2927 }; 2928 2929 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2930 .halt_reg = 0x770b8, 2931 .halt_check = BRANCH_HALT_DELAY, 2932 .clkr = { 2933 .enable_reg = 0x770b8, 2934 .enable_mask = BIT(0), 2935 .hw.init = &(struct clk_init_data){ 2936 .name = "gcc_ufs_phy_rx_symbol_1_clk", 2937 .ops = &clk_branch2_ops, 2938 }, 2939 }, 2940 }; 2941 2942 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2943 .halt_reg = 0x7701c, 2944 .halt_check = BRANCH_HALT_DELAY, 2945 .clkr = { 2946 .enable_reg = 0x7701c, 2947 .enable_mask = BIT(0), 2948 .hw.init = &(struct clk_init_data){ 2949 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2950 .ops = &clk_branch2_ops, 2951 }, 2952 }, 2953 }; 2954 2955 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2956 .halt_reg = 0x7705c, 2957 .halt_check = BRANCH_HALT, 2958 .hwcg_reg = 0x7705c, 2959 .hwcg_bit = 1, 2960 .clkr = { 2961 .enable_reg = 0x7705c, 2962 .enable_mask = BIT(0), 2963 .hw.init = &(struct clk_init_data){ 2964 .name = "gcc_ufs_phy_unipro_core_clk", 2965 .parent_hws = (const struct clk_hw*[]){ 2966 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2967 }, 2968 .num_parents = 1, 2969 .flags = CLK_SET_RATE_PARENT, 2970 .ops = &clk_branch2_ops, 2971 }, 2972 }, 2973 }; 2974 2975 static struct clk_branch gcc_usb30_prim_master_clk = { 2976 .halt_reg = 0xf010, 2977 .halt_check = BRANCH_HALT_VOTED, 2978 .clkr = { 2979 .enable_reg = 0xf010, 2980 .enable_mask = BIT(0), 2981 .hw.init = &(struct clk_init_data){ 2982 .name = "gcc_usb30_prim_master_clk", 2983 .parent_hws = (const struct clk_hw*[]){ 2984 &gcc_usb30_prim_master_clk_src.clkr.hw, 2985 }, 2986 .num_parents = 1, 2987 .flags = CLK_SET_RATE_PARENT, 2988 .ops = &clk_branch2_ops, 2989 }, 2990 }, 2991 }; 2992 2993 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2994 .halt_reg = 0xf01c, 2995 .halt_check = BRANCH_HALT, 2996 .clkr = { 2997 .enable_reg = 0xf01c, 2998 .enable_mask = BIT(0), 2999 .hw.init = &(struct clk_init_data){ 3000 .name = "gcc_usb30_prim_mock_utmi_clk", 3001 .parent_data = &(const struct clk_parent_data){ 3002 .hw = 3003 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 3004 }, 3005 .num_parents = 1, 3006 .flags = CLK_SET_RATE_PARENT, 3007 .ops = &clk_branch2_ops, 3008 }, 3009 }, 3010 }; 3011 3012 static struct clk_branch gcc_usb30_prim_sleep_clk = { 3013 .halt_reg = 0xf018, 3014 .halt_check = BRANCH_HALT, 3015 .clkr = { 3016 .enable_reg = 0xf018, 3017 .enable_mask = BIT(0), 3018 .hw.init = &(struct clk_init_data){ 3019 .name = "gcc_usb30_prim_sleep_clk", 3020 .ops = &clk_branch2_ops, 3021 }, 3022 }, 3023 }; 3024 3025 static struct clk_branch gcc_usb30_sec_master_clk = { 3026 .halt_reg = 0x10010, 3027 .halt_check = BRANCH_HALT_VOTED, 3028 .clkr = { 3029 .enable_reg = 0x10010, 3030 .enable_mask = BIT(0), 3031 .hw.init = &(struct clk_init_data){ 3032 .name = "gcc_usb30_sec_master_clk", 3033 .parent_hws = (const struct clk_hw*[]){ 3034 &gcc_usb30_sec_master_clk_src.clkr.hw, 3035 }, 3036 .num_parents = 1, 3037 .flags = CLK_SET_RATE_PARENT, 3038 .ops = &clk_branch2_ops, 3039 }, 3040 }, 3041 }; 3042 3043 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { 3044 .halt_reg = 0x1001c, 3045 .halt_check = BRANCH_HALT, 3046 .clkr = { 3047 .enable_reg = 0x1001c, 3048 .enable_mask = BIT(0), 3049 .hw.init = &(struct clk_init_data){ 3050 .name = "gcc_usb30_sec_mock_utmi_clk", 3051 .parent_data = &(const struct clk_parent_data){ 3052 .hw = 3053 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw, 3054 }, 3055 .num_parents = 1, 3056 .flags = CLK_SET_RATE_PARENT, 3057 .ops = &clk_branch2_ops, 3058 }, 3059 }, 3060 }; 3061 3062 static struct clk_branch gcc_usb30_sec_sleep_clk = { 3063 .halt_reg = 0x10018, 3064 .halt_check = BRANCH_HALT, 3065 .clkr = { 3066 .enable_reg = 0x10018, 3067 .enable_mask = BIT(0), 3068 .hw.init = &(struct clk_init_data){ 3069 .name = "gcc_usb30_sec_sleep_clk", 3070 .ops = &clk_branch2_ops, 3071 }, 3072 }, 3073 }; 3074 3075 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 3076 .halt_reg = 0xf054, 3077 .halt_check = BRANCH_HALT, 3078 .clkr = { 3079 .enable_reg = 0xf054, 3080 .enable_mask = BIT(0), 3081 .hw.init = &(struct clk_init_data){ 3082 .name = "gcc_usb3_prim_phy_aux_clk", 3083 .parent_hws = (const struct clk_hw*[]){ 3084 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3085 }, 3086 .num_parents = 1, 3087 .flags = CLK_SET_RATE_PARENT, 3088 .ops = &clk_branch2_ops, 3089 }, 3090 }, 3091 }; 3092 3093 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3094 .halt_reg = 0xf058, 3095 .halt_check = BRANCH_HALT, 3096 .clkr = { 3097 .enable_reg = 0xf058, 3098 .enable_mask = BIT(0), 3099 .hw.init = &(struct clk_init_data){ 3100 .name = "gcc_usb3_prim_phy_com_aux_clk", 3101 .parent_hws = (const struct clk_hw*[]){ 3102 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3103 }, 3104 .num_parents = 1, 3105 .flags = CLK_SET_RATE_PARENT, 3106 .ops = &clk_branch2_ops, 3107 }, 3108 }, 3109 }; 3110 3111 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3112 .halt_reg = 0xf05c, 3113 .halt_check = BRANCH_HALT_DELAY, 3114 .clkr = { 3115 .enable_reg = 0xf05c, 3116 .enable_mask = BIT(0), 3117 .hw.init = &(struct clk_init_data){ 3118 .name = "gcc_usb3_prim_phy_pipe_clk", 3119 .ops = &clk_branch2_ops, 3120 }, 3121 }, 3122 }; 3123 3124 static struct clk_branch gcc_usb3_sec_clkref_en = { 3125 .halt_reg = 0x8c010, 3126 .halt_check = BRANCH_HALT, 3127 .clkr = { 3128 .enable_reg = 0x8c010, 3129 .enable_mask = BIT(0), 3130 .hw.init = &(struct clk_init_data){ 3131 .name = "gcc_usb3_sec_clkref_en", 3132 .ops = &clk_branch2_ops, 3133 }, 3134 }, 3135 }; 3136 3137 static struct clk_branch gcc_usb3_sec_phy_aux_clk = { 3138 .halt_reg = 0x10054, 3139 .halt_check = BRANCH_HALT, 3140 .clkr = { 3141 .enable_reg = 0x10054, 3142 .enable_mask = BIT(0), 3143 .hw.init = &(struct clk_init_data){ 3144 .name = "gcc_usb3_sec_phy_aux_clk", 3145 .parent_hws = (const struct clk_hw*[]){ 3146 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 3147 }, 3148 .num_parents = 1, 3149 .flags = CLK_SET_RATE_PARENT, 3150 .ops = &clk_branch2_ops, 3151 }, 3152 }, 3153 }; 3154 3155 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { 3156 .halt_reg = 0x10058, 3157 .halt_check = BRANCH_HALT, 3158 .clkr = { 3159 .enable_reg = 0x10058, 3160 .enable_mask = BIT(0), 3161 .hw.init = &(struct clk_init_data){ 3162 .name = "gcc_usb3_sec_phy_com_aux_clk", 3163 .parent_hws = (const struct clk_hw*[]){ 3164 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 3165 }, 3166 .num_parents = 1, 3167 .flags = CLK_SET_RATE_PARENT, 3168 .ops = &clk_branch2_ops, 3169 }, 3170 }, 3171 }; 3172 3173 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { 3174 .halt_reg = 0x1005c, 3175 .halt_check = BRANCH_HALT_DELAY, 3176 .clkr = { 3177 .enable_reg = 0x1005c, 3178 .enable_mask = BIT(0), 3179 .hw.init = &(struct clk_init_data){ 3180 .name = "gcc_usb3_sec_phy_pipe_clk", 3181 .ops = &clk_branch2_ops, 3182 }, 3183 }, 3184 }; 3185 3186 static struct clk_branch gcc_video_axi0_clk = { 3187 .halt_reg = 0xb024, 3188 .halt_check = BRANCH_HALT_VOTED, 3189 .clkr = { 3190 .enable_reg = 0xb024, 3191 .enable_mask = BIT(0), 3192 .hw.init = &(struct clk_init_data){ 3193 .name = "gcc_video_axi0_clk", 3194 .ops = &clk_branch2_ops, 3195 }, 3196 }, 3197 }; 3198 3199 static struct clk_branch gcc_video_axi1_clk = { 3200 .halt_reg = 0xb028, 3201 .halt_check = BRANCH_HALT_VOTED, 3202 .clkr = { 3203 .enable_reg = 0xb028, 3204 .enable_mask = BIT(0), 3205 .hw.init = &(struct clk_init_data){ 3206 .name = "gcc_video_axi1_clk", 3207 .ops = &clk_branch2_ops, 3208 }, 3209 }, 3210 }; 3211 3212 static struct clk_branch gcc_video_xo_clk = { 3213 .halt_reg = 0xb03c, 3214 .halt_check = BRANCH_HALT, 3215 .clkr = { 3216 .enable_reg = 0xb03c, 3217 .enable_mask = BIT(0), 3218 .hw.init = &(struct clk_init_data){ 3219 .name = "gcc_video_xo_clk", 3220 .ops = &clk_branch2_ops, 3221 }, 3222 }, 3223 }; 3224 3225 static struct gdsc pcie_0_gdsc = { 3226 .gdscr = 0x6b004, 3227 .pd = { 3228 .name = "pcie_0_gdsc", 3229 }, 3230 .pwrsts = PWRSTS_OFF_ON, 3231 }; 3232 3233 static struct gdsc pcie_1_gdsc = { 3234 .gdscr = 0x8d004, 3235 .pd = { 3236 .name = "pcie_1_gdsc", 3237 }, 3238 .pwrsts = PWRSTS_OFF_ON, 3239 }; 3240 3241 static struct gdsc pcie_2_gdsc = { 3242 .gdscr = 0x6004, 3243 .pd = { 3244 .name = "pcie_2_gdsc", 3245 }, 3246 .pwrsts = PWRSTS_OFF_ON, 3247 }; 3248 3249 static struct gdsc ufs_card_gdsc = { 3250 .gdscr = 0x75004, 3251 .pd = { 3252 .name = "ufs_card_gdsc", 3253 }, 3254 .pwrsts = PWRSTS_OFF_ON, 3255 }; 3256 3257 static struct gdsc ufs_phy_gdsc = { 3258 .gdscr = 0x77004, 3259 .pd = { 3260 .name = "ufs_phy_gdsc", 3261 }, 3262 .pwrsts = PWRSTS_OFF_ON, 3263 }; 3264 3265 static struct gdsc usb30_prim_gdsc = { 3266 .gdscr = 0xf004, 3267 .pd = { 3268 .name = "usb30_prim_gdsc", 3269 }, 3270 .pwrsts = PWRSTS_OFF_ON, 3271 }; 3272 3273 static struct gdsc usb30_sec_gdsc = { 3274 .gdscr = 0x10004, 3275 .pd = { 3276 .name = "usb30_sec_gdsc", 3277 }, 3278 .pwrsts = PWRSTS_OFF_ON, 3279 }; 3280 3281 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { 3282 .gdscr = 0x7d050, 3283 .pd = { 3284 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", 3285 }, 3286 .pwrsts = PWRSTS_OFF_ON, 3287 .flags = VOTABLE, 3288 }; 3289 3290 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = { 3291 .gdscr = 0x7d058, 3292 .pd = { 3293 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", 3294 }, 3295 .pwrsts = PWRSTS_OFF_ON, 3296 .flags = VOTABLE, 3297 }; 3298 3299 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = { 3300 .gdscr = 0x7d054, 3301 .pd = { 3302 .name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc", 3303 }, 3304 .pwrsts = PWRSTS_OFF_ON, 3305 .flags = VOTABLE, 3306 }; 3307 3308 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = { 3309 .gdscr = 0x7d06c, 3310 .pd = { 3311 .name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc", 3312 }, 3313 .pwrsts = PWRSTS_OFF_ON, 3314 .flags = VOTABLE, 3315 }; 3316 3317 static struct clk_regmap *gcc_sm8250_clocks[] = { 3318 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, 3319 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, 3320 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 3321 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 3322 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, 3323 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3324 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 3325 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 3326 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 3327 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3328 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, 3329 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, 3330 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, 3331 [GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr, 3332 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, 3333 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 3334 [GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr, 3335 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3336 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, 3337 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 3338 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3339 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3340 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3341 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3342 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3343 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3344 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3345 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3346 [GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr, 3347 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3348 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3349 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, 3350 [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr, 3351 [GCC_NPU_BWMON_CFG_AHB_CLK] = &gcc_npu_bwmon_cfg_ahb_clk.clkr, 3352 [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr, 3353 [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr, 3354 [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr, 3355 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr, 3356 [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr, 3357 [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr, 3358 [GCC_PCIE2_PHY_REFGEN_CLK] = &gcc_pcie2_phy_refgen_clk.clkr, 3359 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3360 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 3361 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3362 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3363 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3364 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3365 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 3366 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 3367 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 3368 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 3369 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 3370 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 3371 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 3372 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 3373 [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr, 3374 [GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr, 3375 [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr, 3376 [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr, 3377 [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr, 3378 [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr, 3379 [GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr, 3380 [GCC_PCIE_MDM_CLKREF_EN] = &gcc_pcie_mdm_clkref_en.clkr, 3381 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, 3382 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, 3383 [GCC_PCIE_WIFI_CLKREF_EN] = &gcc_pcie_wifi_clkref_en.clkr, 3384 [GCC_PCIE_WIGIG_CLKREF_EN] = &gcc_pcie_wigig_clkref_en.clkr, 3385 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3386 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3387 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3388 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3389 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3390 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3391 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3392 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3393 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 3394 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3395 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 3396 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 3397 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3398 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3399 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3400 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3401 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3402 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3403 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3404 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3405 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3406 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3407 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3408 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3409 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 3410 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 3411 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 3412 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 3413 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3414 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3415 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3416 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3417 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3418 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3419 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3420 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3421 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3422 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3423 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3424 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3425 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3426 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3427 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 3428 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 3429 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 3430 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 3431 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 3432 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 3433 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 3434 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 3435 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 3436 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 3437 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 3438 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 3439 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 3440 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 3441 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3442 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3443 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3444 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3445 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 3446 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 3447 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3448 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3449 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3450 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3451 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3452 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 3453 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 3454 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, 3455 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 3456 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, 3457 [GCC_UFS_1X_CLKREF_EN] = &gcc_ufs_1x_clkref_en.clkr, 3458 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, 3459 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, 3460 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, 3461 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, 3462 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, 3463 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, 3464 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, 3465 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, 3466 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, 3467 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, 3468 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, 3469 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = 3470 &gcc_ufs_card_unipro_core_clk_src.clkr, 3471 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3472 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3473 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3474 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3475 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3476 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3477 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3478 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3479 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3480 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3481 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3482 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 3483 &gcc_ufs_phy_unipro_core_clk_src.clkr, 3484 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3485 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3486 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3487 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 3488 &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3489 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = 3490 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3491 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3492 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, 3493 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, 3494 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, 3495 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = 3496 &gcc_usb30_sec_mock_utmi_clk_src.clkr, 3497 [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = 3498 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr, 3499 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, 3500 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3501 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3502 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3503 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3504 [GCC_USB3_SEC_CLKREF_EN] = &gcc_usb3_sec_clkref_en.clkr, 3505 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, 3506 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, 3507 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, 3508 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, 3509 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3510 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 3511 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 3512 [GPLL0] = &gpll0.clkr, 3513 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 3514 [GPLL4] = &gpll4.clkr, 3515 [GPLL9] = &gpll9.clkr, 3516 }; 3517 3518 static struct gdsc *gcc_sm8250_gdscs[] = { 3519 [PCIE_0_GDSC] = &pcie_0_gdsc, 3520 [PCIE_1_GDSC] = &pcie_1_gdsc, 3521 [PCIE_2_GDSC] = &pcie_2_gdsc, 3522 [UFS_CARD_GDSC] = &ufs_card_gdsc, 3523 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3524 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3525 [USB30_SEC_GDSC] = &usb30_sec_gdsc, 3526 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = 3527 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, 3528 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = 3529 &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, 3530 [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = 3531 &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc, 3532 [HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC] = 3533 &hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc, 3534 }; 3535 3536 static const struct qcom_reset_map gcc_sm8250_resets[] = { 3537 [GCC_GPU_BCR] = { 0x71000 }, 3538 [GCC_MMSS_BCR] = { 0xb000 }, 3539 [GCC_NPU_BWMON_BCR] = { 0x73000 }, 3540 [GCC_NPU_BCR] = { 0x4d000 }, 3541 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3542 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 3543 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 3544 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3545 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, 3546 [GCC_PCIE_1_BCR] = { 0x8d000 }, 3547 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, 3548 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, 3549 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 3550 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 }, 3551 [GCC_PCIE_2_BCR] = { 0x6000 }, 3552 [GCC_PCIE_2_LINK_DOWN_BCR] = { 0x1f014 }, 3553 [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x1f020 }, 3554 [GCC_PCIE_2_PHY_BCR] = { 0x1f01c }, 3555 [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0x1f028 }, 3556 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 3557 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, 3558 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, 3559 [GCC_PDM_BCR] = { 0x33000 }, 3560 [GCC_PRNG_BCR] = { 0x34000 }, 3561 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, 3562 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 3563 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, 3564 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3565 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3566 [GCC_SDCC2_BCR] = { 0x14000 }, 3567 [GCC_SDCC4_BCR] = { 0x16000 }, 3568 [GCC_TSIF_BCR] = { 0x36000 }, 3569 [GCC_UFS_CARD_BCR] = { 0x75000 }, 3570 [GCC_UFS_PHY_BCR] = { 0x77000 }, 3571 [GCC_USB30_PRIM_BCR] = { 0xf000 }, 3572 [GCC_USB30_SEC_BCR] = { 0x10000 }, 3573 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 3574 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 3575 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 3576 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 3577 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3578 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3579 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 3580 [GCC_VIDEO_AXI0_CLK_ARES] = { 0xb024, 2 }, 3581 [GCC_VIDEO_AXI1_CLK_ARES] = { 0xb028, 2 }, 3582 }; 3583 3584 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3585 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3586 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3587 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3588 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3589 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3590 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3591 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 3592 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 3593 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3594 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3595 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 3596 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3597 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3598 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3599 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 3600 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 3601 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 3602 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 3603 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 3604 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 3605 }; 3606 3607 static const struct regmap_config gcc_sm8250_regmap_config = { 3608 .reg_bits = 32, 3609 .reg_stride = 4, 3610 .val_bits = 32, 3611 .max_register = 0x9c100, 3612 .fast_io = true, 3613 }; 3614 3615 static const struct qcom_cc_desc gcc_sm8250_desc = { 3616 .config = &gcc_sm8250_regmap_config, 3617 .clks = gcc_sm8250_clocks, 3618 .num_clks = ARRAY_SIZE(gcc_sm8250_clocks), 3619 .resets = gcc_sm8250_resets, 3620 .num_resets = ARRAY_SIZE(gcc_sm8250_resets), 3621 .gdscs = gcc_sm8250_gdscs, 3622 .num_gdscs = ARRAY_SIZE(gcc_sm8250_gdscs), 3623 }; 3624 3625 static const struct of_device_id gcc_sm8250_match_table[] = { 3626 { .compatible = "qcom,gcc-sm8250" }, 3627 { } 3628 }; 3629 MODULE_DEVICE_TABLE(of, gcc_sm8250_match_table); 3630 3631 static int gcc_sm8250_probe(struct platform_device *pdev) 3632 { 3633 struct regmap *regmap; 3634 int ret; 3635 3636 regmap = qcom_cc_map(pdev, &gcc_sm8250_desc); 3637 if (IS_ERR(regmap)) 3638 return PTR_ERR(regmap); 3639 3640 /* 3641 * Disable the GPLL0 active input to NPU and GPU 3642 * via MISC registers. 3643 */ 3644 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); 3645 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 3646 3647 /* 3648 * Keep the clocks always-ON 3649 * GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK, 3650 * GCC_CPUSS_DVM_BUS_CLK, GCC_GPU_CFG_AHB_CLK, 3651 * GCC_SYS_NOC_CPUSS_AHB_CLK 3652 */ 3653 regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); 3654 regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); 3655 regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); 3656 regmap_update_bits(regmap, 0x4818c, BIT(0), BIT(0)); 3657 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 3658 regmap_update_bits(regmap, 0x52000, BIT(0), BIT(0)); 3659 3660 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3661 ARRAY_SIZE(gcc_dfs_clocks)); 3662 if (ret) 3663 return ret; 3664 3665 return qcom_cc_really_probe(pdev, &gcc_sm8250_desc, regmap); 3666 } 3667 3668 static struct platform_driver gcc_sm8250_driver = { 3669 .probe = gcc_sm8250_probe, 3670 .driver = { 3671 .name = "gcc-sm8250", 3672 .of_match_table = gcc_sm8250_match_table, 3673 }, 3674 }; 3675 3676 static int __init gcc_sm8250_init(void) 3677 { 3678 return platform_driver_register(&gcc_sm8250_driver); 3679 } 3680 subsys_initcall(gcc_sm8250_init); 3681 3682 static void __exit gcc_sm8250_exit(void) 3683 { 3684 platform_driver_unregister(&gcc_sm8250_driver); 3685 } 3686 module_exit(gcc_sm8250_exit); 3687 3688 MODULE_DESCRIPTION("QTI GCC SM8250 Driver"); 3689 MODULE_LICENSE("GPL v2"); 3690