1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/err.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of_device.h> 11 #include <linux/of.h> 12 #include <linux/regmap.h> 13 14 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 15 16 #include "clk-alpha-pll.h" 17 #include "clk-branch.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "clk-regmap-divider.h" 21 #include "common.h" 22 #include "gdsc.h" 23 #include "reset.h" 24 25 enum { 26 P_BI_TCXO, 27 P_AUD_REF_CLK, 28 P_CORE_BI_PLL_TEST_SE, 29 P_GPLL0_OUT_EVEN, 30 P_GPLL0_OUT_MAIN, 31 P_GPLL4_OUT_MAIN, 32 P_GPLL9_OUT_MAIN, 33 P_SLEEP_CLK, 34 }; 35 36 static struct clk_alpha_pll gpll0 = { 37 .offset = 0x0, 38 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 39 .clkr = { 40 .enable_reg = 0x52018, 41 .enable_mask = BIT(0), 42 .hw.init = &(struct clk_init_data){ 43 .name = "gpll0", 44 .parent_data = &(const struct clk_parent_data){ 45 .fw_name = "bi_tcxo", 46 }, 47 .num_parents = 1, 48 .ops = &clk_alpha_pll_fixed_lucid_ops, 49 }, 50 }, 51 }; 52 53 static const struct clk_div_table post_div_table_gpll0_out_even[] = { 54 { 0x1, 2 }, 55 { } 56 }; 57 58 static struct clk_alpha_pll_postdiv gpll0_out_even = { 59 .offset = 0x0, 60 .post_div_shift = 8, 61 .post_div_table = post_div_table_gpll0_out_even, 62 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even), 63 .width = 4, 64 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 65 .clkr.hw.init = &(struct clk_init_data){ 66 .name = "gpll0_out_even", 67 .parent_data = &(const struct clk_parent_data){ 68 .hw = &gpll0.clkr.hw, 69 }, 70 .num_parents = 1, 71 .ops = &clk_alpha_pll_postdiv_lucid_ops, 72 }, 73 }; 74 75 static struct clk_alpha_pll gpll4 = { 76 .offset = 0x76000, 77 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 78 .clkr = { 79 .enable_reg = 0x52018, 80 .enable_mask = BIT(4), 81 .hw.init = &(struct clk_init_data){ 82 .name = "gpll4", 83 .parent_data = &(const struct clk_parent_data){ 84 .fw_name = "bi_tcxo", 85 }, 86 .num_parents = 1, 87 .ops = &clk_alpha_pll_fixed_lucid_ops, 88 }, 89 }, 90 }; 91 92 static struct clk_alpha_pll gpll9 = { 93 .offset = 0x1c000, 94 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 95 .clkr = { 96 .enable_reg = 0x52018, 97 .enable_mask = BIT(9), 98 .hw.init = &(struct clk_init_data){ 99 .name = "gpll9", 100 .parent_data = &(const struct clk_parent_data){ 101 .fw_name = "bi_tcxo", 102 }, 103 .num_parents = 1, 104 .ops = &clk_alpha_pll_fixed_lucid_ops, 105 }, 106 }, 107 }; 108 109 static const struct parent_map gcc_parent_map_0[] = { 110 { P_BI_TCXO, 0 }, 111 { P_GPLL0_OUT_MAIN, 1 }, 112 { P_GPLL0_OUT_EVEN, 6 }, 113 }; 114 115 static const struct clk_parent_data gcc_parent_data_0[] = { 116 { .fw_name = "bi_tcxo" }, 117 { .hw = &gpll0.clkr.hw }, 118 { .hw = &gpll0_out_even.clkr.hw }, 119 }; 120 121 static const struct clk_parent_data gcc_parent_data_0_ao[] = { 122 { .fw_name = "bi_tcxo_ao" }, 123 { .hw = &gpll0.clkr.hw }, 124 { .hw = &gpll0_out_even.clkr.hw }, 125 }; 126 127 static const struct parent_map gcc_parent_map_1[] = { 128 { P_BI_TCXO, 0 }, 129 { P_GPLL0_OUT_MAIN, 1 }, 130 { P_SLEEP_CLK, 5 }, 131 { P_GPLL0_OUT_EVEN, 6 }, 132 }; 133 134 static const struct clk_parent_data gcc_parent_data_1[] = { 135 { .fw_name = "bi_tcxo" }, 136 { .hw = &gpll0.clkr.hw }, 137 { .fw_name = "sleep_clk" }, 138 { .hw = &gpll0_out_even.clkr.hw }, 139 }; 140 141 static const struct parent_map gcc_parent_map_2[] = { 142 { P_BI_TCXO, 0 }, 143 { P_SLEEP_CLK, 5 }, 144 }; 145 146 static const struct clk_parent_data gcc_parent_data_2[] = { 147 { .fw_name = "bi_tcxo" }, 148 { .fw_name = "sleep_clk" }, 149 }; 150 151 static const struct parent_map gcc_parent_map_3[] = { 152 { P_BI_TCXO, 0 }, 153 }; 154 155 static const struct clk_parent_data gcc_parent_data_3[] = { 156 { .fw_name = "bi_tcxo" }, 157 }; 158 159 static const struct parent_map gcc_parent_map_4[] = { 160 { P_BI_TCXO, 0 }, 161 { P_GPLL0_OUT_MAIN, 1 }, 162 { P_GPLL9_OUT_MAIN, 2 }, 163 { P_GPLL4_OUT_MAIN, 5 }, 164 { P_GPLL0_OUT_EVEN, 6 }, 165 }; 166 167 static const struct clk_parent_data gcc_parent_data_4[] = { 168 { .fw_name = "bi_tcxo" }, 169 { .hw = &gpll0.clkr.hw }, 170 { .hw = &gpll9.clkr.hw }, 171 { .hw = &gpll4.clkr.hw }, 172 { .hw = &gpll0_out_even.clkr.hw }, 173 }; 174 175 static const struct parent_map gcc_parent_map_5[] = { 176 { P_BI_TCXO, 0 }, 177 { P_GPLL0_OUT_MAIN, 1 }, 178 { P_AUD_REF_CLK, 2 }, 179 { P_GPLL0_OUT_EVEN, 6 }, 180 }; 181 182 static const struct clk_parent_data gcc_parent_data_5[] = { 183 { .fw_name = "bi_tcxo" }, 184 { .hw = &gpll0.clkr.hw }, 185 { .fw_name = "aud_ref_clk" }, 186 { .hw = &gpll0_out_even.clkr.hw }, 187 }; 188 189 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { 190 F(19200000, P_BI_TCXO, 1, 0, 0), 191 { } 192 }; 193 194 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 195 .cmd_rcgr = 0x48010, 196 .mnd_width = 0, 197 .hid_width = 5, 198 .parent_map = gcc_parent_map_0, 199 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, 200 .clkr.hw.init = &(struct clk_init_data){ 201 .name = "gcc_cpuss_ahb_clk_src", 202 .parent_data = gcc_parent_data_0_ao, 203 .num_parents = 3, 204 .flags = CLK_SET_RATE_PARENT, 205 .ops = &clk_rcg2_ops, 206 }, 207 }; 208 209 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 210 F(19200000, P_BI_TCXO, 1, 0, 0), 211 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 212 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 213 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 214 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 215 { } 216 }; 217 218 static struct clk_rcg2 gcc_gp1_clk_src = { 219 .cmd_rcgr = 0x64004, 220 .mnd_width = 8, 221 .hid_width = 5, 222 .parent_map = gcc_parent_map_1, 223 .freq_tbl = ftbl_gcc_gp1_clk_src, 224 .clkr.hw.init = &(struct clk_init_data){ 225 .name = "gcc_gp1_clk_src", 226 .parent_data = gcc_parent_data_1, 227 .num_parents = 4, 228 .ops = &clk_rcg2_ops, 229 }, 230 }; 231 232 static struct clk_rcg2 gcc_gp2_clk_src = { 233 .cmd_rcgr = 0x65004, 234 .mnd_width = 8, 235 .hid_width = 5, 236 .parent_map = gcc_parent_map_1, 237 .freq_tbl = ftbl_gcc_gp1_clk_src, 238 .clkr.hw.init = &(struct clk_init_data){ 239 .name = "gcc_gp2_clk_src", 240 .parent_data = gcc_parent_data_1, 241 .num_parents = 4, 242 .ops = &clk_rcg2_ops, 243 }, 244 }; 245 246 static struct clk_rcg2 gcc_gp3_clk_src = { 247 .cmd_rcgr = 0x66004, 248 .mnd_width = 8, 249 .hid_width = 5, 250 .parent_map = gcc_parent_map_1, 251 .freq_tbl = ftbl_gcc_gp1_clk_src, 252 .clkr.hw.init = &(struct clk_init_data){ 253 .name = "gcc_gp3_clk_src", 254 .parent_data = gcc_parent_data_1, 255 .num_parents = 4, 256 .ops = &clk_rcg2_ops, 257 }, 258 }; 259 260 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 261 F(9600000, P_BI_TCXO, 2, 0, 0), 262 F(19200000, P_BI_TCXO, 1, 0, 0), 263 { } 264 }; 265 266 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 267 .cmd_rcgr = 0x6b038, 268 .mnd_width = 16, 269 .hid_width = 5, 270 .parent_map = gcc_parent_map_2, 271 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 272 .clkr.hw.init = &(struct clk_init_data){ 273 .name = "gcc_pcie_0_aux_clk_src", 274 .parent_data = gcc_parent_data_2, 275 .num_parents = 2, 276 .ops = &clk_rcg2_ops, 277 }, 278 }; 279 280 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 281 .cmd_rcgr = 0x8d038, 282 .mnd_width = 16, 283 .hid_width = 5, 284 .parent_map = gcc_parent_map_2, 285 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 286 .clkr.hw.init = &(struct clk_init_data){ 287 .name = "gcc_pcie_1_aux_clk_src", 288 .parent_data = gcc_parent_data_2, 289 .num_parents = 2, 290 .ops = &clk_rcg2_ops, 291 }, 292 }; 293 294 static struct clk_rcg2 gcc_pcie_2_aux_clk_src = { 295 .cmd_rcgr = 0x6038, 296 .mnd_width = 16, 297 .hid_width = 5, 298 .parent_map = gcc_parent_map_2, 299 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 300 .clkr.hw.init = &(struct clk_init_data){ 301 .name = "gcc_pcie_2_aux_clk_src", 302 .parent_data = gcc_parent_data_2, 303 .num_parents = 2, 304 .ops = &clk_rcg2_ops, 305 }, 306 }; 307 308 static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { 309 F(19200000, P_BI_TCXO, 1, 0, 0), 310 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 311 { } 312 }; 313 314 static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { 315 .cmd_rcgr = 0x6f014, 316 .mnd_width = 0, 317 .hid_width = 5, 318 .parent_map = gcc_parent_map_0, 319 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, 320 .clkr.hw.init = &(struct clk_init_data){ 321 .name = "gcc_pcie_phy_refgen_clk_src", 322 .parent_data = gcc_parent_data_0_ao, 323 .num_parents = 3, 324 .ops = &clk_rcg2_ops, 325 }, 326 }; 327 328 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 329 F(9600000, P_BI_TCXO, 2, 0, 0), 330 F(19200000, P_BI_TCXO, 1, 0, 0), 331 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 332 { } 333 }; 334 335 static struct clk_rcg2 gcc_pdm2_clk_src = { 336 .cmd_rcgr = 0x33010, 337 .mnd_width = 0, 338 .hid_width = 5, 339 .parent_map = gcc_parent_map_0, 340 .freq_tbl = ftbl_gcc_pdm2_clk_src, 341 .clkr.hw.init = &(struct clk_init_data){ 342 .name = "gcc_pdm2_clk_src", 343 .parent_data = gcc_parent_data_0, 344 .num_parents = 3, 345 .ops = &clk_rcg2_ops, 346 }, 347 }; 348 349 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 350 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 351 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 352 F(19200000, P_BI_TCXO, 1, 0, 0), 353 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 354 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 355 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 356 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 357 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 358 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 359 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 360 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 361 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 362 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), 363 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), 364 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), 365 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), 366 { } 367 }; 368 369 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 370 .name = "gcc_qupv3_wrap0_s0_clk_src", 371 .parent_data = gcc_parent_data_0, 372 .num_parents = 3, 373 .ops = &clk_rcg2_ops, 374 }; 375 376 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 377 .cmd_rcgr = 0x17010, 378 .mnd_width = 16, 379 .hid_width = 5, 380 .parent_map = gcc_parent_map_0, 381 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 382 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 383 }; 384 385 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 386 .name = "gcc_qupv3_wrap0_s1_clk_src", 387 .parent_data = gcc_parent_data_0, 388 .num_parents = 3, 389 .ops = &clk_rcg2_ops, 390 }; 391 392 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 393 .cmd_rcgr = 0x17140, 394 .mnd_width = 16, 395 .hid_width = 5, 396 .parent_map = gcc_parent_map_0, 397 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 398 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 399 }; 400 401 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = { 402 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 403 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 404 F(19200000, P_BI_TCXO, 1, 0, 0), 405 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 406 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 407 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 408 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 409 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 410 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 411 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 412 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 413 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 414 { } 415 }; 416 417 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 418 .name = "gcc_qupv3_wrap0_s2_clk_src", 419 .parent_data = gcc_parent_data_0, 420 .num_parents = 3, 421 .ops = &clk_rcg2_ops, 422 }; 423 424 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 425 .cmd_rcgr = 0x17270, 426 .mnd_width = 16, 427 .hid_width = 5, 428 .parent_map = gcc_parent_map_0, 429 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 430 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 431 }; 432 433 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 434 .name = "gcc_qupv3_wrap0_s3_clk_src", 435 .parent_data = gcc_parent_data_0, 436 .num_parents = 3, 437 .ops = &clk_rcg2_ops, 438 }; 439 440 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 441 .cmd_rcgr = 0x173a0, 442 .mnd_width = 16, 443 .hid_width = 5, 444 .parent_map = gcc_parent_map_0, 445 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 446 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 447 }; 448 449 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 450 .name = "gcc_qupv3_wrap0_s4_clk_src", 451 .parent_data = gcc_parent_data_0, 452 .num_parents = 3, 453 .ops = &clk_rcg2_ops, 454 }; 455 456 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 457 .cmd_rcgr = 0x174d0, 458 .mnd_width = 16, 459 .hid_width = 5, 460 .parent_map = gcc_parent_map_0, 461 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 462 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 463 }; 464 465 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 466 .name = "gcc_qupv3_wrap0_s5_clk_src", 467 .parent_data = gcc_parent_data_0, 468 .num_parents = 3, 469 .ops = &clk_rcg2_ops, 470 }; 471 472 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 473 .cmd_rcgr = 0x17600, 474 .mnd_width = 16, 475 .hid_width = 5, 476 .parent_map = gcc_parent_map_0, 477 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 478 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 479 }; 480 481 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 482 .name = "gcc_qupv3_wrap0_s6_clk_src", 483 .parent_data = gcc_parent_data_0, 484 .num_parents = 3, 485 .ops = &clk_rcg2_ops, 486 }; 487 488 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 489 .cmd_rcgr = 0x17730, 490 .mnd_width = 16, 491 .hid_width = 5, 492 .parent_map = gcc_parent_map_0, 493 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 494 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 495 }; 496 497 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 498 .name = "gcc_qupv3_wrap0_s7_clk_src", 499 .parent_data = gcc_parent_data_0, 500 .num_parents = 3, 501 .ops = &clk_rcg2_ops, 502 }; 503 504 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 505 .cmd_rcgr = 0x17860, 506 .mnd_width = 16, 507 .hid_width = 5, 508 .parent_map = gcc_parent_map_0, 509 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 510 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 511 }; 512 513 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 514 .name = "gcc_qupv3_wrap1_s0_clk_src", 515 .parent_data = gcc_parent_data_0, 516 .num_parents = 3, 517 .ops = &clk_rcg2_ops, 518 }; 519 520 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 521 .cmd_rcgr = 0x18010, 522 .mnd_width = 16, 523 .hid_width = 5, 524 .parent_map = gcc_parent_map_0, 525 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 526 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 527 }; 528 529 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 530 .name = "gcc_qupv3_wrap1_s1_clk_src", 531 .parent_data = gcc_parent_data_0, 532 .num_parents = 3, 533 .ops = &clk_rcg2_ops, 534 }; 535 536 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 537 .cmd_rcgr = 0x18140, 538 .mnd_width = 16, 539 .hid_width = 5, 540 .parent_map = gcc_parent_map_0, 541 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 542 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 543 }; 544 545 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 546 .name = "gcc_qupv3_wrap1_s2_clk_src", 547 .parent_data = gcc_parent_data_0, 548 .num_parents = 3, 549 .ops = &clk_rcg2_ops, 550 }; 551 552 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 553 .cmd_rcgr = 0x18270, 554 .mnd_width = 16, 555 .hid_width = 5, 556 .parent_map = gcc_parent_map_0, 557 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 558 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 559 }; 560 561 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 562 .name = "gcc_qupv3_wrap1_s3_clk_src", 563 .parent_data = gcc_parent_data_0, 564 .num_parents = 3, 565 .ops = &clk_rcg2_ops, 566 }; 567 568 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 569 .cmd_rcgr = 0x183a0, 570 .mnd_width = 16, 571 .hid_width = 5, 572 .parent_map = gcc_parent_map_0, 573 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 574 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 575 }; 576 577 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 578 .name = "gcc_qupv3_wrap1_s4_clk_src", 579 .parent_data = gcc_parent_data_0, 580 .num_parents = 3, 581 .ops = &clk_rcg2_ops, 582 }; 583 584 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 585 .cmd_rcgr = 0x184d0, 586 .mnd_width = 16, 587 .hid_width = 5, 588 .parent_map = gcc_parent_map_0, 589 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 590 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 591 }; 592 593 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 594 .name = "gcc_qupv3_wrap1_s5_clk_src", 595 .parent_data = gcc_parent_data_0, 596 .num_parents = 3, 597 .ops = &clk_rcg2_ops, 598 }; 599 600 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 601 .cmd_rcgr = 0x18600, 602 .mnd_width = 16, 603 .hid_width = 5, 604 .parent_map = gcc_parent_map_0, 605 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 606 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 607 }; 608 609 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 610 .name = "gcc_qupv3_wrap2_s0_clk_src", 611 .parent_data = gcc_parent_data_0, 612 .num_parents = 3, 613 .ops = &clk_rcg2_ops, 614 }; 615 616 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 617 .cmd_rcgr = 0x1e010, 618 .mnd_width = 16, 619 .hid_width = 5, 620 .parent_map = gcc_parent_map_0, 621 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 622 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 623 }; 624 625 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 626 .name = "gcc_qupv3_wrap2_s1_clk_src", 627 .parent_data = gcc_parent_data_0, 628 .num_parents = 3, 629 .ops = &clk_rcg2_ops, 630 }; 631 632 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 633 .cmd_rcgr = 0x1e140, 634 .mnd_width = 16, 635 .hid_width = 5, 636 .parent_map = gcc_parent_map_0, 637 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 638 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 639 }; 640 641 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 642 .name = "gcc_qupv3_wrap2_s2_clk_src", 643 .parent_data = gcc_parent_data_0, 644 .num_parents = 3, 645 .ops = &clk_rcg2_ops, 646 }; 647 648 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 649 .cmd_rcgr = 0x1e270, 650 .mnd_width = 16, 651 .hid_width = 5, 652 .parent_map = gcc_parent_map_0, 653 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 654 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 655 }; 656 657 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 658 .name = "gcc_qupv3_wrap2_s3_clk_src", 659 .parent_data = gcc_parent_data_0, 660 .num_parents = 3, 661 .ops = &clk_rcg2_ops, 662 }; 663 664 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 665 .cmd_rcgr = 0x1e3a0, 666 .mnd_width = 16, 667 .hid_width = 5, 668 .parent_map = gcc_parent_map_0, 669 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 670 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 671 }; 672 673 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 674 .name = "gcc_qupv3_wrap2_s4_clk_src", 675 .parent_data = gcc_parent_data_0, 676 .num_parents = 3, 677 .ops = &clk_rcg2_ops, 678 }; 679 680 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 681 .cmd_rcgr = 0x1e4d0, 682 .mnd_width = 16, 683 .hid_width = 5, 684 .parent_map = gcc_parent_map_0, 685 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 686 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 687 }; 688 689 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 690 .name = "gcc_qupv3_wrap2_s5_clk_src", 691 .parent_data = gcc_parent_data_0, 692 .num_parents = 3, 693 .ops = &clk_rcg2_ops, 694 }; 695 696 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 697 .cmd_rcgr = 0x1e600, 698 .mnd_width = 16, 699 .hid_width = 5, 700 .parent_map = gcc_parent_map_0, 701 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 702 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 703 }; 704 705 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 706 F(400000, P_BI_TCXO, 12, 1, 4), 707 F(19200000, P_BI_TCXO, 1, 0, 0), 708 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 709 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 710 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 711 F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0), 712 { } 713 }; 714 715 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 716 .cmd_rcgr = 0x1400c, 717 .mnd_width = 8, 718 .hid_width = 5, 719 .parent_map = gcc_parent_map_4, 720 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 721 .clkr.hw.init = &(struct clk_init_data){ 722 .name = "gcc_sdcc2_apps_clk_src", 723 .parent_data = gcc_parent_data_4, 724 .num_parents = 5, 725 .ops = &clk_rcg2_ops, 726 }, 727 }; 728 729 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 730 F(400000, P_BI_TCXO, 12, 1, 4), 731 F(19200000, P_BI_TCXO, 1, 0, 0), 732 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 733 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 734 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 735 { } 736 }; 737 738 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 739 .cmd_rcgr = 0x1600c, 740 .mnd_width = 8, 741 .hid_width = 5, 742 .parent_map = gcc_parent_map_0, 743 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 744 .clkr.hw.init = &(struct clk_init_data){ 745 .name = "gcc_sdcc4_apps_clk_src", 746 .parent_data = gcc_parent_data_0, 747 .num_parents = 3, 748 .ops = &clk_rcg2_ops, 749 }, 750 }; 751 752 static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { 753 F(105495, P_BI_TCXO, 2, 1, 91), 754 { } 755 }; 756 757 static struct clk_rcg2 gcc_tsif_ref_clk_src = { 758 .cmd_rcgr = 0x36010, 759 .mnd_width = 8, 760 .hid_width = 5, 761 .parent_map = gcc_parent_map_5, 762 .freq_tbl = ftbl_gcc_tsif_ref_clk_src, 763 .clkr.hw.init = &(struct clk_init_data){ 764 .name = "gcc_tsif_ref_clk_src", 765 .parent_data = gcc_parent_data_5, 766 .num_parents = 4, 767 .ops = &clk_rcg2_ops, 768 }, 769 }; 770 771 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { 772 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 773 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 774 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 775 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 776 { } 777 }; 778 779 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { 780 .cmd_rcgr = 0x75024, 781 .mnd_width = 8, 782 .hid_width = 5, 783 .parent_map = gcc_parent_map_0, 784 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, 785 .clkr.hw.init = &(struct clk_init_data){ 786 .name = "gcc_ufs_card_axi_clk_src", 787 .parent_data = gcc_parent_data_0, 788 .num_parents = 3, 789 .ops = &clk_rcg2_ops, 790 }, 791 }; 792 793 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { 794 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 795 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 796 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 797 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 798 { } 799 }; 800 801 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { 802 .cmd_rcgr = 0x7506c, 803 .mnd_width = 0, 804 .hid_width = 5, 805 .parent_map = gcc_parent_map_0, 806 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 807 .clkr.hw.init = &(struct clk_init_data){ 808 .name = "gcc_ufs_card_ice_core_clk_src", 809 .parent_data = gcc_parent_data_0, 810 .num_parents = 3, 811 .ops = &clk_rcg2_ops, 812 }, 813 }; 814 815 static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = { 816 F(19200000, P_BI_TCXO, 1, 0, 0), 817 { } 818 }; 819 820 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { 821 .cmd_rcgr = 0x750a0, 822 .mnd_width = 0, 823 .hid_width = 5, 824 .parent_map = gcc_parent_map_3, 825 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 826 .clkr.hw.init = &(struct clk_init_data){ 827 .name = "gcc_ufs_card_phy_aux_clk_src", 828 .parent_data = gcc_parent_data_3, 829 .num_parents = 1, 830 .ops = &clk_rcg2_ops, 831 }, 832 }; 833 834 static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { 835 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 836 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 837 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 838 { } 839 }; 840 841 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { 842 .cmd_rcgr = 0x75084, 843 .mnd_width = 0, 844 .hid_width = 5, 845 .parent_map = gcc_parent_map_0, 846 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, 847 .clkr.hw.init = &(struct clk_init_data){ 848 .name = "gcc_ufs_card_unipro_core_clk_src", 849 .parent_data = gcc_parent_data_0, 850 .num_parents = 3, 851 .ops = &clk_rcg2_ops, 852 }, 853 }; 854 855 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 856 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 857 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 858 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 859 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 860 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 861 { } 862 }; 863 864 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 865 .cmd_rcgr = 0x77024, 866 .mnd_width = 8, 867 .hid_width = 5, 868 .parent_map = gcc_parent_map_0, 869 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 870 .clkr.hw.init = &(struct clk_init_data){ 871 .name = "gcc_ufs_phy_axi_clk_src", 872 .parent_data = gcc_parent_data_0, 873 .num_parents = 3, 874 .ops = &clk_rcg2_ops, 875 }, 876 }; 877 878 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 879 .cmd_rcgr = 0x7706c, 880 .mnd_width = 0, 881 .hid_width = 5, 882 .parent_map = gcc_parent_map_0, 883 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 884 .clkr.hw.init = &(struct clk_init_data){ 885 .name = "gcc_ufs_phy_ice_core_clk_src", 886 .parent_data = gcc_parent_data_0, 887 .num_parents = 3, 888 .ops = &clk_rcg2_ops, 889 }, 890 }; 891 892 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 893 .cmd_rcgr = 0x770a0, 894 .mnd_width = 0, 895 .hid_width = 5, 896 .parent_map = gcc_parent_map_3, 897 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 898 .clkr.hw.init = &(struct clk_init_data){ 899 .name = "gcc_ufs_phy_phy_aux_clk_src", 900 .parent_data = gcc_parent_data_3, 901 .num_parents = 1, 902 .ops = &clk_rcg2_ops, 903 }, 904 }; 905 906 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 907 .cmd_rcgr = 0x77084, 908 .mnd_width = 0, 909 .hid_width = 5, 910 .parent_map = gcc_parent_map_0, 911 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 912 .clkr.hw.init = &(struct clk_init_data){ 913 .name = "gcc_ufs_phy_unipro_core_clk_src", 914 .parent_data = gcc_parent_data_0, 915 .num_parents = 3, 916 .ops = &clk_rcg2_ops, 917 }, 918 }; 919 920 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 921 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), 922 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), 923 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 924 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 925 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 926 { } 927 }; 928 929 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 930 .cmd_rcgr = 0xf020, 931 .mnd_width = 8, 932 .hid_width = 5, 933 .parent_map = gcc_parent_map_0, 934 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 935 .clkr.hw.init = &(struct clk_init_data){ 936 .name = "gcc_usb30_prim_master_clk_src", 937 .parent_data = gcc_parent_data_0, 938 .num_parents = 3, 939 .ops = &clk_rcg2_ops, 940 }, 941 }; 942 943 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 944 .cmd_rcgr = 0xf038, 945 .mnd_width = 0, 946 .hid_width = 5, 947 .parent_map = gcc_parent_map_0, 948 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 949 .clkr.hw.init = &(struct clk_init_data){ 950 .name = "gcc_usb30_prim_mock_utmi_clk_src", 951 .parent_data = gcc_parent_data_0, 952 .num_parents = 3, 953 .ops = &clk_rcg2_ops, 954 }, 955 }; 956 957 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { 958 .cmd_rcgr = 0x10020, 959 .mnd_width = 8, 960 .hid_width = 5, 961 .parent_map = gcc_parent_map_0, 962 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 963 .clkr.hw.init = &(struct clk_init_data){ 964 .name = "gcc_usb30_sec_master_clk_src", 965 .parent_data = gcc_parent_data_0, 966 .num_parents = 3, 967 .ops = &clk_rcg2_ops, 968 }, 969 }; 970 971 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { 972 .cmd_rcgr = 0x10038, 973 .mnd_width = 0, 974 .hid_width = 5, 975 .parent_map = gcc_parent_map_0, 976 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 977 .clkr.hw.init = &(struct clk_init_data){ 978 .name = "gcc_usb30_sec_mock_utmi_clk_src", 979 .parent_data = gcc_parent_data_0, 980 .num_parents = 3, 981 .ops = &clk_rcg2_ops, 982 }, 983 }; 984 985 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 986 .cmd_rcgr = 0xf064, 987 .mnd_width = 0, 988 .hid_width = 5, 989 .parent_map = gcc_parent_map_2, 990 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 991 .clkr.hw.init = &(struct clk_init_data){ 992 .name = "gcc_usb3_prim_phy_aux_clk_src", 993 .parent_data = gcc_parent_data_2, 994 .num_parents = 2, 995 .ops = &clk_rcg2_ops, 996 }, 997 }; 998 999 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { 1000 .cmd_rcgr = 0x10064, 1001 .mnd_width = 0, 1002 .hid_width = 5, 1003 .parent_map = gcc_parent_map_2, 1004 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 1005 .clkr.hw.init = &(struct clk_init_data){ 1006 .name = "gcc_usb3_sec_phy_aux_clk_src", 1007 .parent_data = gcc_parent_data_2, 1008 .num_parents = 2, 1009 .ops = &clk_rcg2_ops, 1010 }, 1011 }; 1012 1013 static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = { 1014 .reg = 0x48028, 1015 .shift = 0, 1016 .width = 4, 1017 .clkr.hw.init = &(struct clk_init_data) { 1018 .name = "gcc_cpuss_ahb_postdiv_clk_src", 1019 .parent_data = &(const struct clk_parent_data){ 1020 .hw = &gcc_cpuss_ahb_clk_src.clkr.hw, 1021 }, 1022 .num_parents = 1, 1023 .flags = CLK_SET_RATE_PARENT, 1024 .ops = &clk_regmap_div_ro_ops, 1025 }, 1026 }; 1027 1028 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1029 .reg = 0xf050, 1030 .shift = 0, 1031 .width = 2, 1032 .clkr.hw.init = &(struct clk_init_data) { 1033 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1034 .parent_data = &(const struct clk_parent_data){ 1035 .hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1036 }, 1037 .num_parents = 1, 1038 .flags = CLK_SET_RATE_PARENT, 1039 .ops = &clk_regmap_div_ro_ops, 1040 }, 1041 }; 1042 1043 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = { 1044 .reg = 0x10050, 1045 .shift = 0, 1046 .width = 2, 1047 .clkr.hw.init = &(struct clk_init_data) { 1048 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src", 1049 .parent_data = &(const struct clk_parent_data){ 1050 .hw = &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, 1051 }, 1052 .num_parents = 1, 1053 .flags = CLK_SET_RATE_PARENT, 1054 .ops = &clk_regmap_div_ro_ops, 1055 }, 1056 }; 1057 1058 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { 1059 .halt_reg = 0x9000c, 1060 .halt_check = BRANCH_HALT_VOTED, 1061 .clkr = { 1062 .enable_reg = 0x9000c, 1063 .enable_mask = BIT(0), 1064 .hw.init = &(struct clk_init_data){ 1065 .name = "gcc_aggre_noc_pcie_tbu_clk", 1066 .ops = &clk_branch2_ops, 1067 }, 1068 }, 1069 }; 1070 1071 static struct clk_branch gcc_aggre_ufs_card_axi_clk = { 1072 .halt_reg = 0x750cc, 1073 .halt_check = BRANCH_HALT_VOTED, 1074 .hwcg_reg = 0x750cc, 1075 .hwcg_bit = 1, 1076 .clkr = { 1077 .enable_reg = 0x750cc, 1078 .enable_mask = BIT(0), 1079 .hw.init = &(struct clk_init_data){ 1080 .name = "gcc_aggre_ufs_card_axi_clk", 1081 .parent_data = &(const struct clk_parent_data){ 1082 .hw = &gcc_ufs_card_axi_clk_src.clkr.hw, 1083 }, 1084 .num_parents = 1, 1085 .flags = CLK_SET_RATE_PARENT, 1086 .ops = &clk_branch2_ops, 1087 }, 1088 }, 1089 }; 1090 1091 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1092 .halt_reg = 0x770cc, 1093 .halt_check = BRANCH_HALT_VOTED, 1094 .hwcg_reg = 0x770cc, 1095 .hwcg_bit = 1, 1096 .clkr = { 1097 .enable_reg = 0x770cc, 1098 .enable_mask = BIT(0), 1099 .hw.init = &(struct clk_init_data){ 1100 .name = "gcc_aggre_ufs_phy_axi_clk", 1101 .parent_data = &(const struct clk_parent_data){ 1102 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 1103 }, 1104 .num_parents = 1, 1105 .flags = CLK_SET_RATE_PARENT, 1106 .ops = &clk_branch2_ops, 1107 }, 1108 }, 1109 }; 1110 1111 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1112 .halt_reg = 0xf080, 1113 .halt_check = BRANCH_HALT_VOTED, 1114 .clkr = { 1115 .enable_reg = 0xf080, 1116 .enable_mask = BIT(0), 1117 .hw.init = &(struct clk_init_data){ 1118 .name = "gcc_aggre_usb3_prim_axi_clk", 1119 .parent_data = &(const struct clk_parent_data){ 1120 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 1121 }, 1122 .num_parents = 1, 1123 .flags = CLK_SET_RATE_PARENT, 1124 .ops = &clk_branch2_ops, 1125 }, 1126 }, 1127 }; 1128 1129 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { 1130 .halt_reg = 0x10080, 1131 .halt_check = BRANCH_HALT_VOTED, 1132 .clkr = { 1133 .enable_reg = 0x10080, 1134 .enable_mask = BIT(0), 1135 .hw.init = &(struct clk_init_data){ 1136 .name = "gcc_aggre_usb3_sec_axi_clk", 1137 .parent_data = &(const struct clk_parent_data){ 1138 .hw = &gcc_usb30_sec_master_clk_src.clkr.hw, 1139 }, 1140 .num_parents = 1, 1141 .flags = CLK_SET_RATE_PARENT, 1142 .ops = &clk_branch2_ops, 1143 }, 1144 }, 1145 }; 1146 1147 static struct clk_branch gcc_boot_rom_ahb_clk = { 1148 .halt_reg = 0x38004, 1149 .halt_check = BRANCH_HALT_VOTED, 1150 .hwcg_reg = 0x38004, 1151 .hwcg_bit = 1, 1152 .clkr = { 1153 .enable_reg = 0x52000, 1154 .enable_mask = BIT(10), 1155 .hw.init = &(struct clk_init_data){ 1156 .name = "gcc_boot_rom_ahb_clk", 1157 .ops = &clk_branch2_ops, 1158 }, 1159 }, 1160 }; 1161 1162 static struct clk_branch gcc_camera_hf_axi_clk = { 1163 .halt_reg = 0xb02c, 1164 .halt_check = BRANCH_HALT_VOTED, 1165 .clkr = { 1166 .enable_reg = 0xb02c, 1167 .enable_mask = BIT(0), 1168 .hw.init = &(struct clk_init_data){ 1169 .name = "gcc_camera_hf_axi_clk", 1170 .ops = &clk_branch2_ops, 1171 }, 1172 }, 1173 }; 1174 1175 static struct clk_branch gcc_camera_sf_axi_clk = { 1176 .halt_reg = 0xb030, 1177 .halt_check = BRANCH_HALT_VOTED, 1178 .clkr = { 1179 .enable_reg = 0xb030, 1180 .enable_mask = BIT(0), 1181 .hw.init = &(struct clk_init_data){ 1182 .name = "gcc_camera_sf_axi_clk", 1183 .ops = &clk_branch2_ops, 1184 }, 1185 }, 1186 }; 1187 1188 static struct clk_branch gcc_camera_xo_clk = { 1189 .halt_reg = 0xb040, 1190 .halt_check = BRANCH_HALT, 1191 .clkr = { 1192 .enable_reg = 0xb040, 1193 .enable_mask = BIT(0), 1194 .hw.init = &(struct clk_init_data){ 1195 .name = "gcc_camera_xo_clk", 1196 .ops = &clk_branch2_ops, 1197 }, 1198 }, 1199 }; 1200 1201 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1202 .halt_reg = 0xf07c, 1203 .halt_check = BRANCH_HALT_VOTED, 1204 .clkr = { 1205 .enable_reg = 0xf07c, 1206 .enable_mask = BIT(0), 1207 .hw.init = &(struct clk_init_data){ 1208 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1209 .parent_data = &(const struct clk_parent_data){ 1210 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 1211 }, 1212 .num_parents = 1, 1213 .flags = CLK_SET_RATE_PARENT, 1214 .ops = &clk_branch2_ops, 1215 }, 1216 }, 1217 }; 1218 1219 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { 1220 .halt_reg = 0x1007c, 1221 .halt_check = BRANCH_HALT_VOTED, 1222 .clkr = { 1223 .enable_reg = 0x1007c, 1224 .enable_mask = BIT(0), 1225 .hw.init = &(struct clk_init_data){ 1226 .name = "gcc_cfg_noc_usb3_sec_axi_clk", 1227 .parent_data = &(const struct clk_parent_data){ 1228 .hw = &gcc_usb30_sec_master_clk_src.clkr.hw, 1229 }, 1230 .num_parents = 1, 1231 .flags = CLK_SET_RATE_PARENT, 1232 .ops = &clk_branch2_ops, 1233 }, 1234 }, 1235 }; 1236 1237 static struct clk_branch gcc_cpuss_ahb_clk = { 1238 .halt_reg = 0x48000, 1239 .halt_check = BRANCH_HALT_VOTED, 1240 .clkr = { 1241 .enable_reg = 0x52000, 1242 .enable_mask = BIT(21), 1243 .hw.init = &(struct clk_init_data){ 1244 .name = "gcc_cpuss_ahb_clk", 1245 .parent_data = &(const struct clk_parent_data){ 1246 .hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, 1247 }, 1248 .num_parents = 1, 1249 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 1250 .ops = &clk_branch2_ops, 1251 }, 1252 }, 1253 }; 1254 1255 static struct clk_branch gcc_cpuss_rbcpr_clk = { 1256 .halt_reg = 0x48004, 1257 .halt_check = BRANCH_HALT, 1258 .clkr = { 1259 .enable_reg = 0x48004, 1260 .enable_mask = BIT(0), 1261 .hw.init = &(struct clk_init_data){ 1262 .name = "gcc_cpuss_rbcpr_clk", 1263 .ops = &clk_branch2_ops, 1264 }, 1265 }, 1266 }; 1267 1268 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1269 .halt_reg = 0x71154, 1270 .halt_check = BRANCH_HALT_VOTED, 1271 .clkr = { 1272 .enable_reg = 0x71154, 1273 .enable_mask = BIT(0), 1274 .hw.init = &(struct clk_init_data){ 1275 .name = "gcc_ddrss_gpu_axi_clk", 1276 .ops = &clk_branch2_ops, 1277 }, 1278 }, 1279 }; 1280 1281 static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = { 1282 .halt_reg = 0x8d058, 1283 .halt_check = BRANCH_HALT_VOTED, 1284 .clkr = { 1285 .enable_reg = 0x8d058, 1286 .enable_mask = BIT(0), 1287 .hw.init = &(struct clk_init_data){ 1288 .name = "gcc_ddrss_pcie_sf_tbu_clk", 1289 .ops = &clk_branch2_ops, 1290 }, 1291 }, 1292 }; 1293 1294 static struct clk_branch gcc_disp_hf_axi_clk = { 1295 .halt_reg = 0xb034, 1296 .halt_check = BRANCH_HALT_VOTED, 1297 .clkr = { 1298 .enable_reg = 0xb034, 1299 .enable_mask = BIT(0), 1300 .hw.init = &(struct clk_init_data){ 1301 .name = "gcc_disp_hf_axi_clk", 1302 .ops = &clk_branch2_ops, 1303 }, 1304 }, 1305 }; 1306 1307 static struct clk_branch gcc_disp_sf_axi_clk = { 1308 .halt_reg = 0xb038, 1309 .halt_check = BRANCH_HALT_VOTED, 1310 .clkr = { 1311 .enable_reg = 0xb038, 1312 .enable_mask = BIT(0), 1313 .hw.init = &(struct clk_init_data){ 1314 .name = "gcc_disp_sf_axi_clk", 1315 .ops = &clk_branch2_ops, 1316 }, 1317 }, 1318 }; 1319 1320 static struct clk_branch gcc_disp_xo_clk = { 1321 .halt_reg = 0xb044, 1322 .halt_check = BRANCH_HALT, 1323 .clkr = { 1324 .enable_reg = 0xb044, 1325 .enable_mask = BIT(0), 1326 .hw.init = &(struct clk_init_data){ 1327 .name = "gcc_disp_xo_clk", 1328 .ops = &clk_branch2_ops, 1329 }, 1330 }, 1331 }; 1332 1333 static struct clk_branch gcc_gp1_clk = { 1334 .halt_reg = 0x64000, 1335 .halt_check = BRANCH_HALT, 1336 .clkr = { 1337 .enable_reg = 0x64000, 1338 .enable_mask = BIT(0), 1339 .hw.init = &(struct clk_init_data){ 1340 .name = "gcc_gp1_clk", 1341 .parent_data = &(const struct clk_parent_data){ 1342 .hw = &gcc_gp1_clk_src.clkr.hw, 1343 }, 1344 .num_parents = 1, 1345 .flags = CLK_SET_RATE_PARENT, 1346 .ops = &clk_branch2_ops, 1347 }, 1348 }, 1349 }; 1350 1351 static struct clk_branch gcc_gp2_clk = { 1352 .halt_reg = 0x65000, 1353 .halt_check = BRANCH_HALT, 1354 .clkr = { 1355 .enable_reg = 0x65000, 1356 .enable_mask = BIT(0), 1357 .hw.init = &(struct clk_init_data){ 1358 .name = "gcc_gp2_clk", 1359 .parent_data = &(const struct clk_parent_data){ 1360 .hw = &gcc_gp2_clk_src.clkr.hw, 1361 }, 1362 .num_parents = 1, 1363 .flags = CLK_SET_RATE_PARENT, 1364 .ops = &clk_branch2_ops, 1365 }, 1366 }, 1367 }; 1368 1369 static struct clk_branch gcc_gp3_clk = { 1370 .halt_reg = 0x66000, 1371 .halt_check = BRANCH_HALT, 1372 .clkr = { 1373 .enable_reg = 0x66000, 1374 .enable_mask = BIT(0), 1375 .hw.init = &(struct clk_init_data){ 1376 .name = "gcc_gp3_clk", 1377 .parent_data = &(const struct clk_parent_data){ 1378 .hw = &gcc_gp3_clk_src.clkr.hw, 1379 }, 1380 .num_parents = 1, 1381 .flags = CLK_SET_RATE_PARENT, 1382 .ops = &clk_branch2_ops, 1383 }, 1384 }, 1385 }; 1386 1387 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1388 .halt_check = BRANCH_HALT_DELAY, 1389 .clkr = { 1390 .enable_reg = 0x52000, 1391 .enable_mask = BIT(15), 1392 .hw.init = &(struct clk_init_data){ 1393 .name = "gcc_gpu_gpll0_clk_src", 1394 .parent_data = &(const struct clk_parent_data){ 1395 .hw = &gpll0.clkr.hw, 1396 }, 1397 .num_parents = 1, 1398 .flags = CLK_SET_RATE_PARENT, 1399 .ops = &clk_branch2_ops, 1400 }, 1401 }, 1402 }; 1403 1404 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1405 .halt_check = BRANCH_HALT_DELAY, 1406 .clkr = { 1407 .enable_reg = 0x52000, 1408 .enable_mask = BIT(16), 1409 .hw.init = &(struct clk_init_data){ 1410 .name = "gcc_gpu_gpll0_div_clk_src", 1411 .parent_data = &(const struct clk_parent_data){ 1412 .hw = &gpll0_out_even.clkr.hw, 1413 }, 1414 .num_parents = 1, 1415 .flags = CLK_SET_RATE_PARENT, 1416 .ops = &clk_branch2_ops, 1417 }, 1418 }, 1419 }; 1420 1421 static struct clk_branch gcc_gpu_iref_en = { 1422 .halt_reg = 0x8c014, 1423 .halt_check = BRANCH_HALT, 1424 .clkr = { 1425 .enable_reg = 0x8c014, 1426 .enable_mask = BIT(0), 1427 .hw.init = &(struct clk_init_data){ 1428 .name = "gcc_gpu_iref_en", 1429 .ops = &clk_branch2_ops, 1430 }, 1431 }, 1432 }; 1433 1434 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1435 .halt_reg = 0x7100c, 1436 .halt_check = BRANCH_HALT_VOTED, 1437 .clkr = { 1438 .enable_reg = 0x7100c, 1439 .enable_mask = BIT(0), 1440 .hw.init = &(struct clk_init_data){ 1441 .name = "gcc_gpu_memnoc_gfx_clk", 1442 .ops = &clk_branch2_ops, 1443 }, 1444 }, 1445 }; 1446 1447 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1448 .halt_reg = 0x71018, 1449 .halt_check = BRANCH_HALT, 1450 .clkr = { 1451 .enable_reg = 0x71018, 1452 .enable_mask = BIT(0), 1453 .hw.init = &(struct clk_init_data){ 1454 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1455 .ops = &clk_branch2_ops, 1456 }, 1457 }, 1458 }; 1459 1460 static struct clk_branch gcc_npu_axi_clk = { 1461 .halt_reg = 0x4d008, 1462 .halt_check = BRANCH_HALT_VOTED, 1463 .clkr = { 1464 .enable_reg = 0x4d008, 1465 .enable_mask = BIT(0), 1466 .hw.init = &(struct clk_init_data){ 1467 .name = "gcc_npu_axi_clk", 1468 .ops = &clk_branch2_ops, 1469 }, 1470 }, 1471 }; 1472 1473 static struct clk_branch gcc_npu_bwmon_axi_clk = { 1474 .halt_reg = 0x73008, 1475 .halt_check = BRANCH_HALT_VOTED, 1476 .clkr = { 1477 .enable_reg = 0x73008, 1478 .enable_mask = BIT(0), 1479 .hw.init = &(struct clk_init_data){ 1480 .name = "gcc_npu_bwmon_axi_clk", 1481 .ops = &clk_branch2_ops, 1482 }, 1483 }, 1484 }; 1485 1486 static struct clk_branch gcc_npu_bwmon_cfg_ahb_clk = { 1487 .halt_reg = 0x73004, 1488 .halt_check = BRANCH_HALT, 1489 .clkr = { 1490 .enable_reg = 0x73004, 1491 .enable_mask = BIT(0), 1492 .hw.init = &(struct clk_init_data){ 1493 .name = "gcc_npu_bwmon_cfg_ahb_clk", 1494 .ops = &clk_branch2_ops, 1495 }, 1496 }, 1497 }; 1498 1499 static struct clk_branch gcc_npu_cfg_ahb_clk = { 1500 .halt_reg = 0x4d004, 1501 .halt_check = BRANCH_HALT, 1502 .hwcg_reg = 0x4d004, 1503 .hwcg_bit = 1, 1504 .clkr = { 1505 .enable_reg = 0x4d004, 1506 .enable_mask = BIT(0), 1507 .hw.init = &(struct clk_init_data){ 1508 .name = "gcc_npu_cfg_ahb_clk", 1509 .ops = &clk_branch2_ops, 1510 }, 1511 }, 1512 }; 1513 1514 static struct clk_branch gcc_npu_dma_clk = { 1515 .halt_reg = 0x4d00c, 1516 .halt_check = BRANCH_HALT_VOTED, 1517 .clkr = { 1518 .enable_reg = 0x4d00c, 1519 .enable_mask = BIT(0), 1520 .hw.init = &(struct clk_init_data){ 1521 .name = "gcc_npu_dma_clk", 1522 .ops = &clk_branch2_ops, 1523 }, 1524 }, 1525 }; 1526 1527 static struct clk_branch gcc_npu_gpll0_clk_src = { 1528 .halt_check = BRANCH_HALT_DELAY, 1529 .clkr = { 1530 .enable_reg = 0x52000, 1531 .enable_mask = BIT(18), 1532 .hw.init = &(struct clk_init_data){ 1533 .name = "gcc_npu_gpll0_clk_src", 1534 .parent_data = &(const struct clk_parent_data){ 1535 .hw = &gpll0.clkr.hw, 1536 }, 1537 .num_parents = 1, 1538 .flags = CLK_SET_RATE_PARENT, 1539 .ops = &clk_branch2_ops, 1540 }, 1541 }, 1542 }; 1543 1544 static struct clk_branch gcc_npu_gpll0_div_clk_src = { 1545 .halt_check = BRANCH_HALT_DELAY, 1546 .clkr = { 1547 .enable_reg = 0x52000, 1548 .enable_mask = BIT(19), 1549 .hw.init = &(struct clk_init_data){ 1550 .name = "gcc_npu_gpll0_div_clk_src", 1551 .parent_data = &(const struct clk_parent_data){ 1552 .hw = &gpll0_out_even.clkr.hw, 1553 }, 1554 .num_parents = 1, 1555 .flags = CLK_SET_RATE_PARENT, 1556 .ops = &clk_branch2_ops, 1557 }, 1558 }, 1559 }; 1560 1561 static struct clk_branch gcc_pcie0_phy_refgen_clk = { 1562 .halt_reg = 0x6f02c, 1563 .halt_check = BRANCH_HALT, 1564 .clkr = { 1565 .enable_reg = 0x6f02c, 1566 .enable_mask = BIT(0), 1567 .hw.init = &(struct clk_init_data){ 1568 .name = "gcc_pcie0_phy_refgen_clk", 1569 .parent_data = &(const struct clk_parent_data){ 1570 .hw = &gcc_pcie_phy_refgen_clk_src.clkr.hw, 1571 }, 1572 .num_parents = 1, 1573 .flags = CLK_SET_RATE_PARENT, 1574 .ops = &clk_branch2_ops, 1575 }, 1576 }, 1577 }; 1578 1579 static struct clk_branch gcc_pcie1_phy_refgen_clk = { 1580 .halt_reg = 0x6f030, 1581 .halt_check = BRANCH_HALT, 1582 .clkr = { 1583 .enable_reg = 0x6f030, 1584 .enable_mask = BIT(0), 1585 .hw.init = &(struct clk_init_data){ 1586 .name = "gcc_pcie1_phy_refgen_clk", 1587 .parent_data = &(const struct clk_parent_data){ 1588 .hw = &gcc_pcie_phy_refgen_clk_src.clkr.hw, 1589 }, 1590 .num_parents = 1, 1591 .flags = CLK_SET_RATE_PARENT, 1592 .ops = &clk_branch2_ops, 1593 }, 1594 }, 1595 }; 1596 1597 static struct clk_branch gcc_pcie2_phy_refgen_clk = { 1598 .halt_reg = 0x6f034, 1599 .halt_check = BRANCH_HALT, 1600 .clkr = { 1601 .enable_reg = 0x6f034, 1602 .enable_mask = BIT(0), 1603 .hw.init = &(struct clk_init_data){ 1604 .name = "gcc_pcie2_phy_refgen_clk", 1605 .parent_data = &(const struct clk_parent_data){ 1606 .hw = &gcc_pcie_phy_refgen_clk_src.clkr.hw, 1607 }, 1608 .num_parents = 1, 1609 .flags = CLK_SET_RATE_PARENT, 1610 .ops = &clk_branch2_ops, 1611 }, 1612 }, 1613 }; 1614 1615 static struct clk_branch gcc_pcie_0_aux_clk = { 1616 .halt_reg = 0x6b028, 1617 .halt_check = BRANCH_HALT_VOTED, 1618 .clkr = { 1619 .enable_reg = 0x52008, 1620 .enable_mask = BIT(3), 1621 .hw.init = &(struct clk_init_data){ 1622 .name = "gcc_pcie_0_aux_clk", 1623 .parent_data = &(const struct clk_parent_data){ 1624 .hw = &gcc_pcie_0_aux_clk_src.clkr.hw, 1625 }, 1626 .num_parents = 1, 1627 .flags = CLK_SET_RATE_PARENT, 1628 .ops = &clk_branch2_ops, 1629 }, 1630 }, 1631 }; 1632 1633 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1634 .halt_reg = 0x6b024, 1635 .halt_check = BRANCH_HALT_VOTED, 1636 .hwcg_reg = 0x6b024, 1637 .hwcg_bit = 1, 1638 .clkr = { 1639 .enable_reg = 0x52008, 1640 .enable_mask = BIT(2), 1641 .hw.init = &(struct clk_init_data){ 1642 .name = "gcc_pcie_0_cfg_ahb_clk", 1643 .ops = &clk_branch2_ops, 1644 }, 1645 }, 1646 }; 1647 1648 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1649 .halt_reg = 0x6b01c, 1650 .halt_check = BRANCH_HALT_VOTED, 1651 .clkr = { 1652 .enable_reg = 0x52008, 1653 .enable_mask = BIT(1), 1654 .hw.init = &(struct clk_init_data){ 1655 .name = "gcc_pcie_0_mstr_axi_clk", 1656 .ops = &clk_branch2_ops, 1657 }, 1658 }, 1659 }; 1660 1661 static struct clk_branch gcc_pcie_0_pipe_clk = { 1662 .halt_reg = 0x6b02c, 1663 .halt_check = BRANCH_HALT_SKIP, 1664 .clkr = { 1665 .enable_reg = 0x52008, 1666 .enable_mask = BIT(4), 1667 .hw.init = &(struct clk_init_data){ 1668 .name = "gcc_pcie_0_pipe_clk", 1669 .ops = &clk_branch2_ops, 1670 }, 1671 }, 1672 }; 1673 1674 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1675 .halt_reg = 0x6b014, 1676 .halt_check = BRANCH_HALT_VOTED, 1677 .hwcg_reg = 0x6b014, 1678 .hwcg_bit = 1, 1679 .clkr = { 1680 .enable_reg = 0x52008, 1681 .enable_mask = BIT(0), 1682 .hw.init = &(struct clk_init_data){ 1683 .name = "gcc_pcie_0_slv_axi_clk", 1684 .ops = &clk_branch2_ops, 1685 }, 1686 }, 1687 }; 1688 1689 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1690 .halt_reg = 0x6b010, 1691 .halt_check = BRANCH_HALT_VOTED, 1692 .clkr = { 1693 .enable_reg = 0x52008, 1694 .enable_mask = BIT(5), 1695 .hw.init = &(struct clk_init_data){ 1696 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1697 .ops = &clk_branch2_ops, 1698 }, 1699 }, 1700 }; 1701 1702 static struct clk_branch gcc_pcie_1_aux_clk = { 1703 .halt_reg = 0x8d028, 1704 .halt_check = BRANCH_HALT_VOTED, 1705 .clkr = { 1706 .enable_reg = 0x52000, 1707 .enable_mask = BIT(29), 1708 .hw.init = &(struct clk_init_data){ 1709 .name = "gcc_pcie_1_aux_clk", 1710 .parent_data = &(const struct clk_parent_data){ 1711 .hw = &gcc_pcie_1_aux_clk_src.clkr.hw, 1712 }, 1713 .num_parents = 1, 1714 .flags = CLK_SET_RATE_PARENT, 1715 .ops = &clk_branch2_ops, 1716 }, 1717 }, 1718 }; 1719 1720 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1721 .halt_reg = 0x8d024, 1722 .halt_check = BRANCH_HALT_VOTED, 1723 .hwcg_reg = 0x8d024, 1724 .hwcg_bit = 1, 1725 .clkr = { 1726 .enable_reg = 0x52000, 1727 .enable_mask = BIT(28), 1728 .hw.init = &(struct clk_init_data){ 1729 .name = "gcc_pcie_1_cfg_ahb_clk", 1730 .ops = &clk_branch2_ops, 1731 }, 1732 }, 1733 }; 1734 1735 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1736 .halt_reg = 0x8d01c, 1737 .halt_check = BRANCH_HALT_VOTED, 1738 .clkr = { 1739 .enable_reg = 0x52000, 1740 .enable_mask = BIT(27), 1741 .hw.init = &(struct clk_init_data){ 1742 .name = "gcc_pcie_1_mstr_axi_clk", 1743 .ops = &clk_branch2_ops, 1744 }, 1745 }, 1746 }; 1747 1748 static struct clk_branch gcc_pcie_1_pipe_clk = { 1749 .halt_reg = 0x8d02c, 1750 .halt_check = BRANCH_HALT_SKIP, 1751 .clkr = { 1752 .enable_reg = 0x52000, 1753 .enable_mask = BIT(30), 1754 .hw.init = &(struct clk_init_data){ 1755 .name = "gcc_pcie_1_pipe_clk", 1756 .ops = &clk_branch2_ops, 1757 }, 1758 }, 1759 }; 1760 1761 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1762 .halt_reg = 0x8d014, 1763 .halt_check = BRANCH_HALT_VOTED, 1764 .hwcg_reg = 0x8d014, 1765 .hwcg_bit = 1, 1766 .clkr = { 1767 .enable_reg = 0x52000, 1768 .enable_mask = BIT(26), 1769 .hw.init = &(struct clk_init_data){ 1770 .name = "gcc_pcie_1_slv_axi_clk", 1771 .ops = &clk_branch2_ops, 1772 }, 1773 }, 1774 }; 1775 1776 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 1777 .halt_reg = 0x8d010, 1778 .halt_check = BRANCH_HALT_VOTED, 1779 .clkr = { 1780 .enable_reg = 0x52000, 1781 .enable_mask = BIT(25), 1782 .hw.init = &(struct clk_init_data){ 1783 .name = "gcc_pcie_1_slv_q2a_axi_clk", 1784 .ops = &clk_branch2_ops, 1785 }, 1786 }, 1787 }; 1788 1789 static struct clk_branch gcc_pcie_2_aux_clk = { 1790 .halt_reg = 0x6028, 1791 .halt_check = BRANCH_HALT_VOTED, 1792 .clkr = { 1793 .enable_reg = 0x52010, 1794 .enable_mask = BIT(14), 1795 .hw.init = &(struct clk_init_data){ 1796 .name = "gcc_pcie_2_aux_clk", 1797 .parent_data = &(const struct clk_parent_data){ 1798 .hw = &gcc_pcie_2_aux_clk_src.clkr.hw, 1799 }, 1800 .num_parents = 1, 1801 .flags = CLK_SET_RATE_PARENT, 1802 .ops = &clk_branch2_ops, 1803 }, 1804 }, 1805 }; 1806 1807 static struct clk_branch gcc_pcie_2_cfg_ahb_clk = { 1808 .halt_reg = 0x6024, 1809 .halt_check = BRANCH_HALT_VOTED, 1810 .hwcg_reg = 0x6024, 1811 .hwcg_bit = 1, 1812 .clkr = { 1813 .enable_reg = 0x52010, 1814 .enable_mask = BIT(13), 1815 .hw.init = &(struct clk_init_data){ 1816 .name = "gcc_pcie_2_cfg_ahb_clk", 1817 .ops = &clk_branch2_ops, 1818 }, 1819 }, 1820 }; 1821 1822 static struct clk_branch gcc_pcie_2_mstr_axi_clk = { 1823 .halt_reg = 0x601c, 1824 .halt_check = BRANCH_HALT_VOTED, 1825 .clkr = { 1826 .enable_reg = 0x52010, 1827 .enable_mask = BIT(12), 1828 .hw.init = &(struct clk_init_data){ 1829 .name = "gcc_pcie_2_mstr_axi_clk", 1830 .ops = &clk_branch2_ops, 1831 }, 1832 }, 1833 }; 1834 1835 static struct clk_branch gcc_pcie_2_pipe_clk = { 1836 .halt_reg = 0x602c, 1837 .halt_check = BRANCH_HALT_SKIP, 1838 .clkr = { 1839 .enable_reg = 0x52010, 1840 .enable_mask = BIT(15), 1841 .hw.init = &(struct clk_init_data){ 1842 .name = "gcc_pcie_2_pipe_clk", 1843 .ops = &clk_branch2_ops, 1844 }, 1845 }, 1846 }; 1847 1848 static struct clk_branch gcc_pcie_2_slv_axi_clk = { 1849 .halt_reg = 0x6014, 1850 .halt_check = BRANCH_HALT_VOTED, 1851 .hwcg_reg = 0x6014, 1852 .hwcg_bit = 1, 1853 .clkr = { 1854 .enable_reg = 0x52010, 1855 .enable_mask = BIT(11), 1856 .hw.init = &(struct clk_init_data){ 1857 .name = "gcc_pcie_2_slv_axi_clk", 1858 .ops = &clk_branch2_ops, 1859 }, 1860 }, 1861 }; 1862 1863 static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = { 1864 .halt_reg = 0x6010, 1865 .halt_check = BRANCH_HALT_VOTED, 1866 .clkr = { 1867 .enable_reg = 0x52010, 1868 .enable_mask = BIT(10), 1869 .hw.init = &(struct clk_init_data){ 1870 .name = "gcc_pcie_2_slv_q2a_axi_clk", 1871 .ops = &clk_branch2_ops, 1872 }, 1873 }, 1874 }; 1875 1876 static struct clk_branch gcc_pcie_mdm_clkref_en = { 1877 .halt_reg = 0x8c00c, 1878 .halt_check = BRANCH_HALT, 1879 .clkr = { 1880 .enable_reg = 0x8c00c, 1881 .enable_mask = BIT(0), 1882 .hw.init = &(struct clk_init_data){ 1883 .name = "gcc_pcie_mdm_clkref_en", 1884 .ops = &clk_branch2_ops, 1885 }, 1886 }, 1887 }; 1888 1889 static struct clk_branch gcc_pcie_phy_aux_clk = { 1890 .halt_reg = 0x6f004, 1891 .halt_check = BRANCH_HALT, 1892 .clkr = { 1893 .enable_reg = 0x6f004, 1894 .enable_mask = BIT(0), 1895 .hw.init = &(struct clk_init_data){ 1896 .name = "gcc_pcie_phy_aux_clk", 1897 .parent_data = &(const struct clk_parent_data){ 1898 .hw = &gcc_pcie_0_aux_clk_src.clkr.hw, 1899 }, 1900 .num_parents = 1, 1901 .flags = CLK_SET_RATE_PARENT, 1902 .ops = &clk_branch2_ops, 1903 }, 1904 }, 1905 }; 1906 1907 static struct clk_branch gcc_pcie_wifi_clkref_en = { 1908 .halt_reg = 0x8c004, 1909 .halt_check = BRANCH_HALT, 1910 .clkr = { 1911 .enable_reg = 0x8c004, 1912 .enable_mask = BIT(0), 1913 .hw.init = &(struct clk_init_data){ 1914 .name = "gcc_pcie_wifi_clkref_en", 1915 .ops = &clk_branch2_ops, 1916 }, 1917 }, 1918 }; 1919 1920 static struct clk_branch gcc_pcie_wigig_clkref_en = { 1921 .halt_reg = 0x8c008, 1922 .halt_check = BRANCH_HALT, 1923 .clkr = { 1924 .enable_reg = 0x8c008, 1925 .enable_mask = BIT(0), 1926 .hw.init = &(struct clk_init_data){ 1927 .name = "gcc_pcie_wigig_clkref_en", 1928 .ops = &clk_branch2_ops, 1929 }, 1930 }, 1931 }; 1932 1933 static struct clk_branch gcc_pdm2_clk = { 1934 .halt_reg = 0x3300c, 1935 .halt_check = BRANCH_HALT, 1936 .clkr = { 1937 .enable_reg = 0x3300c, 1938 .enable_mask = BIT(0), 1939 .hw.init = &(struct clk_init_data){ 1940 .name = "gcc_pdm2_clk", 1941 .parent_data = &(const struct clk_parent_data){ 1942 .hw = &gcc_pdm2_clk_src.clkr.hw, 1943 }, 1944 .num_parents = 1, 1945 .flags = CLK_SET_RATE_PARENT, 1946 .ops = &clk_branch2_ops, 1947 }, 1948 }, 1949 }; 1950 1951 static struct clk_branch gcc_pdm_ahb_clk = { 1952 .halt_reg = 0x33004, 1953 .halt_check = BRANCH_HALT, 1954 .hwcg_reg = 0x33004, 1955 .hwcg_bit = 1, 1956 .clkr = { 1957 .enable_reg = 0x33004, 1958 .enable_mask = BIT(0), 1959 .hw.init = &(struct clk_init_data){ 1960 .name = "gcc_pdm_ahb_clk", 1961 .ops = &clk_branch2_ops, 1962 }, 1963 }, 1964 }; 1965 1966 static struct clk_branch gcc_pdm_xo4_clk = { 1967 .halt_reg = 0x33008, 1968 .halt_check = BRANCH_HALT, 1969 .clkr = { 1970 .enable_reg = 0x33008, 1971 .enable_mask = BIT(0), 1972 .hw.init = &(struct clk_init_data){ 1973 .name = "gcc_pdm_xo4_clk", 1974 .ops = &clk_branch2_ops, 1975 }, 1976 }, 1977 }; 1978 1979 static struct clk_branch gcc_prng_ahb_clk = { 1980 .halt_reg = 0x34004, 1981 .halt_check = BRANCH_HALT_VOTED, 1982 .clkr = { 1983 .enable_reg = 0x52000, 1984 .enable_mask = BIT(13), 1985 .hw.init = &(struct clk_init_data){ 1986 .name = "gcc_prng_ahb_clk", 1987 .ops = &clk_branch2_ops, 1988 }, 1989 }, 1990 }; 1991 1992 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 1993 .halt_reg = 0xb018, 1994 .halt_check = BRANCH_HALT_VOTED, 1995 .hwcg_reg = 0xb018, 1996 .hwcg_bit = 1, 1997 .clkr = { 1998 .enable_reg = 0xb018, 1999 .enable_mask = BIT(0), 2000 .hw.init = &(struct clk_init_data){ 2001 .name = "gcc_qmip_camera_nrt_ahb_clk", 2002 .ops = &clk_branch2_ops, 2003 }, 2004 }, 2005 }; 2006 2007 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2008 .halt_reg = 0xb01c, 2009 .halt_check = BRANCH_HALT_VOTED, 2010 .hwcg_reg = 0xb01c, 2011 .hwcg_bit = 1, 2012 .clkr = { 2013 .enable_reg = 0xb01c, 2014 .enable_mask = BIT(0), 2015 .hw.init = &(struct clk_init_data){ 2016 .name = "gcc_qmip_camera_rt_ahb_clk", 2017 .ops = &clk_branch2_ops, 2018 }, 2019 }, 2020 }; 2021 2022 static struct clk_branch gcc_qmip_disp_ahb_clk = { 2023 .halt_reg = 0xb020, 2024 .halt_check = BRANCH_HALT_VOTED, 2025 .hwcg_reg = 0xb020, 2026 .hwcg_bit = 1, 2027 .clkr = { 2028 .enable_reg = 0xb020, 2029 .enable_mask = BIT(0), 2030 .hw.init = &(struct clk_init_data){ 2031 .name = "gcc_qmip_disp_ahb_clk", 2032 .ops = &clk_branch2_ops, 2033 }, 2034 }, 2035 }; 2036 2037 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 2038 .halt_reg = 0xb010, 2039 .halt_check = BRANCH_HALT_VOTED, 2040 .hwcg_reg = 0xb010, 2041 .hwcg_bit = 1, 2042 .clkr = { 2043 .enable_reg = 0xb010, 2044 .enable_mask = BIT(0), 2045 .hw.init = &(struct clk_init_data){ 2046 .name = "gcc_qmip_video_cvp_ahb_clk", 2047 .ops = &clk_branch2_ops, 2048 }, 2049 }, 2050 }; 2051 2052 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2053 .halt_reg = 0xb014, 2054 .halt_check = BRANCH_HALT_VOTED, 2055 .hwcg_reg = 0xb014, 2056 .hwcg_bit = 1, 2057 .clkr = { 2058 .enable_reg = 0xb014, 2059 .enable_mask = BIT(0), 2060 .hw.init = &(struct clk_init_data){ 2061 .name = "gcc_qmip_video_vcodec_ahb_clk", 2062 .ops = &clk_branch2_ops, 2063 }, 2064 }, 2065 }; 2066 2067 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2068 .halt_reg = 0x23008, 2069 .halt_check = BRANCH_HALT_VOTED, 2070 .clkr = { 2071 .enable_reg = 0x52008, 2072 .enable_mask = BIT(9), 2073 .hw.init = &(struct clk_init_data){ 2074 .name = "gcc_qupv3_wrap0_core_2x_clk", 2075 .ops = &clk_branch2_ops, 2076 }, 2077 }, 2078 }; 2079 2080 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2081 .halt_reg = 0x23000, 2082 .halt_check = BRANCH_HALT_VOTED, 2083 .clkr = { 2084 .enable_reg = 0x52008, 2085 .enable_mask = BIT(8), 2086 .hw.init = &(struct clk_init_data){ 2087 .name = "gcc_qupv3_wrap0_core_clk", 2088 .ops = &clk_branch2_ops, 2089 }, 2090 }, 2091 }; 2092 2093 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2094 .halt_reg = 0x1700c, 2095 .halt_check = BRANCH_HALT_VOTED, 2096 .clkr = { 2097 .enable_reg = 0x52008, 2098 .enable_mask = BIT(10), 2099 .hw.init = &(struct clk_init_data){ 2100 .name = "gcc_qupv3_wrap0_s0_clk", 2101 .parent_data = &(const struct clk_parent_data){ 2102 .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 2103 }, 2104 .num_parents = 1, 2105 .flags = CLK_SET_RATE_PARENT, 2106 .ops = &clk_branch2_ops, 2107 }, 2108 }, 2109 }; 2110 2111 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2112 .halt_reg = 0x1713c, 2113 .halt_check = BRANCH_HALT_VOTED, 2114 .clkr = { 2115 .enable_reg = 0x52008, 2116 .enable_mask = BIT(11), 2117 .hw.init = &(struct clk_init_data){ 2118 .name = "gcc_qupv3_wrap0_s1_clk", 2119 .parent_data = &(const struct clk_parent_data){ 2120 .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 2121 }, 2122 .num_parents = 1, 2123 .flags = CLK_SET_RATE_PARENT, 2124 .ops = &clk_branch2_ops, 2125 }, 2126 }, 2127 }; 2128 2129 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2130 .halt_reg = 0x1726c, 2131 .halt_check = BRANCH_HALT_VOTED, 2132 .clkr = { 2133 .enable_reg = 0x52008, 2134 .enable_mask = BIT(12), 2135 .hw.init = &(struct clk_init_data){ 2136 .name = "gcc_qupv3_wrap0_s2_clk", 2137 .parent_data = &(const struct clk_parent_data){ 2138 .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2139 }, 2140 .num_parents = 1, 2141 .flags = CLK_SET_RATE_PARENT, 2142 .ops = &clk_branch2_ops, 2143 }, 2144 }, 2145 }; 2146 2147 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2148 .halt_reg = 0x1739c, 2149 .halt_check = BRANCH_HALT_VOTED, 2150 .clkr = { 2151 .enable_reg = 0x52008, 2152 .enable_mask = BIT(13), 2153 .hw.init = &(struct clk_init_data){ 2154 .name = "gcc_qupv3_wrap0_s3_clk", 2155 .parent_data = &(const struct clk_parent_data){ 2156 .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2157 }, 2158 .num_parents = 1, 2159 .flags = CLK_SET_RATE_PARENT, 2160 .ops = &clk_branch2_ops, 2161 }, 2162 }, 2163 }; 2164 2165 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2166 .halt_reg = 0x174cc, 2167 .halt_check = BRANCH_HALT_VOTED, 2168 .clkr = { 2169 .enable_reg = 0x52008, 2170 .enable_mask = BIT(14), 2171 .hw.init = &(struct clk_init_data){ 2172 .name = "gcc_qupv3_wrap0_s4_clk", 2173 .parent_data = &(const struct clk_parent_data){ 2174 .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2175 }, 2176 .num_parents = 1, 2177 .flags = CLK_SET_RATE_PARENT, 2178 .ops = &clk_branch2_ops, 2179 }, 2180 }, 2181 }; 2182 2183 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2184 .halt_reg = 0x175fc, 2185 .halt_check = BRANCH_HALT_VOTED, 2186 .clkr = { 2187 .enable_reg = 0x52008, 2188 .enable_mask = BIT(15), 2189 .hw.init = &(struct clk_init_data){ 2190 .name = "gcc_qupv3_wrap0_s5_clk", 2191 .parent_data = &(const struct clk_parent_data){ 2192 .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2193 }, 2194 .num_parents = 1, 2195 .flags = CLK_SET_RATE_PARENT, 2196 .ops = &clk_branch2_ops, 2197 }, 2198 }, 2199 }; 2200 2201 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 2202 .halt_reg = 0x1772c, 2203 .halt_check = BRANCH_HALT_VOTED, 2204 .clkr = { 2205 .enable_reg = 0x52008, 2206 .enable_mask = BIT(16), 2207 .hw.init = &(struct clk_init_data){ 2208 .name = "gcc_qupv3_wrap0_s6_clk", 2209 .parent_data = &(const struct clk_parent_data){ 2210 .hw = &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 2211 }, 2212 .num_parents = 1, 2213 .flags = CLK_SET_RATE_PARENT, 2214 .ops = &clk_branch2_ops, 2215 }, 2216 }, 2217 }; 2218 2219 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 2220 .halt_reg = 0x1785c, 2221 .halt_check = BRANCH_HALT_VOTED, 2222 .clkr = { 2223 .enable_reg = 0x52008, 2224 .enable_mask = BIT(17), 2225 .hw.init = &(struct clk_init_data){ 2226 .name = "gcc_qupv3_wrap0_s7_clk", 2227 .parent_data = &(const struct clk_parent_data){ 2228 .hw = &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 2229 }, 2230 .num_parents = 1, 2231 .flags = CLK_SET_RATE_PARENT, 2232 .ops = &clk_branch2_ops, 2233 }, 2234 }, 2235 }; 2236 2237 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2238 .halt_reg = 0x23140, 2239 .halt_check = BRANCH_HALT_VOTED, 2240 .clkr = { 2241 .enable_reg = 0x52008, 2242 .enable_mask = BIT(18), 2243 .hw.init = &(struct clk_init_data){ 2244 .name = "gcc_qupv3_wrap1_core_2x_clk", 2245 .ops = &clk_branch2_ops, 2246 }, 2247 }, 2248 }; 2249 2250 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2251 .halt_reg = 0x23138, 2252 .halt_check = BRANCH_HALT_VOTED, 2253 .clkr = { 2254 .enable_reg = 0x52008, 2255 .enable_mask = BIT(19), 2256 .hw.init = &(struct clk_init_data){ 2257 .name = "gcc_qupv3_wrap1_core_clk", 2258 .ops = &clk_branch2_ops, 2259 }, 2260 }, 2261 }; 2262 2263 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2264 .halt_reg = 0x1800c, 2265 .halt_check = BRANCH_HALT_VOTED, 2266 .clkr = { 2267 .enable_reg = 0x52008, 2268 .enable_mask = BIT(22), 2269 .hw.init = &(struct clk_init_data){ 2270 .name = "gcc_qupv3_wrap1_s0_clk", 2271 .parent_data = &(const struct clk_parent_data){ 2272 .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2273 }, 2274 .num_parents = 1, 2275 .flags = CLK_SET_RATE_PARENT, 2276 .ops = &clk_branch2_ops, 2277 }, 2278 }, 2279 }; 2280 2281 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2282 .halt_reg = 0x1813c, 2283 .halt_check = BRANCH_HALT_VOTED, 2284 .clkr = { 2285 .enable_reg = 0x52008, 2286 .enable_mask = BIT(23), 2287 .hw.init = &(struct clk_init_data){ 2288 .name = "gcc_qupv3_wrap1_s1_clk", 2289 .parent_data = &(const struct clk_parent_data){ 2290 .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2291 }, 2292 .num_parents = 1, 2293 .flags = CLK_SET_RATE_PARENT, 2294 .ops = &clk_branch2_ops, 2295 }, 2296 }, 2297 }; 2298 2299 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2300 .halt_reg = 0x1826c, 2301 .halt_check = BRANCH_HALT_VOTED, 2302 .clkr = { 2303 .enable_reg = 0x52008, 2304 .enable_mask = BIT(24), 2305 .hw.init = &(struct clk_init_data){ 2306 .name = "gcc_qupv3_wrap1_s2_clk", 2307 .parent_data = &(const struct clk_parent_data){ 2308 .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2309 }, 2310 .num_parents = 1, 2311 .flags = CLK_SET_RATE_PARENT, 2312 .ops = &clk_branch2_ops, 2313 }, 2314 }, 2315 }; 2316 2317 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2318 .halt_reg = 0x1839c, 2319 .halt_check = BRANCH_HALT_VOTED, 2320 .clkr = { 2321 .enable_reg = 0x52008, 2322 .enable_mask = BIT(25), 2323 .hw.init = &(struct clk_init_data){ 2324 .name = "gcc_qupv3_wrap1_s3_clk", 2325 .parent_data = &(const struct clk_parent_data){ 2326 .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2327 }, 2328 .num_parents = 1, 2329 .flags = CLK_SET_RATE_PARENT, 2330 .ops = &clk_branch2_ops, 2331 }, 2332 }, 2333 }; 2334 2335 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2336 .halt_reg = 0x184cc, 2337 .halt_check = BRANCH_HALT_VOTED, 2338 .clkr = { 2339 .enable_reg = 0x52008, 2340 .enable_mask = BIT(26), 2341 .hw.init = &(struct clk_init_data){ 2342 .name = "gcc_qupv3_wrap1_s4_clk", 2343 .parent_data = &(const struct clk_parent_data){ 2344 .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2345 }, 2346 .num_parents = 1, 2347 .flags = CLK_SET_RATE_PARENT, 2348 .ops = &clk_branch2_ops, 2349 }, 2350 }, 2351 }; 2352 2353 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2354 .halt_reg = 0x185fc, 2355 .halt_check = BRANCH_HALT_VOTED, 2356 .clkr = { 2357 .enable_reg = 0x52008, 2358 .enable_mask = BIT(27), 2359 .hw.init = &(struct clk_init_data){ 2360 .name = "gcc_qupv3_wrap1_s5_clk", 2361 .parent_data = &(const struct clk_parent_data){ 2362 .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2363 }, 2364 .num_parents = 1, 2365 .flags = CLK_SET_RATE_PARENT, 2366 .ops = &clk_branch2_ops, 2367 }, 2368 }, 2369 }; 2370 2371 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 2372 .halt_reg = 0x23278, 2373 .halt_check = BRANCH_HALT_VOTED, 2374 .clkr = { 2375 .enable_reg = 0x52010, 2376 .enable_mask = BIT(3), 2377 .hw.init = &(struct clk_init_data){ 2378 .name = "gcc_qupv3_wrap2_core_2x_clk", 2379 .ops = &clk_branch2_ops, 2380 }, 2381 }, 2382 }; 2383 2384 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 2385 .halt_reg = 0x23270, 2386 .halt_check = BRANCH_HALT_VOTED, 2387 .clkr = { 2388 .enable_reg = 0x52010, 2389 .enable_mask = BIT(0), 2390 .hw.init = &(struct clk_init_data){ 2391 .name = "gcc_qupv3_wrap2_core_clk", 2392 .ops = &clk_branch2_ops, 2393 }, 2394 }, 2395 }; 2396 2397 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 2398 .halt_reg = 0x1e00c, 2399 .halt_check = BRANCH_HALT_VOTED, 2400 .clkr = { 2401 .enable_reg = 0x52010, 2402 .enable_mask = BIT(4), 2403 .hw.init = &(struct clk_init_data){ 2404 .name = "gcc_qupv3_wrap2_s0_clk", 2405 .parent_data = &(const struct clk_parent_data){ 2406 .hw = &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 2407 }, 2408 .num_parents = 1, 2409 .flags = CLK_SET_RATE_PARENT, 2410 .ops = &clk_branch2_ops, 2411 }, 2412 }, 2413 }; 2414 2415 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 2416 .halt_reg = 0x1e13c, 2417 .halt_check = BRANCH_HALT_VOTED, 2418 .clkr = { 2419 .enable_reg = 0x52010, 2420 .enable_mask = BIT(5), 2421 .hw.init = &(struct clk_init_data){ 2422 .name = "gcc_qupv3_wrap2_s1_clk", 2423 .parent_data = &(const struct clk_parent_data){ 2424 .hw = &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 2425 }, 2426 .num_parents = 1, 2427 .flags = CLK_SET_RATE_PARENT, 2428 .ops = &clk_branch2_ops, 2429 }, 2430 }, 2431 }; 2432 2433 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 2434 .halt_reg = 0x1e26c, 2435 .halt_check = BRANCH_HALT_VOTED, 2436 .clkr = { 2437 .enable_reg = 0x52010, 2438 .enable_mask = BIT(6), 2439 .hw.init = &(struct clk_init_data){ 2440 .name = "gcc_qupv3_wrap2_s2_clk", 2441 .parent_data = &(const struct clk_parent_data){ 2442 .hw = &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 2443 }, 2444 .num_parents = 1, 2445 .flags = CLK_SET_RATE_PARENT, 2446 .ops = &clk_branch2_ops, 2447 }, 2448 }, 2449 }; 2450 2451 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 2452 .halt_reg = 0x1e39c, 2453 .halt_check = BRANCH_HALT_VOTED, 2454 .clkr = { 2455 .enable_reg = 0x52010, 2456 .enable_mask = BIT(7), 2457 .hw.init = &(struct clk_init_data){ 2458 .name = "gcc_qupv3_wrap2_s3_clk", 2459 .parent_data = &(const struct clk_parent_data){ 2460 .hw = &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 2461 }, 2462 .num_parents = 1, 2463 .flags = CLK_SET_RATE_PARENT, 2464 .ops = &clk_branch2_ops, 2465 }, 2466 }, 2467 }; 2468 2469 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 2470 .halt_reg = 0x1e4cc, 2471 .halt_check = BRANCH_HALT_VOTED, 2472 .clkr = { 2473 .enable_reg = 0x52010, 2474 .enable_mask = BIT(8), 2475 .hw.init = &(struct clk_init_data){ 2476 .name = "gcc_qupv3_wrap2_s4_clk", 2477 .parent_data = &(const struct clk_parent_data){ 2478 .hw = &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 2479 }, 2480 .num_parents = 1, 2481 .flags = CLK_SET_RATE_PARENT, 2482 .ops = &clk_branch2_ops, 2483 }, 2484 }, 2485 }; 2486 2487 static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 2488 .halt_reg = 0x1e5fc, 2489 .halt_check = BRANCH_HALT_VOTED, 2490 .clkr = { 2491 .enable_reg = 0x52010, 2492 .enable_mask = BIT(9), 2493 .hw.init = &(struct clk_init_data){ 2494 .name = "gcc_qupv3_wrap2_s5_clk", 2495 .parent_data = &(const struct clk_parent_data){ 2496 .hw = &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 2497 }, 2498 .num_parents = 1, 2499 .flags = CLK_SET_RATE_PARENT, 2500 .ops = &clk_branch2_ops, 2501 }, 2502 }, 2503 }; 2504 2505 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2506 .halt_reg = 0x17004, 2507 .halt_check = BRANCH_HALT_VOTED, 2508 .clkr = { 2509 .enable_reg = 0x52008, 2510 .enable_mask = BIT(6), 2511 .hw.init = &(struct clk_init_data){ 2512 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2513 .ops = &clk_branch2_ops, 2514 }, 2515 }, 2516 }; 2517 2518 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2519 .halt_reg = 0x17008, 2520 .halt_check = BRANCH_HALT_VOTED, 2521 .hwcg_reg = 0x17008, 2522 .hwcg_bit = 1, 2523 .clkr = { 2524 .enable_reg = 0x52008, 2525 .enable_mask = BIT(7), 2526 .hw.init = &(struct clk_init_data){ 2527 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2528 .ops = &clk_branch2_ops, 2529 }, 2530 }, 2531 }; 2532 2533 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2534 .halt_reg = 0x18004, 2535 .halt_check = BRANCH_HALT_VOTED, 2536 .clkr = { 2537 .enable_reg = 0x52008, 2538 .enable_mask = BIT(20), 2539 .hw.init = &(struct clk_init_data){ 2540 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2541 .ops = &clk_branch2_ops, 2542 }, 2543 }, 2544 }; 2545 2546 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2547 .halt_reg = 0x18008, 2548 .halt_check = BRANCH_HALT_VOTED, 2549 .hwcg_reg = 0x18008, 2550 .hwcg_bit = 1, 2551 .clkr = { 2552 .enable_reg = 0x52008, 2553 .enable_mask = BIT(21), 2554 .hw.init = &(struct clk_init_data){ 2555 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2556 .ops = &clk_branch2_ops, 2557 }, 2558 }, 2559 }; 2560 2561 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 2562 .halt_reg = 0x1e004, 2563 .halt_check = BRANCH_HALT_VOTED, 2564 .clkr = { 2565 .enable_reg = 0x52010, 2566 .enable_mask = BIT(2), 2567 .hw.init = &(struct clk_init_data){ 2568 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 2569 .ops = &clk_branch2_ops, 2570 }, 2571 }, 2572 }; 2573 2574 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 2575 .halt_reg = 0x1e008, 2576 .halt_check = BRANCH_HALT_VOTED, 2577 .hwcg_reg = 0x1e008, 2578 .hwcg_bit = 1, 2579 .clkr = { 2580 .enable_reg = 0x52010, 2581 .enable_mask = BIT(1), 2582 .hw.init = &(struct clk_init_data){ 2583 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 2584 .ops = &clk_branch2_ops, 2585 }, 2586 }, 2587 }; 2588 2589 static struct clk_branch gcc_sdcc2_ahb_clk = { 2590 .halt_reg = 0x14008, 2591 .halt_check = BRANCH_HALT, 2592 .clkr = { 2593 .enable_reg = 0x14008, 2594 .enable_mask = BIT(0), 2595 .hw.init = &(struct clk_init_data){ 2596 .name = "gcc_sdcc2_ahb_clk", 2597 .ops = &clk_branch2_ops, 2598 }, 2599 }, 2600 }; 2601 2602 static struct clk_branch gcc_sdcc2_apps_clk = { 2603 .halt_reg = 0x14004, 2604 .halt_check = BRANCH_HALT, 2605 .clkr = { 2606 .enable_reg = 0x14004, 2607 .enable_mask = BIT(0), 2608 .hw.init = &(struct clk_init_data){ 2609 .name = "gcc_sdcc2_apps_clk", 2610 .parent_data = &(const struct clk_parent_data){ 2611 .hw = &gcc_sdcc2_apps_clk_src.clkr.hw, 2612 }, 2613 .num_parents = 1, 2614 .flags = CLK_SET_RATE_PARENT, 2615 .ops = &clk_branch2_ops, 2616 }, 2617 }, 2618 }; 2619 2620 static struct clk_branch gcc_sdcc4_ahb_clk = { 2621 .halt_reg = 0x16008, 2622 .halt_check = BRANCH_HALT, 2623 .clkr = { 2624 .enable_reg = 0x16008, 2625 .enable_mask = BIT(0), 2626 .hw.init = &(struct clk_init_data){ 2627 .name = "gcc_sdcc4_ahb_clk", 2628 .ops = &clk_branch2_ops, 2629 }, 2630 }, 2631 }; 2632 2633 static struct clk_branch gcc_sdcc4_apps_clk = { 2634 .halt_reg = 0x16004, 2635 .halt_check = BRANCH_HALT, 2636 .clkr = { 2637 .enable_reg = 0x16004, 2638 .enable_mask = BIT(0), 2639 .hw.init = &(struct clk_init_data){ 2640 .name = "gcc_sdcc4_apps_clk", 2641 .parent_data = &(const struct clk_parent_data){ 2642 .hw = &gcc_sdcc4_apps_clk_src.clkr.hw, 2643 }, 2644 .num_parents = 1, 2645 .flags = CLK_SET_RATE_PARENT, 2646 .ops = &clk_branch2_ops, 2647 }, 2648 }, 2649 }; 2650 2651 static struct clk_branch gcc_tsif_ahb_clk = { 2652 .halt_reg = 0x36004, 2653 .halt_check = BRANCH_HALT_VOTED, 2654 .clkr = { 2655 .enable_reg = 0x36004, 2656 .enable_mask = BIT(0), 2657 .hw.init = &(struct clk_init_data){ 2658 .name = "gcc_tsif_ahb_clk", 2659 .ops = &clk_branch2_ops, 2660 }, 2661 }, 2662 }; 2663 2664 static struct clk_branch gcc_tsif_inactivity_timers_clk = { 2665 .halt_reg = 0x3600c, 2666 .halt_check = BRANCH_HALT, 2667 .clkr = { 2668 .enable_reg = 0x3600c, 2669 .enable_mask = BIT(0), 2670 .hw.init = &(struct clk_init_data){ 2671 .name = "gcc_tsif_inactivity_timers_clk", 2672 .ops = &clk_branch2_ops, 2673 }, 2674 }, 2675 }; 2676 2677 static struct clk_branch gcc_tsif_ref_clk = { 2678 .halt_reg = 0x36008, 2679 .halt_check = BRANCH_HALT, 2680 .clkr = { 2681 .enable_reg = 0x36008, 2682 .enable_mask = BIT(0), 2683 .hw.init = &(struct clk_init_data){ 2684 .name = "gcc_tsif_ref_clk", 2685 .parent_data = &(const struct clk_parent_data){ 2686 .hw = &gcc_tsif_ref_clk_src.clkr.hw, 2687 }, 2688 .num_parents = 1, 2689 .flags = CLK_SET_RATE_PARENT, 2690 .ops = &clk_branch2_ops, 2691 }, 2692 }, 2693 }; 2694 2695 static struct clk_branch gcc_ufs_1x_clkref_en = { 2696 .halt_reg = 0x8c000, 2697 .halt_check = BRANCH_HALT, 2698 .clkr = { 2699 .enable_reg = 0x8c000, 2700 .enable_mask = BIT(0), 2701 .hw.init = &(struct clk_init_data){ 2702 .name = "gcc_ufs_1x_clkref_en", 2703 .ops = &clk_branch2_ops, 2704 }, 2705 }, 2706 }; 2707 2708 static struct clk_branch gcc_ufs_card_ahb_clk = { 2709 .halt_reg = 0x75018, 2710 .halt_check = BRANCH_HALT_VOTED, 2711 .hwcg_reg = 0x75018, 2712 .hwcg_bit = 1, 2713 .clkr = { 2714 .enable_reg = 0x75018, 2715 .enable_mask = BIT(0), 2716 .hw.init = &(struct clk_init_data){ 2717 .name = "gcc_ufs_card_ahb_clk", 2718 .ops = &clk_branch2_ops, 2719 }, 2720 }, 2721 }; 2722 2723 static struct clk_branch gcc_ufs_card_axi_clk = { 2724 .halt_reg = 0x75010, 2725 .halt_check = BRANCH_HALT, 2726 .hwcg_reg = 0x75010, 2727 .hwcg_bit = 1, 2728 .clkr = { 2729 .enable_reg = 0x75010, 2730 .enable_mask = BIT(0), 2731 .hw.init = &(struct clk_init_data){ 2732 .name = "gcc_ufs_card_axi_clk", 2733 .parent_data = &(const struct clk_parent_data){ 2734 .hw = &gcc_ufs_card_axi_clk_src.clkr.hw, 2735 }, 2736 .num_parents = 1, 2737 .flags = CLK_SET_RATE_PARENT, 2738 .ops = &clk_branch2_ops, 2739 }, 2740 }, 2741 }; 2742 2743 static struct clk_branch gcc_ufs_card_ice_core_clk = { 2744 .halt_reg = 0x75064, 2745 .halt_check = BRANCH_HALT_VOTED, 2746 .hwcg_reg = 0x75064, 2747 .hwcg_bit = 1, 2748 .clkr = { 2749 .enable_reg = 0x75064, 2750 .enable_mask = BIT(0), 2751 .hw.init = &(struct clk_init_data){ 2752 .name = "gcc_ufs_card_ice_core_clk", 2753 .parent_data = &(const struct clk_parent_data){ 2754 .hw = &gcc_ufs_card_ice_core_clk_src.clkr.hw, 2755 }, 2756 .num_parents = 1, 2757 .flags = CLK_SET_RATE_PARENT, 2758 .ops = &clk_branch2_ops, 2759 }, 2760 }, 2761 }; 2762 2763 static struct clk_branch gcc_ufs_card_phy_aux_clk = { 2764 .halt_reg = 0x7509c, 2765 .halt_check = BRANCH_HALT, 2766 .hwcg_reg = 0x7509c, 2767 .hwcg_bit = 1, 2768 .clkr = { 2769 .enable_reg = 0x7509c, 2770 .enable_mask = BIT(0), 2771 .hw.init = &(struct clk_init_data){ 2772 .name = "gcc_ufs_card_phy_aux_clk", 2773 .parent_data = &(const struct clk_parent_data){ 2774 .hw = &gcc_ufs_card_phy_aux_clk_src.clkr.hw, 2775 }, 2776 .num_parents = 1, 2777 .flags = CLK_SET_RATE_PARENT, 2778 .ops = &clk_branch2_ops, 2779 }, 2780 }, 2781 }; 2782 2783 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { 2784 .halt_reg = 0x75020, 2785 .halt_check = BRANCH_HALT_DELAY, 2786 .clkr = { 2787 .enable_reg = 0x75020, 2788 .enable_mask = BIT(0), 2789 .hw.init = &(struct clk_init_data){ 2790 .name = "gcc_ufs_card_rx_symbol_0_clk", 2791 .ops = &clk_branch2_ops, 2792 }, 2793 }, 2794 }; 2795 2796 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { 2797 .halt_reg = 0x750b8, 2798 .halt_check = BRANCH_HALT_DELAY, 2799 .clkr = { 2800 .enable_reg = 0x750b8, 2801 .enable_mask = BIT(0), 2802 .hw.init = &(struct clk_init_data){ 2803 .name = "gcc_ufs_card_rx_symbol_1_clk", 2804 .ops = &clk_branch2_ops, 2805 }, 2806 }, 2807 }; 2808 2809 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { 2810 .halt_reg = 0x7501c, 2811 .halt_check = BRANCH_HALT_DELAY, 2812 .clkr = { 2813 .enable_reg = 0x7501c, 2814 .enable_mask = BIT(0), 2815 .hw.init = &(struct clk_init_data){ 2816 .name = "gcc_ufs_card_tx_symbol_0_clk", 2817 .ops = &clk_branch2_ops, 2818 }, 2819 }, 2820 }; 2821 2822 static struct clk_branch gcc_ufs_card_unipro_core_clk = { 2823 .halt_reg = 0x7505c, 2824 .halt_check = BRANCH_HALT, 2825 .hwcg_reg = 0x7505c, 2826 .hwcg_bit = 1, 2827 .clkr = { 2828 .enable_reg = 0x7505c, 2829 .enable_mask = BIT(0), 2830 .hw.init = &(struct clk_init_data){ 2831 .name = "gcc_ufs_card_unipro_core_clk", 2832 .parent_data = &(const struct clk_parent_data){ 2833 .hw = &gcc_ufs_card_unipro_core_clk_src.clkr.hw, 2834 }, 2835 .num_parents = 1, 2836 .flags = CLK_SET_RATE_PARENT, 2837 .ops = &clk_branch2_ops, 2838 }, 2839 }, 2840 }; 2841 2842 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2843 .halt_reg = 0x77018, 2844 .halt_check = BRANCH_HALT_VOTED, 2845 .hwcg_reg = 0x77018, 2846 .hwcg_bit = 1, 2847 .clkr = { 2848 .enable_reg = 0x77018, 2849 .enable_mask = BIT(0), 2850 .hw.init = &(struct clk_init_data){ 2851 .name = "gcc_ufs_phy_ahb_clk", 2852 .ops = &clk_branch2_ops, 2853 }, 2854 }, 2855 }; 2856 2857 static struct clk_branch gcc_ufs_phy_axi_clk = { 2858 .halt_reg = 0x77010, 2859 .halt_check = BRANCH_HALT, 2860 .hwcg_reg = 0x77010, 2861 .hwcg_bit = 1, 2862 .clkr = { 2863 .enable_reg = 0x77010, 2864 .enable_mask = BIT(0), 2865 .hw.init = &(struct clk_init_data){ 2866 .name = "gcc_ufs_phy_axi_clk", 2867 .parent_data = &(const struct clk_parent_data){ 2868 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 2869 }, 2870 .num_parents = 1, 2871 .flags = CLK_SET_RATE_PARENT, 2872 .ops = &clk_branch2_ops, 2873 }, 2874 }, 2875 }; 2876 2877 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2878 .halt_reg = 0x77064, 2879 .halt_check = BRANCH_HALT_VOTED, 2880 .hwcg_reg = 0x77064, 2881 .hwcg_bit = 1, 2882 .clkr = { 2883 .enable_reg = 0x77064, 2884 .enable_mask = BIT(0), 2885 .hw.init = &(struct clk_init_data){ 2886 .name = "gcc_ufs_phy_ice_core_clk", 2887 .parent_data = &(const struct clk_parent_data){ 2888 .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2889 }, 2890 .num_parents = 1, 2891 .flags = CLK_SET_RATE_PARENT, 2892 .ops = &clk_branch2_ops, 2893 }, 2894 }, 2895 }; 2896 2897 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2898 .halt_reg = 0x7709c, 2899 .halt_check = BRANCH_HALT, 2900 .hwcg_reg = 0x7709c, 2901 .hwcg_bit = 1, 2902 .clkr = { 2903 .enable_reg = 0x7709c, 2904 .enable_mask = BIT(0), 2905 .hw.init = &(struct clk_init_data){ 2906 .name = "gcc_ufs_phy_phy_aux_clk", 2907 .parent_data = &(const struct clk_parent_data){ 2908 .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2909 }, 2910 .num_parents = 1, 2911 .flags = CLK_SET_RATE_PARENT, 2912 .ops = &clk_branch2_ops, 2913 }, 2914 }, 2915 }; 2916 2917 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2918 .halt_reg = 0x77020, 2919 .halt_check = BRANCH_HALT_DELAY, 2920 .clkr = { 2921 .enable_reg = 0x77020, 2922 .enable_mask = BIT(0), 2923 .hw.init = &(struct clk_init_data){ 2924 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2925 .ops = &clk_branch2_ops, 2926 }, 2927 }, 2928 }; 2929 2930 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2931 .halt_reg = 0x770b8, 2932 .halt_check = BRANCH_HALT_DELAY, 2933 .clkr = { 2934 .enable_reg = 0x770b8, 2935 .enable_mask = BIT(0), 2936 .hw.init = &(struct clk_init_data){ 2937 .name = "gcc_ufs_phy_rx_symbol_1_clk", 2938 .ops = &clk_branch2_ops, 2939 }, 2940 }, 2941 }; 2942 2943 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2944 .halt_reg = 0x7701c, 2945 .halt_check = BRANCH_HALT_DELAY, 2946 .clkr = { 2947 .enable_reg = 0x7701c, 2948 .enable_mask = BIT(0), 2949 .hw.init = &(struct clk_init_data){ 2950 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2951 .ops = &clk_branch2_ops, 2952 }, 2953 }, 2954 }; 2955 2956 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2957 .halt_reg = 0x7705c, 2958 .halt_check = BRANCH_HALT, 2959 .hwcg_reg = 0x7705c, 2960 .hwcg_bit = 1, 2961 .clkr = { 2962 .enable_reg = 0x7705c, 2963 .enable_mask = BIT(0), 2964 .hw.init = &(struct clk_init_data){ 2965 .name = "gcc_ufs_phy_unipro_core_clk", 2966 .parent_data = &(const struct clk_parent_data){ 2967 .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2968 }, 2969 .num_parents = 1, 2970 .flags = CLK_SET_RATE_PARENT, 2971 .ops = &clk_branch2_ops, 2972 }, 2973 }, 2974 }; 2975 2976 static struct clk_branch gcc_usb30_prim_master_clk = { 2977 .halt_reg = 0xf010, 2978 .halt_check = BRANCH_HALT_VOTED, 2979 .clkr = { 2980 .enable_reg = 0xf010, 2981 .enable_mask = BIT(0), 2982 .hw.init = &(struct clk_init_data){ 2983 .name = "gcc_usb30_prim_master_clk", 2984 .parent_data = &(const struct clk_parent_data){ 2985 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 2986 }, 2987 .num_parents = 1, 2988 .flags = CLK_SET_RATE_PARENT, 2989 .ops = &clk_branch2_ops, 2990 }, 2991 }, 2992 }; 2993 2994 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2995 .halt_reg = 0xf01c, 2996 .halt_check = BRANCH_HALT, 2997 .clkr = { 2998 .enable_reg = 0xf01c, 2999 .enable_mask = BIT(0), 3000 .hw.init = &(struct clk_init_data){ 3001 .name = "gcc_usb30_prim_mock_utmi_clk", 3002 .parent_data = &(const struct clk_parent_data){ 3003 .hw = 3004 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 3005 }, 3006 .num_parents = 1, 3007 .flags = CLK_SET_RATE_PARENT, 3008 .ops = &clk_branch2_ops, 3009 }, 3010 }, 3011 }; 3012 3013 static struct clk_branch gcc_usb30_prim_sleep_clk = { 3014 .halt_reg = 0xf018, 3015 .halt_check = BRANCH_HALT, 3016 .clkr = { 3017 .enable_reg = 0xf018, 3018 .enable_mask = BIT(0), 3019 .hw.init = &(struct clk_init_data){ 3020 .name = "gcc_usb30_prim_sleep_clk", 3021 .ops = &clk_branch2_ops, 3022 }, 3023 }, 3024 }; 3025 3026 static struct clk_branch gcc_usb30_sec_master_clk = { 3027 .halt_reg = 0x10010, 3028 .halt_check = BRANCH_HALT_VOTED, 3029 .clkr = { 3030 .enable_reg = 0x10010, 3031 .enable_mask = BIT(0), 3032 .hw.init = &(struct clk_init_data){ 3033 .name = "gcc_usb30_sec_master_clk", 3034 .parent_data = &(const struct clk_parent_data){ 3035 .hw = &gcc_usb30_sec_master_clk_src.clkr.hw, 3036 }, 3037 .num_parents = 1, 3038 .flags = CLK_SET_RATE_PARENT, 3039 .ops = &clk_branch2_ops, 3040 }, 3041 }, 3042 }; 3043 3044 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { 3045 .halt_reg = 0x1001c, 3046 .halt_check = BRANCH_HALT, 3047 .clkr = { 3048 .enable_reg = 0x1001c, 3049 .enable_mask = BIT(0), 3050 .hw.init = &(struct clk_init_data){ 3051 .name = "gcc_usb30_sec_mock_utmi_clk", 3052 .parent_data = &(const struct clk_parent_data){ 3053 .hw = 3054 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw, 3055 }, 3056 .num_parents = 1, 3057 .flags = CLK_SET_RATE_PARENT, 3058 .ops = &clk_branch2_ops, 3059 }, 3060 }, 3061 }; 3062 3063 static struct clk_branch gcc_usb30_sec_sleep_clk = { 3064 .halt_reg = 0x10018, 3065 .halt_check = BRANCH_HALT, 3066 .clkr = { 3067 .enable_reg = 0x10018, 3068 .enable_mask = BIT(0), 3069 .hw.init = &(struct clk_init_data){ 3070 .name = "gcc_usb30_sec_sleep_clk", 3071 .ops = &clk_branch2_ops, 3072 }, 3073 }, 3074 }; 3075 3076 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 3077 .halt_reg = 0xf054, 3078 .halt_check = BRANCH_HALT, 3079 .clkr = { 3080 .enable_reg = 0xf054, 3081 .enable_mask = BIT(0), 3082 .hw.init = &(struct clk_init_data){ 3083 .name = "gcc_usb3_prim_phy_aux_clk", 3084 .parent_data = &(const struct clk_parent_data){ 3085 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3086 }, 3087 .num_parents = 1, 3088 .flags = CLK_SET_RATE_PARENT, 3089 .ops = &clk_branch2_ops, 3090 }, 3091 }, 3092 }; 3093 3094 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3095 .halt_reg = 0xf058, 3096 .halt_check = BRANCH_HALT, 3097 .clkr = { 3098 .enable_reg = 0xf058, 3099 .enable_mask = BIT(0), 3100 .hw.init = &(struct clk_init_data){ 3101 .name = "gcc_usb3_prim_phy_com_aux_clk", 3102 .parent_data = &(const struct clk_parent_data){ 3103 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3104 }, 3105 .num_parents = 1, 3106 .flags = CLK_SET_RATE_PARENT, 3107 .ops = &clk_branch2_ops, 3108 }, 3109 }, 3110 }; 3111 3112 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3113 .halt_reg = 0xf05c, 3114 .halt_check = BRANCH_HALT_DELAY, 3115 .clkr = { 3116 .enable_reg = 0xf05c, 3117 .enable_mask = BIT(0), 3118 .hw.init = &(struct clk_init_data){ 3119 .name = "gcc_usb3_prim_phy_pipe_clk", 3120 .ops = &clk_branch2_ops, 3121 }, 3122 }, 3123 }; 3124 3125 static struct clk_branch gcc_usb3_sec_clkref_en = { 3126 .halt_reg = 0x8c010, 3127 .halt_check = BRANCH_HALT, 3128 .clkr = { 3129 .enable_reg = 0x8c010, 3130 .enable_mask = BIT(0), 3131 .hw.init = &(struct clk_init_data){ 3132 .name = "gcc_usb3_sec_clkref_en", 3133 .ops = &clk_branch2_ops, 3134 }, 3135 }, 3136 }; 3137 3138 static struct clk_branch gcc_usb3_sec_phy_aux_clk = { 3139 .halt_reg = 0x10054, 3140 .halt_check = BRANCH_HALT, 3141 .clkr = { 3142 .enable_reg = 0x10054, 3143 .enable_mask = BIT(0), 3144 .hw.init = &(struct clk_init_data){ 3145 .name = "gcc_usb3_sec_phy_aux_clk", 3146 .parent_data = &(const struct clk_parent_data){ 3147 .hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 3148 }, 3149 .num_parents = 1, 3150 .flags = CLK_SET_RATE_PARENT, 3151 .ops = &clk_branch2_ops, 3152 }, 3153 }, 3154 }; 3155 3156 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { 3157 .halt_reg = 0x10058, 3158 .halt_check = BRANCH_HALT, 3159 .clkr = { 3160 .enable_reg = 0x10058, 3161 .enable_mask = BIT(0), 3162 .hw.init = &(struct clk_init_data){ 3163 .name = "gcc_usb3_sec_phy_com_aux_clk", 3164 .parent_data = &(const struct clk_parent_data){ 3165 .hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 3166 }, 3167 .num_parents = 1, 3168 .flags = CLK_SET_RATE_PARENT, 3169 .ops = &clk_branch2_ops, 3170 }, 3171 }, 3172 }; 3173 3174 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { 3175 .halt_reg = 0x1005c, 3176 .halt_check = BRANCH_HALT_DELAY, 3177 .clkr = { 3178 .enable_reg = 0x1005c, 3179 .enable_mask = BIT(0), 3180 .hw.init = &(struct clk_init_data){ 3181 .name = "gcc_usb3_sec_phy_pipe_clk", 3182 .ops = &clk_branch2_ops, 3183 }, 3184 }, 3185 }; 3186 3187 static struct clk_branch gcc_video_axi0_clk = { 3188 .halt_reg = 0xb024, 3189 .halt_check = BRANCH_HALT_VOTED, 3190 .clkr = { 3191 .enable_reg = 0xb024, 3192 .enable_mask = BIT(0), 3193 .hw.init = &(struct clk_init_data){ 3194 .name = "gcc_video_axi0_clk", 3195 .ops = &clk_branch2_ops, 3196 }, 3197 }, 3198 }; 3199 3200 static struct clk_branch gcc_video_axi1_clk = { 3201 .halt_reg = 0xb028, 3202 .halt_check = BRANCH_HALT_VOTED, 3203 .clkr = { 3204 .enable_reg = 0xb028, 3205 .enable_mask = BIT(0), 3206 .hw.init = &(struct clk_init_data){ 3207 .name = "gcc_video_axi1_clk", 3208 .ops = &clk_branch2_ops, 3209 }, 3210 }, 3211 }; 3212 3213 static struct clk_branch gcc_video_xo_clk = { 3214 .halt_reg = 0xb03c, 3215 .halt_check = BRANCH_HALT, 3216 .clkr = { 3217 .enable_reg = 0xb03c, 3218 .enable_mask = BIT(0), 3219 .hw.init = &(struct clk_init_data){ 3220 .name = "gcc_video_xo_clk", 3221 .ops = &clk_branch2_ops, 3222 }, 3223 }, 3224 }; 3225 3226 static struct gdsc pcie_0_gdsc = { 3227 .gdscr = 0x6b004, 3228 .pd = { 3229 .name = "pcie_0_gdsc", 3230 }, 3231 .pwrsts = PWRSTS_OFF_ON, 3232 }; 3233 3234 static struct gdsc pcie_1_gdsc = { 3235 .gdscr = 0x8d004, 3236 .pd = { 3237 .name = "pcie_1_gdsc", 3238 }, 3239 .pwrsts = PWRSTS_OFF_ON, 3240 }; 3241 3242 static struct gdsc pcie_2_gdsc = { 3243 .gdscr = 0x6004, 3244 .pd = { 3245 .name = "pcie_2_gdsc", 3246 }, 3247 .pwrsts = PWRSTS_OFF_ON, 3248 }; 3249 3250 static struct gdsc ufs_card_gdsc = { 3251 .gdscr = 0x75004, 3252 .pd = { 3253 .name = "ufs_card_gdsc", 3254 }, 3255 .pwrsts = PWRSTS_OFF_ON, 3256 }; 3257 3258 static struct gdsc ufs_phy_gdsc = { 3259 .gdscr = 0x77004, 3260 .pd = { 3261 .name = "ufs_phy_gdsc", 3262 }, 3263 .pwrsts = PWRSTS_OFF_ON, 3264 }; 3265 3266 static struct gdsc usb30_prim_gdsc = { 3267 .gdscr = 0xf004, 3268 .pd = { 3269 .name = "usb30_prim_gdsc", 3270 }, 3271 .pwrsts = PWRSTS_OFF_ON, 3272 }; 3273 3274 static struct gdsc usb30_sec_gdsc = { 3275 .gdscr = 0x10004, 3276 .pd = { 3277 .name = "usb30_sec_gdsc", 3278 }, 3279 .pwrsts = PWRSTS_OFF_ON, 3280 }; 3281 3282 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { 3283 .gdscr = 0x7d050, 3284 .pd = { 3285 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", 3286 }, 3287 .pwrsts = PWRSTS_OFF_ON, 3288 .flags = VOTABLE, 3289 }; 3290 3291 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = { 3292 .gdscr = 0x7d058, 3293 .pd = { 3294 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", 3295 }, 3296 .pwrsts = PWRSTS_OFF_ON, 3297 .flags = VOTABLE, 3298 }; 3299 3300 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = { 3301 .gdscr = 0x7d054, 3302 .pd = { 3303 .name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc", 3304 }, 3305 .pwrsts = PWRSTS_OFF_ON, 3306 .flags = VOTABLE, 3307 }; 3308 3309 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = { 3310 .gdscr = 0x7d06c, 3311 .pd = { 3312 .name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc", 3313 }, 3314 .pwrsts = PWRSTS_OFF_ON, 3315 .flags = VOTABLE, 3316 }; 3317 3318 static struct clk_regmap *gcc_sm8250_clocks[] = { 3319 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, 3320 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, 3321 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 3322 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 3323 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, 3324 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3325 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 3326 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 3327 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 3328 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3329 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, 3330 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, 3331 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, 3332 [GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr, 3333 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, 3334 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 3335 [GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr, 3336 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3337 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, 3338 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 3339 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3340 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3341 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3342 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3343 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3344 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3345 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3346 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3347 [GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr, 3348 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3349 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3350 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, 3351 [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr, 3352 [GCC_NPU_BWMON_CFG_AHB_CLK] = &gcc_npu_bwmon_cfg_ahb_clk.clkr, 3353 [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr, 3354 [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr, 3355 [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr, 3356 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr, 3357 [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr, 3358 [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr, 3359 [GCC_PCIE2_PHY_REFGEN_CLK] = &gcc_pcie2_phy_refgen_clk.clkr, 3360 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3361 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 3362 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3363 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3364 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3365 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3366 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 3367 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 3368 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 3369 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 3370 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 3371 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 3372 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 3373 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 3374 [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr, 3375 [GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr, 3376 [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr, 3377 [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr, 3378 [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr, 3379 [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr, 3380 [GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr, 3381 [GCC_PCIE_MDM_CLKREF_EN] = &gcc_pcie_mdm_clkref_en.clkr, 3382 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, 3383 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, 3384 [GCC_PCIE_WIFI_CLKREF_EN] = &gcc_pcie_wifi_clkref_en.clkr, 3385 [GCC_PCIE_WIGIG_CLKREF_EN] = &gcc_pcie_wigig_clkref_en.clkr, 3386 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3387 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3388 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3389 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3390 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3391 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3392 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3393 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3394 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 3395 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3396 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 3397 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 3398 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3399 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3400 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3401 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3402 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3403 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3404 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3405 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3406 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3407 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3408 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3409 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3410 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 3411 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 3412 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 3413 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 3414 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3415 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3416 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3417 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3418 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3419 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3420 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3421 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3422 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3423 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3424 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3425 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3426 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3427 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3428 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 3429 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 3430 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 3431 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 3432 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 3433 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 3434 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 3435 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 3436 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 3437 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 3438 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 3439 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 3440 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 3441 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 3442 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3443 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3444 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3445 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3446 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 3447 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 3448 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3449 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3450 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3451 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3452 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3453 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 3454 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 3455 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, 3456 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 3457 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, 3458 [GCC_UFS_1X_CLKREF_EN] = &gcc_ufs_1x_clkref_en.clkr, 3459 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, 3460 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, 3461 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, 3462 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, 3463 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, 3464 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, 3465 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, 3466 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, 3467 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, 3468 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, 3469 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, 3470 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = 3471 &gcc_ufs_card_unipro_core_clk_src.clkr, 3472 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3473 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3474 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3475 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3476 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3477 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3478 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3479 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3480 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3481 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3482 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3483 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 3484 &gcc_ufs_phy_unipro_core_clk_src.clkr, 3485 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3486 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3487 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3488 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 3489 &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3490 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = 3491 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3492 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3493 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, 3494 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, 3495 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, 3496 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = 3497 &gcc_usb30_sec_mock_utmi_clk_src.clkr, 3498 [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = 3499 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr, 3500 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, 3501 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3502 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3503 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3504 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3505 [GCC_USB3_SEC_CLKREF_EN] = &gcc_usb3_sec_clkref_en.clkr, 3506 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, 3507 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, 3508 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, 3509 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, 3510 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3511 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 3512 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 3513 [GPLL0] = &gpll0.clkr, 3514 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 3515 [GPLL4] = &gpll4.clkr, 3516 [GPLL9] = &gpll9.clkr, 3517 }; 3518 3519 static struct gdsc *gcc_sm8250_gdscs[] = { 3520 [PCIE_0_GDSC] = &pcie_0_gdsc, 3521 [PCIE_1_GDSC] = &pcie_1_gdsc, 3522 [PCIE_2_GDSC] = &pcie_2_gdsc, 3523 [UFS_CARD_GDSC] = &ufs_card_gdsc, 3524 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3525 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3526 [USB30_SEC_GDSC] = &usb30_sec_gdsc, 3527 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = 3528 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, 3529 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = 3530 &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, 3531 [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = 3532 &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc, 3533 [HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC] = 3534 &hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc, 3535 }; 3536 3537 static const struct qcom_reset_map gcc_sm8250_resets[] = { 3538 [GCC_GPU_BCR] = { 0x71000 }, 3539 [GCC_MMSS_BCR] = { 0xb000 }, 3540 [GCC_NPU_BWMON_BCR] = { 0x73000 }, 3541 [GCC_NPU_BCR] = { 0x4d000 }, 3542 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3543 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 3544 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 3545 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3546 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, 3547 [GCC_PCIE_1_BCR] = { 0x8d000 }, 3548 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, 3549 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, 3550 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 3551 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 }, 3552 [GCC_PCIE_2_BCR] = { 0x6000 }, 3553 [GCC_PCIE_2_LINK_DOWN_BCR] = { 0x1f014 }, 3554 [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x1f020 }, 3555 [GCC_PCIE_2_PHY_BCR] = { 0x1f01c }, 3556 [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0x1f028 }, 3557 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 3558 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, 3559 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, 3560 [GCC_PDM_BCR] = { 0x33000 }, 3561 [GCC_PRNG_BCR] = { 0x34000 }, 3562 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, 3563 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 3564 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, 3565 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3566 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3567 [GCC_SDCC2_BCR] = { 0x14000 }, 3568 [GCC_SDCC4_BCR] = { 0x16000 }, 3569 [GCC_TSIF_BCR] = { 0x36000 }, 3570 [GCC_UFS_CARD_BCR] = { 0x75000 }, 3571 [GCC_UFS_PHY_BCR] = { 0x77000 }, 3572 [GCC_USB30_PRIM_BCR] = { 0xf000 }, 3573 [GCC_USB30_SEC_BCR] = { 0x10000 }, 3574 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 3575 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 3576 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 3577 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 3578 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3579 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3580 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 3581 [GCC_VIDEO_AXI0_CLK_ARES] = { 0xb024, 2 }, 3582 [GCC_VIDEO_AXI1_CLK_ARES] = { 0xb028, 2 }, 3583 }; 3584 3585 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3586 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3587 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3588 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3589 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3590 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3591 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3592 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 3593 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 3594 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3595 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3596 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 3597 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3598 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3599 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3600 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 3601 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 3602 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 3603 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 3604 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 3605 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 3606 }; 3607 3608 static const struct regmap_config gcc_sm8250_regmap_config = { 3609 .reg_bits = 32, 3610 .reg_stride = 4, 3611 .val_bits = 32, 3612 .max_register = 0x9c100, 3613 .fast_io = true, 3614 }; 3615 3616 static const struct qcom_cc_desc gcc_sm8250_desc = { 3617 .config = &gcc_sm8250_regmap_config, 3618 .clks = gcc_sm8250_clocks, 3619 .num_clks = ARRAY_SIZE(gcc_sm8250_clocks), 3620 .resets = gcc_sm8250_resets, 3621 .num_resets = ARRAY_SIZE(gcc_sm8250_resets), 3622 .gdscs = gcc_sm8250_gdscs, 3623 .num_gdscs = ARRAY_SIZE(gcc_sm8250_gdscs), 3624 }; 3625 3626 static const struct of_device_id gcc_sm8250_match_table[] = { 3627 { .compatible = "qcom,gcc-sm8250" }, 3628 { } 3629 }; 3630 MODULE_DEVICE_TABLE(of, gcc_sm8250_match_table); 3631 3632 static int gcc_sm8250_probe(struct platform_device *pdev) 3633 { 3634 struct regmap *regmap; 3635 int ret; 3636 3637 regmap = qcom_cc_map(pdev, &gcc_sm8250_desc); 3638 if (IS_ERR(regmap)) 3639 return PTR_ERR(regmap); 3640 3641 /* 3642 * Disable the GPLL0 active input to NPU and GPU 3643 * via MISC registers. 3644 */ 3645 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); 3646 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 3647 3648 /* 3649 * Keep the clocks always-ON 3650 * GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK, 3651 * GCC_CPUSS_DVM_BUS_CLK, GCC_GPU_CFG_AHB_CLK, 3652 * GCC_SYS_NOC_CPUSS_AHB_CLK 3653 */ 3654 regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); 3655 regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); 3656 regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); 3657 regmap_update_bits(regmap, 0x4818c, BIT(0), BIT(0)); 3658 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 3659 regmap_update_bits(regmap, 0x52000, BIT(0), BIT(0)); 3660 3661 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3662 ARRAY_SIZE(gcc_dfs_clocks)); 3663 if (ret) 3664 return ret; 3665 3666 return qcom_cc_really_probe(pdev, &gcc_sm8250_desc, regmap); 3667 } 3668 3669 static struct platform_driver gcc_sm8250_driver = { 3670 .probe = gcc_sm8250_probe, 3671 .driver = { 3672 .name = "gcc-sm8250", 3673 .of_match_table = gcc_sm8250_match_table, 3674 }, 3675 }; 3676 3677 static int __init gcc_sm8250_init(void) 3678 { 3679 return platform_driver_register(&gcc_sm8250_driver); 3680 } 3681 subsys_initcall(gcc_sm8250_init); 3682 3683 static void __exit gcc_sm8250_exit(void) 3684 { 3685 platform_driver_unregister(&gcc_sm8250_driver); 3686 } 3687 module_exit(gcc_sm8250_exit); 3688 3689 MODULE_DESCRIPTION("QTI GCC SM8250 Driver"); 3690 MODULE_LICENSE("GPL v2"); 3691