1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 3 4 #include <linux/kernel.h> 5 #include <linux/bitops.h> 6 #include <linux/err.h> 7 #include <linux/platform_device.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/of_device.h> 11 #include <linux/clk-provider.h> 12 #include <linux/regmap.h> 13 #include <linux/reset-controller.h> 14 15 #include <dt-bindings/clock/qcom,gcc-sm8150.h> 16 17 #include "common.h" 18 #include "clk-alpha-pll.h" 19 #include "clk-branch.h" 20 #include "clk-pll.h" 21 #include "clk-rcg.h" 22 #include "clk-regmap.h" 23 #include "reset.h" 24 #include "gdsc.h" 25 26 enum { 27 P_BI_TCXO, 28 P_AUD_REF_CLK, 29 P_GPLL0_OUT_EVEN, 30 P_GPLL0_OUT_MAIN, 31 P_GPLL7_OUT_MAIN, 32 P_GPLL9_OUT_MAIN, 33 P_SLEEP_CLK, 34 }; 35 36 static struct clk_alpha_pll gpll0 = { 37 .offset = 0x0, 38 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 39 .clkr = { 40 .enable_reg = 0x52000, 41 .enable_mask = BIT(0), 42 .hw.init = &(struct clk_init_data){ 43 .name = "gpll0", 44 .parent_data = &(const struct clk_parent_data){ 45 .fw_name = "bi_tcxo", 46 .name = "bi_tcxo", 47 }, 48 .num_parents = 1, 49 .ops = &clk_alpha_pll_fixed_trion_ops, 50 }, 51 }, 52 }; 53 54 static const struct clk_div_table post_div_table_trion_even[] = { 55 { 0x0, 1 }, 56 { 0x1, 2 }, 57 { 0x3, 4 }, 58 { 0x7, 8 }, 59 { } 60 }; 61 62 static struct clk_alpha_pll_postdiv gpll0_out_even = { 63 .offset = 0x0, 64 .post_div_shift = 8, 65 .post_div_table = post_div_table_trion_even, 66 .num_post_div = ARRAY_SIZE(post_div_table_trion_even), 67 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 68 .width = 4, 69 .clkr.hw.init = &(struct clk_init_data){ 70 .name = "gpll0_out_even", 71 .parent_hws = (const struct clk_hw*[]){ 72 &gpll0.clkr.hw, 73 }, 74 .num_parents = 1, 75 .ops = &clk_alpha_pll_postdiv_trion_ops, 76 }, 77 }; 78 79 static struct clk_alpha_pll gpll7 = { 80 .offset = 0x1a000, 81 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 82 .clkr = { 83 .enable_reg = 0x52000, 84 .enable_mask = BIT(7), 85 .hw.init = &(struct clk_init_data){ 86 .name = "gpll7", 87 .parent_data = &(const struct clk_parent_data){ 88 .fw_name = "bi_tcxo", 89 .name = "bi_tcxo", 90 }, 91 .num_parents = 1, 92 .ops = &clk_alpha_pll_fixed_trion_ops, 93 }, 94 }, 95 }; 96 97 static struct clk_alpha_pll gpll9 = { 98 .offset = 0x1c000, 99 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 100 .clkr = { 101 .enable_reg = 0x52000, 102 .enable_mask = BIT(9), 103 .hw.init = &(struct clk_init_data){ 104 .name = "gpll9", 105 .parent_data = &(const struct clk_parent_data){ 106 .fw_name = "bi_tcxo", 107 .name = "bi_tcxo", 108 }, 109 .num_parents = 1, 110 .ops = &clk_alpha_pll_fixed_trion_ops, 111 }, 112 }, 113 }; 114 115 static const struct parent_map gcc_parent_map_0[] = { 116 { P_BI_TCXO, 0 }, 117 { P_GPLL0_OUT_MAIN, 1 }, 118 { P_GPLL0_OUT_EVEN, 6 }, 119 }; 120 121 static const struct clk_parent_data gcc_parents_0[] = { 122 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 123 { .hw = &gpll0.clkr.hw }, 124 { .hw = &gpll0_out_even.clkr.hw }, 125 }; 126 127 static const struct parent_map gcc_parent_map_1[] = { 128 { P_BI_TCXO, 0 }, 129 { P_GPLL0_OUT_MAIN, 1 }, 130 { P_SLEEP_CLK, 5 }, 131 { P_GPLL0_OUT_EVEN, 6 }, 132 }; 133 134 static const struct clk_parent_data gcc_parents_1[] = { 135 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 136 { .hw = &gpll0.clkr.hw }, 137 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 138 { .hw = &gpll0_out_even.clkr.hw }, 139 }; 140 141 static const struct parent_map gcc_parent_map_2[] = { 142 { P_BI_TCXO, 0 }, 143 { P_SLEEP_CLK, 5 }, 144 }; 145 146 static const struct clk_parent_data gcc_parents_2[] = { 147 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 148 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 149 }; 150 151 static const struct parent_map gcc_parent_map_3[] = { 152 { P_BI_TCXO, 0 }, 153 { P_GPLL0_OUT_MAIN, 1 }, 154 }; 155 156 static const struct clk_parent_data gcc_parents_3[] = { 157 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 158 { .hw = &gpll0.clkr.hw }, 159 }; 160 161 static const struct parent_map gcc_parent_map_4[] = { 162 { P_BI_TCXO, 0 }, 163 }; 164 165 static const struct clk_parent_data gcc_parents_4[] = { 166 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 167 }; 168 169 static const struct parent_map gcc_parent_map_5[] = { 170 { P_BI_TCXO, 0 }, 171 { P_GPLL0_OUT_MAIN, 1 }, 172 { P_GPLL7_OUT_MAIN, 3 }, 173 { P_GPLL0_OUT_EVEN, 6 }, 174 }; 175 176 static const struct clk_parent_data gcc_parents_5[] = { 177 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 178 { .hw = &gpll0.clkr.hw }, 179 { .hw = &gpll7.clkr.hw }, 180 { .hw = &gpll0_out_even.clkr.hw }, 181 }; 182 183 static const struct parent_map gcc_parent_map_6[] = { 184 { P_BI_TCXO, 0 }, 185 { P_GPLL0_OUT_MAIN, 1 }, 186 { P_GPLL9_OUT_MAIN, 2 }, 187 { P_GPLL0_OUT_EVEN, 6 }, 188 }; 189 190 static const struct clk_parent_data gcc_parents_6[] = { 191 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 192 { .hw = &gpll0.clkr.hw }, 193 { .hw = &gpll9.clkr.hw }, 194 { .hw = &gpll0_out_even.clkr.hw }, 195 }; 196 197 static const struct parent_map gcc_parent_map_7[] = { 198 { P_BI_TCXO, 0 }, 199 { P_GPLL0_OUT_MAIN, 1 }, 200 { P_AUD_REF_CLK, 2 }, 201 { P_GPLL0_OUT_EVEN, 6 }, 202 }; 203 204 static const struct clk_parent_data gcc_parents_7[] = { 205 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 206 { .hw = &gpll0.clkr.hw }, 207 { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }, 208 { .hw = &gpll0_out_even.clkr.hw }, 209 }; 210 211 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { 212 F(19200000, P_BI_TCXO, 1, 0, 0), 213 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 214 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 215 { } 216 }; 217 218 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 219 .cmd_rcgr = 0x48014, 220 .mnd_width = 0, 221 .hid_width = 5, 222 .parent_map = gcc_parent_map_0, 223 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, 224 .clkr.hw.init = &(struct clk_init_data){ 225 .name = "gcc_cpuss_ahb_clk_src", 226 .parent_data = gcc_parents_0, 227 .num_parents = ARRAY_SIZE(gcc_parents_0), 228 .flags = CLK_SET_RATE_PARENT, 229 .ops = &clk_rcg2_ops, 230 }, 231 }; 232 233 static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = { 234 F(19200000, P_BI_TCXO, 1, 0, 0), 235 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 236 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), 237 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), 238 { } 239 }; 240 241 static struct clk_rcg2 gcc_emac_ptp_clk_src = { 242 .cmd_rcgr = 0x6038, 243 .mnd_width = 0, 244 .hid_width = 5, 245 .parent_map = gcc_parent_map_5, 246 .freq_tbl = ftbl_gcc_emac_ptp_clk_src, 247 .clkr.hw.init = &(struct clk_init_data){ 248 .name = "gcc_emac_ptp_clk_src", 249 .parent_data = gcc_parents_5, 250 .num_parents = ARRAY_SIZE(gcc_parents_5), 251 .flags = CLK_SET_RATE_PARENT, 252 .ops = &clk_rcg2_ops, 253 }, 254 }; 255 256 static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = { 257 F(2500000, P_BI_TCXO, 1, 25, 192), 258 F(5000000, P_BI_TCXO, 1, 25, 96), 259 F(19200000, P_BI_TCXO, 1, 0, 0), 260 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 261 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 262 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), 263 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), 264 { } 265 }; 266 267 static struct clk_rcg2 gcc_emac_rgmii_clk_src = { 268 .cmd_rcgr = 0x601c, 269 .mnd_width = 8, 270 .hid_width = 5, 271 .parent_map = gcc_parent_map_5, 272 .freq_tbl = ftbl_gcc_emac_rgmii_clk_src, 273 .clkr.hw.init = &(struct clk_init_data){ 274 .name = "gcc_emac_rgmii_clk_src", 275 .parent_data = gcc_parents_5, 276 .num_parents = ARRAY_SIZE(gcc_parents_5), 277 .flags = CLK_SET_RATE_PARENT, 278 .ops = &clk_rcg2_ops, 279 }, 280 }; 281 282 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 283 F(19200000, P_BI_TCXO, 1, 0, 0), 284 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 285 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 286 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 287 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 288 { } 289 }; 290 291 static struct clk_rcg2 gcc_gp1_clk_src = { 292 .cmd_rcgr = 0x64004, 293 .mnd_width = 8, 294 .hid_width = 5, 295 .parent_map = gcc_parent_map_1, 296 .freq_tbl = ftbl_gcc_gp1_clk_src, 297 .clkr.hw.init = &(struct clk_init_data){ 298 .name = "gcc_gp1_clk_src", 299 .parent_data = gcc_parents_1, 300 .num_parents = ARRAY_SIZE(gcc_parents_1), 301 .flags = CLK_SET_RATE_PARENT, 302 .ops = &clk_rcg2_ops, 303 }, 304 }; 305 306 static struct clk_rcg2 gcc_gp2_clk_src = { 307 .cmd_rcgr = 0x65004, 308 .mnd_width = 8, 309 .hid_width = 5, 310 .parent_map = gcc_parent_map_1, 311 .freq_tbl = ftbl_gcc_gp1_clk_src, 312 .clkr.hw.init = &(struct clk_init_data){ 313 .name = "gcc_gp2_clk_src", 314 .parent_data = gcc_parents_1, 315 .num_parents = ARRAY_SIZE(gcc_parents_1), 316 .flags = CLK_SET_RATE_PARENT, 317 .ops = &clk_rcg2_ops, 318 }, 319 }; 320 321 static struct clk_rcg2 gcc_gp3_clk_src = { 322 .cmd_rcgr = 0x66004, 323 .mnd_width = 8, 324 .hid_width = 5, 325 .parent_map = gcc_parent_map_1, 326 .freq_tbl = ftbl_gcc_gp1_clk_src, 327 .clkr.hw.init = &(struct clk_init_data){ 328 .name = "gcc_gp3_clk_src", 329 .parent_data = gcc_parents_1, 330 .num_parents = ARRAY_SIZE(gcc_parents_1), 331 .flags = CLK_SET_RATE_PARENT, 332 .ops = &clk_rcg2_ops, 333 }, 334 }; 335 336 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 337 F(9600000, P_BI_TCXO, 2, 0, 0), 338 F(19200000, P_BI_TCXO, 1, 0, 0), 339 { } 340 }; 341 342 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 343 .cmd_rcgr = 0x6b02c, 344 .mnd_width = 16, 345 .hid_width = 5, 346 .parent_map = gcc_parent_map_2, 347 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 348 .clkr.hw.init = &(struct clk_init_data){ 349 .name = "gcc_pcie_0_aux_clk_src", 350 .parent_data = gcc_parents_2, 351 .num_parents = ARRAY_SIZE(gcc_parents_2), 352 .flags = CLK_SET_RATE_PARENT, 353 .ops = &clk_rcg2_ops, 354 }, 355 }; 356 357 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 358 .cmd_rcgr = 0x8d02c, 359 .mnd_width = 16, 360 .hid_width = 5, 361 .parent_map = gcc_parent_map_2, 362 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 363 .clkr.hw.init = &(struct clk_init_data){ 364 .name = "gcc_pcie_1_aux_clk_src", 365 .parent_data = gcc_parents_2, 366 .num_parents = ARRAY_SIZE(gcc_parents_2), 367 .flags = CLK_SET_RATE_PARENT, 368 .ops = &clk_rcg2_ops, 369 }, 370 }; 371 372 static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { 373 F(19200000, P_BI_TCXO, 1, 0, 0), 374 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 375 { } 376 }; 377 378 static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { 379 .cmd_rcgr = 0x6f014, 380 .mnd_width = 0, 381 .hid_width = 5, 382 .parent_map = gcc_parent_map_0, 383 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, 384 .clkr.hw.init = &(struct clk_init_data){ 385 .name = "gcc_pcie_phy_refgen_clk_src", 386 .parent_data = gcc_parents_0, 387 .num_parents = ARRAY_SIZE(gcc_parents_0), 388 .flags = CLK_SET_RATE_PARENT, 389 .ops = &clk_rcg2_ops, 390 }, 391 }; 392 393 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 394 F(9600000, P_BI_TCXO, 2, 0, 0), 395 F(19200000, P_BI_TCXO, 1, 0, 0), 396 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 397 { } 398 }; 399 400 static struct clk_rcg2 gcc_pdm2_clk_src = { 401 .cmd_rcgr = 0x33010, 402 .mnd_width = 0, 403 .hid_width = 5, 404 .parent_map = gcc_parent_map_0, 405 .freq_tbl = ftbl_gcc_pdm2_clk_src, 406 .clkr.hw.init = &(struct clk_init_data){ 407 .name = "gcc_pdm2_clk_src", 408 .parent_data = gcc_parents_0, 409 .num_parents = ARRAY_SIZE(gcc_parents_0), 410 .flags = CLK_SET_RATE_PARENT, 411 .ops = &clk_rcg2_ops, 412 }, 413 }; 414 415 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { 416 F(19200000, P_BI_TCXO, 1, 0, 0), 417 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 418 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 419 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 420 { } 421 }; 422 423 static struct clk_rcg2 gcc_qspi_core_clk_src = { 424 .cmd_rcgr = 0x4b008, 425 .mnd_width = 0, 426 .hid_width = 5, 427 .parent_map = gcc_parent_map_0, 428 .freq_tbl = ftbl_gcc_qspi_core_clk_src, 429 .clkr.hw.init = &(struct clk_init_data){ 430 .name = "gcc_qspi_core_clk_src", 431 .parent_data = gcc_parents_0, 432 .num_parents = ARRAY_SIZE(gcc_parents_0), 433 .flags = CLK_SET_RATE_PARENT, 434 .ops = &clk_rcg2_ops, 435 }, 436 }; 437 438 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 439 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 440 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 441 F(19200000, P_BI_TCXO, 1, 0, 0), 442 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 443 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 444 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 445 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 446 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 447 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 448 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 449 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), 450 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), 451 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), 452 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), 453 F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75), 454 { } 455 }; 456 457 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 458 .cmd_rcgr = 0x17148, 459 .mnd_width = 16, 460 .hid_width = 5, 461 .parent_map = gcc_parent_map_0, 462 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 463 .clkr.hw.init = &(struct clk_init_data){ 464 .name = "gcc_qupv3_wrap0_s0_clk_src", 465 .parent_data = gcc_parents_0, 466 .num_parents = ARRAY_SIZE(gcc_parents_0), 467 .flags = CLK_SET_RATE_PARENT, 468 .ops = &clk_rcg2_ops, 469 }, 470 }; 471 472 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 473 .cmd_rcgr = 0x17278, 474 .mnd_width = 16, 475 .hid_width = 5, 476 .parent_map = gcc_parent_map_0, 477 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 478 .clkr.hw.init = &(struct clk_init_data){ 479 .name = "gcc_qupv3_wrap0_s1_clk_src", 480 .parent_data = gcc_parents_0, 481 .num_parents = ARRAY_SIZE(gcc_parents_0), 482 .flags = CLK_SET_RATE_PARENT, 483 .ops = &clk_rcg2_ops, 484 }, 485 }; 486 487 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 488 .cmd_rcgr = 0x173a8, 489 .mnd_width = 16, 490 .hid_width = 5, 491 .parent_map = gcc_parent_map_0, 492 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 493 .clkr.hw.init = &(struct clk_init_data){ 494 .name = "gcc_qupv3_wrap0_s2_clk_src", 495 .parent_data = gcc_parents_0, 496 .num_parents = ARRAY_SIZE(gcc_parents_0), 497 .flags = CLK_SET_RATE_PARENT, 498 .ops = &clk_rcg2_ops, 499 }, 500 }; 501 502 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 503 .cmd_rcgr = 0x174d8, 504 .mnd_width = 16, 505 .hid_width = 5, 506 .parent_map = gcc_parent_map_0, 507 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 508 .clkr.hw.init = &(struct clk_init_data){ 509 .name = "gcc_qupv3_wrap0_s3_clk_src", 510 .parent_data = gcc_parents_0, 511 .num_parents = ARRAY_SIZE(gcc_parents_0), 512 .flags = CLK_SET_RATE_PARENT, 513 .ops = &clk_rcg2_ops, 514 }, 515 }; 516 517 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 518 .cmd_rcgr = 0x17608, 519 .mnd_width = 16, 520 .hid_width = 5, 521 .parent_map = gcc_parent_map_0, 522 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 523 .clkr.hw.init = &(struct clk_init_data){ 524 .name = "gcc_qupv3_wrap0_s4_clk_src", 525 .parent_data = gcc_parents_0, 526 .num_parents = ARRAY_SIZE(gcc_parents_0), 527 .flags = CLK_SET_RATE_PARENT, 528 .ops = &clk_rcg2_ops, 529 }, 530 }; 531 532 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 533 .cmd_rcgr = 0x17738, 534 .mnd_width = 16, 535 .hid_width = 5, 536 .parent_map = gcc_parent_map_0, 537 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 538 .clkr.hw.init = &(struct clk_init_data){ 539 .name = "gcc_qupv3_wrap0_s5_clk_src", 540 .parent_data = gcc_parents_0, 541 .num_parents = ARRAY_SIZE(gcc_parents_0), 542 .flags = CLK_SET_RATE_PARENT, 543 .ops = &clk_rcg2_ops, 544 }, 545 }; 546 547 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 548 .cmd_rcgr = 0x17868, 549 .mnd_width = 16, 550 .hid_width = 5, 551 .parent_map = gcc_parent_map_0, 552 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 553 .clkr.hw.init = &(struct clk_init_data){ 554 .name = "gcc_qupv3_wrap0_s6_clk_src", 555 .parent_data = gcc_parents_0, 556 .num_parents = ARRAY_SIZE(gcc_parents_0), 557 .flags = CLK_SET_RATE_PARENT, 558 .ops = &clk_rcg2_ops, 559 }, 560 }; 561 562 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 563 .cmd_rcgr = 0x17998, 564 .mnd_width = 16, 565 .hid_width = 5, 566 .parent_map = gcc_parent_map_0, 567 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 568 .clkr.hw.init = &(struct clk_init_data){ 569 .name = "gcc_qupv3_wrap0_s7_clk_src", 570 .parent_data = gcc_parents_0, 571 .num_parents = ARRAY_SIZE(gcc_parents_0), 572 .flags = CLK_SET_RATE_PARENT, 573 .ops = &clk_rcg2_ops, 574 }, 575 }; 576 577 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 578 .cmd_rcgr = 0x18148, 579 .mnd_width = 16, 580 .hid_width = 5, 581 .parent_map = gcc_parent_map_0, 582 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 583 .clkr.hw.init = &(struct clk_init_data){ 584 .name = "gcc_qupv3_wrap1_s0_clk_src", 585 .parent_data = gcc_parents_0, 586 .num_parents = ARRAY_SIZE(gcc_parents_0), 587 .flags = CLK_SET_RATE_PARENT, 588 .ops = &clk_rcg2_ops, 589 }, 590 }; 591 592 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 593 .cmd_rcgr = 0x18278, 594 .mnd_width = 16, 595 .hid_width = 5, 596 .parent_map = gcc_parent_map_0, 597 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 598 .clkr.hw.init = &(struct clk_init_data){ 599 .name = "gcc_qupv3_wrap1_s1_clk_src", 600 .parent_data = gcc_parents_0, 601 .num_parents = ARRAY_SIZE(gcc_parents_0), 602 .flags = CLK_SET_RATE_PARENT, 603 .ops = &clk_rcg2_ops, 604 }, 605 }; 606 607 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 608 .cmd_rcgr = 0x183a8, 609 .mnd_width = 16, 610 .hid_width = 5, 611 .parent_map = gcc_parent_map_0, 612 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 613 .clkr.hw.init = &(struct clk_init_data){ 614 .name = "gcc_qupv3_wrap1_s2_clk_src", 615 .parent_data = gcc_parents_0, 616 .num_parents = ARRAY_SIZE(gcc_parents_0), 617 .flags = CLK_SET_RATE_PARENT, 618 .ops = &clk_rcg2_ops, 619 }, 620 }; 621 622 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 623 .cmd_rcgr = 0x184d8, 624 .mnd_width = 16, 625 .hid_width = 5, 626 .parent_map = gcc_parent_map_0, 627 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 628 .clkr.hw.init = &(struct clk_init_data){ 629 .name = "gcc_qupv3_wrap1_s3_clk_src", 630 .parent_data = gcc_parents_0, 631 .num_parents = ARRAY_SIZE(gcc_parents_0), 632 .flags = CLK_SET_RATE_PARENT, 633 .ops = &clk_rcg2_ops, 634 }, 635 }; 636 637 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 638 .cmd_rcgr = 0x18608, 639 .mnd_width = 16, 640 .hid_width = 5, 641 .parent_map = gcc_parent_map_0, 642 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 643 .clkr.hw.init = &(struct clk_init_data){ 644 .name = "gcc_qupv3_wrap1_s4_clk_src", 645 .parent_data = gcc_parents_0, 646 .num_parents = ARRAY_SIZE(gcc_parents_0), 647 .flags = CLK_SET_RATE_PARENT, 648 .ops = &clk_rcg2_ops, 649 }, 650 }; 651 652 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 653 .cmd_rcgr = 0x18738, 654 .mnd_width = 16, 655 .hid_width = 5, 656 .parent_map = gcc_parent_map_0, 657 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 658 .clkr.hw.init = &(struct clk_init_data){ 659 .name = "gcc_qupv3_wrap1_s5_clk_src", 660 .parent_data = gcc_parents_0, 661 .num_parents = ARRAY_SIZE(gcc_parents_0), 662 .flags = CLK_SET_RATE_PARENT, 663 .ops = &clk_rcg2_ops, 664 }, 665 }; 666 667 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 668 .cmd_rcgr = 0x1e148, 669 .mnd_width = 16, 670 .hid_width = 5, 671 .parent_map = gcc_parent_map_0, 672 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 673 .clkr.hw.init = &(struct clk_init_data){ 674 .name = "gcc_qupv3_wrap2_s0_clk_src", 675 .parent_data = gcc_parents_0, 676 .num_parents = ARRAY_SIZE(gcc_parents_0), 677 .flags = CLK_SET_RATE_PARENT, 678 .ops = &clk_rcg2_ops, 679 }, 680 }; 681 682 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 683 .cmd_rcgr = 0x1e278, 684 .mnd_width = 16, 685 .hid_width = 5, 686 .parent_map = gcc_parent_map_0, 687 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 688 .clkr.hw.init = &(struct clk_init_data){ 689 .name = "gcc_qupv3_wrap2_s1_clk_src", 690 .parent_data = gcc_parents_0, 691 .num_parents = ARRAY_SIZE(gcc_parents_0), 692 .flags = CLK_SET_RATE_PARENT, 693 .ops = &clk_rcg2_ops, 694 }, 695 }; 696 697 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 698 .cmd_rcgr = 0x1e3a8, 699 .mnd_width = 16, 700 .hid_width = 5, 701 .parent_map = gcc_parent_map_0, 702 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 703 .clkr.hw.init = &(struct clk_init_data){ 704 .name = "gcc_qupv3_wrap2_s2_clk_src", 705 .parent_data = gcc_parents_0, 706 .num_parents = ARRAY_SIZE(gcc_parents_0), 707 .flags = CLK_SET_RATE_PARENT, 708 .ops = &clk_rcg2_ops, 709 }, 710 }; 711 712 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 713 .cmd_rcgr = 0x1e4d8, 714 .mnd_width = 16, 715 .hid_width = 5, 716 .parent_map = gcc_parent_map_0, 717 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 718 .clkr.hw.init = &(struct clk_init_data){ 719 .name = "gcc_qupv3_wrap2_s3_clk_src", 720 .parent_data = gcc_parents_0, 721 .num_parents = ARRAY_SIZE(gcc_parents_0), 722 .flags = CLK_SET_RATE_PARENT, 723 .ops = &clk_rcg2_ops, 724 }, 725 }; 726 727 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 728 .cmd_rcgr = 0x1e608, 729 .mnd_width = 16, 730 .hid_width = 5, 731 .parent_map = gcc_parent_map_0, 732 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 733 .clkr.hw.init = &(struct clk_init_data){ 734 .name = "gcc_qupv3_wrap2_s4_clk_src", 735 .parent_data = gcc_parents_0, 736 .num_parents = ARRAY_SIZE(gcc_parents_0), 737 .flags = CLK_SET_RATE_PARENT, 738 .ops = &clk_rcg2_ops, 739 }, 740 }; 741 742 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 743 .cmd_rcgr = 0x1e738, 744 .mnd_width = 16, 745 .hid_width = 5, 746 .parent_map = gcc_parent_map_0, 747 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 748 .clkr.hw.init = &(struct clk_init_data){ 749 .name = "gcc_qupv3_wrap2_s5_clk_src", 750 .parent_data = gcc_parents_0, 751 .num_parents = ARRAY_SIZE(gcc_parents_0), 752 .flags = CLK_SET_RATE_PARENT, 753 .ops = &clk_rcg2_ops, 754 }, 755 }; 756 757 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 758 F(400000, P_BI_TCXO, 12, 1, 4), 759 F(9600000, P_BI_TCXO, 2, 0, 0), 760 F(19200000, P_BI_TCXO, 1, 0, 0), 761 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 762 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 763 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 764 F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0), 765 { } 766 }; 767 768 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 769 .cmd_rcgr = 0x1400c, 770 .mnd_width = 8, 771 .hid_width = 5, 772 .parent_map = gcc_parent_map_6, 773 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 774 .clkr.hw.init = &(struct clk_init_data){ 775 .name = "gcc_sdcc2_apps_clk_src", 776 .parent_data = gcc_parents_6, 777 .num_parents = ARRAY_SIZE(gcc_parents_6), 778 .flags = CLK_SET_RATE_PARENT, 779 .ops = &clk_rcg2_floor_ops, 780 }, 781 }; 782 783 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 784 F(400000, P_BI_TCXO, 12, 1, 4), 785 F(9600000, P_BI_TCXO, 2, 0, 0), 786 F(19200000, P_BI_TCXO, 1, 0, 0), 787 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 788 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 789 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 790 { } 791 }; 792 793 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 794 .cmd_rcgr = 0x1600c, 795 .mnd_width = 8, 796 .hid_width = 5, 797 .parent_map = gcc_parent_map_3, 798 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 799 .clkr.hw.init = &(struct clk_init_data){ 800 .name = "gcc_sdcc4_apps_clk_src", 801 .parent_data = gcc_parents_3, 802 .num_parents = ARRAY_SIZE(gcc_parents_3), 803 .flags = CLK_SET_RATE_PARENT, 804 .ops = &clk_rcg2_floor_ops, 805 }, 806 }; 807 808 static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { 809 F(105495, P_BI_TCXO, 2, 1, 91), 810 { } 811 }; 812 813 static struct clk_rcg2 gcc_tsif_ref_clk_src = { 814 .cmd_rcgr = 0x36010, 815 .mnd_width = 8, 816 .hid_width = 5, 817 .parent_map = gcc_parent_map_7, 818 .freq_tbl = ftbl_gcc_tsif_ref_clk_src, 819 .clkr.hw.init = &(struct clk_init_data){ 820 .name = "gcc_tsif_ref_clk_src", 821 .parent_data = gcc_parents_7, 822 .num_parents = ARRAY_SIZE(gcc_parents_7), 823 .flags = CLK_SET_RATE_PARENT, 824 .ops = &clk_rcg2_ops, 825 }, 826 }; 827 828 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { 829 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 830 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 831 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 832 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 833 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 834 { } 835 }; 836 837 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { 838 .cmd_rcgr = 0x75020, 839 .mnd_width = 8, 840 .hid_width = 5, 841 .parent_map = gcc_parent_map_0, 842 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, 843 .clkr.hw.init = &(struct clk_init_data){ 844 .name = "gcc_ufs_card_axi_clk_src", 845 .parent_data = gcc_parents_0, 846 .num_parents = ARRAY_SIZE(gcc_parents_0), 847 .flags = CLK_SET_RATE_PARENT, 848 .ops = &clk_rcg2_ops, 849 }, 850 }; 851 852 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { 853 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 854 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 855 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 856 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 857 { } 858 }; 859 860 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { 861 .cmd_rcgr = 0x75060, 862 .mnd_width = 0, 863 .hid_width = 5, 864 .parent_map = gcc_parent_map_0, 865 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 866 .clkr.hw.init = &(struct clk_init_data){ 867 .name = "gcc_ufs_card_ice_core_clk_src", 868 .parent_data = gcc_parents_0, 869 .num_parents = ARRAY_SIZE(gcc_parents_0), 870 .flags = CLK_SET_RATE_PARENT, 871 .ops = &clk_rcg2_ops, 872 }, 873 }; 874 875 static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = { 876 F(19200000, P_BI_TCXO, 1, 0, 0), 877 { } 878 }; 879 880 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { 881 .cmd_rcgr = 0x75094, 882 .mnd_width = 0, 883 .hid_width = 5, 884 .parent_map = gcc_parent_map_4, 885 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 886 .clkr.hw.init = &(struct clk_init_data){ 887 .name = "gcc_ufs_card_phy_aux_clk_src", 888 .parent_data = gcc_parents_4, 889 .num_parents = ARRAY_SIZE(gcc_parents_4), 890 .flags = CLK_SET_RATE_PARENT, 891 .ops = &clk_rcg2_ops, 892 }, 893 }; 894 895 static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { 896 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 897 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 898 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 899 { } 900 }; 901 902 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { 903 .cmd_rcgr = 0x75078, 904 .mnd_width = 0, 905 .hid_width = 5, 906 .parent_map = gcc_parent_map_0, 907 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, 908 .clkr.hw.init = &(struct clk_init_data){ 909 .name = "gcc_ufs_card_unipro_core_clk_src", 910 .parent_data = gcc_parents_0, 911 .num_parents = ARRAY_SIZE(gcc_parents_0), 912 .flags = CLK_SET_RATE_PARENT, 913 .ops = &clk_rcg2_ops, 914 }, 915 }; 916 917 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 918 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 919 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 920 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 921 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 922 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 923 { } 924 }; 925 926 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 927 .cmd_rcgr = 0x77020, 928 .mnd_width = 8, 929 .hid_width = 5, 930 .parent_map = gcc_parent_map_0, 931 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 932 .clkr.hw.init = &(struct clk_init_data){ 933 .name = "gcc_ufs_phy_axi_clk_src", 934 .parent_data = gcc_parents_0, 935 .num_parents = ARRAY_SIZE(gcc_parents_0), 936 .flags = CLK_SET_RATE_PARENT, 937 .ops = &clk_rcg2_ops, 938 }, 939 }; 940 941 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 942 .cmd_rcgr = 0x77060, 943 .mnd_width = 0, 944 .hid_width = 5, 945 .parent_map = gcc_parent_map_0, 946 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 947 .clkr.hw.init = &(struct clk_init_data){ 948 .name = "gcc_ufs_phy_ice_core_clk_src", 949 .parent_data = gcc_parents_0, 950 .num_parents = ARRAY_SIZE(gcc_parents_0), 951 .flags = CLK_SET_RATE_PARENT, 952 .ops = &clk_rcg2_ops, 953 }, 954 }; 955 956 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 957 .cmd_rcgr = 0x77094, 958 .mnd_width = 0, 959 .hid_width = 5, 960 .parent_map = gcc_parent_map_4, 961 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 962 .clkr.hw.init = &(struct clk_init_data){ 963 .name = "gcc_ufs_phy_phy_aux_clk_src", 964 .parent_data = gcc_parents_4, 965 .num_parents = ARRAY_SIZE(gcc_parents_4), 966 .flags = CLK_SET_RATE_PARENT, 967 .ops = &clk_rcg2_ops, 968 }, 969 }; 970 971 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 972 .cmd_rcgr = 0x77078, 973 .mnd_width = 0, 974 .hid_width = 5, 975 .parent_map = gcc_parent_map_0, 976 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 977 .clkr.hw.init = &(struct clk_init_data){ 978 .name = "gcc_ufs_phy_unipro_core_clk_src", 979 .parent_data = gcc_parents_0, 980 .num_parents = ARRAY_SIZE(gcc_parents_0), 981 .flags = CLK_SET_RATE_PARENT, 982 .ops = &clk_rcg2_ops, 983 }, 984 }; 985 986 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 987 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), 988 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), 989 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 990 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 991 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 992 { } 993 }; 994 995 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 996 .cmd_rcgr = 0xf01c, 997 .mnd_width = 8, 998 .hid_width = 5, 999 .parent_map = gcc_parent_map_0, 1000 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1001 .clkr.hw.init = &(struct clk_init_data){ 1002 .name = "gcc_usb30_prim_master_clk_src", 1003 .parent_data = gcc_parents_0, 1004 .num_parents = ARRAY_SIZE(gcc_parents_0), 1005 .flags = CLK_SET_RATE_PARENT, 1006 .ops = &clk_rcg2_ops, 1007 }, 1008 }; 1009 1010 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 1011 F(19200000, P_BI_TCXO, 1, 0, 0), 1012 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), 1013 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), 1014 { } 1015 }; 1016 1017 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1018 .cmd_rcgr = 0xf034, 1019 .mnd_width = 0, 1020 .hid_width = 5, 1021 .parent_map = gcc_parent_map_0, 1022 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1023 .clkr.hw.init = &(struct clk_init_data){ 1024 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1025 .parent_data = gcc_parents_0, 1026 .num_parents = ARRAY_SIZE(gcc_parents_0), 1027 .flags = CLK_SET_RATE_PARENT, 1028 .ops = &clk_rcg2_ops, 1029 }, 1030 }; 1031 1032 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { 1033 .cmd_rcgr = 0x1001c, 1034 .mnd_width = 8, 1035 .hid_width = 5, 1036 .parent_map = gcc_parent_map_0, 1037 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1038 .clkr.hw.init = &(struct clk_init_data){ 1039 .name = "gcc_usb30_sec_master_clk_src", 1040 .parent_data = gcc_parents_0, 1041 .num_parents = ARRAY_SIZE(gcc_parents_0), 1042 .flags = CLK_SET_RATE_PARENT, 1043 .ops = &clk_rcg2_ops, 1044 }, 1045 }; 1046 1047 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { 1048 .cmd_rcgr = 0x10034, 1049 .mnd_width = 0, 1050 .hid_width = 5, 1051 .parent_map = gcc_parent_map_0, 1052 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1053 .clkr.hw.init = &(struct clk_init_data){ 1054 .name = "gcc_usb30_sec_mock_utmi_clk_src", 1055 .parent_data = gcc_parents_0, 1056 .num_parents = ARRAY_SIZE(gcc_parents_0), 1057 .flags = CLK_SET_RATE_PARENT, 1058 .ops = &clk_rcg2_ops, 1059 }, 1060 }; 1061 1062 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1063 .cmd_rcgr = 0xf060, 1064 .mnd_width = 0, 1065 .hid_width = 5, 1066 .parent_map = gcc_parent_map_2, 1067 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 1068 .clkr.hw.init = &(struct clk_init_data){ 1069 .name = "gcc_usb3_prim_phy_aux_clk_src", 1070 .parent_data = gcc_parents_2, 1071 .num_parents = ARRAY_SIZE(gcc_parents_2), 1072 .flags = CLK_SET_RATE_PARENT, 1073 .ops = &clk_rcg2_ops, 1074 }, 1075 }; 1076 1077 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { 1078 .cmd_rcgr = 0x10060, 1079 .mnd_width = 0, 1080 .hid_width = 5, 1081 .parent_map = gcc_parent_map_2, 1082 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 1083 .clkr.hw.init = &(struct clk_init_data){ 1084 .name = "gcc_usb3_sec_phy_aux_clk_src", 1085 .parent_data = gcc_parents_2, 1086 .num_parents = ARRAY_SIZE(gcc_parents_2), 1087 .flags = CLK_SET_RATE_PARENT, 1088 .ops = &clk_rcg2_ops, 1089 }, 1090 }; 1091 1092 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { 1093 .halt_reg = 0x90018, 1094 .halt_check = BRANCH_HALT, 1095 .clkr = { 1096 .enable_reg = 0x90018, 1097 .enable_mask = BIT(0), 1098 .hw.init = &(struct clk_init_data){ 1099 .name = "gcc_aggre_noc_pcie_tbu_clk", 1100 .ops = &clk_branch2_ops, 1101 }, 1102 }, 1103 }; 1104 1105 static struct clk_branch gcc_aggre_ufs_card_axi_clk = { 1106 .halt_reg = 0x750c0, 1107 .halt_check = BRANCH_HALT, 1108 .hwcg_reg = 0x750c0, 1109 .hwcg_bit = 1, 1110 .clkr = { 1111 .enable_reg = 0x750c0, 1112 .enable_mask = BIT(0), 1113 .hw.init = &(struct clk_init_data){ 1114 .name = "gcc_aggre_ufs_card_axi_clk", 1115 .parent_hws = (const struct clk_hw *[]){ 1116 &gcc_ufs_card_axi_clk_src.clkr.hw }, 1117 .num_parents = 1, 1118 .flags = CLK_SET_RATE_PARENT, 1119 .ops = &clk_branch2_ops, 1120 }, 1121 }, 1122 }; 1123 1124 static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = { 1125 .halt_reg = 0x750c0, 1126 .halt_check = BRANCH_HALT, 1127 .hwcg_reg = 0x750c0, 1128 .hwcg_bit = 1, 1129 .clkr = { 1130 .enable_reg = 0x750c0, 1131 .enable_mask = BIT(1), 1132 .hw.init = &(struct clk_init_data){ 1133 .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk", 1134 .parent_hws = (const struct clk_hw *[]){ 1135 &gcc_aggre_ufs_card_axi_clk.clkr.hw }, 1136 .num_parents = 1, 1137 .flags = CLK_SET_RATE_PARENT, 1138 .ops = &clk_branch_simple_ops, 1139 }, 1140 }, 1141 }; 1142 1143 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1144 .halt_reg = 0x770c0, 1145 .halt_check = BRANCH_HALT, 1146 .hwcg_reg = 0x770c0, 1147 .hwcg_bit = 1, 1148 .clkr = { 1149 .enable_reg = 0x770c0, 1150 .enable_mask = BIT(0), 1151 .hw.init = &(struct clk_init_data){ 1152 .name = "gcc_aggre_ufs_phy_axi_clk", 1153 .parent_hws = (const struct clk_hw *[]){ 1154 &gcc_ufs_phy_axi_clk_src.clkr.hw }, 1155 .num_parents = 1, 1156 .flags = CLK_SET_RATE_PARENT, 1157 .ops = &clk_branch2_ops, 1158 }, 1159 }, 1160 }; 1161 1162 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { 1163 .halt_reg = 0x770c0, 1164 .halt_check = BRANCH_HALT, 1165 .hwcg_reg = 0x770c0, 1166 .hwcg_bit = 1, 1167 .clkr = { 1168 .enable_reg = 0x770c0, 1169 .enable_mask = BIT(1), 1170 .hw.init = &(struct clk_init_data){ 1171 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", 1172 .parent_hws = (const struct clk_hw *[]){ 1173 &gcc_aggre_ufs_phy_axi_clk.clkr.hw }, 1174 .num_parents = 1, 1175 .flags = CLK_SET_RATE_PARENT, 1176 .ops = &clk_branch_simple_ops, 1177 }, 1178 }, 1179 }; 1180 1181 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1182 .halt_reg = 0xf07c, 1183 .halt_check = BRANCH_HALT, 1184 .clkr = { 1185 .enable_reg = 0xf07c, 1186 .enable_mask = BIT(0), 1187 .hw.init = &(struct clk_init_data){ 1188 .name = "gcc_aggre_usb3_prim_axi_clk", 1189 .parent_hws = (const struct clk_hw *[]){ 1190 &gcc_usb30_prim_master_clk_src.clkr.hw }, 1191 .num_parents = 1, 1192 .flags = CLK_SET_RATE_PARENT, 1193 .ops = &clk_branch2_ops, 1194 }, 1195 }, 1196 }; 1197 1198 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { 1199 .halt_reg = 0x1007c, 1200 .halt_check = BRANCH_HALT, 1201 .clkr = { 1202 .enable_reg = 0x1007c, 1203 .enable_mask = BIT(0), 1204 .hw.init = &(struct clk_init_data){ 1205 .name = "gcc_aggre_usb3_sec_axi_clk", 1206 .parent_hws = (const struct clk_hw *[]){ 1207 &gcc_usb30_sec_master_clk_src.clkr.hw }, 1208 .num_parents = 1, 1209 .flags = CLK_SET_RATE_PARENT, 1210 .ops = &clk_branch2_ops, 1211 }, 1212 }, 1213 }; 1214 1215 static struct clk_branch gcc_boot_rom_ahb_clk = { 1216 .halt_reg = 0x38004, 1217 .halt_check = BRANCH_HALT_VOTED, 1218 .hwcg_reg = 0x38004, 1219 .hwcg_bit = 1, 1220 .clkr = { 1221 .enable_reg = 0x52004, 1222 .enable_mask = BIT(10), 1223 .hw.init = &(struct clk_init_data){ 1224 .name = "gcc_boot_rom_ahb_clk", 1225 .ops = &clk_branch2_ops, 1226 }, 1227 }, 1228 }; 1229 1230 /* 1231 * Clock ON depends on external parent 'config noc', so cant poll 1232 * delay and also mark as crtitical for camss boot 1233 */ 1234 static struct clk_branch gcc_camera_ahb_clk = { 1235 .halt_reg = 0xb008, 1236 .halt_check = BRANCH_HALT_DELAY, 1237 .hwcg_reg = 0xb008, 1238 .hwcg_bit = 1, 1239 .clkr = { 1240 .enable_reg = 0xb008, 1241 .enable_mask = BIT(0), 1242 .hw.init = &(struct clk_init_data){ 1243 .name = "gcc_camera_ahb_clk", 1244 .flags = CLK_IS_CRITICAL, 1245 .ops = &clk_branch2_ops, 1246 }, 1247 }, 1248 }; 1249 1250 static struct clk_branch gcc_camera_hf_axi_clk = { 1251 .halt_reg = 0xb030, 1252 .halt_check = BRANCH_HALT, 1253 .clkr = { 1254 .enable_reg = 0xb030, 1255 .enable_mask = BIT(0), 1256 .hw.init = &(struct clk_init_data){ 1257 .name = "gcc_camera_hf_axi_clk", 1258 .ops = &clk_branch2_ops, 1259 }, 1260 }, 1261 }; 1262 1263 static struct clk_branch gcc_camera_sf_axi_clk = { 1264 .halt_reg = 0xb034, 1265 .halt_check = BRANCH_HALT, 1266 .clkr = { 1267 .enable_reg = 0xb034, 1268 .enable_mask = BIT(0), 1269 .hw.init = &(struct clk_init_data){ 1270 .name = "gcc_camera_sf_axi_clk", 1271 .ops = &clk_branch2_ops, 1272 }, 1273 }, 1274 }; 1275 1276 /* XO critical input to camss, so no need to poll */ 1277 static struct clk_branch gcc_camera_xo_clk = { 1278 .halt_reg = 0xb044, 1279 .halt_check = BRANCH_HALT_DELAY, 1280 .clkr = { 1281 .enable_reg = 0xb044, 1282 .enable_mask = BIT(0), 1283 .hw.init = &(struct clk_init_data){ 1284 .name = "gcc_camera_xo_clk", 1285 .flags = CLK_IS_CRITICAL, 1286 .ops = &clk_branch2_ops, 1287 }, 1288 }, 1289 }; 1290 1291 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1292 .halt_reg = 0xf078, 1293 .halt_check = BRANCH_HALT, 1294 .clkr = { 1295 .enable_reg = 0xf078, 1296 .enable_mask = BIT(0), 1297 .hw.init = &(struct clk_init_data){ 1298 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1299 .parent_hws = (const struct clk_hw *[]){ 1300 &gcc_usb30_prim_master_clk_src.clkr.hw }, 1301 .num_parents = 1, 1302 .flags = CLK_SET_RATE_PARENT, 1303 .ops = &clk_branch2_ops, 1304 }, 1305 }, 1306 }; 1307 1308 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { 1309 .halt_reg = 0x10078, 1310 .halt_check = BRANCH_HALT, 1311 .clkr = { 1312 .enable_reg = 0x10078, 1313 .enable_mask = BIT(0), 1314 .hw.init = &(struct clk_init_data){ 1315 .name = "gcc_cfg_noc_usb3_sec_axi_clk", 1316 .parent_hws = (const struct clk_hw *[]){ 1317 &gcc_usb30_sec_master_clk_src.clkr.hw }, 1318 .num_parents = 1, 1319 .flags = CLK_SET_RATE_PARENT, 1320 .ops = &clk_branch2_ops, 1321 }, 1322 }, 1323 }; 1324 1325 static struct clk_branch gcc_cpuss_ahb_clk = { 1326 .halt_reg = 0x48000, 1327 .halt_check = BRANCH_HALT_VOTED, 1328 .clkr = { 1329 .enable_reg = 0x52004, 1330 .enable_mask = BIT(21), 1331 .hw.init = &(struct clk_init_data){ 1332 .name = "gcc_cpuss_ahb_clk", 1333 .parent_hws = (const struct clk_hw *[]){ 1334 &gcc_cpuss_ahb_clk_src.clkr.hw }, 1335 .num_parents = 1, 1336 /* required for cpuss */ 1337 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 1338 .ops = &clk_branch2_ops, 1339 }, 1340 }, 1341 }; 1342 1343 static struct clk_branch gcc_cpuss_dvm_bus_clk = { 1344 .halt_reg = 0x48190, 1345 .halt_check = BRANCH_HALT, 1346 .clkr = { 1347 .enable_reg = 0x48190, 1348 .enable_mask = BIT(0), 1349 .hw.init = &(struct clk_init_data){ 1350 .name = "gcc_cpuss_dvm_bus_clk", 1351 /* required for cpuss */ 1352 .flags = CLK_IS_CRITICAL, 1353 .ops = &clk_branch2_ops, 1354 }, 1355 }, 1356 }; 1357 1358 static struct clk_branch gcc_cpuss_gnoc_clk = { 1359 .halt_reg = 0x48004, 1360 .halt_check = BRANCH_HALT_VOTED, 1361 .hwcg_reg = 0x48004, 1362 .hwcg_bit = 1, 1363 .clkr = { 1364 .enable_reg = 0x52004, 1365 .enable_mask = BIT(22), 1366 .hw.init = &(struct clk_init_data){ 1367 .name = "gcc_cpuss_gnoc_clk", 1368 /* required for cpuss */ 1369 .flags = CLK_IS_CRITICAL, 1370 .ops = &clk_branch2_ops, 1371 }, 1372 }, 1373 }; 1374 1375 static struct clk_branch gcc_cpuss_rbcpr_clk = { 1376 .halt_reg = 0x48008, 1377 .halt_check = BRANCH_HALT, 1378 .clkr = { 1379 .enable_reg = 0x48008, 1380 .enable_mask = BIT(0), 1381 .hw.init = &(struct clk_init_data){ 1382 .name = "gcc_cpuss_rbcpr_clk", 1383 .ops = &clk_branch2_ops, 1384 }, 1385 }, 1386 }; 1387 1388 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1389 .halt_reg = 0x71154, 1390 .halt_check = BRANCH_VOTED, 1391 .clkr = { 1392 .enable_reg = 0x71154, 1393 .enable_mask = BIT(0), 1394 .hw.init = &(struct clk_init_data){ 1395 .name = "gcc_ddrss_gpu_axi_clk", 1396 .ops = &clk_branch2_ops, 1397 }, 1398 }, 1399 }; 1400 1401 /* 1402 * Clock ON depends on external parent 'config noc', so cant poll 1403 * delay and also mark as crtitical for disp boot 1404 */ 1405 static struct clk_branch gcc_disp_ahb_clk = { 1406 .halt_reg = 0xb00c, 1407 .halt_check = BRANCH_HALT_DELAY, 1408 .hwcg_reg = 0xb00c, 1409 .hwcg_bit = 1, 1410 .clkr = { 1411 .enable_reg = 0xb00c, 1412 .enable_mask = BIT(0), 1413 .hw.init = &(struct clk_init_data){ 1414 .name = "gcc_disp_ahb_clk", 1415 .flags = CLK_IS_CRITICAL, 1416 .ops = &clk_branch2_ops, 1417 }, 1418 }, 1419 }; 1420 1421 static struct clk_branch gcc_disp_hf_axi_clk = { 1422 .halt_reg = 0xb038, 1423 .halt_check = BRANCH_HALT, 1424 .clkr = { 1425 .enable_reg = 0xb038, 1426 .enable_mask = BIT(0), 1427 .hw.init = &(struct clk_init_data){ 1428 .name = "gcc_disp_hf_axi_clk", 1429 .ops = &clk_branch2_ops, 1430 }, 1431 }, 1432 }; 1433 1434 static struct clk_branch gcc_disp_sf_axi_clk = { 1435 .halt_reg = 0xb03c, 1436 .halt_check = BRANCH_HALT, 1437 .clkr = { 1438 .enable_reg = 0xb03c, 1439 .enable_mask = BIT(0), 1440 .hw.init = &(struct clk_init_data){ 1441 .name = "gcc_disp_sf_axi_clk", 1442 .ops = &clk_branch2_ops, 1443 }, 1444 }, 1445 }; 1446 1447 /* XO critical input to disp, so no need to poll */ 1448 static struct clk_branch gcc_disp_xo_clk = { 1449 .halt_reg = 0xb048, 1450 .halt_check = BRANCH_HALT_DELAY, 1451 .clkr = { 1452 .enable_reg = 0xb048, 1453 .enable_mask = BIT(0), 1454 .hw.init = &(struct clk_init_data){ 1455 .name = "gcc_disp_xo_clk", 1456 .flags = CLK_IS_CRITICAL, 1457 .ops = &clk_branch2_ops, 1458 }, 1459 }, 1460 }; 1461 1462 static struct clk_branch gcc_emac_axi_clk = { 1463 .halt_reg = 0x6010, 1464 .halt_check = BRANCH_HALT, 1465 .clkr = { 1466 .enable_reg = 0x6010, 1467 .enable_mask = BIT(0), 1468 .hw.init = &(struct clk_init_data){ 1469 .name = "gcc_emac_axi_clk", 1470 .ops = &clk_branch2_ops, 1471 }, 1472 }, 1473 }; 1474 1475 static struct clk_branch gcc_emac_ptp_clk = { 1476 .halt_reg = 0x6034, 1477 .halt_check = BRANCH_HALT, 1478 .clkr = { 1479 .enable_reg = 0x6034, 1480 .enable_mask = BIT(0), 1481 .hw.init = &(struct clk_init_data){ 1482 .name = "gcc_emac_ptp_clk", 1483 .parent_hws = (const struct clk_hw *[]){ 1484 &gcc_emac_ptp_clk_src.clkr.hw }, 1485 .num_parents = 1, 1486 .flags = CLK_SET_RATE_PARENT, 1487 .ops = &clk_branch2_ops, 1488 }, 1489 }, 1490 }; 1491 1492 static struct clk_branch gcc_emac_rgmii_clk = { 1493 .halt_reg = 0x6018, 1494 .halt_check = BRANCH_HALT, 1495 .clkr = { 1496 .enable_reg = 0x6018, 1497 .enable_mask = BIT(0), 1498 .hw.init = &(struct clk_init_data){ 1499 .name = "gcc_emac_rgmii_clk", 1500 .parent_hws = (const struct clk_hw *[]){ 1501 &gcc_emac_rgmii_clk_src.clkr.hw }, 1502 .num_parents = 1, 1503 .flags = CLK_SET_RATE_PARENT, 1504 .ops = &clk_branch2_ops, 1505 }, 1506 }, 1507 }; 1508 1509 static struct clk_branch gcc_emac_slv_ahb_clk = { 1510 .halt_reg = 0x6014, 1511 .halt_check = BRANCH_HALT, 1512 .hwcg_reg = 0x6014, 1513 .hwcg_bit = 1, 1514 .clkr = { 1515 .enable_reg = 0x6014, 1516 .enable_mask = BIT(0), 1517 .hw.init = &(struct clk_init_data){ 1518 .name = "gcc_emac_slv_ahb_clk", 1519 .ops = &clk_branch2_ops, 1520 }, 1521 }, 1522 }; 1523 1524 static struct clk_branch gcc_gp1_clk = { 1525 .halt_reg = 0x64000, 1526 .halt_check = BRANCH_HALT, 1527 .clkr = { 1528 .enable_reg = 0x64000, 1529 .enable_mask = BIT(0), 1530 .hw.init = &(struct clk_init_data){ 1531 .name = "gcc_gp1_clk", 1532 .parent_hws = (const struct clk_hw *[]){ 1533 &gcc_gp1_clk_src.clkr.hw }, 1534 .num_parents = 1, 1535 .flags = CLK_SET_RATE_PARENT, 1536 .ops = &clk_branch2_ops, 1537 }, 1538 }, 1539 }; 1540 1541 static struct clk_branch gcc_gp2_clk = { 1542 .halt_reg = 0x65000, 1543 .halt_check = BRANCH_HALT, 1544 .clkr = { 1545 .enable_reg = 0x65000, 1546 .enable_mask = BIT(0), 1547 .hw.init = &(struct clk_init_data){ 1548 .name = "gcc_gp2_clk", 1549 .parent_hws = (const struct clk_hw *[]){ 1550 &gcc_gp2_clk_src.clkr.hw }, 1551 .num_parents = 1, 1552 .flags = CLK_SET_RATE_PARENT, 1553 .ops = &clk_branch2_ops, 1554 }, 1555 }, 1556 }; 1557 1558 static struct clk_branch gcc_gp3_clk = { 1559 .halt_reg = 0x66000, 1560 .halt_check = BRANCH_HALT, 1561 .clkr = { 1562 .enable_reg = 0x66000, 1563 .enable_mask = BIT(0), 1564 .hw.init = &(struct clk_init_data){ 1565 .name = "gcc_gp3_clk", 1566 .parent_hws = (const struct clk_hw *[]){ 1567 &gcc_gp3_clk_src.clkr.hw }, 1568 .num_parents = 1, 1569 .flags = CLK_SET_RATE_PARENT, 1570 .ops = &clk_branch2_ops, 1571 }, 1572 }, 1573 }; 1574 1575 static struct clk_branch gcc_gpu_cfg_ahb_clk = { 1576 .halt_reg = 0x71004, 1577 .halt_check = BRANCH_HALT, 1578 .hwcg_reg = 0x71004, 1579 .hwcg_bit = 1, 1580 .clkr = { 1581 .enable_reg = 0x71004, 1582 .enable_mask = BIT(0), 1583 .hw.init = &(struct clk_init_data){ 1584 .name = "gcc_gpu_cfg_ahb_clk", 1585 /* required for gpu */ 1586 .flags = CLK_IS_CRITICAL, 1587 .ops = &clk_branch2_ops, 1588 }, 1589 }, 1590 }; 1591 1592 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1593 .halt_check = BRANCH_HALT_SKIP, 1594 .clkr = { 1595 .enable_reg = 0x52004, 1596 .enable_mask = BIT(15), 1597 .hw.init = &(struct clk_init_data){ 1598 .name = "gcc_gpu_gpll0_clk_src", 1599 .parent_hws = (const struct clk_hw *[]){ 1600 &gpll0.clkr.hw }, 1601 .num_parents = 1, 1602 .flags = CLK_SET_RATE_PARENT, 1603 .ops = &clk_branch2_ops, 1604 }, 1605 }, 1606 }; 1607 1608 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1609 .halt_check = BRANCH_HALT_SKIP, 1610 .clkr = { 1611 .enable_reg = 0x52004, 1612 .enable_mask = BIT(16), 1613 .hw.init = &(struct clk_init_data){ 1614 .name = "gcc_gpu_gpll0_div_clk_src", 1615 .parent_hws = (const struct clk_hw *[]){ 1616 &gpll0_out_even.clkr.hw }, 1617 .num_parents = 1, 1618 .flags = CLK_SET_RATE_PARENT, 1619 .ops = &clk_branch2_ops, 1620 }, 1621 }, 1622 }; 1623 1624 static struct clk_branch gcc_gpu_iref_clk = { 1625 .halt_reg = 0x8c010, 1626 .halt_check = BRANCH_HALT, 1627 .clkr = { 1628 .enable_reg = 0x8c010, 1629 .enable_mask = BIT(0), 1630 .hw.init = &(struct clk_init_data){ 1631 .name = "gcc_gpu_iref_clk", 1632 .ops = &clk_branch2_ops, 1633 }, 1634 }, 1635 }; 1636 1637 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1638 .halt_reg = 0x7100c, 1639 .halt_check = BRANCH_VOTED, 1640 .clkr = { 1641 .enable_reg = 0x7100c, 1642 .enable_mask = BIT(0), 1643 .hw.init = &(struct clk_init_data){ 1644 .name = "gcc_gpu_memnoc_gfx_clk", 1645 .ops = &clk_branch2_ops, 1646 }, 1647 }, 1648 }; 1649 1650 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1651 .halt_reg = 0x71018, 1652 .halt_check = BRANCH_HALT, 1653 .clkr = { 1654 .enable_reg = 0x71018, 1655 .enable_mask = BIT(0), 1656 .hw.init = &(struct clk_init_data){ 1657 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1658 .ops = &clk_branch2_ops, 1659 }, 1660 }, 1661 }; 1662 1663 static struct clk_branch gcc_npu_at_clk = { 1664 .halt_reg = 0x4d010, 1665 .halt_check = BRANCH_VOTED, 1666 .clkr = { 1667 .enable_reg = 0x4d010, 1668 .enable_mask = BIT(0), 1669 .hw.init = &(struct clk_init_data){ 1670 .name = "gcc_npu_at_clk", 1671 .ops = &clk_branch2_ops, 1672 }, 1673 }, 1674 }; 1675 1676 static struct clk_branch gcc_npu_axi_clk = { 1677 .halt_reg = 0x4d008, 1678 .halt_check = BRANCH_VOTED, 1679 .clkr = { 1680 .enable_reg = 0x4d008, 1681 .enable_mask = BIT(0), 1682 .hw.init = &(struct clk_init_data){ 1683 .name = "gcc_npu_axi_clk", 1684 .ops = &clk_branch2_ops, 1685 }, 1686 }, 1687 }; 1688 1689 static struct clk_branch gcc_npu_cfg_ahb_clk = { 1690 .halt_reg = 0x4d004, 1691 .halt_check = BRANCH_HALT, 1692 .hwcg_reg = 0x4d004, 1693 .hwcg_bit = 1, 1694 .clkr = { 1695 .enable_reg = 0x4d004, 1696 .enable_mask = BIT(0), 1697 .hw.init = &(struct clk_init_data){ 1698 .name = "gcc_npu_cfg_ahb_clk", 1699 /* required for npu */ 1700 .flags = CLK_IS_CRITICAL, 1701 .ops = &clk_branch2_ops, 1702 }, 1703 }, 1704 }; 1705 1706 static struct clk_branch gcc_npu_gpll0_clk_src = { 1707 .halt_check = BRANCH_HALT_SKIP, 1708 .clkr = { 1709 .enable_reg = 0x52004, 1710 .enable_mask = BIT(18), 1711 .hw.init = &(struct clk_init_data){ 1712 .name = "gcc_npu_gpll0_clk_src", 1713 .parent_hws = (const struct clk_hw *[]){ 1714 &gpll0.clkr.hw }, 1715 .num_parents = 1, 1716 .flags = CLK_SET_RATE_PARENT, 1717 .ops = &clk_branch2_ops, 1718 }, 1719 }, 1720 }; 1721 1722 static struct clk_branch gcc_npu_gpll0_div_clk_src = { 1723 .halt_check = BRANCH_HALT_SKIP, 1724 .clkr = { 1725 .enable_reg = 0x52004, 1726 .enable_mask = BIT(19), 1727 .hw.init = &(struct clk_init_data){ 1728 .name = "gcc_npu_gpll0_div_clk_src", 1729 .parent_hws = (const struct clk_hw *[]){ 1730 &gpll0_out_even.clkr.hw }, 1731 .num_parents = 1, 1732 .flags = CLK_SET_RATE_PARENT, 1733 .ops = &clk_branch2_ops, 1734 }, 1735 }, 1736 }; 1737 1738 static struct clk_branch gcc_npu_trig_clk = { 1739 .halt_reg = 0x4d00c, 1740 .halt_check = BRANCH_VOTED, 1741 .clkr = { 1742 .enable_reg = 0x4d00c, 1743 .enable_mask = BIT(0), 1744 .hw.init = &(struct clk_init_data){ 1745 .name = "gcc_npu_trig_clk", 1746 .ops = &clk_branch2_ops, 1747 }, 1748 }, 1749 }; 1750 1751 static struct clk_branch gcc_pcie0_phy_refgen_clk = { 1752 .halt_reg = 0x6f02c, 1753 .halt_check = BRANCH_HALT, 1754 .clkr = { 1755 .enable_reg = 0x6f02c, 1756 .enable_mask = BIT(0), 1757 .hw.init = &(struct clk_init_data){ 1758 .name = "gcc_pcie0_phy_refgen_clk", 1759 .parent_hws = (const struct clk_hw *[]){ 1760 &gcc_pcie_phy_refgen_clk_src.clkr.hw }, 1761 .num_parents = 1, 1762 .flags = CLK_SET_RATE_PARENT, 1763 .ops = &clk_branch2_ops, 1764 }, 1765 }, 1766 }; 1767 1768 static struct clk_branch gcc_pcie1_phy_refgen_clk = { 1769 .halt_reg = 0x6f030, 1770 .halt_check = BRANCH_HALT, 1771 .clkr = { 1772 .enable_reg = 0x6f030, 1773 .enable_mask = BIT(0), 1774 .hw.init = &(struct clk_init_data){ 1775 .name = "gcc_pcie1_phy_refgen_clk", 1776 .parent_hws = (const struct clk_hw *[]){ 1777 &gcc_pcie_phy_refgen_clk_src.clkr.hw }, 1778 .num_parents = 1, 1779 .flags = CLK_SET_RATE_PARENT, 1780 .ops = &clk_branch2_ops, 1781 }, 1782 }, 1783 }; 1784 1785 static struct clk_branch gcc_pcie_0_aux_clk = { 1786 .halt_reg = 0x6b020, 1787 .halt_check = BRANCH_HALT_VOTED, 1788 .clkr = { 1789 .enable_reg = 0x5200c, 1790 .enable_mask = BIT(3), 1791 .hw.init = &(struct clk_init_data){ 1792 .name = "gcc_pcie_0_aux_clk", 1793 .parent_hws = (const struct clk_hw *[]){ 1794 &gcc_pcie_0_aux_clk_src.clkr.hw }, 1795 .num_parents = 1, 1796 .flags = CLK_SET_RATE_PARENT, 1797 .ops = &clk_branch2_ops, 1798 }, 1799 }, 1800 }; 1801 1802 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1803 .halt_reg = 0x6b01c, 1804 .halt_check = BRANCH_HALT_VOTED, 1805 .hwcg_reg = 0x6b01c, 1806 .hwcg_bit = 1, 1807 .clkr = { 1808 .enable_reg = 0x5200c, 1809 .enable_mask = BIT(2), 1810 .hw.init = &(struct clk_init_data){ 1811 .name = "gcc_pcie_0_cfg_ahb_clk", 1812 .ops = &clk_branch2_ops, 1813 }, 1814 }, 1815 }; 1816 1817 static struct clk_branch gcc_pcie_0_clkref_clk = { 1818 .halt_reg = 0x8c00c, 1819 .halt_check = BRANCH_HALT, 1820 .clkr = { 1821 .enable_reg = 0x8c00c, 1822 .enable_mask = BIT(0), 1823 .hw.init = &(struct clk_init_data){ 1824 .name = "gcc_pcie_0_clkref_clk", 1825 .ops = &clk_branch2_ops, 1826 }, 1827 }, 1828 }; 1829 1830 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1831 .halt_reg = 0x6b018, 1832 .halt_check = BRANCH_HALT_VOTED, 1833 .clkr = { 1834 .enable_reg = 0x5200c, 1835 .enable_mask = BIT(1), 1836 .hw.init = &(struct clk_init_data){ 1837 .name = "gcc_pcie_0_mstr_axi_clk", 1838 .ops = &clk_branch2_ops, 1839 }, 1840 }, 1841 }; 1842 1843 /* Clock ON depends on external parent 'PIPE' clock, so dont poll */ 1844 static struct clk_branch gcc_pcie_0_pipe_clk = { 1845 .halt_reg = 0x6b024, 1846 .halt_check = BRANCH_HALT_DELAY, 1847 .clkr = { 1848 .enable_reg = 0x5200c, 1849 .enable_mask = BIT(4), 1850 .hw.init = &(struct clk_init_data){ 1851 .name = "gcc_pcie_0_pipe_clk", 1852 .ops = &clk_branch2_ops, 1853 }, 1854 }, 1855 }; 1856 1857 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1858 .halt_reg = 0x6b014, 1859 .halt_check = BRANCH_HALT_VOTED, 1860 .hwcg_reg = 0x6b014, 1861 .hwcg_bit = 1, 1862 .clkr = { 1863 .enable_reg = 0x5200c, 1864 .enable_mask = BIT(0), 1865 .hw.init = &(struct clk_init_data){ 1866 .name = "gcc_pcie_0_slv_axi_clk", 1867 .ops = &clk_branch2_ops, 1868 }, 1869 }, 1870 }; 1871 1872 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1873 .halt_reg = 0x6b010, 1874 .halt_check = BRANCH_HALT_VOTED, 1875 .clkr = { 1876 .enable_reg = 0x5200c, 1877 .enable_mask = BIT(5), 1878 .hw.init = &(struct clk_init_data){ 1879 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1880 .ops = &clk_branch2_ops, 1881 }, 1882 }, 1883 }; 1884 1885 static struct clk_branch gcc_pcie_1_aux_clk = { 1886 .halt_reg = 0x8d020, 1887 .halt_check = BRANCH_HALT_VOTED, 1888 .clkr = { 1889 .enable_reg = 0x52004, 1890 .enable_mask = BIT(29), 1891 .hw.init = &(struct clk_init_data){ 1892 .name = "gcc_pcie_1_aux_clk", 1893 .parent_hws = (const struct clk_hw *[]){ 1894 &gcc_pcie_1_aux_clk_src.clkr.hw }, 1895 .num_parents = 1, 1896 .flags = CLK_SET_RATE_PARENT, 1897 .ops = &clk_branch2_ops, 1898 }, 1899 }, 1900 }; 1901 1902 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1903 .halt_reg = 0x8d01c, 1904 .halt_check = BRANCH_HALT_VOTED, 1905 .hwcg_reg = 0x8d01c, 1906 .hwcg_bit = 1, 1907 .clkr = { 1908 .enable_reg = 0x52004, 1909 .enable_mask = BIT(28), 1910 .hw.init = &(struct clk_init_data){ 1911 .name = "gcc_pcie_1_cfg_ahb_clk", 1912 .ops = &clk_branch2_ops, 1913 }, 1914 }, 1915 }; 1916 1917 static struct clk_branch gcc_pcie_1_clkref_clk = { 1918 .halt_reg = 0x8c02c, 1919 .halt_check = BRANCH_HALT, 1920 .clkr = { 1921 .enable_reg = 0x8c02c, 1922 .enable_mask = BIT(0), 1923 .hw.init = &(struct clk_init_data){ 1924 .name = "gcc_pcie_1_clkref_clk", 1925 .ops = &clk_branch2_ops, 1926 }, 1927 }, 1928 }; 1929 1930 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1931 .halt_reg = 0x8d018, 1932 .halt_check = BRANCH_HALT_VOTED, 1933 .clkr = { 1934 .enable_reg = 0x52004, 1935 .enable_mask = BIT(27), 1936 .hw.init = &(struct clk_init_data){ 1937 .name = "gcc_pcie_1_mstr_axi_clk", 1938 .ops = &clk_branch2_ops, 1939 }, 1940 }, 1941 }; 1942 1943 /* Clock ON depends on external parent 'PIPE' clock, so dont poll */ 1944 static struct clk_branch gcc_pcie_1_pipe_clk = { 1945 .halt_reg = 0x8d024, 1946 .halt_check = BRANCH_HALT_DELAY, 1947 .clkr = { 1948 .enable_reg = 0x52004, 1949 .enable_mask = BIT(30), 1950 .hw.init = &(struct clk_init_data){ 1951 .name = "gcc_pcie_1_pipe_clk", 1952 .ops = &clk_branch2_ops, 1953 }, 1954 }, 1955 }; 1956 1957 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1958 .halt_reg = 0x8d014, 1959 .halt_check = BRANCH_HALT_VOTED, 1960 .hwcg_reg = 0x8d014, 1961 .hwcg_bit = 1, 1962 .clkr = { 1963 .enable_reg = 0x52004, 1964 .enable_mask = BIT(26), 1965 .hw.init = &(struct clk_init_data){ 1966 .name = "gcc_pcie_1_slv_axi_clk", 1967 .ops = &clk_branch2_ops, 1968 }, 1969 }, 1970 }; 1971 1972 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 1973 .halt_reg = 0x8d010, 1974 .halt_check = BRANCH_HALT_VOTED, 1975 .clkr = { 1976 .enable_reg = 0x52004, 1977 .enable_mask = BIT(25), 1978 .hw.init = &(struct clk_init_data){ 1979 .name = "gcc_pcie_1_slv_q2a_axi_clk", 1980 .ops = &clk_branch2_ops, 1981 }, 1982 }, 1983 }; 1984 1985 static struct clk_branch gcc_pcie_phy_aux_clk = { 1986 .halt_reg = 0x6f004, 1987 .halt_check = BRANCH_HALT, 1988 .clkr = { 1989 .enable_reg = 0x6f004, 1990 .enable_mask = BIT(0), 1991 .hw.init = &(struct clk_init_data){ 1992 .name = "gcc_pcie_phy_aux_clk", 1993 .parent_hws = (const struct clk_hw *[]){ 1994 &gcc_pcie_0_aux_clk_src.clkr.hw }, 1995 .num_parents = 1, 1996 .flags = CLK_SET_RATE_PARENT, 1997 .ops = &clk_branch2_ops, 1998 }, 1999 }, 2000 }; 2001 2002 static struct clk_branch gcc_pdm2_clk = { 2003 .halt_reg = 0x3300c, 2004 .halt_check = BRANCH_HALT, 2005 .clkr = { 2006 .enable_reg = 0x3300c, 2007 .enable_mask = BIT(0), 2008 .hw.init = &(struct clk_init_data){ 2009 .name = "gcc_pdm2_clk", 2010 .parent_hws = (const struct clk_hw *[]){ 2011 &gcc_pdm2_clk_src.clkr.hw }, 2012 .num_parents = 1, 2013 .flags = CLK_SET_RATE_PARENT, 2014 .ops = &clk_branch2_ops, 2015 }, 2016 }, 2017 }; 2018 2019 static struct clk_branch gcc_pdm_ahb_clk = { 2020 .halt_reg = 0x33004, 2021 .halt_check = BRANCH_HALT, 2022 .hwcg_reg = 0x33004, 2023 .hwcg_bit = 1, 2024 .clkr = { 2025 .enable_reg = 0x33004, 2026 .enable_mask = BIT(0), 2027 .hw.init = &(struct clk_init_data){ 2028 .name = "gcc_pdm_ahb_clk", 2029 .ops = &clk_branch2_ops, 2030 }, 2031 }, 2032 }; 2033 2034 static struct clk_branch gcc_pdm_xo4_clk = { 2035 .halt_reg = 0x33008, 2036 .halt_check = BRANCH_HALT, 2037 .clkr = { 2038 .enable_reg = 0x33008, 2039 .enable_mask = BIT(0), 2040 .hw.init = &(struct clk_init_data){ 2041 .name = "gcc_pdm_xo4_clk", 2042 .ops = &clk_branch2_ops, 2043 }, 2044 }, 2045 }; 2046 2047 static struct clk_branch gcc_prng_ahb_clk = { 2048 .halt_reg = 0x34004, 2049 .halt_check = BRANCH_HALT_VOTED, 2050 .clkr = { 2051 .enable_reg = 0x52004, 2052 .enable_mask = BIT(13), 2053 .hw.init = &(struct clk_init_data){ 2054 .name = "gcc_prng_ahb_clk", 2055 .ops = &clk_branch2_ops, 2056 }, 2057 }, 2058 }; 2059 2060 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2061 .halt_reg = 0xb018, 2062 .halt_check = BRANCH_HALT, 2063 .hwcg_reg = 0xb018, 2064 .hwcg_bit = 1, 2065 .clkr = { 2066 .enable_reg = 0xb018, 2067 .enable_mask = BIT(0), 2068 .hw.init = &(struct clk_init_data){ 2069 .name = "gcc_qmip_camera_nrt_ahb_clk", 2070 .ops = &clk_branch2_ops, 2071 }, 2072 }, 2073 }; 2074 2075 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2076 .halt_reg = 0xb01c, 2077 .halt_check = BRANCH_HALT, 2078 .hwcg_reg = 0xb01c, 2079 .hwcg_bit = 1, 2080 .clkr = { 2081 .enable_reg = 0xb01c, 2082 .enable_mask = BIT(0), 2083 .hw.init = &(struct clk_init_data){ 2084 .name = "gcc_qmip_camera_rt_ahb_clk", 2085 .ops = &clk_branch2_ops, 2086 }, 2087 }, 2088 }; 2089 2090 static struct clk_branch gcc_qmip_disp_ahb_clk = { 2091 .halt_reg = 0xb020, 2092 .halt_check = BRANCH_HALT, 2093 .hwcg_reg = 0xb020, 2094 .hwcg_bit = 1, 2095 .clkr = { 2096 .enable_reg = 0xb020, 2097 .enable_mask = BIT(0), 2098 .hw.init = &(struct clk_init_data){ 2099 .name = "gcc_qmip_disp_ahb_clk", 2100 .ops = &clk_branch2_ops, 2101 }, 2102 }, 2103 }; 2104 2105 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 2106 .halt_reg = 0xb010, 2107 .halt_check = BRANCH_HALT, 2108 .hwcg_reg = 0xb010, 2109 .hwcg_bit = 1, 2110 .clkr = { 2111 .enable_reg = 0xb010, 2112 .enable_mask = BIT(0), 2113 .hw.init = &(struct clk_init_data){ 2114 .name = "gcc_qmip_video_cvp_ahb_clk", 2115 .ops = &clk_branch2_ops, 2116 }, 2117 }, 2118 }; 2119 2120 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2121 .halt_reg = 0xb014, 2122 .halt_check = BRANCH_HALT, 2123 .hwcg_reg = 0xb014, 2124 .hwcg_bit = 1, 2125 .clkr = { 2126 .enable_reg = 0xb014, 2127 .enable_mask = BIT(0), 2128 .hw.init = &(struct clk_init_data){ 2129 .name = "gcc_qmip_video_vcodec_ahb_clk", 2130 .ops = &clk_branch2_ops, 2131 }, 2132 }, 2133 }; 2134 2135 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { 2136 .halt_reg = 0x4b000, 2137 .halt_check = BRANCH_HALT, 2138 .clkr = { 2139 .enable_reg = 0x4b000, 2140 .enable_mask = BIT(0), 2141 .hw.init = &(struct clk_init_data){ 2142 .name = "gcc_qspi_cnoc_periph_ahb_clk", 2143 .ops = &clk_branch2_ops, 2144 }, 2145 }, 2146 }; 2147 2148 static struct clk_branch gcc_qspi_core_clk = { 2149 .halt_reg = 0x4b004, 2150 .halt_check = BRANCH_HALT, 2151 .clkr = { 2152 .enable_reg = 0x4b004, 2153 .enable_mask = BIT(0), 2154 .hw.init = &(struct clk_init_data){ 2155 .name = "gcc_qspi_core_clk", 2156 .parent_hws = (const struct clk_hw *[]){ 2157 &gcc_qspi_core_clk_src.clkr.hw }, 2158 .num_parents = 1, 2159 .flags = CLK_SET_RATE_PARENT, 2160 .ops = &clk_branch2_ops, 2161 }, 2162 }, 2163 }; 2164 2165 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2166 .halt_reg = 0x17144, 2167 .halt_check = BRANCH_HALT_VOTED, 2168 .clkr = { 2169 .enable_reg = 0x5200c, 2170 .enable_mask = BIT(10), 2171 .hw.init = &(struct clk_init_data){ 2172 .name = "gcc_qupv3_wrap0_s0_clk", 2173 .parent_hws = (const struct clk_hw *[]){ 2174 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw }, 2175 .num_parents = 1, 2176 .flags = CLK_SET_RATE_PARENT, 2177 .ops = &clk_branch2_ops, 2178 }, 2179 }, 2180 }; 2181 2182 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2183 .halt_reg = 0x17274, 2184 .halt_check = BRANCH_HALT_VOTED, 2185 .clkr = { 2186 .enable_reg = 0x5200c, 2187 .enable_mask = BIT(11), 2188 .hw.init = &(struct clk_init_data){ 2189 .name = "gcc_qupv3_wrap0_s1_clk", 2190 .parent_hws = (const struct clk_hw *[]){ 2191 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw }, 2192 .num_parents = 1, 2193 .flags = CLK_SET_RATE_PARENT, 2194 .ops = &clk_branch2_ops, 2195 }, 2196 }, 2197 }; 2198 2199 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2200 .halt_reg = 0x173a4, 2201 .halt_check = BRANCH_HALT_VOTED, 2202 .clkr = { 2203 .enable_reg = 0x5200c, 2204 .enable_mask = BIT(12), 2205 .hw.init = &(struct clk_init_data){ 2206 .name = "gcc_qupv3_wrap0_s2_clk", 2207 .parent_hws = (const struct clk_hw *[]){ 2208 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw }, 2209 .num_parents = 1, 2210 .flags = CLK_SET_RATE_PARENT, 2211 .ops = &clk_branch2_ops, 2212 }, 2213 }, 2214 }; 2215 2216 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2217 .halt_reg = 0x174d4, 2218 .halt_check = BRANCH_HALT_VOTED, 2219 .clkr = { 2220 .enable_reg = 0x5200c, 2221 .enable_mask = BIT(13), 2222 .hw.init = &(struct clk_init_data){ 2223 .name = "gcc_qupv3_wrap0_s3_clk", 2224 .parent_hws = (const struct clk_hw *[]){ 2225 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw }, 2226 .num_parents = 1, 2227 .flags = CLK_SET_RATE_PARENT, 2228 .ops = &clk_branch2_ops, 2229 }, 2230 }, 2231 }; 2232 2233 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2234 .halt_reg = 0x17604, 2235 .halt_check = BRANCH_HALT_VOTED, 2236 .clkr = { 2237 .enable_reg = 0x5200c, 2238 .enable_mask = BIT(14), 2239 .hw.init = &(struct clk_init_data){ 2240 .name = "gcc_qupv3_wrap0_s4_clk", 2241 .parent_hws = (const struct clk_hw *[]){ 2242 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw }, 2243 .num_parents = 1, 2244 .flags = CLK_SET_RATE_PARENT, 2245 .ops = &clk_branch2_ops, 2246 }, 2247 }, 2248 }; 2249 2250 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2251 .halt_reg = 0x17734, 2252 .halt_check = BRANCH_HALT_VOTED, 2253 .clkr = { 2254 .enable_reg = 0x5200c, 2255 .enable_mask = BIT(15), 2256 .hw.init = &(struct clk_init_data){ 2257 .name = "gcc_qupv3_wrap0_s5_clk", 2258 .parent_hws = (const struct clk_hw *[]){ 2259 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw }, 2260 .num_parents = 1, 2261 .flags = CLK_SET_RATE_PARENT, 2262 .ops = &clk_branch2_ops, 2263 }, 2264 }, 2265 }; 2266 2267 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 2268 .halt_reg = 0x17864, 2269 .halt_check = BRANCH_HALT_VOTED, 2270 .clkr = { 2271 .enable_reg = 0x5200c, 2272 .enable_mask = BIT(16), 2273 .hw.init = &(struct clk_init_data){ 2274 .name = "gcc_qupv3_wrap0_s6_clk", 2275 .parent_hws = (const struct clk_hw *[]){ 2276 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw }, 2277 .num_parents = 1, 2278 .flags = CLK_SET_RATE_PARENT, 2279 .ops = &clk_branch2_ops, 2280 }, 2281 }, 2282 }; 2283 2284 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 2285 .halt_reg = 0x17994, 2286 .halt_check = BRANCH_HALT_VOTED, 2287 .clkr = { 2288 .enable_reg = 0x5200c, 2289 .enable_mask = BIT(17), 2290 .hw.init = &(struct clk_init_data){ 2291 .name = "gcc_qupv3_wrap0_s7_clk", 2292 .parent_hws = (const struct clk_hw *[]){ 2293 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw }, 2294 .num_parents = 1, 2295 .flags = CLK_SET_RATE_PARENT, 2296 .ops = &clk_branch2_ops, 2297 }, 2298 }, 2299 }; 2300 2301 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2302 .halt_reg = 0x18144, 2303 .halt_check = BRANCH_HALT_VOTED, 2304 .clkr = { 2305 .enable_reg = 0x5200c, 2306 .enable_mask = BIT(22), 2307 .hw.init = &(struct clk_init_data){ 2308 .name = "gcc_qupv3_wrap1_s0_clk", 2309 .parent_hws = (const struct clk_hw *[]){ 2310 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw }, 2311 .num_parents = 1, 2312 .flags = CLK_SET_RATE_PARENT, 2313 .ops = &clk_branch2_ops, 2314 }, 2315 }, 2316 }; 2317 2318 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2319 .halt_reg = 0x18274, 2320 .halt_check = BRANCH_HALT_VOTED, 2321 .clkr = { 2322 .enable_reg = 0x5200c, 2323 .enable_mask = BIT(23), 2324 .hw.init = &(struct clk_init_data){ 2325 .name = "gcc_qupv3_wrap1_s1_clk", 2326 .parent_hws = (const struct clk_hw *[]){ 2327 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw }, 2328 .num_parents = 1, 2329 .flags = CLK_SET_RATE_PARENT, 2330 .ops = &clk_branch2_ops, 2331 }, 2332 }, 2333 }; 2334 2335 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2336 .halt_reg = 0x183a4, 2337 .halt_check = BRANCH_HALT_VOTED, 2338 .clkr = { 2339 .enable_reg = 0x5200c, 2340 .enable_mask = BIT(24), 2341 .hw.init = &(struct clk_init_data){ 2342 .name = "gcc_qupv3_wrap1_s2_clk", 2343 .parent_hws = (const struct clk_hw *[]){ 2344 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw }, 2345 .num_parents = 1, 2346 .flags = CLK_SET_RATE_PARENT, 2347 .ops = &clk_branch2_ops, 2348 }, 2349 }, 2350 }; 2351 2352 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2353 .halt_reg = 0x184d4, 2354 .halt_check = BRANCH_HALT_VOTED, 2355 .clkr = { 2356 .enable_reg = 0x5200c, 2357 .enable_mask = BIT(25), 2358 .hw.init = &(struct clk_init_data){ 2359 .name = "gcc_qupv3_wrap1_s3_clk", 2360 .parent_hws = (const struct clk_hw *[]){ 2361 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw }, 2362 .num_parents = 1, 2363 .flags = CLK_SET_RATE_PARENT, 2364 .ops = &clk_branch2_ops, 2365 }, 2366 }, 2367 }; 2368 2369 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2370 .halt_reg = 0x18604, 2371 .halt_check = BRANCH_HALT_VOTED, 2372 .clkr = { 2373 .enable_reg = 0x5200c, 2374 .enable_mask = BIT(26), 2375 .hw.init = &(struct clk_init_data){ 2376 .name = "gcc_qupv3_wrap1_s4_clk", 2377 .parent_hws = (const struct clk_hw *[]){ 2378 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw }, 2379 .num_parents = 1, 2380 .flags = CLK_SET_RATE_PARENT, 2381 .ops = &clk_branch2_ops, 2382 }, 2383 }, 2384 }; 2385 2386 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2387 .halt_reg = 0x18734, 2388 .halt_check = BRANCH_HALT_VOTED, 2389 .clkr = { 2390 .enable_reg = 0x5200c, 2391 .enable_mask = BIT(27), 2392 .hw.init = &(struct clk_init_data){ 2393 .name = "gcc_qupv3_wrap1_s5_clk", 2394 .parent_hws = (const struct clk_hw *[]){ 2395 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw }, 2396 .num_parents = 1, 2397 .flags = CLK_SET_RATE_PARENT, 2398 .ops = &clk_branch2_ops, 2399 }, 2400 }, 2401 }; 2402 2403 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 2404 .halt_reg = 0x1e144, 2405 .halt_check = BRANCH_HALT_VOTED, 2406 .clkr = { 2407 .enable_reg = 0x52014, 2408 .enable_mask = BIT(4), 2409 .hw.init = &(struct clk_init_data){ 2410 .name = "gcc_qupv3_wrap2_s0_clk", 2411 .parent_hws = (const struct clk_hw *[]){ 2412 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw }, 2413 .num_parents = 1, 2414 .flags = CLK_SET_RATE_PARENT, 2415 .ops = &clk_branch2_ops, 2416 }, 2417 }, 2418 }; 2419 2420 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 2421 .halt_reg = 0x1e274, 2422 .halt_check = BRANCH_HALT_VOTED, 2423 .clkr = { 2424 .enable_reg = 0x52014, 2425 .enable_mask = BIT(5), 2426 .hw.init = &(struct clk_init_data){ 2427 .name = "gcc_qupv3_wrap2_s1_clk", 2428 .parent_hws = (const struct clk_hw *[]){ 2429 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw }, 2430 .num_parents = 1, 2431 .flags = CLK_SET_RATE_PARENT, 2432 .ops = &clk_branch2_ops, 2433 }, 2434 }, 2435 }; 2436 2437 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 2438 .halt_reg = 0x1e3a4, 2439 .halt_check = BRANCH_HALT_VOTED, 2440 .clkr = { 2441 .enable_reg = 0x52014, 2442 .enable_mask = BIT(6), 2443 .hw.init = &(struct clk_init_data){ 2444 .name = "gcc_qupv3_wrap2_s2_clk", 2445 .parent_hws = (const struct clk_hw *[]){ 2446 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw }, 2447 .num_parents = 1, 2448 .flags = CLK_SET_RATE_PARENT, 2449 .ops = &clk_branch2_ops, 2450 }, 2451 }, 2452 }; 2453 2454 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 2455 .halt_reg = 0x1e4d4, 2456 .halt_check = BRANCH_HALT_VOTED, 2457 .clkr = { 2458 .enable_reg = 0x52014, 2459 .enable_mask = BIT(7), 2460 .hw.init = &(struct clk_init_data){ 2461 .name = "gcc_qupv3_wrap2_s3_clk", 2462 .parent_hws = (const struct clk_hw *[]){ 2463 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw }, 2464 .num_parents = 1, 2465 .flags = CLK_SET_RATE_PARENT, 2466 .ops = &clk_branch2_ops, 2467 }, 2468 }, 2469 }; 2470 2471 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 2472 .halt_reg = 0x1e604, 2473 .halt_check = BRANCH_HALT_VOTED, 2474 .clkr = { 2475 .enable_reg = 0x52014, 2476 .enable_mask = BIT(8), 2477 .hw.init = &(struct clk_init_data){ 2478 .name = "gcc_qupv3_wrap2_s4_clk", 2479 .parent_hws = (const struct clk_hw *[]){ 2480 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw }, 2481 .num_parents = 1, 2482 .flags = CLK_SET_RATE_PARENT, 2483 .ops = &clk_branch2_ops, 2484 }, 2485 }, 2486 }; 2487 2488 static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 2489 .halt_reg = 0x1e734, 2490 .halt_check = BRANCH_HALT_VOTED, 2491 .clkr = { 2492 .enable_reg = 0x52014, 2493 .enable_mask = BIT(9), 2494 .hw.init = &(struct clk_init_data){ 2495 .name = "gcc_qupv3_wrap2_s5_clk", 2496 .parent_hws = (const struct clk_hw *[]){ 2497 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw }, 2498 .num_parents = 1, 2499 .flags = CLK_SET_RATE_PARENT, 2500 .ops = &clk_branch2_ops, 2501 }, 2502 }, 2503 }; 2504 2505 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2506 .halt_reg = 0x17004, 2507 .halt_check = BRANCH_HALT_VOTED, 2508 .clkr = { 2509 .enable_reg = 0x5200c, 2510 .enable_mask = BIT(6), 2511 .hw.init = &(struct clk_init_data){ 2512 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2513 .ops = &clk_branch2_ops, 2514 }, 2515 }, 2516 }; 2517 2518 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2519 .halt_reg = 0x17008, 2520 .halt_check = BRANCH_HALT_VOTED, 2521 .hwcg_reg = 0x17008, 2522 .hwcg_bit = 1, 2523 .clkr = { 2524 .enable_reg = 0x5200c, 2525 .enable_mask = BIT(7), 2526 .hw.init = &(struct clk_init_data){ 2527 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2528 .ops = &clk_branch2_ops, 2529 }, 2530 }, 2531 }; 2532 2533 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2534 .halt_reg = 0x18004, 2535 .halt_check = BRANCH_HALT_VOTED, 2536 .clkr = { 2537 .enable_reg = 0x5200c, 2538 .enable_mask = BIT(20), 2539 .hw.init = &(struct clk_init_data){ 2540 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2541 .ops = &clk_branch2_ops, 2542 }, 2543 }, 2544 }; 2545 2546 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2547 .halt_reg = 0x18008, 2548 .halt_check = BRANCH_HALT_VOTED, 2549 .hwcg_reg = 0x18008, 2550 .hwcg_bit = 1, 2551 .clkr = { 2552 .enable_reg = 0x5200c, 2553 .enable_mask = BIT(21), 2554 .hw.init = &(struct clk_init_data){ 2555 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2556 .ops = &clk_branch2_ops, 2557 }, 2558 }, 2559 }; 2560 2561 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 2562 .halt_reg = 0x1e004, 2563 .halt_check = BRANCH_HALT_VOTED, 2564 .clkr = { 2565 .enable_reg = 0x52014, 2566 .enable_mask = BIT(2), 2567 .hw.init = &(struct clk_init_data){ 2568 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 2569 .ops = &clk_branch2_ops, 2570 }, 2571 }, 2572 }; 2573 2574 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 2575 .halt_reg = 0x1e008, 2576 .halt_check = BRANCH_HALT_VOTED, 2577 .hwcg_reg = 0x1e008, 2578 .hwcg_bit = 1, 2579 .clkr = { 2580 .enable_reg = 0x52014, 2581 .enable_mask = BIT(1), 2582 .hw.init = &(struct clk_init_data){ 2583 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 2584 .ops = &clk_branch2_ops, 2585 }, 2586 }, 2587 }; 2588 2589 static struct clk_branch gcc_sdcc2_ahb_clk = { 2590 .halt_reg = 0x14008, 2591 .halt_check = BRANCH_HALT, 2592 .clkr = { 2593 .enable_reg = 0x14008, 2594 .enable_mask = BIT(0), 2595 .hw.init = &(struct clk_init_data){ 2596 .name = "gcc_sdcc2_ahb_clk", 2597 .ops = &clk_branch2_ops, 2598 }, 2599 }, 2600 }; 2601 2602 static struct clk_branch gcc_sdcc2_apps_clk = { 2603 .halt_reg = 0x14004, 2604 .halt_check = BRANCH_HALT, 2605 .clkr = { 2606 .enable_reg = 0x14004, 2607 .enable_mask = BIT(0), 2608 .hw.init = &(struct clk_init_data){ 2609 .name = "gcc_sdcc2_apps_clk", 2610 .parent_hws = (const struct clk_hw *[]){ 2611 &gcc_sdcc2_apps_clk_src.clkr.hw }, 2612 .num_parents = 1, 2613 .flags = CLK_SET_RATE_PARENT, 2614 .ops = &clk_branch2_ops, 2615 }, 2616 }, 2617 }; 2618 2619 static struct clk_branch gcc_sdcc4_ahb_clk = { 2620 .halt_reg = 0x16008, 2621 .halt_check = BRANCH_HALT, 2622 .clkr = { 2623 .enable_reg = 0x16008, 2624 .enable_mask = BIT(0), 2625 .hw.init = &(struct clk_init_data){ 2626 .name = "gcc_sdcc4_ahb_clk", 2627 .ops = &clk_branch2_ops, 2628 }, 2629 }, 2630 }; 2631 2632 static struct clk_branch gcc_sdcc4_apps_clk = { 2633 .halt_reg = 0x16004, 2634 .halt_check = BRANCH_HALT, 2635 .clkr = { 2636 .enable_reg = 0x16004, 2637 .enable_mask = BIT(0), 2638 .hw.init = &(struct clk_init_data){ 2639 .name = "gcc_sdcc4_apps_clk", 2640 .parent_hws = (const struct clk_hw *[]){ 2641 &gcc_sdcc4_apps_clk_src.clkr.hw }, 2642 .num_parents = 1, 2643 .flags = CLK_SET_RATE_PARENT, 2644 .ops = &clk_branch2_ops, 2645 }, 2646 }, 2647 }; 2648 2649 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 2650 .halt_reg = 0x4819c, 2651 .halt_check = BRANCH_HALT_VOTED, 2652 .clkr = { 2653 .enable_reg = 0x52004, 2654 .enable_mask = BIT(0), 2655 .hw.init = &(struct clk_init_data){ 2656 .name = "gcc_sys_noc_cpuss_ahb_clk", 2657 .parent_hws = (const struct clk_hw *[]){ 2658 &gcc_cpuss_ahb_clk_src.clkr.hw }, 2659 .num_parents = 1, 2660 /* required for cpuss */ 2661 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 2662 .ops = &clk_branch2_ops, 2663 }, 2664 }, 2665 }; 2666 2667 static struct clk_branch gcc_tsif_ahb_clk = { 2668 .halt_reg = 0x36004, 2669 .halt_check = BRANCH_HALT, 2670 .clkr = { 2671 .enable_reg = 0x36004, 2672 .enable_mask = BIT(0), 2673 .hw.init = &(struct clk_init_data){ 2674 .name = "gcc_tsif_ahb_clk", 2675 .ops = &clk_branch2_ops, 2676 }, 2677 }, 2678 }; 2679 2680 static struct clk_branch gcc_tsif_inactivity_timers_clk = { 2681 .halt_reg = 0x3600c, 2682 .halt_check = BRANCH_HALT, 2683 .clkr = { 2684 .enable_reg = 0x3600c, 2685 .enable_mask = BIT(0), 2686 .hw.init = &(struct clk_init_data){ 2687 .name = "gcc_tsif_inactivity_timers_clk", 2688 .ops = &clk_branch2_ops, 2689 }, 2690 }, 2691 }; 2692 2693 static struct clk_branch gcc_tsif_ref_clk = { 2694 .halt_reg = 0x36008, 2695 .halt_check = BRANCH_HALT, 2696 .clkr = { 2697 .enable_reg = 0x36008, 2698 .enable_mask = BIT(0), 2699 .hw.init = &(struct clk_init_data){ 2700 .name = "gcc_tsif_ref_clk", 2701 .parent_hws = (const struct clk_hw *[]){ 2702 &gcc_tsif_ref_clk_src.clkr.hw }, 2703 .num_parents = 1, 2704 .flags = CLK_SET_RATE_PARENT, 2705 .ops = &clk_branch2_ops, 2706 }, 2707 }, 2708 }; 2709 2710 static struct clk_branch gcc_ufs_card_ahb_clk = { 2711 .halt_reg = 0x75014, 2712 .halt_check = BRANCH_HALT, 2713 .hwcg_reg = 0x75014, 2714 .hwcg_bit = 1, 2715 .clkr = { 2716 .enable_reg = 0x75014, 2717 .enable_mask = BIT(0), 2718 .hw.init = &(struct clk_init_data){ 2719 .name = "gcc_ufs_card_ahb_clk", 2720 .ops = &clk_branch2_ops, 2721 }, 2722 }, 2723 }; 2724 2725 static struct clk_branch gcc_ufs_card_axi_clk = { 2726 .halt_reg = 0x75010, 2727 .halt_check = BRANCH_HALT, 2728 .hwcg_reg = 0x75010, 2729 .hwcg_bit = 1, 2730 .clkr = { 2731 .enable_reg = 0x75010, 2732 .enable_mask = BIT(0), 2733 .hw.init = &(struct clk_init_data){ 2734 .name = "gcc_ufs_card_axi_clk", 2735 .parent_hws = (const struct clk_hw *[]){ 2736 &gcc_ufs_card_axi_clk_src.clkr.hw }, 2737 .num_parents = 1, 2738 .flags = CLK_SET_RATE_PARENT, 2739 .ops = &clk_branch2_ops, 2740 }, 2741 }, 2742 }; 2743 2744 static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = { 2745 .halt_reg = 0x75010, 2746 .halt_check = BRANCH_HALT, 2747 .hwcg_reg = 0x75010, 2748 .hwcg_bit = 1, 2749 .clkr = { 2750 .enable_reg = 0x75010, 2751 .enable_mask = BIT(1), 2752 .hw.init = &(struct clk_init_data){ 2753 .name = "gcc_ufs_card_axi_hw_ctl_clk", 2754 .parent_hws = (const struct clk_hw *[]){ 2755 &gcc_ufs_card_axi_clk.clkr.hw }, 2756 .num_parents = 1, 2757 .flags = CLK_SET_RATE_PARENT, 2758 .ops = &clk_branch_simple_ops, 2759 }, 2760 }, 2761 }; 2762 2763 static struct clk_branch gcc_ufs_card_clkref_clk = { 2764 .halt_reg = 0x8c004, 2765 .halt_check = BRANCH_HALT, 2766 .clkr = { 2767 .enable_reg = 0x8c004, 2768 .enable_mask = BIT(0), 2769 .hw.init = &(struct clk_init_data){ 2770 .name = "gcc_ufs_card_clkref_clk", 2771 .ops = &clk_branch2_ops, 2772 }, 2773 }, 2774 }; 2775 2776 static struct clk_branch gcc_ufs_card_ice_core_clk = { 2777 .halt_reg = 0x7505c, 2778 .halt_check = BRANCH_HALT, 2779 .hwcg_reg = 0x7505c, 2780 .hwcg_bit = 1, 2781 .clkr = { 2782 .enable_reg = 0x7505c, 2783 .enable_mask = BIT(0), 2784 .hw.init = &(struct clk_init_data){ 2785 .name = "gcc_ufs_card_ice_core_clk", 2786 .parent_hws = (const struct clk_hw *[]){ 2787 &gcc_ufs_card_ice_core_clk_src.clkr.hw }, 2788 .num_parents = 1, 2789 .flags = CLK_SET_RATE_PARENT, 2790 .ops = &clk_branch2_ops, 2791 }, 2792 }, 2793 }; 2794 2795 static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = { 2796 .halt_reg = 0x7505c, 2797 .halt_check = BRANCH_HALT, 2798 .hwcg_reg = 0x7505c, 2799 .hwcg_bit = 1, 2800 .clkr = { 2801 .enable_reg = 0x7505c, 2802 .enable_mask = BIT(1), 2803 .hw.init = &(struct clk_init_data){ 2804 .name = "gcc_ufs_card_ice_core_hw_ctl_clk", 2805 .parent_hws = (const struct clk_hw *[]){ 2806 &gcc_ufs_card_ice_core_clk.clkr.hw }, 2807 .num_parents = 1, 2808 .flags = CLK_SET_RATE_PARENT, 2809 .ops = &clk_branch_simple_ops, 2810 }, 2811 }, 2812 }; 2813 2814 static struct clk_branch gcc_ufs_card_phy_aux_clk = { 2815 .halt_reg = 0x75090, 2816 .halt_check = BRANCH_HALT, 2817 .hwcg_reg = 0x75090, 2818 .hwcg_bit = 1, 2819 .clkr = { 2820 .enable_reg = 0x75090, 2821 .enable_mask = BIT(0), 2822 .hw.init = &(struct clk_init_data){ 2823 .name = "gcc_ufs_card_phy_aux_clk", 2824 .parent_hws = (const struct clk_hw *[]){ 2825 &gcc_ufs_card_phy_aux_clk_src.clkr.hw }, 2826 .num_parents = 1, 2827 .flags = CLK_SET_RATE_PARENT, 2828 .ops = &clk_branch2_ops, 2829 }, 2830 }, 2831 }; 2832 2833 static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { 2834 .halt_reg = 0x75090, 2835 .halt_check = BRANCH_HALT, 2836 .hwcg_reg = 0x75090, 2837 .hwcg_bit = 1, 2838 .clkr = { 2839 .enable_reg = 0x75090, 2840 .enable_mask = BIT(1), 2841 .hw.init = &(struct clk_init_data){ 2842 .name = "gcc_ufs_card_phy_aux_hw_ctl_clk", 2843 .parent_hws = (const struct clk_hw *[]){ 2844 &gcc_ufs_card_phy_aux_clk.clkr.hw }, 2845 .num_parents = 1, 2846 .flags = CLK_SET_RATE_PARENT, 2847 .ops = &clk_branch_simple_ops, 2848 }, 2849 }, 2850 }; 2851 2852 /* external clocks so add BRANCH_HALT_SKIP */ 2853 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { 2854 .halt_check = BRANCH_HALT_SKIP, 2855 .clkr = { 2856 .enable_reg = 0x7501c, 2857 .enable_mask = BIT(0), 2858 .hw.init = &(struct clk_init_data){ 2859 .name = "gcc_ufs_card_rx_symbol_0_clk", 2860 .ops = &clk_branch2_ops, 2861 }, 2862 }, 2863 }; 2864 2865 /* external clocks so add BRANCH_HALT_SKIP */ 2866 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { 2867 .halt_check = BRANCH_HALT_SKIP, 2868 .clkr = { 2869 .enable_reg = 0x750ac, 2870 .enable_mask = BIT(0), 2871 .hw.init = &(struct clk_init_data){ 2872 .name = "gcc_ufs_card_rx_symbol_1_clk", 2873 .ops = &clk_branch2_ops, 2874 }, 2875 }, 2876 }; 2877 2878 /* external clocks so add BRANCH_HALT_SKIP */ 2879 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { 2880 .halt_check = BRANCH_HALT_SKIP, 2881 .clkr = { 2882 .enable_reg = 0x75018, 2883 .enable_mask = BIT(0), 2884 .hw.init = &(struct clk_init_data){ 2885 .name = "gcc_ufs_card_tx_symbol_0_clk", 2886 .ops = &clk_branch2_ops, 2887 }, 2888 }, 2889 }; 2890 2891 static struct clk_branch gcc_ufs_card_unipro_core_clk = { 2892 .halt_reg = 0x75058, 2893 .halt_check = BRANCH_HALT, 2894 .hwcg_reg = 0x75058, 2895 .hwcg_bit = 1, 2896 .clkr = { 2897 .enable_reg = 0x75058, 2898 .enable_mask = BIT(0), 2899 .hw.init = &(struct clk_init_data){ 2900 .name = "gcc_ufs_card_unipro_core_clk", 2901 .parent_hws = (const struct clk_hw *[]){ 2902 &gcc_ufs_card_unipro_core_clk_src.clkr.hw }, 2903 .num_parents = 1, 2904 .flags = CLK_SET_RATE_PARENT, 2905 .ops = &clk_branch2_ops, 2906 }, 2907 }, 2908 }; 2909 2910 static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { 2911 .halt_reg = 0x75058, 2912 .halt_check = BRANCH_HALT, 2913 .hwcg_reg = 0x75058, 2914 .hwcg_bit = 1, 2915 .clkr = { 2916 .enable_reg = 0x75058, 2917 .enable_mask = BIT(1), 2918 .hw.init = &(struct clk_init_data){ 2919 .name = "gcc_ufs_card_unipro_core_hw_ctl_clk", 2920 .parent_hws = (const struct clk_hw *[]){ 2921 &gcc_ufs_card_unipro_core_clk.clkr.hw }, 2922 .num_parents = 1, 2923 .flags = CLK_SET_RATE_PARENT, 2924 .ops = &clk_branch_simple_ops, 2925 }, 2926 }, 2927 }; 2928 2929 static struct clk_branch gcc_ufs_mem_clkref_clk = { 2930 .halt_reg = 0x8c000, 2931 .halt_check = BRANCH_HALT, 2932 .clkr = { 2933 .enable_reg = 0x8c000, 2934 .enable_mask = BIT(0), 2935 .hw.init = &(struct clk_init_data){ 2936 .name = "gcc_ufs_mem_clkref_clk", 2937 .ops = &clk_branch2_ops, 2938 }, 2939 }, 2940 }; 2941 2942 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2943 .halt_reg = 0x77014, 2944 .halt_check = BRANCH_HALT, 2945 .hwcg_reg = 0x77014, 2946 .hwcg_bit = 1, 2947 .clkr = { 2948 .enable_reg = 0x77014, 2949 .enable_mask = BIT(0), 2950 .hw.init = &(struct clk_init_data){ 2951 .name = "gcc_ufs_phy_ahb_clk", 2952 .ops = &clk_branch2_ops, 2953 }, 2954 }, 2955 }; 2956 2957 static struct clk_branch gcc_ufs_phy_axi_clk = { 2958 .halt_reg = 0x77010, 2959 .halt_check = BRANCH_HALT, 2960 .hwcg_reg = 0x77010, 2961 .hwcg_bit = 1, 2962 .clkr = { 2963 .enable_reg = 0x77010, 2964 .enable_mask = BIT(0), 2965 .hw.init = &(struct clk_init_data){ 2966 .name = "gcc_ufs_phy_axi_clk", 2967 .parent_hws = (const struct clk_hw *[]){ 2968 &gcc_ufs_phy_axi_clk_src.clkr.hw }, 2969 .num_parents = 1, 2970 .flags = CLK_SET_RATE_PARENT, 2971 .ops = &clk_branch2_ops, 2972 }, 2973 }, 2974 }; 2975 2976 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { 2977 .halt_reg = 0x77010, 2978 .halt_check = BRANCH_HALT, 2979 .hwcg_reg = 0x77010, 2980 .hwcg_bit = 1, 2981 .clkr = { 2982 .enable_reg = 0x77010, 2983 .enable_mask = BIT(1), 2984 .hw.init = &(struct clk_init_data){ 2985 .name = "gcc_ufs_phy_axi_hw_ctl_clk", 2986 .parent_hws = (const struct clk_hw *[]){ 2987 &gcc_ufs_phy_axi_clk.clkr.hw }, 2988 .num_parents = 1, 2989 .flags = CLK_SET_RATE_PARENT, 2990 .ops = &clk_branch_simple_ops, 2991 }, 2992 }, 2993 }; 2994 2995 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2996 .halt_reg = 0x7705c, 2997 .halt_check = BRANCH_HALT, 2998 .hwcg_reg = 0x7705c, 2999 .hwcg_bit = 1, 3000 .clkr = { 3001 .enable_reg = 0x7705c, 3002 .enable_mask = BIT(0), 3003 .hw.init = &(struct clk_init_data){ 3004 .name = "gcc_ufs_phy_ice_core_clk", 3005 .parent_hws = (const struct clk_hw *[]){ 3006 &gcc_ufs_phy_ice_core_clk_src.clkr.hw }, 3007 .num_parents = 1, 3008 .flags = CLK_SET_RATE_PARENT, 3009 .ops = &clk_branch2_ops, 3010 }, 3011 }, 3012 }; 3013 3014 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { 3015 .halt_reg = 0x7705c, 3016 .halt_check = BRANCH_HALT, 3017 .hwcg_reg = 0x7705c, 3018 .hwcg_bit = 1, 3019 .clkr = { 3020 .enable_reg = 0x7705c, 3021 .enable_mask = BIT(1), 3022 .hw.init = &(struct clk_init_data){ 3023 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", 3024 .parent_hws = (const struct clk_hw *[]){ 3025 &gcc_ufs_phy_ice_core_clk.clkr.hw }, 3026 .num_parents = 1, 3027 .flags = CLK_SET_RATE_PARENT, 3028 .ops = &clk_branch_simple_ops, 3029 }, 3030 }, 3031 }; 3032 3033 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 3034 .halt_reg = 0x77090, 3035 .halt_check = BRANCH_HALT, 3036 .hwcg_reg = 0x77090, 3037 .hwcg_bit = 1, 3038 .clkr = { 3039 .enable_reg = 0x77090, 3040 .enable_mask = BIT(0), 3041 .hw.init = &(struct clk_init_data){ 3042 .name = "gcc_ufs_phy_phy_aux_clk", 3043 .parent_hws = (const struct clk_hw *[]){ 3044 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw }, 3045 .num_parents = 1, 3046 .flags = CLK_SET_RATE_PARENT, 3047 .ops = &clk_branch2_ops, 3048 }, 3049 }, 3050 }; 3051 3052 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { 3053 .halt_reg = 0x77090, 3054 .halt_check = BRANCH_HALT, 3055 .hwcg_reg = 0x77090, 3056 .hwcg_bit = 1, 3057 .clkr = { 3058 .enable_reg = 0x77090, 3059 .enable_mask = BIT(1), 3060 .hw.init = &(struct clk_init_data){ 3061 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", 3062 .parent_hws = (const struct clk_hw *[]){ 3063 &gcc_ufs_phy_phy_aux_clk.clkr.hw }, 3064 .num_parents = 1, 3065 .flags = CLK_SET_RATE_PARENT, 3066 .ops = &clk_branch_simple_ops, 3067 }, 3068 }, 3069 }; 3070 3071 /* external clocks so add BRANCH_HALT_SKIP */ 3072 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 3073 .halt_check = BRANCH_HALT_SKIP, 3074 .clkr = { 3075 .enable_reg = 0x7701c, 3076 .enable_mask = BIT(0), 3077 .hw.init = &(struct clk_init_data){ 3078 .name = "gcc_ufs_phy_rx_symbol_0_clk", 3079 .ops = &clk_branch2_ops, 3080 }, 3081 }, 3082 }; 3083 3084 /* external clocks so add BRANCH_HALT_SKIP */ 3085 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 3086 .halt_check = BRANCH_HALT_SKIP, 3087 .clkr = { 3088 .enable_reg = 0x770ac, 3089 .enable_mask = BIT(0), 3090 .hw.init = &(struct clk_init_data){ 3091 .name = "gcc_ufs_phy_rx_symbol_1_clk", 3092 .ops = &clk_branch2_ops, 3093 }, 3094 }, 3095 }; 3096 3097 /* external clocks so add BRANCH_HALT_SKIP */ 3098 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 3099 .halt_check = BRANCH_HALT_SKIP, 3100 .clkr = { 3101 .enable_reg = 0x77018, 3102 .enable_mask = BIT(0), 3103 .hw.init = &(struct clk_init_data){ 3104 .name = "gcc_ufs_phy_tx_symbol_0_clk", 3105 .ops = &clk_branch2_ops, 3106 }, 3107 }, 3108 }; 3109 3110 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 3111 .halt_reg = 0x77058, 3112 .halt_check = BRANCH_HALT, 3113 .hwcg_reg = 0x77058, 3114 .hwcg_bit = 1, 3115 .clkr = { 3116 .enable_reg = 0x77058, 3117 .enable_mask = BIT(0), 3118 .hw.init = &(struct clk_init_data){ 3119 .name = "gcc_ufs_phy_unipro_core_clk", 3120 .parent_hws = (const struct clk_hw *[]){ 3121 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw }, 3122 .num_parents = 1, 3123 .flags = CLK_SET_RATE_PARENT, 3124 .ops = &clk_branch2_ops, 3125 }, 3126 }, 3127 }; 3128 3129 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { 3130 .halt_reg = 0x77058, 3131 .halt_check = BRANCH_HALT, 3132 .hwcg_reg = 0x77058, 3133 .hwcg_bit = 1, 3134 .clkr = { 3135 .enable_reg = 0x77058, 3136 .enable_mask = BIT(1), 3137 .hw.init = &(struct clk_init_data){ 3138 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", 3139 .parent_hws = (const struct clk_hw *[]){ 3140 &gcc_ufs_phy_unipro_core_clk.clkr.hw }, 3141 .num_parents = 1, 3142 .flags = CLK_SET_RATE_PARENT, 3143 .ops = &clk_branch_simple_ops, 3144 }, 3145 }, 3146 }; 3147 3148 static struct clk_branch gcc_usb30_prim_master_clk = { 3149 .halt_reg = 0xf010, 3150 .halt_check = BRANCH_HALT, 3151 .clkr = { 3152 .enable_reg = 0xf010, 3153 .enable_mask = BIT(0), 3154 .hw.init = &(struct clk_init_data){ 3155 .name = "gcc_usb30_prim_master_clk", 3156 .parent_hws = (const struct clk_hw *[]){ 3157 &gcc_usb30_prim_master_clk_src.clkr.hw }, 3158 .num_parents = 1, 3159 .flags = CLK_SET_RATE_PARENT, 3160 .ops = &clk_branch2_ops, 3161 }, 3162 }, 3163 }; 3164 3165 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 3166 .halt_reg = 0xf018, 3167 .halt_check = BRANCH_HALT, 3168 .clkr = { 3169 .enable_reg = 0xf018, 3170 .enable_mask = BIT(0), 3171 .hw.init = &(struct clk_init_data){ 3172 .name = "gcc_usb30_prim_mock_utmi_clk", 3173 .parent_hws = (const struct clk_hw *[]){ 3174 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw }, 3175 .num_parents = 1, 3176 .flags = CLK_SET_RATE_PARENT, 3177 .ops = &clk_branch2_ops, 3178 }, 3179 }, 3180 }; 3181 3182 static struct clk_branch gcc_usb30_prim_sleep_clk = { 3183 .halt_reg = 0xf014, 3184 .halt_check = BRANCH_HALT, 3185 .clkr = { 3186 .enable_reg = 0xf014, 3187 .enable_mask = BIT(0), 3188 .hw.init = &(struct clk_init_data){ 3189 .name = "gcc_usb30_prim_sleep_clk", 3190 .ops = &clk_branch2_ops, 3191 }, 3192 }, 3193 }; 3194 3195 static struct clk_branch gcc_usb30_sec_master_clk = { 3196 .halt_reg = 0x10010, 3197 .halt_check = BRANCH_HALT, 3198 .clkr = { 3199 .enable_reg = 0x10010, 3200 .enable_mask = BIT(0), 3201 .hw.init = &(struct clk_init_data){ 3202 .name = "gcc_usb30_sec_master_clk", 3203 .parent_hws = (const struct clk_hw *[]){ 3204 &gcc_usb30_sec_master_clk_src.clkr.hw }, 3205 .num_parents = 1, 3206 .flags = CLK_SET_RATE_PARENT, 3207 .ops = &clk_branch2_ops, 3208 }, 3209 }, 3210 }; 3211 3212 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { 3213 .halt_reg = 0x10018, 3214 .halt_check = BRANCH_HALT, 3215 .clkr = { 3216 .enable_reg = 0x10018, 3217 .enable_mask = BIT(0), 3218 .hw.init = &(struct clk_init_data){ 3219 .name = "gcc_usb30_sec_mock_utmi_clk", 3220 .parent_hws = (const struct clk_hw *[]){ 3221 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw }, 3222 .num_parents = 1, 3223 .flags = CLK_SET_RATE_PARENT, 3224 .ops = &clk_branch2_ops, 3225 }, 3226 }, 3227 }; 3228 3229 static struct clk_branch gcc_usb30_sec_sleep_clk = { 3230 .halt_reg = 0x10014, 3231 .halt_check = BRANCH_HALT, 3232 .clkr = { 3233 .enable_reg = 0x10014, 3234 .enable_mask = BIT(0), 3235 .hw.init = &(struct clk_init_data){ 3236 .name = "gcc_usb30_sec_sleep_clk", 3237 .ops = &clk_branch2_ops, 3238 }, 3239 }, 3240 }; 3241 3242 static struct clk_branch gcc_usb3_prim_clkref_clk = { 3243 .halt_reg = 0x8c008, 3244 .halt_check = BRANCH_HALT, 3245 .clkr = { 3246 .enable_reg = 0x8c008, 3247 .enable_mask = BIT(0), 3248 .hw.init = &(struct clk_init_data){ 3249 .name = "gcc_usb3_prim_clkref_clk", 3250 .ops = &clk_branch2_ops, 3251 }, 3252 }, 3253 }; 3254 3255 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 3256 .halt_reg = 0xf050, 3257 .halt_check = BRANCH_HALT, 3258 .clkr = { 3259 .enable_reg = 0xf050, 3260 .enable_mask = BIT(0), 3261 .hw.init = &(struct clk_init_data){ 3262 .name = "gcc_usb3_prim_phy_aux_clk", 3263 .parent_hws = (const struct clk_hw *[]){ 3264 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw }, 3265 .num_parents = 1, 3266 .flags = CLK_SET_RATE_PARENT, 3267 .ops = &clk_branch2_ops, 3268 }, 3269 }, 3270 }; 3271 3272 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3273 .halt_reg = 0xf054, 3274 .halt_check = BRANCH_HALT, 3275 .clkr = { 3276 .enable_reg = 0xf054, 3277 .enable_mask = BIT(0), 3278 .hw.init = &(struct clk_init_data){ 3279 .name = "gcc_usb3_prim_phy_com_aux_clk", 3280 .parent_hws = (const struct clk_hw *[]){ 3281 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw }, 3282 .num_parents = 1, 3283 .flags = CLK_SET_RATE_PARENT, 3284 .ops = &clk_branch2_ops, 3285 }, 3286 }, 3287 }; 3288 3289 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3290 .halt_check = BRANCH_HALT_SKIP, 3291 .clkr = { 3292 .enable_reg = 0xf058, 3293 .enable_mask = BIT(0), 3294 .hw.init = &(struct clk_init_data){ 3295 .name = "gcc_usb3_prim_phy_pipe_clk", 3296 .ops = &clk_branch2_ops, 3297 }, 3298 }, 3299 }; 3300 3301 static struct clk_branch gcc_usb3_sec_clkref_clk = { 3302 .halt_reg = 0x8c028, 3303 .halt_check = BRANCH_HALT, 3304 .clkr = { 3305 .enable_reg = 0x8c028, 3306 .enable_mask = BIT(0), 3307 .hw.init = &(struct clk_init_data){ 3308 .name = "gcc_usb3_sec_clkref_clk", 3309 .ops = &clk_branch2_ops, 3310 }, 3311 }, 3312 }; 3313 3314 static struct clk_branch gcc_usb3_sec_phy_aux_clk = { 3315 .halt_reg = 0x10050, 3316 .halt_check = BRANCH_HALT, 3317 .clkr = { 3318 .enable_reg = 0x10050, 3319 .enable_mask = BIT(0), 3320 .hw.init = &(struct clk_init_data){ 3321 .name = "gcc_usb3_sec_phy_aux_clk", 3322 .parent_hws = (const struct clk_hw *[]){ 3323 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw }, 3324 .num_parents = 1, 3325 .flags = CLK_SET_RATE_PARENT, 3326 .ops = &clk_branch2_ops, 3327 }, 3328 }, 3329 }; 3330 3331 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { 3332 .halt_reg = 0x10054, 3333 .halt_check = BRANCH_HALT, 3334 .clkr = { 3335 .enable_reg = 0x10054, 3336 .enable_mask = BIT(0), 3337 .hw.init = &(struct clk_init_data){ 3338 .name = "gcc_usb3_sec_phy_com_aux_clk", 3339 .parent_hws = (const struct clk_hw *[]){ 3340 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw }, 3341 .num_parents = 1, 3342 .flags = CLK_SET_RATE_PARENT, 3343 .ops = &clk_branch2_ops, 3344 }, 3345 }, 3346 }; 3347 3348 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { 3349 .halt_check = BRANCH_HALT_SKIP, 3350 .clkr = { 3351 .enable_reg = 0x10058, 3352 .enable_mask = BIT(0), 3353 .hw.init = &(struct clk_init_data){ 3354 .name = "gcc_usb3_sec_phy_pipe_clk", 3355 .ops = &clk_branch2_ops, 3356 }, 3357 }, 3358 }; 3359 3360 /* 3361 * Clock ON depends on external parent 'config noc', so cant poll 3362 * delay and also mark as crtitical for video boot 3363 */ 3364 static struct clk_branch gcc_video_ahb_clk = { 3365 .halt_reg = 0xb004, 3366 .halt_check = BRANCH_HALT_DELAY, 3367 .hwcg_reg = 0xb004, 3368 .hwcg_bit = 1, 3369 .clkr = { 3370 .enable_reg = 0xb004, 3371 .enable_mask = BIT(0), 3372 .hw.init = &(struct clk_init_data){ 3373 .name = "gcc_video_ahb_clk", 3374 .flags = CLK_IS_CRITICAL, 3375 .ops = &clk_branch2_ops, 3376 }, 3377 }, 3378 }; 3379 3380 static struct clk_branch gcc_video_axi0_clk = { 3381 .halt_reg = 0xb024, 3382 .halt_check = BRANCH_HALT, 3383 .clkr = { 3384 .enable_reg = 0xb024, 3385 .enable_mask = BIT(0), 3386 .hw.init = &(struct clk_init_data){ 3387 .name = "gcc_video_axi0_clk", 3388 .ops = &clk_branch2_ops, 3389 }, 3390 }, 3391 }; 3392 3393 static struct clk_branch gcc_video_axi1_clk = { 3394 .halt_reg = 0xb028, 3395 .halt_check = BRANCH_HALT, 3396 .clkr = { 3397 .enable_reg = 0xb028, 3398 .enable_mask = BIT(0), 3399 .hw.init = &(struct clk_init_data){ 3400 .name = "gcc_video_axi1_clk", 3401 .ops = &clk_branch2_ops, 3402 }, 3403 }, 3404 }; 3405 3406 static struct clk_branch gcc_video_axic_clk = { 3407 .halt_reg = 0xb02c, 3408 .halt_check = BRANCH_HALT, 3409 .clkr = { 3410 .enable_reg = 0xb02c, 3411 .enable_mask = BIT(0), 3412 .hw.init = &(struct clk_init_data){ 3413 .name = "gcc_video_axic_clk", 3414 .ops = &clk_branch2_ops, 3415 }, 3416 }, 3417 }; 3418 3419 /* XO critical input to video, so no need to poll */ 3420 static struct clk_branch gcc_video_xo_clk = { 3421 .halt_reg = 0xb040, 3422 .halt_check = BRANCH_HALT_DELAY, 3423 .clkr = { 3424 .enable_reg = 0xb040, 3425 .enable_mask = BIT(0), 3426 .hw.init = &(struct clk_init_data){ 3427 .name = "gcc_video_xo_clk", 3428 .flags = CLK_IS_CRITICAL, 3429 .ops = &clk_branch2_ops, 3430 }, 3431 }, 3432 }; 3433 3434 static struct gdsc pcie_0_gdsc = { 3435 .gdscr = 0x6b004, 3436 .pd = { 3437 .name = "pcie_0_gdsc", 3438 }, 3439 .pwrsts = PWRSTS_OFF_ON, 3440 .flags = POLL_CFG_GDSCR, 3441 }; 3442 3443 static struct gdsc pcie_1_gdsc = { 3444 .gdscr = 0x8d004, 3445 .pd = { 3446 .name = "pcie_1_gdsc", 3447 }, 3448 .pwrsts = PWRSTS_OFF_ON, 3449 .flags = POLL_CFG_GDSCR, 3450 }; 3451 3452 static struct gdsc ufs_card_gdsc = { 3453 .gdscr = 0x75004, 3454 .pd = { 3455 .name = "ufs_card_gdsc", 3456 }, 3457 .pwrsts = PWRSTS_OFF_ON, 3458 .flags = POLL_CFG_GDSCR, 3459 }; 3460 3461 static struct gdsc ufs_phy_gdsc = { 3462 .gdscr = 0x77004, 3463 .pd = { 3464 .name = "ufs_phy_gdsc", 3465 }, 3466 .pwrsts = PWRSTS_OFF_ON, 3467 .flags = POLL_CFG_GDSCR, 3468 }; 3469 3470 static struct gdsc emac_gdsc = { 3471 .gdscr = 0x6004, 3472 .pd = { 3473 .name = "emac_gdsc", 3474 }, 3475 .pwrsts = PWRSTS_OFF_ON, 3476 .flags = POLL_CFG_GDSCR, 3477 }; 3478 3479 static struct gdsc usb30_prim_gdsc = { 3480 .gdscr = 0xf004, 3481 .pd = { 3482 .name = "usb30_prim_gdsc", 3483 }, 3484 .pwrsts = PWRSTS_OFF_ON, 3485 .flags = POLL_CFG_GDSCR, 3486 }; 3487 3488 static struct gdsc usb30_sec_gdsc = { 3489 .gdscr = 0x10004, 3490 .pd = { 3491 .name = "usb30_sec_gdsc", 3492 }, 3493 .pwrsts = PWRSTS_OFF_ON, 3494 .flags = POLL_CFG_GDSCR, 3495 }; 3496 3497 static struct clk_regmap *gcc_sm8150_clocks[] = { 3498 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, 3499 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, 3500 [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = 3501 &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr, 3502 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 3503 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = 3504 &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, 3505 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 3506 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, 3507 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3508 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 3509 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 3510 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 3511 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 3512 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3513 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, 3514 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, 3515 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, 3516 [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr, 3517 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, 3518 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, 3519 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 3520 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, 3521 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3522 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, 3523 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 3524 [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr, 3525 [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr, 3526 [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr, 3527 [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr, 3528 [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr, 3529 [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr, 3530 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3531 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3532 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3533 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3534 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3535 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3536 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 3537 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3538 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3539 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, 3540 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3541 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3542 [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr, 3543 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, 3544 [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr, 3545 [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr, 3546 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr, 3547 [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr, 3548 [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr, 3549 [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr, 3550 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3551 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 3552 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3553 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr, 3554 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3555 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3556 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3557 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 3558 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 3559 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 3560 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 3561 [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr, 3562 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 3563 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 3564 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 3565 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 3566 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, 3567 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, 3568 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3569 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3570 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3571 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3572 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3573 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3574 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3575 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3576 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 3577 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3578 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, 3579 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, 3580 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, 3581 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3582 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3583 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3584 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3585 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3586 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3587 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3588 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3589 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3590 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3591 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3592 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3593 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 3594 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 3595 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 3596 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 3597 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3598 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3599 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3600 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3601 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3602 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3603 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3604 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3605 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3606 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3607 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3608 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3609 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 3610 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 3611 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 3612 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 3613 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 3614 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 3615 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 3616 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 3617 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 3618 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 3619 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 3620 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 3621 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3622 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3623 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3624 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3625 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 3626 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 3627 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3628 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3629 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3630 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3631 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3632 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 3633 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 3634 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 3635 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, 3636 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 3637 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, 3638 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, 3639 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, 3640 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, 3641 [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr, 3642 [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr, 3643 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, 3644 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, 3645 [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = 3646 &gcc_ufs_card_ice_core_hw_ctl_clk.clkr, 3647 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, 3648 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, 3649 [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = 3650 &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr, 3651 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, 3652 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, 3653 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, 3654 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, 3655 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = 3656 &gcc_ufs_card_unipro_core_clk_src.clkr, 3657 [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = 3658 &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr, 3659 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, 3660 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3661 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3662 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3663 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, 3664 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3665 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3666 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = 3667 &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, 3668 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3669 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3670 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, 3671 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3672 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3673 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3674 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3675 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 3676 &gcc_ufs_phy_unipro_core_clk_src.clkr, 3677 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = 3678 &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, 3679 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3680 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3681 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3682 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 3683 &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3684 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3685 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, 3686 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, 3687 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, 3688 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = 3689 &gcc_usb30_sec_mock_utmi_clk_src.clkr, 3690 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, 3691 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 3692 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3693 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3694 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3695 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3696 [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr, 3697 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, 3698 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, 3699 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, 3700 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, 3701 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 3702 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3703 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 3704 [GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr, 3705 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 3706 [GPLL0] = &gpll0.clkr, 3707 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 3708 [GPLL7] = &gpll7.clkr, 3709 [GPLL9] = &gpll9.clkr, 3710 }; 3711 3712 static const struct qcom_reset_map gcc_sm8150_resets[] = { 3713 [GCC_EMAC_BCR] = { 0x6000 }, 3714 [GCC_GPU_BCR] = { 0x71000 }, 3715 [GCC_MMSS_BCR] = { 0xb000 }, 3716 [GCC_NPU_BCR] = { 0x4d000 }, 3717 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3718 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3719 [GCC_PCIE_1_BCR] = { 0x8d000 }, 3720 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 3721 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 3722 [GCC_PDM_BCR] = { 0x33000 }, 3723 [GCC_PRNG_BCR] = { 0x34000 }, 3724 [GCC_QSPI_BCR] = { 0x24008 }, 3725 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, 3726 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 3727 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, 3728 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3729 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3730 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 3731 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 3732 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 3733 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3734 [GCC_SDCC2_BCR] = { 0x14000 }, 3735 [GCC_SDCC4_BCR] = { 0x16000 }, 3736 [GCC_TSIF_BCR] = { 0x36000 }, 3737 [GCC_UFS_CARD_BCR] = { 0x75000 }, 3738 [GCC_UFS_PHY_BCR] = { 0x77000 }, 3739 [GCC_USB30_PRIM_BCR] = { 0xf000 }, 3740 [GCC_USB30_SEC_BCR] = { 0x10000 }, 3741 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 3742 }; 3743 3744 static struct gdsc *gcc_sm8150_gdscs[] = { 3745 [EMAC_GDSC] = &emac_gdsc, 3746 [PCIE_0_GDSC] = &pcie_0_gdsc, 3747 [PCIE_1_GDSC] = &pcie_1_gdsc, 3748 [UFS_CARD_GDSC] = &ufs_card_gdsc, 3749 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3750 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3751 [USB30_SEC_GDSC] = &usb30_sec_gdsc, 3752 }; 3753 3754 static const struct regmap_config gcc_sm8150_regmap_config = { 3755 .reg_bits = 32, 3756 .reg_stride = 4, 3757 .val_bits = 32, 3758 .max_register = 0x9c040, 3759 .fast_io = true, 3760 }; 3761 3762 static const struct qcom_cc_desc gcc_sm8150_desc = { 3763 .config = &gcc_sm8150_regmap_config, 3764 .clks = gcc_sm8150_clocks, 3765 .num_clks = ARRAY_SIZE(gcc_sm8150_clocks), 3766 .resets = gcc_sm8150_resets, 3767 .num_resets = ARRAY_SIZE(gcc_sm8150_resets), 3768 .gdscs = gcc_sm8150_gdscs, 3769 .num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs), 3770 }; 3771 3772 static const struct of_device_id gcc_sm8150_match_table[] = { 3773 { .compatible = "qcom,gcc-sm8150" }, 3774 { } 3775 }; 3776 MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table); 3777 3778 static int gcc_sm8150_probe(struct platform_device *pdev) 3779 { 3780 struct regmap *regmap; 3781 3782 regmap = qcom_cc_map(pdev, &gcc_sm8150_desc); 3783 if (IS_ERR(regmap)) 3784 return PTR_ERR(regmap); 3785 3786 /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ 3787 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); 3788 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 3789 3790 return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap); 3791 } 3792 3793 static struct platform_driver gcc_sm8150_driver = { 3794 .probe = gcc_sm8150_probe, 3795 .driver = { 3796 .name = "gcc-sm8150", 3797 .of_match_table = gcc_sm8150_match_table, 3798 }, 3799 }; 3800 3801 static int __init gcc_sm8150_init(void) 3802 { 3803 return platform_driver_register(&gcc_sm8150_driver); 3804 } 3805 subsys_initcall(gcc_sm8150_init); 3806 3807 static void __exit gcc_sm8150_exit(void) 3808 { 3809 platform_driver_unregister(&gcc_sm8150_driver); 3810 } 3811 module_exit(gcc_sm8150_exit); 3812 3813 MODULE_DESCRIPTION("QTI GCC SM8150 Driver"); 3814 MODULE_LICENSE("GPL v2"); 3815