1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/module.h> 9 #include <linux/of_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,sm6375-gcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "clk-regmap-divider.h" 19 #include "clk-regmap-mux.h" 20 #include "clk-regmap-phy-mux.h" 21 #include "gdsc.h" 22 #include "reset.h" 23 24 enum { 25 DT_BI_TCXO, 26 DT_BI_TCXO_AO, 27 DT_SLEEP_CLK 28 }; 29 30 enum { 31 P_BI_TCXO, 32 P_GPLL0_OUT_EVEN, 33 P_GPLL0_OUT_MAIN, 34 P_GPLL0_OUT_ODD, 35 P_GPLL10_OUT_EVEN, 36 P_GPLL11_OUT_EVEN, 37 P_GPLL11_OUT_ODD, 38 P_GPLL3_OUT_EVEN, 39 P_GPLL3_OUT_MAIN, 40 P_GPLL4_OUT_EVEN, 41 P_GPLL5_OUT_EVEN, 42 P_GPLL6_OUT_EVEN, 43 P_GPLL6_OUT_MAIN, 44 P_GPLL7_OUT_EVEN, 45 P_GPLL8_OUT_EVEN, 46 P_GPLL8_OUT_MAIN, 47 P_GPLL9_OUT_EARLY, 48 P_GPLL9_OUT_MAIN, 49 P_SLEEP_CLK, 50 }; 51 52 static struct pll_vco lucid_vco[] = { 53 { 249600000, 2000000000, 0 }, 54 }; 55 56 static struct pll_vco zonda_vco[] = { 57 { 595200000, 3600000000, 0 }, 58 }; 59 60 static struct clk_alpha_pll gpll0 = { 61 .offset = 0x0, 62 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 63 .clkr = { 64 .enable_reg = 0x79000, 65 .enable_mask = BIT(0), 66 .hw.init = &(struct clk_init_data){ 67 .name = "gpll0", 68 .parent_data = &(const struct clk_parent_data){ 69 .index = DT_BI_TCXO, 70 }, 71 .num_parents = 1, 72 .ops = &clk_alpha_pll_fixed_lucid_ops, 73 }, 74 }, 75 }; 76 77 static const struct clk_div_table post_div_table_gpll0_out_even[] = { 78 { 0x1, 2 }, 79 { } 80 }; 81 82 static struct clk_alpha_pll_postdiv gpll0_out_even = { 83 .offset = 0x0, 84 .post_div_shift = 8, 85 .post_div_table = post_div_table_gpll0_out_even, 86 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even), 87 .width = 4, 88 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 89 .clkr.hw.init = &(struct clk_init_data){ 90 .name = "gpll0_out_even", 91 .parent_hws = (const struct clk_hw*[]){ 92 &gpll0.clkr.hw, 93 }, 94 .num_parents = 1, 95 .ops = &clk_alpha_pll_postdiv_lucid_ops, 96 }, 97 }; 98 99 static const struct clk_div_table post_div_table_gpll0_out_odd[] = { 100 { 0x3, 3 }, 101 { } 102 }; 103 104 static struct clk_alpha_pll_postdiv gpll0_out_odd = { 105 .offset = 0x0, 106 .post_div_shift = 12, 107 .post_div_table = post_div_table_gpll0_out_odd, 108 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_odd), 109 .width = 4, 110 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 111 .clkr.hw.init = &(struct clk_init_data){ 112 .name = "gpll0_out_odd", 113 .parent_hws = (const struct clk_hw*[]){ 114 &gpll0.clkr.hw, 115 }, 116 .num_parents = 1, 117 .ops = &clk_alpha_pll_postdiv_lucid_ops, 118 }, 119 }; 120 121 static struct clk_alpha_pll gpll1 = { 122 .offset = 0x1000, 123 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 124 .clkr = { 125 .enable_reg = 0x79000, 126 .enable_mask = BIT(1), 127 .hw.init = &(struct clk_init_data){ 128 .name = "gpll1", 129 .parent_data = &(const struct clk_parent_data){ 130 .index = DT_BI_TCXO, 131 }, 132 .num_parents = 1, 133 .ops = &clk_alpha_pll_lucid_ops, 134 }, 135 }, 136 }; 137 138 /* 1152MHz Configuration */ 139 static const struct alpha_pll_config gpll10_config = { 140 .l = 0x3c, 141 .alpha = 0x0, 142 .config_ctl_val = 0x20485699, 143 .config_ctl_hi_val = 0x00002261, 144 .config_ctl_hi1_val = 0x329a299c, 145 .user_ctl_val = 0x00000001, 146 .user_ctl_hi_val = 0x00000805, 147 .user_ctl_hi1_val = 0x00000000, 148 }; 149 150 static struct clk_alpha_pll gpll10 = { 151 .offset = 0xa000, 152 .vco_table = lucid_vco, 153 .num_vco = ARRAY_SIZE(lucid_vco), 154 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 155 .flags = SUPPORTS_FSM_LEGACY_MODE, 156 .clkr = { 157 .enable_reg = 0x79000, 158 .enable_mask = BIT(10), 159 .hw.init = &(struct clk_init_data){ 160 .name = "gpll10", 161 .parent_data = &(const struct clk_parent_data){ 162 .index = DT_BI_TCXO, 163 }, 164 .num_parents = 1, 165 .ops = &clk_alpha_pll_fixed_lucid_ops, 166 }, 167 }, 168 }; 169 170 /* 532MHz Configuration */ 171 static const struct alpha_pll_config gpll11_config = { 172 .l = 0x1b, 173 .alpha = 0xb555, 174 .config_ctl_val = 0x20485699, 175 .config_ctl_hi_val = 0x00002261, 176 .config_ctl_hi1_val = 0x329a299c, 177 .user_ctl_val = 0x00000001, 178 .user_ctl_hi_val = 0x00000805, 179 .user_ctl_hi1_val = 0x00000000, 180 }; 181 182 static struct clk_alpha_pll gpll11 = { 183 .offset = 0xb000, 184 .vco_table = lucid_vco, 185 .num_vco = ARRAY_SIZE(lucid_vco), 186 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 187 .flags = SUPPORTS_FSM_LEGACY_MODE, 188 .clkr = { 189 .enable_reg = 0x79000, 190 .enable_mask = BIT(11), 191 .hw.init = &(struct clk_init_data){ 192 .name = "gpll11", 193 .parent_data = &(const struct clk_parent_data){ 194 .index = DT_BI_TCXO, 195 }, 196 .num_parents = 1, 197 .ops = &clk_alpha_pll_lucid_ops, 198 }, 199 }, 200 }; 201 202 static struct clk_alpha_pll gpll3 = { 203 .offset = 0x3000, 204 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 205 .clkr = { 206 .enable_reg = 0x79000, 207 .enable_mask = BIT(3), 208 .hw.init = &(struct clk_init_data){ 209 .name = "gpll3", 210 .parent_data = &(const struct clk_parent_data){ 211 .index = DT_BI_TCXO, 212 }, 213 .num_parents = 1, 214 .ops = &clk_alpha_pll_fixed_lucid_ops, 215 }, 216 }, 217 }; 218 219 static const struct clk_div_table post_div_table_gpll3_out_even[] = { 220 { 0x1, 2 }, 221 { } 222 }; 223 224 static struct clk_alpha_pll_postdiv gpll3_out_even = { 225 .offset = 0x3000, 226 .post_div_shift = 8, 227 .post_div_table = post_div_table_gpll3_out_even, 228 .num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_even), 229 .width = 4, 230 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 231 .clkr.hw.init = &(struct clk_init_data){ 232 .name = "gpll3_out_even", 233 .parent_hws = (const struct clk_hw*[]){ 234 &gpll3.clkr.hw, 235 }, 236 .num_parents = 1, 237 .ops = &clk_alpha_pll_postdiv_lucid_ops, 238 }, 239 }; 240 241 static struct clk_alpha_pll gpll4 = { 242 .offset = 0x4000, 243 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 244 .clkr = { 245 .enable_reg = 0x79000, 246 .enable_mask = BIT(4), 247 .hw.init = &(struct clk_init_data){ 248 .name = "gpll4", 249 .parent_data = &(const struct clk_parent_data){ 250 .index = DT_BI_TCXO, 251 }, 252 .num_parents = 1, 253 .ops = &clk_alpha_pll_fixed_lucid_ops, 254 }, 255 }, 256 }; 257 258 static struct clk_alpha_pll gpll5 = { 259 .offset = 0x5000, 260 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 261 .clkr = { 262 .enable_reg = 0x79000, 263 .enable_mask = BIT(5), 264 .hw.init = &(struct clk_init_data){ 265 .name = "gpll5", 266 .parent_data = &(const struct clk_parent_data){ 267 .index = DT_BI_TCXO, 268 }, 269 .num_parents = 1, 270 .ops = &clk_alpha_pll_fixed_lucid_ops, 271 }, 272 }, 273 }; 274 275 static struct clk_alpha_pll gpll6 = { 276 .offset = 0x6000, 277 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 278 .clkr = { 279 .enable_reg = 0x79000, 280 .enable_mask = BIT(6), 281 .hw.init = &(struct clk_init_data){ 282 .name = "gpll6", 283 .parent_data = &(const struct clk_parent_data){ 284 .index = DT_BI_TCXO, 285 }, 286 .num_parents = 1, 287 .ops = &clk_alpha_pll_fixed_lucid_ops, 288 }, 289 }, 290 }; 291 292 static const struct clk_div_table post_div_table_gpll6_out_even[] = { 293 { 0x1, 2 }, 294 { } 295 }; 296 297 static struct clk_alpha_pll_postdiv gpll6_out_even = { 298 .offset = 0x6000, 299 .post_div_shift = 8, 300 .post_div_table = post_div_table_gpll6_out_even, 301 .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_even), 302 .width = 4, 303 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 304 .clkr.hw.init = &(struct clk_init_data){ 305 .name = "gpll6_out_even", 306 .parent_hws = (const struct clk_hw*[]){ 307 &gpll6.clkr.hw, 308 }, 309 .num_parents = 1, 310 .ops = &clk_alpha_pll_postdiv_lucid_ops, 311 }, 312 }; 313 314 static struct clk_alpha_pll gpll7 = { 315 .offset = 0x7000, 316 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 317 .clkr = { 318 .enable_reg = 0x79000, 319 .enable_mask = BIT(7), 320 .hw.init = &(struct clk_init_data){ 321 .name = "gpll7", 322 .parent_data = &(const struct clk_parent_data){ 323 .index = DT_BI_TCXO, 324 }, 325 .num_parents = 1, 326 .ops = &clk_alpha_pll_fixed_lucid_ops, 327 }, 328 }, 329 }; 330 331 /* 400MHz Configuration */ 332 static const struct alpha_pll_config gpll8_config = { 333 .l = 0x14, 334 .alpha = 0xd555, 335 .config_ctl_val = 0x20485699, 336 .config_ctl_hi_val = 0x00002261, 337 .config_ctl_hi1_val = 0x329a299c, 338 .user_ctl_val = 0x00000101, 339 .user_ctl_hi_val = 0x00000805, 340 .user_ctl_hi1_val = 0x00000000, 341 }; 342 343 static struct clk_alpha_pll gpll8 = { 344 .offset = 0x8000, 345 .vco_table = lucid_vco, 346 .num_vco = ARRAY_SIZE(lucid_vco), 347 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 348 .flags = SUPPORTS_FSM_LEGACY_MODE, 349 .clkr = { 350 .enable_reg = 0x79000, 351 .enable_mask = BIT(8), 352 .hw.init = &(struct clk_init_data){ 353 .name = "gpll8", 354 .parent_data = &(const struct clk_parent_data){ 355 .index = DT_BI_TCXO, 356 }, 357 .num_parents = 1, 358 .ops = &clk_alpha_pll_lucid_ops, 359 }, 360 }, 361 }; 362 363 static const struct clk_div_table post_div_table_gpll8_out_even[] = { 364 { 0x1, 2 }, 365 { } 366 }; 367 368 static struct clk_alpha_pll_postdiv gpll8_out_even = { 369 .offset = 0x8000, 370 .post_div_shift = 8, 371 .post_div_table = post_div_table_gpll8_out_even, 372 .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_even), 373 .width = 4, 374 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 375 .clkr.hw.init = &(struct clk_init_data){ 376 .name = "gpll8_out_even", 377 .parent_hws = (const struct clk_hw*[]){ 378 &gpll8.clkr.hw, 379 }, 380 .num_parents = 1, 381 .flags = CLK_SET_RATE_PARENT, 382 .ops = &clk_alpha_pll_postdiv_lucid_ops, 383 }, 384 }; 385 386 /* 1440MHz Configuration */ 387 static const struct alpha_pll_config gpll9_config = { 388 .l = 0x4b, 389 .alpha = 0x0, 390 .config_ctl_val = 0x08200800, 391 .config_ctl_hi_val = 0x05022011, 392 .config_ctl_hi1_val = 0x08000000, 393 .user_ctl_val = 0x00000301, 394 }; 395 396 static struct clk_alpha_pll gpll9 = { 397 .offset = 0x9000, 398 .vco_table = zonda_vco, 399 .num_vco = ARRAY_SIZE(zonda_vco), 400 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], 401 .clkr = { 402 .enable_reg = 0x79000, 403 .enable_mask = BIT(9), 404 .hw.init = &(struct clk_init_data){ 405 .name = "gpll9", 406 .parent_data = &(const struct clk_parent_data){ 407 .index = DT_BI_TCXO, 408 }, 409 .num_parents = 1, 410 .ops = &clk_alpha_pll_zonda_ops, 411 }, 412 }, 413 }; 414 415 static const struct clk_div_table post_div_table_gpll9_out_main[] = { 416 { 0x3, 4 }, 417 { } 418 }; 419 420 static struct clk_alpha_pll_postdiv gpll9_out_main = { 421 .offset = 0x9000, 422 .post_div_shift = 8, 423 .post_div_table = post_div_table_gpll9_out_main, 424 .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main), 425 .width = 2, 426 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], 427 .clkr.hw.init = &(struct clk_init_data){ 428 .name = "gpll9_out_main", 429 .parent_hws = (const struct clk_hw*[]){ 430 &gpll9.clkr.hw, 431 }, 432 .num_parents = 1, 433 .flags = CLK_SET_RATE_PARENT, 434 .ops = &clk_alpha_pll_postdiv_zonda_ops, 435 }, 436 }; 437 438 static const struct parent_map gcc_parent_map_0[] = { 439 { P_BI_TCXO, 0 }, 440 { P_GPLL0_OUT_MAIN, 1 }, 441 { P_GPLL0_OUT_EVEN, 2 }, 442 }; 443 444 static const struct clk_parent_data gcc_parent_data_0[] = { 445 { .index = DT_BI_TCXO }, 446 { .hw = &gpll0.clkr.hw }, 447 { .hw = &gpll0_out_even.clkr.hw }, 448 }; 449 450 static const struct parent_map gcc_parent_map_1[] = { 451 { P_BI_TCXO, 0 }, 452 { P_GPLL0_OUT_MAIN, 1 }, 453 { P_GPLL0_OUT_EVEN, 2 }, 454 { P_GPLL6_OUT_EVEN, 4 }, 455 }; 456 457 static const struct clk_parent_data gcc_parent_data_1[] = { 458 { .index = DT_BI_TCXO }, 459 { .hw = &gpll0.clkr.hw }, 460 { .hw = &gpll0_out_even.clkr.hw }, 461 { .hw = &gpll6_out_even.clkr.hw }, 462 }; 463 464 static const struct parent_map gcc_parent_map_2[] = { 465 { P_BI_TCXO, 0 }, 466 { P_GPLL0_OUT_MAIN, 1 }, 467 { P_GPLL0_OUT_EVEN, 2 }, 468 { P_GPLL0_OUT_ODD, 4 }, 469 }; 470 471 static const struct clk_parent_data gcc_parent_data_2[] = { 472 { .index = DT_BI_TCXO }, 473 { .hw = &gpll0.clkr.hw }, 474 { .hw = &gpll0_out_even.clkr.hw }, 475 { .hw = &gpll0_out_odd.clkr.hw }, 476 }; 477 478 static const struct clk_parent_data gcc_parent_data_2_ao[] = { 479 { .index = DT_BI_TCXO_AO }, 480 { .hw = &gpll0.clkr.hw }, 481 { .hw = &gpll0_out_even.clkr.hw }, 482 { .hw = &gpll0_out_odd.clkr.hw }, 483 }; 484 485 static const struct parent_map gcc_parent_map_3[] = { 486 { P_BI_TCXO, 0 }, 487 { P_GPLL0_OUT_MAIN, 1 }, 488 { P_GPLL9_OUT_EARLY, 2 }, 489 { P_GPLL10_OUT_EVEN, 3 }, 490 { P_GPLL9_OUT_MAIN, 4 }, 491 { P_GPLL3_OUT_EVEN, 6 }, 492 }; 493 494 static const struct clk_parent_data gcc_parent_data_3[] = { 495 { .index = DT_BI_TCXO }, 496 { .hw = &gpll0.clkr.hw }, 497 { .hw = &gpll9.clkr.hw }, 498 { .hw = &gpll10.clkr.hw }, 499 { .hw = &gpll9_out_main.clkr.hw }, 500 { .hw = &gpll3_out_even.clkr.hw }, 501 }; 502 503 static const struct parent_map gcc_parent_map_4[] = { 504 { P_BI_TCXO, 0 }, 505 { P_GPLL0_OUT_MAIN, 1 }, 506 { P_GPLL0_OUT_EVEN, 2 }, 507 { P_GPLL0_OUT_ODD, 4 }, 508 { P_GPLL4_OUT_EVEN, 5 }, 509 { P_GPLL3_OUT_EVEN, 6 }, 510 }; 511 512 static const struct clk_parent_data gcc_parent_data_4[] = { 513 { .index = DT_BI_TCXO }, 514 { .hw = &gpll0.clkr.hw }, 515 { .hw = &gpll0_out_even.clkr.hw }, 516 { .hw = &gpll0_out_odd.clkr.hw }, 517 { .hw = &gpll4.clkr.hw }, 518 { .hw = &gpll3_out_even.clkr.hw }, 519 }; 520 521 static const struct parent_map gcc_parent_map_5[] = { 522 { P_BI_TCXO, 0 }, 523 { P_GPLL0_OUT_MAIN, 1 }, 524 { P_GPLL8_OUT_MAIN, 2 }, 525 { P_GPLL10_OUT_EVEN, 3 }, 526 { P_GPLL9_OUT_MAIN, 4 }, 527 { P_GPLL8_OUT_EVEN, 5 }, 528 { P_GPLL3_OUT_EVEN, 6 }, 529 }; 530 531 static const struct clk_parent_data gcc_parent_data_5[] = { 532 { .index = DT_BI_TCXO }, 533 { .hw = &gpll0.clkr.hw }, 534 { .hw = &gpll8.clkr.hw }, 535 { .hw = &gpll10.clkr.hw }, 536 { .hw = &gpll9_out_main.clkr.hw }, 537 { .hw = &gpll8_out_even.clkr.hw }, 538 { .hw = &gpll3_out_even.clkr.hw }, 539 }; 540 541 static const struct parent_map gcc_parent_map_6[] = { 542 { P_BI_TCXO, 0 }, 543 { P_GPLL0_OUT_MAIN, 1 }, 544 { P_GPLL8_OUT_MAIN, 2 }, 545 { P_GPLL5_OUT_EVEN, 3 }, 546 { P_GPLL9_OUT_MAIN, 4 }, 547 { P_GPLL8_OUT_EVEN, 5 }, 548 { P_GPLL3_OUT_MAIN, 6 }, 549 }; 550 551 static const struct clk_parent_data gcc_parent_data_6[] = { 552 { .index = DT_BI_TCXO }, 553 { .hw = &gpll0.clkr.hw }, 554 { .hw = &gpll8.clkr.hw }, 555 { .hw = &gpll5.clkr.hw }, 556 { .hw = &gpll9_out_main.clkr.hw }, 557 { .hw = &gpll8_out_even.clkr.hw }, 558 { .hw = &gpll3.clkr.hw }, 559 }; 560 561 static const struct parent_map gcc_parent_map_7[] = { 562 { P_BI_TCXO, 0 }, 563 { P_GPLL0_OUT_MAIN, 1 }, 564 { P_GPLL0_OUT_EVEN, 2 }, 565 { P_GPLL0_OUT_ODD, 4 }, 566 { P_SLEEP_CLK, 5 }, 567 }; 568 569 static const struct clk_parent_data gcc_parent_data_7[] = { 570 { .index = DT_BI_TCXO }, 571 { .hw = &gpll0.clkr.hw }, 572 { .hw = &gpll0_out_even.clkr.hw }, 573 { .hw = &gpll0_out_odd.clkr.hw }, 574 { .index = DT_SLEEP_CLK }, 575 }; 576 577 static const struct parent_map gcc_parent_map_8[] = { 578 { P_BI_TCXO, 0 }, 579 { P_GPLL0_OUT_MAIN, 1 }, 580 { P_GPLL0_OUT_EVEN, 2 }, 581 { P_GPLL10_OUT_EVEN, 3 }, 582 { P_GPLL4_OUT_EVEN, 5 }, 583 { P_GPLL3_OUT_MAIN, 6 }, 584 }; 585 586 static const struct clk_parent_data gcc_parent_data_8[] = { 587 { .index = DT_BI_TCXO }, 588 { .hw = &gpll0.clkr.hw }, 589 { .hw = &gpll0_out_even.clkr.hw }, 590 { .hw = &gpll10.clkr.hw }, 591 { .hw = &gpll4.clkr.hw }, 592 { .hw = &gpll3.clkr.hw }, 593 }; 594 595 static const struct parent_map gcc_parent_map_9[] = { 596 { P_BI_TCXO, 0 }, 597 { P_GPLL0_OUT_MAIN, 1 }, 598 { P_GPLL0_OUT_EVEN, 2 }, 599 { P_GPLL10_OUT_EVEN, 3 }, 600 { P_GPLL9_OUT_MAIN, 4 }, 601 { P_GPLL8_OUT_EVEN, 5 }, 602 { P_GPLL3_OUT_MAIN, 6 }, 603 }; 604 605 static const struct clk_parent_data gcc_parent_data_9[] = { 606 { .index = DT_BI_TCXO }, 607 { .hw = &gpll0.clkr.hw }, 608 { .hw = &gpll0_out_even.clkr.hw }, 609 { .hw = &gpll10.clkr.hw }, 610 { .hw = &gpll9_out_main.clkr.hw }, 611 { .hw = &gpll8_out_even.clkr.hw }, 612 { .hw = &gpll3.clkr.hw }, 613 }; 614 615 static const struct parent_map gcc_parent_map_10[] = { 616 { P_BI_TCXO, 0 }, 617 { P_GPLL0_OUT_MAIN, 1 }, 618 { P_GPLL8_OUT_MAIN, 2 }, 619 { P_GPLL10_OUT_EVEN, 3 }, 620 { P_GPLL9_OUT_MAIN, 4 }, 621 { P_GPLL8_OUT_EVEN, 5 }, 622 { P_GPLL3_OUT_MAIN, 6 }, 623 }; 624 625 static const struct clk_parent_data gcc_parent_data_10[] = { 626 { .index = DT_BI_TCXO }, 627 { .hw = &gpll0.clkr.hw }, 628 { .hw = &gpll8.clkr.hw }, 629 { .hw = &gpll10.clkr.hw }, 630 { .hw = &gpll9_out_main.clkr.hw }, 631 { .hw = &gpll8_out_even.clkr.hw }, 632 { .hw = &gpll3.clkr.hw }, 633 }; 634 635 static const struct parent_map gcc_parent_map_11[] = { 636 { P_BI_TCXO, 0 }, 637 { P_GPLL0_OUT_MAIN, 1 }, 638 { P_GPLL8_OUT_MAIN, 2 }, 639 { P_GPLL10_OUT_EVEN, 3 }, 640 { P_GPLL6_OUT_MAIN, 4 }, 641 { P_GPLL3_OUT_EVEN, 6 }, 642 }; 643 644 static const struct clk_parent_data gcc_parent_data_11[] = { 645 { .index = DT_BI_TCXO }, 646 { .hw = &gpll0.clkr.hw }, 647 { .hw = &gpll8.clkr.hw }, 648 { .hw = &gpll10.clkr.hw }, 649 { .hw = &gpll6.clkr.hw }, 650 { .hw = &gpll3_out_even.clkr.hw }, 651 }; 652 653 static const struct parent_map gcc_parent_map_12[] = { 654 { P_BI_TCXO, 0 }, 655 { P_GPLL0_OUT_MAIN, 1 }, 656 { P_GPLL0_OUT_EVEN, 2 }, 657 { P_GPLL7_OUT_EVEN, 3 }, 658 { P_GPLL4_OUT_EVEN, 5 }, 659 }; 660 661 static const struct clk_parent_data gcc_parent_data_12[] = { 662 { .index = DT_BI_TCXO }, 663 { .hw = &gpll0.clkr.hw }, 664 { .hw = &gpll0_out_even.clkr.hw }, 665 { .hw = &gpll7.clkr.hw }, 666 { .hw = &gpll4.clkr.hw }, 667 }; 668 669 static const struct parent_map gcc_parent_map_13[] = { 670 { P_BI_TCXO, 0 }, 671 { P_SLEEP_CLK, 5 }, 672 }; 673 674 static const struct clk_parent_data gcc_parent_data_13[] = { 675 { .index = DT_BI_TCXO }, 676 { .index = DT_SLEEP_CLK }, 677 }; 678 679 static const struct parent_map gcc_parent_map_14[] = { 680 { P_BI_TCXO, 0 }, 681 { P_GPLL11_OUT_ODD, 2 }, 682 { P_GPLL11_OUT_EVEN, 3 }, 683 }; 684 685 static const struct clk_parent_data gcc_parent_data_14[] = { 686 { .index = DT_BI_TCXO }, 687 { .hw = &gpll11.clkr.hw }, 688 { .hw = &gpll11.clkr.hw }, 689 }; 690 691 static const struct parent_map gcc_parent_map_15[] = { 692 { P_BI_TCXO, 0 }, 693 { P_GPLL0_OUT_MAIN, 1 }, 694 { P_GPLL6_OUT_EVEN, 4 }, 695 }; 696 697 static const struct clk_parent_data gcc_parent_data_15[] = { 698 { .index = DT_BI_TCXO }, 699 { .hw = &gpll0.clkr.hw }, 700 { .hw = &gpll6_out_even.clkr.hw }, 701 }; 702 703 static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = { 704 F(19200000, P_BI_TCXO, 1, 0, 0), 705 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 706 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 707 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 708 { } 709 }; 710 711 static struct clk_rcg2 gcc_camss_axi_clk_src = { 712 .cmd_rcgr = 0x5802c, 713 .mnd_width = 0, 714 .hid_width = 5, 715 .parent_map = gcc_parent_map_8, 716 .freq_tbl = ftbl_gcc_camss_axi_clk_src, 717 .clkr.hw.init = &(struct clk_init_data){ 718 .name = "gcc_camss_axi_clk_src", 719 .parent_data = gcc_parent_data_8, 720 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 721 .ops = &clk_rcg2_shared_ops, 722 }, 723 }; 724 725 static const struct freq_tbl ftbl_gcc_camss_cci_0_clk_src[] = { 726 F(19200000, P_BI_TCXO, 1, 0, 0), 727 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 728 { } 729 }; 730 731 static struct clk_rcg2 gcc_camss_cci_0_clk_src = { 732 .cmd_rcgr = 0x56000, 733 .mnd_width = 0, 734 .hid_width = 5, 735 .parent_map = gcc_parent_map_9, 736 .freq_tbl = ftbl_gcc_camss_cci_0_clk_src, 737 .clkr.hw.init = &(struct clk_init_data){ 738 .name = "gcc_camss_cci_0_clk_src", 739 .parent_data = gcc_parent_data_9, 740 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 741 .ops = &clk_rcg2_shared_ops, 742 }, 743 }; 744 745 static struct clk_rcg2 gcc_camss_cci_1_clk_src = { 746 .cmd_rcgr = 0x5c000, 747 .mnd_width = 0, 748 .hid_width = 5, 749 .parent_map = gcc_parent_map_9, 750 .freq_tbl = ftbl_gcc_camss_cci_0_clk_src, 751 .clkr.hw.init = &(struct clk_init_data){ 752 .name = "gcc_camss_cci_1_clk_src", 753 .parent_data = gcc_parent_data_9, 754 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 755 .ops = &clk_rcg2_shared_ops, 756 }, 757 }; 758 759 static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = { 760 F(19200000, P_BI_TCXO, 1, 0, 0), 761 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0), 762 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 763 { } 764 }; 765 766 static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { 767 .cmd_rcgr = 0x59000, 768 .mnd_width = 0, 769 .hid_width = 5, 770 .parent_map = gcc_parent_map_4, 771 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 772 .clkr.hw.init = &(struct clk_init_data){ 773 .name = "gcc_camss_csi0phytimer_clk_src", 774 .parent_data = gcc_parent_data_4, 775 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 776 .ops = &clk_rcg2_shared_ops, 777 }, 778 }; 779 780 static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { 781 .cmd_rcgr = 0x5901c, 782 .mnd_width = 0, 783 .hid_width = 5, 784 .parent_map = gcc_parent_map_4, 785 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 786 .clkr.hw.init = &(struct clk_init_data){ 787 .name = "gcc_camss_csi1phytimer_clk_src", 788 .parent_data = gcc_parent_data_4, 789 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 790 .ops = &clk_rcg2_shared_ops, 791 }, 792 }; 793 794 static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = { 795 .cmd_rcgr = 0x59038, 796 .mnd_width = 0, 797 .hid_width = 5, 798 .parent_map = gcc_parent_map_4, 799 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 800 .clkr.hw.init = &(struct clk_init_data){ 801 .name = "gcc_camss_csi2phytimer_clk_src", 802 .parent_data = gcc_parent_data_4, 803 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 804 .ops = &clk_rcg2_shared_ops, 805 }, 806 }; 807 808 static struct clk_rcg2 gcc_camss_csi3phytimer_clk_src = { 809 .cmd_rcgr = 0x59054, 810 .mnd_width = 0, 811 .hid_width = 5, 812 .parent_map = gcc_parent_map_4, 813 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 814 .clkr.hw.init = &(struct clk_init_data){ 815 .name = "gcc_camss_csi3phytimer_clk_src", 816 .parent_data = gcc_parent_data_4, 817 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 818 .ops = &clk_rcg2_shared_ops, 819 }, 820 }; 821 822 static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { 823 F(19200000, P_BI_TCXO, 1, 0, 0), 824 F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 15), 825 F(65454545, P_GPLL9_OUT_EARLY, 11, 1, 2), 826 { } 827 }; 828 829 static struct clk_rcg2 gcc_camss_mclk0_clk_src = { 830 .cmd_rcgr = 0x51000, 831 .mnd_width = 8, 832 .hid_width = 5, 833 .parent_map = gcc_parent_map_3, 834 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 835 .clkr.hw.init = &(struct clk_init_data){ 836 .name = "gcc_camss_mclk0_clk_src", 837 .parent_data = gcc_parent_data_3, 838 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 839 .ops = &clk_rcg2_shared_ops, 840 }, 841 }; 842 843 static struct clk_rcg2 gcc_camss_mclk1_clk_src = { 844 .cmd_rcgr = 0x5101c, 845 .mnd_width = 8, 846 .hid_width = 5, 847 .parent_map = gcc_parent_map_3, 848 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 849 .clkr.hw.init = &(struct clk_init_data){ 850 .name = "gcc_camss_mclk1_clk_src", 851 .parent_data = gcc_parent_data_3, 852 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 853 .ops = &clk_rcg2_shared_ops, 854 }, 855 }; 856 857 static struct clk_rcg2 gcc_camss_mclk2_clk_src = { 858 .cmd_rcgr = 0x51038, 859 .mnd_width = 8, 860 .hid_width = 5, 861 .parent_map = gcc_parent_map_3, 862 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 863 .clkr.hw.init = &(struct clk_init_data){ 864 .name = "gcc_camss_mclk2_clk_src", 865 .parent_data = gcc_parent_data_3, 866 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 867 .ops = &clk_rcg2_shared_ops, 868 }, 869 }; 870 871 static struct clk_rcg2 gcc_camss_mclk3_clk_src = { 872 .cmd_rcgr = 0x51054, 873 .mnd_width = 8, 874 .hid_width = 5, 875 .parent_map = gcc_parent_map_3, 876 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 877 .clkr.hw.init = &(struct clk_init_data){ 878 .name = "gcc_camss_mclk3_clk_src", 879 .parent_data = gcc_parent_data_3, 880 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 881 .ops = &clk_rcg2_shared_ops, 882 }, 883 }; 884 885 static struct clk_rcg2 gcc_camss_mclk4_clk_src = { 886 .cmd_rcgr = 0x51070, 887 .mnd_width = 8, 888 .hid_width = 5, 889 .parent_map = gcc_parent_map_3, 890 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 891 .clkr.hw.init = &(struct clk_init_data){ 892 .name = "gcc_camss_mclk4_clk_src", 893 .parent_data = gcc_parent_data_3, 894 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 895 .ops = &clk_rcg2_shared_ops, 896 }, 897 }; 898 899 static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = { 900 F(19200000, P_BI_TCXO, 1, 0, 0), 901 F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0), 902 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 903 { } 904 }; 905 906 static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = { 907 .cmd_rcgr = 0x55024, 908 .mnd_width = 0, 909 .hid_width = 5, 910 .parent_map = gcc_parent_map_10, 911 .freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src, 912 .clkr.hw.init = &(struct clk_init_data){ 913 .name = "gcc_camss_ope_ahb_clk_src", 914 .parent_data = gcc_parent_data_10, 915 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 916 .ops = &clk_rcg2_shared_ops, 917 }, 918 }; 919 920 static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = { 921 F(19200000, P_BI_TCXO, 1, 0, 0), 922 F(200000000, P_GPLL8_OUT_EVEN, 1, 0, 0), 923 F(266600000, P_GPLL8_OUT_EVEN, 1, 0, 0), 924 F(480000000, P_GPLL8_OUT_EVEN, 1, 0, 0), 925 F(580000000, P_GPLL8_OUT_EVEN, 1, 0, 0), 926 { } 927 }; 928 929 static struct clk_rcg2 gcc_camss_ope_clk_src = { 930 .cmd_rcgr = 0x55004, 931 .mnd_width = 0, 932 .hid_width = 5, 933 .parent_map = gcc_parent_map_10, 934 .freq_tbl = ftbl_gcc_camss_ope_clk_src, 935 .clkr.hw.init = &(struct clk_init_data){ 936 .name = "gcc_camss_ope_clk_src", 937 .parent_data = gcc_parent_data_10, 938 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 939 .flags = CLK_SET_RATE_PARENT, 940 .ops = &clk_rcg2_shared_ops, 941 }, 942 }; 943 944 static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = { 945 F(19200000, P_BI_TCXO, 1, 0, 0), 946 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), 947 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 948 F(144000000, P_GPLL9_OUT_MAIN, 2.5, 0, 0), 949 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 950 F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0), 951 F(180000000, P_GPLL9_OUT_MAIN, 2, 0, 0), 952 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 953 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 954 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 955 F(329142857, P_GPLL10_OUT_EVEN, 3.5, 0, 0), 956 F(384000000, P_GPLL10_OUT_EVEN, 3, 0, 0), 957 F(460800000, P_GPLL10_OUT_EVEN, 2.5, 0, 0), 958 F(576000000, P_GPLL10_OUT_EVEN, 2, 0, 0), 959 { } 960 }; 961 962 static struct clk_rcg2 gcc_camss_tfe_0_clk_src = { 963 .cmd_rcgr = 0x52004, 964 .mnd_width = 8, 965 .hid_width = 5, 966 .parent_map = gcc_parent_map_5, 967 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 968 .clkr.hw.init = &(struct clk_init_data){ 969 .name = "gcc_camss_tfe_0_clk_src", 970 .parent_data = gcc_parent_data_5, 971 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 972 .ops = &clk_rcg2_shared_ops, 973 }, 974 }; 975 976 static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = { 977 F(19200000, P_BI_TCXO, 1, 0, 0), 978 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), 979 F(266571429, P_GPLL5_OUT_EVEN, 3.5, 0, 0), 980 F(426400000, P_GPLL3_OUT_MAIN, 2.5, 0, 0), 981 F(466500000, P_GPLL5_OUT_EVEN, 2, 0, 0), 982 { } 983 }; 984 985 static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = { 986 .cmd_rcgr = 0x52094, 987 .mnd_width = 0, 988 .hid_width = 5, 989 .parent_map = gcc_parent_map_6, 990 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 991 .clkr.hw.init = &(struct clk_init_data){ 992 .name = "gcc_camss_tfe_0_csid_clk_src", 993 .parent_data = gcc_parent_data_6, 994 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 995 .ops = &clk_rcg2_shared_ops, 996 }, 997 }; 998 999 static struct clk_rcg2 gcc_camss_tfe_1_clk_src = { 1000 .cmd_rcgr = 0x52024, 1001 .mnd_width = 8, 1002 .hid_width = 5, 1003 .parent_map = gcc_parent_map_5, 1004 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 1005 .clkr.hw.init = &(struct clk_init_data){ 1006 .name = "gcc_camss_tfe_1_clk_src", 1007 .parent_data = gcc_parent_data_5, 1008 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1009 .ops = &clk_rcg2_shared_ops, 1010 }, 1011 }; 1012 1013 static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = { 1014 .cmd_rcgr = 0x520b4, 1015 .mnd_width = 0, 1016 .hid_width = 5, 1017 .parent_map = gcc_parent_map_6, 1018 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 1019 .clkr.hw.init = &(struct clk_init_data){ 1020 .name = "gcc_camss_tfe_1_csid_clk_src", 1021 .parent_data = gcc_parent_data_6, 1022 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1023 .ops = &clk_rcg2_shared_ops, 1024 }, 1025 }; 1026 1027 static struct clk_rcg2 gcc_camss_tfe_2_clk_src = { 1028 .cmd_rcgr = 0x52044, 1029 .mnd_width = 8, 1030 .hid_width = 5, 1031 .parent_map = gcc_parent_map_5, 1032 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 1033 .clkr.hw.init = &(struct clk_init_data){ 1034 .name = "gcc_camss_tfe_2_clk_src", 1035 .parent_data = gcc_parent_data_5, 1036 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1037 .ops = &clk_rcg2_shared_ops, 1038 }, 1039 }; 1040 1041 static struct clk_rcg2 gcc_camss_tfe_2_csid_clk_src = { 1042 .cmd_rcgr = 0x520d4, 1043 .mnd_width = 0, 1044 .hid_width = 5, 1045 .parent_map = gcc_parent_map_6, 1046 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 1047 .clkr.hw.init = &(struct clk_init_data){ 1048 .name = "gcc_camss_tfe_2_csid_clk_src", 1049 .parent_data = gcc_parent_data_6, 1050 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1051 .ops = &clk_rcg2_shared_ops, 1052 }, 1053 }; 1054 1055 static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = { 1056 F(19200000, P_BI_TCXO, 1, 0, 0), 1057 F(256000000, P_GPLL6_OUT_MAIN, 3, 0, 0), 1058 F(384000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 1059 { } 1060 }; 1061 1062 static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = { 1063 .cmd_rcgr = 0x52064, 1064 .mnd_width = 0, 1065 .hid_width = 5, 1066 .parent_map = gcc_parent_map_11, 1067 .freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src, 1068 .clkr.hw.init = &(struct clk_init_data){ 1069 .name = "gcc_camss_tfe_cphy_rx_clk_src", 1070 .parent_data = gcc_parent_data_11, 1071 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 1072 .ops = &clk_rcg2_shared_ops, 1073 }, 1074 }; 1075 1076 static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = { 1077 F(19200000, P_BI_TCXO, 1, 0, 0), 1078 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0), 1079 F(80000000, P_GPLL0_OUT_MAIN, 7.5, 0, 0), 1080 { } 1081 }; 1082 1083 static struct clk_rcg2 gcc_camss_top_ahb_clk_src = { 1084 .cmd_rcgr = 0x58010, 1085 .mnd_width = 0, 1086 .hid_width = 5, 1087 .parent_map = gcc_parent_map_8, 1088 .freq_tbl = ftbl_gcc_camss_top_ahb_clk_src, 1089 .clkr.hw.init = &(struct clk_init_data){ 1090 .name = "gcc_camss_top_ahb_clk_src", 1091 .parent_data = gcc_parent_data_8, 1092 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 1093 .ops = &clk_rcg2_shared_ops, 1094 }, 1095 }; 1096 1097 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { 1098 F(19200000, P_BI_TCXO, 1, 0, 0), 1099 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0), 1100 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0), 1101 { } 1102 }; 1103 1104 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 1105 .cmd_rcgr = 0x2b13c, 1106 .mnd_width = 0, 1107 .hid_width = 5, 1108 .parent_map = gcc_parent_map_2, 1109 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, 1110 .clkr.hw.init = &(struct clk_init_data){ 1111 .name = "gcc_cpuss_ahb_clk_src", 1112 .parent_data = gcc_parent_data_2_ao, 1113 .num_parents = ARRAY_SIZE(gcc_parent_data_2_ao), 1114 .ops = &clk_rcg2_shared_ops, 1115 }, 1116 }; 1117 1118 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 1119 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 1120 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0), 1121 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0), 1122 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0), 1123 { } 1124 }; 1125 1126 static struct clk_rcg2 gcc_gp1_clk_src = { 1127 .cmd_rcgr = 0x4d004, 1128 .mnd_width = 16, 1129 .hid_width = 5, 1130 .parent_map = gcc_parent_map_7, 1131 .freq_tbl = ftbl_gcc_gp1_clk_src, 1132 .clkr.hw.init = &(struct clk_init_data){ 1133 .name = "gcc_gp1_clk_src", 1134 .parent_data = gcc_parent_data_7, 1135 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 1136 .ops = &clk_rcg2_shared_ops, 1137 }, 1138 }; 1139 1140 static struct clk_rcg2 gcc_gp2_clk_src = { 1141 .cmd_rcgr = 0x4e004, 1142 .mnd_width = 16, 1143 .hid_width = 5, 1144 .parent_map = gcc_parent_map_7, 1145 .freq_tbl = ftbl_gcc_gp1_clk_src, 1146 .clkr.hw.init = &(struct clk_init_data){ 1147 .name = "gcc_gp2_clk_src", 1148 .parent_data = gcc_parent_data_7, 1149 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 1150 .ops = &clk_rcg2_shared_ops, 1151 }, 1152 }; 1153 1154 static struct clk_rcg2 gcc_gp3_clk_src = { 1155 .cmd_rcgr = 0x4f004, 1156 .mnd_width = 16, 1157 .hid_width = 5, 1158 .parent_map = gcc_parent_map_7, 1159 .freq_tbl = ftbl_gcc_gp1_clk_src, 1160 .clkr.hw.init = &(struct clk_init_data){ 1161 .name = "gcc_gp3_clk_src", 1162 .parent_data = gcc_parent_data_7, 1163 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 1164 .ops = &clk_rcg2_shared_ops, 1165 }, 1166 }; 1167 1168 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 1169 F(19200000, P_BI_TCXO, 1, 0, 0), 1170 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), 1171 { } 1172 }; 1173 1174 static struct clk_rcg2 gcc_pdm2_clk_src = { 1175 .cmd_rcgr = 0x20010, 1176 .mnd_width = 0, 1177 .hid_width = 5, 1178 .parent_map = gcc_parent_map_0, 1179 .freq_tbl = ftbl_gcc_pdm2_clk_src, 1180 .clkr.hw.init = &(struct clk_init_data){ 1181 .name = "gcc_pdm2_clk_src", 1182 .parent_data = gcc_parent_data_0, 1183 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1184 .ops = &clk_rcg2_shared_ops, 1185 }, 1186 }; 1187 1188 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 1189 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 1190 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 1191 F(19200000, P_BI_TCXO, 1, 0, 0), 1192 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 1193 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 1194 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 1195 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 1196 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 1197 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 1198 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 1199 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 1200 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), 1201 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), 1202 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), 1203 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), 1204 F(128000000, P_GPLL6_OUT_EVEN, 3, 0, 0), 1205 { } 1206 }; 1207 1208 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 1209 .name = "gcc_qupv3_wrap0_s0_clk_src", 1210 .parent_data = gcc_parent_data_1, 1211 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1212 .ops = &clk_rcg2_shared_ops, 1213 }; 1214 1215 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 1216 .cmd_rcgr = 0x1f148, 1217 .mnd_width = 16, 1218 .hid_width = 5, 1219 .parent_map = gcc_parent_map_1, 1220 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1221 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 1222 }; 1223 1224 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 1225 .name = "gcc_qupv3_wrap0_s1_clk_src", 1226 .parent_data = gcc_parent_data_1, 1227 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1228 .ops = &clk_rcg2_shared_ops, 1229 }; 1230 1231 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 1232 .cmd_rcgr = 0x1f278, 1233 .mnd_width = 16, 1234 .hid_width = 5, 1235 .parent_map = gcc_parent_map_1, 1236 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1237 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 1238 }; 1239 1240 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 1241 .name = "gcc_qupv3_wrap0_s2_clk_src", 1242 .parent_data = gcc_parent_data_1, 1243 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1244 .ops = &clk_rcg2_shared_ops, 1245 }; 1246 1247 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 1248 .cmd_rcgr = 0x1f3a8, 1249 .mnd_width = 16, 1250 .hid_width = 5, 1251 .parent_map = gcc_parent_map_1, 1252 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1253 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 1254 }; 1255 1256 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 1257 .name = "gcc_qupv3_wrap0_s3_clk_src", 1258 .parent_data = gcc_parent_data_1, 1259 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1260 .ops = &clk_rcg2_shared_ops, 1261 }; 1262 1263 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 1264 .cmd_rcgr = 0x1f4d8, 1265 .mnd_width = 16, 1266 .hid_width = 5, 1267 .parent_map = gcc_parent_map_1, 1268 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1269 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 1270 }; 1271 1272 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 1273 .name = "gcc_qupv3_wrap0_s4_clk_src", 1274 .parent_data = gcc_parent_data_1, 1275 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1276 .ops = &clk_rcg2_shared_ops, 1277 }; 1278 1279 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 1280 .cmd_rcgr = 0x1f608, 1281 .mnd_width = 16, 1282 .hid_width = 5, 1283 .parent_map = gcc_parent_map_1, 1284 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1285 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 1286 }; 1287 1288 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 1289 .name = "gcc_qupv3_wrap0_s5_clk_src", 1290 .parent_data = gcc_parent_data_1, 1291 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1292 .ops = &clk_rcg2_shared_ops, 1293 }; 1294 1295 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 1296 .cmd_rcgr = 0x1f738, 1297 .mnd_width = 16, 1298 .hid_width = 5, 1299 .parent_map = gcc_parent_map_1, 1300 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1301 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 1302 }; 1303 1304 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 1305 .name = "gcc_qupv3_wrap1_s0_clk_src", 1306 .parent_data = gcc_parent_data_1, 1307 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1308 .ops = &clk_rcg2_shared_ops, 1309 }; 1310 1311 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 1312 .cmd_rcgr = 0x5301c, 1313 .mnd_width = 16, 1314 .hid_width = 5, 1315 .parent_map = gcc_parent_map_1, 1316 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1317 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 1318 }; 1319 1320 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 1321 .name = "gcc_qupv3_wrap1_s1_clk_src", 1322 .parent_data = gcc_parent_data_1, 1323 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1324 .ops = &clk_rcg2_shared_ops, 1325 }; 1326 1327 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 1328 .cmd_rcgr = 0x5314c, 1329 .mnd_width = 16, 1330 .hid_width = 5, 1331 .parent_map = gcc_parent_map_1, 1332 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1333 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 1334 }; 1335 1336 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 1337 .name = "gcc_qupv3_wrap1_s2_clk_src", 1338 .parent_data = gcc_parent_data_1, 1339 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1340 .ops = &clk_rcg2_shared_ops, 1341 }; 1342 1343 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 1344 .cmd_rcgr = 0x5327c, 1345 .mnd_width = 16, 1346 .hid_width = 5, 1347 .parent_map = gcc_parent_map_1, 1348 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1349 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 1350 }; 1351 1352 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 1353 .name = "gcc_qupv3_wrap1_s3_clk_src", 1354 .parent_data = gcc_parent_data_1, 1355 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1356 .ops = &clk_rcg2_shared_ops, 1357 }; 1358 1359 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 1360 .cmd_rcgr = 0x533ac, 1361 .mnd_width = 16, 1362 .hid_width = 5, 1363 .parent_map = gcc_parent_map_1, 1364 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1365 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 1366 }; 1367 1368 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 1369 .name = "gcc_qupv3_wrap1_s4_clk_src", 1370 .parent_data = gcc_parent_data_1, 1371 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1372 .ops = &clk_rcg2_shared_ops, 1373 }; 1374 1375 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 1376 .cmd_rcgr = 0x534dc, 1377 .mnd_width = 16, 1378 .hid_width = 5, 1379 .parent_map = gcc_parent_map_1, 1380 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1381 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 1382 }; 1383 1384 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 1385 .name = "gcc_qupv3_wrap1_s5_clk_src", 1386 .parent_data = gcc_parent_data_1, 1387 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1388 .ops = &clk_rcg2_shared_ops, 1389 }; 1390 1391 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 1392 .cmd_rcgr = 0x5360c, 1393 .mnd_width = 16, 1394 .hid_width = 5, 1395 .parent_map = gcc_parent_map_1, 1396 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1397 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 1398 }; 1399 1400 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 1401 F(144000, P_BI_TCXO, 16, 3, 25), 1402 F(400000, P_BI_TCXO, 12, 1, 4), 1403 F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), 1404 F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), 1405 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 1406 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 1407 F(192000000, P_GPLL6_OUT_EVEN, 2, 0, 0), 1408 F(384000000, P_GPLL6_OUT_EVEN, 1, 0, 0), 1409 { } 1410 }; 1411 1412 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 1413 .cmd_rcgr = 0x38028, 1414 .mnd_width = 8, 1415 .hid_width = 5, 1416 .parent_map = gcc_parent_map_1, 1417 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 1418 .clkr.hw.init = &(struct clk_init_data){ 1419 .name = "gcc_sdcc1_apps_clk_src", 1420 .parent_data = gcc_parent_data_1, 1421 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1422 .ops = &clk_rcg2_shared_ops, 1423 }, 1424 }; 1425 1426 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 1427 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 1428 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 1429 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 1430 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 1431 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 1432 { } 1433 }; 1434 1435 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 1436 .cmd_rcgr = 0x38010, 1437 .mnd_width = 0, 1438 .hid_width = 5, 1439 .parent_map = gcc_parent_map_0, 1440 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 1441 .clkr.hw.init = &(struct clk_init_data){ 1442 .name = "gcc_sdcc1_ice_core_clk_src", 1443 .parent_data = gcc_parent_data_0, 1444 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1445 .ops = &clk_rcg2_shared_ops, 1446 }, 1447 }; 1448 1449 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1450 F(400000, P_BI_TCXO, 12, 1, 4), 1451 F(19200000, P_BI_TCXO, 1, 0, 0), 1452 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 1453 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 1454 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 1455 F(202000000, P_GPLL7_OUT_EVEN, 4, 0, 0), 1456 { } 1457 }; 1458 1459 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1460 .cmd_rcgr = 0x1e00c, 1461 .mnd_width = 8, 1462 .hid_width = 5, 1463 .parent_map = gcc_parent_map_12, 1464 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1465 .clkr.hw.init = &(struct clk_init_data){ 1466 .name = "gcc_sdcc2_apps_clk_src", 1467 .parent_data = gcc_parent_data_12, 1468 .num_parents = ARRAY_SIZE(gcc_parent_data_12), 1469 .ops = &clk_rcg2_shared_ops, 1470 }, 1471 }; 1472 1473 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1474 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 1475 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0), 1476 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0), 1477 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0), 1478 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 1479 { } 1480 }; 1481 1482 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1483 .cmd_rcgr = 0x45020, 1484 .mnd_width = 8, 1485 .hid_width = 5, 1486 .parent_map = gcc_parent_map_2, 1487 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1488 .clkr.hw.init = &(struct clk_init_data){ 1489 .name = "gcc_ufs_phy_axi_clk_src", 1490 .parent_data = gcc_parent_data_2, 1491 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1492 .ops = &clk_rcg2_shared_ops, 1493 }, 1494 }; 1495 1496 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1497 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 1498 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 1499 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 1500 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 1501 { } 1502 }; 1503 1504 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1505 .cmd_rcgr = 0x45048, 1506 .mnd_width = 0, 1507 .hid_width = 5, 1508 .parent_map = gcc_parent_map_0, 1509 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1510 .clkr.hw.init = &(struct clk_init_data){ 1511 .name = "gcc_ufs_phy_ice_core_clk_src", 1512 .parent_data = gcc_parent_data_0, 1513 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1514 .ops = &clk_rcg2_shared_ops, 1515 }, 1516 }; 1517 1518 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1519 F(9600000, P_BI_TCXO, 2, 0, 0), 1520 F(19200000, P_BI_TCXO, 1, 0, 0), 1521 { } 1522 }; 1523 1524 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1525 .cmd_rcgr = 0x4507c, 1526 .mnd_width = 0, 1527 .hid_width = 5, 1528 .parent_map = gcc_parent_map_0, 1529 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1530 .clkr.hw.init = &(struct clk_init_data){ 1531 .name = "gcc_ufs_phy_phy_aux_clk_src", 1532 .parent_data = gcc_parent_data_0, 1533 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1534 .ops = &clk_rcg2_shared_ops, 1535 }, 1536 }; 1537 1538 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 1539 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 1540 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 1541 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 1542 { } 1543 }; 1544 1545 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1546 .cmd_rcgr = 0x45060, 1547 .mnd_width = 0, 1548 .hid_width = 5, 1549 .parent_map = gcc_parent_map_0, 1550 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 1551 .clkr.hw.init = &(struct clk_init_data){ 1552 .name = "gcc_ufs_phy_unipro_core_clk_src", 1553 .parent_data = gcc_parent_data_0, 1554 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1555 .ops = &clk_rcg2_shared_ops, 1556 }, 1557 }; 1558 1559 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1560 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), 1561 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 1562 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0), 1563 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 1564 { } 1565 }; 1566 1567 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1568 .cmd_rcgr = 0x1a01c, 1569 .mnd_width = 8, 1570 .hid_width = 5, 1571 .parent_map = gcc_parent_map_2, 1572 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1573 .clkr.hw.init = &(struct clk_init_data){ 1574 .name = "gcc_usb30_prim_master_clk_src", 1575 .parent_data = gcc_parent_data_2, 1576 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1577 .ops = &clk_rcg2_shared_ops, 1578 }, 1579 }; 1580 1581 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 1582 F(19200000, P_BI_TCXO, 1, 0, 0), 1583 { } 1584 }; 1585 1586 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1587 .cmd_rcgr = 0x1a034, 1588 .mnd_width = 0, 1589 .hid_width = 5, 1590 .parent_map = gcc_parent_map_0, 1591 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1592 .clkr.hw.init = &(struct clk_init_data){ 1593 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1594 .parent_data = gcc_parent_data_0, 1595 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1596 .ops = &clk_rcg2_shared_ops, 1597 }, 1598 }; 1599 1600 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1601 .cmd_rcgr = 0x1a060, 1602 .mnd_width = 0, 1603 .hid_width = 5, 1604 .parent_map = gcc_parent_map_13, 1605 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1606 .clkr.hw.init = &(struct clk_init_data){ 1607 .name = "gcc_usb3_prim_phy_aux_clk_src", 1608 .parent_data = gcc_parent_data_13, 1609 .num_parents = ARRAY_SIZE(gcc_parent_data_13), 1610 .ops = &clk_rcg2_shared_ops, 1611 }, 1612 }; 1613 1614 static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = { 1615 F(133000000, P_GPLL11_OUT_EVEN, 4, 0, 0), 1616 F(240000000, P_GPLL11_OUT_EVEN, 2.5, 0, 0), 1617 F(300000000, P_GPLL11_OUT_EVEN, 2, 0, 0), 1618 F(384000000, P_GPLL11_OUT_EVEN, 2, 0, 0), 1619 { } 1620 }; 1621 1622 static struct clk_rcg2 gcc_video_venus_clk_src = { 1623 .cmd_rcgr = 0x58060, 1624 .mnd_width = 0, 1625 .hid_width = 5, 1626 .parent_map = gcc_parent_map_14, 1627 .freq_tbl = ftbl_gcc_video_venus_clk_src, 1628 .clkr.hw.init = &(struct clk_init_data){ 1629 .name = "gcc_video_venus_clk_src", 1630 .parent_data = gcc_parent_data_14, 1631 .num_parents = ARRAY_SIZE(gcc_parent_data_14), 1632 .flags = CLK_SET_RATE_PARENT, 1633 .ops = &clk_rcg2_shared_ops, 1634 }, 1635 }; 1636 1637 static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = { 1638 .reg = 0x2b154, 1639 .shift = 0, 1640 .width = 4, 1641 .clkr.hw.init = &(struct clk_init_data) { 1642 .name = "gcc_cpuss_ahb_postdiv_clk_src", 1643 .parent_hws = (const struct clk_hw*[]){ 1644 &gcc_cpuss_ahb_clk_src.clkr.hw, 1645 }, 1646 .num_parents = 1, 1647 .flags = CLK_SET_RATE_PARENT, 1648 .ops = &clk_regmap_div_ro_ops, 1649 }, 1650 }; 1651 1652 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1653 .reg = 0x1a04c, 1654 .shift = 0, 1655 .width = 4, 1656 .clkr.hw.init = &(struct clk_init_data) { 1657 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1658 .parent_hws = (const struct clk_hw*[]){ 1659 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1660 }, 1661 .num_parents = 1, 1662 .flags = CLK_SET_RATE_PARENT, 1663 .ops = &clk_regmap_div_ro_ops, 1664 }, 1665 }; 1666 1667 static struct clk_branch gcc_ahb2phy_csi_clk = { 1668 .halt_reg = 0x1d004, 1669 .halt_check = BRANCH_HALT_VOTED, 1670 .hwcg_reg = 0x1d004, 1671 .hwcg_bit = 1, 1672 .clkr = { 1673 .enable_reg = 0x1d004, 1674 .enable_mask = BIT(0), 1675 .hw.init = &(struct clk_init_data){ 1676 .name = "gcc_ahb2phy_csi_clk", 1677 .ops = &clk_branch2_ops, 1678 }, 1679 }, 1680 }; 1681 1682 static struct clk_branch gcc_ahb2phy_usb_clk = { 1683 .halt_reg = 0x1d008, 1684 .halt_check = BRANCH_HALT_VOTED, 1685 .hwcg_reg = 0x1d008, 1686 .hwcg_bit = 1, 1687 .clkr = { 1688 .enable_reg = 0x1d008, 1689 .enable_mask = BIT(0), 1690 .hw.init = &(struct clk_init_data){ 1691 .name = "gcc_ahb2phy_usb_clk", 1692 .ops = &clk_branch2_ops, 1693 }, 1694 }, 1695 }; 1696 1697 static struct clk_branch gcc_bimc_gpu_axi_clk = { 1698 .halt_reg = 0x71154, 1699 .halt_check = BRANCH_HALT_VOTED, 1700 .hwcg_reg = 0x71154, 1701 .hwcg_bit = 1, 1702 .clkr = { 1703 .enable_reg = 0x71154, 1704 .enable_mask = BIT(0), 1705 .hw.init = &(struct clk_init_data){ 1706 .name = "gcc_bimc_gpu_axi_clk", 1707 .ops = &clk_branch2_ops, 1708 }, 1709 }, 1710 }; 1711 1712 static struct clk_branch gcc_boot_rom_ahb_clk = { 1713 .halt_reg = 0x23004, 1714 .halt_check = BRANCH_HALT_VOTED, 1715 .hwcg_reg = 0x23004, 1716 .hwcg_bit = 1, 1717 .clkr = { 1718 .enable_reg = 0x79004, 1719 .enable_mask = BIT(10), 1720 .hw.init = &(struct clk_init_data){ 1721 .name = "gcc_boot_rom_ahb_clk", 1722 .ops = &clk_branch2_ops, 1723 }, 1724 }, 1725 }; 1726 1727 static struct clk_branch gcc_cam_throttle_nrt_clk = { 1728 .halt_reg = 0x17070, 1729 .halt_check = BRANCH_HALT_VOTED, 1730 .hwcg_reg = 0x17070, 1731 .hwcg_bit = 1, 1732 .clkr = { 1733 .enable_reg = 0x79004, 1734 .enable_mask = BIT(27), 1735 .hw.init = &(struct clk_init_data){ 1736 .name = "gcc_cam_throttle_nrt_clk", 1737 .ops = &clk_branch2_ops, 1738 }, 1739 }, 1740 }; 1741 1742 static struct clk_branch gcc_cam_throttle_rt_clk = { 1743 .halt_reg = 0x1706c, 1744 .halt_check = BRANCH_HALT_VOTED, 1745 .hwcg_reg = 0x1706c, 1746 .hwcg_bit = 1, 1747 .clkr = { 1748 .enable_reg = 0x79004, 1749 .enable_mask = BIT(26), 1750 .hw.init = &(struct clk_init_data){ 1751 .name = "gcc_cam_throttle_rt_clk", 1752 .ops = &clk_branch2_ops, 1753 }, 1754 }, 1755 }; 1756 1757 static struct clk_branch gcc_camera_ahb_clk = { 1758 .halt_reg = 0x17008, 1759 .halt_check = BRANCH_HALT_DELAY, 1760 .hwcg_reg = 0x17008, 1761 .hwcg_bit = 1, 1762 .clkr = { 1763 .enable_reg = 0x17008, 1764 .enable_mask = BIT(0), 1765 .hw.init = &(struct clk_init_data){ 1766 .name = "gcc_camera_ahb_clk", 1767 .flags = CLK_IS_CRITICAL, 1768 .ops = &clk_branch2_ops, 1769 }, 1770 }, 1771 }; 1772 1773 static struct clk_branch gcc_camss_axi_clk = { 1774 .halt_reg = 0x58044, 1775 .halt_check = BRANCH_HALT, 1776 .clkr = { 1777 .enable_reg = 0x58044, 1778 .enable_mask = BIT(0), 1779 .hw.init = &(struct clk_init_data){ 1780 .name = "gcc_camss_axi_clk", 1781 .parent_data = &(const struct clk_parent_data){ 1782 .hw = &gcc_camss_axi_clk_src.clkr.hw, 1783 }, 1784 .num_parents = 1, 1785 .flags = CLK_SET_RATE_PARENT, 1786 .ops = &clk_branch2_ops, 1787 }, 1788 }, 1789 }; 1790 1791 static struct clk_branch gcc_camss_cci_0_clk = { 1792 .halt_reg = 0x56018, 1793 .halt_check = BRANCH_HALT, 1794 .clkr = { 1795 .enable_reg = 0x56018, 1796 .enable_mask = BIT(0), 1797 .hw.init = &(struct clk_init_data){ 1798 .name = "gcc_camss_cci_0_clk", 1799 .parent_data = &(const struct clk_parent_data){ 1800 .hw = &gcc_camss_cci_0_clk_src.clkr.hw, 1801 }, 1802 .num_parents = 1, 1803 .flags = CLK_SET_RATE_PARENT, 1804 .ops = &clk_branch2_ops, 1805 }, 1806 }, 1807 }; 1808 1809 static struct clk_branch gcc_camss_cci_1_clk = { 1810 .halt_reg = 0x5c018, 1811 .halt_check = BRANCH_HALT, 1812 .clkr = { 1813 .enable_reg = 0x5c018, 1814 .enable_mask = BIT(0), 1815 .hw.init = &(struct clk_init_data){ 1816 .name = "gcc_camss_cci_1_clk", 1817 .parent_data = &(const struct clk_parent_data){ 1818 .hw = &gcc_camss_cci_1_clk_src.clkr.hw, 1819 }, 1820 .num_parents = 1, 1821 .flags = CLK_SET_RATE_PARENT, 1822 .ops = &clk_branch2_ops, 1823 }, 1824 }, 1825 }; 1826 1827 static struct clk_branch gcc_camss_cphy_0_clk = { 1828 .halt_reg = 0x52088, 1829 .halt_check = BRANCH_HALT, 1830 .clkr = { 1831 .enable_reg = 0x52088, 1832 .enable_mask = BIT(0), 1833 .hw.init = &(struct clk_init_data){ 1834 .name = "gcc_camss_cphy_0_clk", 1835 .parent_data = &(const struct clk_parent_data){ 1836 .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1837 }, 1838 .num_parents = 1, 1839 .flags = CLK_SET_RATE_PARENT, 1840 .ops = &clk_branch2_ops, 1841 }, 1842 }, 1843 }; 1844 1845 static struct clk_branch gcc_camss_cphy_1_clk = { 1846 .halt_reg = 0x5208c, 1847 .halt_check = BRANCH_HALT, 1848 .clkr = { 1849 .enable_reg = 0x5208c, 1850 .enable_mask = BIT(0), 1851 .hw.init = &(struct clk_init_data){ 1852 .name = "gcc_camss_cphy_1_clk", 1853 .parent_data = &(const struct clk_parent_data){ 1854 .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1855 }, 1856 .num_parents = 1, 1857 .flags = CLK_SET_RATE_PARENT, 1858 .ops = &clk_branch2_ops, 1859 }, 1860 }, 1861 }; 1862 1863 static struct clk_branch gcc_camss_cphy_2_clk = { 1864 .halt_reg = 0x52090, 1865 .halt_check = BRANCH_HALT, 1866 .clkr = { 1867 .enable_reg = 0x52090, 1868 .enable_mask = BIT(0), 1869 .hw.init = &(struct clk_init_data){ 1870 .name = "gcc_camss_cphy_2_clk", 1871 .parent_data = &(const struct clk_parent_data){ 1872 .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1873 }, 1874 .num_parents = 1, 1875 .flags = CLK_SET_RATE_PARENT, 1876 .ops = &clk_branch2_ops, 1877 }, 1878 }, 1879 }; 1880 1881 static struct clk_branch gcc_camss_cphy_3_clk = { 1882 .halt_reg = 0x520f8, 1883 .halt_check = BRANCH_HALT, 1884 .clkr = { 1885 .enable_reg = 0x520f8, 1886 .enable_mask = BIT(0), 1887 .hw.init = &(struct clk_init_data){ 1888 .name = "gcc_camss_cphy_3_clk", 1889 .parent_data = &(const struct clk_parent_data){ 1890 .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1891 }, 1892 .num_parents = 1, 1893 .flags = CLK_SET_RATE_PARENT, 1894 .ops = &clk_branch2_ops, 1895 }, 1896 }, 1897 }; 1898 1899 static struct clk_branch gcc_camss_csi0phytimer_clk = { 1900 .halt_reg = 0x59018, 1901 .halt_check = BRANCH_HALT, 1902 .clkr = { 1903 .enable_reg = 0x59018, 1904 .enable_mask = BIT(0), 1905 .hw.init = &(struct clk_init_data){ 1906 .name = "gcc_camss_csi0phytimer_clk", 1907 .parent_data = &(const struct clk_parent_data){ 1908 .hw = &gcc_camss_csi0phytimer_clk_src.clkr.hw, 1909 }, 1910 .num_parents = 1, 1911 .flags = CLK_SET_RATE_PARENT, 1912 .ops = &clk_branch2_ops, 1913 }, 1914 }, 1915 }; 1916 1917 static struct clk_branch gcc_camss_csi1phytimer_clk = { 1918 .halt_reg = 0x59034, 1919 .halt_check = BRANCH_HALT, 1920 .clkr = { 1921 .enable_reg = 0x59034, 1922 .enable_mask = BIT(0), 1923 .hw.init = &(struct clk_init_data){ 1924 .name = "gcc_camss_csi1phytimer_clk", 1925 .parent_data = &(const struct clk_parent_data){ 1926 .hw = &gcc_camss_csi1phytimer_clk_src.clkr.hw, 1927 }, 1928 .num_parents = 1, 1929 .flags = CLK_SET_RATE_PARENT, 1930 .ops = &clk_branch2_ops, 1931 }, 1932 }, 1933 }; 1934 1935 static struct clk_branch gcc_camss_csi2phytimer_clk = { 1936 .halt_reg = 0x59050, 1937 .halt_check = BRANCH_HALT, 1938 .clkr = { 1939 .enable_reg = 0x59050, 1940 .enable_mask = BIT(0), 1941 .hw.init = &(struct clk_init_data){ 1942 .name = "gcc_camss_csi2phytimer_clk", 1943 .parent_data = &(const struct clk_parent_data){ 1944 .hw = &gcc_camss_csi2phytimer_clk_src.clkr.hw, 1945 }, 1946 .num_parents = 1, 1947 .flags = CLK_SET_RATE_PARENT, 1948 .ops = &clk_branch2_ops, 1949 }, 1950 }, 1951 }; 1952 1953 static struct clk_branch gcc_camss_csi3phytimer_clk = { 1954 .halt_reg = 0x5906c, 1955 .halt_check = BRANCH_HALT, 1956 .clkr = { 1957 .enable_reg = 0x5906c, 1958 .enable_mask = BIT(0), 1959 .hw.init = &(struct clk_init_data){ 1960 .name = "gcc_camss_csi3phytimer_clk", 1961 .parent_data = &(const struct clk_parent_data){ 1962 .hw = &gcc_camss_csi3phytimer_clk_src.clkr.hw, 1963 }, 1964 .num_parents = 1, 1965 .flags = CLK_SET_RATE_PARENT, 1966 .ops = &clk_branch2_ops, 1967 }, 1968 }, 1969 }; 1970 1971 static struct clk_branch gcc_camss_mclk0_clk = { 1972 .halt_reg = 0x51018, 1973 .halt_check = BRANCH_HALT, 1974 .clkr = { 1975 .enable_reg = 0x51018, 1976 .enable_mask = BIT(0), 1977 .hw.init = &(struct clk_init_data){ 1978 .name = "gcc_camss_mclk0_clk", 1979 .parent_data = &(const struct clk_parent_data){ 1980 .hw = &gcc_camss_mclk0_clk_src.clkr.hw, 1981 }, 1982 .num_parents = 1, 1983 .flags = CLK_SET_RATE_PARENT, 1984 .ops = &clk_branch2_ops, 1985 }, 1986 }, 1987 }; 1988 1989 static struct clk_branch gcc_camss_mclk1_clk = { 1990 .halt_reg = 0x51034, 1991 .halt_check = BRANCH_HALT, 1992 .clkr = { 1993 .enable_reg = 0x51034, 1994 .enable_mask = BIT(0), 1995 .hw.init = &(struct clk_init_data){ 1996 .name = "gcc_camss_mclk1_clk", 1997 .parent_data = &(const struct clk_parent_data){ 1998 .hw = &gcc_camss_mclk1_clk_src.clkr.hw, 1999 }, 2000 .num_parents = 1, 2001 .flags = CLK_SET_RATE_PARENT, 2002 .ops = &clk_branch2_ops, 2003 }, 2004 }, 2005 }; 2006 2007 static struct clk_branch gcc_camss_mclk2_clk = { 2008 .halt_reg = 0x51050, 2009 .halt_check = BRANCH_HALT, 2010 .clkr = { 2011 .enable_reg = 0x51050, 2012 .enable_mask = BIT(0), 2013 .hw.init = &(struct clk_init_data){ 2014 .name = "gcc_camss_mclk2_clk", 2015 .parent_data = &(const struct clk_parent_data){ 2016 .hw = &gcc_camss_mclk2_clk_src.clkr.hw, 2017 }, 2018 .num_parents = 1, 2019 .flags = CLK_SET_RATE_PARENT, 2020 .ops = &clk_branch2_ops, 2021 }, 2022 }, 2023 }; 2024 2025 static struct clk_branch gcc_camss_mclk3_clk = { 2026 .halt_reg = 0x5106c, 2027 .halt_check = BRANCH_HALT, 2028 .clkr = { 2029 .enable_reg = 0x5106c, 2030 .enable_mask = BIT(0), 2031 .hw.init = &(struct clk_init_data){ 2032 .name = "gcc_camss_mclk3_clk", 2033 .parent_data = &(const struct clk_parent_data){ 2034 .hw = &gcc_camss_mclk3_clk_src.clkr.hw, 2035 }, 2036 .num_parents = 1, 2037 .flags = CLK_SET_RATE_PARENT, 2038 .ops = &clk_branch2_ops, 2039 }, 2040 }, 2041 }; 2042 2043 static struct clk_branch gcc_camss_mclk4_clk = { 2044 .halt_reg = 0x51088, 2045 .halt_check = BRANCH_HALT, 2046 .clkr = { 2047 .enable_reg = 0x51088, 2048 .enable_mask = BIT(0), 2049 .hw.init = &(struct clk_init_data){ 2050 .name = "gcc_camss_mclk4_clk", 2051 .parent_data = &(const struct clk_parent_data){ 2052 .hw = &gcc_camss_mclk4_clk_src.clkr.hw, 2053 }, 2054 .num_parents = 1, 2055 .flags = CLK_SET_RATE_PARENT, 2056 .ops = &clk_branch2_ops, 2057 }, 2058 }, 2059 }; 2060 2061 static struct clk_branch gcc_camss_nrt_axi_clk = { 2062 .halt_reg = 0x58054, 2063 .halt_check = BRANCH_HALT, 2064 .clkr = { 2065 .enable_reg = 0x58054, 2066 .enable_mask = BIT(0), 2067 .hw.init = &(struct clk_init_data){ 2068 .name = "gcc_camss_nrt_axi_clk", 2069 .ops = &clk_branch2_ops, 2070 }, 2071 }, 2072 }; 2073 2074 static struct clk_branch gcc_camss_ope_ahb_clk = { 2075 .halt_reg = 0x5503c, 2076 .halt_check = BRANCH_HALT, 2077 .clkr = { 2078 .enable_reg = 0x5503c, 2079 .enable_mask = BIT(0), 2080 .hw.init = &(struct clk_init_data){ 2081 .name = "gcc_camss_ope_ahb_clk", 2082 .parent_data = &(const struct clk_parent_data){ 2083 .hw = &gcc_camss_ope_ahb_clk_src.clkr.hw, 2084 }, 2085 .num_parents = 1, 2086 .flags = CLK_SET_RATE_PARENT, 2087 .ops = &clk_branch2_ops, 2088 }, 2089 }, 2090 }; 2091 2092 static struct clk_branch gcc_camss_ope_clk = { 2093 .halt_reg = 0x5501c, 2094 .halt_check = BRANCH_HALT, 2095 .clkr = { 2096 .enable_reg = 0x5501c, 2097 .enable_mask = BIT(0), 2098 .hw.init = &(struct clk_init_data){ 2099 .name = "gcc_camss_ope_clk", 2100 .parent_data = &(const struct clk_parent_data){ 2101 .hw = &gcc_camss_ope_clk_src.clkr.hw, 2102 }, 2103 .num_parents = 1, 2104 .flags = CLK_SET_RATE_PARENT, 2105 .ops = &clk_branch2_ops, 2106 }, 2107 }, 2108 }; 2109 2110 static struct clk_branch gcc_camss_rt_axi_clk = { 2111 .halt_reg = 0x5805c, 2112 .halt_check = BRANCH_HALT, 2113 .clkr = { 2114 .enable_reg = 0x5805c, 2115 .enable_mask = BIT(0), 2116 .hw.init = &(struct clk_init_data){ 2117 .name = "gcc_camss_rt_axi_clk", 2118 .ops = &clk_branch2_ops, 2119 }, 2120 }, 2121 }; 2122 2123 static struct clk_branch gcc_camss_tfe_0_clk = { 2124 .halt_reg = 0x5201c, 2125 .halt_check = BRANCH_HALT, 2126 .clkr = { 2127 .enable_reg = 0x5201c, 2128 .enable_mask = BIT(0), 2129 .hw.init = &(struct clk_init_data){ 2130 .name = "gcc_camss_tfe_0_clk", 2131 .parent_data = &(const struct clk_parent_data){ 2132 .hw = &gcc_camss_tfe_0_clk_src.clkr.hw, 2133 }, 2134 .num_parents = 1, 2135 .flags = CLK_SET_RATE_PARENT, 2136 .ops = &clk_branch2_ops, 2137 }, 2138 }, 2139 }; 2140 2141 static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = { 2142 .halt_reg = 0x5207c, 2143 .halt_check = BRANCH_HALT, 2144 .clkr = { 2145 .enable_reg = 0x5207c, 2146 .enable_mask = BIT(0), 2147 .hw.init = &(struct clk_init_data){ 2148 .name = "gcc_camss_tfe_0_cphy_rx_clk", 2149 .parent_data = &(const struct clk_parent_data){ 2150 .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2151 }, 2152 .num_parents = 1, 2153 .flags = CLK_SET_RATE_PARENT, 2154 .ops = &clk_branch2_ops, 2155 }, 2156 }, 2157 }; 2158 2159 static struct clk_branch gcc_camss_tfe_0_csid_clk = { 2160 .halt_reg = 0x520ac, 2161 .halt_check = BRANCH_HALT, 2162 .clkr = { 2163 .enable_reg = 0x520ac, 2164 .enable_mask = BIT(0), 2165 .hw.init = &(struct clk_init_data){ 2166 .name = "gcc_camss_tfe_0_csid_clk", 2167 .parent_data = &(const struct clk_parent_data){ 2168 .hw = &gcc_camss_tfe_0_csid_clk_src.clkr.hw, 2169 }, 2170 .num_parents = 1, 2171 .flags = CLK_SET_RATE_PARENT, 2172 .ops = &clk_branch2_ops, 2173 }, 2174 }, 2175 }; 2176 2177 static struct clk_branch gcc_camss_tfe_1_clk = { 2178 .halt_reg = 0x5203c, 2179 .halt_check = BRANCH_HALT, 2180 .clkr = { 2181 .enable_reg = 0x5203c, 2182 .enable_mask = BIT(0), 2183 .hw.init = &(struct clk_init_data){ 2184 .name = "gcc_camss_tfe_1_clk", 2185 .parent_data = &(const struct clk_parent_data){ 2186 .hw = &gcc_camss_tfe_1_clk_src.clkr.hw, 2187 }, 2188 .num_parents = 1, 2189 .flags = CLK_SET_RATE_PARENT, 2190 .ops = &clk_branch2_ops, 2191 }, 2192 }, 2193 }; 2194 2195 static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = { 2196 .halt_reg = 0x52080, 2197 .halt_check = BRANCH_HALT, 2198 .clkr = { 2199 .enable_reg = 0x52080, 2200 .enable_mask = BIT(0), 2201 .hw.init = &(struct clk_init_data){ 2202 .name = "gcc_camss_tfe_1_cphy_rx_clk", 2203 .parent_data = &(const struct clk_parent_data){ 2204 .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2205 }, 2206 .num_parents = 1, 2207 .flags = CLK_SET_RATE_PARENT, 2208 .ops = &clk_branch2_ops, 2209 }, 2210 }, 2211 }; 2212 2213 static struct clk_branch gcc_camss_tfe_1_csid_clk = { 2214 .halt_reg = 0x520cc, 2215 .halt_check = BRANCH_HALT, 2216 .clkr = { 2217 .enable_reg = 0x520cc, 2218 .enable_mask = BIT(0), 2219 .hw.init = &(struct clk_init_data){ 2220 .name = "gcc_camss_tfe_1_csid_clk", 2221 .parent_data = &(const struct clk_parent_data){ 2222 .hw = &gcc_camss_tfe_1_csid_clk_src.clkr.hw, 2223 }, 2224 .num_parents = 1, 2225 .flags = CLK_SET_RATE_PARENT, 2226 .ops = &clk_branch2_ops, 2227 }, 2228 }, 2229 }; 2230 2231 static struct clk_branch gcc_camss_tfe_2_clk = { 2232 .halt_reg = 0x5205c, 2233 .halt_check = BRANCH_HALT, 2234 .clkr = { 2235 .enable_reg = 0x5205c, 2236 .enable_mask = BIT(0), 2237 .hw.init = &(struct clk_init_data){ 2238 .name = "gcc_camss_tfe_2_clk", 2239 .parent_data = &(const struct clk_parent_data){ 2240 .hw = &gcc_camss_tfe_2_clk_src.clkr.hw, 2241 }, 2242 .num_parents = 1, 2243 .flags = CLK_SET_RATE_PARENT, 2244 .ops = &clk_branch2_ops, 2245 }, 2246 }, 2247 }; 2248 2249 static struct clk_branch gcc_camss_tfe_2_cphy_rx_clk = { 2250 .halt_reg = 0x52084, 2251 .halt_check = BRANCH_HALT, 2252 .clkr = { 2253 .enable_reg = 0x52084, 2254 .enable_mask = BIT(0), 2255 .hw.init = &(struct clk_init_data){ 2256 .name = "gcc_camss_tfe_2_cphy_rx_clk", 2257 .parent_data = &(const struct clk_parent_data){ 2258 .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2259 }, 2260 .num_parents = 1, 2261 .flags = CLK_SET_RATE_PARENT, 2262 .ops = &clk_branch2_ops, 2263 }, 2264 }, 2265 }; 2266 2267 static struct clk_branch gcc_camss_tfe_2_csid_clk = { 2268 .halt_reg = 0x520ec, 2269 .halt_check = BRANCH_HALT, 2270 .clkr = { 2271 .enable_reg = 0x520ec, 2272 .enable_mask = BIT(0), 2273 .hw.init = &(struct clk_init_data){ 2274 .name = "gcc_camss_tfe_2_csid_clk", 2275 .parent_data = &(const struct clk_parent_data){ 2276 .hw = &gcc_camss_tfe_2_csid_clk_src.clkr.hw, 2277 }, 2278 .num_parents = 1, 2279 .flags = CLK_SET_RATE_PARENT, 2280 .ops = &clk_branch2_ops, 2281 }, 2282 }, 2283 }; 2284 2285 static struct clk_branch gcc_camss_top_ahb_clk = { 2286 .halt_reg = 0x58028, 2287 .halt_check = BRANCH_HALT, 2288 .clkr = { 2289 .enable_reg = 0x58028, 2290 .enable_mask = BIT(0), 2291 .hw.init = &(struct clk_init_data){ 2292 .name = "gcc_camss_top_ahb_clk", 2293 .parent_data = &(const struct clk_parent_data){ 2294 .hw = &gcc_camss_top_ahb_clk_src.clkr.hw, 2295 }, 2296 .num_parents = 1, 2297 .flags = CLK_SET_RATE_PARENT, 2298 .ops = &clk_branch2_ops, 2299 }, 2300 }, 2301 }; 2302 2303 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 2304 .halt_reg = 0x1a084, 2305 .halt_check = BRANCH_HALT_VOTED, 2306 .hwcg_reg = 0x1a084, 2307 .hwcg_bit = 1, 2308 .clkr = { 2309 .enable_reg = 0x1a084, 2310 .enable_mask = BIT(0), 2311 .hw.init = &(struct clk_init_data){ 2312 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 2313 .parent_data = &(const struct clk_parent_data){ 2314 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 2315 }, 2316 .num_parents = 1, 2317 .flags = CLK_SET_RATE_PARENT, 2318 .ops = &clk_branch2_ops, 2319 }, 2320 }, 2321 }; 2322 2323 static struct clk_branch gcc_disp_ahb_clk = { 2324 .halt_reg = 0x1700c, 2325 .halt_check = BRANCH_HALT_VOTED, 2326 .hwcg_reg = 0x1700c, 2327 .hwcg_bit = 1, 2328 .clkr = { 2329 .enable_reg = 0x1700c, 2330 .enable_mask = BIT(0), 2331 .hw.init = &(struct clk_init_data){ 2332 .name = "gcc_disp_ahb_clk", 2333 .flags = CLK_IS_CRITICAL, 2334 .ops = &clk_branch2_ops, 2335 }, 2336 }, 2337 }; 2338 2339 static struct clk_regmap_div gcc_disp_gpll0_clk_src = { 2340 .reg = 0x17058, 2341 .shift = 0, 2342 .width = 2, 2343 .clkr.hw.init = &(struct clk_init_data) { 2344 .name = "gcc_disp_gpll0_clk_src", 2345 .parent_names = 2346 (const char *[]){ "gpll0" }, 2347 .num_parents = 1, 2348 .ops = &clk_regmap_div_ops, 2349 }, 2350 }; 2351 2352 static struct clk_branch gcc_disp_gpll0_div_clk_src = { 2353 .halt_check = BRANCH_HALT_DELAY, 2354 .clkr = { 2355 .enable_reg = 0x79004, 2356 .enable_mask = BIT(20), 2357 .hw.init = &(struct clk_init_data){ 2358 .name = "gcc_disp_gpll0_div_clk_src", 2359 .parent_data = &(const struct clk_parent_data){ 2360 .hw = &gcc_disp_gpll0_clk_src.clkr.hw, 2361 }, 2362 .num_parents = 1, 2363 .flags = CLK_SET_RATE_PARENT, 2364 .ops = &clk_branch2_ops, 2365 }, 2366 }, 2367 }; 2368 2369 static struct clk_branch gcc_disp_hf_axi_clk = { 2370 .halt_reg = 0x17020, 2371 .halt_check = BRANCH_VOTED, 2372 .hwcg_reg = 0x17020, 2373 .hwcg_bit = 1, 2374 .clkr = { 2375 .enable_reg = 0x17020, 2376 .enable_mask = BIT(0), 2377 .hw.init = &(struct clk_init_data){ 2378 .name = "gcc_disp_hf_axi_clk", 2379 .ops = &clk_branch2_ops, 2380 }, 2381 }, 2382 }; 2383 2384 static struct clk_branch gcc_disp_sleep_clk = { 2385 .halt_reg = 0x17074, 2386 .halt_check = BRANCH_HALT_VOTED, 2387 .hwcg_reg = 0x17074, 2388 .hwcg_bit = 1, 2389 .clkr = { 2390 .enable_reg = 0x17074, 2391 .enable_mask = BIT(0), 2392 .hw.init = &(struct clk_init_data){ 2393 .name = "gcc_disp_sleep_clk", 2394 .ops = &clk_branch2_ops, 2395 }, 2396 }, 2397 }; 2398 2399 static struct clk_branch gcc_disp_throttle_core_clk = { 2400 .halt_reg = 0x17064, 2401 .halt_check = BRANCH_HALT_VOTED, 2402 .hwcg_reg = 0x17064, 2403 .hwcg_bit = 1, 2404 .clkr = { 2405 .enable_reg = 0x7900c, 2406 .enable_mask = BIT(5), 2407 .hw.init = &(struct clk_init_data){ 2408 .name = "gcc_disp_throttle_core_clk", 2409 .ops = &clk_branch2_ops, 2410 }, 2411 }, 2412 }; 2413 2414 static struct clk_branch gcc_gp1_clk = { 2415 .halt_reg = 0x4d000, 2416 .halt_check = BRANCH_HALT, 2417 .clkr = { 2418 .enable_reg = 0x4d000, 2419 .enable_mask = BIT(0), 2420 .hw.init = &(struct clk_init_data){ 2421 .name = "gcc_gp1_clk", 2422 .parent_data = &(const struct clk_parent_data){ 2423 .hw = &gcc_gp1_clk_src.clkr.hw, 2424 }, 2425 .num_parents = 1, 2426 .flags = CLK_SET_RATE_PARENT, 2427 .ops = &clk_branch2_ops, 2428 }, 2429 }, 2430 }; 2431 2432 static struct clk_branch gcc_gp2_clk = { 2433 .halt_reg = 0x4e000, 2434 .halt_check = BRANCH_HALT, 2435 .clkr = { 2436 .enable_reg = 0x4e000, 2437 .enable_mask = BIT(0), 2438 .hw.init = &(struct clk_init_data){ 2439 .name = "gcc_gp2_clk", 2440 .parent_data = &(const struct clk_parent_data){ 2441 .hw = &gcc_gp2_clk_src.clkr.hw, 2442 }, 2443 .num_parents = 1, 2444 .flags = CLK_SET_RATE_PARENT, 2445 .ops = &clk_branch2_ops, 2446 }, 2447 }, 2448 }; 2449 2450 static struct clk_branch gcc_gp3_clk = { 2451 .halt_reg = 0x4f000, 2452 .halt_check = BRANCH_HALT, 2453 .clkr = { 2454 .enable_reg = 0x4f000, 2455 .enable_mask = BIT(0), 2456 .hw.init = &(struct clk_init_data){ 2457 .name = "gcc_gp3_clk", 2458 .parent_data = &(const struct clk_parent_data){ 2459 .hw = &gcc_gp3_clk_src.clkr.hw, 2460 }, 2461 .num_parents = 1, 2462 .flags = CLK_SET_RATE_PARENT, 2463 .ops = &clk_branch2_ops, 2464 }, 2465 }, 2466 }; 2467 2468 static struct clk_branch gcc_gpu_cfg_ahb_clk = { 2469 .halt_reg = 0x36004, 2470 .halt_check = BRANCH_HALT_VOTED, 2471 .hwcg_reg = 0x36004, 2472 .hwcg_bit = 1, 2473 .clkr = { 2474 .enable_reg = 0x36004, 2475 .enable_mask = BIT(0), 2476 .hw.init = &(struct clk_init_data){ 2477 .name = "gcc_gpu_cfg_ahb_clk", 2478 .flags = CLK_IS_CRITICAL, 2479 .ops = &clk_branch2_ops, 2480 }, 2481 }, 2482 }; 2483 2484 static struct clk_branch gcc_gpu_gpll0_clk_src = { 2485 .halt_check = BRANCH_HALT_DELAY, 2486 .clkr = { 2487 .enable_reg = 0x79004, 2488 .enable_mask = BIT(15), 2489 .hw.init = &(struct clk_init_data){ 2490 .name = "gcc_gpu_gpll0_clk_src", 2491 .parent_data = &(const struct clk_parent_data){ 2492 .hw = &gpll0.clkr.hw, 2493 }, 2494 .num_parents = 1, 2495 .flags = CLK_SET_RATE_PARENT, 2496 .ops = &clk_branch2_ops, 2497 }, 2498 }, 2499 }; 2500 2501 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 2502 .halt_check = BRANCH_HALT_DELAY, 2503 .clkr = { 2504 .enable_reg = 0x79004, 2505 .enable_mask = BIT(16), 2506 .hw.init = &(struct clk_init_data){ 2507 .name = "gcc_gpu_gpll0_div_clk_src", 2508 .parent_data = &(const struct clk_parent_data){ 2509 .hw = &gpll0_out_even.clkr.hw, 2510 }, 2511 .num_parents = 1, 2512 .flags = CLK_SET_RATE_PARENT, 2513 .ops = &clk_branch2_ops, 2514 }, 2515 }, 2516 }; 2517 2518 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 2519 .halt_reg = 0x3600c, 2520 .halt_check = BRANCH_VOTED, 2521 .hwcg_reg = 0x3600c, 2522 .hwcg_bit = 1, 2523 .clkr = { 2524 .enable_reg = 0x3600c, 2525 .enable_mask = BIT(0), 2526 .hw.init = &(struct clk_init_data){ 2527 .name = "gcc_gpu_memnoc_gfx_clk", 2528 .ops = &clk_branch2_ops, 2529 }, 2530 }, 2531 }; 2532 2533 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2534 .halt_reg = 0x36018, 2535 .halt_check = BRANCH_HALT, 2536 .clkr = { 2537 .enable_reg = 0x36018, 2538 .enable_mask = BIT(0), 2539 .hw.init = &(struct clk_init_data){ 2540 .name = "gcc_gpu_snoc_dvm_gfx_clk", 2541 .ops = &clk_branch2_ops, 2542 }, 2543 }, 2544 }; 2545 2546 static struct clk_branch gcc_gpu_throttle_core_clk = { 2547 .halt_reg = 0x36048, 2548 .halt_check = BRANCH_HALT_VOTED, 2549 .hwcg_reg = 0x36048, 2550 .hwcg_bit = 1, 2551 .clkr = { 2552 .enable_reg = 0x79004, 2553 .enable_mask = BIT(31), 2554 .hw.init = &(struct clk_init_data){ 2555 .name = "gcc_gpu_throttle_core_clk", 2556 .ops = &clk_branch2_ops, 2557 }, 2558 }, 2559 }; 2560 2561 static struct clk_branch gcc_pdm2_clk = { 2562 .halt_reg = 0x2000c, 2563 .halt_check = BRANCH_HALT, 2564 .clkr = { 2565 .enable_reg = 0x2000c, 2566 .enable_mask = BIT(0), 2567 .hw.init = &(struct clk_init_data){ 2568 .name = "gcc_pdm2_clk", 2569 .parent_data = &(const struct clk_parent_data){ 2570 .hw = &gcc_pdm2_clk_src.clkr.hw, 2571 }, 2572 .num_parents = 1, 2573 .flags = CLK_SET_RATE_PARENT, 2574 .ops = &clk_branch2_ops, 2575 }, 2576 }, 2577 }; 2578 2579 static struct clk_branch gcc_pdm_ahb_clk = { 2580 .halt_reg = 0x20004, 2581 .halt_check = BRANCH_HALT_VOTED, 2582 .hwcg_reg = 0x20004, 2583 .hwcg_bit = 1, 2584 .clkr = { 2585 .enable_reg = 0x20004, 2586 .enable_mask = BIT(0), 2587 .hw.init = &(struct clk_init_data){ 2588 .name = "gcc_pdm_ahb_clk", 2589 .ops = &clk_branch2_ops, 2590 }, 2591 }, 2592 }; 2593 2594 static struct clk_branch gcc_pdm_xo4_clk = { 2595 .halt_reg = 0x20008, 2596 .halt_check = BRANCH_HALT, 2597 .clkr = { 2598 .enable_reg = 0x20008, 2599 .enable_mask = BIT(0), 2600 .hw.init = &(struct clk_init_data){ 2601 .name = "gcc_pdm_xo4_clk", 2602 .ops = &clk_branch2_ops, 2603 }, 2604 }, 2605 }; 2606 2607 static struct clk_branch gcc_prng_ahb_clk = { 2608 .halt_reg = 0x21004, 2609 .halt_check = BRANCH_HALT_VOTED, 2610 .hwcg_reg = 0x21004, 2611 .hwcg_bit = 1, 2612 .clkr = { 2613 .enable_reg = 0x79004, 2614 .enable_mask = BIT(13), 2615 .hw.init = &(struct clk_init_data){ 2616 .name = "gcc_prng_ahb_clk", 2617 .ops = &clk_branch2_ops, 2618 }, 2619 }, 2620 }; 2621 2622 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2623 .halt_reg = 0x17014, 2624 .halt_check = BRANCH_HALT_VOTED, 2625 .hwcg_reg = 0x17014, 2626 .hwcg_bit = 1, 2627 .clkr = { 2628 .enable_reg = 0x7900c, 2629 .enable_mask = BIT(0), 2630 .hw.init = &(struct clk_init_data){ 2631 .name = "gcc_qmip_camera_nrt_ahb_clk", 2632 .ops = &clk_branch2_ops, 2633 }, 2634 }, 2635 }; 2636 2637 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2638 .halt_reg = 0x17060, 2639 .halt_check = BRANCH_HALT_VOTED, 2640 .hwcg_reg = 0x17060, 2641 .hwcg_bit = 1, 2642 .clkr = { 2643 .enable_reg = 0x7900c, 2644 .enable_mask = BIT(2), 2645 .hw.init = &(struct clk_init_data){ 2646 .name = "gcc_qmip_camera_rt_ahb_clk", 2647 .ops = &clk_branch2_ops, 2648 }, 2649 }, 2650 }; 2651 2652 static struct clk_branch gcc_qmip_disp_ahb_clk = { 2653 .halt_reg = 0x17018, 2654 .halt_check = BRANCH_HALT_VOTED, 2655 .hwcg_reg = 0x17018, 2656 .hwcg_bit = 1, 2657 .clkr = { 2658 .enable_reg = 0x7900c, 2659 .enable_mask = BIT(1), 2660 .hw.init = &(struct clk_init_data){ 2661 .name = "gcc_qmip_disp_ahb_clk", 2662 .ops = &clk_branch2_ops, 2663 }, 2664 }, 2665 }; 2666 2667 static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = { 2668 .halt_reg = 0x36040, 2669 .halt_check = BRANCH_HALT_VOTED, 2670 .hwcg_reg = 0x36040, 2671 .hwcg_bit = 1, 2672 .clkr = { 2673 .enable_reg = 0x7900c, 2674 .enable_mask = BIT(4), 2675 .hw.init = &(struct clk_init_data){ 2676 .name = "gcc_qmip_gpu_cfg_ahb_clk", 2677 .ops = &clk_branch2_ops, 2678 }, 2679 }, 2680 }; 2681 2682 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2683 .halt_reg = 0x17010, 2684 .halt_check = BRANCH_HALT_VOTED, 2685 .hwcg_reg = 0x17010, 2686 .hwcg_bit = 1, 2687 .clkr = { 2688 .enable_reg = 0x79004, 2689 .enable_mask = BIT(25), 2690 .hw.init = &(struct clk_init_data){ 2691 .name = "gcc_qmip_video_vcodec_ahb_clk", 2692 .ops = &clk_branch2_ops, 2693 }, 2694 }, 2695 }; 2696 2697 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2698 .halt_reg = 0x1f014, 2699 .halt_check = BRANCH_HALT_VOTED, 2700 .clkr = { 2701 .enable_reg = 0x7900c, 2702 .enable_mask = BIT(9), 2703 .hw.init = &(struct clk_init_data){ 2704 .name = "gcc_qupv3_wrap0_core_2x_clk", 2705 .ops = &clk_branch2_ops, 2706 }, 2707 }, 2708 }; 2709 2710 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2711 .halt_reg = 0x1f00c, 2712 .halt_check = BRANCH_HALT_VOTED, 2713 .clkr = { 2714 .enable_reg = 0x7900c, 2715 .enable_mask = BIT(8), 2716 .hw.init = &(struct clk_init_data){ 2717 .name = "gcc_qupv3_wrap0_core_clk", 2718 .ops = &clk_branch2_ops, 2719 }, 2720 }, 2721 }; 2722 2723 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2724 .halt_reg = 0x1f144, 2725 .halt_check = BRANCH_HALT_VOTED, 2726 .clkr = { 2727 .enable_reg = 0x7900c, 2728 .enable_mask = BIT(10), 2729 .hw.init = &(struct clk_init_data){ 2730 .name = "gcc_qupv3_wrap0_s0_clk", 2731 .parent_data = &(const struct clk_parent_data){ 2732 .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 2733 }, 2734 .num_parents = 1, 2735 .flags = CLK_SET_RATE_PARENT, 2736 .ops = &clk_branch2_ops, 2737 }, 2738 }, 2739 }; 2740 2741 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2742 .halt_reg = 0x1f274, 2743 .halt_check = BRANCH_HALT_VOTED, 2744 .clkr = { 2745 .enable_reg = 0x7900c, 2746 .enable_mask = BIT(11), 2747 .hw.init = &(struct clk_init_data){ 2748 .name = "gcc_qupv3_wrap0_s1_clk", 2749 .parent_data = &(const struct clk_parent_data){ 2750 .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 2751 }, 2752 .num_parents = 1, 2753 .flags = CLK_SET_RATE_PARENT, 2754 .ops = &clk_branch2_ops, 2755 }, 2756 }, 2757 }; 2758 2759 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2760 .halt_reg = 0x1f3a4, 2761 .halt_check = BRANCH_HALT_VOTED, 2762 .clkr = { 2763 .enable_reg = 0x7900c, 2764 .enable_mask = BIT(12), 2765 .hw.init = &(struct clk_init_data){ 2766 .name = "gcc_qupv3_wrap0_s2_clk", 2767 .parent_data = &(const struct clk_parent_data){ 2768 .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2769 }, 2770 .num_parents = 1, 2771 .flags = CLK_SET_RATE_PARENT, 2772 .ops = &clk_branch2_ops, 2773 }, 2774 }, 2775 }; 2776 2777 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2778 .halt_reg = 0x1f4d4, 2779 .halt_check = BRANCH_HALT_VOTED, 2780 .clkr = { 2781 .enable_reg = 0x7900c, 2782 .enable_mask = BIT(13), 2783 .hw.init = &(struct clk_init_data){ 2784 .name = "gcc_qupv3_wrap0_s3_clk", 2785 .parent_data = &(const struct clk_parent_data){ 2786 .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2787 }, 2788 .num_parents = 1, 2789 .flags = CLK_SET_RATE_PARENT, 2790 .ops = &clk_branch2_ops, 2791 }, 2792 }, 2793 }; 2794 2795 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2796 .halt_reg = 0x1f604, 2797 .halt_check = BRANCH_HALT_VOTED, 2798 .clkr = { 2799 .enable_reg = 0x7900c, 2800 .enable_mask = BIT(14), 2801 .hw.init = &(struct clk_init_data){ 2802 .name = "gcc_qupv3_wrap0_s4_clk", 2803 .parent_data = &(const struct clk_parent_data){ 2804 .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2805 }, 2806 .num_parents = 1, 2807 .flags = CLK_SET_RATE_PARENT, 2808 .ops = &clk_branch2_ops, 2809 }, 2810 }, 2811 }; 2812 2813 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2814 .halt_reg = 0x1f734, 2815 .halt_check = BRANCH_HALT_VOTED, 2816 .clkr = { 2817 .enable_reg = 0x7900c, 2818 .enable_mask = BIT(15), 2819 .hw.init = &(struct clk_init_data){ 2820 .name = "gcc_qupv3_wrap0_s5_clk", 2821 .parent_data = &(const struct clk_parent_data){ 2822 .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2823 }, 2824 .num_parents = 1, 2825 .flags = CLK_SET_RATE_PARENT, 2826 .ops = &clk_branch2_ops, 2827 }, 2828 }, 2829 }; 2830 2831 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2832 .halt_reg = 0x53014, 2833 .halt_check = BRANCH_HALT_VOTED, 2834 .clkr = { 2835 .enable_reg = 0x7900c, 2836 .enable_mask = BIT(20), 2837 .hw.init = &(struct clk_init_data){ 2838 .name = "gcc_qupv3_wrap1_core_2x_clk", 2839 .ops = &clk_branch2_ops, 2840 }, 2841 }, 2842 }; 2843 2844 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2845 .halt_reg = 0x5300c, 2846 .halt_check = BRANCH_HALT_VOTED, 2847 .clkr = { 2848 .enable_reg = 0x7900c, 2849 .enable_mask = BIT(19), 2850 .hw.init = &(struct clk_init_data){ 2851 .name = "gcc_qupv3_wrap1_core_clk", 2852 .ops = &clk_branch2_ops, 2853 }, 2854 }, 2855 }; 2856 2857 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2858 .halt_reg = 0x53018, 2859 .halt_check = BRANCH_HALT_VOTED, 2860 .clkr = { 2861 .enable_reg = 0x7900c, 2862 .enable_mask = BIT(21), 2863 .hw.init = &(struct clk_init_data){ 2864 .name = "gcc_qupv3_wrap1_s0_clk", 2865 .parent_data = &(const struct clk_parent_data){ 2866 .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2867 }, 2868 .num_parents = 1, 2869 .flags = CLK_SET_RATE_PARENT, 2870 .ops = &clk_branch2_ops, 2871 }, 2872 }, 2873 }; 2874 2875 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2876 .halt_reg = 0x53148, 2877 .halt_check = BRANCH_HALT_VOTED, 2878 .clkr = { 2879 .enable_reg = 0x7900c, 2880 .enable_mask = BIT(22), 2881 .hw.init = &(struct clk_init_data){ 2882 .name = "gcc_qupv3_wrap1_s1_clk", 2883 .parent_data = &(const struct clk_parent_data){ 2884 .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2885 }, 2886 .num_parents = 1, 2887 .flags = CLK_SET_RATE_PARENT, 2888 .ops = &clk_branch2_ops, 2889 }, 2890 }, 2891 }; 2892 2893 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2894 .halt_reg = 0x53278, 2895 .halt_check = BRANCH_HALT_VOTED, 2896 .clkr = { 2897 .enable_reg = 0x7900c, 2898 .enable_mask = BIT(23), 2899 .hw.init = &(struct clk_init_data){ 2900 .name = "gcc_qupv3_wrap1_s2_clk", 2901 .parent_data = &(const struct clk_parent_data){ 2902 .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2903 }, 2904 .num_parents = 1, 2905 .flags = CLK_SET_RATE_PARENT, 2906 .ops = &clk_branch2_ops, 2907 }, 2908 }, 2909 }; 2910 2911 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2912 .halt_reg = 0x533a8, 2913 .halt_check = BRANCH_HALT_VOTED, 2914 .clkr = { 2915 .enable_reg = 0x7900c, 2916 .enable_mask = BIT(24), 2917 .hw.init = &(struct clk_init_data){ 2918 .name = "gcc_qupv3_wrap1_s3_clk", 2919 .parent_data = &(const struct clk_parent_data){ 2920 .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2921 }, 2922 .num_parents = 1, 2923 .flags = CLK_SET_RATE_PARENT, 2924 .ops = &clk_branch2_ops, 2925 }, 2926 }, 2927 }; 2928 2929 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2930 .halt_reg = 0x534d8, 2931 .halt_check = BRANCH_HALT_VOTED, 2932 .clkr = { 2933 .enable_reg = 0x7900c, 2934 .enable_mask = BIT(25), 2935 .hw.init = &(struct clk_init_data){ 2936 .name = "gcc_qupv3_wrap1_s4_clk", 2937 .parent_data = &(const struct clk_parent_data){ 2938 .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2939 }, 2940 .num_parents = 1, 2941 .flags = CLK_SET_RATE_PARENT, 2942 .ops = &clk_branch2_ops, 2943 }, 2944 }, 2945 }; 2946 2947 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2948 .halt_reg = 0x53608, 2949 .halt_check = BRANCH_HALT_VOTED, 2950 .clkr = { 2951 .enable_reg = 0x7900c, 2952 .enable_mask = BIT(26), 2953 .hw.init = &(struct clk_init_data){ 2954 .name = "gcc_qupv3_wrap1_s5_clk", 2955 .parent_data = &(const struct clk_parent_data){ 2956 .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2957 }, 2958 .num_parents = 1, 2959 .flags = CLK_SET_RATE_PARENT, 2960 .ops = &clk_branch2_ops, 2961 }, 2962 }, 2963 }; 2964 2965 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2966 .halt_reg = 0x1f004, 2967 .halt_check = BRANCH_HALT_VOTED, 2968 .hwcg_reg = 0x1f004, 2969 .hwcg_bit = 1, 2970 .clkr = { 2971 .enable_reg = 0x7900c, 2972 .enable_mask = BIT(6), 2973 .hw.init = &(struct clk_init_data){ 2974 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2975 .ops = &clk_branch2_ops, 2976 }, 2977 }, 2978 }; 2979 2980 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2981 .halt_reg = 0x1f008, 2982 .halt_check = BRANCH_HALT_VOTED, 2983 .hwcg_reg = 0x1f008, 2984 .hwcg_bit = 1, 2985 .clkr = { 2986 .enable_reg = 0x7900c, 2987 .enable_mask = BIT(7), 2988 .hw.init = &(struct clk_init_data){ 2989 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2990 .ops = &clk_branch2_ops, 2991 }, 2992 }, 2993 }; 2994 2995 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2996 .halt_reg = 0x53004, 2997 .halt_check = BRANCH_HALT_VOTED, 2998 .hwcg_reg = 0x53004, 2999 .hwcg_bit = 1, 3000 .clkr = { 3001 .enable_reg = 0x7900c, 3002 .enable_mask = BIT(17), 3003 .hw.init = &(struct clk_init_data){ 3004 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 3005 .ops = &clk_branch2_ops, 3006 }, 3007 }, 3008 }; 3009 3010 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 3011 .halt_reg = 0x53008, 3012 .halt_check = BRANCH_HALT_VOTED, 3013 .hwcg_reg = 0x53008, 3014 .hwcg_bit = 1, 3015 .clkr = { 3016 .enable_reg = 0x7900c, 3017 .enable_mask = BIT(18), 3018 .hw.init = &(struct clk_init_data){ 3019 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 3020 .ops = &clk_branch2_ops, 3021 }, 3022 }, 3023 }; 3024 3025 static struct clk_branch gcc_sdcc1_ahb_clk = { 3026 .halt_reg = 0x38008, 3027 .halt_check = BRANCH_HALT, 3028 .clkr = { 3029 .enable_reg = 0x38008, 3030 .enable_mask = BIT(0), 3031 .hw.init = &(struct clk_init_data){ 3032 .name = "gcc_sdcc1_ahb_clk", 3033 .ops = &clk_branch2_ops, 3034 }, 3035 }, 3036 }; 3037 3038 static struct clk_branch gcc_sdcc1_apps_clk = { 3039 .halt_reg = 0x38004, 3040 .halt_check = BRANCH_HALT, 3041 .clkr = { 3042 .enable_reg = 0x38004, 3043 .enable_mask = BIT(0), 3044 .hw.init = &(struct clk_init_data){ 3045 .name = "gcc_sdcc1_apps_clk", 3046 .parent_data = &(const struct clk_parent_data){ 3047 .hw = &gcc_sdcc1_apps_clk_src.clkr.hw, 3048 }, 3049 .num_parents = 1, 3050 .flags = CLK_SET_RATE_PARENT, 3051 .ops = &clk_branch2_ops, 3052 }, 3053 }, 3054 }; 3055 3056 static struct clk_branch gcc_sdcc1_ice_core_clk = { 3057 .halt_reg = 0x3800c, 3058 .halt_check = BRANCH_HALT_VOTED, 3059 .hwcg_reg = 0x3800c, 3060 .hwcg_bit = 1, 3061 .clkr = { 3062 .enable_reg = 0x3800c, 3063 .enable_mask = BIT(0), 3064 .hw.init = &(struct clk_init_data){ 3065 .name = "gcc_sdcc1_ice_core_clk", 3066 .parent_data = &(const struct clk_parent_data){ 3067 .hw = &gcc_sdcc1_ice_core_clk_src.clkr.hw, 3068 }, 3069 .num_parents = 1, 3070 .flags = CLK_SET_RATE_PARENT, 3071 .ops = &clk_branch2_ops, 3072 }, 3073 }, 3074 }; 3075 3076 static struct clk_branch gcc_sdcc2_ahb_clk = { 3077 .halt_reg = 0x1e008, 3078 .halt_check = BRANCH_HALT, 3079 .clkr = { 3080 .enable_reg = 0x1e008, 3081 .enable_mask = BIT(0), 3082 .hw.init = &(struct clk_init_data){ 3083 .name = "gcc_sdcc2_ahb_clk", 3084 .ops = &clk_branch2_ops, 3085 }, 3086 }, 3087 }; 3088 3089 static struct clk_branch gcc_sdcc2_apps_clk = { 3090 .halt_reg = 0x1e004, 3091 .halt_check = BRANCH_HALT, 3092 .clkr = { 3093 .enable_reg = 0x1e004, 3094 .enable_mask = BIT(0), 3095 .hw.init = &(struct clk_init_data){ 3096 .name = "gcc_sdcc2_apps_clk", 3097 .parent_data = &(const struct clk_parent_data){ 3098 .hw = &gcc_sdcc2_apps_clk_src.clkr.hw, 3099 }, 3100 .num_parents = 1, 3101 .flags = CLK_SET_RATE_PARENT, 3102 .ops = &clk_branch2_ops, 3103 }, 3104 }, 3105 }; 3106 3107 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 3108 .halt_reg = 0x2b06c, 3109 .halt_check = BRANCH_HALT_VOTED, 3110 .hwcg_reg = 0x2b06c, 3111 .hwcg_bit = 1, 3112 .clkr = { 3113 .enable_reg = 0x79004, 3114 .enable_mask = BIT(0), 3115 .hw.init = &(struct clk_init_data){ 3116 .name = "gcc_sys_noc_cpuss_ahb_clk", 3117 .parent_data = &(const struct clk_parent_data){ 3118 .hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, 3119 }, 3120 .num_parents = 1, 3121 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 3122 .ops = &clk_branch2_ops, 3123 }, 3124 }, 3125 }; 3126 3127 static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { 3128 .halt_reg = 0x45098, 3129 .halt_check = BRANCH_HALT, 3130 .clkr = { 3131 .enable_reg = 0x45098, 3132 .enable_mask = BIT(0), 3133 .hw.init = &(struct clk_init_data){ 3134 .name = "gcc_sys_noc_ufs_phy_axi_clk", 3135 .parent_data = &(const struct clk_parent_data){ 3136 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 3137 }, 3138 .num_parents = 1, 3139 .flags = CLK_SET_RATE_PARENT, 3140 .ops = &clk_branch2_ops, 3141 }, 3142 }, 3143 }; 3144 3145 static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { 3146 .halt_reg = 0x1a080, 3147 .halt_check = BRANCH_HALT_VOTED, 3148 .hwcg_reg = 0x1a080, 3149 .hwcg_bit = 1, 3150 .clkr = { 3151 .enable_reg = 0x1a080, 3152 .enable_mask = BIT(0), 3153 .hw.init = &(struct clk_init_data){ 3154 .name = "gcc_sys_noc_usb3_prim_axi_clk", 3155 .parent_data = &(const struct clk_parent_data){ 3156 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 3157 }, 3158 .num_parents = 1, 3159 .flags = CLK_SET_RATE_PARENT, 3160 .ops = &clk_branch2_ops, 3161 }, 3162 }, 3163 }; 3164 3165 static struct clk_branch gcc_ufs_phy_ahb_clk = { 3166 .halt_reg = 0x45014, 3167 .halt_check = BRANCH_HALT_VOTED, 3168 .hwcg_reg = 0x45014, 3169 .hwcg_bit = 1, 3170 .clkr = { 3171 .enable_reg = 0x45014, 3172 .enable_mask = BIT(0), 3173 .hw.init = &(struct clk_init_data){ 3174 .name = "gcc_ufs_phy_ahb_clk", 3175 .ops = &clk_branch2_ops, 3176 }, 3177 }, 3178 }; 3179 3180 static struct clk_branch gcc_ufs_phy_axi_clk = { 3181 .halt_reg = 0x45010, 3182 .halt_check = BRANCH_HALT_VOTED, 3183 .hwcg_reg = 0x45010, 3184 .hwcg_bit = 1, 3185 .clkr = { 3186 .enable_reg = 0x45010, 3187 .enable_mask = BIT(0), 3188 .hw.init = &(struct clk_init_data){ 3189 .name = "gcc_ufs_phy_axi_clk", 3190 .parent_data = &(const struct clk_parent_data){ 3191 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 3192 }, 3193 .num_parents = 1, 3194 .flags = CLK_SET_RATE_PARENT, 3195 .ops = &clk_branch2_ops, 3196 }, 3197 }, 3198 }; 3199 3200 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 3201 .halt_reg = 0x45044, 3202 .halt_check = BRANCH_HALT_VOTED, 3203 .hwcg_reg = 0x45044, 3204 .hwcg_bit = 1, 3205 .clkr = { 3206 .enable_reg = 0x45044, 3207 .enable_mask = BIT(0), 3208 .hw.init = &(struct clk_init_data){ 3209 .name = "gcc_ufs_phy_ice_core_clk", 3210 .parent_data = &(const struct clk_parent_data){ 3211 .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 3212 }, 3213 .num_parents = 1, 3214 .flags = CLK_SET_RATE_PARENT, 3215 .ops = &clk_branch2_ops, 3216 }, 3217 }, 3218 }; 3219 3220 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 3221 .halt_reg = 0x45078, 3222 .halt_check = BRANCH_HALT_VOTED, 3223 .hwcg_reg = 0x45078, 3224 .hwcg_bit = 1, 3225 .clkr = { 3226 .enable_reg = 0x45078, 3227 .enable_mask = BIT(0), 3228 .hw.init = &(struct clk_init_data){ 3229 .name = "gcc_ufs_phy_phy_aux_clk", 3230 .parent_data = &(const struct clk_parent_data){ 3231 .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 3232 }, 3233 .num_parents = 1, 3234 .flags = CLK_SET_RATE_PARENT, 3235 .ops = &clk_branch2_ops, 3236 }, 3237 }, 3238 }; 3239 3240 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 3241 .halt_reg = 0x4501c, 3242 .halt_check = BRANCH_HALT_SKIP, 3243 .clkr = { 3244 .enable_reg = 0x4501c, 3245 .enable_mask = BIT(0), 3246 .hw.init = &(struct clk_init_data){ 3247 .name = "gcc_ufs_phy_rx_symbol_0_clk", 3248 .ops = &clk_branch2_ops, 3249 }, 3250 }, 3251 }; 3252 3253 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 3254 .halt_reg = 0x45018, 3255 .halt_check = BRANCH_HALT_SKIP, 3256 .clkr = { 3257 .enable_reg = 0x45018, 3258 .enable_mask = BIT(0), 3259 .hw.init = &(struct clk_init_data){ 3260 .name = "gcc_ufs_phy_tx_symbol_0_clk", 3261 .ops = &clk_branch2_ops, 3262 }, 3263 }, 3264 }; 3265 3266 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 3267 .halt_reg = 0x45040, 3268 .halt_check = BRANCH_HALT_VOTED, 3269 .hwcg_reg = 0x45040, 3270 .hwcg_bit = 1, 3271 .clkr = { 3272 .enable_reg = 0x45040, 3273 .enable_mask = BIT(0), 3274 .hw.init = &(struct clk_init_data){ 3275 .name = "gcc_ufs_phy_unipro_core_clk", 3276 .parent_data = &(const struct clk_parent_data){ 3277 .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 3278 }, 3279 .num_parents = 1, 3280 .flags = CLK_SET_RATE_PARENT, 3281 .ops = &clk_branch2_ops, 3282 }, 3283 }, 3284 }; 3285 3286 static struct clk_branch gcc_usb30_prim_master_clk = { 3287 .halt_reg = 0x1a010, 3288 .halt_check = BRANCH_HALT, 3289 .clkr = { 3290 .enable_reg = 0x1a010, 3291 .enable_mask = BIT(0), 3292 .hw.init = &(struct clk_init_data){ 3293 .name = "gcc_usb30_prim_master_clk", 3294 .parent_data = &(const struct clk_parent_data){ 3295 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 3296 }, 3297 .num_parents = 1, 3298 .flags = CLK_SET_RATE_PARENT, 3299 .ops = &clk_branch2_ops, 3300 }, 3301 }, 3302 }; 3303 3304 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 3305 .halt_reg = 0x1a018, 3306 .halt_check = BRANCH_HALT, 3307 .clkr = { 3308 .enable_reg = 0x1a018, 3309 .enable_mask = BIT(0), 3310 .hw.init = &(struct clk_init_data){ 3311 .name = "gcc_usb30_prim_mock_utmi_clk", 3312 .parent_data = &(const struct clk_parent_data){ 3313 .hw = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 3314 }, 3315 .num_parents = 1, 3316 .flags = CLK_SET_RATE_PARENT, 3317 .ops = &clk_branch2_ops, 3318 }, 3319 }, 3320 }; 3321 3322 static struct clk_branch gcc_usb30_prim_sleep_clk = { 3323 .halt_reg = 0x1a014, 3324 .halt_check = BRANCH_HALT, 3325 .clkr = { 3326 .enable_reg = 0x1a014, 3327 .enable_mask = BIT(0), 3328 .hw.init = &(struct clk_init_data){ 3329 .name = "gcc_usb30_prim_sleep_clk", 3330 .ops = &clk_branch2_ops, 3331 }, 3332 }, 3333 }; 3334 3335 static struct clk_branch gcc_ufs_mem_clkref_clk = { 3336 .halt_reg = 0x8c000, 3337 .halt_check = BRANCH_HALT, 3338 .clkr = { 3339 .enable_reg = 0x8c000, 3340 .enable_mask = BIT(0), 3341 .hw.init = &(struct clk_init_data){ 3342 .name = "gcc_ufs_mem_clkref_clk", 3343 .ops = &clk_branch2_ops, 3344 }, 3345 }, 3346 }; 3347 3348 static struct clk_branch gcc_rx5_pcie_clkref_en_clk = { 3349 .halt_reg = 0x8c00c, 3350 .halt_check = BRANCH_HALT, 3351 .clkr = { 3352 .enable_reg = 0x8c00c, 3353 .enable_mask = BIT(0), 3354 .hw.init = &(struct clk_init_data){ 3355 .name = "gcc_rx5_pcie_clkref_en_clk", 3356 .ops = &clk_branch2_ops, 3357 }, 3358 }, 3359 }; 3360 3361 static struct clk_branch gcc_usb3_prim_clkref_clk = { 3362 .halt_reg = 0x8c010, 3363 .halt_check = BRANCH_HALT, 3364 .clkr = { 3365 .enable_reg = 0x8c010, 3366 .enable_mask = BIT(0), 3367 .hw.init = &(struct clk_init_data){ 3368 .name = "gcc_usb3_prim_clkref_clk", 3369 .ops = &clk_branch2_ops, 3370 }, 3371 }, 3372 }; 3373 3374 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3375 .halt_reg = 0x1a054, 3376 .halt_check = BRANCH_HALT, 3377 .clkr = { 3378 .enable_reg = 0x1a054, 3379 .enable_mask = BIT(0), 3380 .hw.init = &(struct clk_init_data){ 3381 .name = "gcc_usb3_prim_phy_com_aux_clk", 3382 .parent_data = &(const struct clk_parent_data){ 3383 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3384 }, 3385 .num_parents = 1, 3386 .flags = CLK_SET_RATE_PARENT, 3387 .ops = &clk_branch2_ops, 3388 }, 3389 }, 3390 }; 3391 3392 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3393 .halt_reg = 0x1a058, 3394 .halt_check = BRANCH_HALT_SKIP, 3395 .hwcg_reg = 0x1a058, 3396 .hwcg_bit = 1, 3397 .clkr = { 3398 .enable_reg = 0x1a058, 3399 .enable_mask = BIT(0), 3400 .hw.init = &(struct clk_init_data){ 3401 .name = "gcc_usb3_prim_phy_pipe_clk", 3402 .ops = &clk_branch2_ops, 3403 }, 3404 }, 3405 }; 3406 3407 static struct clk_branch gcc_vcodec0_axi_clk = { 3408 .halt_reg = 0x6e008, 3409 .halt_check = BRANCH_HALT, 3410 .clkr = { 3411 .enable_reg = 0x6e008, 3412 .enable_mask = BIT(0), 3413 .hw.init = &(struct clk_init_data){ 3414 .name = "gcc_vcodec0_axi_clk", 3415 .ops = &clk_branch2_ops, 3416 }, 3417 }, 3418 }; 3419 3420 static struct clk_branch gcc_venus_ahb_clk = { 3421 .halt_reg = 0x6e010, 3422 .halt_check = BRANCH_HALT, 3423 .clkr = { 3424 .enable_reg = 0x6e010, 3425 .enable_mask = BIT(0), 3426 .hw.init = &(struct clk_init_data){ 3427 .name = "gcc_venus_ahb_clk", 3428 .ops = &clk_branch2_ops, 3429 }, 3430 }, 3431 }; 3432 3433 static struct clk_branch gcc_venus_ctl_axi_clk = { 3434 .halt_reg = 0x6e004, 3435 .halt_check = BRANCH_HALT, 3436 .clkr = { 3437 .enable_reg = 0x6e004, 3438 .enable_mask = BIT(0), 3439 .hw.init = &(struct clk_init_data){ 3440 .name = "gcc_venus_ctl_axi_clk", 3441 .ops = &clk_branch2_ops, 3442 }, 3443 }, 3444 }; 3445 3446 static struct clk_branch gcc_video_ahb_clk = { 3447 .halt_reg = 0x17004, 3448 .halt_check = BRANCH_HALT_DELAY, 3449 .hwcg_reg = 0x17004, 3450 .hwcg_bit = 1, 3451 .clkr = { 3452 .enable_reg = 0x17004, 3453 .enable_mask = BIT(0), 3454 .hw.init = &(struct clk_init_data){ 3455 .name = "gcc_video_ahb_clk", 3456 .flags = CLK_IS_CRITICAL, 3457 .ops = &clk_branch2_ops, 3458 }, 3459 }, 3460 }; 3461 3462 static struct clk_branch gcc_video_axi0_clk = { 3463 .halt_reg = 0x1701c, 3464 .halt_check = BRANCH_HALT_VOTED, 3465 .hwcg_reg = 0x1701c, 3466 .hwcg_bit = 1, 3467 .clkr = { 3468 .enable_reg = 0x1701c, 3469 .enable_mask = BIT(0), 3470 .hw.init = &(struct clk_init_data){ 3471 .name = "gcc_video_axi0_clk", 3472 .ops = &clk_branch2_ops, 3473 }, 3474 }, 3475 }; 3476 3477 static struct clk_branch gcc_video_throttle_core_clk = { 3478 .halt_reg = 0x17068, 3479 .halt_check = BRANCH_HALT_VOTED, 3480 .hwcg_reg = 0x17068, 3481 .hwcg_bit = 1, 3482 .clkr = { 3483 .enable_reg = 0x79004, 3484 .enable_mask = BIT(28), 3485 .hw.init = &(struct clk_init_data){ 3486 .name = "gcc_video_throttle_core_clk", 3487 .ops = &clk_branch2_ops, 3488 }, 3489 }, 3490 }; 3491 3492 static struct clk_branch gcc_video_vcodec0_sys_clk = { 3493 .halt_reg = 0x580a4, 3494 .halt_check = BRANCH_HALT_VOTED, 3495 .hwcg_reg = 0x580a4, 3496 .hwcg_bit = 1, 3497 .clkr = { 3498 .enable_reg = 0x580a4, 3499 .enable_mask = BIT(0), 3500 .hw.init = &(struct clk_init_data){ 3501 .name = "gcc_video_vcodec0_sys_clk", 3502 .parent_data = &(const struct clk_parent_data){ 3503 .hw = &gcc_video_venus_clk_src.clkr.hw, 3504 }, 3505 .num_parents = 1, 3506 .flags = CLK_SET_RATE_PARENT, 3507 .ops = &clk_branch2_ops, 3508 }, 3509 }, 3510 }; 3511 3512 static struct clk_branch gcc_video_venus_ctl_clk = { 3513 .halt_reg = 0x5808c, 3514 .halt_check = BRANCH_HALT, 3515 .clkr = { 3516 .enable_reg = 0x5808c, 3517 .enable_mask = BIT(0), 3518 .hw.init = &(struct clk_init_data){ 3519 .name = "gcc_video_venus_ctl_clk", 3520 .parent_data = &(const struct clk_parent_data){ 3521 .hw = &gcc_video_venus_clk_src.clkr.hw, 3522 }, 3523 .num_parents = 1, 3524 .flags = CLK_SET_RATE_PARENT, 3525 .ops = &clk_branch2_ops, 3526 }, 3527 }, 3528 }; 3529 3530 static struct clk_branch gcc_video_xo_clk = { 3531 .halt_reg = 0x17024, 3532 .halt_check = BRANCH_HALT, 3533 .clkr = { 3534 .enable_reg = 0x17024, 3535 .enable_mask = BIT(0), 3536 .hw.init = &(struct clk_init_data){ 3537 .name = "gcc_video_xo_clk", 3538 .ops = &clk_branch2_ops, 3539 }, 3540 }, 3541 }; 3542 3543 static struct gdsc usb30_prim_gdsc = { 3544 .gdscr = 0x1a004, 3545 .pd = { 3546 .name = "usb30_prim_gdsc", 3547 }, 3548 .pwrsts = PWRSTS_OFF_ON, 3549 }; 3550 3551 static struct gdsc ufs_phy_gdsc = { 3552 .gdscr = 0x45004, 3553 .pd = { 3554 .name = "ufs_phy_gdsc", 3555 }, 3556 .pwrsts = PWRSTS_OFF_ON, 3557 }; 3558 3559 static struct gdsc camss_top_gdsc = { 3560 .gdscr = 0x58004, 3561 .pd = { 3562 .name = "camss_top_gdsc", 3563 }, 3564 .pwrsts = PWRSTS_OFF_ON, 3565 }; 3566 3567 static struct gdsc venus_gdsc = { 3568 .gdscr = 0x5807c, 3569 .pd = { 3570 .name = "venus_gdsc", 3571 }, 3572 .pwrsts = PWRSTS_OFF_ON, 3573 }; 3574 3575 static struct gdsc vcodec0_gdsc = { 3576 .gdscr = 0x58098, 3577 .pd = { 3578 .name = "vcodec0_gdsc", 3579 }, 3580 .pwrsts = PWRSTS_OFF_ON, 3581 .flags = HW_CTRL, 3582 }; 3583 3584 static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = { 3585 .gdscr = 0x7d074, 3586 .pd = { 3587 .name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc", 3588 }, 3589 .pwrsts = PWRSTS_OFF_ON, 3590 .flags = VOTABLE, 3591 }; 3592 3593 static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = { 3594 .gdscr = 0x7d078, 3595 .pd = { 3596 .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc", 3597 }, 3598 .pwrsts = PWRSTS_OFF_ON, 3599 .flags = VOTABLE, 3600 }; 3601 3602 static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = { 3603 .gdscr = 0x7d060, 3604 .pd = { 3605 .name = "hlos1_vote_turing_mmu_tbu1_gdsc", 3606 }, 3607 .pwrsts = PWRSTS_OFF_ON, 3608 .flags = VOTABLE, 3609 }; 3610 3611 static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { 3612 .gdscr = 0x7d07c, 3613 .pd = { 3614 .name = "hlos1_vote_turing_mmu_tbu0_gdsc", 3615 }, 3616 .pwrsts = PWRSTS_OFF_ON, 3617 .flags = VOTABLE, 3618 }; 3619 3620 static struct clk_regmap *gcc_sm6375_clocks[] = { 3621 [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr, 3622 [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr, 3623 [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr, 3624 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3625 [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, 3626 [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, 3627 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 3628 [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, 3629 [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, 3630 [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr, 3631 [GCC_CAMSS_CCI_0_CLK_SRC] = &gcc_camss_cci_0_clk_src.clkr, 3632 [GCC_CAMSS_CCI_1_CLK] = &gcc_camss_cci_1_clk.clkr, 3633 [GCC_CAMSS_CCI_1_CLK_SRC] = &gcc_camss_cci_1_clk_src.clkr, 3634 [GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr, 3635 [GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr, 3636 [GCC_CAMSS_CPHY_2_CLK] = &gcc_camss_cphy_2_clk.clkr, 3637 [GCC_CAMSS_CPHY_3_CLK] = &gcc_camss_cphy_3_clk.clkr, 3638 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 3639 [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr, 3640 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, 3641 [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr, 3642 [GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr, 3643 [GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr, 3644 [GCC_CAMSS_CSI3PHYTIMER_CLK] = &gcc_camss_csi3phytimer_clk.clkr, 3645 [GCC_CAMSS_CSI3PHYTIMER_CLK_SRC] = &gcc_camss_csi3phytimer_clk_src.clkr, 3646 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 3647 [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr, 3648 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 3649 [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr, 3650 [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, 3651 [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr, 3652 [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr, 3653 [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr, 3654 [GCC_CAMSS_MCLK4_CLK] = &gcc_camss_mclk4_clk.clkr, 3655 [GCC_CAMSS_MCLK4_CLK_SRC] = &gcc_camss_mclk4_clk_src.clkr, 3656 [GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr, 3657 [GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr, 3658 [GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr, 3659 [GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr, 3660 [GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr, 3661 [GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr, 3662 [GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr, 3663 [GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr, 3664 [GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr, 3665 [GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr, 3666 [GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr, 3667 [GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr, 3668 [GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr, 3669 [GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr, 3670 [GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr, 3671 [GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr, 3672 [GCC_CAMSS_TFE_2_CLK] = &gcc_camss_tfe_2_clk.clkr, 3673 [GCC_CAMSS_TFE_2_CLK_SRC] = &gcc_camss_tfe_2_clk_src.clkr, 3674 [GCC_CAMSS_TFE_2_CPHY_RX_CLK] = &gcc_camss_tfe_2_cphy_rx_clk.clkr, 3675 [GCC_CAMSS_TFE_2_CSID_CLK] = &gcc_camss_tfe_2_csid_clk.clkr, 3676 [GCC_CAMSS_TFE_2_CSID_CLK_SRC] = &gcc_camss_tfe_2_csid_clk_src.clkr, 3677 [GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr, 3678 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 3679 [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, 3680 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3681 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, 3682 [GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr, 3683 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, 3684 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 3685 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 3686 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3687 [GCC_DISP_SLEEP_CLK] = &gcc_disp_sleep_clk.clkr, 3688 [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, 3689 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3690 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3691 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3692 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3693 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3694 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3695 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 3696 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3697 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3698 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3699 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3700 [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, 3701 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3702 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3703 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3704 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3705 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3706 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3707 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3708 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3709 [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr, 3710 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3711 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 3712 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 3713 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3714 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3715 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3716 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3717 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3718 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3719 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3720 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3721 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3722 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3723 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3724 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3725 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3726 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3727 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3728 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3729 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3730 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3731 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3732 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3733 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3734 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3735 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3736 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3737 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3738 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3739 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3740 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3741 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3742 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3743 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3744 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3745 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 3746 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 3747 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 3748 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3749 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3750 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3751 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 3752 [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, 3753 [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, 3754 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3755 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3756 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3757 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3758 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3759 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3760 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3761 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3762 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3763 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3764 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 3765 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3766 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3767 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3768 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3769 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3770 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3771 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 3772 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3773 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3774 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3775 [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr, 3776 [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr, 3777 [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr, 3778 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 3779 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3780 [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, 3781 [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr, 3782 [GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr, 3783 [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr, 3784 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 3785 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, 3786 [GCC_RX5_PCIE_CLKREF_EN_CLK] = &gcc_rx5_pcie_clkref_en_clk.clkr, 3787 [GPLL0] = &gpll0.clkr, 3788 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 3789 [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr, 3790 [GPLL1] = &gpll1.clkr, 3791 [GPLL10] = &gpll10.clkr, 3792 [GPLL11] = &gpll11.clkr, 3793 [GPLL3] = &gpll3.clkr, 3794 [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr, 3795 [GPLL4] = &gpll4.clkr, 3796 [GPLL5] = &gpll5.clkr, 3797 [GPLL6] = &gpll6.clkr, 3798 [GPLL6_OUT_EVEN] = &gpll6_out_even.clkr, 3799 [GPLL7] = &gpll7.clkr, 3800 [GPLL8] = &gpll8.clkr, 3801 [GPLL8_OUT_EVEN] = &gpll8_out_even.clkr, 3802 [GPLL9] = &gpll9.clkr, 3803 [GPLL9_OUT_MAIN] = &gpll9_out_main.clkr, 3804 }; 3805 3806 static const struct qcom_reset_map gcc_sm6375_resets[] = { 3807 [GCC_MMSS_BCR] = { 0x17000 }, 3808 [GCC_USB30_PRIM_BCR] = { 0x1a000 }, 3809 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, 3810 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1b020 }, 3811 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, 3812 [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, 3813 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, 3814 [GCC_SDCC2_BCR] = { 0x1e000 }, 3815 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 }, 3816 [GCC_PDM_BCR] = { 0x20000 }, 3817 [GCC_GPU_BCR] = { 0x36000 }, 3818 [GCC_SDCC1_BCR] = { 0x38000 }, 3819 [GCC_UFS_PHY_BCR] = { 0x45000 }, 3820 [GCC_CAMSS_TFE_BCR] = { 0x52000 }, 3821 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x53000 }, 3822 [GCC_CAMSS_OPE_BCR] = { 0x55000 }, 3823 [GCC_CAMSS_TOP_BCR] = { 0x58000 }, 3824 [GCC_VENUS_BCR] = { 0x58078 }, 3825 [GCC_VCODEC0_BCR] = { 0x58094 }, 3826 [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 }, 3827 }; 3828 3829 3830 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3831 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3832 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3833 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3834 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3835 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3836 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3837 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3838 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3839 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 3840 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3841 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3842 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3843 }; 3844 3845 static struct gdsc *gcc_sm6375_gdscs[] = { 3846 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3847 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3848 [CAMSS_TOP_GDSC] = &camss_top_gdsc, 3849 [VENUS_GDSC] = &venus_gdsc, 3850 [VCODEC0_GDSC] = &vcodec0_gdsc, 3851 [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc, 3852 [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc, 3853 [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc, 3854 [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, 3855 }; 3856 3857 static const struct regmap_config gcc_sm6375_regmap_config = { 3858 .reg_bits = 32, 3859 .reg_stride = 4, 3860 .val_bits = 32, 3861 .max_register = 0xc7000, 3862 .fast_io = true, 3863 }; 3864 3865 static const struct qcom_cc_desc gcc_sm6375_desc = { 3866 .config = &gcc_sm6375_regmap_config, 3867 .clks = gcc_sm6375_clocks, 3868 .num_clks = ARRAY_SIZE(gcc_sm6375_clocks), 3869 .resets = gcc_sm6375_resets, 3870 .num_resets = ARRAY_SIZE(gcc_sm6375_resets), 3871 .gdscs = gcc_sm6375_gdscs, 3872 .num_gdscs = ARRAY_SIZE(gcc_sm6375_gdscs), 3873 }; 3874 3875 static const struct of_device_id gcc_sm6375_match_table[] = { 3876 { .compatible = "qcom,sm6375-gcc" }, 3877 { } 3878 }; 3879 MODULE_DEVICE_TABLE(of, gcc_sm6375_match_table); 3880 3881 static int gcc_sm6375_probe(struct platform_device *pdev) 3882 { 3883 struct regmap *regmap; 3884 int ret; 3885 3886 regmap = qcom_cc_map(pdev, &gcc_sm6375_desc); 3887 if (IS_ERR(regmap)) 3888 return PTR_ERR(regmap); 3889 3890 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); 3891 if (ret) 3892 return ret; 3893 3894 /* 3895 * Keep the following clocks always on: 3896 * GCC_CAMERA_XO_CLK, GCC_CPUSS_GNOC_CLK, GCC_DISP_XO_CLK 3897 */ 3898 regmap_update_bits(regmap, 0x17028, BIT(0), BIT(0)); 3899 regmap_update_bits(regmap, 0x2b004, BIT(0), BIT(0)); 3900 regmap_update_bits(regmap, 0x1702c, BIT(0), BIT(0)); 3901 3902 clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config); 3903 clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config); 3904 clk_lucid_pll_configure(&gpll8, regmap, &gpll8_config); 3905 clk_zonda_pll_configure(&gpll9, regmap, &gpll9_config); 3906 3907 return qcom_cc_really_probe(pdev, &gcc_sm6375_desc, regmap); 3908 } 3909 3910 static struct platform_driver gcc_sm6375_driver = { 3911 .probe = gcc_sm6375_probe, 3912 .driver = { 3913 .name = "gcc-sm6375", 3914 .of_match_table = gcc_sm6375_match_table, 3915 }, 3916 }; 3917 3918 static int __init gcc_sm6375_init(void) 3919 { 3920 return platform_driver_register(&gcc_sm6375_driver); 3921 } 3922 subsys_initcall(gcc_sm6375_init); 3923 3924 static void __exit gcc_sm6375_exit(void) 3925 { 3926 platform_driver_unregister(&gcc_sm6375_driver); 3927 } 3928 module_exit(gcc_sm6375_exit); 3929 3930 MODULE_DESCRIPTION("QTI GCC SM6375 Driver"); 3931 MODULE_LICENSE("GPL"); 3932