1184fdd87SKonrad Dybcio // SPDX-License-Identifier: GPL-2.0-only 2184fdd87SKonrad Dybcio /* 3184fdd87SKonrad Dybcio * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4184fdd87SKonrad Dybcio * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> 5184fdd87SKonrad Dybcio */ 6184fdd87SKonrad Dybcio 7184fdd87SKonrad Dybcio #include <linux/clk-provider.h> 8184fdd87SKonrad Dybcio #include <linux/module.h> 9184fdd87SKonrad Dybcio #include <linux/of_device.h> 10184fdd87SKonrad Dybcio #include <linux/regmap.h> 11184fdd87SKonrad Dybcio 12184fdd87SKonrad Dybcio #include <dt-bindings/clock/qcom,sm6375-gcc.h> 13184fdd87SKonrad Dybcio 14184fdd87SKonrad Dybcio #include "clk-alpha-pll.h" 15184fdd87SKonrad Dybcio #include "clk-branch.h" 16184fdd87SKonrad Dybcio #include "clk-rcg.h" 17184fdd87SKonrad Dybcio #include "clk-regmap.h" 18184fdd87SKonrad Dybcio #include "clk-regmap-divider.h" 19184fdd87SKonrad Dybcio #include "clk-regmap-mux.h" 20184fdd87SKonrad Dybcio #include "clk-regmap-phy-mux.h" 21184fdd87SKonrad Dybcio #include "gdsc.h" 22184fdd87SKonrad Dybcio #include "reset.h" 23184fdd87SKonrad Dybcio 24184fdd87SKonrad Dybcio enum { 25184fdd87SKonrad Dybcio DT_BI_TCXO, 26184fdd87SKonrad Dybcio DT_BI_TCXO_AO, 27184fdd87SKonrad Dybcio DT_SLEEP_CLK 28184fdd87SKonrad Dybcio }; 29184fdd87SKonrad Dybcio 30184fdd87SKonrad Dybcio enum { 31184fdd87SKonrad Dybcio P_BI_TCXO, 32184fdd87SKonrad Dybcio P_GPLL0_OUT_EVEN, 33184fdd87SKonrad Dybcio P_GPLL0_OUT_MAIN, 34184fdd87SKonrad Dybcio P_GPLL0_OUT_ODD, 35184fdd87SKonrad Dybcio P_GPLL10_OUT_EVEN, 36184fdd87SKonrad Dybcio P_GPLL11_OUT_EVEN, 37184fdd87SKonrad Dybcio P_GPLL11_OUT_ODD, 38184fdd87SKonrad Dybcio P_GPLL3_OUT_EVEN, 39184fdd87SKonrad Dybcio P_GPLL3_OUT_MAIN, 40184fdd87SKonrad Dybcio P_GPLL4_OUT_EVEN, 41184fdd87SKonrad Dybcio P_GPLL5_OUT_EVEN, 42184fdd87SKonrad Dybcio P_GPLL6_OUT_EVEN, 43184fdd87SKonrad Dybcio P_GPLL6_OUT_MAIN, 44184fdd87SKonrad Dybcio P_GPLL7_OUT_EVEN, 45184fdd87SKonrad Dybcio P_GPLL8_OUT_EVEN, 46184fdd87SKonrad Dybcio P_GPLL8_OUT_MAIN, 47184fdd87SKonrad Dybcio P_GPLL9_OUT_EARLY, 48184fdd87SKonrad Dybcio P_GPLL9_OUT_MAIN, 49184fdd87SKonrad Dybcio P_SLEEP_CLK, 50184fdd87SKonrad Dybcio }; 51184fdd87SKonrad Dybcio 52184fdd87SKonrad Dybcio static struct pll_vco lucid_vco[] = { 53184fdd87SKonrad Dybcio { 249600000, 2000000000, 0 }, 54184fdd87SKonrad Dybcio }; 55184fdd87SKonrad Dybcio 56184fdd87SKonrad Dybcio static struct pll_vco zonda_vco[] = { 5739bc9b58SStephen Boyd { 595200000, 3600000000UL, 0 }, 58184fdd87SKonrad Dybcio }; 59184fdd87SKonrad Dybcio 60184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll0 = { 61184fdd87SKonrad Dybcio .offset = 0x0, 62184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 63184fdd87SKonrad Dybcio .clkr = { 64184fdd87SKonrad Dybcio .enable_reg = 0x79000, 65184fdd87SKonrad Dybcio .enable_mask = BIT(0), 66184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 67184fdd87SKonrad Dybcio .name = "gpll0", 68184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 69184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 70184fdd87SKonrad Dybcio }, 71184fdd87SKonrad Dybcio .num_parents = 1, 72184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_fixed_lucid_ops, 73184fdd87SKonrad Dybcio }, 74184fdd87SKonrad Dybcio }, 75184fdd87SKonrad Dybcio }; 76184fdd87SKonrad Dybcio 77184fdd87SKonrad Dybcio static const struct clk_div_table post_div_table_gpll0_out_even[] = { 78184fdd87SKonrad Dybcio { 0x1, 2 }, 79184fdd87SKonrad Dybcio { } 80184fdd87SKonrad Dybcio }; 81184fdd87SKonrad Dybcio 82184fdd87SKonrad Dybcio static struct clk_alpha_pll_postdiv gpll0_out_even = { 83184fdd87SKonrad Dybcio .offset = 0x0, 84184fdd87SKonrad Dybcio .post_div_shift = 8, 85184fdd87SKonrad Dybcio .post_div_table = post_div_table_gpll0_out_even, 86184fdd87SKonrad Dybcio .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even), 87184fdd87SKonrad Dybcio .width = 4, 88184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 89184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 90184fdd87SKonrad Dybcio .name = "gpll0_out_even", 91184fdd87SKonrad Dybcio .parent_hws = (const struct clk_hw*[]){ 92184fdd87SKonrad Dybcio &gpll0.clkr.hw, 93184fdd87SKonrad Dybcio }, 94184fdd87SKonrad Dybcio .num_parents = 1, 95184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_postdiv_lucid_ops, 96184fdd87SKonrad Dybcio }, 97184fdd87SKonrad Dybcio }; 98184fdd87SKonrad Dybcio 99184fdd87SKonrad Dybcio static const struct clk_div_table post_div_table_gpll0_out_odd[] = { 100184fdd87SKonrad Dybcio { 0x3, 3 }, 101184fdd87SKonrad Dybcio { } 102184fdd87SKonrad Dybcio }; 103184fdd87SKonrad Dybcio 104184fdd87SKonrad Dybcio static struct clk_alpha_pll_postdiv gpll0_out_odd = { 105184fdd87SKonrad Dybcio .offset = 0x0, 106184fdd87SKonrad Dybcio .post_div_shift = 12, 107184fdd87SKonrad Dybcio .post_div_table = post_div_table_gpll0_out_odd, 108184fdd87SKonrad Dybcio .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_odd), 109184fdd87SKonrad Dybcio .width = 4, 110184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 111184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 112184fdd87SKonrad Dybcio .name = "gpll0_out_odd", 113184fdd87SKonrad Dybcio .parent_hws = (const struct clk_hw*[]){ 114184fdd87SKonrad Dybcio &gpll0.clkr.hw, 115184fdd87SKonrad Dybcio }, 116184fdd87SKonrad Dybcio .num_parents = 1, 117184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_postdiv_lucid_ops, 118184fdd87SKonrad Dybcio }, 119184fdd87SKonrad Dybcio }; 120184fdd87SKonrad Dybcio 121184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll1 = { 122184fdd87SKonrad Dybcio .offset = 0x1000, 123184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 124184fdd87SKonrad Dybcio .clkr = { 125184fdd87SKonrad Dybcio .enable_reg = 0x79000, 126184fdd87SKonrad Dybcio .enable_mask = BIT(1), 127184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 128184fdd87SKonrad Dybcio .name = "gpll1", 129184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 130184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 131184fdd87SKonrad Dybcio }, 132184fdd87SKonrad Dybcio .num_parents = 1, 133184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_lucid_ops, 134184fdd87SKonrad Dybcio }, 135184fdd87SKonrad Dybcio }, 136184fdd87SKonrad Dybcio }; 137184fdd87SKonrad Dybcio 138184fdd87SKonrad Dybcio /* 1152MHz Configuration */ 139184fdd87SKonrad Dybcio static const struct alpha_pll_config gpll10_config = { 140184fdd87SKonrad Dybcio .l = 0x3c, 141184fdd87SKonrad Dybcio .alpha = 0x0, 142184fdd87SKonrad Dybcio .config_ctl_val = 0x20485699, 143184fdd87SKonrad Dybcio .config_ctl_hi_val = 0x00002261, 144184fdd87SKonrad Dybcio .config_ctl_hi1_val = 0x329a299c, 145184fdd87SKonrad Dybcio .user_ctl_val = 0x00000001, 146184fdd87SKonrad Dybcio .user_ctl_hi_val = 0x00000805, 147184fdd87SKonrad Dybcio .user_ctl_hi1_val = 0x00000000, 148184fdd87SKonrad Dybcio }; 149184fdd87SKonrad Dybcio 150184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll10 = { 151184fdd87SKonrad Dybcio .offset = 0xa000, 152184fdd87SKonrad Dybcio .vco_table = lucid_vco, 153184fdd87SKonrad Dybcio .num_vco = ARRAY_SIZE(lucid_vco), 154184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 155184fdd87SKonrad Dybcio .flags = SUPPORTS_FSM_LEGACY_MODE, 156184fdd87SKonrad Dybcio .clkr = { 157184fdd87SKonrad Dybcio .enable_reg = 0x79000, 158184fdd87SKonrad Dybcio .enable_mask = BIT(10), 159184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 160184fdd87SKonrad Dybcio .name = "gpll10", 161184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 162184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 163184fdd87SKonrad Dybcio }, 164184fdd87SKonrad Dybcio .num_parents = 1, 165184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_fixed_lucid_ops, 166184fdd87SKonrad Dybcio }, 167184fdd87SKonrad Dybcio }, 168184fdd87SKonrad Dybcio }; 169184fdd87SKonrad Dybcio 170184fdd87SKonrad Dybcio /* 532MHz Configuration */ 171184fdd87SKonrad Dybcio static const struct alpha_pll_config gpll11_config = { 172184fdd87SKonrad Dybcio .l = 0x1b, 173184fdd87SKonrad Dybcio .alpha = 0xb555, 174184fdd87SKonrad Dybcio .config_ctl_val = 0x20485699, 175184fdd87SKonrad Dybcio .config_ctl_hi_val = 0x00002261, 176184fdd87SKonrad Dybcio .config_ctl_hi1_val = 0x329a299c, 177184fdd87SKonrad Dybcio .user_ctl_val = 0x00000001, 178184fdd87SKonrad Dybcio .user_ctl_hi_val = 0x00000805, 179184fdd87SKonrad Dybcio .user_ctl_hi1_val = 0x00000000, 180184fdd87SKonrad Dybcio }; 181184fdd87SKonrad Dybcio 182184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll11 = { 183184fdd87SKonrad Dybcio .offset = 0xb000, 184184fdd87SKonrad Dybcio .vco_table = lucid_vco, 185184fdd87SKonrad Dybcio .num_vco = ARRAY_SIZE(lucid_vco), 186184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 187184fdd87SKonrad Dybcio .flags = SUPPORTS_FSM_LEGACY_MODE, 188184fdd87SKonrad Dybcio .clkr = { 189184fdd87SKonrad Dybcio .enable_reg = 0x79000, 190184fdd87SKonrad Dybcio .enable_mask = BIT(11), 191184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 192184fdd87SKonrad Dybcio .name = "gpll11", 193184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 194184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 195184fdd87SKonrad Dybcio }, 196184fdd87SKonrad Dybcio .num_parents = 1, 197184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_lucid_ops, 198184fdd87SKonrad Dybcio }, 199184fdd87SKonrad Dybcio }, 200184fdd87SKonrad Dybcio }; 201184fdd87SKonrad Dybcio 202184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll3 = { 203184fdd87SKonrad Dybcio .offset = 0x3000, 204184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 205184fdd87SKonrad Dybcio .clkr = { 206184fdd87SKonrad Dybcio .enable_reg = 0x79000, 207184fdd87SKonrad Dybcio .enable_mask = BIT(3), 208184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 209184fdd87SKonrad Dybcio .name = "gpll3", 210184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 211184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 212184fdd87SKonrad Dybcio }, 213184fdd87SKonrad Dybcio .num_parents = 1, 214184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_fixed_lucid_ops, 215184fdd87SKonrad Dybcio }, 216184fdd87SKonrad Dybcio }, 217184fdd87SKonrad Dybcio }; 218184fdd87SKonrad Dybcio 219184fdd87SKonrad Dybcio static const struct clk_div_table post_div_table_gpll3_out_even[] = { 220184fdd87SKonrad Dybcio { 0x1, 2 }, 221184fdd87SKonrad Dybcio { } 222184fdd87SKonrad Dybcio }; 223184fdd87SKonrad Dybcio 224184fdd87SKonrad Dybcio static struct clk_alpha_pll_postdiv gpll3_out_even = { 225184fdd87SKonrad Dybcio .offset = 0x3000, 226184fdd87SKonrad Dybcio .post_div_shift = 8, 227184fdd87SKonrad Dybcio .post_div_table = post_div_table_gpll3_out_even, 228184fdd87SKonrad Dybcio .num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_even), 229184fdd87SKonrad Dybcio .width = 4, 230184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 231184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 232184fdd87SKonrad Dybcio .name = "gpll3_out_even", 233184fdd87SKonrad Dybcio .parent_hws = (const struct clk_hw*[]){ 234184fdd87SKonrad Dybcio &gpll3.clkr.hw, 235184fdd87SKonrad Dybcio }, 236184fdd87SKonrad Dybcio .num_parents = 1, 237184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_postdiv_lucid_ops, 238184fdd87SKonrad Dybcio }, 239184fdd87SKonrad Dybcio }; 240184fdd87SKonrad Dybcio 241184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll4 = { 242184fdd87SKonrad Dybcio .offset = 0x4000, 243184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 244184fdd87SKonrad Dybcio .clkr = { 245184fdd87SKonrad Dybcio .enable_reg = 0x79000, 246184fdd87SKonrad Dybcio .enable_mask = BIT(4), 247184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 248184fdd87SKonrad Dybcio .name = "gpll4", 249184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 250184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 251184fdd87SKonrad Dybcio }, 252184fdd87SKonrad Dybcio .num_parents = 1, 253184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_fixed_lucid_ops, 254184fdd87SKonrad Dybcio }, 255184fdd87SKonrad Dybcio }, 256184fdd87SKonrad Dybcio }; 257184fdd87SKonrad Dybcio 258184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll5 = { 259184fdd87SKonrad Dybcio .offset = 0x5000, 260184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 261184fdd87SKonrad Dybcio .clkr = { 262184fdd87SKonrad Dybcio .enable_reg = 0x79000, 263184fdd87SKonrad Dybcio .enable_mask = BIT(5), 264184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 265184fdd87SKonrad Dybcio .name = "gpll5", 266184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 267184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 268184fdd87SKonrad Dybcio }, 269184fdd87SKonrad Dybcio .num_parents = 1, 270184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_fixed_lucid_ops, 271184fdd87SKonrad Dybcio }, 272184fdd87SKonrad Dybcio }, 273184fdd87SKonrad Dybcio }; 274184fdd87SKonrad Dybcio 275184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll6 = { 276184fdd87SKonrad Dybcio .offset = 0x6000, 277184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 278184fdd87SKonrad Dybcio .clkr = { 279184fdd87SKonrad Dybcio .enable_reg = 0x79000, 280184fdd87SKonrad Dybcio .enable_mask = BIT(6), 281184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 282184fdd87SKonrad Dybcio .name = "gpll6", 283184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 284184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 285184fdd87SKonrad Dybcio }, 286184fdd87SKonrad Dybcio .num_parents = 1, 287184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_fixed_lucid_ops, 288184fdd87SKonrad Dybcio }, 289184fdd87SKonrad Dybcio }, 290184fdd87SKonrad Dybcio }; 291184fdd87SKonrad Dybcio 292184fdd87SKonrad Dybcio static const struct clk_div_table post_div_table_gpll6_out_even[] = { 293184fdd87SKonrad Dybcio { 0x1, 2 }, 294184fdd87SKonrad Dybcio { } 295184fdd87SKonrad Dybcio }; 296184fdd87SKonrad Dybcio 297184fdd87SKonrad Dybcio static struct clk_alpha_pll_postdiv gpll6_out_even = { 298184fdd87SKonrad Dybcio .offset = 0x6000, 299184fdd87SKonrad Dybcio .post_div_shift = 8, 300184fdd87SKonrad Dybcio .post_div_table = post_div_table_gpll6_out_even, 301184fdd87SKonrad Dybcio .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_even), 302184fdd87SKonrad Dybcio .width = 4, 303184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 304184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 305184fdd87SKonrad Dybcio .name = "gpll6_out_even", 306184fdd87SKonrad Dybcio .parent_hws = (const struct clk_hw*[]){ 307184fdd87SKonrad Dybcio &gpll6.clkr.hw, 308184fdd87SKonrad Dybcio }, 309184fdd87SKonrad Dybcio .num_parents = 1, 310184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_postdiv_lucid_ops, 311184fdd87SKonrad Dybcio }, 312184fdd87SKonrad Dybcio }; 313184fdd87SKonrad Dybcio 314184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll7 = { 315184fdd87SKonrad Dybcio .offset = 0x7000, 316184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 317184fdd87SKonrad Dybcio .clkr = { 318184fdd87SKonrad Dybcio .enable_reg = 0x79000, 319184fdd87SKonrad Dybcio .enable_mask = BIT(7), 320184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 321184fdd87SKonrad Dybcio .name = "gpll7", 322184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 323184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 324184fdd87SKonrad Dybcio }, 325184fdd87SKonrad Dybcio .num_parents = 1, 326184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_fixed_lucid_ops, 327184fdd87SKonrad Dybcio }, 328184fdd87SKonrad Dybcio }, 329184fdd87SKonrad Dybcio }; 330184fdd87SKonrad Dybcio 331184fdd87SKonrad Dybcio /* 400MHz Configuration */ 332184fdd87SKonrad Dybcio static const struct alpha_pll_config gpll8_config = { 333184fdd87SKonrad Dybcio .l = 0x14, 334184fdd87SKonrad Dybcio .alpha = 0xd555, 335184fdd87SKonrad Dybcio .config_ctl_val = 0x20485699, 336184fdd87SKonrad Dybcio .config_ctl_hi_val = 0x00002261, 337184fdd87SKonrad Dybcio .config_ctl_hi1_val = 0x329a299c, 338184fdd87SKonrad Dybcio .user_ctl_val = 0x00000101, 339184fdd87SKonrad Dybcio .user_ctl_hi_val = 0x00000805, 340184fdd87SKonrad Dybcio .user_ctl_hi1_val = 0x00000000, 341184fdd87SKonrad Dybcio }; 342184fdd87SKonrad Dybcio 343184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll8 = { 344184fdd87SKonrad Dybcio .offset = 0x8000, 345184fdd87SKonrad Dybcio .vco_table = lucid_vco, 346184fdd87SKonrad Dybcio .num_vco = ARRAY_SIZE(lucid_vco), 347184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 348184fdd87SKonrad Dybcio .flags = SUPPORTS_FSM_LEGACY_MODE, 349184fdd87SKonrad Dybcio .clkr = { 350184fdd87SKonrad Dybcio .enable_reg = 0x79000, 351184fdd87SKonrad Dybcio .enable_mask = BIT(8), 352184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 353184fdd87SKonrad Dybcio .name = "gpll8", 354184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 355184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 356184fdd87SKonrad Dybcio }, 357184fdd87SKonrad Dybcio .num_parents = 1, 358184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_lucid_ops, 359184fdd87SKonrad Dybcio }, 360184fdd87SKonrad Dybcio }, 361184fdd87SKonrad Dybcio }; 362184fdd87SKonrad Dybcio 363184fdd87SKonrad Dybcio static const struct clk_div_table post_div_table_gpll8_out_even[] = { 364184fdd87SKonrad Dybcio { 0x1, 2 }, 365184fdd87SKonrad Dybcio { } 366184fdd87SKonrad Dybcio }; 367184fdd87SKonrad Dybcio 368184fdd87SKonrad Dybcio static struct clk_alpha_pll_postdiv gpll8_out_even = { 369184fdd87SKonrad Dybcio .offset = 0x8000, 370184fdd87SKonrad Dybcio .post_div_shift = 8, 371184fdd87SKonrad Dybcio .post_div_table = post_div_table_gpll8_out_even, 372184fdd87SKonrad Dybcio .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_even), 373184fdd87SKonrad Dybcio .width = 4, 374184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 375184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 376184fdd87SKonrad Dybcio .name = "gpll8_out_even", 377184fdd87SKonrad Dybcio .parent_hws = (const struct clk_hw*[]){ 378184fdd87SKonrad Dybcio &gpll8.clkr.hw, 379184fdd87SKonrad Dybcio }, 380184fdd87SKonrad Dybcio .num_parents = 1, 381184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 382184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_postdiv_lucid_ops, 383184fdd87SKonrad Dybcio }, 384184fdd87SKonrad Dybcio }; 385184fdd87SKonrad Dybcio 386184fdd87SKonrad Dybcio /* 1440MHz Configuration */ 387184fdd87SKonrad Dybcio static const struct alpha_pll_config gpll9_config = { 388184fdd87SKonrad Dybcio .l = 0x4b, 389184fdd87SKonrad Dybcio .alpha = 0x0, 390184fdd87SKonrad Dybcio .config_ctl_val = 0x08200800, 391184fdd87SKonrad Dybcio .config_ctl_hi_val = 0x05022011, 392184fdd87SKonrad Dybcio .config_ctl_hi1_val = 0x08000000, 393184fdd87SKonrad Dybcio .user_ctl_val = 0x00000301, 394184fdd87SKonrad Dybcio }; 395184fdd87SKonrad Dybcio 396184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll9 = { 397184fdd87SKonrad Dybcio .offset = 0x9000, 398184fdd87SKonrad Dybcio .vco_table = zonda_vco, 399184fdd87SKonrad Dybcio .num_vco = ARRAY_SIZE(zonda_vco), 400184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], 401184fdd87SKonrad Dybcio .clkr = { 402184fdd87SKonrad Dybcio .enable_reg = 0x79000, 403184fdd87SKonrad Dybcio .enable_mask = BIT(9), 404184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 405184fdd87SKonrad Dybcio .name = "gpll9", 406184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 407184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 408184fdd87SKonrad Dybcio }, 409184fdd87SKonrad Dybcio .num_parents = 1, 410184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_zonda_ops, 411184fdd87SKonrad Dybcio }, 412184fdd87SKonrad Dybcio }, 413184fdd87SKonrad Dybcio }; 414184fdd87SKonrad Dybcio 415184fdd87SKonrad Dybcio static const struct clk_div_table post_div_table_gpll9_out_main[] = { 416184fdd87SKonrad Dybcio { 0x3, 4 }, 417184fdd87SKonrad Dybcio { } 418184fdd87SKonrad Dybcio }; 419184fdd87SKonrad Dybcio 420184fdd87SKonrad Dybcio static struct clk_alpha_pll_postdiv gpll9_out_main = { 421184fdd87SKonrad Dybcio .offset = 0x9000, 422184fdd87SKonrad Dybcio .post_div_shift = 8, 423184fdd87SKonrad Dybcio .post_div_table = post_div_table_gpll9_out_main, 424184fdd87SKonrad Dybcio .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main), 425184fdd87SKonrad Dybcio .width = 2, 426184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], 427184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 428184fdd87SKonrad Dybcio .name = "gpll9_out_main", 429184fdd87SKonrad Dybcio .parent_hws = (const struct clk_hw*[]){ 430184fdd87SKonrad Dybcio &gpll9.clkr.hw, 431184fdd87SKonrad Dybcio }, 432184fdd87SKonrad Dybcio .num_parents = 1, 433184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 434184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_postdiv_zonda_ops, 435184fdd87SKonrad Dybcio }, 436184fdd87SKonrad Dybcio }; 437184fdd87SKonrad Dybcio 438184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_0[] = { 439184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 440184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 441184fdd87SKonrad Dybcio { P_GPLL0_OUT_EVEN, 2 }, 442184fdd87SKonrad Dybcio }; 443184fdd87SKonrad Dybcio 444184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_0[] = { 445184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 446184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 447184fdd87SKonrad Dybcio { .hw = &gpll0_out_even.clkr.hw }, 448184fdd87SKonrad Dybcio }; 449184fdd87SKonrad Dybcio 450184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_1[] = { 451184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 452184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 453184fdd87SKonrad Dybcio { P_GPLL0_OUT_EVEN, 2 }, 454184fdd87SKonrad Dybcio { P_GPLL6_OUT_EVEN, 4 }, 455184fdd87SKonrad Dybcio }; 456184fdd87SKonrad Dybcio 457184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_1[] = { 458184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 459184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 460184fdd87SKonrad Dybcio { .hw = &gpll0_out_even.clkr.hw }, 461184fdd87SKonrad Dybcio { .hw = &gpll6_out_even.clkr.hw }, 462184fdd87SKonrad Dybcio }; 463184fdd87SKonrad Dybcio 464184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_2[] = { 465184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 466184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 467184fdd87SKonrad Dybcio { P_GPLL0_OUT_EVEN, 2 }, 468184fdd87SKonrad Dybcio { P_GPLL0_OUT_ODD, 4 }, 469184fdd87SKonrad Dybcio }; 470184fdd87SKonrad Dybcio 471184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_2[] = { 472184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 473184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 474184fdd87SKonrad Dybcio { .hw = &gpll0_out_even.clkr.hw }, 475184fdd87SKonrad Dybcio { .hw = &gpll0_out_odd.clkr.hw }, 476184fdd87SKonrad Dybcio }; 477184fdd87SKonrad Dybcio 478184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_2_ao[] = { 479184fdd87SKonrad Dybcio { .index = DT_BI_TCXO_AO }, 480184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 481184fdd87SKonrad Dybcio { .hw = &gpll0_out_even.clkr.hw }, 482184fdd87SKonrad Dybcio { .hw = &gpll0_out_odd.clkr.hw }, 483184fdd87SKonrad Dybcio }; 484184fdd87SKonrad Dybcio 485184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_3[] = { 486184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 487184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 488184fdd87SKonrad Dybcio { P_GPLL9_OUT_EARLY, 2 }, 489184fdd87SKonrad Dybcio { P_GPLL10_OUT_EVEN, 3 }, 490184fdd87SKonrad Dybcio { P_GPLL9_OUT_MAIN, 4 }, 491184fdd87SKonrad Dybcio { P_GPLL3_OUT_EVEN, 6 }, 492184fdd87SKonrad Dybcio }; 493184fdd87SKonrad Dybcio 494184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_3[] = { 495184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 496184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 497184fdd87SKonrad Dybcio { .hw = &gpll9.clkr.hw }, 498184fdd87SKonrad Dybcio { .hw = &gpll10.clkr.hw }, 499184fdd87SKonrad Dybcio { .hw = &gpll9_out_main.clkr.hw }, 500184fdd87SKonrad Dybcio { .hw = &gpll3_out_even.clkr.hw }, 501184fdd87SKonrad Dybcio }; 502184fdd87SKonrad Dybcio 503184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_4[] = { 504184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 505184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 506184fdd87SKonrad Dybcio { P_GPLL0_OUT_EVEN, 2 }, 507184fdd87SKonrad Dybcio { P_GPLL0_OUT_ODD, 4 }, 508184fdd87SKonrad Dybcio { P_GPLL4_OUT_EVEN, 5 }, 509184fdd87SKonrad Dybcio { P_GPLL3_OUT_EVEN, 6 }, 510184fdd87SKonrad Dybcio }; 511184fdd87SKonrad Dybcio 512184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_4[] = { 513184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 514184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 515184fdd87SKonrad Dybcio { .hw = &gpll0_out_even.clkr.hw }, 516184fdd87SKonrad Dybcio { .hw = &gpll0_out_odd.clkr.hw }, 517184fdd87SKonrad Dybcio { .hw = &gpll4.clkr.hw }, 518184fdd87SKonrad Dybcio { .hw = &gpll3_out_even.clkr.hw }, 519184fdd87SKonrad Dybcio }; 520184fdd87SKonrad Dybcio 521184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_5[] = { 522184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 523184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 524184fdd87SKonrad Dybcio { P_GPLL8_OUT_MAIN, 2 }, 525184fdd87SKonrad Dybcio { P_GPLL10_OUT_EVEN, 3 }, 526184fdd87SKonrad Dybcio { P_GPLL9_OUT_MAIN, 4 }, 527184fdd87SKonrad Dybcio { P_GPLL8_OUT_EVEN, 5 }, 528184fdd87SKonrad Dybcio { P_GPLL3_OUT_EVEN, 6 }, 529184fdd87SKonrad Dybcio }; 530184fdd87SKonrad Dybcio 531184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_5[] = { 532184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 533184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 534184fdd87SKonrad Dybcio { .hw = &gpll8.clkr.hw }, 535184fdd87SKonrad Dybcio { .hw = &gpll10.clkr.hw }, 536184fdd87SKonrad Dybcio { .hw = &gpll9_out_main.clkr.hw }, 537184fdd87SKonrad Dybcio { .hw = &gpll8_out_even.clkr.hw }, 538184fdd87SKonrad Dybcio { .hw = &gpll3_out_even.clkr.hw }, 539184fdd87SKonrad Dybcio }; 540184fdd87SKonrad Dybcio 541184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_6[] = { 542184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 543184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 544184fdd87SKonrad Dybcio { P_GPLL8_OUT_MAIN, 2 }, 545184fdd87SKonrad Dybcio { P_GPLL5_OUT_EVEN, 3 }, 546184fdd87SKonrad Dybcio { P_GPLL9_OUT_MAIN, 4 }, 547184fdd87SKonrad Dybcio { P_GPLL8_OUT_EVEN, 5 }, 548184fdd87SKonrad Dybcio { P_GPLL3_OUT_MAIN, 6 }, 549184fdd87SKonrad Dybcio }; 550184fdd87SKonrad Dybcio 551184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_6[] = { 552184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 553184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 554184fdd87SKonrad Dybcio { .hw = &gpll8.clkr.hw }, 555184fdd87SKonrad Dybcio { .hw = &gpll5.clkr.hw }, 556184fdd87SKonrad Dybcio { .hw = &gpll9_out_main.clkr.hw }, 557184fdd87SKonrad Dybcio { .hw = &gpll8_out_even.clkr.hw }, 558184fdd87SKonrad Dybcio { .hw = &gpll3.clkr.hw }, 559184fdd87SKonrad Dybcio }; 560184fdd87SKonrad Dybcio 561184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_7[] = { 562184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 563184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 564184fdd87SKonrad Dybcio { P_GPLL0_OUT_EVEN, 2 }, 565184fdd87SKonrad Dybcio { P_GPLL0_OUT_ODD, 4 }, 566184fdd87SKonrad Dybcio { P_SLEEP_CLK, 5 }, 567184fdd87SKonrad Dybcio }; 568184fdd87SKonrad Dybcio 569184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_7[] = { 570184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 571184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 572184fdd87SKonrad Dybcio { .hw = &gpll0_out_even.clkr.hw }, 573184fdd87SKonrad Dybcio { .hw = &gpll0_out_odd.clkr.hw }, 574184fdd87SKonrad Dybcio { .index = DT_SLEEP_CLK }, 575184fdd87SKonrad Dybcio }; 576184fdd87SKonrad Dybcio 577184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_8[] = { 578184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 579184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 580184fdd87SKonrad Dybcio { P_GPLL0_OUT_EVEN, 2 }, 581184fdd87SKonrad Dybcio { P_GPLL10_OUT_EVEN, 3 }, 582184fdd87SKonrad Dybcio { P_GPLL4_OUT_EVEN, 5 }, 583184fdd87SKonrad Dybcio { P_GPLL3_OUT_MAIN, 6 }, 584184fdd87SKonrad Dybcio }; 585184fdd87SKonrad Dybcio 586184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_8[] = { 587184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 588184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 589184fdd87SKonrad Dybcio { .hw = &gpll0_out_even.clkr.hw }, 590184fdd87SKonrad Dybcio { .hw = &gpll10.clkr.hw }, 591184fdd87SKonrad Dybcio { .hw = &gpll4.clkr.hw }, 592184fdd87SKonrad Dybcio { .hw = &gpll3.clkr.hw }, 593184fdd87SKonrad Dybcio }; 594184fdd87SKonrad Dybcio 595184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_9[] = { 596184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 597184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 598184fdd87SKonrad Dybcio { P_GPLL0_OUT_EVEN, 2 }, 599184fdd87SKonrad Dybcio { P_GPLL10_OUT_EVEN, 3 }, 600184fdd87SKonrad Dybcio { P_GPLL9_OUT_MAIN, 4 }, 601184fdd87SKonrad Dybcio { P_GPLL8_OUT_EVEN, 5 }, 602184fdd87SKonrad Dybcio { P_GPLL3_OUT_MAIN, 6 }, 603184fdd87SKonrad Dybcio }; 604184fdd87SKonrad Dybcio 605184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_9[] = { 606184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 607184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 608184fdd87SKonrad Dybcio { .hw = &gpll0_out_even.clkr.hw }, 609184fdd87SKonrad Dybcio { .hw = &gpll10.clkr.hw }, 610184fdd87SKonrad Dybcio { .hw = &gpll9_out_main.clkr.hw }, 611184fdd87SKonrad Dybcio { .hw = &gpll8_out_even.clkr.hw }, 612184fdd87SKonrad Dybcio { .hw = &gpll3.clkr.hw }, 613184fdd87SKonrad Dybcio }; 614184fdd87SKonrad Dybcio 615184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_10[] = { 616184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 617184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 618184fdd87SKonrad Dybcio { P_GPLL8_OUT_MAIN, 2 }, 619184fdd87SKonrad Dybcio { P_GPLL10_OUT_EVEN, 3 }, 620184fdd87SKonrad Dybcio { P_GPLL9_OUT_MAIN, 4 }, 621184fdd87SKonrad Dybcio { P_GPLL8_OUT_EVEN, 5 }, 622184fdd87SKonrad Dybcio { P_GPLL3_OUT_MAIN, 6 }, 623184fdd87SKonrad Dybcio }; 624184fdd87SKonrad Dybcio 625184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_10[] = { 626184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 627184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 628184fdd87SKonrad Dybcio { .hw = &gpll8.clkr.hw }, 629184fdd87SKonrad Dybcio { .hw = &gpll10.clkr.hw }, 630184fdd87SKonrad Dybcio { .hw = &gpll9_out_main.clkr.hw }, 631184fdd87SKonrad Dybcio { .hw = &gpll8_out_even.clkr.hw }, 632184fdd87SKonrad Dybcio { .hw = &gpll3.clkr.hw }, 633184fdd87SKonrad Dybcio }; 634184fdd87SKonrad Dybcio 635184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_11[] = { 636184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 637184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 638184fdd87SKonrad Dybcio { P_GPLL8_OUT_MAIN, 2 }, 639184fdd87SKonrad Dybcio { P_GPLL10_OUT_EVEN, 3 }, 640184fdd87SKonrad Dybcio { P_GPLL6_OUT_MAIN, 4 }, 641184fdd87SKonrad Dybcio { P_GPLL3_OUT_EVEN, 6 }, 642184fdd87SKonrad Dybcio }; 643184fdd87SKonrad Dybcio 644184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_11[] = { 645184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 646184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 647184fdd87SKonrad Dybcio { .hw = &gpll8.clkr.hw }, 648184fdd87SKonrad Dybcio { .hw = &gpll10.clkr.hw }, 649184fdd87SKonrad Dybcio { .hw = &gpll6.clkr.hw }, 650184fdd87SKonrad Dybcio { .hw = &gpll3_out_even.clkr.hw }, 651184fdd87SKonrad Dybcio }; 652184fdd87SKonrad Dybcio 653184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_12[] = { 654184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 655184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 656184fdd87SKonrad Dybcio { P_GPLL0_OUT_EVEN, 2 }, 657184fdd87SKonrad Dybcio { P_GPLL7_OUT_EVEN, 3 }, 658184fdd87SKonrad Dybcio { P_GPLL4_OUT_EVEN, 5 }, 659184fdd87SKonrad Dybcio }; 660184fdd87SKonrad Dybcio 661184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_12[] = { 662184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 663184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 664184fdd87SKonrad Dybcio { .hw = &gpll0_out_even.clkr.hw }, 665184fdd87SKonrad Dybcio { .hw = &gpll7.clkr.hw }, 666184fdd87SKonrad Dybcio { .hw = &gpll4.clkr.hw }, 667184fdd87SKonrad Dybcio }; 668184fdd87SKonrad Dybcio 669184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_13[] = { 670184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 671184fdd87SKonrad Dybcio { P_SLEEP_CLK, 5 }, 672184fdd87SKonrad Dybcio }; 673184fdd87SKonrad Dybcio 674184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_13[] = { 675184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 676184fdd87SKonrad Dybcio { .index = DT_SLEEP_CLK }, 677184fdd87SKonrad Dybcio }; 678184fdd87SKonrad Dybcio 679184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_14[] = { 680184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 681184fdd87SKonrad Dybcio { P_GPLL11_OUT_ODD, 2 }, 682184fdd87SKonrad Dybcio { P_GPLL11_OUT_EVEN, 3 }, 683184fdd87SKonrad Dybcio }; 684184fdd87SKonrad Dybcio 685184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_14[] = { 686184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 687184fdd87SKonrad Dybcio { .hw = &gpll11.clkr.hw }, 688184fdd87SKonrad Dybcio { .hw = &gpll11.clkr.hw }, 689184fdd87SKonrad Dybcio }; 690184fdd87SKonrad Dybcio 691184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = { 692184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 693184fdd87SKonrad Dybcio F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 694184fdd87SKonrad Dybcio F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 695184fdd87SKonrad Dybcio F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 696184fdd87SKonrad Dybcio { } 697184fdd87SKonrad Dybcio }; 698184fdd87SKonrad Dybcio 699184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_axi_clk_src = { 700184fdd87SKonrad Dybcio .cmd_rcgr = 0x5802c, 701184fdd87SKonrad Dybcio .mnd_width = 0, 702184fdd87SKonrad Dybcio .hid_width = 5, 703184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_8, 704184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_axi_clk_src, 705184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 706184fdd87SKonrad Dybcio .name = "gcc_camss_axi_clk_src", 707184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_8, 708184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_8), 709184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 710184fdd87SKonrad Dybcio }, 711184fdd87SKonrad Dybcio }; 712184fdd87SKonrad Dybcio 713184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_camss_cci_0_clk_src[] = { 714184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 715184fdd87SKonrad Dybcio F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 716184fdd87SKonrad Dybcio { } 717184fdd87SKonrad Dybcio }; 718184fdd87SKonrad Dybcio 719184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_cci_0_clk_src = { 720184fdd87SKonrad Dybcio .cmd_rcgr = 0x56000, 721184fdd87SKonrad Dybcio .mnd_width = 0, 722184fdd87SKonrad Dybcio .hid_width = 5, 723184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_9, 724184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_cci_0_clk_src, 725184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 726184fdd87SKonrad Dybcio .name = "gcc_camss_cci_0_clk_src", 727184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_9, 728184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_9), 729184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 730184fdd87SKonrad Dybcio }, 731184fdd87SKonrad Dybcio }; 732184fdd87SKonrad Dybcio 733184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_cci_1_clk_src = { 734184fdd87SKonrad Dybcio .cmd_rcgr = 0x5c000, 735184fdd87SKonrad Dybcio .mnd_width = 0, 736184fdd87SKonrad Dybcio .hid_width = 5, 737184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_9, 738184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_cci_0_clk_src, 739184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 740184fdd87SKonrad Dybcio .name = "gcc_camss_cci_1_clk_src", 741184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_9, 742184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_9), 743184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 744184fdd87SKonrad Dybcio }, 745184fdd87SKonrad Dybcio }; 746184fdd87SKonrad Dybcio 747184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = { 748184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 749184fdd87SKonrad Dybcio F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0), 750184fdd87SKonrad Dybcio F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 751184fdd87SKonrad Dybcio { } 752184fdd87SKonrad Dybcio }; 753184fdd87SKonrad Dybcio 754184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { 755184fdd87SKonrad Dybcio .cmd_rcgr = 0x59000, 756184fdd87SKonrad Dybcio .mnd_width = 0, 757184fdd87SKonrad Dybcio .hid_width = 5, 758184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_4, 759184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 760184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 761184fdd87SKonrad Dybcio .name = "gcc_camss_csi0phytimer_clk_src", 762184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_4, 763184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_4), 764184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 765184fdd87SKonrad Dybcio }, 766184fdd87SKonrad Dybcio }; 767184fdd87SKonrad Dybcio 768184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { 769184fdd87SKonrad Dybcio .cmd_rcgr = 0x5901c, 770184fdd87SKonrad Dybcio .mnd_width = 0, 771184fdd87SKonrad Dybcio .hid_width = 5, 772184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_4, 773184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 774184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 775184fdd87SKonrad Dybcio .name = "gcc_camss_csi1phytimer_clk_src", 776184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_4, 777184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_4), 778184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 779184fdd87SKonrad Dybcio }, 780184fdd87SKonrad Dybcio }; 781184fdd87SKonrad Dybcio 782184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = { 783184fdd87SKonrad Dybcio .cmd_rcgr = 0x59038, 784184fdd87SKonrad Dybcio .mnd_width = 0, 785184fdd87SKonrad Dybcio .hid_width = 5, 786184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_4, 787184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 788184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 789184fdd87SKonrad Dybcio .name = "gcc_camss_csi2phytimer_clk_src", 790184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_4, 791184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_4), 792184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 793184fdd87SKonrad Dybcio }, 794184fdd87SKonrad Dybcio }; 795184fdd87SKonrad Dybcio 796184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_csi3phytimer_clk_src = { 797184fdd87SKonrad Dybcio .cmd_rcgr = 0x59054, 798184fdd87SKonrad Dybcio .mnd_width = 0, 799184fdd87SKonrad Dybcio .hid_width = 5, 800184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_4, 801184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 802184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 803184fdd87SKonrad Dybcio .name = "gcc_camss_csi3phytimer_clk_src", 804184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_4, 805184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_4), 806184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 807184fdd87SKonrad Dybcio }, 808184fdd87SKonrad Dybcio }; 809184fdd87SKonrad Dybcio 810184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { 811184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 812184fdd87SKonrad Dybcio F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 15), 813184fdd87SKonrad Dybcio F(65454545, P_GPLL9_OUT_EARLY, 11, 1, 2), 814184fdd87SKonrad Dybcio { } 815184fdd87SKonrad Dybcio }; 816184fdd87SKonrad Dybcio 817184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_mclk0_clk_src = { 818184fdd87SKonrad Dybcio .cmd_rcgr = 0x51000, 819184fdd87SKonrad Dybcio .mnd_width = 8, 820184fdd87SKonrad Dybcio .hid_width = 5, 821184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_3, 822184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 823184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 824184fdd87SKonrad Dybcio .name = "gcc_camss_mclk0_clk_src", 825184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_3, 826184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_3), 827184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 828184fdd87SKonrad Dybcio }, 829184fdd87SKonrad Dybcio }; 830184fdd87SKonrad Dybcio 831184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_mclk1_clk_src = { 832184fdd87SKonrad Dybcio .cmd_rcgr = 0x5101c, 833184fdd87SKonrad Dybcio .mnd_width = 8, 834184fdd87SKonrad Dybcio .hid_width = 5, 835184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_3, 836184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 837184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 838184fdd87SKonrad Dybcio .name = "gcc_camss_mclk1_clk_src", 839184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_3, 840184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_3), 841184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 842184fdd87SKonrad Dybcio }, 843184fdd87SKonrad Dybcio }; 844184fdd87SKonrad Dybcio 845184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_mclk2_clk_src = { 846184fdd87SKonrad Dybcio .cmd_rcgr = 0x51038, 847184fdd87SKonrad Dybcio .mnd_width = 8, 848184fdd87SKonrad Dybcio .hid_width = 5, 849184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_3, 850184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 851184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 852184fdd87SKonrad Dybcio .name = "gcc_camss_mclk2_clk_src", 853184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_3, 854184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_3), 855184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 856184fdd87SKonrad Dybcio }, 857184fdd87SKonrad Dybcio }; 858184fdd87SKonrad Dybcio 859184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_mclk3_clk_src = { 860184fdd87SKonrad Dybcio .cmd_rcgr = 0x51054, 861184fdd87SKonrad Dybcio .mnd_width = 8, 862184fdd87SKonrad Dybcio .hid_width = 5, 863184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_3, 864184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 865184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 866184fdd87SKonrad Dybcio .name = "gcc_camss_mclk3_clk_src", 867184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_3, 868184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_3), 869184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 870184fdd87SKonrad Dybcio }, 871184fdd87SKonrad Dybcio }; 872184fdd87SKonrad Dybcio 873184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_mclk4_clk_src = { 874184fdd87SKonrad Dybcio .cmd_rcgr = 0x51070, 875184fdd87SKonrad Dybcio .mnd_width = 8, 876184fdd87SKonrad Dybcio .hid_width = 5, 877184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_3, 878184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 879184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 880184fdd87SKonrad Dybcio .name = "gcc_camss_mclk4_clk_src", 881184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_3, 882184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_3), 883184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 884184fdd87SKonrad Dybcio }, 885184fdd87SKonrad Dybcio }; 886184fdd87SKonrad Dybcio 887184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = { 888184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 889184fdd87SKonrad Dybcio F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0), 890184fdd87SKonrad Dybcio F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 891184fdd87SKonrad Dybcio { } 892184fdd87SKonrad Dybcio }; 893184fdd87SKonrad Dybcio 894184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = { 895184fdd87SKonrad Dybcio .cmd_rcgr = 0x55024, 896184fdd87SKonrad Dybcio .mnd_width = 0, 897184fdd87SKonrad Dybcio .hid_width = 5, 898184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_10, 899184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src, 900184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 901184fdd87SKonrad Dybcio .name = "gcc_camss_ope_ahb_clk_src", 902184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_10, 903184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_10), 904184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 905184fdd87SKonrad Dybcio }, 906184fdd87SKonrad Dybcio }; 907184fdd87SKonrad Dybcio 908184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = { 909184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 910184fdd87SKonrad Dybcio F(200000000, P_GPLL8_OUT_EVEN, 1, 0, 0), 911184fdd87SKonrad Dybcio F(266600000, P_GPLL8_OUT_EVEN, 1, 0, 0), 912184fdd87SKonrad Dybcio F(480000000, P_GPLL8_OUT_EVEN, 1, 0, 0), 913184fdd87SKonrad Dybcio F(580000000, P_GPLL8_OUT_EVEN, 1, 0, 0), 914184fdd87SKonrad Dybcio { } 915184fdd87SKonrad Dybcio }; 916184fdd87SKonrad Dybcio 917184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_ope_clk_src = { 918184fdd87SKonrad Dybcio .cmd_rcgr = 0x55004, 919184fdd87SKonrad Dybcio .mnd_width = 0, 920184fdd87SKonrad Dybcio .hid_width = 5, 921184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_10, 922184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_ope_clk_src, 923184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 924184fdd87SKonrad Dybcio .name = "gcc_camss_ope_clk_src", 925184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_10, 926184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_10), 927184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 928184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 929184fdd87SKonrad Dybcio }, 930184fdd87SKonrad Dybcio }; 931184fdd87SKonrad Dybcio 932184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = { 933184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 934184fdd87SKonrad Dybcio F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), 935184fdd87SKonrad Dybcio F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 936184fdd87SKonrad Dybcio F(144000000, P_GPLL9_OUT_MAIN, 2.5, 0, 0), 937184fdd87SKonrad Dybcio F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 938184fdd87SKonrad Dybcio F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0), 939184fdd87SKonrad Dybcio F(180000000, P_GPLL9_OUT_MAIN, 2, 0, 0), 940184fdd87SKonrad Dybcio F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 941184fdd87SKonrad Dybcio F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 942184fdd87SKonrad Dybcio F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 943184fdd87SKonrad Dybcio F(329142857, P_GPLL10_OUT_EVEN, 3.5, 0, 0), 944184fdd87SKonrad Dybcio F(384000000, P_GPLL10_OUT_EVEN, 3, 0, 0), 945184fdd87SKonrad Dybcio F(460800000, P_GPLL10_OUT_EVEN, 2.5, 0, 0), 946184fdd87SKonrad Dybcio F(576000000, P_GPLL10_OUT_EVEN, 2, 0, 0), 947184fdd87SKonrad Dybcio { } 948184fdd87SKonrad Dybcio }; 949184fdd87SKonrad Dybcio 950184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_tfe_0_clk_src = { 951184fdd87SKonrad Dybcio .cmd_rcgr = 0x52004, 952184fdd87SKonrad Dybcio .mnd_width = 8, 953184fdd87SKonrad Dybcio .hid_width = 5, 954184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_5, 955184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 956184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 957184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_0_clk_src", 958184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_5, 959184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_5), 960184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 961184fdd87SKonrad Dybcio }, 962184fdd87SKonrad Dybcio }; 963184fdd87SKonrad Dybcio 964184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = { 965184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 966184fdd87SKonrad Dybcio F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), 967184fdd87SKonrad Dybcio F(266571429, P_GPLL5_OUT_EVEN, 3.5, 0, 0), 968184fdd87SKonrad Dybcio F(426400000, P_GPLL3_OUT_MAIN, 2.5, 0, 0), 969184fdd87SKonrad Dybcio F(466500000, P_GPLL5_OUT_EVEN, 2, 0, 0), 970184fdd87SKonrad Dybcio { } 971184fdd87SKonrad Dybcio }; 972184fdd87SKonrad Dybcio 973184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = { 974184fdd87SKonrad Dybcio .cmd_rcgr = 0x52094, 975184fdd87SKonrad Dybcio .mnd_width = 0, 976184fdd87SKonrad Dybcio .hid_width = 5, 977184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_6, 978184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 979184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 980184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_0_csid_clk_src", 981184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_6, 982184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_6), 983184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 984184fdd87SKonrad Dybcio }, 985184fdd87SKonrad Dybcio }; 986184fdd87SKonrad Dybcio 987184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_tfe_1_clk_src = { 988184fdd87SKonrad Dybcio .cmd_rcgr = 0x52024, 989184fdd87SKonrad Dybcio .mnd_width = 8, 990184fdd87SKonrad Dybcio .hid_width = 5, 991184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_5, 992184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 993184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 994184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_1_clk_src", 995184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_5, 996184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_5), 997184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 998184fdd87SKonrad Dybcio }, 999184fdd87SKonrad Dybcio }; 1000184fdd87SKonrad Dybcio 1001184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = { 1002184fdd87SKonrad Dybcio .cmd_rcgr = 0x520b4, 1003184fdd87SKonrad Dybcio .mnd_width = 0, 1004184fdd87SKonrad Dybcio .hid_width = 5, 1005184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_6, 1006184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 1007184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1008184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_1_csid_clk_src", 1009184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_6, 1010184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1011184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1012184fdd87SKonrad Dybcio }, 1013184fdd87SKonrad Dybcio }; 1014184fdd87SKonrad Dybcio 1015184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_tfe_2_clk_src = { 1016184fdd87SKonrad Dybcio .cmd_rcgr = 0x52044, 1017184fdd87SKonrad Dybcio .mnd_width = 8, 1018184fdd87SKonrad Dybcio .hid_width = 5, 1019184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_5, 1020184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 1021184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1022184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_2_clk_src", 1023184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_5, 1024184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1025184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1026184fdd87SKonrad Dybcio }, 1027184fdd87SKonrad Dybcio }; 1028184fdd87SKonrad Dybcio 1029184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_tfe_2_csid_clk_src = { 1030184fdd87SKonrad Dybcio .cmd_rcgr = 0x520d4, 1031184fdd87SKonrad Dybcio .mnd_width = 0, 1032184fdd87SKonrad Dybcio .hid_width = 5, 1033184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_6, 1034184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 1035184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1036184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_2_csid_clk_src", 1037184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_6, 1038184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1039184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1040184fdd87SKonrad Dybcio }, 1041184fdd87SKonrad Dybcio }; 1042184fdd87SKonrad Dybcio 1043184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = { 1044184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 1045184fdd87SKonrad Dybcio F(256000000, P_GPLL6_OUT_MAIN, 3, 0, 0), 1046184fdd87SKonrad Dybcio F(384000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 1047184fdd87SKonrad Dybcio { } 1048184fdd87SKonrad Dybcio }; 1049184fdd87SKonrad Dybcio 1050184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = { 1051184fdd87SKonrad Dybcio .cmd_rcgr = 0x52064, 1052184fdd87SKonrad Dybcio .mnd_width = 0, 1053184fdd87SKonrad Dybcio .hid_width = 5, 1054184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_11, 1055184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src, 1056184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1057184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_cphy_rx_clk_src", 1058184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_11, 1059184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_11), 1060184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1061184fdd87SKonrad Dybcio }, 1062184fdd87SKonrad Dybcio }; 1063184fdd87SKonrad Dybcio 1064184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = { 1065184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 1066184fdd87SKonrad Dybcio F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0), 1067184fdd87SKonrad Dybcio F(80000000, P_GPLL0_OUT_MAIN, 7.5, 0, 0), 1068184fdd87SKonrad Dybcio { } 1069184fdd87SKonrad Dybcio }; 1070184fdd87SKonrad Dybcio 1071184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_top_ahb_clk_src = { 1072184fdd87SKonrad Dybcio .cmd_rcgr = 0x58010, 1073184fdd87SKonrad Dybcio .mnd_width = 0, 1074184fdd87SKonrad Dybcio .hid_width = 5, 1075184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_8, 1076184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_top_ahb_clk_src, 1077184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1078184fdd87SKonrad Dybcio .name = "gcc_camss_top_ahb_clk_src", 1079184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_8, 1080184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_8), 1081184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1082184fdd87SKonrad Dybcio }, 1083184fdd87SKonrad Dybcio }; 1084184fdd87SKonrad Dybcio 1085184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { 1086184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 1087184fdd87SKonrad Dybcio F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0), 1088184fdd87SKonrad Dybcio F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0), 1089184fdd87SKonrad Dybcio { } 1090184fdd87SKonrad Dybcio }; 1091184fdd87SKonrad Dybcio 1092184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 1093184fdd87SKonrad Dybcio .cmd_rcgr = 0x2b13c, 1094184fdd87SKonrad Dybcio .mnd_width = 0, 1095184fdd87SKonrad Dybcio .hid_width = 5, 1096184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_2, 1097184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, 1098184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1099184fdd87SKonrad Dybcio .name = "gcc_cpuss_ahb_clk_src", 1100184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_2_ao, 1101184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_2_ao), 1102184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1103184fdd87SKonrad Dybcio }, 1104184fdd87SKonrad Dybcio }; 1105184fdd87SKonrad Dybcio 1106184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 1107184fdd87SKonrad Dybcio F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 1108184fdd87SKonrad Dybcio F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0), 1109184fdd87SKonrad Dybcio F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0), 1110184fdd87SKonrad Dybcio F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0), 1111184fdd87SKonrad Dybcio { } 1112184fdd87SKonrad Dybcio }; 1113184fdd87SKonrad Dybcio 1114184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_gp1_clk_src = { 1115184fdd87SKonrad Dybcio .cmd_rcgr = 0x4d004, 1116184fdd87SKonrad Dybcio .mnd_width = 16, 1117184fdd87SKonrad Dybcio .hid_width = 5, 1118184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_7, 1119184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_gp1_clk_src, 1120184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1121184fdd87SKonrad Dybcio .name = "gcc_gp1_clk_src", 1122184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_7, 1123184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_7), 1124184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1125184fdd87SKonrad Dybcio }, 1126184fdd87SKonrad Dybcio }; 1127184fdd87SKonrad Dybcio 1128184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_gp2_clk_src = { 1129184fdd87SKonrad Dybcio .cmd_rcgr = 0x4e004, 1130184fdd87SKonrad Dybcio .mnd_width = 16, 1131184fdd87SKonrad Dybcio .hid_width = 5, 1132184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_7, 1133184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_gp1_clk_src, 1134184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1135184fdd87SKonrad Dybcio .name = "gcc_gp2_clk_src", 1136184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_7, 1137184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_7), 1138184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1139184fdd87SKonrad Dybcio }, 1140184fdd87SKonrad Dybcio }; 1141184fdd87SKonrad Dybcio 1142184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_gp3_clk_src = { 1143184fdd87SKonrad Dybcio .cmd_rcgr = 0x4f004, 1144184fdd87SKonrad Dybcio .mnd_width = 16, 1145184fdd87SKonrad Dybcio .hid_width = 5, 1146184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_7, 1147184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_gp1_clk_src, 1148184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1149184fdd87SKonrad Dybcio .name = "gcc_gp3_clk_src", 1150184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_7, 1151184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_7), 1152184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1153184fdd87SKonrad Dybcio }, 1154184fdd87SKonrad Dybcio }; 1155184fdd87SKonrad Dybcio 1156184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 1157184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 1158184fdd87SKonrad Dybcio F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), 1159184fdd87SKonrad Dybcio { } 1160184fdd87SKonrad Dybcio }; 1161184fdd87SKonrad Dybcio 1162184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_pdm2_clk_src = { 1163184fdd87SKonrad Dybcio .cmd_rcgr = 0x20010, 1164184fdd87SKonrad Dybcio .mnd_width = 0, 1165184fdd87SKonrad Dybcio .hid_width = 5, 1166184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_0, 1167184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_pdm2_clk_src, 1168184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1169184fdd87SKonrad Dybcio .name = "gcc_pdm2_clk_src", 1170184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_0, 1171184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1172184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1173184fdd87SKonrad Dybcio }, 1174184fdd87SKonrad Dybcio }; 1175184fdd87SKonrad Dybcio 1176184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 1177184fdd87SKonrad Dybcio F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 1178184fdd87SKonrad Dybcio F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 1179184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 1180184fdd87SKonrad Dybcio F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 1181184fdd87SKonrad Dybcio F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 1182184fdd87SKonrad Dybcio F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 1183184fdd87SKonrad Dybcio F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 1184184fdd87SKonrad Dybcio F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 1185184fdd87SKonrad Dybcio F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 1186184fdd87SKonrad Dybcio F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 1187184fdd87SKonrad Dybcio F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 1188184fdd87SKonrad Dybcio F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), 1189184fdd87SKonrad Dybcio F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), 1190184fdd87SKonrad Dybcio F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), 1191184fdd87SKonrad Dybcio F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), 1192184fdd87SKonrad Dybcio F(128000000, P_GPLL6_OUT_EVEN, 3, 0, 0), 1193184fdd87SKonrad Dybcio { } 1194184fdd87SKonrad Dybcio }; 1195184fdd87SKonrad Dybcio 1196184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 1197184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s0_clk_src", 1198184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1199184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1200184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1201184fdd87SKonrad Dybcio }; 1202184fdd87SKonrad Dybcio 1203184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 1204184fdd87SKonrad Dybcio .cmd_rcgr = 0x1f148, 1205184fdd87SKonrad Dybcio .mnd_width = 16, 1206184fdd87SKonrad Dybcio .hid_width = 5, 1207184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1208184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1209184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 1210184fdd87SKonrad Dybcio }; 1211184fdd87SKonrad Dybcio 1212184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 1213184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s1_clk_src", 1214184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1215184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1216184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1217184fdd87SKonrad Dybcio }; 1218184fdd87SKonrad Dybcio 1219184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 1220184fdd87SKonrad Dybcio .cmd_rcgr = 0x1f278, 1221184fdd87SKonrad Dybcio .mnd_width = 16, 1222184fdd87SKonrad Dybcio .hid_width = 5, 1223184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1224184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1225184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 1226184fdd87SKonrad Dybcio }; 1227184fdd87SKonrad Dybcio 1228184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 1229184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s2_clk_src", 1230184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1231184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1232184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1233184fdd87SKonrad Dybcio }; 1234184fdd87SKonrad Dybcio 1235184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 1236184fdd87SKonrad Dybcio .cmd_rcgr = 0x1f3a8, 1237184fdd87SKonrad Dybcio .mnd_width = 16, 1238184fdd87SKonrad Dybcio .hid_width = 5, 1239184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1240184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1241184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 1242184fdd87SKonrad Dybcio }; 1243184fdd87SKonrad Dybcio 1244184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 1245184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s3_clk_src", 1246184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1247184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1248184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1249184fdd87SKonrad Dybcio }; 1250184fdd87SKonrad Dybcio 1251184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 1252184fdd87SKonrad Dybcio .cmd_rcgr = 0x1f4d8, 1253184fdd87SKonrad Dybcio .mnd_width = 16, 1254184fdd87SKonrad Dybcio .hid_width = 5, 1255184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1256184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1257184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 1258184fdd87SKonrad Dybcio }; 1259184fdd87SKonrad Dybcio 1260184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 1261184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s4_clk_src", 1262184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1263184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1264184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1265184fdd87SKonrad Dybcio }; 1266184fdd87SKonrad Dybcio 1267184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 1268184fdd87SKonrad Dybcio .cmd_rcgr = 0x1f608, 1269184fdd87SKonrad Dybcio .mnd_width = 16, 1270184fdd87SKonrad Dybcio .hid_width = 5, 1271184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1272184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1273184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 1274184fdd87SKonrad Dybcio }; 1275184fdd87SKonrad Dybcio 1276184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 1277184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s5_clk_src", 1278184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1279184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1280184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1281184fdd87SKonrad Dybcio }; 1282184fdd87SKonrad Dybcio 1283184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 1284184fdd87SKonrad Dybcio .cmd_rcgr = 0x1f738, 1285184fdd87SKonrad Dybcio .mnd_width = 16, 1286184fdd87SKonrad Dybcio .hid_width = 5, 1287184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1288184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1289184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 1290184fdd87SKonrad Dybcio }; 1291184fdd87SKonrad Dybcio 1292184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 1293184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s0_clk_src", 1294184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1295184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1296184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1297184fdd87SKonrad Dybcio }; 1298184fdd87SKonrad Dybcio 1299184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 1300184fdd87SKonrad Dybcio .cmd_rcgr = 0x5301c, 1301184fdd87SKonrad Dybcio .mnd_width = 16, 1302184fdd87SKonrad Dybcio .hid_width = 5, 1303184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1304184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1305184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 1306184fdd87SKonrad Dybcio }; 1307184fdd87SKonrad Dybcio 1308184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 1309184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s1_clk_src", 1310184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1311184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1312184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1313184fdd87SKonrad Dybcio }; 1314184fdd87SKonrad Dybcio 1315184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 1316184fdd87SKonrad Dybcio .cmd_rcgr = 0x5314c, 1317184fdd87SKonrad Dybcio .mnd_width = 16, 1318184fdd87SKonrad Dybcio .hid_width = 5, 1319184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1320184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1321184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 1322184fdd87SKonrad Dybcio }; 1323184fdd87SKonrad Dybcio 1324184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 1325184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s2_clk_src", 1326184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1327184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1328184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1329184fdd87SKonrad Dybcio }; 1330184fdd87SKonrad Dybcio 1331184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 1332184fdd87SKonrad Dybcio .cmd_rcgr = 0x5327c, 1333184fdd87SKonrad Dybcio .mnd_width = 16, 1334184fdd87SKonrad Dybcio .hid_width = 5, 1335184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1336184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1337184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 1338184fdd87SKonrad Dybcio }; 1339184fdd87SKonrad Dybcio 1340184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 1341184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s3_clk_src", 1342184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1343184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1344184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1345184fdd87SKonrad Dybcio }; 1346184fdd87SKonrad Dybcio 1347184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 1348184fdd87SKonrad Dybcio .cmd_rcgr = 0x533ac, 1349184fdd87SKonrad Dybcio .mnd_width = 16, 1350184fdd87SKonrad Dybcio .hid_width = 5, 1351184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1352184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1353184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 1354184fdd87SKonrad Dybcio }; 1355184fdd87SKonrad Dybcio 1356184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 1357184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s4_clk_src", 1358184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1359184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1360184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1361184fdd87SKonrad Dybcio }; 1362184fdd87SKonrad Dybcio 1363184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 1364184fdd87SKonrad Dybcio .cmd_rcgr = 0x534dc, 1365184fdd87SKonrad Dybcio .mnd_width = 16, 1366184fdd87SKonrad Dybcio .hid_width = 5, 1367184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1368184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1369184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 1370184fdd87SKonrad Dybcio }; 1371184fdd87SKonrad Dybcio 1372184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 1373184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s5_clk_src", 1374184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1375184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1376184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1377184fdd87SKonrad Dybcio }; 1378184fdd87SKonrad Dybcio 1379184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 1380184fdd87SKonrad Dybcio .cmd_rcgr = 0x5360c, 1381184fdd87SKonrad Dybcio .mnd_width = 16, 1382184fdd87SKonrad Dybcio .hid_width = 5, 1383184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1384184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1385184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 1386184fdd87SKonrad Dybcio }; 1387184fdd87SKonrad Dybcio 1388184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 1389184fdd87SKonrad Dybcio F(144000, P_BI_TCXO, 16, 3, 25), 1390184fdd87SKonrad Dybcio F(400000, P_BI_TCXO, 12, 1, 4), 1391184fdd87SKonrad Dybcio F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), 1392184fdd87SKonrad Dybcio F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), 1393184fdd87SKonrad Dybcio F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 1394184fdd87SKonrad Dybcio F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 1395184fdd87SKonrad Dybcio F(192000000, P_GPLL6_OUT_EVEN, 2, 0, 0), 1396184fdd87SKonrad Dybcio F(384000000, P_GPLL6_OUT_EVEN, 1, 0, 0), 1397184fdd87SKonrad Dybcio { } 1398184fdd87SKonrad Dybcio }; 1399184fdd87SKonrad Dybcio 1400184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 1401184fdd87SKonrad Dybcio .cmd_rcgr = 0x38028, 1402184fdd87SKonrad Dybcio .mnd_width = 8, 1403184fdd87SKonrad Dybcio .hid_width = 5, 1404184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1405184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 1406184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1407184fdd87SKonrad Dybcio .name = "gcc_sdcc1_apps_clk_src", 1408184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1409184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1410184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1411184fdd87SKonrad Dybcio }, 1412184fdd87SKonrad Dybcio }; 1413184fdd87SKonrad Dybcio 1414184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 1415184fdd87SKonrad Dybcio F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 1416184fdd87SKonrad Dybcio F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 1417184fdd87SKonrad Dybcio F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 1418184fdd87SKonrad Dybcio F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 1419184fdd87SKonrad Dybcio F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 1420184fdd87SKonrad Dybcio { } 1421184fdd87SKonrad Dybcio }; 1422184fdd87SKonrad Dybcio 1423184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 1424184fdd87SKonrad Dybcio .cmd_rcgr = 0x38010, 1425184fdd87SKonrad Dybcio .mnd_width = 0, 1426184fdd87SKonrad Dybcio .hid_width = 5, 1427184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_0, 1428184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 1429184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1430184fdd87SKonrad Dybcio .name = "gcc_sdcc1_ice_core_clk_src", 1431184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_0, 1432184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1433184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1434184fdd87SKonrad Dybcio }, 1435184fdd87SKonrad Dybcio }; 1436184fdd87SKonrad Dybcio 1437184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1438184fdd87SKonrad Dybcio F(400000, P_BI_TCXO, 12, 1, 4), 1439184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 1440184fdd87SKonrad Dybcio F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 1441184fdd87SKonrad Dybcio F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 1442184fdd87SKonrad Dybcio F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 1443184fdd87SKonrad Dybcio F(202000000, P_GPLL7_OUT_EVEN, 4, 0, 0), 1444184fdd87SKonrad Dybcio { } 1445184fdd87SKonrad Dybcio }; 1446184fdd87SKonrad Dybcio 1447184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1448184fdd87SKonrad Dybcio .cmd_rcgr = 0x1e00c, 1449184fdd87SKonrad Dybcio .mnd_width = 8, 1450184fdd87SKonrad Dybcio .hid_width = 5, 1451184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_12, 1452184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1453184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1454184fdd87SKonrad Dybcio .name = "gcc_sdcc2_apps_clk_src", 1455184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_12, 1456184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_12), 1457184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1458184fdd87SKonrad Dybcio }, 1459184fdd87SKonrad Dybcio }; 1460184fdd87SKonrad Dybcio 1461184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1462184fdd87SKonrad Dybcio F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 1463184fdd87SKonrad Dybcio F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0), 1464184fdd87SKonrad Dybcio F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0), 1465184fdd87SKonrad Dybcio F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0), 1466184fdd87SKonrad Dybcio F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 1467184fdd87SKonrad Dybcio { } 1468184fdd87SKonrad Dybcio }; 1469184fdd87SKonrad Dybcio 1470184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1471184fdd87SKonrad Dybcio .cmd_rcgr = 0x45020, 1472184fdd87SKonrad Dybcio .mnd_width = 8, 1473184fdd87SKonrad Dybcio .hid_width = 5, 1474184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_2, 1475184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1476184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1477184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_axi_clk_src", 1478184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_2, 1479184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1480184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1481184fdd87SKonrad Dybcio }, 1482184fdd87SKonrad Dybcio }; 1483184fdd87SKonrad Dybcio 1484184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1485184fdd87SKonrad Dybcio F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 1486184fdd87SKonrad Dybcio F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 1487184fdd87SKonrad Dybcio F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 1488184fdd87SKonrad Dybcio F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 1489184fdd87SKonrad Dybcio { } 1490184fdd87SKonrad Dybcio }; 1491184fdd87SKonrad Dybcio 1492184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1493184fdd87SKonrad Dybcio .cmd_rcgr = 0x45048, 1494184fdd87SKonrad Dybcio .mnd_width = 0, 1495184fdd87SKonrad Dybcio .hid_width = 5, 1496184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_0, 1497184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1498184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1499184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_ice_core_clk_src", 1500184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_0, 1501184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1502184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1503184fdd87SKonrad Dybcio }, 1504184fdd87SKonrad Dybcio }; 1505184fdd87SKonrad Dybcio 1506184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1507184fdd87SKonrad Dybcio F(9600000, P_BI_TCXO, 2, 0, 0), 1508184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 1509184fdd87SKonrad Dybcio { } 1510184fdd87SKonrad Dybcio }; 1511184fdd87SKonrad Dybcio 1512184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1513184fdd87SKonrad Dybcio .cmd_rcgr = 0x4507c, 1514184fdd87SKonrad Dybcio .mnd_width = 0, 1515184fdd87SKonrad Dybcio .hid_width = 5, 1516184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_0, 1517184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1518184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1519184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_phy_aux_clk_src", 1520184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_0, 1521184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1522184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1523184fdd87SKonrad Dybcio }, 1524184fdd87SKonrad Dybcio }; 1525184fdd87SKonrad Dybcio 1526184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 1527184fdd87SKonrad Dybcio F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 1528184fdd87SKonrad Dybcio F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 1529184fdd87SKonrad Dybcio F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 1530184fdd87SKonrad Dybcio { } 1531184fdd87SKonrad Dybcio }; 1532184fdd87SKonrad Dybcio 1533184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1534184fdd87SKonrad Dybcio .cmd_rcgr = 0x45060, 1535184fdd87SKonrad Dybcio .mnd_width = 0, 1536184fdd87SKonrad Dybcio .hid_width = 5, 1537184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_0, 1538184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 1539184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1540184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_unipro_core_clk_src", 1541184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_0, 1542184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1543184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1544184fdd87SKonrad Dybcio }, 1545184fdd87SKonrad Dybcio }; 1546184fdd87SKonrad Dybcio 1547184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1548184fdd87SKonrad Dybcio F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), 1549184fdd87SKonrad Dybcio F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 1550184fdd87SKonrad Dybcio F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0), 1551184fdd87SKonrad Dybcio F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 1552184fdd87SKonrad Dybcio { } 1553184fdd87SKonrad Dybcio }; 1554184fdd87SKonrad Dybcio 1555184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1556184fdd87SKonrad Dybcio .cmd_rcgr = 0x1a01c, 1557184fdd87SKonrad Dybcio .mnd_width = 8, 1558184fdd87SKonrad Dybcio .hid_width = 5, 1559184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_2, 1560184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1561184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1562184fdd87SKonrad Dybcio .name = "gcc_usb30_prim_master_clk_src", 1563184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_2, 1564184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1565184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1566184fdd87SKonrad Dybcio }, 1567184fdd87SKonrad Dybcio }; 1568184fdd87SKonrad Dybcio 1569184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 1570184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 1571184fdd87SKonrad Dybcio { } 1572184fdd87SKonrad Dybcio }; 1573184fdd87SKonrad Dybcio 1574184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1575184fdd87SKonrad Dybcio .cmd_rcgr = 0x1a034, 1576184fdd87SKonrad Dybcio .mnd_width = 0, 1577184fdd87SKonrad Dybcio .hid_width = 5, 1578184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_0, 1579184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1580184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1581184fdd87SKonrad Dybcio .name = "gcc_usb30_prim_mock_utmi_clk_src", 1582184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_0, 1583184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1584184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1585184fdd87SKonrad Dybcio }, 1586184fdd87SKonrad Dybcio }; 1587184fdd87SKonrad Dybcio 1588184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1589184fdd87SKonrad Dybcio .cmd_rcgr = 0x1a060, 1590184fdd87SKonrad Dybcio .mnd_width = 0, 1591184fdd87SKonrad Dybcio .hid_width = 5, 1592184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_13, 1593184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1594184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1595184fdd87SKonrad Dybcio .name = "gcc_usb3_prim_phy_aux_clk_src", 1596184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_13, 1597184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_13), 1598184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1599184fdd87SKonrad Dybcio }, 1600184fdd87SKonrad Dybcio }; 1601184fdd87SKonrad Dybcio 1602184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = { 1603184fdd87SKonrad Dybcio F(133000000, P_GPLL11_OUT_EVEN, 4, 0, 0), 1604184fdd87SKonrad Dybcio F(240000000, P_GPLL11_OUT_EVEN, 2.5, 0, 0), 1605184fdd87SKonrad Dybcio F(300000000, P_GPLL11_OUT_EVEN, 2, 0, 0), 1606184fdd87SKonrad Dybcio F(384000000, P_GPLL11_OUT_EVEN, 2, 0, 0), 1607184fdd87SKonrad Dybcio { } 1608184fdd87SKonrad Dybcio }; 1609184fdd87SKonrad Dybcio 1610184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_video_venus_clk_src = { 1611184fdd87SKonrad Dybcio .cmd_rcgr = 0x58060, 1612184fdd87SKonrad Dybcio .mnd_width = 0, 1613184fdd87SKonrad Dybcio .hid_width = 5, 1614184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_14, 1615184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_video_venus_clk_src, 1616184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1617184fdd87SKonrad Dybcio .name = "gcc_video_venus_clk_src", 1618184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_14, 1619184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_14), 1620184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1621184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1622184fdd87SKonrad Dybcio }, 1623184fdd87SKonrad Dybcio }; 1624184fdd87SKonrad Dybcio 1625184fdd87SKonrad Dybcio static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = { 1626184fdd87SKonrad Dybcio .reg = 0x2b154, 1627184fdd87SKonrad Dybcio .shift = 0, 1628184fdd87SKonrad Dybcio .width = 4, 1629184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data) { 1630184fdd87SKonrad Dybcio .name = "gcc_cpuss_ahb_postdiv_clk_src", 1631184fdd87SKonrad Dybcio .parent_hws = (const struct clk_hw*[]){ 1632184fdd87SKonrad Dybcio &gcc_cpuss_ahb_clk_src.clkr.hw, 1633184fdd87SKonrad Dybcio }, 1634184fdd87SKonrad Dybcio .num_parents = 1, 1635184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1636184fdd87SKonrad Dybcio .ops = &clk_regmap_div_ro_ops, 1637184fdd87SKonrad Dybcio }, 1638184fdd87SKonrad Dybcio }; 1639184fdd87SKonrad Dybcio 1640184fdd87SKonrad Dybcio static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1641184fdd87SKonrad Dybcio .reg = 0x1a04c, 1642184fdd87SKonrad Dybcio .shift = 0, 1643184fdd87SKonrad Dybcio .width = 4, 1644184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data) { 1645184fdd87SKonrad Dybcio .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1646184fdd87SKonrad Dybcio .parent_hws = (const struct clk_hw*[]){ 1647184fdd87SKonrad Dybcio &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1648184fdd87SKonrad Dybcio }, 1649184fdd87SKonrad Dybcio .num_parents = 1, 1650184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1651184fdd87SKonrad Dybcio .ops = &clk_regmap_div_ro_ops, 1652184fdd87SKonrad Dybcio }, 1653184fdd87SKonrad Dybcio }; 1654184fdd87SKonrad Dybcio 1655184fdd87SKonrad Dybcio static struct clk_branch gcc_ahb2phy_csi_clk = { 1656184fdd87SKonrad Dybcio .halt_reg = 0x1d004, 1657184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 1658184fdd87SKonrad Dybcio .hwcg_reg = 0x1d004, 1659184fdd87SKonrad Dybcio .hwcg_bit = 1, 1660184fdd87SKonrad Dybcio .clkr = { 1661184fdd87SKonrad Dybcio .enable_reg = 0x1d004, 1662184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1663184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1664184fdd87SKonrad Dybcio .name = "gcc_ahb2phy_csi_clk", 1665184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1666184fdd87SKonrad Dybcio }, 1667184fdd87SKonrad Dybcio }, 1668184fdd87SKonrad Dybcio }; 1669184fdd87SKonrad Dybcio 1670184fdd87SKonrad Dybcio static struct clk_branch gcc_ahb2phy_usb_clk = { 1671184fdd87SKonrad Dybcio .halt_reg = 0x1d008, 1672184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 1673184fdd87SKonrad Dybcio .hwcg_reg = 0x1d008, 1674184fdd87SKonrad Dybcio .hwcg_bit = 1, 1675184fdd87SKonrad Dybcio .clkr = { 1676184fdd87SKonrad Dybcio .enable_reg = 0x1d008, 1677184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1678184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1679184fdd87SKonrad Dybcio .name = "gcc_ahb2phy_usb_clk", 1680184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1681184fdd87SKonrad Dybcio }, 1682184fdd87SKonrad Dybcio }, 1683184fdd87SKonrad Dybcio }; 1684184fdd87SKonrad Dybcio 1685184fdd87SKonrad Dybcio static struct clk_branch gcc_bimc_gpu_axi_clk = { 1686184fdd87SKonrad Dybcio .halt_reg = 0x71154, 1687184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 1688184fdd87SKonrad Dybcio .hwcg_reg = 0x71154, 1689184fdd87SKonrad Dybcio .hwcg_bit = 1, 1690184fdd87SKonrad Dybcio .clkr = { 1691184fdd87SKonrad Dybcio .enable_reg = 0x71154, 1692184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1693184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1694184fdd87SKonrad Dybcio .name = "gcc_bimc_gpu_axi_clk", 1695184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1696184fdd87SKonrad Dybcio }, 1697184fdd87SKonrad Dybcio }, 1698184fdd87SKonrad Dybcio }; 1699184fdd87SKonrad Dybcio 1700184fdd87SKonrad Dybcio static struct clk_branch gcc_boot_rom_ahb_clk = { 1701184fdd87SKonrad Dybcio .halt_reg = 0x23004, 1702184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 1703184fdd87SKonrad Dybcio .hwcg_reg = 0x23004, 1704184fdd87SKonrad Dybcio .hwcg_bit = 1, 1705184fdd87SKonrad Dybcio .clkr = { 1706184fdd87SKonrad Dybcio .enable_reg = 0x79004, 1707184fdd87SKonrad Dybcio .enable_mask = BIT(10), 1708184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1709184fdd87SKonrad Dybcio .name = "gcc_boot_rom_ahb_clk", 1710184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1711184fdd87SKonrad Dybcio }, 1712184fdd87SKonrad Dybcio }, 1713184fdd87SKonrad Dybcio }; 1714184fdd87SKonrad Dybcio 1715184fdd87SKonrad Dybcio static struct clk_branch gcc_cam_throttle_nrt_clk = { 1716184fdd87SKonrad Dybcio .halt_reg = 0x17070, 1717184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 1718184fdd87SKonrad Dybcio .hwcg_reg = 0x17070, 1719184fdd87SKonrad Dybcio .hwcg_bit = 1, 1720184fdd87SKonrad Dybcio .clkr = { 1721184fdd87SKonrad Dybcio .enable_reg = 0x79004, 1722184fdd87SKonrad Dybcio .enable_mask = BIT(27), 1723184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1724184fdd87SKonrad Dybcio .name = "gcc_cam_throttle_nrt_clk", 1725184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1726184fdd87SKonrad Dybcio }, 1727184fdd87SKonrad Dybcio }, 1728184fdd87SKonrad Dybcio }; 1729184fdd87SKonrad Dybcio 1730184fdd87SKonrad Dybcio static struct clk_branch gcc_cam_throttle_rt_clk = { 1731184fdd87SKonrad Dybcio .halt_reg = 0x1706c, 1732184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 1733184fdd87SKonrad Dybcio .hwcg_reg = 0x1706c, 1734184fdd87SKonrad Dybcio .hwcg_bit = 1, 1735184fdd87SKonrad Dybcio .clkr = { 1736184fdd87SKonrad Dybcio .enable_reg = 0x79004, 1737184fdd87SKonrad Dybcio .enable_mask = BIT(26), 1738184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1739184fdd87SKonrad Dybcio .name = "gcc_cam_throttle_rt_clk", 1740184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1741184fdd87SKonrad Dybcio }, 1742184fdd87SKonrad Dybcio }, 1743184fdd87SKonrad Dybcio }; 1744184fdd87SKonrad Dybcio 1745184fdd87SKonrad Dybcio static struct clk_branch gcc_camera_ahb_clk = { 1746184fdd87SKonrad Dybcio .halt_reg = 0x17008, 1747184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_DELAY, 1748184fdd87SKonrad Dybcio .hwcg_reg = 0x17008, 1749184fdd87SKonrad Dybcio .hwcg_bit = 1, 1750184fdd87SKonrad Dybcio .clkr = { 1751184fdd87SKonrad Dybcio .enable_reg = 0x17008, 1752184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1753184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1754184fdd87SKonrad Dybcio .name = "gcc_camera_ahb_clk", 1755184fdd87SKonrad Dybcio .flags = CLK_IS_CRITICAL, 1756184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1757184fdd87SKonrad Dybcio }, 1758184fdd87SKonrad Dybcio }, 1759184fdd87SKonrad Dybcio }; 1760184fdd87SKonrad Dybcio 1761184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_axi_clk = { 1762184fdd87SKonrad Dybcio .halt_reg = 0x58044, 1763184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1764184fdd87SKonrad Dybcio .clkr = { 1765184fdd87SKonrad Dybcio .enable_reg = 0x58044, 1766184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1767184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1768184fdd87SKonrad Dybcio .name = "gcc_camss_axi_clk", 1769*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 1770*5d0e6922SDmitry Baryshkov &gcc_camss_axi_clk_src.clkr.hw, 1771184fdd87SKonrad Dybcio }, 1772184fdd87SKonrad Dybcio .num_parents = 1, 1773184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1774184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1775184fdd87SKonrad Dybcio }, 1776184fdd87SKonrad Dybcio }, 1777184fdd87SKonrad Dybcio }; 1778184fdd87SKonrad Dybcio 1779184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_cci_0_clk = { 1780184fdd87SKonrad Dybcio .halt_reg = 0x56018, 1781184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1782184fdd87SKonrad Dybcio .clkr = { 1783184fdd87SKonrad Dybcio .enable_reg = 0x56018, 1784184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1785184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1786184fdd87SKonrad Dybcio .name = "gcc_camss_cci_0_clk", 1787*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 1788*5d0e6922SDmitry Baryshkov &gcc_camss_cci_0_clk_src.clkr.hw, 1789184fdd87SKonrad Dybcio }, 1790184fdd87SKonrad Dybcio .num_parents = 1, 1791184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1792184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1793184fdd87SKonrad Dybcio }, 1794184fdd87SKonrad Dybcio }, 1795184fdd87SKonrad Dybcio }; 1796184fdd87SKonrad Dybcio 1797184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_cci_1_clk = { 1798184fdd87SKonrad Dybcio .halt_reg = 0x5c018, 1799184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1800184fdd87SKonrad Dybcio .clkr = { 1801184fdd87SKonrad Dybcio .enable_reg = 0x5c018, 1802184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1803184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1804184fdd87SKonrad Dybcio .name = "gcc_camss_cci_1_clk", 1805*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 1806*5d0e6922SDmitry Baryshkov &gcc_camss_cci_1_clk_src.clkr.hw, 1807184fdd87SKonrad Dybcio }, 1808184fdd87SKonrad Dybcio .num_parents = 1, 1809184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1810184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1811184fdd87SKonrad Dybcio }, 1812184fdd87SKonrad Dybcio }, 1813184fdd87SKonrad Dybcio }; 1814184fdd87SKonrad Dybcio 1815184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_cphy_0_clk = { 1816184fdd87SKonrad Dybcio .halt_reg = 0x52088, 1817184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1818184fdd87SKonrad Dybcio .clkr = { 1819184fdd87SKonrad Dybcio .enable_reg = 0x52088, 1820184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1821184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1822184fdd87SKonrad Dybcio .name = "gcc_camss_cphy_0_clk", 1823*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 1824*5d0e6922SDmitry Baryshkov &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1825184fdd87SKonrad Dybcio }, 1826184fdd87SKonrad Dybcio .num_parents = 1, 1827184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1828184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1829184fdd87SKonrad Dybcio }, 1830184fdd87SKonrad Dybcio }, 1831184fdd87SKonrad Dybcio }; 1832184fdd87SKonrad Dybcio 1833184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_cphy_1_clk = { 1834184fdd87SKonrad Dybcio .halt_reg = 0x5208c, 1835184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1836184fdd87SKonrad Dybcio .clkr = { 1837184fdd87SKonrad Dybcio .enable_reg = 0x5208c, 1838184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1839184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1840184fdd87SKonrad Dybcio .name = "gcc_camss_cphy_1_clk", 1841*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 1842*5d0e6922SDmitry Baryshkov &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1843184fdd87SKonrad Dybcio }, 1844184fdd87SKonrad Dybcio .num_parents = 1, 1845184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1846184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1847184fdd87SKonrad Dybcio }, 1848184fdd87SKonrad Dybcio }, 1849184fdd87SKonrad Dybcio }; 1850184fdd87SKonrad Dybcio 1851184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_cphy_2_clk = { 1852184fdd87SKonrad Dybcio .halt_reg = 0x52090, 1853184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1854184fdd87SKonrad Dybcio .clkr = { 1855184fdd87SKonrad Dybcio .enable_reg = 0x52090, 1856184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1857184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1858184fdd87SKonrad Dybcio .name = "gcc_camss_cphy_2_clk", 1859*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 1860*5d0e6922SDmitry Baryshkov &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1861184fdd87SKonrad Dybcio }, 1862184fdd87SKonrad Dybcio .num_parents = 1, 1863184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1864184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1865184fdd87SKonrad Dybcio }, 1866184fdd87SKonrad Dybcio }, 1867184fdd87SKonrad Dybcio }; 1868184fdd87SKonrad Dybcio 1869184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_cphy_3_clk = { 1870184fdd87SKonrad Dybcio .halt_reg = 0x520f8, 1871184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1872184fdd87SKonrad Dybcio .clkr = { 1873184fdd87SKonrad Dybcio .enable_reg = 0x520f8, 1874184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1875184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1876184fdd87SKonrad Dybcio .name = "gcc_camss_cphy_3_clk", 1877*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 1878*5d0e6922SDmitry Baryshkov &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1879184fdd87SKonrad Dybcio }, 1880184fdd87SKonrad Dybcio .num_parents = 1, 1881184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1882184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1883184fdd87SKonrad Dybcio }, 1884184fdd87SKonrad Dybcio }, 1885184fdd87SKonrad Dybcio }; 1886184fdd87SKonrad Dybcio 1887184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_csi0phytimer_clk = { 1888184fdd87SKonrad Dybcio .halt_reg = 0x59018, 1889184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1890184fdd87SKonrad Dybcio .clkr = { 1891184fdd87SKonrad Dybcio .enable_reg = 0x59018, 1892184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1893184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1894184fdd87SKonrad Dybcio .name = "gcc_camss_csi0phytimer_clk", 1895*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 1896*5d0e6922SDmitry Baryshkov &gcc_camss_csi0phytimer_clk_src.clkr.hw, 1897184fdd87SKonrad Dybcio }, 1898184fdd87SKonrad Dybcio .num_parents = 1, 1899184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1900184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1901184fdd87SKonrad Dybcio }, 1902184fdd87SKonrad Dybcio }, 1903184fdd87SKonrad Dybcio }; 1904184fdd87SKonrad Dybcio 1905184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_csi1phytimer_clk = { 1906184fdd87SKonrad Dybcio .halt_reg = 0x59034, 1907184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1908184fdd87SKonrad Dybcio .clkr = { 1909184fdd87SKonrad Dybcio .enable_reg = 0x59034, 1910184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1911184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1912184fdd87SKonrad Dybcio .name = "gcc_camss_csi1phytimer_clk", 1913*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 1914*5d0e6922SDmitry Baryshkov &gcc_camss_csi1phytimer_clk_src.clkr.hw, 1915184fdd87SKonrad Dybcio }, 1916184fdd87SKonrad Dybcio .num_parents = 1, 1917184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1918184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1919184fdd87SKonrad Dybcio }, 1920184fdd87SKonrad Dybcio }, 1921184fdd87SKonrad Dybcio }; 1922184fdd87SKonrad Dybcio 1923184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_csi2phytimer_clk = { 1924184fdd87SKonrad Dybcio .halt_reg = 0x59050, 1925184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1926184fdd87SKonrad Dybcio .clkr = { 1927184fdd87SKonrad Dybcio .enable_reg = 0x59050, 1928184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1929184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1930184fdd87SKonrad Dybcio .name = "gcc_camss_csi2phytimer_clk", 1931*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 1932*5d0e6922SDmitry Baryshkov &gcc_camss_csi2phytimer_clk_src.clkr.hw, 1933184fdd87SKonrad Dybcio }, 1934184fdd87SKonrad Dybcio .num_parents = 1, 1935184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1936184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1937184fdd87SKonrad Dybcio }, 1938184fdd87SKonrad Dybcio }, 1939184fdd87SKonrad Dybcio }; 1940184fdd87SKonrad Dybcio 1941184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_csi3phytimer_clk = { 1942184fdd87SKonrad Dybcio .halt_reg = 0x5906c, 1943184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1944184fdd87SKonrad Dybcio .clkr = { 1945184fdd87SKonrad Dybcio .enable_reg = 0x5906c, 1946184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1947184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1948184fdd87SKonrad Dybcio .name = "gcc_camss_csi3phytimer_clk", 1949*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 1950*5d0e6922SDmitry Baryshkov &gcc_camss_csi3phytimer_clk_src.clkr.hw, 1951184fdd87SKonrad Dybcio }, 1952184fdd87SKonrad Dybcio .num_parents = 1, 1953184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1954184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1955184fdd87SKonrad Dybcio }, 1956184fdd87SKonrad Dybcio }, 1957184fdd87SKonrad Dybcio }; 1958184fdd87SKonrad Dybcio 1959184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_mclk0_clk = { 1960184fdd87SKonrad Dybcio .halt_reg = 0x51018, 1961184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1962184fdd87SKonrad Dybcio .clkr = { 1963184fdd87SKonrad Dybcio .enable_reg = 0x51018, 1964184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1965184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1966184fdd87SKonrad Dybcio .name = "gcc_camss_mclk0_clk", 1967*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 1968*5d0e6922SDmitry Baryshkov &gcc_camss_mclk0_clk_src.clkr.hw, 1969184fdd87SKonrad Dybcio }, 1970184fdd87SKonrad Dybcio .num_parents = 1, 1971184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1972184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1973184fdd87SKonrad Dybcio }, 1974184fdd87SKonrad Dybcio }, 1975184fdd87SKonrad Dybcio }; 1976184fdd87SKonrad Dybcio 1977184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_mclk1_clk = { 1978184fdd87SKonrad Dybcio .halt_reg = 0x51034, 1979184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1980184fdd87SKonrad Dybcio .clkr = { 1981184fdd87SKonrad Dybcio .enable_reg = 0x51034, 1982184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1983184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1984184fdd87SKonrad Dybcio .name = "gcc_camss_mclk1_clk", 1985*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 1986*5d0e6922SDmitry Baryshkov &gcc_camss_mclk1_clk_src.clkr.hw, 1987184fdd87SKonrad Dybcio }, 1988184fdd87SKonrad Dybcio .num_parents = 1, 1989184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1990184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1991184fdd87SKonrad Dybcio }, 1992184fdd87SKonrad Dybcio }, 1993184fdd87SKonrad Dybcio }; 1994184fdd87SKonrad Dybcio 1995184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_mclk2_clk = { 1996184fdd87SKonrad Dybcio .halt_reg = 0x51050, 1997184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1998184fdd87SKonrad Dybcio .clkr = { 1999184fdd87SKonrad Dybcio .enable_reg = 0x51050, 2000184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2001184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2002184fdd87SKonrad Dybcio .name = "gcc_camss_mclk2_clk", 2003*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2004*5d0e6922SDmitry Baryshkov &gcc_camss_mclk2_clk_src.clkr.hw, 2005184fdd87SKonrad Dybcio }, 2006184fdd87SKonrad Dybcio .num_parents = 1, 2007184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2008184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2009184fdd87SKonrad Dybcio }, 2010184fdd87SKonrad Dybcio }, 2011184fdd87SKonrad Dybcio }; 2012184fdd87SKonrad Dybcio 2013184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_mclk3_clk = { 2014184fdd87SKonrad Dybcio .halt_reg = 0x5106c, 2015184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2016184fdd87SKonrad Dybcio .clkr = { 2017184fdd87SKonrad Dybcio .enable_reg = 0x5106c, 2018184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2019184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2020184fdd87SKonrad Dybcio .name = "gcc_camss_mclk3_clk", 2021*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2022*5d0e6922SDmitry Baryshkov &gcc_camss_mclk3_clk_src.clkr.hw, 2023184fdd87SKonrad Dybcio }, 2024184fdd87SKonrad Dybcio .num_parents = 1, 2025184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2026184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2027184fdd87SKonrad Dybcio }, 2028184fdd87SKonrad Dybcio }, 2029184fdd87SKonrad Dybcio }; 2030184fdd87SKonrad Dybcio 2031184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_mclk4_clk = { 2032184fdd87SKonrad Dybcio .halt_reg = 0x51088, 2033184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2034184fdd87SKonrad Dybcio .clkr = { 2035184fdd87SKonrad Dybcio .enable_reg = 0x51088, 2036184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2037184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2038184fdd87SKonrad Dybcio .name = "gcc_camss_mclk4_clk", 2039*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2040*5d0e6922SDmitry Baryshkov &gcc_camss_mclk4_clk_src.clkr.hw, 2041184fdd87SKonrad Dybcio }, 2042184fdd87SKonrad Dybcio .num_parents = 1, 2043184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2044184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2045184fdd87SKonrad Dybcio }, 2046184fdd87SKonrad Dybcio }, 2047184fdd87SKonrad Dybcio }; 2048184fdd87SKonrad Dybcio 2049184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_nrt_axi_clk = { 2050184fdd87SKonrad Dybcio .halt_reg = 0x58054, 2051184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2052184fdd87SKonrad Dybcio .clkr = { 2053184fdd87SKonrad Dybcio .enable_reg = 0x58054, 2054184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2055184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2056184fdd87SKonrad Dybcio .name = "gcc_camss_nrt_axi_clk", 2057184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2058184fdd87SKonrad Dybcio }, 2059184fdd87SKonrad Dybcio }, 2060184fdd87SKonrad Dybcio }; 2061184fdd87SKonrad Dybcio 2062184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_ope_ahb_clk = { 2063184fdd87SKonrad Dybcio .halt_reg = 0x5503c, 2064184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2065184fdd87SKonrad Dybcio .clkr = { 2066184fdd87SKonrad Dybcio .enable_reg = 0x5503c, 2067184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2068184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2069184fdd87SKonrad Dybcio .name = "gcc_camss_ope_ahb_clk", 2070*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2071*5d0e6922SDmitry Baryshkov &gcc_camss_ope_ahb_clk_src.clkr.hw, 2072184fdd87SKonrad Dybcio }, 2073184fdd87SKonrad Dybcio .num_parents = 1, 2074184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2075184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2076184fdd87SKonrad Dybcio }, 2077184fdd87SKonrad Dybcio }, 2078184fdd87SKonrad Dybcio }; 2079184fdd87SKonrad Dybcio 2080184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_ope_clk = { 2081184fdd87SKonrad Dybcio .halt_reg = 0x5501c, 2082184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2083184fdd87SKonrad Dybcio .clkr = { 2084184fdd87SKonrad Dybcio .enable_reg = 0x5501c, 2085184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2086184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2087184fdd87SKonrad Dybcio .name = "gcc_camss_ope_clk", 2088*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2089*5d0e6922SDmitry Baryshkov &gcc_camss_ope_clk_src.clkr.hw, 2090184fdd87SKonrad Dybcio }, 2091184fdd87SKonrad Dybcio .num_parents = 1, 2092184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2093184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2094184fdd87SKonrad Dybcio }, 2095184fdd87SKonrad Dybcio }, 2096184fdd87SKonrad Dybcio }; 2097184fdd87SKonrad Dybcio 2098184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_rt_axi_clk = { 2099184fdd87SKonrad Dybcio .halt_reg = 0x5805c, 2100184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2101184fdd87SKonrad Dybcio .clkr = { 2102184fdd87SKonrad Dybcio .enable_reg = 0x5805c, 2103184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2104184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2105184fdd87SKonrad Dybcio .name = "gcc_camss_rt_axi_clk", 2106184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2107184fdd87SKonrad Dybcio }, 2108184fdd87SKonrad Dybcio }, 2109184fdd87SKonrad Dybcio }; 2110184fdd87SKonrad Dybcio 2111184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_tfe_0_clk = { 2112184fdd87SKonrad Dybcio .halt_reg = 0x5201c, 2113184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2114184fdd87SKonrad Dybcio .clkr = { 2115184fdd87SKonrad Dybcio .enable_reg = 0x5201c, 2116184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2117184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2118184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_0_clk", 2119*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2120*5d0e6922SDmitry Baryshkov &gcc_camss_tfe_0_clk_src.clkr.hw, 2121184fdd87SKonrad Dybcio }, 2122184fdd87SKonrad Dybcio .num_parents = 1, 2123184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2124184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2125184fdd87SKonrad Dybcio }, 2126184fdd87SKonrad Dybcio }, 2127184fdd87SKonrad Dybcio }; 2128184fdd87SKonrad Dybcio 2129184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = { 2130184fdd87SKonrad Dybcio .halt_reg = 0x5207c, 2131184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2132184fdd87SKonrad Dybcio .clkr = { 2133184fdd87SKonrad Dybcio .enable_reg = 0x5207c, 2134184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2135184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2136184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_0_cphy_rx_clk", 2137*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2138*5d0e6922SDmitry Baryshkov &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2139184fdd87SKonrad Dybcio }, 2140184fdd87SKonrad Dybcio .num_parents = 1, 2141184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2142184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2143184fdd87SKonrad Dybcio }, 2144184fdd87SKonrad Dybcio }, 2145184fdd87SKonrad Dybcio }; 2146184fdd87SKonrad Dybcio 2147184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_tfe_0_csid_clk = { 2148184fdd87SKonrad Dybcio .halt_reg = 0x520ac, 2149184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2150184fdd87SKonrad Dybcio .clkr = { 2151184fdd87SKonrad Dybcio .enable_reg = 0x520ac, 2152184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2153184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2154184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_0_csid_clk", 2155*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2156*5d0e6922SDmitry Baryshkov &gcc_camss_tfe_0_csid_clk_src.clkr.hw, 2157184fdd87SKonrad Dybcio }, 2158184fdd87SKonrad Dybcio .num_parents = 1, 2159184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2160184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2161184fdd87SKonrad Dybcio }, 2162184fdd87SKonrad Dybcio }, 2163184fdd87SKonrad Dybcio }; 2164184fdd87SKonrad Dybcio 2165184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_tfe_1_clk = { 2166184fdd87SKonrad Dybcio .halt_reg = 0x5203c, 2167184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2168184fdd87SKonrad Dybcio .clkr = { 2169184fdd87SKonrad Dybcio .enable_reg = 0x5203c, 2170184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2171184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2172184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_1_clk", 2173*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2174*5d0e6922SDmitry Baryshkov &gcc_camss_tfe_1_clk_src.clkr.hw, 2175184fdd87SKonrad Dybcio }, 2176184fdd87SKonrad Dybcio .num_parents = 1, 2177184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2178184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2179184fdd87SKonrad Dybcio }, 2180184fdd87SKonrad Dybcio }, 2181184fdd87SKonrad Dybcio }; 2182184fdd87SKonrad Dybcio 2183184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = { 2184184fdd87SKonrad Dybcio .halt_reg = 0x52080, 2185184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2186184fdd87SKonrad Dybcio .clkr = { 2187184fdd87SKonrad Dybcio .enable_reg = 0x52080, 2188184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2189184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2190184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_1_cphy_rx_clk", 2191*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2192*5d0e6922SDmitry Baryshkov &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2193184fdd87SKonrad Dybcio }, 2194184fdd87SKonrad Dybcio .num_parents = 1, 2195184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2196184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2197184fdd87SKonrad Dybcio }, 2198184fdd87SKonrad Dybcio }, 2199184fdd87SKonrad Dybcio }; 2200184fdd87SKonrad Dybcio 2201184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_tfe_1_csid_clk = { 2202184fdd87SKonrad Dybcio .halt_reg = 0x520cc, 2203184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2204184fdd87SKonrad Dybcio .clkr = { 2205184fdd87SKonrad Dybcio .enable_reg = 0x520cc, 2206184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2207184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2208184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_1_csid_clk", 2209*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2210*5d0e6922SDmitry Baryshkov &gcc_camss_tfe_1_csid_clk_src.clkr.hw, 2211184fdd87SKonrad Dybcio }, 2212184fdd87SKonrad Dybcio .num_parents = 1, 2213184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2214184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2215184fdd87SKonrad Dybcio }, 2216184fdd87SKonrad Dybcio }, 2217184fdd87SKonrad Dybcio }; 2218184fdd87SKonrad Dybcio 2219184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_tfe_2_clk = { 2220184fdd87SKonrad Dybcio .halt_reg = 0x5205c, 2221184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2222184fdd87SKonrad Dybcio .clkr = { 2223184fdd87SKonrad Dybcio .enable_reg = 0x5205c, 2224184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2225184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2226184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_2_clk", 2227*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2228*5d0e6922SDmitry Baryshkov &gcc_camss_tfe_2_clk_src.clkr.hw, 2229184fdd87SKonrad Dybcio }, 2230184fdd87SKonrad Dybcio .num_parents = 1, 2231184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2232184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2233184fdd87SKonrad Dybcio }, 2234184fdd87SKonrad Dybcio }, 2235184fdd87SKonrad Dybcio }; 2236184fdd87SKonrad Dybcio 2237184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_tfe_2_cphy_rx_clk = { 2238184fdd87SKonrad Dybcio .halt_reg = 0x52084, 2239184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2240184fdd87SKonrad Dybcio .clkr = { 2241184fdd87SKonrad Dybcio .enable_reg = 0x52084, 2242184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2243184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2244184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_2_cphy_rx_clk", 2245*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2246*5d0e6922SDmitry Baryshkov &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2247184fdd87SKonrad Dybcio }, 2248184fdd87SKonrad Dybcio .num_parents = 1, 2249184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2250184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2251184fdd87SKonrad Dybcio }, 2252184fdd87SKonrad Dybcio }, 2253184fdd87SKonrad Dybcio }; 2254184fdd87SKonrad Dybcio 2255184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_tfe_2_csid_clk = { 2256184fdd87SKonrad Dybcio .halt_reg = 0x520ec, 2257184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2258184fdd87SKonrad Dybcio .clkr = { 2259184fdd87SKonrad Dybcio .enable_reg = 0x520ec, 2260184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2261184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2262184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_2_csid_clk", 2263*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2264*5d0e6922SDmitry Baryshkov &gcc_camss_tfe_2_csid_clk_src.clkr.hw, 2265184fdd87SKonrad Dybcio }, 2266184fdd87SKonrad Dybcio .num_parents = 1, 2267184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2268184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2269184fdd87SKonrad Dybcio }, 2270184fdd87SKonrad Dybcio }, 2271184fdd87SKonrad Dybcio }; 2272184fdd87SKonrad Dybcio 2273184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_top_ahb_clk = { 2274184fdd87SKonrad Dybcio .halt_reg = 0x58028, 2275184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2276184fdd87SKonrad Dybcio .clkr = { 2277184fdd87SKonrad Dybcio .enable_reg = 0x58028, 2278184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2279184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2280184fdd87SKonrad Dybcio .name = "gcc_camss_top_ahb_clk", 2281*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2282*5d0e6922SDmitry Baryshkov &gcc_camss_top_ahb_clk_src.clkr.hw, 2283184fdd87SKonrad Dybcio }, 2284184fdd87SKonrad Dybcio .num_parents = 1, 2285184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2286184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2287184fdd87SKonrad Dybcio }, 2288184fdd87SKonrad Dybcio }, 2289184fdd87SKonrad Dybcio }; 2290184fdd87SKonrad Dybcio 2291184fdd87SKonrad Dybcio static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 2292184fdd87SKonrad Dybcio .halt_reg = 0x1a084, 2293184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2294184fdd87SKonrad Dybcio .hwcg_reg = 0x1a084, 2295184fdd87SKonrad Dybcio .hwcg_bit = 1, 2296184fdd87SKonrad Dybcio .clkr = { 2297184fdd87SKonrad Dybcio .enable_reg = 0x1a084, 2298184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2299184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2300184fdd87SKonrad Dybcio .name = "gcc_cfg_noc_usb3_prim_axi_clk", 2301*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2302*5d0e6922SDmitry Baryshkov &gcc_usb30_prim_master_clk_src.clkr.hw, 2303184fdd87SKonrad Dybcio }, 2304184fdd87SKonrad Dybcio .num_parents = 1, 2305184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2306184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2307184fdd87SKonrad Dybcio }, 2308184fdd87SKonrad Dybcio }, 2309184fdd87SKonrad Dybcio }; 2310184fdd87SKonrad Dybcio 2311184fdd87SKonrad Dybcio static struct clk_branch gcc_disp_ahb_clk = { 2312184fdd87SKonrad Dybcio .halt_reg = 0x1700c, 2313184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2314184fdd87SKonrad Dybcio .hwcg_reg = 0x1700c, 2315184fdd87SKonrad Dybcio .hwcg_bit = 1, 2316184fdd87SKonrad Dybcio .clkr = { 2317184fdd87SKonrad Dybcio .enable_reg = 0x1700c, 2318184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2319184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2320184fdd87SKonrad Dybcio .name = "gcc_disp_ahb_clk", 2321184fdd87SKonrad Dybcio .flags = CLK_IS_CRITICAL, 2322184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2323184fdd87SKonrad Dybcio }, 2324184fdd87SKonrad Dybcio }, 2325184fdd87SKonrad Dybcio }; 2326184fdd87SKonrad Dybcio 2327184fdd87SKonrad Dybcio static struct clk_regmap_div gcc_disp_gpll0_clk_src = { 2328184fdd87SKonrad Dybcio .reg = 0x17058, 2329184fdd87SKonrad Dybcio .shift = 0, 2330184fdd87SKonrad Dybcio .width = 2, 2331184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data) { 2332184fdd87SKonrad Dybcio .name = "gcc_disp_gpll0_clk_src", 2333184fdd87SKonrad Dybcio .parent_names = 2334184fdd87SKonrad Dybcio (const char *[]){ "gpll0" }, 2335184fdd87SKonrad Dybcio .num_parents = 1, 2336184fdd87SKonrad Dybcio .ops = &clk_regmap_div_ops, 2337184fdd87SKonrad Dybcio }, 2338184fdd87SKonrad Dybcio }; 2339184fdd87SKonrad Dybcio 2340184fdd87SKonrad Dybcio static struct clk_branch gcc_disp_gpll0_div_clk_src = { 2341184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_DELAY, 2342184fdd87SKonrad Dybcio .clkr = { 2343184fdd87SKonrad Dybcio .enable_reg = 0x79004, 2344184fdd87SKonrad Dybcio .enable_mask = BIT(20), 2345184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2346184fdd87SKonrad Dybcio .name = "gcc_disp_gpll0_div_clk_src", 2347*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2348*5d0e6922SDmitry Baryshkov &gcc_disp_gpll0_clk_src.clkr.hw, 2349184fdd87SKonrad Dybcio }, 2350184fdd87SKonrad Dybcio .num_parents = 1, 2351184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2352184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2353184fdd87SKonrad Dybcio }, 2354184fdd87SKonrad Dybcio }, 2355184fdd87SKonrad Dybcio }; 2356184fdd87SKonrad Dybcio 2357184fdd87SKonrad Dybcio static struct clk_branch gcc_disp_hf_axi_clk = { 2358184fdd87SKonrad Dybcio .halt_reg = 0x17020, 2359184fdd87SKonrad Dybcio .halt_check = BRANCH_VOTED, 2360184fdd87SKonrad Dybcio .hwcg_reg = 0x17020, 2361184fdd87SKonrad Dybcio .hwcg_bit = 1, 2362184fdd87SKonrad Dybcio .clkr = { 2363184fdd87SKonrad Dybcio .enable_reg = 0x17020, 2364184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2365184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2366184fdd87SKonrad Dybcio .name = "gcc_disp_hf_axi_clk", 2367184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2368184fdd87SKonrad Dybcio }, 2369184fdd87SKonrad Dybcio }, 2370184fdd87SKonrad Dybcio }; 2371184fdd87SKonrad Dybcio 2372184fdd87SKonrad Dybcio static struct clk_branch gcc_disp_sleep_clk = { 2373184fdd87SKonrad Dybcio .halt_reg = 0x17074, 2374184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2375184fdd87SKonrad Dybcio .hwcg_reg = 0x17074, 2376184fdd87SKonrad Dybcio .hwcg_bit = 1, 2377184fdd87SKonrad Dybcio .clkr = { 2378184fdd87SKonrad Dybcio .enable_reg = 0x17074, 2379184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2380184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2381184fdd87SKonrad Dybcio .name = "gcc_disp_sleep_clk", 2382184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2383184fdd87SKonrad Dybcio }, 2384184fdd87SKonrad Dybcio }, 2385184fdd87SKonrad Dybcio }; 2386184fdd87SKonrad Dybcio 2387184fdd87SKonrad Dybcio static struct clk_branch gcc_disp_throttle_core_clk = { 2388184fdd87SKonrad Dybcio .halt_reg = 0x17064, 2389184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2390184fdd87SKonrad Dybcio .hwcg_reg = 0x17064, 2391184fdd87SKonrad Dybcio .hwcg_bit = 1, 2392184fdd87SKonrad Dybcio .clkr = { 2393184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2394184fdd87SKonrad Dybcio .enable_mask = BIT(5), 2395184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2396184fdd87SKonrad Dybcio .name = "gcc_disp_throttle_core_clk", 2397184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2398184fdd87SKonrad Dybcio }, 2399184fdd87SKonrad Dybcio }, 2400184fdd87SKonrad Dybcio }; 2401184fdd87SKonrad Dybcio 2402184fdd87SKonrad Dybcio static struct clk_branch gcc_gp1_clk = { 2403184fdd87SKonrad Dybcio .halt_reg = 0x4d000, 2404184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2405184fdd87SKonrad Dybcio .clkr = { 2406184fdd87SKonrad Dybcio .enable_reg = 0x4d000, 2407184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2408184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2409184fdd87SKonrad Dybcio .name = "gcc_gp1_clk", 2410*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2411*5d0e6922SDmitry Baryshkov &gcc_gp1_clk_src.clkr.hw, 2412184fdd87SKonrad Dybcio }, 2413184fdd87SKonrad Dybcio .num_parents = 1, 2414184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2415184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2416184fdd87SKonrad Dybcio }, 2417184fdd87SKonrad Dybcio }, 2418184fdd87SKonrad Dybcio }; 2419184fdd87SKonrad Dybcio 2420184fdd87SKonrad Dybcio static struct clk_branch gcc_gp2_clk = { 2421184fdd87SKonrad Dybcio .halt_reg = 0x4e000, 2422184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2423184fdd87SKonrad Dybcio .clkr = { 2424184fdd87SKonrad Dybcio .enable_reg = 0x4e000, 2425184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2426184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2427184fdd87SKonrad Dybcio .name = "gcc_gp2_clk", 2428*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2429*5d0e6922SDmitry Baryshkov &gcc_gp2_clk_src.clkr.hw, 2430184fdd87SKonrad Dybcio }, 2431184fdd87SKonrad Dybcio .num_parents = 1, 2432184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2433184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2434184fdd87SKonrad Dybcio }, 2435184fdd87SKonrad Dybcio }, 2436184fdd87SKonrad Dybcio }; 2437184fdd87SKonrad Dybcio 2438184fdd87SKonrad Dybcio static struct clk_branch gcc_gp3_clk = { 2439184fdd87SKonrad Dybcio .halt_reg = 0x4f000, 2440184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2441184fdd87SKonrad Dybcio .clkr = { 2442184fdd87SKonrad Dybcio .enable_reg = 0x4f000, 2443184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2444184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2445184fdd87SKonrad Dybcio .name = "gcc_gp3_clk", 2446*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2447*5d0e6922SDmitry Baryshkov &gcc_gp3_clk_src.clkr.hw, 2448184fdd87SKonrad Dybcio }, 2449184fdd87SKonrad Dybcio .num_parents = 1, 2450184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2451184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2452184fdd87SKonrad Dybcio }, 2453184fdd87SKonrad Dybcio }, 2454184fdd87SKonrad Dybcio }; 2455184fdd87SKonrad Dybcio 2456184fdd87SKonrad Dybcio static struct clk_branch gcc_gpu_cfg_ahb_clk = { 2457184fdd87SKonrad Dybcio .halt_reg = 0x36004, 2458184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2459184fdd87SKonrad Dybcio .hwcg_reg = 0x36004, 2460184fdd87SKonrad Dybcio .hwcg_bit = 1, 2461184fdd87SKonrad Dybcio .clkr = { 2462184fdd87SKonrad Dybcio .enable_reg = 0x36004, 2463184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2464184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2465184fdd87SKonrad Dybcio .name = "gcc_gpu_cfg_ahb_clk", 2466184fdd87SKonrad Dybcio .flags = CLK_IS_CRITICAL, 2467184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2468184fdd87SKonrad Dybcio }, 2469184fdd87SKonrad Dybcio }, 2470184fdd87SKonrad Dybcio }; 2471184fdd87SKonrad Dybcio 2472184fdd87SKonrad Dybcio static struct clk_branch gcc_gpu_gpll0_clk_src = { 2473184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_DELAY, 2474184fdd87SKonrad Dybcio .clkr = { 2475184fdd87SKonrad Dybcio .enable_reg = 0x79004, 2476184fdd87SKonrad Dybcio .enable_mask = BIT(15), 2477184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2478184fdd87SKonrad Dybcio .name = "gcc_gpu_gpll0_clk_src", 2479*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2480*5d0e6922SDmitry Baryshkov &gpll0.clkr.hw, 2481184fdd87SKonrad Dybcio }, 2482184fdd87SKonrad Dybcio .num_parents = 1, 2483184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2484184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2485184fdd87SKonrad Dybcio }, 2486184fdd87SKonrad Dybcio }, 2487184fdd87SKonrad Dybcio }; 2488184fdd87SKonrad Dybcio 2489184fdd87SKonrad Dybcio static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 2490184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_DELAY, 2491184fdd87SKonrad Dybcio .clkr = { 2492184fdd87SKonrad Dybcio .enable_reg = 0x79004, 2493184fdd87SKonrad Dybcio .enable_mask = BIT(16), 2494184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2495184fdd87SKonrad Dybcio .name = "gcc_gpu_gpll0_div_clk_src", 2496*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2497*5d0e6922SDmitry Baryshkov &gpll0_out_even.clkr.hw, 2498184fdd87SKonrad Dybcio }, 2499184fdd87SKonrad Dybcio .num_parents = 1, 2500184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2501184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2502184fdd87SKonrad Dybcio }, 2503184fdd87SKonrad Dybcio }, 2504184fdd87SKonrad Dybcio }; 2505184fdd87SKonrad Dybcio 2506184fdd87SKonrad Dybcio static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 2507184fdd87SKonrad Dybcio .halt_reg = 0x3600c, 2508184fdd87SKonrad Dybcio .halt_check = BRANCH_VOTED, 2509184fdd87SKonrad Dybcio .hwcg_reg = 0x3600c, 2510184fdd87SKonrad Dybcio .hwcg_bit = 1, 2511184fdd87SKonrad Dybcio .clkr = { 2512184fdd87SKonrad Dybcio .enable_reg = 0x3600c, 2513184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2514184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2515184fdd87SKonrad Dybcio .name = "gcc_gpu_memnoc_gfx_clk", 2516184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2517184fdd87SKonrad Dybcio }, 2518184fdd87SKonrad Dybcio }, 2519184fdd87SKonrad Dybcio }; 2520184fdd87SKonrad Dybcio 2521184fdd87SKonrad Dybcio static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2522184fdd87SKonrad Dybcio .halt_reg = 0x36018, 2523184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2524184fdd87SKonrad Dybcio .clkr = { 2525184fdd87SKonrad Dybcio .enable_reg = 0x36018, 2526184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2527184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2528184fdd87SKonrad Dybcio .name = "gcc_gpu_snoc_dvm_gfx_clk", 2529184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2530184fdd87SKonrad Dybcio }, 2531184fdd87SKonrad Dybcio }, 2532184fdd87SKonrad Dybcio }; 2533184fdd87SKonrad Dybcio 2534184fdd87SKonrad Dybcio static struct clk_branch gcc_gpu_throttle_core_clk = { 2535184fdd87SKonrad Dybcio .halt_reg = 0x36048, 2536184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2537184fdd87SKonrad Dybcio .hwcg_reg = 0x36048, 2538184fdd87SKonrad Dybcio .hwcg_bit = 1, 2539184fdd87SKonrad Dybcio .clkr = { 2540184fdd87SKonrad Dybcio .enable_reg = 0x79004, 2541184fdd87SKonrad Dybcio .enable_mask = BIT(31), 2542184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2543184fdd87SKonrad Dybcio .name = "gcc_gpu_throttle_core_clk", 2544184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2545184fdd87SKonrad Dybcio }, 2546184fdd87SKonrad Dybcio }, 2547184fdd87SKonrad Dybcio }; 2548184fdd87SKonrad Dybcio 2549184fdd87SKonrad Dybcio static struct clk_branch gcc_pdm2_clk = { 2550184fdd87SKonrad Dybcio .halt_reg = 0x2000c, 2551184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2552184fdd87SKonrad Dybcio .clkr = { 2553184fdd87SKonrad Dybcio .enable_reg = 0x2000c, 2554184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2555184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2556184fdd87SKonrad Dybcio .name = "gcc_pdm2_clk", 2557*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2558*5d0e6922SDmitry Baryshkov &gcc_pdm2_clk_src.clkr.hw, 2559184fdd87SKonrad Dybcio }, 2560184fdd87SKonrad Dybcio .num_parents = 1, 2561184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2562184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2563184fdd87SKonrad Dybcio }, 2564184fdd87SKonrad Dybcio }, 2565184fdd87SKonrad Dybcio }; 2566184fdd87SKonrad Dybcio 2567184fdd87SKonrad Dybcio static struct clk_branch gcc_pdm_ahb_clk = { 2568184fdd87SKonrad Dybcio .halt_reg = 0x20004, 2569184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2570184fdd87SKonrad Dybcio .hwcg_reg = 0x20004, 2571184fdd87SKonrad Dybcio .hwcg_bit = 1, 2572184fdd87SKonrad Dybcio .clkr = { 2573184fdd87SKonrad Dybcio .enable_reg = 0x20004, 2574184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2575184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2576184fdd87SKonrad Dybcio .name = "gcc_pdm_ahb_clk", 2577184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2578184fdd87SKonrad Dybcio }, 2579184fdd87SKonrad Dybcio }, 2580184fdd87SKonrad Dybcio }; 2581184fdd87SKonrad Dybcio 2582184fdd87SKonrad Dybcio static struct clk_branch gcc_pdm_xo4_clk = { 2583184fdd87SKonrad Dybcio .halt_reg = 0x20008, 2584184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2585184fdd87SKonrad Dybcio .clkr = { 2586184fdd87SKonrad Dybcio .enable_reg = 0x20008, 2587184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2588184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2589184fdd87SKonrad Dybcio .name = "gcc_pdm_xo4_clk", 2590184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2591184fdd87SKonrad Dybcio }, 2592184fdd87SKonrad Dybcio }, 2593184fdd87SKonrad Dybcio }; 2594184fdd87SKonrad Dybcio 2595184fdd87SKonrad Dybcio static struct clk_branch gcc_prng_ahb_clk = { 2596184fdd87SKonrad Dybcio .halt_reg = 0x21004, 2597184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2598184fdd87SKonrad Dybcio .hwcg_reg = 0x21004, 2599184fdd87SKonrad Dybcio .hwcg_bit = 1, 2600184fdd87SKonrad Dybcio .clkr = { 2601184fdd87SKonrad Dybcio .enable_reg = 0x79004, 2602184fdd87SKonrad Dybcio .enable_mask = BIT(13), 2603184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2604184fdd87SKonrad Dybcio .name = "gcc_prng_ahb_clk", 2605184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2606184fdd87SKonrad Dybcio }, 2607184fdd87SKonrad Dybcio }, 2608184fdd87SKonrad Dybcio }; 2609184fdd87SKonrad Dybcio 2610184fdd87SKonrad Dybcio static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2611184fdd87SKonrad Dybcio .halt_reg = 0x17014, 2612184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2613184fdd87SKonrad Dybcio .hwcg_reg = 0x17014, 2614184fdd87SKonrad Dybcio .hwcg_bit = 1, 2615184fdd87SKonrad Dybcio .clkr = { 2616184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2617184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2618184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2619184fdd87SKonrad Dybcio .name = "gcc_qmip_camera_nrt_ahb_clk", 2620184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2621184fdd87SKonrad Dybcio }, 2622184fdd87SKonrad Dybcio }, 2623184fdd87SKonrad Dybcio }; 2624184fdd87SKonrad Dybcio 2625184fdd87SKonrad Dybcio static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2626184fdd87SKonrad Dybcio .halt_reg = 0x17060, 2627184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2628184fdd87SKonrad Dybcio .hwcg_reg = 0x17060, 2629184fdd87SKonrad Dybcio .hwcg_bit = 1, 2630184fdd87SKonrad Dybcio .clkr = { 2631184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2632184fdd87SKonrad Dybcio .enable_mask = BIT(2), 2633184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2634184fdd87SKonrad Dybcio .name = "gcc_qmip_camera_rt_ahb_clk", 2635184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2636184fdd87SKonrad Dybcio }, 2637184fdd87SKonrad Dybcio }, 2638184fdd87SKonrad Dybcio }; 2639184fdd87SKonrad Dybcio 2640184fdd87SKonrad Dybcio static struct clk_branch gcc_qmip_disp_ahb_clk = { 2641184fdd87SKonrad Dybcio .halt_reg = 0x17018, 2642184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2643184fdd87SKonrad Dybcio .hwcg_reg = 0x17018, 2644184fdd87SKonrad Dybcio .hwcg_bit = 1, 2645184fdd87SKonrad Dybcio .clkr = { 2646184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2647184fdd87SKonrad Dybcio .enable_mask = BIT(1), 2648184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2649184fdd87SKonrad Dybcio .name = "gcc_qmip_disp_ahb_clk", 2650184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2651184fdd87SKonrad Dybcio }, 2652184fdd87SKonrad Dybcio }, 2653184fdd87SKonrad Dybcio }; 2654184fdd87SKonrad Dybcio 2655184fdd87SKonrad Dybcio static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = { 2656184fdd87SKonrad Dybcio .halt_reg = 0x36040, 2657184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2658184fdd87SKonrad Dybcio .hwcg_reg = 0x36040, 2659184fdd87SKonrad Dybcio .hwcg_bit = 1, 2660184fdd87SKonrad Dybcio .clkr = { 2661184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2662184fdd87SKonrad Dybcio .enable_mask = BIT(4), 2663184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2664184fdd87SKonrad Dybcio .name = "gcc_qmip_gpu_cfg_ahb_clk", 2665184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2666184fdd87SKonrad Dybcio }, 2667184fdd87SKonrad Dybcio }, 2668184fdd87SKonrad Dybcio }; 2669184fdd87SKonrad Dybcio 2670184fdd87SKonrad Dybcio static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2671184fdd87SKonrad Dybcio .halt_reg = 0x17010, 2672184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2673184fdd87SKonrad Dybcio .hwcg_reg = 0x17010, 2674184fdd87SKonrad Dybcio .hwcg_bit = 1, 2675184fdd87SKonrad Dybcio .clkr = { 2676184fdd87SKonrad Dybcio .enable_reg = 0x79004, 2677184fdd87SKonrad Dybcio .enable_mask = BIT(25), 2678184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2679184fdd87SKonrad Dybcio .name = "gcc_qmip_video_vcodec_ahb_clk", 2680184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2681184fdd87SKonrad Dybcio }, 2682184fdd87SKonrad Dybcio }, 2683184fdd87SKonrad Dybcio }; 2684184fdd87SKonrad Dybcio 2685184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2686184fdd87SKonrad Dybcio .halt_reg = 0x1f014, 2687184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2688184fdd87SKonrad Dybcio .clkr = { 2689184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2690184fdd87SKonrad Dybcio .enable_mask = BIT(9), 2691184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2692184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_core_2x_clk", 2693184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2694184fdd87SKonrad Dybcio }, 2695184fdd87SKonrad Dybcio }, 2696184fdd87SKonrad Dybcio }; 2697184fdd87SKonrad Dybcio 2698184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2699184fdd87SKonrad Dybcio .halt_reg = 0x1f00c, 2700184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2701184fdd87SKonrad Dybcio .clkr = { 2702184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2703184fdd87SKonrad Dybcio .enable_mask = BIT(8), 2704184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2705184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_core_clk", 2706184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2707184fdd87SKonrad Dybcio }, 2708184fdd87SKonrad Dybcio }, 2709184fdd87SKonrad Dybcio }; 2710184fdd87SKonrad Dybcio 2711184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2712184fdd87SKonrad Dybcio .halt_reg = 0x1f144, 2713184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2714184fdd87SKonrad Dybcio .clkr = { 2715184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2716184fdd87SKonrad Dybcio .enable_mask = BIT(10), 2717184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2718184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s0_clk", 2719*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2720*5d0e6922SDmitry Baryshkov &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 2721184fdd87SKonrad Dybcio }, 2722184fdd87SKonrad Dybcio .num_parents = 1, 2723184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2724184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2725184fdd87SKonrad Dybcio }, 2726184fdd87SKonrad Dybcio }, 2727184fdd87SKonrad Dybcio }; 2728184fdd87SKonrad Dybcio 2729184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2730184fdd87SKonrad Dybcio .halt_reg = 0x1f274, 2731184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2732184fdd87SKonrad Dybcio .clkr = { 2733184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2734184fdd87SKonrad Dybcio .enable_mask = BIT(11), 2735184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2736184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s1_clk", 2737*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2738*5d0e6922SDmitry Baryshkov &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 2739184fdd87SKonrad Dybcio }, 2740184fdd87SKonrad Dybcio .num_parents = 1, 2741184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2742184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2743184fdd87SKonrad Dybcio }, 2744184fdd87SKonrad Dybcio }, 2745184fdd87SKonrad Dybcio }; 2746184fdd87SKonrad Dybcio 2747184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2748184fdd87SKonrad Dybcio .halt_reg = 0x1f3a4, 2749184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2750184fdd87SKonrad Dybcio .clkr = { 2751184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2752184fdd87SKonrad Dybcio .enable_mask = BIT(12), 2753184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2754184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s2_clk", 2755*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2756*5d0e6922SDmitry Baryshkov &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2757184fdd87SKonrad Dybcio }, 2758184fdd87SKonrad Dybcio .num_parents = 1, 2759184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2760184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2761184fdd87SKonrad Dybcio }, 2762184fdd87SKonrad Dybcio }, 2763184fdd87SKonrad Dybcio }; 2764184fdd87SKonrad Dybcio 2765184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2766184fdd87SKonrad Dybcio .halt_reg = 0x1f4d4, 2767184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2768184fdd87SKonrad Dybcio .clkr = { 2769184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2770184fdd87SKonrad Dybcio .enable_mask = BIT(13), 2771184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2772184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s3_clk", 2773*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2774*5d0e6922SDmitry Baryshkov &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2775184fdd87SKonrad Dybcio }, 2776184fdd87SKonrad Dybcio .num_parents = 1, 2777184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2778184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2779184fdd87SKonrad Dybcio }, 2780184fdd87SKonrad Dybcio }, 2781184fdd87SKonrad Dybcio }; 2782184fdd87SKonrad Dybcio 2783184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2784184fdd87SKonrad Dybcio .halt_reg = 0x1f604, 2785184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2786184fdd87SKonrad Dybcio .clkr = { 2787184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2788184fdd87SKonrad Dybcio .enable_mask = BIT(14), 2789184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2790184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s4_clk", 2791*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2792*5d0e6922SDmitry Baryshkov &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2793184fdd87SKonrad Dybcio }, 2794184fdd87SKonrad Dybcio .num_parents = 1, 2795184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2796184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2797184fdd87SKonrad Dybcio }, 2798184fdd87SKonrad Dybcio }, 2799184fdd87SKonrad Dybcio }; 2800184fdd87SKonrad Dybcio 2801184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2802184fdd87SKonrad Dybcio .halt_reg = 0x1f734, 2803184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2804184fdd87SKonrad Dybcio .clkr = { 2805184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2806184fdd87SKonrad Dybcio .enable_mask = BIT(15), 2807184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2808184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s5_clk", 2809*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2810*5d0e6922SDmitry Baryshkov &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2811184fdd87SKonrad Dybcio }, 2812184fdd87SKonrad Dybcio .num_parents = 1, 2813184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2814184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2815184fdd87SKonrad Dybcio }, 2816184fdd87SKonrad Dybcio }, 2817184fdd87SKonrad Dybcio }; 2818184fdd87SKonrad Dybcio 2819184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2820184fdd87SKonrad Dybcio .halt_reg = 0x53014, 2821184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2822184fdd87SKonrad Dybcio .clkr = { 2823184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2824184fdd87SKonrad Dybcio .enable_mask = BIT(20), 2825184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2826184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_core_2x_clk", 2827184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2828184fdd87SKonrad Dybcio }, 2829184fdd87SKonrad Dybcio }, 2830184fdd87SKonrad Dybcio }; 2831184fdd87SKonrad Dybcio 2832184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2833184fdd87SKonrad Dybcio .halt_reg = 0x5300c, 2834184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2835184fdd87SKonrad Dybcio .clkr = { 2836184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2837184fdd87SKonrad Dybcio .enable_mask = BIT(19), 2838184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2839184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_core_clk", 2840184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2841184fdd87SKonrad Dybcio }, 2842184fdd87SKonrad Dybcio }, 2843184fdd87SKonrad Dybcio }; 2844184fdd87SKonrad Dybcio 2845184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2846184fdd87SKonrad Dybcio .halt_reg = 0x53018, 2847184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2848184fdd87SKonrad Dybcio .clkr = { 2849184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2850184fdd87SKonrad Dybcio .enable_mask = BIT(21), 2851184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2852184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s0_clk", 2853*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2854*5d0e6922SDmitry Baryshkov &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2855184fdd87SKonrad Dybcio }, 2856184fdd87SKonrad Dybcio .num_parents = 1, 2857184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2858184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2859184fdd87SKonrad Dybcio }, 2860184fdd87SKonrad Dybcio }, 2861184fdd87SKonrad Dybcio }; 2862184fdd87SKonrad Dybcio 2863184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2864184fdd87SKonrad Dybcio .halt_reg = 0x53148, 2865184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2866184fdd87SKonrad Dybcio .clkr = { 2867184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2868184fdd87SKonrad Dybcio .enable_mask = BIT(22), 2869184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2870184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s1_clk", 2871*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2872*5d0e6922SDmitry Baryshkov &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2873184fdd87SKonrad Dybcio }, 2874184fdd87SKonrad Dybcio .num_parents = 1, 2875184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2876184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2877184fdd87SKonrad Dybcio }, 2878184fdd87SKonrad Dybcio }, 2879184fdd87SKonrad Dybcio }; 2880184fdd87SKonrad Dybcio 2881184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2882184fdd87SKonrad Dybcio .halt_reg = 0x53278, 2883184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2884184fdd87SKonrad Dybcio .clkr = { 2885184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2886184fdd87SKonrad Dybcio .enable_mask = BIT(23), 2887184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2888184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s2_clk", 2889*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2890*5d0e6922SDmitry Baryshkov &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2891184fdd87SKonrad Dybcio }, 2892184fdd87SKonrad Dybcio .num_parents = 1, 2893184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2894184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2895184fdd87SKonrad Dybcio }, 2896184fdd87SKonrad Dybcio }, 2897184fdd87SKonrad Dybcio }; 2898184fdd87SKonrad Dybcio 2899184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2900184fdd87SKonrad Dybcio .halt_reg = 0x533a8, 2901184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2902184fdd87SKonrad Dybcio .clkr = { 2903184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2904184fdd87SKonrad Dybcio .enable_mask = BIT(24), 2905184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2906184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s3_clk", 2907*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2908*5d0e6922SDmitry Baryshkov &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2909184fdd87SKonrad Dybcio }, 2910184fdd87SKonrad Dybcio .num_parents = 1, 2911184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2912184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2913184fdd87SKonrad Dybcio }, 2914184fdd87SKonrad Dybcio }, 2915184fdd87SKonrad Dybcio }; 2916184fdd87SKonrad Dybcio 2917184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2918184fdd87SKonrad Dybcio .halt_reg = 0x534d8, 2919184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2920184fdd87SKonrad Dybcio .clkr = { 2921184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2922184fdd87SKonrad Dybcio .enable_mask = BIT(25), 2923184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2924184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s4_clk", 2925*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2926*5d0e6922SDmitry Baryshkov &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2927184fdd87SKonrad Dybcio }, 2928184fdd87SKonrad Dybcio .num_parents = 1, 2929184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2930184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2931184fdd87SKonrad Dybcio }, 2932184fdd87SKonrad Dybcio }, 2933184fdd87SKonrad Dybcio }; 2934184fdd87SKonrad Dybcio 2935184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2936184fdd87SKonrad Dybcio .halt_reg = 0x53608, 2937184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2938184fdd87SKonrad Dybcio .clkr = { 2939184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2940184fdd87SKonrad Dybcio .enable_mask = BIT(26), 2941184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2942184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s5_clk", 2943*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 2944*5d0e6922SDmitry Baryshkov &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2945184fdd87SKonrad Dybcio }, 2946184fdd87SKonrad Dybcio .num_parents = 1, 2947184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2948184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2949184fdd87SKonrad Dybcio }, 2950184fdd87SKonrad Dybcio }, 2951184fdd87SKonrad Dybcio }; 2952184fdd87SKonrad Dybcio 2953184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2954184fdd87SKonrad Dybcio .halt_reg = 0x1f004, 2955184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2956184fdd87SKonrad Dybcio .hwcg_reg = 0x1f004, 2957184fdd87SKonrad Dybcio .hwcg_bit = 1, 2958184fdd87SKonrad Dybcio .clkr = { 2959184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2960184fdd87SKonrad Dybcio .enable_mask = BIT(6), 2961184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2962184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2963184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2964184fdd87SKonrad Dybcio }, 2965184fdd87SKonrad Dybcio }, 2966184fdd87SKonrad Dybcio }; 2967184fdd87SKonrad Dybcio 2968184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2969184fdd87SKonrad Dybcio .halt_reg = 0x1f008, 2970184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2971184fdd87SKonrad Dybcio .hwcg_reg = 0x1f008, 2972184fdd87SKonrad Dybcio .hwcg_bit = 1, 2973184fdd87SKonrad Dybcio .clkr = { 2974184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2975184fdd87SKonrad Dybcio .enable_mask = BIT(7), 2976184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2977184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2978184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2979184fdd87SKonrad Dybcio }, 2980184fdd87SKonrad Dybcio }, 2981184fdd87SKonrad Dybcio }; 2982184fdd87SKonrad Dybcio 2983184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2984184fdd87SKonrad Dybcio .halt_reg = 0x53004, 2985184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2986184fdd87SKonrad Dybcio .hwcg_reg = 0x53004, 2987184fdd87SKonrad Dybcio .hwcg_bit = 1, 2988184fdd87SKonrad Dybcio .clkr = { 2989184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2990184fdd87SKonrad Dybcio .enable_mask = BIT(17), 2991184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2992184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2993184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2994184fdd87SKonrad Dybcio }, 2995184fdd87SKonrad Dybcio }, 2996184fdd87SKonrad Dybcio }; 2997184fdd87SKonrad Dybcio 2998184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2999184fdd87SKonrad Dybcio .halt_reg = 0x53008, 3000184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3001184fdd87SKonrad Dybcio .hwcg_reg = 0x53008, 3002184fdd87SKonrad Dybcio .hwcg_bit = 1, 3003184fdd87SKonrad Dybcio .clkr = { 3004184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 3005184fdd87SKonrad Dybcio .enable_mask = BIT(18), 3006184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3007184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap_1_s_ahb_clk", 3008184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3009184fdd87SKonrad Dybcio }, 3010184fdd87SKonrad Dybcio }, 3011184fdd87SKonrad Dybcio }; 3012184fdd87SKonrad Dybcio 3013184fdd87SKonrad Dybcio static struct clk_branch gcc_sdcc1_ahb_clk = { 3014184fdd87SKonrad Dybcio .halt_reg = 0x38008, 3015184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3016184fdd87SKonrad Dybcio .clkr = { 3017184fdd87SKonrad Dybcio .enable_reg = 0x38008, 3018184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3019184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3020184fdd87SKonrad Dybcio .name = "gcc_sdcc1_ahb_clk", 3021184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3022184fdd87SKonrad Dybcio }, 3023184fdd87SKonrad Dybcio }, 3024184fdd87SKonrad Dybcio }; 3025184fdd87SKonrad Dybcio 3026184fdd87SKonrad Dybcio static struct clk_branch gcc_sdcc1_apps_clk = { 3027184fdd87SKonrad Dybcio .halt_reg = 0x38004, 3028184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3029184fdd87SKonrad Dybcio .clkr = { 3030184fdd87SKonrad Dybcio .enable_reg = 0x38004, 3031184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3032184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3033184fdd87SKonrad Dybcio .name = "gcc_sdcc1_apps_clk", 3034*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 3035*5d0e6922SDmitry Baryshkov &gcc_sdcc1_apps_clk_src.clkr.hw, 3036184fdd87SKonrad Dybcio }, 3037184fdd87SKonrad Dybcio .num_parents = 1, 3038184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3039184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3040184fdd87SKonrad Dybcio }, 3041184fdd87SKonrad Dybcio }, 3042184fdd87SKonrad Dybcio }; 3043184fdd87SKonrad Dybcio 3044184fdd87SKonrad Dybcio static struct clk_branch gcc_sdcc1_ice_core_clk = { 3045184fdd87SKonrad Dybcio .halt_reg = 0x3800c, 3046184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3047184fdd87SKonrad Dybcio .hwcg_reg = 0x3800c, 3048184fdd87SKonrad Dybcio .hwcg_bit = 1, 3049184fdd87SKonrad Dybcio .clkr = { 3050184fdd87SKonrad Dybcio .enable_reg = 0x3800c, 3051184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3052184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3053184fdd87SKonrad Dybcio .name = "gcc_sdcc1_ice_core_clk", 3054*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 3055*5d0e6922SDmitry Baryshkov &gcc_sdcc1_ice_core_clk_src.clkr.hw, 3056184fdd87SKonrad Dybcio }, 3057184fdd87SKonrad Dybcio .num_parents = 1, 3058184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3059184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3060184fdd87SKonrad Dybcio }, 3061184fdd87SKonrad Dybcio }, 3062184fdd87SKonrad Dybcio }; 3063184fdd87SKonrad Dybcio 3064184fdd87SKonrad Dybcio static struct clk_branch gcc_sdcc2_ahb_clk = { 3065184fdd87SKonrad Dybcio .halt_reg = 0x1e008, 3066184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3067184fdd87SKonrad Dybcio .clkr = { 3068184fdd87SKonrad Dybcio .enable_reg = 0x1e008, 3069184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3070184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3071184fdd87SKonrad Dybcio .name = "gcc_sdcc2_ahb_clk", 3072184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3073184fdd87SKonrad Dybcio }, 3074184fdd87SKonrad Dybcio }, 3075184fdd87SKonrad Dybcio }; 3076184fdd87SKonrad Dybcio 3077184fdd87SKonrad Dybcio static struct clk_branch gcc_sdcc2_apps_clk = { 3078184fdd87SKonrad Dybcio .halt_reg = 0x1e004, 3079184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3080184fdd87SKonrad Dybcio .clkr = { 3081184fdd87SKonrad Dybcio .enable_reg = 0x1e004, 3082184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3083184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3084184fdd87SKonrad Dybcio .name = "gcc_sdcc2_apps_clk", 3085*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 3086*5d0e6922SDmitry Baryshkov &gcc_sdcc2_apps_clk_src.clkr.hw, 3087184fdd87SKonrad Dybcio }, 3088184fdd87SKonrad Dybcio .num_parents = 1, 3089184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3090184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3091184fdd87SKonrad Dybcio }, 3092184fdd87SKonrad Dybcio }, 3093184fdd87SKonrad Dybcio }; 3094184fdd87SKonrad Dybcio 3095184fdd87SKonrad Dybcio static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 3096184fdd87SKonrad Dybcio .halt_reg = 0x2b06c, 3097184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3098184fdd87SKonrad Dybcio .hwcg_reg = 0x2b06c, 3099184fdd87SKonrad Dybcio .hwcg_bit = 1, 3100184fdd87SKonrad Dybcio .clkr = { 3101184fdd87SKonrad Dybcio .enable_reg = 0x79004, 3102184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3103184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3104184fdd87SKonrad Dybcio .name = "gcc_sys_noc_cpuss_ahb_clk", 3105*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 3106*5d0e6922SDmitry Baryshkov &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, 3107184fdd87SKonrad Dybcio }, 3108184fdd87SKonrad Dybcio .num_parents = 1, 3109184fdd87SKonrad Dybcio .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 3110184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3111184fdd87SKonrad Dybcio }, 3112184fdd87SKonrad Dybcio }, 3113184fdd87SKonrad Dybcio }; 3114184fdd87SKonrad Dybcio 3115184fdd87SKonrad Dybcio static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { 3116184fdd87SKonrad Dybcio .halt_reg = 0x45098, 3117184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3118184fdd87SKonrad Dybcio .clkr = { 3119184fdd87SKonrad Dybcio .enable_reg = 0x45098, 3120184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3121184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3122184fdd87SKonrad Dybcio .name = "gcc_sys_noc_ufs_phy_axi_clk", 3123*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 3124*5d0e6922SDmitry Baryshkov &gcc_ufs_phy_axi_clk_src.clkr.hw, 3125184fdd87SKonrad Dybcio }, 3126184fdd87SKonrad Dybcio .num_parents = 1, 3127184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3128184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3129184fdd87SKonrad Dybcio }, 3130184fdd87SKonrad Dybcio }, 3131184fdd87SKonrad Dybcio }; 3132184fdd87SKonrad Dybcio 3133184fdd87SKonrad Dybcio static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { 3134184fdd87SKonrad Dybcio .halt_reg = 0x1a080, 3135184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3136184fdd87SKonrad Dybcio .hwcg_reg = 0x1a080, 3137184fdd87SKonrad Dybcio .hwcg_bit = 1, 3138184fdd87SKonrad Dybcio .clkr = { 3139184fdd87SKonrad Dybcio .enable_reg = 0x1a080, 3140184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3141184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3142184fdd87SKonrad Dybcio .name = "gcc_sys_noc_usb3_prim_axi_clk", 3143*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 3144*5d0e6922SDmitry Baryshkov &gcc_usb30_prim_master_clk_src.clkr.hw, 3145184fdd87SKonrad Dybcio }, 3146184fdd87SKonrad Dybcio .num_parents = 1, 3147184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3148184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3149184fdd87SKonrad Dybcio }, 3150184fdd87SKonrad Dybcio }, 3151184fdd87SKonrad Dybcio }; 3152184fdd87SKonrad Dybcio 3153184fdd87SKonrad Dybcio static struct clk_branch gcc_ufs_phy_ahb_clk = { 3154184fdd87SKonrad Dybcio .halt_reg = 0x45014, 3155184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3156184fdd87SKonrad Dybcio .hwcg_reg = 0x45014, 3157184fdd87SKonrad Dybcio .hwcg_bit = 1, 3158184fdd87SKonrad Dybcio .clkr = { 3159184fdd87SKonrad Dybcio .enable_reg = 0x45014, 3160184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3161184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3162184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_ahb_clk", 3163184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3164184fdd87SKonrad Dybcio }, 3165184fdd87SKonrad Dybcio }, 3166184fdd87SKonrad Dybcio }; 3167184fdd87SKonrad Dybcio 3168184fdd87SKonrad Dybcio static struct clk_branch gcc_ufs_phy_axi_clk = { 3169184fdd87SKonrad Dybcio .halt_reg = 0x45010, 3170184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3171184fdd87SKonrad Dybcio .hwcg_reg = 0x45010, 3172184fdd87SKonrad Dybcio .hwcg_bit = 1, 3173184fdd87SKonrad Dybcio .clkr = { 3174184fdd87SKonrad Dybcio .enable_reg = 0x45010, 3175184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3176184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3177184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_axi_clk", 3178*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 3179*5d0e6922SDmitry Baryshkov &gcc_ufs_phy_axi_clk_src.clkr.hw, 3180184fdd87SKonrad Dybcio }, 3181184fdd87SKonrad Dybcio .num_parents = 1, 3182184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3183184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3184184fdd87SKonrad Dybcio }, 3185184fdd87SKonrad Dybcio }, 3186184fdd87SKonrad Dybcio }; 3187184fdd87SKonrad Dybcio 3188184fdd87SKonrad Dybcio static struct clk_branch gcc_ufs_phy_ice_core_clk = { 3189184fdd87SKonrad Dybcio .halt_reg = 0x45044, 3190184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3191184fdd87SKonrad Dybcio .hwcg_reg = 0x45044, 3192184fdd87SKonrad Dybcio .hwcg_bit = 1, 3193184fdd87SKonrad Dybcio .clkr = { 3194184fdd87SKonrad Dybcio .enable_reg = 0x45044, 3195184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3196184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3197184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_ice_core_clk", 3198*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 3199*5d0e6922SDmitry Baryshkov &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 3200184fdd87SKonrad Dybcio }, 3201184fdd87SKonrad Dybcio .num_parents = 1, 3202184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3203184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3204184fdd87SKonrad Dybcio }, 3205184fdd87SKonrad Dybcio }, 3206184fdd87SKonrad Dybcio }; 3207184fdd87SKonrad Dybcio 3208184fdd87SKonrad Dybcio static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 3209184fdd87SKonrad Dybcio .halt_reg = 0x45078, 3210184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3211184fdd87SKonrad Dybcio .hwcg_reg = 0x45078, 3212184fdd87SKonrad Dybcio .hwcg_bit = 1, 3213184fdd87SKonrad Dybcio .clkr = { 3214184fdd87SKonrad Dybcio .enable_reg = 0x45078, 3215184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3216184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3217184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_phy_aux_clk", 3218*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 3219*5d0e6922SDmitry Baryshkov &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 3220184fdd87SKonrad Dybcio }, 3221184fdd87SKonrad Dybcio .num_parents = 1, 3222184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3223184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3224184fdd87SKonrad Dybcio }, 3225184fdd87SKonrad Dybcio }, 3226184fdd87SKonrad Dybcio }; 3227184fdd87SKonrad Dybcio 3228184fdd87SKonrad Dybcio static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 3229184fdd87SKonrad Dybcio .halt_reg = 0x4501c, 3230184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_SKIP, 3231184fdd87SKonrad Dybcio .clkr = { 3232184fdd87SKonrad Dybcio .enable_reg = 0x4501c, 3233184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3234184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3235184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_rx_symbol_0_clk", 3236184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3237184fdd87SKonrad Dybcio }, 3238184fdd87SKonrad Dybcio }, 3239184fdd87SKonrad Dybcio }; 3240184fdd87SKonrad Dybcio 3241184fdd87SKonrad Dybcio static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 3242184fdd87SKonrad Dybcio .halt_reg = 0x45018, 3243184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_SKIP, 3244184fdd87SKonrad Dybcio .clkr = { 3245184fdd87SKonrad Dybcio .enable_reg = 0x45018, 3246184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3247184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3248184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_tx_symbol_0_clk", 3249184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3250184fdd87SKonrad Dybcio }, 3251184fdd87SKonrad Dybcio }, 3252184fdd87SKonrad Dybcio }; 3253184fdd87SKonrad Dybcio 3254184fdd87SKonrad Dybcio static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 3255184fdd87SKonrad Dybcio .halt_reg = 0x45040, 3256184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3257184fdd87SKonrad Dybcio .hwcg_reg = 0x45040, 3258184fdd87SKonrad Dybcio .hwcg_bit = 1, 3259184fdd87SKonrad Dybcio .clkr = { 3260184fdd87SKonrad Dybcio .enable_reg = 0x45040, 3261184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3262184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3263184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_unipro_core_clk", 3264*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 3265*5d0e6922SDmitry Baryshkov &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 3266184fdd87SKonrad Dybcio }, 3267184fdd87SKonrad Dybcio .num_parents = 1, 3268184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3269184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3270184fdd87SKonrad Dybcio }, 3271184fdd87SKonrad Dybcio }, 3272184fdd87SKonrad Dybcio }; 3273184fdd87SKonrad Dybcio 3274184fdd87SKonrad Dybcio static struct clk_branch gcc_usb30_prim_master_clk = { 3275184fdd87SKonrad Dybcio .halt_reg = 0x1a010, 3276184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3277184fdd87SKonrad Dybcio .clkr = { 3278184fdd87SKonrad Dybcio .enable_reg = 0x1a010, 3279184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3280184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3281184fdd87SKonrad Dybcio .name = "gcc_usb30_prim_master_clk", 3282*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 3283*5d0e6922SDmitry Baryshkov &gcc_usb30_prim_master_clk_src.clkr.hw, 3284184fdd87SKonrad Dybcio }, 3285184fdd87SKonrad Dybcio .num_parents = 1, 3286184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3287184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3288184fdd87SKonrad Dybcio }, 3289184fdd87SKonrad Dybcio }, 3290184fdd87SKonrad Dybcio }; 3291184fdd87SKonrad Dybcio 3292184fdd87SKonrad Dybcio static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 3293184fdd87SKonrad Dybcio .halt_reg = 0x1a018, 3294184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3295184fdd87SKonrad Dybcio .clkr = { 3296184fdd87SKonrad Dybcio .enable_reg = 0x1a018, 3297184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3298184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3299184fdd87SKonrad Dybcio .name = "gcc_usb30_prim_mock_utmi_clk", 3300*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 3301*5d0e6922SDmitry Baryshkov &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 3302184fdd87SKonrad Dybcio }, 3303184fdd87SKonrad Dybcio .num_parents = 1, 3304184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3305184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3306184fdd87SKonrad Dybcio }, 3307184fdd87SKonrad Dybcio }, 3308184fdd87SKonrad Dybcio }; 3309184fdd87SKonrad Dybcio 3310184fdd87SKonrad Dybcio static struct clk_branch gcc_usb30_prim_sleep_clk = { 3311184fdd87SKonrad Dybcio .halt_reg = 0x1a014, 3312184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3313184fdd87SKonrad Dybcio .clkr = { 3314184fdd87SKonrad Dybcio .enable_reg = 0x1a014, 3315184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3316184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3317184fdd87SKonrad Dybcio .name = "gcc_usb30_prim_sleep_clk", 3318184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3319184fdd87SKonrad Dybcio }, 3320184fdd87SKonrad Dybcio }, 3321184fdd87SKonrad Dybcio }; 3322184fdd87SKonrad Dybcio 3323184fdd87SKonrad Dybcio static struct clk_branch gcc_ufs_mem_clkref_clk = { 3324184fdd87SKonrad Dybcio .halt_reg = 0x8c000, 3325184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3326184fdd87SKonrad Dybcio .clkr = { 3327184fdd87SKonrad Dybcio .enable_reg = 0x8c000, 3328184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3329184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3330184fdd87SKonrad Dybcio .name = "gcc_ufs_mem_clkref_clk", 3331184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3332184fdd87SKonrad Dybcio }, 3333184fdd87SKonrad Dybcio }, 3334184fdd87SKonrad Dybcio }; 3335184fdd87SKonrad Dybcio 3336184fdd87SKonrad Dybcio static struct clk_branch gcc_rx5_pcie_clkref_en_clk = { 3337184fdd87SKonrad Dybcio .halt_reg = 0x8c00c, 3338184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3339184fdd87SKonrad Dybcio .clkr = { 3340184fdd87SKonrad Dybcio .enable_reg = 0x8c00c, 3341184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3342184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3343184fdd87SKonrad Dybcio .name = "gcc_rx5_pcie_clkref_en_clk", 3344184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3345184fdd87SKonrad Dybcio }, 3346184fdd87SKonrad Dybcio }, 3347184fdd87SKonrad Dybcio }; 3348184fdd87SKonrad Dybcio 3349184fdd87SKonrad Dybcio static struct clk_branch gcc_usb3_prim_clkref_clk = { 3350184fdd87SKonrad Dybcio .halt_reg = 0x8c010, 3351184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3352184fdd87SKonrad Dybcio .clkr = { 3353184fdd87SKonrad Dybcio .enable_reg = 0x8c010, 3354184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3355184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3356184fdd87SKonrad Dybcio .name = "gcc_usb3_prim_clkref_clk", 3357184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3358184fdd87SKonrad Dybcio }, 3359184fdd87SKonrad Dybcio }, 3360184fdd87SKonrad Dybcio }; 3361184fdd87SKonrad Dybcio 3362184fdd87SKonrad Dybcio static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3363184fdd87SKonrad Dybcio .halt_reg = 0x1a054, 3364184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3365184fdd87SKonrad Dybcio .clkr = { 3366184fdd87SKonrad Dybcio .enable_reg = 0x1a054, 3367184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3368184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3369184fdd87SKonrad Dybcio .name = "gcc_usb3_prim_phy_com_aux_clk", 3370*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 3371*5d0e6922SDmitry Baryshkov &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3372184fdd87SKonrad Dybcio }, 3373184fdd87SKonrad Dybcio .num_parents = 1, 3374184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3375184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3376184fdd87SKonrad Dybcio }, 3377184fdd87SKonrad Dybcio }, 3378184fdd87SKonrad Dybcio }; 3379184fdd87SKonrad Dybcio 3380184fdd87SKonrad Dybcio static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3381184fdd87SKonrad Dybcio .halt_reg = 0x1a058, 3382184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_SKIP, 3383184fdd87SKonrad Dybcio .hwcg_reg = 0x1a058, 3384184fdd87SKonrad Dybcio .hwcg_bit = 1, 3385184fdd87SKonrad Dybcio .clkr = { 3386184fdd87SKonrad Dybcio .enable_reg = 0x1a058, 3387184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3388184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3389184fdd87SKonrad Dybcio .name = "gcc_usb3_prim_phy_pipe_clk", 3390184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3391184fdd87SKonrad Dybcio }, 3392184fdd87SKonrad Dybcio }, 3393184fdd87SKonrad Dybcio }; 3394184fdd87SKonrad Dybcio 3395184fdd87SKonrad Dybcio static struct clk_branch gcc_vcodec0_axi_clk = { 3396184fdd87SKonrad Dybcio .halt_reg = 0x6e008, 3397184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3398184fdd87SKonrad Dybcio .clkr = { 3399184fdd87SKonrad Dybcio .enable_reg = 0x6e008, 3400184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3401184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3402184fdd87SKonrad Dybcio .name = "gcc_vcodec0_axi_clk", 3403184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3404184fdd87SKonrad Dybcio }, 3405184fdd87SKonrad Dybcio }, 3406184fdd87SKonrad Dybcio }; 3407184fdd87SKonrad Dybcio 3408184fdd87SKonrad Dybcio static struct clk_branch gcc_venus_ahb_clk = { 3409184fdd87SKonrad Dybcio .halt_reg = 0x6e010, 3410184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3411184fdd87SKonrad Dybcio .clkr = { 3412184fdd87SKonrad Dybcio .enable_reg = 0x6e010, 3413184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3414184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3415184fdd87SKonrad Dybcio .name = "gcc_venus_ahb_clk", 3416184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3417184fdd87SKonrad Dybcio }, 3418184fdd87SKonrad Dybcio }, 3419184fdd87SKonrad Dybcio }; 3420184fdd87SKonrad Dybcio 3421184fdd87SKonrad Dybcio static struct clk_branch gcc_venus_ctl_axi_clk = { 3422184fdd87SKonrad Dybcio .halt_reg = 0x6e004, 3423184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3424184fdd87SKonrad Dybcio .clkr = { 3425184fdd87SKonrad Dybcio .enable_reg = 0x6e004, 3426184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3427184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3428184fdd87SKonrad Dybcio .name = "gcc_venus_ctl_axi_clk", 3429184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3430184fdd87SKonrad Dybcio }, 3431184fdd87SKonrad Dybcio }, 3432184fdd87SKonrad Dybcio }; 3433184fdd87SKonrad Dybcio 3434184fdd87SKonrad Dybcio static struct clk_branch gcc_video_ahb_clk = { 3435184fdd87SKonrad Dybcio .halt_reg = 0x17004, 3436184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_DELAY, 3437184fdd87SKonrad Dybcio .hwcg_reg = 0x17004, 3438184fdd87SKonrad Dybcio .hwcg_bit = 1, 3439184fdd87SKonrad Dybcio .clkr = { 3440184fdd87SKonrad Dybcio .enable_reg = 0x17004, 3441184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3442184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3443184fdd87SKonrad Dybcio .name = "gcc_video_ahb_clk", 3444184fdd87SKonrad Dybcio .flags = CLK_IS_CRITICAL, 3445184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3446184fdd87SKonrad Dybcio }, 3447184fdd87SKonrad Dybcio }, 3448184fdd87SKonrad Dybcio }; 3449184fdd87SKonrad Dybcio 3450184fdd87SKonrad Dybcio static struct clk_branch gcc_video_axi0_clk = { 3451184fdd87SKonrad Dybcio .halt_reg = 0x1701c, 3452184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3453184fdd87SKonrad Dybcio .hwcg_reg = 0x1701c, 3454184fdd87SKonrad Dybcio .hwcg_bit = 1, 3455184fdd87SKonrad Dybcio .clkr = { 3456184fdd87SKonrad Dybcio .enable_reg = 0x1701c, 3457184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3458184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3459184fdd87SKonrad Dybcio .name = "gcc_video_axi0_clk", 3460184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3461184fdd87SKonrad Dybcio }, 3462184fdd87SKonrad Dybcio }, 3463184fdd87SKonrad Dybcio }; 3464184fdd87SKonrad Dybcio 3465184fdd87SKonrad Dybcio static struct clk_branch gcc_video_throttle_core_clk = { 3466184fdd87SKonrad Dybcio .halt_reg = 0x17068, 3467184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3468184fdd87SKonrad Dybcio .hwcg_reg = 0x17068, 3469184fdd87SKonrad Dybcio .hwcg_bit = 1, 3470184fdd87SKonrad Dybcio .clkr = { 3471184fdd87SKonrad Dybcio .enable_reg = 0x79004, 3472184fdd87SKonrad Dybcio .enable_mask = BIT(28), 3473184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3474184fdd87SKonrad Dybcio .name = "gcc_video_throttle_core_clk", 3475184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3476184fdd87SKonrad Dybcio }, 3477184fdd87SKonrad Dybcio }, 3478184fdd87SKonrad Dybcio }; 3479184fdd87SKonrad Dybcio 3480184fdd87SKonrad Dybcio static struct clk_branch gcc_video_vcodec0_sys_clk = { 3481184fdd87SKonrad Dybcio .halt_reg = 0x580a4, 3482184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3483184fdd87SKonrad Dybcio .hwcg_reg = 0x580a4, 3484184fdd87SKonrad Dybcio .hwcg_bit = 1, 3485184fdd87SKonrad Dybcio .clkr = { 3486184fdd87SKonrad Dybcio .enable_reg = 0x580a4, 3487184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3488184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3489184fdd87SKonrad Dybcio .name = "gcc_video_vcodec0_sys_clk", 3490*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 3491*5d0e6922SDmitry Baryshkov &gcc_video_venus_clk_src.clkr.hw, 3492184fdd87SKonrad Dybcio }, 3493184fdd87SKonrad Dybcio .num_parents = 1, 3494184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3495184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3496184fdd87SKonrad Dybcio }, 3497184fdd87SKonrad Dybcio }, 3498184fdd87SKonrad Dybcio }; 3499184fdd87SKonrad Dybcio 3500184fdd87SKonrad Dybcio static struct clk_branch gcc_video_venus_ctl_clk = { 3501184fdd87SKonrad Dybcio .halt_reg = 0x5808c, 3502184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3503184fdd87SKonrad Dybcio .clkr = { 3504184fdd87SKonrad Dybcio .enable_reg = 0x5808c, 3505184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3506184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3507184fdd87SKonrad Dybcio .name = "gcc_video_venus_ctl_clk", 3508*5d0e6922SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]) { 3509*5d0e6922SDmitry Baryshkov &gcc_video_venus_clk_src.clkr.hw, 3510184fdd87SKonrad Dybcio }, 3511184fdd87SKonrad Dybcio .num_parents = 1, 3512184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3513184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3514184fdd87SKonrad Dybcio }, 3515184fdd87SKonrad Dybcio }, 3516184fdd87SKonrad Dybcio }; 3517184fdd87SKonrad Dybcio 3518184fdd87SKonrad Dybcio static struct clk_branch gcc_video_xo_clk = { 3519184fdd87SKonrad Dybcio .halt_reg = 0x17024, 3520184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3521184fdd87SKonrad Dybcio .clkr = { 3522184fdd87SKonrad Dybcio .enable_reg = 0x17024, 3523184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3524184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3525184fdd87SKonrad Dybcio .name = "gcc_video_xo_clk", 3526184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3527184fdd87SKonrad Dybcio }, 3528184fdd87SKonrad Dybcio }, 3529184fdd87SKonrad Dybcio }; 3530184fdd87SKonrad Dybcio 3531184fdd87SKonrad Dybcio static struct gdsc usb30_prim_gdsc = { 3532184fdd87SKonrad Dybcio .gdscr = 0x1a004, 3533184fdd87SKonrad Dybcio .pd = { 3534184fdd87SKonrad Dybcio .name = "usb30_prim_gdsc", 3535184fdd87SKonrad Dybcio }, 3536184fdd87SKonrad Dybcio .pwrsts = PWRSTS_OFF_ON, 3537184fdd87SKonrad Dybcio }; 3538184fdd87SKonrad Dybcio 3539184fdd87SKonrad Dybcio static struct gdsc ufs_phy_gdsc = { 3540184fdd87SKonrad Dybcio .gdscr = 0x45004, 3541184fdd87SKonrad Dybcio .pd = { 3542184fdd87SKonrad Dybcio .name = "ufs_phy_gdsc", 3543184fdd87SKonrad Dybcio }, 3544184fdd87SKonrad Dybcio .pwrsts = PWRSTS_OFF_ON, 3545184fdd87SKonrad Dybcio }; 3546184fdd87SKonrad Dybcio 3547184fdd87SKonrad Dybcio static struct gdsc camss_top_gdsc = { 3548184fdd87SKonrad Dybcio .gdscr = 0x58004, 3549184fdd87SKonrad Dybcio .pd = { 3550184fdd87SKonrad Dybcio .name = "camss_top_gdsc", 3551184fdd87SKonrad Dybcio }, 3552184fdd87SKonrad Dybcio .pwrsts = PWRSTS_OFF_ON, 3553184fdd87SKonrad Dybcio }; 3554184fdd87SKonrad Dybcio 3555184fdd87SKonrad Dybcio static struct gdsc venus_gdsc = { 3556184fdd87SKonrad Dybcio .gdscr = 0x5807c, 3557184fdd87SKonrad Dybcio .pd = { 3558184fdd87SKonrad Dybcio .name = "venus_gdsc", 3559184fdd87SKonrad Dybcio }, 3560184fdd87SKonrad Dybcio .pwrsts = PWRSTS_OFF_ON, 3561184fdd87SKonrad Dybcio }; 3562184fdd87SKonrad Dybcio 3563184fdd87SKonrad Dybcio static struct gdsc vcodec0_gdsc = { 3564184fdd87SKonrad Dybcio .gdscr = 0x58098, 3565184fdd87SKonrad Dybcio .pd = { 3566184fdd87SKonrad Dybcio .name = "vcodec0_gdsc", 3567184fdd87SKonrad Dybcio }, 3568184fdd87SKonrad Dybcio .pwrsts = PWRSTS_OFF_ON, 3569184fdd87SKonrad Dybcio .flags = HW_CTRL, 3570184fdd87SKonrad Dybcio }; 3571184fdd87SKonrad Dybcio 3572184fdd87SKonrad Dybcio static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = { 3573184fdd87SKonrad Dybcio .gdscr = 0x7d074, 3574184fdd87SKonrad Dybcio .pd = { 3575184fdd87SKonrad Dybcio .name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc", 3576184fdd87SKonrad Dybcio }, 3577184fdd87SKonrad Dybcio .pwrsts = PWRSTS_OFF_ON, 3578184fdd87SKonrad Dybcio .flags = VOTABLE, 3579184fdd87SKonrad Dybcio }; 3580184fdd87SKonrad Dybcio 3581184fdd87SKonrad Dybcio static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = { 3582184fdd87SKonrad Dybcio .gdscr = 0x7d078, 3583184fdd87SKonrad Dybcio .pd = { 3584184fdd87SKonrad Dybcio .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc", 3585184fdd87SKonrad Dybcio }, 3586184fdd87SKonrad Dybcio .pwrsts = PWRSTS_OFF_ON, 3587184fdd87SKonrad Dybcio .flags = VOTABLE, 3588184fdd87SKonrad Dybcio }; 3589184fdd87SKonrad Dybcio 3590184fdd87SKonrad Dybcio static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = { 3591184fdd87SKonrad Dybcio .gdscr = 0x7d060, 3592184fdd87SKonrad Dybcio .pd = { 3593184fdd87SKonrad Dybcio .name = "hlos1_vote_turing_mmu_tbu1_gdsc", 3594184fdd87SKonrad Dybcio }, 3595184fdd87SKonrad Dybcio .pwrsts = PWRSTS_OFF_ON, 3596184fdd87SKonrad Dybcio .flags = VOTABLE, 3597184fdd87SKonrad Dybcio }; 3598184fdd87SKonrad Dybcio 3599184fdd87SKonrad Dybcio static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { 3600184fdd87SKonrad Dybcio .gdscr = 0x7d07c, 3601184fdd87SKonrad Dybcio .pd = { 3602184fdd87SKonrad Dybcio .name = "hlos1_vote_turing_mmu_tbu0_gdsc", 3603184fdd87SKonrad Dybcio }, 3604184fdd87SKonrad Dybcio .pwrsts = PWRSTS_OFF_ON, 3605184fdd87SKonrad Dybcio .flags = VOTABLE, 3606184fdd87SKonrad Dybcio }; 3607184fdd87SKonrad Dybcio 3608184fdd87SKonrad Dybcio static struct clk_regmap *gcc_sm6375_clocks[] = { 3609184fdd87SKonrad Dybcio [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr, 3610184fdd87SKonrad Dybcio [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr, 3611184fdd87SKonrad Dybcio [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr, 3612184fdd87SKonrad Dybcio [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3613184fdd87SKonrad Dybcio [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, 3614184fdd87SKonrad Dybcio [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, 3615184fdd87SKonrad Dybcio [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 3616184fdd87SKonrad Dybcio [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, 3617184fdd87SKonrad Dybcio [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, 3618184fdd87SKonrad Dybcio [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr, 3619184fdd87SKonrad Dybcio [GCC_CAMSS_CCI_0_CLK_SRC] = &gcc_camss_cci_0_clk_src.clkr, 3620184fdd87SKonrad Dybcio [GCC_CAMSS_CCI_1_CLK] = &gcc_camss_cci_1_clk.clkr, 3621184fdd87SKonrad Dybcio [GCC_CAMSS_CCI_1_CLK_SRC] = &gcc_camss_cci_1_clk_src.clkr, 3622184fdd87SKonrad Dybcio [GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr, 3623184fdd87SKonrad Dybcio [GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr, 3624184fdd87SKonrad Dybcio [GCC_CAMSS_CPHY_2_CLK] = &gcc_camss_cphy_2_clk.clkr, 3625184fdd87SKonrad Dybcio [GCC_CAMSS_CPHY_3_CLK] = &gcc_camss_cphy_3_clk.clkr, 3626184fdd87SKonrad Dybcio [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 3627184fdd87SKonrad Dybcio [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr, 3628184fdd87SKonrad Dybcio [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, 3629184fdd87SKonrad Dybcio [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr, 3630184fdd87SKonrad Dybcio [GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr, 3631184fdd87SKonrad Dybcio [GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr, 3632184fdd87SKonrad Dybcio [GCC_CAMSS_CSI3PHYTIMER_CLK] = &gcc_camss_csi3phytimer_clk.clkr, 3633184fdd87SKonrad Dybcio [GCC_CAMSS_CSI3PHYTIMER_CLK_SRC] = &gcc_camss_csi3phytimer_clk_src.clkr, 3634184fdd87SKonrad Dybcio [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 3635184fdd87SKonrad Dybcio [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr, 3636184fdd87SKonrad Dybcio [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 3637184fdd87SKonrad Dybcio [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr, 3638184fdd87SKonrad Dybcio [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, 3639184fdd87SKonrad Dybcio [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr, 3640184fdd87SKonrad Dybcio [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr, 3641184fdd87SKonrad Dybcio [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr, 3642184fdd87SKonrad Dybcio [GCC_CAMSS_MCLK4_CLK] = &gcc_camss_mclk4_clk.clkr, 3643184fdd87SKonrad Dybcio [GCC_CAMSS_MCLK4_CLK_SRC] = &gcc_camss_mclk4_clk_src.clkr, 3644184fdd87SKonrad Dybcio [GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr, 3645184fdd87SKonrad Dybcio [GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr, 3646184fdd87SKonrad Dybcio [GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr, 3647184fdd87SKonrad Dybcio [GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr, 3648184fdd87SKonrad Dybcio [GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr, 3649184fdd87SKonrad Dybcio [GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr, 3650184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr, 3651184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr, 3652184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr, 3653184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr, 3654184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr, 3655184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr, 3656184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr, 3657184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr, 3658184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr, 3659184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr, 3660184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_2_CLK] = &gcc_camss_tfe_2_clk.clkr, 3661184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_2_CLK_SRC] = &gcc_camss_tfe_2_clk_src.clkr, 3662184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_2_CPHY_RX_CLK] = &gcc_camss_tfe_2_cphy_rx_clk.clkr, 3663184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_2_CSID_CLK] = &gcc_camss_tfe_2_csid_clk.clkr, 3664184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_2_CSID_CLK_SRC] = &gcc_camss_tfe_2_csid_clk_src.clkr, 3665184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr, 3666184fdd87SKonrad Dybcio [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 3667184fdd87SKonrad Dybcio [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, 3668184fdd87SKonrad Dybcio [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3669184fdd87SKonrad Dybcio [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, 3670184fdd87SKonrad Dybcio [GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr, 3671184fdd87SKonrad Dybcio [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, 3672184fdd87SKonrad Dybcio [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 3673184fdd87SKonrad Dybcio [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 3674184fdd87SKonrad Dybcio [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3675184fdd87SKonrad Dybcio [GCC_DISP_SLEEP_CLK] = &gcc_disp_sleep_clk.clkr, 3676184fdd87SKonrad Dybcio [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, 3677184fdd87SKonrad Dybcio [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3678184fdd87SKonrad Dybcio [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3679184fdd87SKonrad Dybcio [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3680184fdd87SKonrad Dybcio [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3681184fdd87SKonrad Dybcio [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3682184fdd87SKonrad Dybcio [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3683184fdd87SKonrad Dybcio [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 3684184fdd87SKonrad Dybcio [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3685184fdd87SKonrad Dybcio [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3686184fdd87SKonrad Dybcio [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3687184fdd87SKonrad Dybcio [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3688184fdd87SKonrad Dybcio [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, 3689184fdd87SKonrad Dybcio [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3690184fdd87SKonrad Dybcio [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3691184fdd87SKonrad Dybcio [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3692184fdd87SKonrad Dybcio [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3693184fdd87SKonrad Dybcio [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3694184fdd87SKonrad Dybcio [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3695184fdd87SKonrad Dybcio [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3696184fdd87SKonrad Dybcio [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3697184fdd87SKonrad Dybcio [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr, 3698184fdd87SKonrad Dybcio [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3699184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 3700184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 3701184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3702184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3703184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3704184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3705184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3706184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3707184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3708184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3709184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3710184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3711184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3712184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3713184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3714184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3715184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3716184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3717184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3718184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3719184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3720184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3721184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3722184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3723184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3724184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3725184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3726184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3727184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3728184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3729184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3730184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3731184fdd87SKonrad Dybcio [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3732184fdd87SKonrad Dybcio [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3733184fdd87SKonrad Dybcio [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 3734184fdd87SKonrad Dybcio [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 3735184fdd87SKonrad Dybcio [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 3736184fdd87SKonrad Dybcio [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3737184fdd87SKonrad Dybcio [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3738184fdd87SKonrad Dybcio [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3739184fdd87SKonrad Dybcio [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 3740184fdd87SKonrad Dybcio [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, 3741184fdd87SKonrad Dybcio [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, 3742184fdd87SKonrad Dybcio [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3743184fdd87SKonrad Dybcio [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3744184fdd87SKonrad Dybcio [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3745184fdd87SKonrad Dybcio [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3746184fdd87SKonrad Dybcio [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3747184fdd87SKonrad Dybcio [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3748184fdd87SKonrad Dybcio [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3749184fdd87SKonrad Dybcio [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3750184fdd87SKonrad Dybcio [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3751184fdd87SKonrad Dybcio [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3752184fdd87SKonrad Dybcio [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 3753184fdd87SKonrad Dybcio [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3754184fdd87SKonrad Dybcio [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3755184fdd87SKonrad Dybcio [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3756184fdd87SKonrad Dybcio [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3757184fdd87SKonrad Dybcio [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3758184fdd87SKonrad Dybcio [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3759184fdd87SKonrad Dybcio [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 3760184fdd87SKonrad Dybcio [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3761184fdd87SKonrad Dybcio [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3762184fdd87SKonrad Dybcio [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3763184fdd87SKonrad Dybcio [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr, 3764184fdd87SKonrad Dybcio [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr, 3765184fdd87SKonrad Dybcio [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr, 3766184fdd87SKonrad Dybcio [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 3767184fdd87SKonrad Dybcio [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3768184fdd87SKonrad Dybcio [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, 3769184fdd87SKonrad Dybcio [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr, 3770184fdd87SKonrad Dybcio [GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr, 3771184fdd87SKonrad Dybcio [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr, 3772184fdd87SKonrad Dybcio [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 3773184fdd87SKonrad Dybcio [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, 3774184fdd87SKonrad Dybcio [GCC_RX5_PCIE_CLKREF_EN_CLK] = &gcc_rx5_pcie_clkref_en_clk.clkr, 3775184fdd87SKonrad Dybcio [GPLL0] = &gpll0.clkr, 3776184fdd87SKonrad Dybcio [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 3777184fdd87SKonrad Dybcio [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr, 3778184fdd87SKonrad Dybcio [GPLL1] = &gpll1.clkr, 3779184fdd87SKonrad Dybcio [GPLL10] = &gpll10.clkr, 3780184fdd87SKonrad Dybcio [GPLL11] = &gpll11.clkr, 3781184fdd87SKonrad Dybcio [GPLL3] = &gpll3.clkr, 3782184fdd87SKonrad Dybcio [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr, 3783184fdd87SKonrad Dybcio [GPLL4] = &gpll4.clkr, 3784184fdd87SKonrad Dybcio [GPLL5] = &gpll5.clkr, 3785184fdd87SKonrad Dybcio [GPLL6] = &gpll6.clkr, 3786184fdd87SKonrad Dybcio [GPLL6_OUT_EVEN] = &gpll6_out_even.clkr, 3787184fdd87SKonrad Dybcio [GPLL7] = &gpll7.clkr, 3788184fdd87SKonrad Dybcio [GPLL8] = &gpll8.clkr, 3789184fdd87SKonrad Dybcio [GPLL8_OUT_EVEN] = &gpll8_out_even.clkr, 3790184fdd87SKonrad Dybcio [GPLL9] = &gpll9.clkr, 3791184fdd87SKonrad Dybcio [GPLL9_OUT_MAIN] = &gpll9_out_main.clkr, 3792184fdd87SKonrad Dybcio }; 3793184fdd87SKonrad Dybcio 3794184fdd87SKonrad Dybcio static const struct qcom_reset_map gcc_sm6375_resets[] = { 3795184fdd87SKonrad Dybcio [GCC_MMSS_BCR] = { 0x17000 }, 3796184fdd87SKonrad Dybcio [GCC_USB30_PRIM_BCR] = { 0x1a000 }, 3797184fdd87SKonrad Dybcio [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, 3798184fdd87SKonrad Dybcio [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1b020 }, 3799184fdd87SKonrad Dybcio [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, 3800184fdd87SKonrad Dybcio [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, 3801184fdd87SKonrad Dybcio [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, 3802184fdd87SKonrad Dybcio [GCC_SDCC2_BCR] = { 0x1e000 }, 3803184fdd87SKonrad Dybcio [GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 }, 3804184fdd87SKonrad Dybcio [GCC_PDM_BCR] = { 0x20000 }, 3805184fdd87SKonrad Dybcio [GCC_GPU_BCR] = { 0x36000 }, 3806184fdd87SKonrad Dybcio [GCC_SDCC1_BCR] = { 0x38000 }, 3807184fdd87SKonrad Dybcio [GCC_UFS_PHY_BCR] = { 0x45000 }, 3808184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_BCR] = { 0x52000 }, 3809184fdd87SKonrad Dybcio [GCC_QUPV3_WRAPPER_1_BCR] = { 0x53000 }, 3810184fdd87SKonrad Dybcio [GCC_CAMSS_OPE_BCR] = { 0x55000 }, 3811184fdd87SKonrad Dybcio [GCC_CAMSS_TOP_BCR] = { 0x58000 }, 3812184fdd87SKonrad Dybcio [GCC_VENUS_BCR] = { 0x58078 }, 3813184fdd87SKonrad Dybcio [GCC_VCODEC0_BCR] = { 0x58094 }, 3814184fdd87SKonrad Dybcio [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 }, 3815184fdd87SKonrad Dybcio }; 3816184fdd87SKonrad Dybcio 3817184fdd87SKonrad Dybcio 3818184fdd87SKonrad Dybcio static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3819184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3820184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3821184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3822184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3823184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3824184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3825184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3826184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3827184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 3828184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3829184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3830184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3831184fdd87SKonrad Dybcio }; 3832184fdd87SKonrad Dybcio 3833184fdd87SKonrad Dybcio static struct gdsc *gcc_sm6375_gdscs[] = { 3834184fdd87SKonrad Dybcio [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3835184fdd87SKonrad Dybcio [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3836184fdd87SKonrad Dybcio [CAMSS_TOP_GDSC] = &camss_top_gdsc, 3837184fdd87SKonrad Dybcio [VENUS_GDSC] = &venus_gdsc, 3838184fdd87SKonrad Dybcio [VCODEC0_GDSC] = &vcodec0_gdsc, 3839184fdd87SKonrad Dybcio [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc, 3840184fdd87SKonrad Dybcio [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc, 3841184fdd87SKonrad Dybcio [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc, 3842184fdd87SKonrad Dybcio [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, 3843184fdd87SKonrad Dybcio }; 3844184fdd87SKonrad Dybcio 3845184fdd87SKonrad Dybcio static const struct regmap_config gcc_sm6375_regmap_config = { 3846184fdd87SKonrad Dybcio .reg_bits = 32, 3847184fdd87SKonrad Dybcio .reg_stride = 4, 3848184fdd87SKonrad Dybcio .val_bits = 32, 3849184fdd87SKonrad Dybcio .max_register = 0xc7000, 3850184fdd87SKonrad Dybcio .fast_io = true, 3851184fdd87SKonrad Dybcio }; 3852184fdd87SKonrad Dybcio 3853184fdd87SKonrad Dybcio static const struct qcom_cc_desc gcc_sm6375_desc = { 3854184fdd87SKonrad Dybcio .config = &gcc_sm6375_regmap_config, 3855184fdd87SKonrad Dybcio .clks = gcc_sm6375_clocks, 3856184fdd87SKonrad Dybcio .num_clks = ARRAY_SIZE(gcc_sm6375_clocks), 3857184fdd87SKonrad Dybcio .resets = gcc_sm6375_resets, 3858184fdd87SKonrad Dybcio .num_resets = ARRAY_SIZE(gcc_sm6375_resets), 3859184fdd87SKonrad Dybcio .gdscs = gcc_sm6375_gdscs, 3860184fdd87SKonrad Dybcio .num_gdscs = ARRAY_SIZE(gcc_sm6375_gdscs), 3861184fdd87SKonrad Dybcio }; 3862184fdd87SKonrad Dybcio 3863184fdd87SKonrad Dybcio static const struct of_device_id gcc_sm6375_match_table[] = { 3864184fdd87SKonrad Dybcio { .compatible = "qcom,sm6375-gcc" }, 3865184fdd87SKonrad Dybcio { } 3866184fdd87SKonrad Dybcio }; 3867184fdd87SKonrad Dybcio MODULE_DEVICE_TABLE(of, gcc_sm6375_match_table); 3868184fdd87SKonrad Dybcio 3869184fdd87SKonrad Dybcio static int gcc_sm6375_probe(struct platform_device *pdev) 3870184fdd87SKonrad Dybcio { 3871184fdd87SKonrad Dybcio struct regmap *regmap; 3872184fdd87SKonrad Dybcio int ret; 3873184fdd87SKonrad Dybcio 3874184fdd87SKonrad Dybcio regmap = qcom_cc_map(pdev, &gcc_sm6375_desc); 3875184fdd87SKonrad Dybcio if (IS_ERR(regmap)) 3876184fdd87SKonrad Dybcio return PTR_ERR(regmap); 3877184fdd87SKonrad Dybcio 3878184fdd87SKonrad Dybcio ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); 3879184fdd87SKonrad Dybcio if (ret) 3880184fdd87SKonrad Dybcio return ret; 3881184fdd87SKonrad Dybcio 3882184fdd87SKonrad Dybcio /* 3883184fdd87SKonrad Dybcio * Keep the following clocks always on: 3884184fdd87SKonrad Dybcio * GCC_CAMERA_XO_CLK, GCC_CPUSS_GNOC_CLK, GCC_DISP_XO_CLK 3885184fdd87SKonrad Dybcio */ 3886184fdd87SKonrad Dybcio regmap_update_bits(regmap, 0x17028, BIT(0), BIT(0)); 3887184fdd87SKonrad Dybcio regmap_update_bits(regmap, 0x2b004, BIT(0), BIT(0)); 3888184fdd87SKonrad Dybcio regmap_update_bits(regmap, 0x1702c, BIT(0), BIT(0)); 3889184fdd87SKonrad Dybcio 3890184fdd87SKonrad Dybcio clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config); 3891184fdd87SKonrad Dybcio clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config); 3892184fdd87SKonrad Dybcio clk_lucid_pll_configure(&gpll8, regmap, &gpll8_config); 3893184fdd87SKonrad Dybcio clk_zonda_pll_configure(&gpll9, regmap, &gpll9_config); 3894184fdd87SKonrad Dybcio 3895184fdd87SKonrad Dybcio return qcom_cc_really_probe(pdev, &gcc_sm6375_desc, regmap); 3896184fdd87SKonrad Dybcio } 3897184fdd87SKonrad Dybcio 3898184fdd87SKonrad Dybcio static struct platform_driver gcc_sm6375_driver = { 3899184fdd87SKonrad Dybcio .probe = gcc_sm6375_probe, 3900184fdd87SKonrad Dybcio .driver = { 3901184fdd87SKonrad Dybcio .name = "gcc-sm6375", 3902184fdd87SKonrad Dybcio .of_match_table = gcc_sm6375_match_table, 3903184fdd87SKonrad Dybcio }, 3904184fdd87SKonrad Dybcio }; 3905184fdd87SKonrad Dybcio 3906184fdd87SKonrad Dybcio static int __init gcc_sm6375_init(void) 3907184fdd87SKonrad Dybcio { 3908184fdd87SKonrad Dybcio return platform_driver_register(&gcc_sm6375_driver); 3909184fdd87SKonrad Dybcio } 3910184fdd87SKonrad Dybcio subsys_initcall(gcc_sm6375_init); 3911184fdd87SKonrad Dybcio 3912184fdd87SKonrad Dybcio static void __exit gcc_sm6375_exit(void) 3913184fdd87SKonrad Dybcio { 3914184fdd87SKonrad Dybcio platform_driver_unregister(&gcc_sm6375_driver); 3915184fdd87SKonrad Dybcio } 3916184fdd87SKonrad Dybcio module_exit(gcc_sm6375_exit); 3917184fdd87SKonrad Dybcio 3918184fdd87SKonrad Dybcio MODULE_DESCRIPTION("QTI GCC SM6375 Driver"); 3919184fdd87SKonrad Dybcio MODULE_LICENSE("GPL"); 3920