1*184fdd87SKonrad Dybcio // SPDX-License-Identifier: GPL-2.0-only 2*184fdd87SKonrad Dybcio /* 3*184fdd87SKonrad Dybcio * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4*184fdd87SKonrad Dybcio * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> 5*184fdd87SKonrad Dybcio */ 6*184fdd87SKonrad Dybcio 7*184fdd87SKonrad Dybcio #include <linux/clk-provider.h> 8*184fdd87SKonrad Dybcio #include <linux/module.h> 9*184fdd87SKonrad Dybcio #include <linux/of_device.h> 10*184fdd87SKonrad Dybcio #include <linux/regmap.h> 11*184fdd87SKonrad Dybcio 12*184fdd87SKonrad Dybcio #include <dt-bindings/clock/qcom,sm6375-gcc.h> 13*184fdd87SKonrad Dybcio 14*184fdd87SKonrad Dybcio #include "clk-alpha-pll.h" 15*184fdd87SKonrad Dybcio #include "clk-branch.h" 16*184fdd87SKonrad Dybcio #include "clk-rcg.h" 17*184fdd87SKonrad Dybcio #include "clk-regmap.h" 18*184fdd87SKonrad Dybcio #include "clk-regmap-divider.h" 19*184fdd87SKonrad Dybcio #include "clk-regmap-mux.h" 20*184fdd87SKonrad Dybcio #include "clk-regmap-phy-mux.h" 21*184fdd87SKonrad Dybcio #include "gdsc.h" 22*184fdd87SKonrad Dybcio #include "reset.h" 23*184fdd87SKonrad Dybcio 24*184fdd87SKonrad Dybcio enum { 25*184fdd87SKonrad Dybcio DT_BI_TCXO, 26*184fdd87SKonrad Dybcio DT_BI_TCXO_AO, 27*184fdd87SKonrad Dybcio DT_SLEEP_CLK 28*184fdd87SKonrad Dybcio }; 29*184fdd87SKonrad Dybcio 30*184fdd87SKonrad Dybcio enum { 31*184fdd87SKonrad Dybcio P_BI_TCXO, 32*184fdd87SKonrad Dybcio P_GPLL0_OUT_EVEN, 33*184fdd87SKonrad Dybcio P_GPLL0_OUT_MAIN, 34*184fdd87SKonrad Dybcio P_GPLL0_OUT_ODD, 35*184fdd87SKonrad Dybcio P_GPLL10_OUT_EVEN, 36*184fdd87SKonrad Dybcio P_GPLL11_OUT_EVEN, 37*184fdd87SKonrad Dybcio P_GPLL11_OUT_ODD, 38*184fdd87SKonrad Dybcio P_GPLL3_OUT_EVEN, 39*184fdd87SKonrad Dybcio P_GPLL3_OUT_MAIN, 40*184fdd87SKonrad Dybcio P_GPLL4_OUT_EVEN, 41*184fdd87SKonrad Dybcio P_GPLL5_OUT_EVEN, 42*184fdd87SKonrad Dybcio P_GPLL6_OUT_EVEN, 43*184fdd87SKonrad Dybcio P_GPLL6_OUT_MAIN, 44*184fdd87SKonrad Dybcio P_GPLL7_OUT_EVEN, 45*184fdd87SKonrad Dybcio P_GPLL8_OUT_EVEN, 46*184fdd87SKonrad Dybcio P_GPLL8_OUT_MAIN, 47*184fdd87SKonrad Dybcio P_GPLL9_OUT_EARLY, 48*184fdd87SKonrad Dybcio P_GPLL9_OUT_MAIN, 49*184fdd87SKonrad Dybcio P_SLEEP_CLK, 50*184fdd87SKonrad Dybcio }; 51*184fdd87SKonrad Dybcio 52*184fdd87SKonrad Dybcio static struct pll_vco lucid_vco[] = { 53*184fdd87SKonrad Dybcio { 249600000, 2000000000, 0 }, 54*184fdd87SKonrad Dybcio }; 55*184fdd87SKonrad Dybcio 56*184fdd87SKonrad Dybcio static struct pll_vco zonda_vco[] = { 57*184fdd87SKonrad Dybcio { 595200000, 3600000000, 0 }, 58*184fdd87SKonrad Dybcio }; 59*184fdd87SKonrad Dybcio 60*184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll0 = { 61*184fdd87SKonrad Dybcio .offset = 0x0, 62*184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 63*184fdd87SKonrad Dybcio .clkr = { 64*184fdd87SKonrad Dybcio .enable_reg = 0x79000, 65*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 66*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 67*184fdd87SKonrad Dybcio .name = "gpll0", 68*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 69*184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 70*184fdd87SKonrad Dybcio }, 71*184fdd87SKonrad Dybcio .num_parents = 1, 72*184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_fixed_lucid_ops, 73*184fdd87SKonrad Dybcio }, 74*184fdd87SKonrad Dybcio }, 75*184fdd87SKonrad Dybcio }; 76*184fdd87SKonrad Dybcio 77*184fdd87SKonrad Dybcio static const struct clk_div_table post_div_table_gpll0_out_even[] = { 78*184fdd87SKonrad Dybcio { 0x1, 2 }, 79*184fdd87SKonrad Dybcio { } 80*184fdd87SKonrad Dybcio }; 81*184fdd87SKonrad Dybcio 82*184fdd87SKonrad Dybcio static struct clk_alpha_pll_postdiv gpll0_out_even = { 83*184fdd87SKonrad Dybcio .offset = 0x0, 84*184fdd87SKonrad Dybcio .post_div_shift = 8, 85*184fdd87SKonrad Dybcio .post_div_table = post_div_table_gpll0_out_even, 86*184fdd87SKonrad Dybcio .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even), 87*184fdd87SKonrad Dybcio .width = 4, 88*184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 89*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 90*184fdd87SKonrad Dybcio .name = "gpll0_out_even", 91*184fdd87SKonrad Dybcio .parent_hws = (const struct clk_hw*[]){ 92*184fdd87SKonrad Dybcio &gpll0.clkr.hw, 93*184fdd87SKonrad Dybcio }, 94*184fdd87SKonrad Dybcio .num_parents = 1, 95*184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_postdiv_lucid_ops, 96*184fdd87SKonrad Dybcio }, 97*184fdd87SKonrad Dybcio }; 98*184fdd87SKonrad Dybcio 99*184fdd87SKonrad Dybcio static const struct clk_div_table post_div_table_gpll0_out_odd[] = { 100*184fdd87SKonrad Dybcio { 0x3, 3 }, 101*184fdd87SKonrad Dybcio { } 102*184fdd87SKonrad Dybcio }; 103*184fdd87SKonrad Dybcio 104*184fdd87SKonrad Dybcio static struct clk_alpha_pll_postdiv gpll0_out_odd = { 105*184fdd87SKonrad Dybcio .offset = 0x0, 106*184fdd87SKonrad Dybcio .post_div_shift = 12, 107*184fdd87SKonrad Dybcio .post_div_table = post_div_table_gpll0_out_odd, 108*184fdd87SKonrad Dybcio .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_odd), 109*184fdd87SKonrad Dybcio .width = 4, 110*184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 111*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 112*184fdd87SKonrad Dybcio .name = "gpll0_out_odd", 113*184fdd87SKonrad Dybcio .parent_hws = (const struct clk_hw*[]){ 114*184fdd87SKonrad Dybcio &gpll0.clkr.hw, 115*184fdd87SKonrad Dybcio }, 116*184fdd87SKonrad Dybcio .num_parents = 1, 117*184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_postdiv_lucid_ops, 118*184fdd87SKonrad Dybcio }, 119*184fdd87SKonrad Dybcio }; 120*184fdd87SKonrad Dybcio 121*184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll1 = { 122*184fdd87SKonrad Dybcio .offset = 0x1000, 123*184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 124*184fdd87SKonrad Dybcio .clkr = { 125*184fdd87SKonrad Dybcio .enable_reg = 0x79000, 126*184fdd87SKonrad Dybcio .enable_mask = BIT(1), 127*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 128*184fdd87SKonrad Dybcio .name = "gpll1", 129*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 130*184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 131*184fdd87SKonrad Dybcio }, 132*184fdd87SKonrad Dybcio .num_parents = 1, 133*184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_lucid_ops, 134*184fdd87SKonrad Dybcio }, 135*184fdd87SKonrad Dybcio }, 136*184fdd87SKonrad Dybcio }; 137*184fdd87SKonrad Dybcio 138*184fdd87SKonrad Dybcio /* 1152MHz Configuration */ 139*184fdd87SKonrad Dybcio static const struct alpha_pll_config gpll10_config = { 140*184fdd87SKonrad Dybcio .l = 0x3c, 141*184fdd87SKonrad Dybcio .alpha = 0x0, 142*184fdd87SKonrad Dybcio .config_ctl_val = 0x20485699, 143*184fdd87SKonrad Dybcio .config_ctl_hi_val = 0x00002261, 144*184fdd87SKonrad Dybcio .config_ctl_hi1_val = 0x329a299c, 145*184fdd87SKonrad Dybcio .user_ctl_val = 0x00000001, 146*184fdd87SKonrad Dybcio .user_ctl_hi_val = 0x00000805, 147*184fdd87SKonrad Dybcio .user_ctl_hi1_val = 0x00000000, 148*184fdd87SKonrad Dybcio }; 149*184fdd87SKonrad Dybcio 150*184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll10 = { 151*184fdd87SKonrad Dybcio .offset = 0xa000, 152*184fdd87SKonrad Dybcio .vco_table = lucid_vco, 153*184fdd87SKonrad Dybcio .num_vco = ARRAY_SIZE(lucid_vco), 154*184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 155*184fdd87SKonrad Dybcio .flags = SUPPORTS_FSM_LEGACY_MODE, 156*184fdd87SKonrad Dybcio .clkr = { 157*184fdd87SKonrad Dybcio .enable_reg = 0x79000, 158*184fdd87SKonrad Dybcio .enable_mask = BIT(10), 159*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 160*184fdd87SKonrad Dybcio .name = "gpll10", 161*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 162*184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 163*184fdd87SKonrad Dybcio }, 164*184fdd87SKonrad Dybcio .num_parents = 1, 165*184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_fixed_lucid_ops, 166*184fdd87SKonrad Dybcio }, 167*184fdd87SKonrad Dybcio }, 168*184fdd87SKonrad Dybcio }; 169*184fdd87SKonrad Dybcio 170*184fdd87SKonrad Dybcio /* 532MHz Configuration */ 171*184fdd87SKonrad Dybcio static const struct alpha_pll_config gpll11_config = { 172*184fdd87SKonrad Dybcio .l = 0x1b, 173*184fdd87SKonrad Dybcio .alpha = 0xb555, 174*184fdd87SKonrad Dybcio .config_ctl_val = 0x20485699, 175*184fdd87SKonrad Dybcio .config_ctl_hi_val = 0x00002261, 176*184fdd87SKonrad Dybcio .config_ctl_hi1_val = 0x329a299c, 177*184fdd87SKonrad Dybcio .user_ctl_val = 0x00000001, 178*184fdd87SKonrad Dybcio .user_ctl_hi_val = 0x00000805, 179*184fdd87SKonrad Dybcio .user_ctl_hi1_val = 0x00000000, 180*184fdd87SKonrad Dybcio }; 181*184fdd87SKonrad Dybcio 182*184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll11 = { 183*184fdd87SKonrad Dybcio .offset = 0xb000, 184*184fdd87SKonrad Dybcio .vco_table = lucid_vco, 185*184fdd87SKonrad Dybcio .num_vco = ARRAY_SIZE(lucid_vco), 186*184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 187*184fdd87SKonrad Dybcio .flags = SUPPORTS_FSM_LEGACY_MODE, 188*184fdd87SKonrad Dybcio .clkr = { 189*184fdd87SKonrad Dybcio .enable_reg = 0x79000, 190*184fdd87SKonrad Dybcio .enable_mask = BIT(11), 191*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 192*184fdd87SKonrad Dybcio .name = "gpll11", 193*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 194*184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 195*184fdd87SKonrad Dybcio }, 196*184fdd87SKonrad Dybcio .num_parents = 1, 197*184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_lucid_ops, 198*184fdd87SKonrad Dybcio }, 199*184fdd87SKonrad Dybcio }, 200*184fdd87SKonrad Dybcio }; 201*184fdd87SKonrad Dybcio 202*184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll3 = { 203*184fdd87SKonrad Dybcio .offset = 0x3000, 204*184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 205*184fdd87SKonrad Dybcio .clkr = { 206*184fdd87SKonrad Dybcio .enable_reg = 0x79000, 207*184fdd87SKonrad Dybcio .enable_mask = BIT(3), 208*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 209*184fdd87SKonrad Dybcio .name = "gpll3", 210*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 211*184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 212*184fdd87SKonrad Dybcio }, 213*184fdd87SKonrad Dybcio .num_parents = 1, 214*184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_fixed_lucid_ops, 215*184fdd87SKonrad Dybcio }, 216*184fdd87SKonrad Dybcio }, 217*184fdd87SKonrad Dybcio }; 218*184fdd87SKonrad Dybcio 219*184fdd87SKonrad Dybcio static const struct clk_div_table post_div_table_gpll3_out_even[] = { 220*184fdd87SKonrad Dybcio { 0x1, 2 }, 221*184fdd87SKonrad Dybcio { } 222*184fdd87SKonrad Dybcio }; 223*184fdd87SKonrad Dybcio 224*184fdd87SKonrad Dybcio static struct clk_alpha_pll_postdiv gpll3_out_even = { 225*184fdd87SKonrad Dybcio .offset = 0x3000, 226*184fdd87SKonrad Dybcio .post_div_shift = 8, 227*184fdd87SKonrad Dybcio .post_div_table = post_div_table_gpll3_out_even, 228*184fdd87SKonrad Dybcio .num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_even), 229*184fdd87SKonrad Dybcio .width = 4, 230*184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 231*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 232*184fdd87SKonrad Dybcio .name = "gpll3_out_even", 233*184fdd87SKonrad Dybcio .parent_hws = (const struct clk_hw*[]){ 234*184fdd87SKonrad Dybcio &gpll3.clkr.hw, 235*184fdd87SKonrad Dybcio }, 236*184fdd87SKonrad Dybcio .num_parents = 1, 237*184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_postdiv_lucid_ops, 238*184fdd87SKonrad Dybcio }, 239*184fdd87SKonrad Dybcio }; 240*184fdd87SKonrad Dybcio 241*184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll4 = { 242*184fdd87SKonrad Dybcio .offset = 0x4000, 243*184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 244*184fdd87SKonrad Dybcio .clkr = { 245*184fdd87SKonrad Dybcio .enable_reg = 0x79000, 246*184fdd87SKonrad Dybcio .enable_mask = BIT(4), 247*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 248*184fdd87SKonrad Dybcio .name = "gpll4", 249*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 250*184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 251*184fdd87SKonrad Dybcio }, 252*184fdd87SKonrad Dybcio .num_parents = 1, 253*184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_fixed_lucid_ops, 254*184fdd87SKonrad Dybcio }, 255*184fdd87SKonrad Dybcio }, 256*184fdd87SKonrad Dybcio }; 257*184fdd87SKonrad Dybcio 258*184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll5 = { 259*184fdd87SKonrad Dybcio .offset = 0x5000, 260*184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 261*184fdd87SKonrad Dybcio .clkr = { 262*184fdd87SKonrad Dybcio .enable_reg = 0x79000, 263*184fdd87SKonrad Dybcio .enable_mask = BIT(5), 264*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 265*184fdd87SKonrad Dybcio .name = "gpll5", 266*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 267*184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 268*184fdd87SKonrad Dybcio }, 269*184fdd87SKonrad Dybcio .num_parents = 1, 270*184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_fixed_lucid_ops, 271*184fdd87SKonrad Dybcio }, 272*184fdd87SKonrad Dybcio }, 273*184fdd87SKonrad Dybcio }; 274*184fdd87SKonrad Dybcio 275*184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll6 = { 276*184fdd87SKonrad Dybcio .offset = 0x6000, 277*184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 278*184fdd87SKonrad Dybcio .clkr = { 279*184fdd87SKonrad Dybcio .enable_reg = 0x79000, 280*184fdd87SKonrad Dybcio .enable_mask = BIT(6), 281*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 282*184fdd87SKonrad Dybcio .name = "gpll6", 283*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 284*184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 285*184fdd87SKonrad Dybcio }, 286*184fdd87SKonrad Dybcio .num_parents = 1, 287*184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_fixed_lucid_ops, 288*184fdd87SKonrad Dybcio }, 289*184fdd87SKonrad Dybcio }, 290*184fdd87SKonrad Dybcio }; 291*184fdd87SKonrad Dybcio 292*184fdd87SKonrad Dybcio static const struct clk_div_table post_div_table_gpll6_out_even[] = { 293*184fdd87SKonrad Dybcio { 0x1, 2 }, 294*184fdd87SKonrad Dybcio { } 295*184fdd87SKonrad Dybcio }; 296*184fdd87SKonrad Dybcio 297*184fdd87SKonrad Dybcio static struct clk_alpha_pll_postdiv gpll6_out_even = { 298*184fdd87SKonrad Dybcio .offset = 0x6000, 299*184fdd87SKonrad Dybcio .post_div_shift = 8, 300*184fdd87SKonrad Dybcio .post_div_table = post_div_table_gpll6_out_even, 301*184fdd87SKonrad Dybcio .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_even), 302*184fdd87SKonrad Dybcio .width = 4, 303*184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 304*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 305*184fdd87SKonrad Dybcio .name = "gpll6_out_even", 306*184fdd87SKonrad Dybcio .parent_hws = (const struct clk_hw*[]){ 307*184fdd87SKonrad Dybcio &gpll6.clkr.hw, 308*184fdd87SKonrad Dybcio }, 309*184fdd87SKonrad Dybcio .num_parents = 1, 310*184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_postdiv_lucid_ops, 311*184fdd87SKonrad Dybcio }, 312*184fdd87SKonrad Dybcio }; 313*184fdd87SKonrad Dybcio 314*184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll7 = { 315*184fdd87SKonrad Dybcio .offset = 0x7000, 316*184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 317*184fdd87SKonrad Dybcio .clkr = { 318*184fdd87SKonrad Dybcio .enable_reg = 0x79000, 319*184fdd87SKonrad Dybcio .enable_mask = BIT(7), 320*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 321*184fdd87SKonrad Dybcio .name = "gpll7", 322*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 323*184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 324*184fdd87SKonrad Dybcio }, 325*184fdd87SKonrad Dybcio .num_parents = 1, 326*184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_fixed_lucid_ops, 327*184fdd87SKonrad Dybcio }, 328*184fdd87SKonrad Dybcio }, 329*184fdd87SKonrad Dybcio }; 330*184fdd87SKonrad Dybcio 331*184fdd87SKonrad Dybcio /* 400MHz Configuration */ 332*184fdd87SKonrad Dybcio static const struct alpha_pll_config gpll8_config = { 333*184fdd87SKonrad Dybcio .l = 0x14, 334*184fdd87SKonrad Dybcio .alpha = 0xd555, 335*184fdd87SKonrad Dybcio .config_ctl_val = 0x20485699, 336*184fdd87SKonrad Dybcio .config_ctl_hi_val = 0x00002261, 337*184fdd87SKonrad Dybcio .config_ctl_hi1_val = 0x329a299c, 338*184fdd87SKonrad Dybcio .user_ctl_val = 0x00000101, 339*184fdd87SKonrad Dybcio .user_ctl_hi_val = 0x00000805, 340*184fdd87SKonrad Dybcio .user_ctl_hi1_val = 0x00000000, 341*184fdd87SKonrad Dybcio }; 342*184fdd87SKonrad Dybcio 343*184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll8 = { 344*184fdd87SKonrad Dybcio .offset = 0x8000, 345*184fdd87SKonrad Dybcio .vco_table = lucid_vco, 346*184fdd87SKonrad Dybcio .num_vco = ARRAY_SIZE(lucid_vco), 347*184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 348*184fdd87SKonrad Dybcio .flags = SUPPORTS_FSM_LEGACY_MODE, 349*184fdd87SKonrad Dybcio .clkr = { 350*184fdd87SKonrad Dybcio .enable_reg = 0x79000, 351*184fdd87SKonrad Dybcio .enable_mask = BIT(8), 352*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 353*184fdd87SKonrad Dybcio .name = "gpll8", 354*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 355*184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 356*184fdd87SKonrad Dybcio }, 357*184fdd87SKonrad Dybcio .num_parents = 1, 358*184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_lucid_ops, 359*184fdd87SKonrad Dybcio }, 360*184fdd87SKonrad Dybcio }, 361*184fdd87SKonrad Dybcio }; 362*184fdd87SKonrad Dybcio 363*184fdd87SKonrad Dybcio static const struct clk_div_table post_div_table_gpll8_out_even[] = { 364*184fdd87SKonrad Dybcio { 0x1, 2 }, 365*184fdd87SKonrad Dybcio { } 366*184fdd87SKonrad Dybcio }; 367*184fdd87SKonrad Dybcio 368*184fdd87SKonrad Dybcio static struct clk_alpha_pll_postdiv gpll8_out_even = { 369*184fdd87SKonrad Dybcio .offset = 0x8000, 370*184fdd87SKonrad Dybcio .post_div_shift = 8, 371*184fdd87SKonrad Dybcio .post_div_table = post_div_table_gpll8_out_even, 372*184fdd87SKonrad Dybcio .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_even), 373*184fdd87SKonrad Dybcio .width = 4, 374*184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 375*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 376*184fdd87SKonrad Dybcio .name = "gpll8_out_even", 377*184fdd87SKonrad Dybcio .parent_hws = (const struct clk_hw*[]){ 378*184fdd87SKonrad Dybcio &gpll8.clkr.hw, 379*184fdd87SKonrad Dybcio }, 380*184fdd87SKonrad Dybcio .num_parents = 1, 381*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 382*184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_postdiv_lucid_ops, 383*184fdd87SKonrad Dybcio }, 384*184fdd87SKonrad Dybcio }; 385*184fdd87SKonrad Dybcio 386*184fdd87SKonrad Dybcio /* 1440MHz Configuration */ 387*184fdd87SKonrad Dybcio static const struct alpha_pll_config gpll9_config = { 388*184fdd87SKonrad Dybcio .l = 0x4b, 389*184fdd87SKonrad Dybcio .alpha = 0x0, 390*184fdd87SKonrad Dybcio .config_ctl_val = 0x08200800, 391*184fdd87SKonrad Dybcio .config_ctl_hi_val = 0x05022011, 392*184fdd87SKonrad Dybcio .config_ctl_hi1_val = 0x08000000, 393*184fdd87SKonrad Dybcio .user_ctl_val = 0x00000301, 394*184fdd87SKonrad Dybcio }; 395*184fdd87SKonrad Dybcio 396*184fdd87SKonrad Dybcio static struct clk_alpha_pll gpll9 = { 397*184fdd87SKonrad Dybcio .offset = 0x9000, 398*184fdd87SKonrad Dybcio .vco_table = zonda_vco, 399*184fdd87SKonrad Dybcio .num_vco = ARRAY_SIZE(zonda_vco), 400*184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], 401*184fdd87SKonrad Dybcio .clkr = { 402*184fdd87SKonrad Dybcio .enable_reg = 0x79000, 403*184fdd87SKonrad Dybcio .enable_mask = BIT(9), 404*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 405*184fdd87SKonrad Dybcio .name = "gpll9", 406*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 407*184fdd87SKonrad Dybcio .index = DT_BI_TCXO, 408*184fdd87SKonrad Dybcio }, 409*184fdd87SKonrad Dybcio .num_parents = 1, 410*184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_zonda_ops, 411*184fdd87SKonrad Dybcio }, 412*184fdd87SKonrad Dybcio }, 413*184fdd87SKonrad Dybcio }; 414*184fdd87SKonrad Dybcio 415*184fdd87SKonrad Dybcio static const struct clk_div_table post_div_table_gpll9_out_main[] = { 416*184fdd87SKonrad Dybcio { 0x3, 4 }, 417*184fdd87SKonrad Dybcio { } 418*184fdd87SKonrad Dybcio }; 419*184fdd87SKonrad Dybcio 420*184fdd87SKonrad Dybcio static struct clk_alpha_pll_postdiv gpll9_out_main = { 421*184fdd87SKonrad Dybcio .offset = 0x9000, 422*184fdd87SKonrad Dybcio .post_div_shift = 8, 423*184fdd87SKonrad Dybcio .post_div_table = post_div_table_gpll9_out_main, 424*184fdd87SKonrad Dybcio .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main), 425*184fdd87SKonrad Dybcio .width = 2, 426*184fdd87SKonrad Dybcio .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], 427*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 428*184fdd87SKonrad Dybcio .name = "gpll9_out_main", 429*184fdd87SKonrad Dybcio .parent_hws = (const struct clk_hw*[]){ 430*184fdd87SKonrad Dybcio &gpll9.clkr.hw, 431*184fdd87SKonrad Dybcio }, 432*184fdd87SKonrad Dybcio .num_parents = 1, 433*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 434*184fdd87SKonrad Dybcio .ops = &clk_alpha_pll_postdiv_zonda_ops, 435*184fdd87SKonrad Dybcio }, 436*184fdd87SKonrad Dybcio }; 437*184fdd87SKonrad Dybcio 438*184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_0[] = { 439*184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 440*184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 441*184fdd87SKonrad Dybcio { P_GPLL0_OUT_EVEN, 2 }, 442*184fdd87SKonrad Dybcio }; 443*184fdd87SKonrad Dybcio 444*184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_0[] = { 445*184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 446*184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 447*184fdd87SKonrad Dybcio { .hw = &gpll0_out_even.clkr.hw }, 448*184fdd87SKonrad Dybcio }; 449*184fdd87SKonrad Dybcio 450*184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_1[] = { 451*184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 452*184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 453*184fdd87SKonrad Dybcio { P_GPLL0_OUT_EVEN, 2 }, 454*184fdd87SKonrad Dybcio { P_GPLL6_OUT_EVEN, 4 }, 455*184fdd87SKonrad Dybcio }; 456*184fdd87SKonrad Dybcio 457*184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_1[] = { 458*184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 459*184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 460*184fdd87SKonrad Dybcio { .hw = &gpll0_out_even.clkr.hw }, 461*184fdd87SKonrad Dybcio { .hw = &gpll6_out_even.clkr.hw }, 462*184fdd87SKonrad Dybcio }; 463*184fdd87SKonrad Dybcio 464*184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_2[] = { 465*184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 466*184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 467*184fdd87SKonrad Dybcio { P_GPLL0_OUT_EVEN, 2 }, 468*184fdd87SKonrad Dybcio { P_GPLL0_OUT_ODD, 4 }, 469*184fdd87SKonrad Dybcio }; 470*184fdd87SKonrad Dybcio 471*184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_2[] = { 472*184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 473*184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 474*184fdd87SKonrad Dybcio { .hw = &gpll0_out_even.clkr.hw }, 475*184fdd87SKonrad Dybcio { .hw = &gpll0_out_odd.clkr.hw }, 476*184fdd87SKonrad Dybcio }; 477*184fdd87SKonrad Dybcio 478*184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_2_ao[] = { 479*184fdd87SKonrad Dybcio { .index = DT_BI_TCXO_AO }, 480*184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 481*184fdd87SKonrad Dybcio { .hw = &gpll0_out_even.clkr.hw }, 482*184fdd87SKonrad Dybcio { .hw = &gpll0_out_odd.clkr.hw }, 483*184fdd87SKonrad Dybcio }; 484*184fdd87SKonrad Dybcio 485*184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_3[] = { 486*184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 487*184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 488*184fdd87SKonrad Dybcio { P_GPLL9_OUT_EARLY, 2 }, 489*184fdd87SKonrad Dybcio { P_GPLL10_OUT_EVEN, 3 }, 490*184fdd87SKonrad Dybcio { P_GPLL9_OUT_MAIN, 4 }, 491*184fdd87SKonrad Dybcio { P_GPLL3_OUT_EVEN, 6 }, 492*184fdd87SKonrad Dybcio }; 493*184fdd87SKonrad Dybcio 494*184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_3[] = { 495*184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 496*184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 497*184fdd87SKonrad Dybcio { .hw = &gpll9.clkr.hw }, 498*184fdd87SKonrad Dybcio { .hw = &gpll10.clkr.hw }, 499*184fdd87SKonrad Dybcio { .hw = &gpll9_out_main.clkr.hw }, 500*184fdd87SKonrad Dybcio { .hw = &gpll3_out_even.clkr.hw }, 501*184fdd87SKonrad Dybcio }; 502*184fdd87SKonrad Dybcio 503*184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_4[] = { 504*184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 505*184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 506*184fdd87SKonrad Dybcio { P_GPLL0_OUT_EVEN, 2 }, 507*184fdd87SKonrad Dybcio { P_GPLL0_OUT_ODD, 4 }, 508*184fdd87SKonrad Dybcio { P_GPLL4_OUT_EVEN, 5 }, 509*184fdd87SKonrad Dybcio { P_GPLL3_OUT_EVEN, 6 }, 510*184fdd87SKonrad Dybcio }; 511*184fdd87SKonrad Dybcio 512*184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_4[] = { 513*184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 514*184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 515*184fdd87SKonrad Dybcio { .hw = &gpll0_out_even.clkr.hw }, 516*184fdd87SKonrad Dybcio { .hw = &gpll0_out_odd.clkr.hw }, 517*184fdd87SKonrad Dybcio { .hw = &gpll4.clkr.hw }, 518*184fdd87SKonrad Dybcio { .hw = &gpll3_out_even.clkr.hw }, 519*184fdd87SKonrad Dybcio }; 520*184fdd87SKonrad Dybcio 521*184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_5[] = { 522*184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 523*184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 524*184fdd87SKonrad Dybcio { P_GPLL8_OUT_MAIN, 2 }, 525*184fdd87SKonrad Dybcio { P_GPLL10_OUT_EVEN, 3 }, 526*184fdd87SKonrad Dybcio { P_GPLL9_OUT_MAIN, 4 }, 527*184fdd87SKonrad Dybcio { P_GPLL8_OUT_EVEN, 5 }, 528*184fdd87SKonrad Dybcio { P_GPLL3_OUT_EVEN, 6 }, 529*184fdd87SKonrad Dybcio }; 530*184fdd87SKonrad Dybcio 531*184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_5[] = { 532*184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 533*184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 534*184fdd87SKonrad Dybcio { .hw = &gpll8.clkr.hw }, 535*184fdd87SKonrad Dybcio { .hw = &gpll10.clkr.hw }, 536*184fdd87SKonrad Dybcio { .hw = &gpll9_out_main.clkr.hw }, 537*184fdd87SKonrad Dybcio { .hw = &gpll8_out_even.clkr.hw }, 538*184fdd87SKonrad Dybcio { .hw = &gpll3_out_even.clkr.hw }, 539*184fdd87SKonrad Dybcio }; 540*184fdd87SKonrad Dybcio 541*184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_6[] = { 542*184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 543*184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 544*184fdd87SKonrad Dybcio { P_GPLL8_OUT_MAIN, 2 }, 545*184fdd87SKonrad Dybcio { P_GPLL5_OUT_EVEN, 3 }, 546*184fdd87SKonrad Dybcio { P_GPLL9_OUT_MAIN, 4 }, 547*184fdd87SKonrad Dybcio { P_GPLL8_OUT_EVEN, 5 }, 548*184fdd87SKonrad Dybcio { P_GPLL3_OUT_MAIN, 6 }, 549*184fdd87SKonrad Dybcio }; 550*184fdd87SKonrad Dybcio 551*184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_6[] = { 552*184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 553*184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 554*184fdd87SKonrad Dybcio { .hw = &gpll8.clkr.hw }, 555*184fdd87SKonrad Dybcio { .hw = &gpll5.clkr.hw }, 556*184fdd87SKonrad Dybcio { .hw = &gpll9_out_main.clkr.hw }, 557*184fdd87SKonrad Dybcio { .hw = &gpll8_out_even.clkr.hw }, 558*184fdd87SKonrad Dybcio { .hw = &gpll3.clkr.hw }, 559*184fdd87SKonrad Dybcio }; 560*184fdd87SKonrad Dybcio 561*184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_7[] = { 562*184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 563*184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 564*184fdd87SKonrad Dybcio { P_GPLL0_OUT_EVEN, 2 }, 565*184fdd87SKonrad Dybcio { P_GPLL0_OUT_ODD, 4 }, 566*184fdd87SKonrad Dybcio { P_SLEEP_CLK, 5 }, 567*184fdd87SKonrad Dybcio }; 568*184fdd87SKonrad Dybcio 569*184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_7[] = { 570*184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 571*184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 572*184fdd87SKonrad Dybcio { .hw = &gpll0_out_even.clkr.hw }, 573*184fdd87SKonrad Dybcio { .hw = &gpll0_out_odd.clkr.hw }, 574*184fdd87SKonrad Dybcio { .index = DT_SLEEP_CLK }, 575*184fdd87SKonrad Dybcio }; 576*184fdd87SKonrad Dybcio 577*184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_8[] = { 578*184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 579*184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 580*184fdd87SKonrad Dybcio { P_GPLL0_OUT_EVEN, 2 }, 581*184fdd87SKonrad Dybcio { P_GPLL10_OUT_EVEN, 3 }, 582*184fdd87SKonrad Dybcio { P_GPLL4_OUT_EVEN, 5 }, 583*184fdd87SKonrad Dybcio { P_GPLL3_OUT_MAIN, 6 }, 584*184fdd87SKonrad Dybcio }; 585*184fdd87SKonrad Dybcio 586*184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_8[] = { 587*184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 588*184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 589*184fdd87SKonrad Dybcio { .hw = &gpll0_out_even.clkr.hw }, 590*184fdd87SKonrad Dybcio { .hw = &gpll10.clkr.hw }, 591*184fdd87SKonrad Dybcio { .hw = &gpll4.clkr.hw }, 592*184fdd87SKonrad Dybcio { .hw = &gpll3.clkr.hw }, 593*184fdd87SKonrad Dybcio }; 594*184fdd87SKonrad Dybcio 595*184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_9[] = { 596*184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 597*184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 598*184fdd87SKonrad Dybcio { P_GPLL0_OUT_EVEN, 2 }, 599*184fdd87SKonrad Dybcio { P_GPLL10_OUT_EVEN, 3 }, 600*184fdd87SKonrad Dybcio { P_GPLL9_OUT_MAIN, 4 }, 601*184fdd87SKonrad Dybcio { P_GPLL8_OUT_EVEN, 5 }, 602*184fdd87SKonrad Dybcio { P_GPLL3_OUT_MAIN, 6 }, 603*184fdd87SKonrad Dybcio }; 604*184fdd87SKonrad Dybcio 605*184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_9[] = { 606*184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 607*184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 608*184fdd87SKonrad Dybcio { .hw = &gpll0_out_even.clkr.hw }, 609*184fdd87SKonrad Dybcio { .hw = &gpll10.clkr.hw }, 610*184fdd87SKonrad Dybcio { .hw = &gpll9_out_main.clkr.hw }, 611*184fdd87SKonrad Dybcio { .hw = &gpll8_out_even.clkr.hw }, 612*184fdd87SKonrad Dybcio { .hw = &gpll3.clkr.hw }, 613*184fdd87SKonrad Dybcio }; 614*184fdd87SKonrad Dybcio 615*184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_10[] = { 616*184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 617*184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 618*184fdd87SKonrad Dybcio { P_GPLL8_OUT_MAIN, 2 }, 619*184fdd87SKonrad Dybcio { P_GPLL10_OUT_EVEN, 3 }, 620*184fdd87SKonrad Dybcio { P_GPLL9_OUT_MAIN, 4 }, 621*184fdd87SKonrad Dybcio { P_GPLL8_OUT_EVEN, 5 }, 622*184fdd87SKonrad Dybcio { P_GPLL3_OUT_MAIN, 6 }, 623*184fdd87SKonrad Dybcio }; 624*184fdd87SKonrad Dybcio 625*184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_10[] = { 626*184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 627*184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 628*184fdd87SKonrad Dybcio { .hw = &gpll8.clkr.hw }, 629*184fdd87SKonrad Dybcio { .hw = &gpll10.clkr.hw }, 630*184fdd87SKonrad Dybcio { .hw = &gpll9_out_main.clkr.hw }, 631*184fdd87SKonrad Dybcio { .hw = &gpll8_out_even.clkr.hw }, 632*184fdd87SKonrad Dybcio { .hw = &gpll3.clkr.hw }, 633*184fdd87SKonrad Dybcio }; 634*184fdd87SKonrad Dybcio 635*184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_11[] = { 636*184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 637*184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 638*184fdd87SKonrad Dybcio { P_GPLL8_OUT_MAIN, 2 }, 639*184fdd87SKonrad Dybcio { P_GPLL10_OUT_EVEN, 3 }, 640*184fdd87SKonrad Dybcio { P_GPLL6_OUT_MAIN, 4 }, 641*184fdd87SKonrad Dybcio { P_GPLL3_OUT_EVEN, 6 }, 642*184fdd87SKonrad Dybcio }; 643*184fdd87SKonrad Dybcio 644*184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_11[] = { 645*184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 646*184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 647*184fdd87SKonrad Dybcio { .hw = &gpll8.clkr.hw }, 648*184fdd87SKonrad Dybcio { .hw = &gpll10.clkr.hw }, 649*184fdd87SKonrad Dybcio { .hw = &gpll6.clkr.hw }, 650*184fdd87SKonrad Dybcio { .hw = &gpll3_out_even.clkr.hw }, 651*184fdd87SKonrad Dybcio }; 652*184fdd87SKonrad Dybcio 653*184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_12[] = { 654*184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 655*184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 656*184fdd87SKonrad Dybcio { P_GPLL0_OUT_EVEN, 2 }, 657*184fdd87SKonrad Dybcio { P_GPLL7_OUT_EVEN, 3 }, 658*184fdd87SKonrad Dybcio { P_GPLL4_OUT_EVEN, 5 }, 659*184fdd87SKonrad Dybcio }; 660*184fdd87SKonrad Dybcio 661*184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_12[] = { 662*184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 663*184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 664*184fdd87SKonrad Dybcio { .hw = &gpll0_out_even.clkr.hw }, 665*184fdd87SKonrad Dybcio { .hw = &gpll7.clkr.hw }, 666*184fdd87SKonrad Dybcio { .hw = &gpll4.clkr.hw }, 667*184fdd87SKonrad Dybcio }; 668*184fdd87SKonrad Dybcio 669*184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_13[] = { 670*184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 671*184fdd87SKonrad Dybcio { P_SLEEP_CLK, 5 }, 672*184fdd87SKonrad Dybcio }; 673*184fdd87SKonrad Dybcio 674*184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_13[] = { 675*184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 676*184fdd87SKonrad Dybcio { .index = DT_SLEEP_CLK }, 677*184fdd87SKonrad Dybcio }; 678*184fdd87SKonrad Dybcio 679*184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_14[] = { 680*184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 681*184fdd87SKonrad Dybcio { P_GPLL11_OUT_ODD, 2 }, 682*184fdd87SKonrad Dybcio { P_GPLL11_OUT_EVEN, 3 }, 683*184fdd87SKonrad Dybcio }; 684*184fdd87SKonrad Dybcio 685*184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_14[] = { 686*184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 687*184fdd87SKonrad Dybcio { .hw = &gpll11.clkr.hw }, 688*184fdd87SKonrad Dybcio { .hw = &gpll11.clkr.hw }, 689*184fdd87SKonrad Dybcio }; 690*184fdd87SKonrad Dybcio 691*184fdd87SKonrad Dybcio static const struct parent_map gcc_parent_map_15[] = { 692*184fdd87SKonrad Dybcio { P_BI_TCXO, 0 }, 693*184fdd87SKonrad Dybcio { P_GPLL0_OUT_MAIN, 1 }, 694*184fdd87SKonrad Dybcio { P_GPLL6_OUT_EVEN, 4 }, 695*184fdd87SKonrad Dybcio }; 696*184fdd87SKonrad Dybcio 697*184fdd87SKonrad Dybcio static const struct clk_parent_data gcc_parent_data_15[] = { 698*184fdd87SKonrad Dybcio { .index = DT_BI_TCXO }, 699*184fdd87SKonrad Dybcio { .hw = &gpll0.clkr.hw }, 700*184fdd87SKonrad Dybcio { .hw = &gpll6_out_even.clkr.hw }, 701*184fdd87SKonrad Dybcio }; 702*184fdd87SKonrad Dybcio 703*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = { 704*184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 705*184fdd87SKonrad Dybcio F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 706*184fdd87SKonrad Dybcio F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 707*184fdd87SKonrad Dybcio F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 708*184fdd87SKonrad Dybcio { } 709*184fdd87SKonrad Dybcio }; 710*184fdd87SKonrad Dybcio 711*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_axi_clk_src = { 712*184fdd87SKonrad Dybcio .cmd_rcgr = 0x5802c, 713*184fdd87SKonrad Dybcio .mnd_width = 0, 714*184fdd87SKonrad Dybcio .hid_width = 5, 715*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_8, 716*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_axi_clk_src, 717*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 718*184fdd87SKonrad Dybcio .name = "gcc_camss_axi_clk_src", 719*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_8, 720*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_8), 721*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 722*184fdd87SKonrad Dybcio }, 723*184fdd87SKonrad Dybcio }; 724*184fdd87SKonrad Dybcio 725*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_camss_cci_0_clk_src[] = { 726*184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 727*184fdd87SKonrad Dybcio F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 728*184fdd87SKonrad Dybcio { } 729*184fdd87SKonrad Dybcio }; 730*184fdd87SKonrad Dybcio 731*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_cci_0_clk_src = { 732*184fdd87SKonrad Dybcio .cmd_rcgr = 0x56000, 733*184fdd87SKonrad Dybcio .mnd_width = 0, 734*184fdd87SKonrad Dybcio .hid_width = 5, 735*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_9, 736*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_cci_0_clk_src, 737*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 738*184fdd87SKonrad Dybcio .name = "gcc_camss_cci_0_clk_src", 739*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_9, 740*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_9), 741*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 742*184fdd87SKonrad Dybcio }, 743*184fdd87SKonrad Dybcio }; 744*184fdd87SKonrad Dybcio 745*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_cci_1_clk_src = { 746*184fdd87SKonrad Dybcio .cmd_rcgr = 0x5c000, 747*184fdd87SKonrad Dybcio .mnd_width = 0, 748*184fdd87SKonrad Dybcio .hid_width = 5, 749*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_9, 750*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_cci_0_clk_src, 751*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 752*184fdd87SKonrad Dybcio .name = "gcc_camss_cci_1_clk_src", 753*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_9, 754*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_9), 755*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 756*184fdd87SKonrad Dybcio }, 757*184fdd87SKonrad Dybcio }; 758*184fdd87SKonrad Dybcio 759*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = { 760*184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 761*184fdd87SKonrad Dybcio F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0), 762*184fdd87SKonrad Dybcio F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 763*184fdd87SKonrad Dybcio { } 764*184fdd87SKonrad Dybcio }; 765*184fdd87SKonrad Dybcio 766*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { 767*184fdd87SKonrad Dybcio .cmd_rcgr = 0x59000, 768*184fdd87SKonrad Dybcio .mnd_width = 0, 769*184fdd87SKonrad Dybcio .hid_width = 5, 770*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_4, 771*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 772*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 773*184fdd87SKonrad Dybcio .name = "gcc_camss_csi0phytimer_clk_src", 774*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_4, 775*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_4), 776*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 777*184fdd87SKonrad Dybcio }, 778*184fdd87SKonrad Dybcio }; 779*184fdd87SKonrad Dybcio 780*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { 781*184fdd87SKonrad Dybcio .cmd_rcgr = 0x5901c, 782*184fdd87SKonrad Dybcio .mnd_width = 0, 783*184fdd87SKonrad Dybcio .hid_width = 5, 784*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_4, 785*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 786*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 787*184fdd87SKonrad Dybcio .name = "gcc_camss_csi1phytimer_clk_src", 788*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_4, 789*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_4), 790*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 791*184fdd87SKonrad Dybcio }, 792*184fdd87SKonrad Dybcio }; 793*184fdd87SKonrad Dybcio 794*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = { 795*184fdd87SKonrad Dybcio .cmd_rcgr = 0x59038, 796*184fdd87SKonrad Dybcio .mnd_width = 0, 797*184fdd87SKonrad Dybcio .hid_width = 5, 798*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_4, 799*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 800*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 801*184fdd87SKonrad Dybcio .name = "gcc_camss_csi2phytimer_clk_src", 802*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_4, 803*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_4), 804*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 805*184fdd87SKonrad Dybcio }, 806*184fdd87SKonrad Dybcio }; 807*184fdd87SKonrad Dybcio 808*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_csi3phytimer_clk_src = { 809*184fdd87SKonrad Dybcio .cmd_rcgr = 0x59054, 810*184fdd87SKonrad Dybcio .mnd_width = 0, 811*184fdd87SKonrad Dybcio .hid_width = 5, 812*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_4, 813*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 814*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 815*184fdd87SKonrad Dybcio .name = "gcc_camss_csi3phytimer_clk_src", 816*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_4, 817*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_4), 818*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 819*184fdd87SKonrad Dybcio }, 820*184fdd87SKonrad Dybcio }; 821*184fdd87SKonrad Dybcio 822*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { 823*184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 824*184fdd87SKonrad Dybcio F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 15), 825*184fdd87SKonrad Dybcio F(65454545, P_GPLL9_OUT_EARLY, 11, 1, 2), 826*184fdd87SKonrad Dybcio { } 827*184fdd87SKonrad Dybcio }; 828*184fdd87SKonrad Dybcio 829*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_mclk0_clk_src = { 830*184fdd87SKonrad Dybcio .cmd_rcgr = 0x51000, 831*184fdd87SKonrad Dybcio .mnd_width = 8, 832*184fdd87SKonrad Dybcio .hid_width = 5, 833*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_3, 834*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 835*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 836*184fdd87SKonrad Dybcio .name = "gcc_camss_mclk0_clk_src", 837*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_3, 838*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_3), 839*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 840*184fdd87SKonrad Dybcio }, 841*184fdd87SKonrad Dybcio }; 842*184fdd87SKonrad Dybcio 843*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_mclk1_clk_src = { 844*184fdd87SKonrad Dybcio .cmd_rcgr = 0x5101c, 845*184fdd87SKonrad Dybcio .mnd_width = 8, 846*184fdd87SKonrad Dybcio .hid_width = 5, 847*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_3, 848*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 849*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 850*184fdd87SKonrad Dybcio .name = "gcc_camss_mclk1_clk_src", 851*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_3, 852*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_3), 853*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 854*184fdd87SKonrad Dybcio }, 855*184fdd87SKonrad Dybcio }; 856*184fdd87SKonrad Dybcio 857*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_mclk2_clk_src = { 858*184fdd87SKonrad Dybcio .cmd_rcgr = 0x51038, 859*184fdd87SKonrad Dybcio .mnd_width = 8, 860*184fdd87SKonrad Dybcio .hid_width = 5, 861*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_3, 862*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 863*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 864*184fdd87SKonrad Dybcio .name = "gcc_camss_mclk2_clk_src", 865*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_3, 866*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_3), 867*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 868*184fdd87SKonrad Dybcio }, 869*184fdd87SKonrad Dybcio }; 870*184fdd87SKonrad Dybcio 871*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_mclk3_clk_src = { 872*184fdd87SKonrad Dybcio .cmd_rcgr = 0x51054, 873*184fdd87SKonrad Dybcio .mnd_width = 8, 874*184fdd87SKonrad Dybcio .hid_width = 5, 875*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_3, 876*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 877*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 878*184fdd87SKonrad Dybcio .name = "gcc_camss_mclk3_clk_src", 879*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_3, 880*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_3), 881*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 882*184fdd87SKonrad Dybcio }, 883*184fdd87SKonrad Dybcio }; 884*184fdd87SKonrad Dybcio 885*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_mclk4_clk_src = { 886*184fdd87SKonrad Dybcio .cmd_rcgr = 0x51070, 887*184fdd87SKonrad Dybcio .mnd_width = 8, 888*184fdd87SKonrad Dybcio .hid_width = 5, 889*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_3, 890*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 891*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 892*184fdd87SKonrad Dybcio .name = "gcc_camss_mclk4_clk_src", 893*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_3, 894*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_3), 895*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 896*184fdd87SKonrad Dybcio }, 897*184fdd87SKonrad Dybcio }; 898*184fdd87SKonrad Dybcio 899*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = { 900*184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 901*184fdd87SKonrad Dybcio F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0), 902*184fdd87SKonrad Dybcio F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 903*184fdd87SKonrad Dybcio { } 904*184fdd87SKonrad Dybcio }; 905*184fdd87SKonrad Dybcio 906*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = { 907*184fdd87SKonrad Dybcio .cmd_rcgr = 0x55024, 908*184fdd87SKonrad Dybcio .mnd_width = 0, 909*184fdd87SKonrad Dybcio .hid_width = 5, 910*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_10, 911*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src, 912*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 913*184fdd87SKonrad Dybcio .name = "gcc_camss_ope_ahb_clk_src", 914*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_10, 915*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_10), 916*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 917*184fdd87SKonrad Dybcio }, 918*184fdd87SKonrad Dybcio }; 919*184fdd87SKonrad Dybcio 920*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = { 921*184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 922*184fdd87SKonrad Dybcio F(200000000, P_GPLL8_OUT_EVEN, 1, 0, 0), 923*184fdd87SKonrad Dybcio F(266600000, P_GPLL8_OUT_EVEN, 1, 0, 0), 924*184fdd87SKonrad Dybcio F(480000000, P_GPLL8_OUT_EVEN, 1, 0, 0), 925*184fdd87SKonrad Dybcio F(580000000, P_GPLL8_OUT_EVEN, 1, 0, 0), 926*184fdd87SKonrad Dybcio { } 927*184fdd87SKonrad Dybcio }; 928*184fdd87SKonrad Dybcio 929*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_ope_clk_src = { 930*184fdd87SKonrad Dybcio .cmd_rcgr = 0x55004, 931*184fdd87SKonrad Dybcio .mnd_width = 0, 932*184fdd87SKonrad Dybcio .hid_width = 5, 933*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_10, 934*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_ope_clk_src, 935*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 936*184fdd87SKonrad Dybcio .name = "gcc_camss_ope_clk_src", 937*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_10, 938*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_10), 939*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 940*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 941*184fdd87SKonrad Dybcio }, 942*184fdd87SKonrad Dybcio }; 943*184fdd87SKonrad Dybcio 944*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = { 945*184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 946*184fdd87SKonrad Dybcio F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), 947*184fdd87SKonrad Dybcio F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 948*184fdd87SKonrad Dybcio F(144000000, P_GPLL9_OUT_MAIN, 2.5, 0, 0), 949*184fdd87SKonrad Dybcio F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 950*184fdd87SKonrad Dybcio F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0), 951*184fdd87SKonrad Dybcio F(180000000, P_GPLL9_OUT_MAIN, 2, 0, 0), 952*184fdd87SKonrad Dybcio F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 953*184fdd87SKonrad Dybcio F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 954*184fdd87SKonrad Dybcio F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 955*184fdd87SKonrad Dybcio F(329142857, P_GPLL10_OUT_EVEN, 3.5, 0, 0), 956*184fdd87SKonrad Dybcio F(384000000, P_GPLL10_OUT_EVEN, 3, 0, 0), 957*184fdd87SKonrad Dybcio F(460800000, P_GPLL10_OUT_EVEN, 2.5, 0, 0), 958*184fdd87SKonrad Dybcio F(576000000, P_GPLL10_OUT_EVEN, 2, 0, 0), 959*184fdd87SKonrad Dybcio { } 960*184fdd87SKonrad Dybcio }; 961*184fdd87SKonrad Dybcio 962*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_tfe_0_clk_src = { 963*184fdd87SKonrad Dybcio .cmd_rcgr = 0x52004, 964*184fdd87SKonrad Dybcio .mnd_width = 8, 965*184fdd87SKonrad Dybcio .hid_width = 5, 966*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_5, 967*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 968*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 969*184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_0_clk_src", 970*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_5, 971*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_5), 972*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 973*184fdd87SKonrad Dybcio }, 974*184fdd87SKonrad Dybcio }; 975*184fdd87SKonrad Dybcio 976*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = { 977*184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 978*184fdd87SKonrad Dybcio F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), 979*184fdd87SKonrad Dybcio F(266571429, P_GPLL5_OUT_EVEN, 3.5, 0, 0), 980*184fdd87SKonrad Dybcio F(426400000, P_GPLL3_OUT_MAIN, 2.5, 0, 0), 981*184fdd87SKonrad Dybcio F(466500000, P_GPLL5_OUT_EVEN, 2, 0, 0), 982*184fdd87SKonrad Dybcio { } 983*184fdd87SKonrad Dybcio }; 984*184fdd87SKonrad Dybcio 985*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = { 986*184fdd87SKonrad Dybcio .cmd_rcgr = 0x52094, 987*184fdd87SKonrad Dybcio .mnd_width = 0, 988*184fdd87SKonrad Dybcio .hid_width = 5, 989*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_6, 990*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 991*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 992*184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_0_csid_clk_src", 993*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_6, 994*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_6), 995*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 996*184fdd87SKonrad Dybcio }, 997*184fdd87SKonrad Dybcio }; 998*184fdd87SKonrad Dybcio 999*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_tfe_1_clk_src = { 1000*184fdd87SKonrad Dybcio .cmd_rcgr = 0x52024, 1001*184fdd87SKonrad Dybcio .mnd_width = 8, 1002*184fdd87SKonrad Dybcio .hid_width = 5, 1003*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_5, 1004*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 1005*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1006*184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_1_clk_src", 1007*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_5, 1008*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1009*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1010*184fdd87SKonrad Dybcio }, 1011*184fdd87SKonrad Dybcio }; 1012*184fdd87SKonrad Dybcio 1013*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = { 1014*184fdd87SKonrad Dybcio .cmd_rcgr = 0x520b4, 1015*184fdd87SKonrad Dybcio .mnd_width = 0, 1016*184fdd87SKonrad Dybcio .hid_width = 5, 1017*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_6, 1018*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 1019*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1020*184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_1_csid_clk_src", 1021*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_6, 1022*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1023*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1024*184fdd87SKonrad Dybcio }, 1025*184fdd87SKonrad Dybcio }; 1026*184fdd87SKonrad Dybcio 1027*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_tfe_2_clk_src = { 1028*184fdd87SKonrad Dybcio .cmd_rcgr = 0x52044, 1029*184fdd87SKonrad Dybcio .mnd_width = 8, 1030*184fdd87SKonrad Dybcio .hid_width = 5, 1031*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_5, 1032*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 1033*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1034*184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_2_clk_src", 1035*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_5, 1036*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1037*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1038*184fdd87SKonrad Dybcio }, 1039*184fdd87SKonrad Dybcio }; 1040*184fdd87SKonrad Dybcio 1041*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_tfe_2_csid_clk_src = { 1042*184fdd87SKonrad Dybcio .cmd_rcgr = 0x520d4, 1043*184fdd87SKonrad Dybcio .mnd_width = 0, 1044*184fdd87SKonrad Dybcio .hid_width = 5, 1045*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_6, 1046*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 1047*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1048*184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_2_csid_clk_src", 1049*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_6, 1050*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1051*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1052*184fdd87SKonrad Dybcio }, 1053*184fdd87SKonrad Dybcio }; 1054*184fdd87SKonrad Dybcio 1055*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = { 1056*184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 1057*184fdd87SKonrad Dybcio F(256000000, P_GPLL6_OUT_MAIN, 3, 0, 0), 1058*184fdd87SKonrad Dybcio F(384000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 1059*184fdd87SKonrad Dybcio { } 1060*184fdd87SKonrad Dybcio }; 1061*184fdd87SKonrad Dybcio 1062*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = { 1063*184fdd87SKonrad Dybcio .cmd_rcgr = 0x52064, 1064*184fdd87SKonrad Dybcio .mnd_width = 0, 1065*184fdd87SKonrad Dybcio .hid_width = 5, 1066*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_11, 1067*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src, 1068*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1069*184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_cphy_rx_clk_src", 1070*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_11, 1071*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_11), 1072*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1073*184fdd87SKonrad Dybcio }, 1074*184fdd87SKonrad Dybcio }; 1075*184fdd87SKonrad Dybcio 1076*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = { 1077*184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 1078*184fdd87SKonrad Dybcio F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0), 1079*184fdd87SKonrad Dybcio F(80000000, P_GPLL0_OUT_MAIN, 7.5, 0, 0), 1080*184fdd87SKonrad Dybcio { } 1081*184fdd87SKonrad Dybcio }; 1082*184fdd87SKonrad Dybcio 1083*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_camss_top_ahb_clk_src = { 1084*184fdd87SKonrad Dybcio .cmd_rcgr = 0x58010, 1085*184fdd87SKonrad Dybcio .mnd_width = 0, 1086*184fdd87SKonrad Dybcio .hid_width = 5, 1087*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_8, 1088*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_camss_top_ahb_clk_src, 1089*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1090*184fdd87SKonrad Dybcio .name = "gcc_camss_top_ahb_clk_src", 1091*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_8, 1092*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_8), 1093*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1094*184fdd87SKonrad Dybcio }, 1095*184fdd87SKonrad Dybcio }; 1096*184fdd87SKonrad Dybcio 1097*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { 1098*184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 1099*184fdd87SKonrad Dybcio F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0), 1100*184fdd87SKonrad Dybcio F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0), 1101*184fdd87SKonrad Dybcio { } 1102*184fdd87SKonrad Dybcio }; 1103*184fdd87SKonrad Dybcio 1104*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 1105*184fdd87SKonrad Dybcio .cmd_rcgr = 0x2b13c, 1106*184fdd87SKonrad Dybcio .mnd_width = 0, 1107*184fdd87SKonrad Dybcio .hid_width = 5, 1108*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_2, 1109*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, 1110*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1111*184fdd87SKonrad Dybcio .name = "gcc_cpuss_ahb_clk_src", 1112*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_2_ao, 1113*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_2_ao), 1114*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1115*184fdd87SKonrad Dybcio }, 1116*184fdd87SKonrad Dybcio }; 1117*184fdd87SKonrad Dybcio 1118*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 1119*184fdd87SKonrad Dybcio F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 1120*184fdd87SKonrad Dybcio F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0), 1121*184fdd87SKonrad Dybcio F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0), 1122*184fdd87SKonrad Dybcio F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0), 1123*184fdd87SKonrad Dybcio { } 1124*184fdd87SKonrad Dybcio }; 1125*184fdd87SKonrad Dybcio 1126*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_gp1_clk_src = { 1127*184fdd87SKonrad Dybcio .cmd_rcgr = 0x4d004, 1128*184fdd87SKonrad Dybcio .mnd_width = 16, 1129*184fdd87SKonrad Dybcio .hid_width = 5, 1130*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_7, 1131*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_gp1_clk_src, 1132*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1133*184fdd87SKonrad Dybcio .name = "gcc_gp1_clk_src", 1134*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_7, 1135*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_7), 1136*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1137*184fdd87SKonrad Dybcio }, 1138*184fdd87SKonrad Dybcio }; 1139*184fdd87SKonrad Dybcio 1140*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_gp2_clk_src = { 1141*184fdd87SKonrad Dybcio .cmd_rcgr = 0x4e004, 1142*184fdd87SKonrad Dybcio .mnd_width = 16, 1143*184fdd87SKonrad Dybcio .hid_width = 5, 1144*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_7, 1145*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_gp1_clk_src, 1146*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1147*184fdd87SKonrad Dybcio .name = "gcc_gp2_clk_src", 1148*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_7, 1149*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_7), 1150*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1151*184fdd87SKonrad Dybcio }, 1152*184fdd87SKonrad Dybcio }; 1153*184fdd87SKonrad Dybcio 1154*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_gp3_clk_src = { 1155*184fdd87SKonrad Dybcio .cmd_rcgr = 0x4f004, 1156*184fdd87SKonrad Dybcio .mnd_width = 16, 1157*184fdd87SKonrad Dybcio .hid_width = 5, 1158*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_7, 1159*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_gp1_clk_src, 1160*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1161*184fdd87SKonrad Dybcio .name = "gcc_gp3_clk_src", 1162*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_7, 1163*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_7), 1164*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1165*184fdd87SKonrad Dybcio }, 1166*184fdd87SKonrad Dybcio }; 1167*184fdd87SKonrad Dybcio 1168*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 1169*184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 1170*184fdd87SKonrad Dybcio F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), 1171*184fdd87SKonrad Dybcio { } 1172*184fdd87SKonrad Dybcio }; 1173*184fdd87SKonrad Dybcio 1174*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_pdm2_clk_src = { 1175*184fdd87SKonrad Dybcio .cmd_rcgr = 0x20010, 1176*184fdd87SKonrad Dybcio .mnd_width = 0, 1177*184fdd87SKonrad Dybcio .hid_width = 5, 1178*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_0, 1179*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_pdm2_clk_src, 1180*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1181*184fdd87SKonrad Dybcio .name = "gcc_pdm2_clk_src", 1182*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_0, 1183*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1184*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1185*184fdd87SKonrad Dybcio }, 1186*184fdd87SKonrad Dybcio }; 1187*184fdd87SKonrad Dybcio 1188*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 1189*184fdd87SKonrad Dybcio F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 1190*184fdd87SKonrad Dybcio F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 1191*184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 1192*184fdd87SKonrad Dybcio F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 1193*184fdd87SKonrad Dybcio F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 1194*184fdd87SKonrad Dybcio F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 1195*184fdd87SKonrad Dybcio F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 1196*184fdd87SKonrad Dybcio F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 1197*184fdd87SKonrad Dybcio F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 1198*184fdd87SKonrad Dybcio F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 1199*184fdd87SKonrad Dybcio F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 1200*184fdd87SKonrad Dybcio F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), 1201*184fdd87SKonrad Dybcio F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), 1202*184fdd87SKonrad Dybcio F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), 1203*184fdd87SKonrad Dybcio F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), 1204*184fdd87SKonrad Dybcio F(128000000, P_GPLL6_OUT_EVEN, 3, 0, 0), 1205*184fdd87SKonrad Dybcio { } 1206*184fdd87SKonrad Dybcio }; 1207*184fdd87SKonrad Dybcio 1208*184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 1209*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s0_clk_src", 1210*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1211*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1212*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1213*184fdd87SKonrad Dybcio }; 1214*184fdd87SKonrad Dybcio 1215*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 1216*184fdd87SKonrad Dybcio .cmd_rcgr = 0x1f148, 1217*184fdd87SKonrad Dybcio .mnd_width = 16, 1218*184fdd87SKonrad Dybcio .hid_width = 5, 1219*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1220*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1221*184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 1222*184fdd87SKonrad Dybcio }; 1223*184fdd87SKonrad Dybcio 1224*184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 1225*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s1_clk_src", 1226*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1227*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1228*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1229*184fdd87SKonrad Dybcio }; 1230*184fdd87SKonrad Dybcio 1231*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 1232*184fdd87SKonrad Dybcio .cmd_rcgr = 0x1f278, 1233*184fdd87SKonrad Dybcio .mnd_width = 16, 1234*184fdd87SKonrad Dybcio .hid_width = 5, 1235*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1236*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1237*184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 1238*184fdd87SKonrad Dybcio }; 1239*184fdd87SKonrad Dybcio 1240*184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 1241*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s2_clk_src", 1242*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1243*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1244*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1245*184fdd87SKonrad Dybcio }; 1246*184fdd87SKonrad Dybcio 1247*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 1248*184fdd87SKonrad Dybcio .cmd_rcgr = 0x1f3a8, 1249*184fdd87SKonrad Dybcio .mnd_width = 16, 1250*184fdd87SKonrad Dybcio .hid_width = 5, 1251*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1252*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1253*184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 1254*184fdd87SKonrad Dybcio }; 1255*184fdd87SKonrad Dybcio 1256*184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 1257*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s3_clk_src", 1258*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1259*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1260*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1261*184fdd87SKonrad Dybcio }; 1262*184fdd87SKonrad Dybcio 1263*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 1264*184fdd87SKonrad Dybcio .cmd_rcgr = 0x1f4d8, 1265*184fdd87SKonrad Dybcio .mnd_width = 16, 1266*184fdd87SKonrad Dybcio .hid_width = 5, 1267*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1268*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1269*184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 1270*184fdd87SKonrad Dybcio }; 1271*184fdd87SKonrad Dybcio 1272*184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 1273*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s4_clk_src", 1274*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1275*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1276*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1277*184fdd87SKonrad Dybcio }; 1278*184fdd87SKonrad Dybcio 1279*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 1280*184fdd87SKonrad Dybcio .cmd_rcgr = 0x1f608, 1281*184fdd87SKonrad Dybcio .mnd_width = 16, 1282*184fdd87SKonrad Dybcio .hid_width = 5, 1283*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1284*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1285*184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 1286*184fdd87SKonrad Dybcio }; 1287*184fdd87SKonrad Dybcio 1288*184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 1289*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s5_clk_src", 1290*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1291*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1292*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1293*184fdd87SKonrad Dybcio }; 1294*184fdd87SKonrad Dybcio 1295*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 1296*184fdd87SKonrad Dybcio .cmd_rcgr = 0x1f738, 1297*184fdd87SKonrad Dybcio .mnd_width = 16, 1298*184fdd87SKonrad Dybcio .hid_width = 5, 1299*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1300*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1301*184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 1302*184fdd87SKonrad Dybcio }; 1303*184fdd87SKonrad Dybcio 1304*184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 1305*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s0_clk_src", 1306*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1307*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1308*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1309*184fdd87SKonrad Dybcio }; 1310*184fdd87SKonrad Dybcio 1311*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 1312*184fdd87SKonrad Dybcio .cmd_rcgr = 0x5301c, 1313*184fdd87SKonrad Dybcio .mnd_width = 16, 1314*184fdd87SKonrad Dybcio .hid_width = 5, 1315*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1316*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1317*184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 1318*184fdd87SKonrad Dybcio }; 1319*184fdd87SKonrad Dybcio 1320*184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 1321*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s1_clk_src", 1322*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1323*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1324*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1325*184fdd87SKonrad Dybcio }; 1326*184fdd87SKonrad Dybcio 1327*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 1328*184fdd87SKonrad Dybcio .cmd_rcgr = 0x5314c, 1329*184fdd87SKonrad Dybcio .mnd_width = 16, 1330*184fdd87SKonrad Dybcio .hid_width = 5, 1331*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1332*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1333*184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 1334*184fdd87SKonrad Dybcio }; 1335*184fdd87SKonrad Dybcio 1336*184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 1337*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s2_clk_src", 1338*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1339*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1340*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1341*184fdd87SKonrad Dybcio }; 1342*184fdd87SKonrad Dybcio 1343*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 1344*184fdd87SKonrad Dybcio .cmd_rcgr = 0x5327c, 1345*184fdd87SKonrad Dybcio .mnd_width = 16, 1346*184fdd87SKonrad Dybcio .hid_width = 5, 1347*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1348*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1349*184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 1350*184fdd87SKonrad Dybcio }; 1351*184fdd87SKonrad Dybcio 1352*184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 1353*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s3_clk_src", 1354*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1355*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1356*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1357*184fdd87SKonrad Dybcio }; 1358*184fdd87SKonrad Dybcio 1359*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 1360*184fdd87SKonrad Dybcio .cmd_rcgr = 0x533ac, 1361*184fdd87SKonrad Dybcio .mnd_width = 16, 1362*184fdd87SKonrad Dybcio .hid_width = 5, 1363*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1364*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1365*184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 1366*184fdd87SKonrad Dybcio }; 1367*184fdd87SKonrad Dybcio 1368*184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 1369*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s4_clk_src", 1370*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1371*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1372*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1373*184fdd87SKonrad Dybcio }; 1374*184fdd87SKonrad Dybcio 1375*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 1376*184fdd87SKonrad Dybcio .cmd_rcgr = 0x534dc, 1377*184fdd87SKonrad Dybcio .mnd_width = 16, 1378*184fdd87SKonrad Dybcio .hid_width = 5, 1379*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1380*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1381*184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 1382*184fdd87SKonrad Dybcio }; 1383*184fdd87SKonrad Dybcio 1384*184fdd87SKonrad Dybcio static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 1385*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s5_clk_src", 1386*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1387*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1388*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1389*184fdd87SKonrad Dybcio }; 1390*184fdd87SKonrad Dybcio 1391*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 1392*184fdd87SKonrad Dybcio .cmd_rcgr = 0x5360c, 1393*184fdd87SKonrad Dybcio .mnd_width = 16, 1394*184fdd87SKonrad Dybcio .hid_width = 5, 1395*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1396*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1397*184fdd87SKonrad Dybcio .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 1398*184fdd87SKonrad Dybcio }; 1399*184fdd87SKonrad Dybcio 1400*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 1401*184fdd87SKonrad Dybcio F(144000, P_BI_TCXO, 16, 3, 25), 1402*184fdd87SKonrad Dybcio F(400000, P_BI_TCXO, 12, 1, 4), 1403*184fdd87SKonrad Dybcio F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), 1404*184fdd87SKonrad Dybcio F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), 1405*184fdd87SKonrad Dybcio F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 1406*184fdd87SKonrad Dybcio F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 1407*184fdd87SKonrad Dybcio F(192000000, P_GPLL6_OUT_EVEN, 2, 0, 0), 1408*184fdd87SKonrad Dybcio F(384000000, P_GPLL6_OUT_EVEN, 1, 0, 0), 1409*184fdd87SKonrad Dybcio { } 1410*184fdd87SKonrad Dybcio }; 1411*184fdd87SKonrad Dybcio 1412*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 1413*184fdd87SKonrad Dybcio .cmd_rcgr = 0x38028, 1414*184fdd87SKonrad Dybcio .mnd_width = 8, 1415*184fdd87SKonrad Dybcio .hid_width = 5, 1416*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_1, 1417*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 1418*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1419*184fdd87SKonrad Dybcio .name = "gcc_sdcc1_apps_clk_src", 1420*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_1, 1421*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1422*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1423*184fdd87SKonrad Dybcio }, 1424*184fdd87SKonrad Dybcio }; 1425*184fdd87SKonrad Dybcio 1426*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 1427*184fdd87SKonrad Dybcio F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 1428*184fdd87SKonrad Dybcio F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 1429*184fdd87SKonrad Dybcio F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 1430*184fdd87SKonrad Dybcio F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 1431*184fdd87SKonrad Dybcio F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 1432*184fdd87SKonrad Dybcio { } 1433*184fdd87SKonrad Dybcio }; 1434*184fdd87SKonrad Dybcio 1435*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 1436*184fdd87SKonrad Dybcio .cmd_rcgr = 0x38010, 1437*184fdd87SKonrad Dybcio .mnd_width = 0, 1438*184fdd87SKonrad Dybcio .hid_width = 5, 1439*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_0, 1440*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 1441*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1442*184fdd87SKonrad Dybcio .name = "gcc_sdcc1_ice_core_clk_src", 1443*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_0, 1444*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1445*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1446*184fdd87SKonrad Dybcio }, 1447*184fdd87SKonrad Dybcio }; 1448*184fdd87SKonrad Dybcio 1449*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1450*184fdd87SKonrad Dybcio F(400000, P_BI_TCXO, 12, 1, 4), 1451*184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 1452*184fdd87SKonrad Dybcio F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 1453*184fdd87SKonrad Dybcio F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 1454*184fdd87SKonrad Dybcio F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 1455*184fdd87SKonrad Dybcio F(202000000, P_GPLL7_OUT_EVEN, 4, 0, 0), 1456*184fdd87SKonrad Dybcio { } 1457*184fdd87SKonrad Dybcio }; 1458*184fdd87SKonrad Dybcio 1459*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1460*184fdd87SKonrad Dybcio .cmd_rcgr = 0x1e00c, 1461*184fdd87SKonrad Dybcio .mnd_width = 8, 1462*184fdd87SKonrad Dybcio .hid_width = 5, 1463*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_12, 1464*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1465*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1466*184fdd87SKonrad Dybcio .name = "gcc_sdcc2_apps_clk_src", 1467*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_12, 1468*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_12), 1469*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1470*184fdd87SKonrad Dybcio }, 1471*184fdd87SKonrad Dybcio }; 1472*184fdd87SKonrad Dybcio 1473*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1474*184fdd87SKonrad Dybcio F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 1475*184fdd87SKonrad Dybcio F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0), 1476*184fdd87SKonrad Dybcio F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0), 1477*184fdd87SKonrad Dybcio F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0), 1478*184fdd87SKonrad Dybcio F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 1479*184fdd87SKonrad Dybcio { } 1480*184fdd87SKonrad Dybcio }; 1481*184fdd87SKonrad Dybcio 1482*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1483*184fdd87SKonrad Dybcio .cmd_rcgr = 0x45020, 1484*184fdd87SKonrad Dybcio .mnd_width = 8, 1485*184fdd87SKonrad Dybcio .hid_width = 5, 1486*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_2, 1487*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1488*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1489*184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_axi_clk_src", 1490*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_2, 1491*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1492*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1493*184fdd87SKonrad Dybcio }, 1494*184fdd87SKonrad Dybcio }; 1495*184fdd87SKonrad Dybcio 1496*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1497*184fdd87SKonrad Dybcio F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 1498*184fdd87SKonrad Dybcio F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 1499*184fdd87SKonrad Dybcio F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 1500*184fdd87SKonrad Dybcio F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 1501*184fdd87SKonrad Dybcio { } 1502*184fdd87SKonrad Dybcio }; 1503*184fdd87SKonrad Dybcio 1504*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1505*184fdd87SKonrad Dybcio .cmd_rcgr = 0x45048, 1506*184fdd87SKonrad Dybcio .mnd_width = 0, 1507*184fdd87SKonrad Dybcio .hid_width = 5, 1508*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_0, 1509*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1510*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1511*184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_ice_core_clk_src", 1512*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_0, 1513*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1514*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1515*184fdd87SKonrad Dybcio }, 1516*184fdd87SKonrad Dybcio }; 1517*184fdd87SKonrad Dybcio 1518*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1519*184fdd87SKonrad Dybcio F(9600000, P_BI_TCXO, 2, 0, 0), 1520*184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 1521*184fdd87SKonrad Dybcio { } 1522*184fdd87SKonrad Dybcio }; 1523*184fdd87SKonrad Dybcio 1524*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1525*184fdd87SKonrad Dybcio .cmd_rcgr = 0x4507c, 1526*184fdd87SKonrad Dybcio .mnd_width = 0, 1527*184fdd87SKonrad Dybcio .hid_width = 5, 1528*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_0, 1529*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1530*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1531*184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_phy_aux_clk_src", 1532*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_0, 1533*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1534*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1535*184fdd87SKonrad Dybcio }, 1536*184fdd87SKonrad Dybcio }; 1537*184fdd87SKonrad Dybcio 1538*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 1539*184fdd87SKonrad Dybcio F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 1540*184fdd87SKonrad Dybcio F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 1541*184fdd87SKonrad Dybcio F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 1542*184fdd87SKonrad Dybcio { } 1543*184fdd87SKonrad Dybcio }; 1544*184fdd87SKonrad Dybcio 1545*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1546*184fdd87SKonrad Dybcio .cmd_rcgr = 0x45060, 1547*184fdd87SKonrad Dybcio .mnd_width = 0, 1548*184fdd87SKonrad Dybcio .hid_width = 5, 1549*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_0, 1550*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 1551*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1552*184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_unipro_core_clk_src", 1553*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_0, 1554*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1555*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1556*184fdd87SKonrad Dybcio }, 1557*184fdd87SKonrad Dybcio }; 1558*184fdd87SKonrad Dybcio 1559*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1560*184fdd87SKonrad Dybcio F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), 1561*184fdd87SKonrad Dybcio F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 1562*184fdd87SKonrad Dybcio F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0), 1563*184fdd87SKonrad Dybcio F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 1564*184fdd87SKonrad Dybcio { } 1565*184fdd87SKonrad Dybcio }; 1566*184fdd87SKonrad Dybcio 1567*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1568*184fdd87SKonrad Dybcio .cmd_rcgr = 0x1a01c, 1569*184fdd87SKonrad Dybcio .mnd_width = 8, 1570*184fdd87SKonrad Dybcio .hid_width = 5, 1571*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_2, 1572*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1573*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1574*184fdd87SKonrad Dybcio .name = "gcc_usb30_prim_master_clk_src", 1575*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_2, 1576*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1577*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1578*184fdd87SKonrad Dybcio }, 1579*184fdd87SKonrad Dybcio }; 1580*184fdd87SKonrad Dybcio 1581*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 1582*184fdd87SKonrad Dybcio F(19200000, P_BI_TCXO, 1, 0, 0), 1583*184fdd87SKonrad Dybcio { } 1584*184fdd87SKonrad Dybcio }; 1585*184fdd87SKonrad Dybcio 1586*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1587*184fdd87SKonrad Dybcio .cmd_rcgr = 0x1a034, 1588*184fdd87SKonrad Dybcio .mnd_width = 0, 1589*184fdd87SKonrad Dybcio .hid_width = 5, 1590*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_0, 1591*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1592*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1593*184fdd87SKonrad Dybcio .name = "gcc_usb30_prim_mock_utmi_clk_src", 1594*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_0, 1595*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1596*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1597*184fdd87SKonrad Dybcio }, 1598*184fdd87SKonrad Dybcio }; 1599*184fdd87SKonrad Dybcio 1600*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1601*184fdd87SKonrad Dybcio .cmd_rcgr = 0x1a060, 1602*184fdd87SKonrad Dybcio .mnd_width = 0, 1603*184fdd87SKonrad Dybcio .hid_width = 5, 1604*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_13, 1605*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1606*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1607*184fdd87SKonrad Dybcio .name = "gcc_usb3_prim_phy_aux_clk_src", 1608*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_13, 1609*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_13), 1610*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1611*184fdd87SKonrad Dybcio }, 1612*184fdd87SKonrad Dybcio }; 1613*184fdd87SKonrad Dybcio 1614*184fdd87SKonrad Dybcio static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = { 1615*184fdd87SKonrad Dybcio F(133000000, P_GPLL11_OUT_EVEN, 4, 0, 0), 1616*184fdd87SKonrad Dybcio F(240000000, P_GPLL11_OUT_EVEN, 2.5, 0, 0), 1617*184fdd87SKonrad Dybcio F(300000000, P_GPLL11_OUT_EVEN, 2, 0, 0), 1618*184fdd87SKonrad Dybcio F(384000000, P_GPLL11_OUT_EVEN, 2, 0, 0), 1619*184fdd87SKonrad Dybcio { } 1620*184fdd87SKonrad Dybcio }; 1621*184fdd87SKonrad Dybcio 1622*184fdd87SKonrad Dybcio static struct clk_rcg2 gcc_video_venus_clk_src = { 1623*184fdd87SKonrad Dybcio .cmd_rcgr = 0x58060, 1624*184fdd87SKonrad Dybcio .mnd_width = 0, 1625*184fdd87SKonrad Dybcio .hid_width = 5, 1626*184fdd87SKonrad Dybcio .parent_map = gcc_parent_map_14, 1627*184fdd87SKonrad Dybcio .freq_tbl = ftbl_gcc_video_venus_clk_src, 1628*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data){ 1629*184fdd87SKonrad Dybcio .name = "gcc_video_venus_clk_src", 1630*184fdd87SKonrad Dybcio .parent_data = gcc_parent_data_14, 1631*184fdd87SKonrad Dybcio .num_parents = ARRAY_SIZE(gcc_parent_data_14), 1632*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1633*184fdd87SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1634*184fdd87SKonrad Dybcio }, 1635*184fdd87SKonrad Dybcio }; 1636*184fdd87SKonrad Dybcio 1637*184fdd87SKonrad Dybcio static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = { 1638*184fdd87SKonrad Dybcio .reg = 0x2b154, 1639*184fdd87SKonrad Dybcio .shift = 0, 1640*184fdd87SKonrad Dybcio .width = 4, 1641*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data) { 1642*184fdd87SKonrad Dybcio .name = "gcc_cpuss_ahb_postdiv_clk_src", 1643*184fdd87SKonrad Dybcio .parent_hws = (const struct clk_hw*[]){ 1644*184fdd87SKonrad Dybcio &gcc_cpuss_ahb_clk_src.clkr.hw, 1645*184fdd87SKonrad Dybcio }, 1646*184fdd87SKonrad Dybcio .num_parents = 1, 1647*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1648*184fdd87SKonrad Dybcio .ops = &clk_regmap_div_ro_ops, 1649*184fdd87SKonrad Dybcio }, 1650*184fdd87SKonrad Dybcio }; 1651*184fdd87SKonrad Dybcio 1652*184fdd87SKonrad Dybcio static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1653*184fdd87SKonrad Dybcio .reg = 0x1a04c, 1654*184fdd87SKonrad Dybcio .shift = 0, 1655*184fdd87SKonrad Dybcio .width = 4, 1656*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data) { 1657*184fdd87SKonrad Dybcio .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1658*184fdd87SKonrad Dybcio .parent_hws = (const struct clk_hw*[]){ 1659*184fdd87SKonrad Dybcio &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1660*184fdd87SKonrad Dybcio }, 1661*184fdd87SKonrad Dybcio .num_parents = 1, 1662*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1663*184fdd87SKonrad Dybcio .ops = &clk_regmap_div_ro_ops, 1664*184fdd87SKonrad Dybcio }, 1665*184fdd87SKonrad Dybcio }; 1666*184fdd87SKonrad Dybcio 1667*184fdd87SKonrad Dybcio static struct clk_branch gcc_ahb2phy_csi_clk = { 1668*184fdd87SKonrad Dybcio .halt_reg = 0x1d004, 1669*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 1670*184fdd87SKonrad Dybcio .hwcg_reg = 0x1d004, 1671*184fdd87SKonrad Dybcio .hwcg_bit = 1, 1672*184fdd87SKonrad Dybcio .clkr = { 1673*184fdd87SKonrad Dybcio .enable_reg = 0x1d004, 1674*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1675*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1676*184fdd87SKonrad Dybcio .name = "gcc_ahb2phy_csi_clk", 1677*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1678*184fdd87SKonrad Dybcio }, 1679*184fdd87SKonrad Dybcio }, 1680*184fdd87SKonrad Dybcio }; 1681*184fdd87SKonrad Dybcio 1682*184fdd87SKonrad Dybcio static struct clk_branch gcc_ahb2phy_usb_clk = { 1683*184fdd87SKonrad Dybcio .halt_reg = 0x1d008, 1684*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 1685*184fdd87SKonrad Dybcio .hwcg_reg = 0x1d008, 1686*184fdd87SKonrad Dybcio .hwcg_bit = 1, 1687*184fdd87SKonrad Dybcio .clkr = { 1688*184fdd87SKonrad Dybcio .enable_reg = 0x1d008, 1689*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1690*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1691*184fdd87SKonrad Dybcio .name = "gcc_ahb2phy_usb_clk", 1692*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1693*184fdd87SKonrad Dybcio }, 1694*184fdd87SKonrad Dybcio }, 1695*184fdd87SKonrad Dybcio }; 1696*184fdd87SKonrad Dybcio 1697*184fdd87SKonrad Dybcio static struct clk_branch gcc_bimc_gpu_axi_clk = { 1698*184fdd87SKonrad Dybcio .halt_reg = 0x71154, 1699*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 1700*184fdd87SKonrad Dybcio .hwcg_reg = 0x71154, 1701*184fdd87SKonrad Dybcio .hwcg_bit = 1, 1702*184fdd87SKonrad Dybcio .clkr = { 1703*184fdd87SKonrad Dybcio .enable_reg = 0x71154, 1704*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1705*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1706*184fdd87SKonrad Dybcio .name = "gcc_bimc_gpu_axi_clk", 1707*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1708*184fdd87SKonrad Dybcio }, 1709*184fdd87SKonrad Dybcio }, 1710*184fdd87SKonrad Dybcio }; 1711*184fdd87SKonrad Dybcio 1712*184fdd87SKonrad Dybcio static struct clk_branch gcc_boot_rom_ahb_clk = { 1713*184fdd87SKonrad Dybcio .halt_reg = 0x23004, 1714*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 1715*184fdd87SKonrad Dybcio .hwcg_reg = 0x23004, 1716*184fdd87SKonrad Dybcio .hwcg_bit = 1, 1717*184fdd87SKonrad Dybcio .clkr = { 1718*184fdd87SKonrad Dybcio .enable_reg = 0x79004, 1719*184fdd87SKonrad Dybcio .enable_mask = BIT(10), 1720*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1721*184fdd87SKonrad Dybcio .name = "gcc_boot_rom_ahb_clk", 1722*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1723*184fdd87SKonrad Dybcio }, 1724*184fdd87SKonrad Dybcio }, 1725*184fdd87SKonrad Dybcio }; 1726*184fdd87SKonrad Dybcio 1727*184fdd87SKonrad Dybcio static struct clk_branch gcc_cam_throttle_nrt_clk = { 1728*184fdd87SKonrad Dybcio .halt_reg = 0x17070, 1729*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 1730*184fdd87SKonrad Dybcio .hwcg_reg = 0x17070, 1731*184fdd87SKonrad Dybcio .hwcg_bit = 1, 1732*184fdd87SKonrad Dybcio .clkr = { 1733*184fdd87SKonrad Dybcio .enable_reg = 0x79004, 1734*184fdd87SKonrad Dybcio .enable_mask = BIT(27), 1735*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1736*184fdd87SKonrad Dybcio .name = "gcc_cam_throttle_nrt_clk", 1737*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1738*184fdd87SKonrad Dybcio }, 1739*184fdd87SKonrad Dybcio }, 1740*184fdd87SKonrad Dybcio }; 1741*184fdd87SKonrad Dybcio 1742*184fdd87SKonrad Dybcio static struct clk_branch gcc_cam_throttle_rt_clk = { 1743*184fdd87SKonrad Dybcio .halt_reg = 0x1706c, 1744*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 1745*184fdd87SKonrad Dybcio .hwcg_reg = 0x1706c, 1746*184fdd87SKonrad Dybcio .hwcg_bit = 1, 1747*184fdd87SKonrad Dybcio .clkr = { 1748*184fdd87SKonrad Dybcio .enable_reg = 0x79004, 1749*184fdd87SKonrad Dybcio .enable_mask = BIT(26), 1750*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1751*184fdd87SKonrad Dybcio .name = "gcc_cam_throttle_rt_clk", 1752*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1753*184fdd87SKonrad Dybcio }, 1754*184fdd87SKonrad Dybcio }, 1755*184fdd87SKonrad Dybcio }; 1756*184fdd87SKonrad Dybcio 1757*184fdd87SKonrad Dybcio static struct clk_branch gcc_camera_ahb_clk = { 1758*184fdd87SKonrad Dybcio .halt_reg = 0x17008, 1759*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_DELAY, 1760*184fdd87SKonrad Dybcio .hwcg_reg = 0x17008, 1761*184fdd87SKonrad Dybcio .hwcg_bit = 1, 1762*184fdd87SKonrad Dybcio .clkr = { 1763*184fdd87SKonrad Dybcio .enable_reg = 0x17008, 1764*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1765*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1766*184fdd87SKonrad Dybcio .name = "gcc_camera_ahb_clk", 1767*184fdd87SKonrad Dybcio .flags = CLK_IS_CRITICAL, 1768*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1769*184fdd87SKonrad Dybcio }, 1770*184fdd87SKonrad Dybcio }, 1771*184fdd87SKonrad Dybcio }; 1772*184fdd87SKonrad Dybcio 1773*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_axi_clk = { 1774*184fdd87SKonrad Dybcio .halt_reg = 0x58044, 1775*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1776*184fdd87SKonrad Dybcio .clkr = { 1777*184fdd87SKonrad Dybcio .enable_reg = 0x58044, 1778*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1779*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1780*184fdd87SKonrad Dybcio .name = "gcc_camss_axi_clk", 1781*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 1782*184fdd87SKonrad Dybcio .hw = &gcc_camss_axi_clk_src.clkr.hw, 1783*184fdd87SKonrad Dybcio }, 1784*184fdd87SKonrad Dybcio .num_parents = 1, 1785*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1786*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1787*184fdd87SKonrad Dybcio }, 1788*184fdd87SKonrad Dybcio }, 1789*184fdd87SKonrad Dybcio }; 1790*184fdd87SKonrad Dybcio 1791*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_cci_0_clk = { 1792*184fdd87SKonrad Dybcio .halt_reg = 0x56018, 1793*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1794*184fdd87SKonrad Dybcio .clkr = { 1795*184fdd87SKonrad Dybcio .enable_reg = 0x56018, 1796*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1797*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1798*184fdd87SKonrad Dybcio .name = "gcc_camss_cci_0_clk", 1799*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 1800*184fdd87SKonrad Dybcio .hw = &gcc_camss_cci_0_clk_src.clkr.hw, 1801*184fdd87SKonrad Dybcio }, 1802*184fdd87SKonrad Dybcio .num_parents = 1, 1803*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1804*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1805*184fdd87SKonrad Dybcio }, 1806*184fdd87SKonrad Dybcio }, 1807*184fdd87SKonrad Dybcio }; 1808*184fdd87SKonrad Dybcio 1809*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_cci_1_clk = { 1810*184fdd87SKonrad Dybcio .halt_reg = 0x5c018, 1811*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1812*184fdd87SKonrad Dybcio .clkr = { 1813*184fdd87SKonrad Dybcio .enable_reg = 0x5c018, 1814*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1815*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1816*184fdd87SKonrad Dybcio .name = "gcc_camss_cci_1_clk", 1817*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 1818*184fdd87SKonrad Dybcio .hw = &gcc_camss_cci_1_clk_src.clkr.hw, 1819*184fdd87SKonrad Dybcio }, 1820*184fdd87SKonrad Dybcio .num_parents = 1, 1821*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1822*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1823*184fdd87SKonrad Dybcio }, 1824*184fdd87SKonrad Dybcio }, 1825*184fdd87SKonrad Dybcio }; 1826*184fdd87SKonrad Dybcio 1827*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_cphy_0_clk = { 1828*184fdd87SKonrad Dybcio .halt_reg = 0x52088, 1829*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1830*184fdd87SKonrad Dybcio .clkr = { 1831*184fdd87SKonrad Dybcio .enable_reg = 0x52088, 1832*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1833*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1834*184fdd87SKonrad Dybcio .name = "gcc_camss_cphy_0_clk", 1835*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 1836*184fdd87SKonrad Dybcio .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1837*184fdd87SKonrad Dybcio }, 1838*184fdd87SKonrad Dybcio .num_parents = 1, 1839*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1840*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1841*184fdd87SKonrad Dybcio }, 1842*184fdd87SKonrad Dybcio }, 1843*184fdd87SKonrad Dybcio }; 1844*184fdd87SKonrad Dybcio 1845*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_cphy_1_clk = { 1846*184fdd87SKonrad Dybcio .halt_reg = 0x5208c, 1847*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1848*184fdd87SKonrad Dybcio .clkr = { 1849*184fdd87SKonrad Dybcio .enable_reg = 0x5208c, 1850*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1851*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1852*184fdd87SKonrad Dybcio .name = "gcc_camss_cphy_1_clk", 1853*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 1854*184fdd87SKonrad Dybcio .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1855*184fdd87SKonrad Dybcio }, 1856*184fdd87SKonrad Dybcio .num_parents = 1, 1857*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1858*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1859*184fdd87SKonrad Dybcio }, 1860*184fdd87SKonrad Dybcio }, 1861*184fdd87SKonrad Dybcio }; 1862*184fdd87SKonrad Dybcio 1863*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_cphy_2_clk = { 1864*184fdd87SKonrad Dybcio .halt_reg = 0x52090, 1865*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1866*184fdd87SKonrad Dybcio .clkr = { 1867*184fdd87SKonrad Dybcio .enable_reg = 0x52090, 1868*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1869*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1870*184fdd87SKonrad Dybcio .name = "gcc_camss_cphy_2_clk", 1871*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 1872*184fdd87SKonrad Dybcio .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1873*184fdd87SKonrad Dybcio }, 1874*184fdd87SKonrad Dybcio .num_parents = 1, 1875*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1876*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1877*184fdd87SKonrad Dybcio }, 1878*184fdd87SKonrad Dybcio }, 1879*184fdd87SKonrad Dybcio }; 1880*184fdd87SKonrad Dybcio 1881*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_cphy_3_clk = { 1882*184fdd87SKonrad Dybcio .halt_reg = 0x520f8, 1883*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1884*184fdd87SKonrad Dybcio .clkr = { 1885*184fdd87SKonrad Dybcio .enable_reg = 0x520f8, 1886*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1887*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1888*184fdd87SKonrad Dybcio .name = "gcc_camss_cphy_3_clk", 1889*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 1890*184fdd87SKonrad Dybcio .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1891*184fdd87SKonrad Dybcio }, 1892*184fdd87SKonrad Dybcio .num_parents = 1, 1893*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1894*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1895*184fdd87SKonrad Dybcio }, 1896*184fdd87SKonrad Dybcio }, 1897*184fdd87SKonrad Dybcio }; 1898*184fdd87SKonrad Dybcio 1899*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_csi0phytimer_clk = { 1900*184fdd87SKonrad Dybcio .halt_reg = 0x59018, 1901*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1902*184fdd87SKonrad Dybcio .clkr = { 1903*184fdd87SKonrad Dybcio .enable_reg = 0x59018, 1904*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1905*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1906*184fdd87SKonrad Dybcio .name = "gcc_camss_csi0phytimer_clk", 1907*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 1908*184fdd87SKonrad Dybcio .hw = &gcc_camss_csi0phytimer_clk_src.clkr.hw, 1909*184fdd87SKonrad Dybcio }, 1910*184fdd87SKonrad Dybcio .num_parents = 1, 1911*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1912*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1913*184fdd87SKonrad Dybcio }, 1914*184fdd87SKonrad Dybcio }, 1915*184fdd87SKonrad Dybcio }; 1916*184fdd87SKonrad Dybcio 1917*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_csi1phytimer_clk = { 1918*184fdd87SKonrad Dybcio .halt_reg = 0x59034, 1919*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1920*184fdd87SKonrad Dybcio .clkr = { 1921*184fdd87SKonrad Dybcio .enable_reg = 0x59034, 1922*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1923*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1924*184fdd87SKonrad Dybcio .name = "gcc_camss_csi1phytimer_clk", 1925*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 1926*184fdd87SKonrad Dybcio .hw = &gcc_camss_csi1phytimer_clk_src.clkr.hw, 1927*184fdd87SKonrad Dybcio }, 1928*184fdd87SKonrad Dybcio .num_parents = 1, 1929*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1930*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1931*184fdd87SKonrad Dybcio }, 1932*184fdd87SKonrad Dybcio }, 1933*184fdd87SKonrad Dybcio }; 1934*184fdd87SKonrad Dybcio 1935*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_csi2phytimer_clk = { 1936*184fdd87SKonrad Dybcio .halt_reg = 0x59050, 1937*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1938*184fdd87SKonrad Dybcio .clkr = { 1939*184fdd87SKonrad Dybcio .enable_reg = 0x59050, 1940*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1941*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1942*184fdd87SKonrad Dybcio .name = "gcc_camss_csi2phytimer_clk", 1943*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 1944*184fdd87SKonrad Dybcio .hw = &gcc_camss_csi2phytimer_clk_src.clkr.hw, 1945*184fdd87SKonrad Dybcio }, 1946*184fdd87SKonrad Dybcio .num_parents = 1, 1947*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1948*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1949*184fdd87SKonrad Dybcio }, 1950*184fdd87SKonrad Dybcio }, 1951*184fdd87SKonrad Dybcio }; 1952*184fdd87SKonrad Dybcio 1953*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_csi3phytimer_clk = { 1954*184fdd87SKonrad Dybcio .halt_reg = 0x5906c, 1955*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1956*184fdd87SKonrad Dybcio .clkr = { 1957*184fdd87SKonrad Dybcio .enable_reg = 0x5906c, 1958*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1959*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1960*184fdd87SKonrad Dybcio .name = "gcc_camss_csi3phytimer_clk", 1961*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 1962*184fdd87SKonrad Dybcio .hw = &gcc_camss_csi3phytimer_clk_src.clkr.hw, 1963*184fdd87SKonrad Dybcio }, 1964*184fdd87SKonrad Dybcio .num_parents = 1, 1965*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1966*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1967*184fdd87SKonrad Dybcio }, 1968*184fdd87SKonrad Dybcio }, 1969*184fdd87SKonrad Dybcio }; 1970*184fdd87SKonrad Dybcio 1971*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_mclk0_clk = { 1972*184fdd87SKonrad Dybcio .halt_reg = 0x51018, 1973*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1974*184fdd87SKonrad Dybcio .clkr = { 1975*184fdd87SKonrad Dybcio .enable_reg = 0x51018, 1976*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1977*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1978*184fdd87SKonrad Dybcio .name = "gcc_camss_mclk0_clk", 1979*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 1980*184fdd87SKonrad Dybcio .hw = &gcc_camss_mclk0_clk_src.clkr.hw, 1981*184fdd87SKonrad Dybcio }, 1982*184fdd87SKonrad Dybcio .num_parents = 1, 1983*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 1984*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 1985*184fdd87SKonrad Dybcio }, 1986*184fdd87SKonrad Dybcio }, 1987*184fdd87SKonrad Dybcio }; 1988*184fdd87SKonrad Dybcio 1989*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_mclk1_clk = { 1990*184fdd87SKonrad Dybcio .halt_reg = 0x51034, 1991*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 1992*184fdd87SKonrad Dybcio .clkr = { 1993*184fdd87SKonrad Dybcio .enable_reg = 0x51034, 1994*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 1995*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 1996*184fdd87SKonrad Dybcio .name = "gcc_camss_mclk1_clk", 1997*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 1998*184fdd87SKonrad Dybcio .hw = &gcc_camss_mclk1_clk_src.clkr.hw, 1999*184fdd87SKonrad Dybcio }, 2000*184fdd87SKonrad Dybcio .num_parents = 1, 2001*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2002*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2003*184fdd87SKonrad Dybcio }, 2004*184fdd87SKonrad Dybcio }, 2005*184fdd87SKonrad Dybcio }; 2006*184fdd87SKonrad Dybcio 2007*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_mclk2_clk = { 2008*184fdd87SKonrad Dybcio .halt_reg = 0x51050, 2009*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2010*184fdd87SKonrad Dybcio .clkr = { 2011*184fdd87SKonrad Dybcio .enable_reg = 0x51050, 2012*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2013*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2014*184fdd87SKonrad Dybcio .name = "gcc_camss_mclk2_clk", 2015*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2016*184fdd87SKonrad Dybcio .hw = &gcc_camss_mclk2_clk_src.clkr.hw, 2017*184fdd87SKonrad Dybcio }, 2018*184fdd87SKonrad Dybcio .num_parents = 1, 2019*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2020*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2021*184fdd87SKonrad Dybcio }, 2022*184fdd87SKonrad Dybcio }, 2023*184fdd87SKonrad Dybcio }; 2024*184fdd87SKonrad Dybcio 2025*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_mclk3_clk = { 2026*184fdd87SKonrad Dybcio .halt_reg = 0x5106c, 2027*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2028*184fdd87SKonrad Dybcio .clkr = { 2029*184fdd87SKonrad Dybcio .enable_reg = 0x5106c, 2030*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2031*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2032*184fdd87SKonrad Dybcio .name = "gcc_camss_mclk3_clk", 2033*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2034*184fdd87SKonrad Dybcio .hw = &gcc_camss_mclk3_clk_src.clkr.hw, 2035*184fdd87SKonrad Dybcio }, 2036*184fdd87SKonrad Dybcio .num_parents = 1, 2037*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2038*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2039*184fdd87SKonrad Dybcio }, 2040*184fdd87SKonrad Dybcio }, 2041*184fdd87SKonrad Dybcio }; 2042*184fdd87SKonrad Dybcio 2043*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_mclk4_clk = { 2044*184fdd87SKonrad Dybcio .halt_reg = 0x51088, 2045*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2046*184fdd87SKonrad Dybcio .clkr = { 2047*184fdd87SKonrad Dybcio .enable_reg = 0x51088, 2048*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2049*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2050*184fdd87SKonrad Dybcio .name = "gcc_camss_mclk4_clk", 2051*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2052*184fdd87SKonrad Dybcio .hw = &gcc_camss_mclk4_clk_src.clkr.hw, 2053*184fdd87SKonrad Dybcio }, 2054*184fdd87SKonrad Dybcio .num_parents = 1, 2055*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2056*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2057*184fdd87SKonrad Dybcio }, 2058*184fdd87SKonrad Dybcio }, 2059*184fdd87SKonrad Dybcio }; 2060*184fdd87SKonrad Dybcio 2061*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_nrt_axi_clk = { 2062*184fdd87SKonrad Dybcio .halt_reg = 0x58054, 2063*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2064*184fdd87SKonrad Dybcio .clkr = { 2065*184fdd87SKonrad Dybcio .enable_reg = 0x58054, 2066*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2067*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2068*184fdd87SKonrad Dybcio .name = "gcc_camss_nrt_axi_clk", 2069*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2070*184fdd87SKonrad Dybcio }, 2071*184fdd87SKonrad Dybcio }, 2072*184fdd87SKonrad Dybcio }; 2073*184fdd87SKonrad Dybcio 2074*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_ope_ahb_clk = { 2075*184fdd87SKonrad Dybcio .halt_reg = 0x5503c, 2076*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2077*184fdd87SKonrad Dybcio .clkr = { 2078*184fdd87SKonrad Dybcio .enable_reg = 0x5503c, 2079*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2080*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2081*184fdd87SKonrad Dybcio .name = "gcc_camss_ope_ahb_clk", 2082*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2083*184fdd87SKonrad Dybcio .hw = &gcc_camss_ope_ahb_clk_src.clkr.hw, 2084*184fdd87SKonrad Dybcio }, 2085*184fdd87SKonrad Dybcio .num_parents = 1, 2086*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2087*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2088*184fdd87SKonrad Dybcio }, 2089*184fdd87SKonrad Dybcio }, 2090*184fdd87SKonrad Dybcio }; 2091*184fdd87SKonrad Dybcio 2092*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_ope_clk = { 2093*184fdd87SKonrad Dybcio .halt_reg = 0x5501c, 2094*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2095*184fdd87SKonrad Dybcio .clkr = { 2096*184fdd87SKonrad Dybcio .enable_reg = 0x5501c, 2097*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2098*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2099*184fdd87SKonrad Dybcio .name = "gcc_camss_ope_clk", 2100*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2101*184fdd87SKonrad Dybcio .hw = &gcc_camss_ope_clk_src.clkr.hw, 2102*184fdd87SKonrad Dybcio }, 2103*184fdd87SKonrad Dybcio .num_parents = 1, 2104*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2105*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2106*184fdd87SKonrad Dybcio }, 2107*184fdd87SKonrad Dybcio }, 2108*184fdd87SKonrad Dybcio }; 2109*184fdd87SKonrad Dybcio 2110*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_rt_axi_clk = { 2111*184fdd87SKonrad Dybcio .halt_reg = 0x5805c, 2112*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2113*184fdd87SKonrad Dybcio .clkr = { 2114*184fdd87SKonrad Dybcio .enable_reg = 0x5805c, 2115*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2116*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2117*184fdd87SKonrad Dybcio .name = "gcc_camss_rt_axi_clk", 2118*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2119*184fdd87SKonrad Dybcio }, 2120*184fdd87SKonrad Dybcio }, 2121*184fdd87SKonrad Dybcio }; 2122*184fdd87SKonrad Dybcio 2123*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_tfe_0_clk = { 2124*184fdd87SKonrad Dybcio .halt_reg = 0x5201c, 2125*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2126*184fdd87SKonrad Dybcio .clkr = { 2127*184fdd87SKonrad Dybcio .enable_reg = 0x5201c, 2128*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2129*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2130*184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_0_clk", 2131*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2132*184fdd87SKonrad Dybcio .hw = &gcc_camss_tfe_0_clk_src.clkr.hw, 2133*184fdd87SKonrad Dybcio }, 2134*184fdd87SKonrad Dybcio .num_parents = 1, 2135*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2136*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2137*184fdd87SKonrad Dybcio }, 2138*184fdd87SKonrad Dybcio }, 2139*184fdd87SKonrad Dybcio }; 2140*184fdd87SKonrad Dybcio 2141*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = { 2142*184fdd87SKonrad Dybcio .halt_reg = 0x5207c, 2143*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2144*184fdd87SKonrad Dybcio .clkr = { 2145*184fdd87SKonrad Dybcio .enable_reg = 0x5207c, 2146*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2147*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2148*184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_0_cphy_rx_clk", 2149*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2150*184fdd87SKonrad Dybcio .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2151*184fdd87SKonrad Dybcio }, 2152*184fdd87SKonrad Dybcio .num_parents = 1, 2153*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2154*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2155*184fdd87SKonrad Dybcio }, 2156*184fdd87SKonrad Dybcio }, 2157*184fdd87SKonrad Dybcio }; 2158*184fdd87SKonrad Dybcio 2159*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_tfe_0_csid_clk = { 2160*184fdd87SKonrad Dybcio .halt_reg = 0x520ac, 2161*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2162*184fdd87SKonrad Dybcio .clkr = { 2163*184fdd87SKonrad Dybcio .enable_reg = 0x520ac, 2164*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2165*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2166*184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_0_csid_clk", 2167*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2168*184fdd87SKonrad Dybcio .hw = &gcc_camss_tfe_0_csid_clk_src.clkr.hw, 2169*184fdd87SKonrad Dybcio }, 2170*184fdd87SKonrad Dybcio .num_parents = 1, 2171*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2172*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2173*184fdd87SKonrad Dybcio }, 2174*184fdd87SKonrad Dybcio }, 2175*184fdd87SKonrad Dybcio }; 2176*184fdd87SKonrad Dybcio 2177*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_tfe_1_clk = { 2178*184fdd87SKonrad Dybcio .halt_reg = 0x5203c, 2179*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2180*184fdd87SKonrad Dybcio .clkr = { 2181*184fdd87SKonrad Dybcio .enable_reg = 0x5203c, 2182*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2183*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2184*184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_1_clk", 2185*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2186*184fdd87SKonrad Dybcio .hw = &gcc_camss_tfe_1_clk_src.clkr.hw, 2187*184fdd87SKonrad Dybcio }, 2188*184fdd87SKonrad Dybcio .num_parents = 1, 2189*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2190*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2191*184fdd87SKonrad Dybcio }, 2192*184fdd87SKonrad Dybcio }, 2193*184fdd87SKonrad Dybcio }; 2194*184fdd87SKonrad Dybcio 2195*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = { 2196*184fdd87SKonrad Dybcio .halt_reg = 0x52080, 2197*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2198*184fdd87SKonrad Dybcio .clkr = { 2199*184fdd87SKonrad Dybcio .enable_reg = 0x52080, 2200*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2201*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2202*184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_1_cphy_rx_clk", 2203*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2204*184fdd87SKonrad Dybcio .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2205*184fdd87SKonrad Dybcio }, 2206*184fdd87SKonrad Dybcio .num_parents = 1, 2207*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2208*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2209*184fdd87SKonrad Dybcio }, 2210*184fdd87SKonrad Dybcio }, 2211*184fdd87SKonrad Dybcio }; 2212*184fdd87SKonrad Dybcio 2213*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_tfe_1_csid_clk = { 2214*184fdd87SKonrad Dybcio .halt_reg = 0x520cc, 2215*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2216*184fdd87SKonrad Dybcio .clkr = { 2217*184fdd87SKonrad Dybcio .enable_reg = 0x520cc, 2218*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2219*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2220*184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_1_csid_clk", 2221*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2222*184fdd87SKonrad Dybcio .hw = &gcc_camss_tfe_1_csid_clk_src.clkr.hw, 2223*184fdd87SKonrad Dybcio }, 2224*184fdd87SKonrad Dybcio .num_parents = 1, 2225*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2226*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2227*184fdd87SKonrad Dybcio }, 2228*184fdd87SKonrad Dybcio }, 2229*184fdd87SKonrad Dybcio }; 2230*184fdd87SKonrad Dybcio 2231*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_tfe_2_clk = { 2232*184fdd87SKonrad Dybcio .halt_reg = 0x5205c, 2233*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2234*184fdd87SKonrad Dybcio .clkr = { 2235*184fdd87SKonrad Dybcio .enable_reg = 0x5205c, 2236*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2237*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2238*184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_2_clk", 2239*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2240*184fdd87SKonrad Dybcio .hw = &gcc_camss_tfe_2_clk_src.clkr.hw, 2241*184fdd87SKonrad Dybcio }, 2242*184fdd87SKonrad Dybcio .num_parents = 1, 2243*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2244*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2245*184fdd87SKonrad Dybcio }, 2246*184fdd87SKonrad Dybcio }, 2247*184fdd87SKonrad Dybcio }; 2248*184fdd87SKonrad Dybcio 2249*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_tfe_2_cphy_rx_clk = { 2250*184fdd87SKonrad Dybcio .halt_reg = 0x52084, 2251*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2252*184fdd87SKonrad Dybcio .clkr = { 2253*184fdd87SKonrad Dybcio .enable_reg = 0x52084, 2254*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2255*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2256*184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_2_cphy_rx_clk", 2257*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2258*184fdd87SKonrad Dybcio .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2259*184fdd87SKonrad Dybcio }, 2260*184fdd87SKonrad Dybcio .num_parents = 1, 2261*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2262*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2263*184fdd87SKonrad Dybcio }, 2264*184fdd87SKonrad Dybcio }, 2265*184fdd87SKonrad Dybcio }; 2266*184fdd87SKonrad Dybcio 2267*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_tfe_2_csid_clk = { 2268*184fdd87SKonrad Dybcio .halt_reg = 0x520ec, 2269*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2270*184fdd87SKonrad Dybcio .clkr = { 2271*184fdd87SKonrad Dybcio .enable_reg = 0x520ec, 2272*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2273*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2274*184fdd87SKonrad Dybcio .name = "gcc_camss_tfe_2_csid_clk", 2275*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2276*184fdd87SKonrad Dybcio .hw = &gcc_camss_tfe_2_csid_clk_src.clkr.hw, 2277*184fdd87SKonrad Dybcio }, 2278*184fdd87SKonrad Dybcio .num_parents = 1, 2279*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2280*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2281*184fdd87SKonrad Dybcio }, 2282*184fdd87SKonrad Dybcio }, 2283*184fdd87SKonrad Dybcio }; 2284*184fdd87SKonrad Dybcio 2285*184fdd87SKonrad Dybcio static struct clk_branch gcc_camss_top_ahb_clk = { 2286*184fdd87SKonrad Dybcio .halt_reg = 0x58028, 2287*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2288*184fdd87SKonrad Dybcio .clkr = { 2289*184fdd87SKonrad Dybcio .enable_reg = 0x58028, 2290*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2291*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2292*184fdd87SKonrad Dybcio .name = "gcc_camss_top_ahb_clk", 2293*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2294*184fdd87SKonrad Dybcio .hw = &gcc_camss_top_ahb_clk_src.clkr.hw, 2295*184fdd87SKonrad Dybcio }, 2296*184fdd87SKonrad Dybcio .num_parents = 1, 2297*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2298*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2299*184fdd87SKonrad Dybcio }, 2300*184fdd87SKonrad Dybcio }, 2301*184fdd87SKonrad Dybcio }; 2302*184fdd87SKonrad Dybcio 2303*184fdd87SKonrad Dybcio static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 2304*184fdd87SKonrad Dybcio .halt_reg = 0x1a084, 2305*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2306*184fdd87SKonrad Dybcio .hwcg_reg = 0x1a084, 2307*184fdd87SKonrad Dybcio .hwcg_bit = 1, 2308*184fdd87SKonrad Dybcio .clkr = { 2309*184fdd87SKonrad Dybcio .enable_reg = 0x1a084, 2310*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2311*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2312*184fdd87SKonrad Dybcio .name = "gcc_cfg_noc_usb3_prim_axi_clk", 2313*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2314*184fdd87SKonrad Dybcio .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 2315*184fdd87SKonrad Dybcio }, 2316*184fdd87SKonrad Dybcio .num_parents = 1, 2317*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2318*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2319*184fdd87SKonrad Dybcio }, 2320*184fdd87SKonrad Dybcio }, 2321*184fdd87SKonrad Dybcio }; 2322*184fdd87SKonrad Dybcio 2323*184fdd87SKonrad Dybcio static struct clk_branch gcc_disp_ahb_clk = { 2324*184fdd87SKonrad Dybcio .halt_reg = 0x1700c, 2325*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2326*184fdd87SKonrad Dybcio .hwcg_reg = 0x1700c, 2327*184fdd87SKonrad Dybcio .hwcg_bit = 1, 2328*184fdd87SKonrad Dybcio .clkr = { 2329*184fdd87SKonrad Dybcio .enable_reg = 0x1700c, 2330*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2331*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2332*184fdd87SKonrad Dybcio .name = "gcc_disp_ahb_clk", 2333*184fdd87SKonrad Dybcio .flags = CLK_IS_CRITICAL, 2334*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2335*184fdd87SKonrad Dybcio }, 2336*184fdd87SKonrad Dybcio }, 2337*184fdd87SKonrad Dybcio }; 2338*184fdd87SKonrad Dybcio 2339*184fdd87SKonrad Dybcio static struct clk_regmap_div gcc_disp_gpll0_clk_src = { 2340*184fdd87SKonrad Dybcio .reg = 0x17058, 2341*184fdd87SKonrad Dybcio .shift = 0, 2342*184fdd87SKonrad Dybcio .width = 2, 2343*184fdd87SKonrad Dybcio .clkr.hw.init = &(struct clk_init_data) { 2344*184fdd87SKonrad Dybcio .name = "gcc_disp_gpll0_clk_src", 2345*184fdd87SKonrad Dybcio .parent_names = 2346*184fdd87SKonrad Dybcio (const char *[]){ "gpll0" }, 2347*184fdd87SKonrad Dybcio .num_parents = 1, 2348*184fdd87SKonrad Dybcio .ops = &clk_regmap_div_ops, 2349*184fdd87SKonrad Dybcio }, 2350*184fdd87SKonrad Dybcio }; 2351*184fdd87SKonrad Dybcio 2352*184fdd87SKonrad Dybcio static struct clk_branch gcc_disp_gpll0_div_clk_src = { 2353*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_DELAY, 2354*184fdd87SKonrad Dybcio .clkr = { 2355*184fdd87SKonrad Dybcio .enable_reg = 0x79004, 2356*184fdd87SKonrad Dybcio .enable_mask = BIT(20), 2357*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2358*184fdd87SKonrad Dybcio .name = "gcc_disp_gpll0_div_clk_src", 2359*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2360*184fdd87SKonrad Dybcio .hw = &gcc_disp_gpll0_clk_src.clkr.hw, 2361*184fdd87SKonrad Dybcio }, 2362*184fdd87SKonrad Dybcio .num_parents = 1, 2363*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2364*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2365*184fdd87SKonrad Dybcio }, 2366*184fdd87SKonrad Dybcio }, 2367*184fdd87SKonrad Dybcio }; 2368*184fdd87SKonrad Dybcio 2369*184fdd87SKonrad Dybcio static struct clk_branch gcc_disp_hf_axi_clk = { 2370*184fdd87SKonrad Dybcio .halt_reg = 0x17020, 2371*184fdd87SKonrad Dybcio .halt_check = BRANCH_VOTED, 2372*184fdd87SKonrad Dybcio .hwcg_reg = 0x17020, 2373*184fdd87SKonrad Dybcio .hwcg_bit = 1, 2374*184fdd87SKonrad Dybcio .clkr = { 2375*184fdd87SKonrad Dybcio .enable_reg = 0x17020, 2376*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2377*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2378*184fdd87SKonrad Dybcio .name = "gcc_disp_hf_axi_clk", 2379*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2380*184fdd87SKonrad Dybcio }, 2381*184fdd87SKonrad Dybcio }, 2382*184fdd87SKonrad Dybcio }; 2383*184fdd87SKonrad Dybcio 2384*184fdd87SKonrad Dybcio static struct clk_branch gcc_disp_sleep_clk = { 2385*184fdd87SKonrad Dybcio .halt_reg = 0x17074, 2386*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2387*184fdd87SKonrad Dybcio .hwcg_reg = 0x17074, 2388*184fdd87SKonrad Dybcio .hwcg_bit = 1, 2389*184fdd87SKonrad Dybcio .clkr = { 2390*184fdd87SKonrad Dybcio .enable_reg = 0x17074, 2391*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2392*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2393*184fdd87SKonrad Dybcio .name = "gcc_disp_sleep_clk", 2394*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2395*184fdd87SKonrad Dybcio }, 2396*184fdd87SKonrad Dybcio }, 2397*184fdd87SKonrad Dybcio }; 2398*184fdd87SKonrad Dybcio 2399*184fdd87SKonrad Dybcio static struct clk_branch gcc_disp_throttle_core_clk = { 2400*184fdd87SKonrad Dybcio .halt_reg = 0x17064, 2401*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2402*184fdd87SKonrad Dybcio .hwcg_reg = 0x17064, 2403*184fdd87SKonrad Dybcio .hwcg_bit = 1, 2404*184fdd87SKonrad Dybcio .clkr = { 2405*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2406*184fdd87SKonrad Dybcio .enable_mask = BIT(5), 2407*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2408*184fdd87SKonrad Dybcio .name = "gcc_disp_throttle_core_clk", 2409*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2410*184fdd87SKonrad Dybcio }, 2411*184fdd87SKonrad Dybcio }, 2412*184fdd87SKonrad Dybcio }; 2413*184fdd87SKonrad Dybcio 2414*184fdd87SKonrad Dybcio static struct clk_branch gcc_gp1_clk = { 2415*184fdd87SKonrad Dybcio .halt_reg = 0x4d000, 2416*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2417*184fdd87SKonrad Dybcio .clkr = { 2418*184fdd87SKonrad Dybcio .enable_reg = 0x4d000, 2419*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2420*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2421*184fdd87SKonrad Dybcio .name = "gcc_gp1_clk", 2422*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2423*184fdd87SKonrad Dybcio .hw = &gcc_gp1_clk_src.clkr.hw, 2424*184fdd87SKonrad Dybcio }, 2425*184fdd87SKonrad Dybcio .num_parents = 1, 2426*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2427*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2428*184fdd87SKonrad Dybcio }, 2429*184fdd87SKonrad Dybcio }, 2430*184fdd87SKonrad Dybcio }; 2431*184fdd87SKonrad Dybcio 2432*184fdd87SKonrad Dybcio static struct clk_branch gcc_gp2_clk = { 2433*184fdd87SKonrad Dybcio .halt_reg = 0x4e000, 2434*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2435*184fdd87SKonrad Dybcio .clkr = { 2436*184fdd87SKonrad Dybcio .enable_reg = 0x4e000, 2437*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2438*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2439*184fdd87SKonrad Dybcio .name = "gcc_gp2_clk", 2440*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2441*184fdd87SKonrad Dybcio .hw = &gcc_gp2_clk_src.clkr.hw, 2442*184fdd87SKonrad Dybcio }, 2443*184fdd87SKonrad Dybcio .num_parents = 1, 2444*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2445*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2446*184fdd87SKonrad Dybcio }, 2447*184fdd87SKonrad Dybcio }, 2448*184fdd87SKonrad Dybcio }; 2449*184fdd87SKonrad Dybcio 2450*184fdd87SKonrad Dybcio static struct clk_branch gcc_gp3_clk = { 2451*184fdd87SKonrad Dybcio .halt_reg = 0x4f000, 2452*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2453*184fdd87SKonrad Dybcio .clkr = { 2454*184fdd87SKonrad Dybcio .enable_reg = 0x4f000, 2455*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2456*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2457*184fdd87SKonrad Dybcio .name = "gcc_gp3_clk", 2458*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2459*184fdd87SKonrad Dybcio .hw = &gcc_gp3_clk_src.clkr.hw, 2460*184fdd87SKonrad Dybcio }, 2461*184fdd87SKonrad Dybcio .num_parents = 1, 2462*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2463*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2464*184fdd87SKonrad Dybcio }, 2465*184fdd87SKonrad Dybcio }, 2466*184fdd87SKonrad Dybcio }; 2467*184fdd87SKonrad Dybcio 2468*184fdd87SKonrad Dybcio static struct clk_branch gcc_gpu_cfg_ahb_clk = { 2469*184fdd87SKonrad Dybcio .halt_reg = 0x36004, 2470*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2471*184fdd87SKonrad Dybcio .hwcg_reg = 0x36004, 2472*184fdd87SKonrad Dybcio .hwcg_bit = 1, 2473*184fdd87SKonrad Dybcio .clkr = { 2474*184fdd87SKonrad Dybcio .enable_reg = 0x36004, 2475*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2476*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2477*184fdd87SKonrad Dybcio .name = "gcc_gpu_cfg_ahb_clk", 2478*184fdd87SKonrad Dybcio .flags = CLK_IS_CRITICAL, 2479*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2480*184fdd87SKonrad Dybcio }, 2481*184fdd87SKonrad Dybcio }, 2482*184fdd87SKonrad Dybcio }; 2483*184fdd87SKonrad Dybcio 2484*184fdd87SKonrad Dybcio static struct clk_branch gcc_gpu_gpll0_clk_src = { 2485*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_DELAY, 2486*184fdd87SKonrad Dybcio .clkr = { 2487*184fdd87SKonrad Dybcio .enable_reg = 0x79004, 2488*184fdd87SKonrad Dybcio .enable_mask = BIT(15), 2489*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2490*184fdd87SKonrad Dybcio .name = "gcc_gpu_gpll0_clk_src", 2491*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2492*184fdd87SKonrad Dybcio .hw = &gpll0.clkr.hw, 2493*184fdd87SKonrad Dybcio }, 2494*184fdd87SKonrad Dybcio .num_parents = 1, 2495*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2496*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2497*184fdd87SKonrad Dybcio }, 2498*184fdd87SKonrad Dybcio }, 2499*184fdd87SKonrad Dybcio }; 2500*184fdd87SKonrad Dybcio 2501*184fdd87SKonrad Dybcio static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 2502*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_DELAY, 2503*184fdd87SKonrad Dybcio .clkr = { 2504*184fdd87SKonrad Dybcio .enable_reg = 0x79004, 2505*184fdd87SKonrad Dybcio .enable_mask = BIT(16), 2506*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2507*184fdd87SKonrad Dybcio .name = "gcc_gpu_gpll0_div_clk_src", 2508*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2509*184fdd87SKonrad Dybcio .hw = &gpll0_out_even.clkr.hw, 2510*184fdd87SKonrad Dybcio }, 2511*184fdd87SKonrad Dybcio .num_parents = 1, 2512*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2513*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2514*184fdd87SKonrad Dybcio }, 2515*184fdd87SKonrad Dybcio }, 2516*184fdd87SKonrad Dybcio }; 2517*184fdd87SKonrad Dybcio 2518*184fdd87SKonrad Dybcio static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 2519*184fdd87SKonrad Dybcio .halt_reg = 0x3600c, 2520*184fdd87SKonrad Dybcio .halt_check = BRANCH_VOTED, 2521*184fdd87SKonrad Dybcio .hwcg_reg = 0x3600c, 2522*184fdd87SKonrad Dybcio .hwcg_bit = 1, 2523*184fdd87SKonrad Dybcio .clkr = { 2524*184fdd87SKonrad Dybcio .enable_reg = 0x3600c, 2525*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2526*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2527*184fdd87SKonrad Dybcio .name = "gcc_gpu_memnoc_gfx_clk", 2528*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2529*184fdd87SKonrad Dybcio }, 2530*184fdd87SKonrad Dybcio }, 2531*184fdd87SKonrad Dybcio }; 2532*184fdd87SKonrad Dybcio 2533*184fdd87SKonrad Dybcio static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2534*184fdd87SKonrad Dybcio .halt_reg = 0x36018, 2535*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2536*184fdd87SKonrad Dybcio .clkr = { 2537*184fdd87SKonrad Dybcio .enable_reg = 0x36018, 2538*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2539*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2540*184fdd87SKonrad Dybcio .name = "gcc_gpu_snoc_dvm_gfx_clk", 2541*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2542*184fdd87SKonrad Dybcio }, 2543*184fdd87SKonrad Dybcio }, 2544*184fdd87SKonrad Dybcio }; 2545*184fdd87SKonrad Dybcio 2546*184fdd87SKonrad Dybcio static struct clk_branch gcc_gpu_throttle_core_clk = { 2547*184fdd87SKonrad Dybcio .halt_reg = 0x36048, 2548*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2549*184fdd87SKonrad Dybcio .hwcg_reg = 0x36048, 2550*184fdd87SKonrad Dybcio .hwcg_bit = 1, 2551*184fdd87SKonrad Dybcio .clkr = { 2552*184fdd87SKonrad Dybcio .enable_reg = 0x79004, 2553*184fdd87SKonrad Dybcio .enable_mask = BIT(31), 2554*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2555*184fdd87SKonrad Dybcio .name = "gcc_gpu_throttle_core_clk", 2556*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2557*184fdd87SKonrad Dybcio }, 2558*184fdd87SKonrad Dybcio }, 2559*184fdd87SKonrad Dybcio }; 2560*184fdd87SKonrad Dybcio 2561*184fdd87SKonrad Dybcio static struct clk_branch gcc_pdm2_clk = { 2562*184fdd87SKonrad Dybcio .halt_reg = 0x2000c, 2563*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2564*184fdd87SKonrad Dybcio .clkr = { 2565*184fdd87SKonrad Dybcio .enable_reg = 0x2000c, 2566*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2567*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2568*184fdd87SKonrad Dybcio .name = "gcc_pdm2_clk", 2569*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2570*184fdd87SKonrad Dybcio .hw = &gcc_pdm2_clk_src.clkr.hw, 2571*184fdd87SKonrad Dybcio }, 2572*184fdd87SKonrad Dybcio .num_parents = 1, 2573*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2574*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2575*184fdd87SKonrad Dybcio }, 2576*184fdd87SKonrad Dybcio }, 2577*184fdd87SKonrad Dybcio }; 2578*184fdd87SKonrad Dybcio 2579*184fdd87SKonrad Dybcio static struct clk_branch gcc_pdm_ahb_clk = { 2580*184fdd87SKonrad Dybcio .halt_reg = 0x20004, 2581*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2582*184fdd87SKonrad Dybcio .hwcg_reg = 0x20004, 2583*184fdd87SKonrad Dybcio .hwcg_bit = 1, 2584*184fdd87SKonrad Dybcio .clkr = { 2585*184fdd87SKonrad Dybcio .enable_reg = 0x20004, 2586*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2587*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2588*184fdd87SKonrad Dybcio .name = "gcc_pdm_ahb_clk", 2589*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2590*184fdd87SKonrad Dybcio }, 2591*184fdd87SKonrad Dybcio }, 2592*184fdd87SKonrad Dybcio }; 2593*184fdd87SKonrad Dybcio 2594*184fdd87SKonrad Dybcio static struct clk_branch gcc_pdm_xo4_clk = { 2595*184fdd87SKonrad Dybcio .halt_reg = 0x20008, 2596*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 2597*184fdd87SKonrad Dybcio .clkr = { 2598*184fdd87SKonrad Dybcio .enable_reg = 0x20008, 2599*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2600*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2601*184fdd87SKonrad Dybcio .name = "gcc_pdm_xo4_clk", 2602*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2603*184fdd87SKonrad Dybcio }, 2604*184fdd87SKonrad Dybcio }, 2605*184fdd87SKonrad Dybcio }; 2606*184fdd87SKonrad Dybcio 2607*184fdd87SKonrad Dybcio static struct clk_branch gcc_prng_ahb_clk = { 2608*184fdd87SKonrad Dybcio .halt_reg = 0x21004, 2609*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2610*184fdd87SKonrad Dybcio .hwcg_reg = 0x21004, 2611*184fdd87SKonrad Dybcio .hwcg_bit = 1, 2612*184fdd87SKonrad Dybcio .clkr = { 2613*184fdd87SKonrad Dybcio .enable_reg = 0x79004, 2614*184fdd87SKonrad Dybcio .enable_mask = BIT(13), 2615*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2616*184fdd87SKonrad Dybcio .name = "gcc_prng_ahb_clk", 2617*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2618*184fdd87SKonrad Dybcio }, 2619*184fdd87SKonrad Dybcio }, 2620*184fdd87SKonrad Dybcio }; 2621*184fdd87SKonrad Dybcio 2622*184fdd87SKonrad Dybcio static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2623*184fdd87SKonrad Dybcio .halt_reg = 0x17014, 2624*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2625*184fdd87SKonrad Dybcio .hwcg_reg = 0x17014, 2626*184fdd87SKonrad Dybcio .hwcg_bit = 1, 2627*184fdd87SKonrad Dybcio .clkr = { 2628*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2629*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 2630*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2631*184fdd87SKonrad Dybcio .name = "gcc_qmip_camera_nrt_ahb_clk", 2632*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2633*184fdd87SKonrad Dybcio }, 2634*184fdd87SKonrad Dybcio }, 2635*184fdd87SKonrad Dybcio }; 2636*184fdd87SKonrad Dybcio 2637*184fdd87SKonrad Dybcio static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2638*184fdd87SKonrad Dybcio .halt_reg = 0x17060, 2639*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2640*184fdd87SKonrad Dybcio .hwcg_reg = 0x17060, 2641*184fdd87SKonrad Dybcio .hwcg_bit = 1, 2642*184fdd87SKonrad Dybcio .clkr = { 2643*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2644*184fdd87SKonrad Dybcio .enable_mask = BIT(2), 2645*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2646*184fdd87SKonrad Dybcio .name = "gcc_qmip_camera_rt_ahb_clk", 2647*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2648*184fdd87SKonrad Dybcio }, 2649*184fdd87SKonrad Dybcio }, 2650*184fdd87SKonrad Dybcio }; 2651*184fdd87SKonrad Dybcio 2652*184fdd87SKonrad Dybcio static struct clk_branch gcc_qmip_disp_ahb_clk = { 2653*184fdd87SKonrad Dybcio .halt_reg = 0x17018, 2654*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2655*184fdd87SKonrad Dybcio .hwcg_reg = 0x17018, 2656*184fdd87SKonrad Dybcio .hwcg_bit = 1, 2657*184fdd87SKonrad Dybcio .clkr = { 2658*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2659*184fdd87SKonrad Dybcio .enable_mask = BIT(1), 2660*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2661*184fdd87SKonrad Dybcio .name = "gcc_qmip_disp_ahb_clk", 2662*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2663*184fdd87SKonrad Dybcio }, 2664*184fdd87SKonrad Dybcio }, 2665*184fdd87SKonrad Dybcio }; 2666*184fdd87SKonrad Dybcio 2667*184fdd87SKonrad Dybcio static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = { 2668*184fdd87SKonrad Dybcio .halt_reg = 0x36040, 2669*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2670*184fdd87SKonrad Dybcio .hwcg_reg = 0x36040, 2671*184fdd87SKonrad Dybcio .hwcg_bit = 1, 2672*184fdd87SKonrad Dybcio .clkr = { 2673*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2674*184fdd87SKonrad Dybcio .enable_mask = BIT(4), 2675*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2676*184fdd87SKonrad Dybcio .name = "gcc_qmip_gpu_cfg_ahb_clk", 2677*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2678*184fdd87SKonrad Dybcio }, 2679*184fdd87SKonrad Dybcio }, 2680*184fdd87SKonrad Dybcio }; 2681*184fdd87SKonrad Dybcio 2682*184fdd87SKonrad Dybcio static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2683*184fdd87SKonrad Dybcio .halt_reg = 0x17010, 2684*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2685*184fdd87SKonrad Dybcio .hwcg_reg = 0x17010, 2686*184fdd87SKonrad Dybcio .hwcg_bit = 1, 2687*184fdd87SKonrad Dybcio .clkr = { 2688*184fdd87SKonrad Dybcio .enable_reg = 0x79004, 2689*184fdd87SKonrad Dybcio .enable_mask = BIT(25), 2690*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2691*184fdd87SKonrad Dybcio .name = "gcc_qmip_video_vcodec_ahb_clk", 2692*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2693*184fdd87SKonrad Dybcio }, 2694*184fdd87SKonrad Dybcio }, 2695*184fdd87SKonrad Dybcio }; 2696*184fdd87SKonrad Dybcio 2697*184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2698*184fdd87SKonrad Dybcio .halt_reg = 0x1f014, 2699*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2700*184fdd87SKonrad Dybcio .clkr = { 2701*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2702*184fdd87SKonrad Dybcio .enable_mask = BIT(9), 2703*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2704*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_core_2x_clk", 2705*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2706*184fdd87SKonrad Dybcio }, 2707*184fdd87SKonrad Dybcio }, 2708*184fdd87SKonrad Dybcio }; 2709*184fdd87SKonrad Dybcio 2710*184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2711*184fdd87SKonrad Dybcio .halt_reg = 0x1f00c, 2712*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2713*184fdd87SKonrad Dybcio .clkr = { 2714*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2715*184fdd87SKonrad Dybcio .enable_mask = BIT(8), 2716*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2717*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_core_clk", 2718*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2719*184fdd87SKonrad Dybcio }, 2720*184fdd87SKonrad Dybcio }, 2721*184fdd87SKonrad Dybcio }; 2722*184fdd87SKonrad Dybcio 2723*184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2724*184fdd87SKonrad Dybcio .halt_reg = 0x1f144, 2725*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2726*184fdd87SKonrad Dybcio .clkr = { 2727*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2728*184fdd87SKonrad Dybcio .enable_mask = BIT(10), 2729*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2730*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s0_clk", 2731*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2732*184fdd87SKonrad Dybcio .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 2733*184fdd87SKonrad Dybcio }, 2734*184fdd87SKonrad Dybcio .num_parents = 1, 2735*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2736*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2737*184fdd87SKonrad Dybcio }, 2738*184fdd87SKonrad Dybcio }, 2739*184fdd87SKonrad Dybcio }; 2740*184fdd87SKonrad Dybcio 2741*184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2742*184fdd87SKonrad Dybcio .halt_reg = 0x1f274, 2743*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2744*184fdd87SKonrad Dybcio .clkr = { 2745*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2746*184fdd87SKonrad Dybcio .enable_mask = BIT(11), 2747*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2748*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s1_clk", 2749*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2750*184fdd87SKonrad Dybcio .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 2751*184fdd87SKonrad Dybcio }, 2752*184fdd87SKonrad Dybcio .num_parents = 1, 2753*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2754*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2755*184fdd87SKonrad Dybcio }, 2756*184fdd87SKonrad Dybcio }, 2757*184fdd87SKonrad Dybcio }; 2758*184fdd87SKonrad Dybcio 2759*184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2760*184fdd87SKonrad Dybcio .halt_reg = 0x1f3a4, 2761*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2762*184fdd87SKonrad Dybcio .clkr = { 2763*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2764*184fdd87SKonrad Dybcio .enable_mask = BIT(12), 2765*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2766*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s2_clk", 2767*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2768*184fdd87SKonrad Dybcio .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2769*184fdd87SKonrad Dybcio }, 2770*184fdd87SKonrad Dybcio .num_parents = 1, 2771*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2772*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2773*184fdd87SKonrad Dybcio }, 2774*184fdd87SKonrad Dybcio }, 2775*184fdd87SKonrad Dybcio }; 2776*184fdd87SKonrad Dybcio 2777*184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2778*184fdd87SKonrad Dybcio .halt_reg = 0x1f4d4, 2779*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2780*184fdd87SKonrad Dybcio .clkr = { 2781*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2782*184fdd87SKonrad Dybcio .enable_mask = BIT(13), 2783*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2784*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s3_clk", 2785*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2786*184fdd87SKonrad Dybcio .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2787*184fdd87SKonrad Dybcio }, 2788*184fdd87SKonrad Dybcio .num_parents = 1, 2789*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2790*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2791*184fdd87SKonrad Dybcio }, 2792*184fdd87SKonrad Dybcio }, 2793*184fdd87SKonrad Dybcio }; 2794*184fdd87SKonrad Dybcio 2795*184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2796*184fdd87SKonrad Dybcio .halt_reg = 0x1f604, 2797*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2798*184fdd87SKonrad Dybcio .clkr = { 2799*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2800*184fdd87SKonrad Dybcio .enable_mask = BIT(14), 2801*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2802*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s4_clk", 2803*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2804*184fdd87SKonrad Dybcio .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2805*184fdd87SKonrad Dybcio }, 2806*184fdd87SKonrad Dybcio .num_parents = 1, 2807*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2808*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2809*184fdd87SKonrad Dybcio }, 2810*184fdd87SKonrad Dybcio }, 2811*184fdd87SKonrad Dybcio }; 2812*184fdd87SKonrad Dybcio 2813*184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2814*184fdd87SKonrad Dybcio .halt_reg = 0x1f734, 2815*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2816*184fdd87SKonrad Dybcio .clkr = { 2817*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2818*184fdd87SKonrad Dybcio .enable_mask = BIT(15), 2819*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2820*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap0_s5_clk", 2821*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2822*184fdd87SKonrad Dybcio .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2823*184fdd87SKonrad Dybcio }, 2824*184fdd87SKonrad Dybcio .num_parents = 1, 2825*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2826*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2827*184fdd87SKonrad Dybcio }, 2828*184fdd87SKonrad Dybcio }, 2829*184fdd87SKonrad Dybcio }; 2830*184fdd87SKonrad Dybcio 2831*184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2832*184fdd87SKonrad Dybcio .halt_reg = 0x53014, 2833*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2834*184fdd87SKonrad Dybcio .clkr = { 2835*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2836*184fdd87SKonrad Dybcio .enable_mask = BIT(20), 2837*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2838*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_core_2x_clk", 2839*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2840*184fdd87SKonrad Dybcio }, 2841*184fdd87SKonrad Dybcio }, 2842*184fdd87SKonrad Dybcio }; 2843*184fdd87SKonrad Dybcio 2844*184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2845*184fdd87SKonrad Dybcio .halt_reg = 0x5300c, 2846*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2847*184fdd87SKonrad Dybcio .clkr = { 2848*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2849*184fdd87SKonrad Dybcio .enable_mask = BIT(19), 2850*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2851*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_core_clk", 2852*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2853*184fdd87SKonrad Dybcio }, 2854*184fdd87SKonrad Dybcio }, 2855*184fdd87SKonrad Dybcio }; 2856*184fdd87SKonrad Dybcio 2857*184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2858*184fdd87SKonrad Dybcio .halt_reg = 0x53018, 2859*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2860*184fdd87SKonrad Dybcio .clkr = { 2861*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2862*184fdd87SKonrad Dybcio .enable_mask = BIT(21), 2863*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2864*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s0_clk", 2865*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2866*184fdd87SKonrad Dybcio .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2867*184fdd87SKonrad Dybcio }, 2868*184fdd87SKonrad Dybcio .num_parents = 1, 2869*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2870*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2871*184fdd87SKonrad Dybcio }, 2872*184fdd87SKonrad Dybcio }, 2873*184fdd87SKonrad Dybcio }; 2874*184fdd87SKonrad Dybcio 2875*184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2876*184fdd87SKonrad Dybcio .halt_reg = 0x53148, 2877*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2878*184fdd87SKonrad Dybcio .clkr = { 2879*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2880*184fdd87SKonrad Dybcio .enable_mask = BIT(22), 2881*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2882*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s1_clk", 2883*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2884*184fdd87SKonrad Dybcio .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2885*184fdd87SKonrad Dybcio }, 2886*184fdd87SKonrad Dybcio .num_parents = 1, 2887*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2888*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2889*184fdd87SKonrad Dybcio }, 2890*184fdd87SKonrad Dybcio }, 2891*184fdd87SKonrad Dybcio }; 2892*184fdd87SKonrad Dybcio 2893*184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2894*184fdd87SKonrad Dybcio .halt_reg = 0x53278, 2895*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2896*184fdd87SKonrad Dybcio .clkr = { 2897*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2898*184fdd87SKonrad Dybcio .enable_mask = BIT(23), 2899*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2900*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s2_clk", 2901*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2902*184fdd87SKonrad Dybcio .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2903*184fdd87SKonrad Dybcio }, 2904*184fdd87SKonrad Dybcio .num_parents = 1, 2905*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2906*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2907*184fdd87SKonrad Dybcio }, 2908*184fdd87SKonrad Dybcio }, 2909*184fdd87SKonrad Dybcio }; 2910*184fdd87SKonrad Dybcio 2911*184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2912*184fdd87SKonrad Dybcio .halt_reg = 0x533a8, 2913*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2914*184fdd87SKonrad Dybcio .clkr = { 2915*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2916*184fdd87SKonrad Dybcio .enable_mask = BIT(24), 2917*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2918*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s3_clk", 2919*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2920*184fdd87SKonrad Dybcio .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2921*184fdd87SKonrad Dybcio }, 2922*184fdd87SKonrad Dybcio .num_parents = 1, 2923*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2924*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2925*184fdd87SKonrad Dybcio }, 2926*184fdd87SKonrad Dybcio }, 2927*184fdd87SKonrad Dybcio }; 2928*184fdd87SKonrad Dybcio 2929*184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2930*184fdd87SKonrad Dybcio .halt_reg = 0x534d8, 2931*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2932*184fdd87SKonrad Dybcio .clkr = { 2933*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2934*184fdd87SKonrad Dybcio .enable_mask = BIT(25), 2935*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2936*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s4_clk", 2937*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2938*184fdd87SKonrad Dybcio .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2939*184fdd87SKonrad Dybcio }, 2940*184fdd87SKonrad Dybcio .num_parents = 1, 2941*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2942*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2943*184fdd87SKonrad Dybcio }, 2944*184fdd87SKonrad Dybcio }, 2945*184fdd87SKonrad Dybcio }; 2946*184fdd87SKonrad Dybcio 2947*184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2948*184fdd87SKonrad Dybcio .halt_reg = 0x53608, 2949*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2950*184fdd87SKonrad Dybcio .clkr = { 2951*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2952*184fdd87SKonrad Dybcio .enable_mask = BIT(26), 2953*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2954*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap1_s5_clk", 2955*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 2956*184fdd87SKonrad Dybcio .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2957*184fdd87SKonrad Dybcio }, 2958*184fdd87SKonrad Dybcio .num_parents = 1, 2959*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 2960*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2961*184fdd87SKonrad Dybcio }, 2962*184fdd87SKonrad Dybcio }, 2963*184fdd87SKonrad Dybcio }; 2964*184fdd87SKonrad Dybcio 2965*184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2966*184fdd87SKonrad Dybcio .halt_reg = 0x1f004, 2967*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2968*184fdd87SKonrad Dybcio .hwcg_reg = 0x1f004, 2969*184fdd87SKonrad Dybcio .hwcg_bit = 1, 2970*184fdd87SKonrad Dybcio .clkr = { 2971*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2972*184fdd87SKonrad Dybcio .enable_mask = BIT(6), 2973*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2974*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2975*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2976*184fdd87SKonrad Dybcio }, 2977*184fdd87SKonrad Dybcio }, 2978*184fdd87SKonrad Dybcio }; 2979*184fdd87SKonrad Dybcio 2980*184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2981*184fdd87SKonrad Dybcio .halt_reg = 0x1f008, 2982*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2983*184fdd87SKonrad Dybcio .hwcg_reg = 0x1f008, 2984*184fdd87SKonrad Dybcio .hwcg_bit = 1, 2985*184fdd87SKonrad Dybcio .clkr = { 2986*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 2987*184fdd87SKonrad Dybcio .enable_mask = BIT(7), 2988*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 2989*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2990*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 2991*184fdd87SKonrad Dybcio }, 2992*184fdd87SKonrad Dybcio }, 2993*184fdd87SKonrad Dybcio }; 2994*184fdd87SKonrad Dybcio 2995*184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2996*184fdd87SKonrad Dybcio .halt_reg = 0x53004, 2997*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 2998*184fdd87SKonrad Dybcio .hwcg_reg = 0x53004, 2999*184fdd87SKonrad Dybcio .hwcg_bit = 1, 3000*184fdd87SKonrad Dybcio .clkr = { 3001*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 3002*184fdd87SKonrad Dybcio .enable_mask = BIT(17), 3003*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3004*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap_1_m_ahb_clk", 3005*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3006*184fdd87SKonrad Dybcio }, 3007*184fdd87SKonrad Dybcio }, 3008*184fdd87SKonrad Dybcio }; 3009*184fdd87SKonrad Dybcio 3010*184fdd87SKonrad Dybcio static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 3011*184fdd87SKonrad Dybcio .halt_reg = 0x53008, 3012*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3013*184fdd87SKonrad Dybcio .hwcg_reg = 0x53008, 3014*184fdd87SKonrad Dybcio .hwcg_bit = 1, 3015*184fdd87SKonrad Dybcio .clkr = { 3016*184fdd87SKonrad Dybcio .enable_reg = 0x7900c, 3017*184fdd87SKonrad Dybcio .enable_mask = BIT(18), 3018*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3019*184fdd87SKonrad Dybcio .name = "gcc_qupv3_wrap_1_s_ahb_clk", 3020*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3021*184fdd87SKonrad Dybcio }, 3022*184fdd87SKonrad Dybcio }, 3023*184fdd87SKonrad Dybcio }; 3024*184fdd87SKonrad Dybcio 3025*184fdd87SKonrad Dybcio static struct clk_branch gcc_sdcc1_ahb_clk = { 3026*184fdd87SKonrad Dybcio .halt_reg = 0x38008, 3027*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3028*184fdd87SKonrad Dybcio .clkr = { 3029*184fdd87SKonrad Dybcio .enable_reg = 0x38008, 3030*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3031*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3032*184fdd87SKonrad Dybcio .name = "gcc_sdcc1_ahb_clk", 3033*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3034*184fdd87SKonrad Dybcio }, 3035*184fdd87SKonrad Dybcio }, 3036*184fdd87SKonrad Dybcio }; 3037*184fdd87SKonrad Dybcio 3038*184fdd87SKonrad Dybcio static struct clk_branch gcc_sdcc1_apps_clk = { 3039*184fdd87SKonrad Dybcio .halt_reg = 0x38004, 3040*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3041*184fdd87SKonrad Dybcio .clkr = { 3042*184fdd87SKonrad Dybcio .enable_reg = 0x38004, 3043*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3044*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3045*184fdd87SKonrad Dybcio .name = "gcc_sdcc1_apps_clk", 3046*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 3047*184fdd87SKonrad Dybcio .hw = &gcc_sdcc1_apps_clk_src.clkr.hw, 3048*184fdd87SKonrad Dybcio }, 3049*184fdd87SKonrad Dybcio .num_parents = 1, 3050*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3051*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3052*184fdd87SKonrad Dybcio }, 3053*184fdd87SKonrad Dybcio }, 3054*184fdd87SKonrad Dybcio }; 3055*184fdd87SKonrad Dybcio 3056*184fdd87SKonrad Dybcio static struct clk_branch gcc_sdcc1_ice_core_clk = { 3057*184fdd87SKonrad Dybcio .halt_reg = 0x3800c, 3058*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3059*184fdd87SKonrad Dybcio .hwcg_reg = 0x3800c, 3060*184fdd87SKonrad Dybcio .hwcg_bit = 1, 3061*184fdd87SKonrad Dybcio .clkr = { 3062*184fdd87SKonrad Dybcio .enable_reg = 0x3800c, 3063*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3064*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3065*184fdd87SKonrad Dybcio .name = "gcc_sdcc1_ice_core_clk", 3066*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 3067*184fdd87SKonrad Dybcio .hw = &gcc_sdcc1_ice_core_clk_src.clkr.hw, 3068*184fdd87SKonrad Dybcio }, 3069*184fdd87SKonrad Dybcio .num_parents = 1, 3070*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3071*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3072*184fdd87SKonrad Dybcio }, 3073*184fdd87SKonrad Dybcio }, 3074*184fdd87SKonrad Dybcio }; 3075*184fdd87SKonrad Dybcio 3076*184fdd87SKonrad Dybcio static struct clk_branch gcc_sdcc2_ahb_clk = { 3077*184fdd87SKonrad Dybcio .halt_reg = 0x1e008, 3078*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3079*184fdd87SKonrad Dybcio .clkr = { 3080*184fdd87SKonrad Dybcio .enable_reg = 0x1e008, 3081*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3082*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3083*184fdd87SKonrad Dybcio .name = "gcc_sdcc2_ahb_clk", 3084*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3085*184fdd87SKonrad Dybcio }, 3086*184fdd87SKonrad Dybcio }, 3087*184fdd87SKonrad Dybcio }; 3088*184fdd87SKonrad Dybcio 3089*184fdd87SKonrad Dybcio static struct clk_branch gcc_sdcc2_apps_clk = { 3090*184fdd87SKonrad Dybcio .halt_reg = 0x1e004, 3091*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3092*184fdd87SKonrad Dybcio .clkr = { 3093*184fdd87SKonrad Dybcio .enable_reg = 0x1e004, 3094*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3095*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3096*184fdd87SKonrad Dybcio .name = "gcc_sdcc2_apps_clk", 3097*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 3098*184fdd87SKonrad Dybcio .hw = &gcc_sdcc2_apps_clk_src.clkr.hw, 3099*184fdd87SKonrad Dybcio }, 3100*184fdd87SKonrad Dybcio .num_parents = 1, 3101*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3102*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3103*184fdd87SKonrad Dybcio }, 3104*184fdd87SKonrad Dybcio }, 3105*184fdd87SKonrad Dybcio }; 3106*184fdd87SKonrad Dybcio 3107*184fdd87SKonrad Dybcio static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 3108*184fdd87SKonrad Dybcio .halt_reg = 0x2b06c, 3109*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3110*184fdd87SKonrad Dybcio .hwcg_reg = 0x2b06c, 3111*184fdd87SKonrad Dybcio .hwcg_bit = 1, 3112*184fdd87SKonrad Dybcio .clkr = { 3113*184fdd87SKonrad Dybcio .enable_reg = 0x79004, 3114*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3115*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3116*184fdd87SKonrad Dybcio .name = "gcc_sys_noc_cpuss_ahb_clk", 3117*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 3118*184fdd87SKonrad Dybcio .hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, 3119*184fdd87SKonrad Dybcio }, 3120*184fdd87SKonrad Dybcio .num_parents = 1, 3121*184fdd87SKonrad Dybcio .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 3122*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3123*184fdd87SKonrad Dybcio }, 3124*184fdd87SKonrad Dybcio }, 3125*184fdd87SKonrad Dybcio }; 3126*184fdd87SKonrad Dybcio 3127*184fdd87SKonrad Dybcio static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { 3128*184fdd87SKonrad Dybcio .halt_reg = 0x45098, 3129*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3130*184fdd87SKonrad Dybcio .clkr = { 3131*184fdd87SKonrad Dybcio .enable_reg = 0x45098, 3132*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3133*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3134*184fdd87SKonrad Dybcio .name = "gcc_sys_noc_ufs_phy_axi_clk", 3135*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 3136*184fdd87SKonrad Dybcio .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 3137*184fdd87SKonrad Dybcio }, 3138*184fdd87SKonrad Dybcio .num_parents = 1, 3139*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3140*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3141*184fdd87SKonrad Dybcio }, 3142*184fdd87SKonrad Dybcio }, 3143*184fdd87SKonrad Dybcio }; 3144*184fdd87SKonrad Dybcio 3145*184fdd87SKonrad Dybcio static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { 3146*184fdd87SKonrad Dybcio .halt_reg = 0x1a080, 3147*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3148*184fdd87SKonrad Dybcio .hwcg_reg = 0x1a080, 3149*184fdd87SKonrad Dybcio .hwcg_bit = 1, 3150*184fdd87SKonrad Dybcio .clkr = { 3151*184fdd87SKonrad Dybcio .enable_reg = 0x1a080, 3152*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3153*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3154*184fdd87SKonrad Dybcio .name = "gcc_sys_noc_usb3_prim_axi_clk", 3155*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 3156*184fdd87SKonrad Dybcio .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 3157*184fdd87SKonrad Dybcio }, 3158*184fdd87SKonrad Dybcio .num_parents = 1, 3159*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3160*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3161*184fdd87SKonrad Dybcio }, 3162*184fdd87SKonrad Dybcio }, 3163*184fdd87SKonrad Dybcio }; 3164*184fdd87SKonrad Dybcio 3165*184fdd87SKonrad Dybcio static struct clk_branch gcc_ufs_phy_ahb_clk = { 3166*184fdd87SKonrad Dybcio .halt_reg = 0x45014, 3167*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3168*184fdd87SKonrad Dybcio .hwcg_reg = 0x45014, 3169*184fdd87SKonrad Dybcio .hwcg_bit = 1, 3170*184fdd87SKonrad Dybcio .clkr = { 3171*184fdd87SKonrad Dybcio .enable_reg = 0x45014, 3172*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3173*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3174*184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_ahb_clk", 3175*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3176*184fdd87SKonrad Dybcio }, 3177*184fdd87SKonrad Dybcio }, 3178*184fdd87SKonrad Dybcio }; 3179*184fdd87SKonrad Dybcio 3180*184fdd87SKonrad Dybcio static struct clk_branch gcc_ufs_phy_axi_clk = { 3181*184fdd87SKonrad Dybcio .halt_reg = 0x45010, 3182*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3183*184fdd87SKonrad Dybcio .hwcg_reg = 0x45010, 3184*184fdd87SKonrad Dybcio .hwcg_bit = 1, 3185*184fdd87SKonrad Dybcio .clkr = { 3186*184fdd87SKonrad Dybcio .enable_reg = 0x45010, 3187*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3188*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3189*184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_axi_clk", 3190*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 3191*184fdd87SKonrad Dybcio .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 3192*184fdd87SKonrad Dybcio }, 3193*184fdd87SKonrad Dybcio .num_parents = 1, 3194*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3195*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3196*184fdd87SKonrad Dybcio }, 3197*184fdd87SKonrad Dybcio }, 3198*184fdd87SKonrad Dybcio }; 3199*184fdd87SKonrad Dybcio 3200*184fdd87SKonrad Dybcio static struct clk_branch gcc_ufs_phy_ice_core_clk = { 3201*184fdd87SKonrad Dybcio .halt_reg = 0x45044, 3202*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3203*184fdd87SKonrad Dybcio .hwcg_reg = 0x45044, 3204*184fdd87SKonrad Dybcio .hwcg_bit = 1, 3205*184fdd87SKonrad Dybcio .clkr = { 3206*184fdd87SKonrad Dybcio .enable_reg = 0x45044, 3207*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3208*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3209*184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_ice_core_clk", 3210*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 3211*184fdd87SKonrad Dybcio .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 3212*184fdd87SKonrad Dybcio }, 3213*184fdd87SKonrad Dybcio .num_parents = 1, 3214*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3215*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3216*184fdd87SKonrad Dybcio }, 3217*184fdd87SKonrad Dybcio }, 3218*184fdd87SKonrad Dybcio }; 3219*184fdd87SKonrad Dybcio 3220*184fdd87SKonrad Dybcio static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 3221*184fdd87SKonrad Dybcio .halt_reg = 0x45078, 3222*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3223*184fdd87SKonrad Dybcio .hwcg_reg = 0x45078, 3224*184fdd87SKonrad Dybcio .hwcg_bit = 1, 3225*184fdd87SKonrad Dybcio .clkr = { 3226*184fdd87SKonrad Dybcio .enable_reg = 0x45078, 3227*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3228*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3229*184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_phy_aux_clk", 3230*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 3231*184fdd87SKonrad Dybcio .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 3232*184fdd87SKonrad Dybcio }, 3233*184fdd87SKonrad Dybcio .num_parents = 1, 3234*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3235*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3236*184fdd87SKonrad Dybcio }, 3237*184fdd87SKonrad Dybcio }, 3238*184fdd87SKonrad Dybcio }; 3239*184fdd87SKonrad Dybcio 3240*184fdd87SKonrad Dybcio static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 3241*184fdd87SKonrad Dybcio .halt_reg = 0x4501c, 3242*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_SKIP, 3243*184fdd87SKonrad Dybcio .clkr = { 3244*184fdd87SKonrad Dybcio .enable_reg = 0x4501c, 3245*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3246*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3247*184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_rx_symbol_0_clk", 3248*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3249*184fdd87SKonrad Dybcio }, 3250*184fdd87SKonrad Dybcio }, 3251*184fdd87SKonrad Dybcio }; 3252*184fdd87SKonrad Dybcio 3253*184fdd87SKonrad Dybcio static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 3254*184fdd87SKonrad Dybcio .halt_reg = 0x45018, 3255*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_SKIP, 3256*184fdd87SKonrad Dybcio .clkr = { 3257*184fdd87SKonrad Dybcio .enable_reg = 0x45018, 3258*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3259*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3260*184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_tx_symbol_0_clk", 3261*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3262*184fdd87SKonrad Dybcio }, 3263*184fdd87SKonrad Dybcio }, 3264*184fdd87SKonrad Dybcio }; 3265*184fdd87SKonrad Dybcio 3266*184fdd87SKonrad Dybcio static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 3267*184fdd87SKonrad Dybcio .halt_reg = 0x45040, 3268*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3269*184fdd87SKonrad Dybcio .hwcg_reg = 0x45040, 3270*184fdd87SKonrad Dybcio .hwcg_bit = 1, 3271*184fdd87SKonrad Dybcio .clkr = { 3272*184fdd87SKonrad Dybcio .enable_reg = 0x45040, 3273*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3274*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3275*184fdd87SKonrad Dybcio .name = "gcc_ufs_phy_unipro_core_clk", 3276*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 3277*184fdd87SKonrad Dybcio .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 3278*184fdd87SKonrad Dybcio }, 3279*184fdd87SKonrad Dybcio .num_parents = 1, 3280*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3281*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3282*184fdd87SKonrad Dybcio }, 3283*184fdd87SKonrad Dybcio }, 3284*184fdd87SKonrad Dybcio }; 3285*184fdd87SKonrad Dybcio 3286*184fdd87SKonrad Dybcio static struct clk_branch gcc_usb30_prim_master_clk = { 3287*184fdd87SKonrad Dybcio .halt_reg = 0x1a010, 3288*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3289*184fdd87SKonrad Dybcio .clkr = { 3290*184fdd87SKonrad Dybcio .enable_reg = 0x1a010, 3291*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3292*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3293*184fdd87SKonrad Dybcio .name = "gcc_usb30_prim_master_clk", 3294*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 3295*184fdd87SKonrad Dybcio .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 3296*184fdd87SKonrad Dybcio }, 3297*184fdd87SKonrad Dybcio .num_parents = 1, 3298*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3299*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3300*184fdd87SKonrad Dybcio }, 3301*184fdd87SKonrad Dybcio }, 3302*184fdd87SKonrad Dybcio }; 3303*184fdd87SKonrad Dybcio 3304*184fdd87SKonrad Dybcio static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 3305*184fdd87SKonrad Dybcio .halt_reg = 0x1a018, 3306*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3307*184fdd87SKonrad Dybcio .clkr = { 3308*184fdd87SKonrad Dybcio .enable_reg = 0x1a018, 3309*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3310*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3311*184fdd87SKonrad Dybcio .name = "gcc_usb30_prim_mock_utmi_clk", 3312*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 3313*184fdd87SKonrad Dybcio .hw = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 3314*184fdd87SKonrad Dybcio }, 3315*184fdd87SKonrad Dybcio .num_parents = 1, 3316*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3317*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3318*184fdd87SKonrad Dybcio }, 3319*184fdd87SKonrad Dybcio }, 3320*184fdd87SKonrad Dybcio }; 3321*184fdd87SKonrad Dybcio 3322*184fdd87SKonrad Dybcio static struct clk_branch gcc_usb30_prim_sleep_clk = { 3323*184fdd87SKonrad Dybcio .halt_reg = 0x1a014, 3324*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3325*184fdd87SKonrad Dybcio .clkr = { 3326*184fdd87SKonrad Dybcio .enable_reg = 0x1a014, 3327*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3328*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3329*184fdd87SKonrad Dybcio .name = "gcc_usb30_prim_sleep_clk", 3330*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3331*184fdd87SKonrad Dybcio }, 3332*184fdd87SKonrad Dybcio }, 3333*184fdd87SKonrad Dybcio }; 3334*184fdd87SKonrad Dybcio 3335*184fdd87SKonrad Dybcio static struct clk_branch gcc_ufs_mem_clkref_clk = { 3336*184fdd87SKonrad Dybcio .halt_reg = 0x8c000, 3337*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3338*184fdd87SKonrad Dybcio .clkr = { 3339*184fdd87SKonrad Dybcio .enable_reg = 0x8c000, 3340*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3341*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3342*184fdd87SKonrad Dybcio .name = "gcc_ufs_mem_clkref_clk", 3343*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3344*184fdd87SKonrad Dybcio }, 3345*184fdd87SKonrad Dybcio }, 3346*184fdd87SKonrad Dybcio }; 3347*184fdd87SKonrad Dybcio 3348*184fdd87SKonrad Dybcio static struct clk_branch gcc_rx5_pcie_clkref_en_clk = { 3349*184fdd87SKonrad Dybcio .halt_reg = 0x8c00c, 3350*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3351*184fdd87SKonrad Dybcio .clkr = { 3352*184fdd87SKonrad Dybcio .enable_reg = 0x8c00c, 3353*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3354*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3355*184fdd87SKonrad Dybcio .name = "gcc_rx5_pcie_clkref_en_clk", 3356*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3357*184fdd87SKonrad Dybcio }, 3358*184fdd87SKonrad Dybcio }, 3359*184fdd87SKonrad Dybcio }; 3360*184fdd87SKonrad Dybcio 3361*184fdd87SKonrad Dybcio static struct clk_branch gcc_usb3_prim_clkref_clk = { 3362*184fdd87SKonrad Dybcio .halt_reg = 0x8c010, 3363*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3364*184fdd87SKonrad Dybcio .clkr = { 3365*184fdd87SKonrad Dybcio .enable_reg = 0x8c010, 3366*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3367*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3368*184fdd87SKonrad Dybcio .name = "gcc_usb3_prim_clkref_clk", 3369*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3370*184fdd87SKonrad Dybcio }, 3371*184fdd87SKonrad Dybcio }, 3372*184fdd87SKonrad Dybcio }; 3373*184fdd87SKonrad Dybcio 3374*184fdd87SKonrad Dybcio static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3375*184fdd87SKonrad Dybcio .halt_reg = 0x1a054, 3376*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3377*184fdd87SKonrad Dybcio .clkr = { 3378*184fdd87SKonrad Dybcio .enable_reg = 0x1a054, 3379*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3380*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3381*184fdd87SKonrad Dybcio .name = "gcc_usb3_prim_phy_com_aux_clk", 3382*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 3383*184fdd87SKonrad Dybcio .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3384*184fdd87SKonrad Dybcio }, 3385*184fdd87SKonrad Dybcio .num_parents = 1, 3386*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3387*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3388*184fdd87SKonrad Dybcio }, 3389*184fdd87SKonrad Dybcio }, 3390*184fdd87SKonrad Dybcio }; 3391*184fdd87SKonrad Dybcio 3392*184fdd87SKonrad Dybcio static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3393*184fdd87SKonrad Dybcio .halt_reg = 0x1a058, 3394*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_SKIP, 3395*184fdd87SKonrad Dybcio .hwcg_reg = 0x1a058, 3396*184fdd87SKonrad Dybcio .hwcg_bit = 1, 3397*184fdd87SKonrad Dybcio .clkr = { 3398*184fdd87SKonrad Dybcio .enable_reg = 0x1a058, 3399*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3400*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3401*184fdd87SKonrad Dybcio .name = "gcc_usb3_prim_phy_pipe_clk", 3402*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3403*184fdd87SKonrad Dybcio }, 3404*184fdd87SKonrad Dybcio }, 3405*184fdd87SKonrad Dybcio }; 3406*184fdd87SKonrad Dybcio 3407*184fdd87SKonrad Dybcio static struct clk_branch gcc_vcodec0_axi_clk = { 3408*184fdd87SKonrad Dybcio .halt_reg = 0x6e008, 3409*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3410*184fdd87SKonrad Dybcio .clkr = { 3411*184fdd87SKonrad Dybcio .enable_reg = 0x6e008, 3412*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3413*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3414*184fdd87SKonrad Dybcio .name = "gcc_vcodec0_axi_clk", 3415*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3416*184fdd87SKonrad Dybcio }, 3417*184fdd87SKonrad Dybcio }, 3418*184fdd87SKonrad Dybcio }; 3419*184fdd87SKonrad Dybcio 3420*184fdd87SKonrad Dybcio static struct clk_branch gcc_venus_ahb_clk = { 3421*184fdd87SKonrad Dybcio .halt_reg = 0x6e010, 3422*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3423*184fdd87SKonrad Dybcio .clkr = { 3424*184fdd87SKonrad Dybcio .enable_reg = 0x6e010, 3425*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3426*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3427*184fdd87SKonrad Dybcio .name = "gcc_venus_ahb_clk", 3428*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3429*184fdd87SKonrad Dybcio }, 3430*184fdd87SKonrad Dybcio }, 3431*184fdd87SKonrad Dybcio }; 3432*184fdd87SKonrad Dybcio 3433*184fdd87SKonrad Dybcio static struct clk_branch gcc_venus_ctl_axi_clk = { 3434*184fdd87SKonrad Dybcio .halt_reg = 0x6e004, 3435*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3436*184fdd87SKonrad Dybcio .clkr = { 3437*184fdd87SKonrad Dybcio .enable_reg = 0x6e004, 3438*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3439*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3440*184fdd87SKonrad Dybcio .name = "gcc_venus_ctl_axi_clk", 3441*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3442*184fdd87SKonrad Dybcio }, 3443*184fdd87SKonrad Dybcio }, 3444*184fdd87SKonrad Dybcio }; 3445*184fdd87SKonrad Dybcio 3446*184fdd87SKonrad Dybcio static struct clk_branch gcc_video_ahb_clk = { 3447*184fdd87SKonrad Dybcio .halt_reg = 0x17004, 3448*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_DELAY, 3449*184fdd87SKonrad Dybcio .hwcg_reg = 0x17004, 3450*184fdd87SKonrad Dybcio .hwcg_bit = 1, 3451*184fdd87SKonrad Dybcio .clkr = { 3452*184fdd87SKonrad Dybcio .enable_reg = 0x17004, 3453*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3454*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3455*184fdd87SKonrad Dybcio .name = "gcc_video_ahb_clk", 3456*184fdd87SKonrad Dybcio .flags = CLK_IS_CRITICAL, 3457*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3458*184fdd87SKonrad Dybcio }, 3459*184fdd87SKonrad Dybcio }, 3460*184fdd87SKonrad Dybcio }; 3461*184fdd87SKonrad Dybcio 3462*184fdd87SKonrad Dybcio static struct clk_branch gcc_video_axi0_clk = { 3463*184fdd87SKonrad Dybcio .halt_reg = 0x1701c, 3464*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3465*184fdd87SKonrad Dybcio .hwcg_reg = 0x1701c, 3466*184fdd87SKonrad Dybcio .hwcg_bit = 1, 3467*184fdd87SKonrad Dybcio .clkr = { 3468*184fdd87SKonrad Dybcio .enable_reg = 0x1701c, 3469*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3470*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3471*184fdd87SKonrad Dybcio .name = "gcc_video_axi0_clk", 3472*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3473*184fdd87SKonrad Dybcio }, 3474*184fdd87SKonrad Dybcio }, 3475*184fdd87SKonrad Dybcio }; 3476*184fdd87SKonrad Dybcio 3477*184fdd87SKonrad Dybcio static struct clk_branch gcc_video_throttle_core_clk = { 3478*184fdd87SKonrad Dybcio .halt_reg = 0x17068, 3479*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3480*184fdd87SKonrad Dybcio .hwcg_reg = 0x17068, 3481*184fdd87SKonrad Dybcio .hwcg_bit = 1, 3482*184fdd87SKonrad Dybcio .clkr = { 3483*184fdd87SKonrad Dybcio .enable_reg = 0x79004, 3484*184fdd87SKonrad Dybcio .enable_mask = BIT(28), 3485*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3486*184fdd87SKonrad Dybcio .name = "gcc_video_throttle_core_clk", 3487*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3488*184fdd87SKonrad Dybcio }, 3489*184fdd87SKonrad Dybcio }, 3490*184fdd87SKonrad Dybcio }; 3491*184fdd87SKonrad Dybcio 3492*184fdd87SKonrad Dybcio static struct clk_branch gcc_video_vcodec0_sys_clk = { 3493*184fdd87SKonrad Dybcio .halt_reg = 0x580a4, 3494*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT_VOTED, 3495*184fdd87SKonrad Dybcio .hwcg_reg = 0x580a4, 3496*184fdd87SKonrad Dybcio .hwcg_bit = 1, 3497*184fdd87SKonrad Dybcio .clkr = { 3498*184fdd87SKonrad Dybcio .enable_reg = 0x580a4, 3499*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3500*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3501*184fdd87SKonrad Dybcio .name = "gcc_video_vcodec0_sys_clk", 3502*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 3503*184fdd87SKonrad Dybcio .hw = &gcc_video_venus_clk_src.clkr.hw, 3504*184fdd87SKonrad Dybcio }, 3505*184fdd87SKonrad Dybcio .num_parents = 1, 3506*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3507*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3508*184fdd87SKonrad Dybcio }, 3509*184fdd87SKonrad Dybcio }, 3510*184fdd87SKonrad Dybcio }; 3511*184fdd87SKonrad Dybcio 3512*184fdd87SKonrad Dybcio static struct clk_branch gcc_video_venus_ctl_clk = { 3513*184fdd87SKonrad Dybcio .halt_reg = 0x5808c, 3514*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3515*184fdd87SKonrad Dybcio .clkr = { 3516*184fdd87SKonrad Dybcio .enable_reg = 0x5808c, 3517*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3518*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3519*184fdd87SKonrad Dybcio .name = "gcc_video_venus_ctl_clk", 3520*184fdd87SKonrad Dybcio .parent_data = &(const struct clk_parent_data){ 3521*184fdd87SKonrad Dybcio .hw = &gcc_video_venus_clk_src.clkr.hw, 3522*184fdd87SKonrad Dybcio }, 3523*184fdd87SKonrad Dybcio .num_parents = 1, 3524*184fdd87SKonrad Dybcio .flags = CLK_SET_RATE_PARENT, 3525*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3526*184fdd87SKonrad Dybcio }, 3527*184fdd87SKonrad Dybcio }, 3528*184fdd87SKonrad Dybcio }; 3529*184fdd87SKonrad Dybcio 3530*184fdd87SKonrad Dybcio static struct clk_branch gcc_video_xo_clk = { 3531*184fdd87SKonrad Dybcio .halt_reg = 0x17024, 3532*184fdd87SKonrad Dybcio .halt_check = BRANCH_HALT, 3533*184fdd87SKonrad Dybcio .clkr = { 3534*184fdd87SKonrad Dybcio .enable_reg = 0x17024, 3535*184fdd87SKonrad Dybcio .enable_mask = BIT(0), 3536*184fdd87SKonrad Dybcio .hw.init = &(struct clk_init_data){ 3537*184fdd87SKonrad Dybcio .name = "gcc_video_xo_clk", 3538*184fdd87SKonrad Dybcio .ops = &clk_branch2_ops, 3539*184fdd87SKonrad Dybcio }, 3540*184fdd87SKonrad Dybcio }, 3541*184fdd87SKonrad Dybcio }; 3542*184fdd87SKonrad Dybcio 3543*184fdd87SKonrad Dybcio static struct gdsc usb30_prim_gdsc = { 3544*184fdd87SKonrad Dybcio .gdscr = 0x1a004, 3545*184fdd87SKonrad Dybcio .pd = { 3546*184fdd87SKonrad Dybcio .name = "usb30_prim_gdsc", 3547*184fdd87SKonrad Dybcio }, 3548*184fdd87SKonrad Dybcio .pwrsts = PWRSTS_OFF_ON, 3549*184fdd87SKonrad Dybcio }; 3550*184fdd87SKonrad Dybcio 3551*184fdd87SKonrad Dybcio static struct gdsc ufs_phy_gdsc = { 3552*184fdd87SKonrad Dybcio .gdscr = 0x45004, 3553*184fdd87SKonrad Dybcio .pd = { 3554*184fdd87SKonrad Dybcio .name = "ufs_phy_gdsc", 3555*184fdd87SKonrad Dybcio }, 3556*184fdd87SKonrad Dybcio .pwrsts = PWRSTS_OFF_ON, 3557*184fdd87SKonrad Dybcio }; 3558*184fdd87SKonrad Dybcio 3559*184fdd87SKonrad Dybcio static struct gdsc camss_top_gdsc = { 3560*184fdd87SKonrad Dybcio .gdscr = 0x58004, 3561*184fdd87SKonrad Dybcio .pd = { 3562*184fdd87SKonrad Dybcio .name = "camss_top_gdsc", 3563*184fdd87SKonrad Dybcio }, 3564*184fdd87SKonrad Dybcio .pwrsts = PWRSTS_OFF_ON, 3565*184fdd87SKonrad Dybcio }; 3566*184fdd87SKonrad Dybcio 3567*184fdd87SKonrad Dybcio static struct gdsc venus_gdsc = { 3568*184fdd87SKonrad Dybcio .gdscr = 0x5807c, 3569*184fdd87SKonrad Dybcio .pd = { 3570*184fdd87SKonrad Dybcio .name = "venus_gdsc", 3571*184fdd87SKonrad Dybcio }, 3572*184fdd87SKonrad Dybcio .pwrsts = PWRSTS_OFF_ON, 3573*184fdd87SKonrad Dybcio }; 3574*184fdd87SKonrad Dybcio 3575*184fdd87SKonrad Dybcio static struct gdsc vcodec0_gdsc = { 3576*184fdd87SKonrad Dybcio .gdscr = 0x58098, 3577*184fdd87SKonrad Dybcio .pd = { 3578*184fdd87SKonrad Dybcio .name = "vcodec0_gdsc", 3579*184fdd87SKonrad Dybcio }, 3580*184fdd87SKonrad Dybcio .pwrsts = PWRSTS_OFF_ON, 3581*184fdd87SKonrad Dybcio .flags = HW_CTRL, 3582*184fdd87SKonrad Dybcio }; 3583*184fdd87SKonrad Dybcio 3584*184fdd87SKonrad Dybcio static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = { 3585*184fdd87SKonrad Dybcio .gdscr = 0x7d074, 3586*184fdd87SKonrad Dybcio .pd = { 3587*184fdd87SKonrad Dybcio .name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc", 3588*184fdd87SKonrad Dybcio }, 3589*184fdd87SKonrad Dybcio .pwrsts = PWRSTS_OFF_ON, 3590*184fdd87SKonrad Dybcio .flags = VOTABLE, 3591*184fdd87SKonrad Dybcio }; 3592*184fdd87SKonrad Dybcio 3593*184fdd87SKonrad Dybcio static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = { 3594*184fdd87SKonrad Dybcio .gdscr = 0x7d078, 3595*184fdd87SKonrad Dybcio .pd = { 3596*184fdd87SKonrad Dybcio .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc", 3597*184fdd87SKonrad Dybcio }, 3598*184fdd87SKonrad Dybcio .pwrsts = PWRSTS_OFF_ON, 3599*184fdd87SKonrad Dybcio .flags = VOTABLE, 3600*184fdd87SKonrad Dybcio }; 3601*184fdd87SKonrad Dybcio 3602*184fdd87SKonrad Dybcio static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = { 3603*184fdd87SKonrad Dybcio .gdscr = 0x7d060, 3604*184fdd87SKonrad Dybcio .pd = { 3605*184fdd87SKonrad Dybcio .name = "hlos1_vote_turing_mmu_tbu1_gdsc", 3606*184fdd87SKonrad Dybcio }, 3607*184fdd87SKonrad Dybcio .pwrsts = PWRSTS_OFF_ON, 3608*184fdd87SKonrad Dybcio .flags = VOTABLE, 3609*184fdd87SKonrad Dybcio }; 3610*184fdd87SKonrad Dybcio 3611*184fdd87SKonrad Dybcio static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { 3612*184fdd87SKonrad Dybcio .gdscr = 0x7d07c, 3613*184fdd87SKonrad Dybcio .pd = { 3614*184fdd87SKonrad Dybcio .name = "hlos1_vote_turing_mmu_tbu0_gdsc", 3615*184fdd87SKonrad Dybcio }, 3616*184fdd87SKonrad Dybcio .pwrsts = PWRSTS_OFF_ON, 3617*184fdd87SKonrad Dybcio .flags = VOTABLE, 3618*184fdd87SKonrad Dybcio }; 3619*184fdd87SKonrad Dybcio 3620*184fdd87SKonrad Dybcio static struct clk_regmap *gcc_sm6375_clocks[] = { 3621*184fdd87SKonrad Dybcio [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr, 3622*184fdd87SKonrad Dybcio [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr, 3623*184fdd87SKonrad Dybcio [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr, 3624*184fdd87SKonrad Dybcio [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3625*184fdd87SKonrad Dybcio [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, 3626*184fdd87SKonrad Dybcio [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, 3627*184fdd87SKonrad Dybcio [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 3628*184fdd87SKonrad Dybcio [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, 3629*184fdd87SKonrad Dybcio [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, 3630*184fdd87SKonrad Dybcio [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr, 3631*184fdd87SKonrad Dybcio [GCC_CAMSS_CCI_0_CLK_SRC] = &gcc_camss_cci_0_clk_src.clkr, 3632*184fdd87SKonrad Dybcio [GCC_CAMSS_CCI_1_CLK] = &gcc_camss_cci_1_clk.clkr, 3633*184fdd87SKonrad Dybcio [GCC_CAMSS_CCI_1_CLK_SRC] = &gcc_camss_cci_1_clk_src.clkr, 3634*184fdd87SKonrad Dybcio [GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr, 3635*184fdd87SKonrad Dybcio [GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr, 3636*184fdd87SKonrad Dybcio [GCC_CAMSS_CPHY_2_CLK] = &gcc_camss_cphy_2_clk.clkr, 3637*184fdd87SKonrad Dybcio [GCC_CAMSS_CPHY_3_CLK] = &gcc_camss_cphy_3_clk.clkr, 3638*184fdd87SKonrad Dybcio [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 3639*184fdd87SKonrad Dybcio [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr, 3640*184fdd87SKonrad Dybcio [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, 3641*184fdd87SKonrad Dybcio [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr, 3642*184fdd87SKonrad Dybcio [GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr, 3643*184fdd87SKonrad Dybcio [GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr, 3644*184fdd87SKonrad Dybcio [GCC_CAMSS_CSI3PHYTIMER_CLK] = &gcc_camss_csi3phytimer_clk.clkr, 3645*184fdd87SKonrad Dybcio [GCC_CAMSS_CSI3PHYTIMER_CLK_SRC] = &gcc_camss_csi3phytimer_clk_src.clkr, 3646*184fdd87SKonrad Dybcio [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 3647*184fdd87SKonrad Dybcio [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr, 3648*184fdd87SKonrad Dybcio [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 3649*184fdd87SKonrad Dybcio [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr, 3650*184fdd87SKonrad Dybcio [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, 3651*184fdd87SKonrad Dybcio [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr, 3652*184fdd87SKonrad Dybcio [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr, 3653*184fdd87SKonrad Dybcio [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr, 3654*184fdd87SKonrad Dybcio [GCC_CAMSS_MCLK4_CLK] = &gcc_camss_mclk4_clk.clkr, 3655*184fdd87SKonrad Dybcio [GCC_CAMSS_MCLK4_CLK_SRC] = &gcc_camss_mclk4_clk_src.clkr, 3656*184fdd87SKonrad Dybcio [GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr, 3657*184fdd87SKonrad Dybcio [GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr, 3658*184fdd87SKonrad Dybcio [GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr, 3659*184fdd87SKonrad Dybcio [GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr, 3660*184fdd87SKonrad Dybcio [GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr, 3661*184fdd87SKonrad Dybcio [GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr, 3662*184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr, 3663*184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr, 3664*184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr, 3665*184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr, 3666*184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr, 3667*184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr, 3668*184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr, 3669*184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr, 3670*184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr, 3671*184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr, 3672*184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_2_CLK] = &gcc_camss_tfe_2_clk.clkr, 3673*184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_2_CLK_SRC] = &gcc_camss_tfe_2_clk_src.clkr, 3674*184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_2_CPHY_RX_CLK] = &gcc_camss_tfe_2_cphy_rx_clk.clkr, 3675*184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_2_CSID_CLK] = &gcc_camss_tfe_2_csid_clk.clkr, 3676*184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_2_CSID_CLK_SRC] = &gcc_camss_tfe_2_csid_clk_src.clkr, 3677*184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr, 3678*184fdd87SKonrad Dybcio [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 3679*184fdd87SKonrad Dybcio [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, 3680*184fdd87SKonrad Dybcio [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3681*184fdd87SKonrad Dybcio [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, 3682*184fdd87SKonrad Dybcio [GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr, 3683*184fdd87SKonrad Dybcio [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, 3684*184fdd87SKonrad Dybcio [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 3685*184fdd87SKonrad Dybcio [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 3686*184fdd87SKonrad Dybcio [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3687*184fdd87SKonrad Dybcio [GCC_DISP_SLEEP_CLK] = &gcc_disp_sleep_clk.clkr, 3688*184fdd87SKonrad Dybcio [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, 3689*184fdd87SKonrad Dybcio [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3690*184fdd87SKonrad Dybcio [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3691*184fdd87SKonrad Dybcio [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3692*184fdd87SKonrad Dybcio [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3693*184fdd87SKonrad Dybcio [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3694*184fdd87SKonrad Dybcio [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3695*184fdd87SKonrad Dybcio [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 3696*184fdd87SKonrad Dybcio [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3697*184fdd87SKonrad Dybcio [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3698*184fdd87SKonrad Dybcio [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3699*184fdd87SKonrad Dybcio [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3700*184fdd87SKonrad Dybcio [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, 3701*184fdd87SKonrad Dybcio [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3702*184fdd87SKonrad Dybcio [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3703*184fdd87SKonrad Dybcio [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3704*184fdd87SKonrad Dybcio [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3705*184fdd87SKonrad Dybcio [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3706*184fdd87SKonrad Dybcio [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3707*184fdd87SKonrad Dybcio [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3708*184fdd87SKonrad Dybcio [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3709*184fdd87SKonrad Dybcio [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr, 3710*184fdd87SKonrad Dybcio [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3711*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 3712*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 3713*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3714*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3715*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3716*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3717*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3718*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3719*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3720*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3721*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3722*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3723*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3724*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3725*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3726*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3727*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3728*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3729*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3730*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3731*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3732*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3733*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3734*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3735*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3736*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3737*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3738*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3739*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3740*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3741*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3742*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3743*184fdd87SKonrad Dybcio [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3744*184fdd87SKonrad Dybcio [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3745*184fdd87SKonrad Dybcio [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 3746*184fdd87SKonrad Dybcio [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 3747*184fdd87SKonrad Dybcio [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 3748*184fdd87SKonrad Dybcio [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3749*184fdd87SKonrad Dybcio [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3750*184fdd87SKonrad Dybcio [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3751*184fdd87SKonrad Dybcio [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 3752*184fdd87SKonrad Dybcio [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, 3753*184fdd87SKonrad Dybcio [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, 3754*184fdd87SKonrad Dybcio [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3755*184fdd87SKonrad Dybcio [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3756*184fdd87SKonrad Dybcio [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3757*184fdd87SKonrad Dybcio [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3758*184fdd87SKonrad Dybcio [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3759*184fdd87SKonrad Dybcio [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3760*184fdd87SKonrad Dybcio [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3761*184fdd87SKonrad Dybcio [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3762*184fdd87SKonrad Dybcio [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3763*184fdd87SKonrad Dybcio [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3764*184fdd87SKonrad Dybcio [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 3765*184fdd87SKonrad Dybcio [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3766*184fdd87SKonrad Dybcio [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3767*184fdd87SKonrad Dybcio [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3768*184fdd87SKonrad Dybcio [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3769*184fdd87SKonrad Dybcio [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3770*184fdd87SKonrad Dybcio [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3771*184fdd87SKonrad Dybcio [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 3772*184fdd87SKonrad Dybcio [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3773*184fdd87SKonrad Dybcio [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3774*184fdd87SKonrad Dybcio [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3775*184fdd87SKonrad Dybcio [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr, 3776*184fdd87SKonrad Dybcio [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr, 3777*184fdd87SKonrad Dybcio [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr, 3778*184fdd87SKonrad Dybcio [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 3779*184fdd87SKonrad Dybcio [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3780*184fdd87SKonrad Dybcio [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, 3781*184fdd87SKonrad Dybcio [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr, 3782*184fdd87SKonrad Dybcio [GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr, 3783*184fdd87SKonrad Dybcio [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr, 3784*184fdd87SKonrad Dybcio [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 3785*184fdd87SKonrad Dybcio [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, 3786*184fdd87SKonrad Dybcio [GCC_RX5_PCIE_CLKREF_EN_CLK] = &gcc_rx5_pcie_clkref_en_clk.clkr, 3787*184fdd87SKonrad Dybcio [GPLL0] = &gpll0.clkr, 3788*184fdd87SKonrad Dybcio [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 3789*184fdd87SKonrad Dybcio [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr, 3790*184fdd87SKonrad Dybcio [GPLL1] = &gpll1.clkr, 3791*184fdd87SKonrad Dybcio [GPLL10] = &gpll10.clkr, 3792*184fdd87SKonrad Dybcio [GPLL11] = &gpll11.clkr, 3793*184fdd87SKonrad Dybcio [GPLL3] = &gpll3.clkr, 3794*184fdd87SKonrad Dybcio [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr, 3795*184fdd87SKonrad Dybcio [GPLL4] = &gpll4.clkr, 3796*184fdd87SKonrad Dybcio [GPLL5] = &gpll5.clkr, 3797*184fdd87SKonrad Dybcio [GPLL6] = &gpll6.clkr, 3798*184fdd87SKonrad Dybcio [GPLL6_OUT_EVEN] = &gpll6_out_even.clkr, 3799*184fdd87SKonrad Dybcio [GPLL7] = &gpll7.clkr, 3800*184fdd87SKonrad Dybcio [GPLL8] = &gpll8.clkr, 3801*184fdd87SKonrad Dybcio [GPLL8_OUT_EVEN] = &gpll8_out_even.clkr, 3802*184fdd87SKonrad Dybcio [GPLL9] = &gpll9.clkr, 3803*184fdd87SKonrad Dybcio [GPLL9_OUT_MAIN] = &gpll9_out_main.clkr, 3804*184fdd87SKonrad Dybcio }; 3805*184fdd87SKonrad Dybcio 3806*184fdd87SKonrad Dybcio static const struct qcom_reset_map gcc_sm6375_resets[] = { 3807*184fdd87SKonrad Dybcio [GCC_MMSS_BCR] = { 0x17000 }, 3808*184fdd87SKonrad Dybcio [GCC_USB30_PRIM_BCR] = { 0x1a000 }, 3809*184fdd87SKonrad Dybcio [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, 3810*184fdd87SKonrad Dybcio [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1b020 }, 3811*184fdd87SKonrad Dybcio [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, 3812*184fdd87SKonrad Dybcio [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, 3813*184fdd87SKonrad Dybcio [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, 3814*184fdd87SKonrad Dybcio [GCC_SDCC2_BCR] = { 0x1e000 }, 3815*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 }, 3816*184fdd87SKonrad Dybcio [GCC_PDM_BCR] = { 0x20000 }, 3817*184fdd87SKonrad Dybcio [GCC_GPU_BCR] = { 0x36000 }, 3818*184fdd87SKonrad Dybcio [GCC_SDCC1_BCR] = { 0x38000 }, 3819*184fdd87SKonrad Dybcio [GCC_UFS_PHY_BCR] = { 0x45000 }, 3820*184fdd87SKonrad Dybcio [GCC_CAMSS_TFE_BCR] = { 0x52000 }, 3821*184fdd87SKonrad Dybcio [GCC_QUPV3_WRAPPER_1_BCR] = { 0x53000 }, 3822*184fdd87SKonrad Dybcio [GCC_CAMSS_OPE_BCR] = { 0x55000 }, 3823*184fdd87SKonrad Dybcio [GCC_CAMSS_TOP_BCR] = { 0x58000 }, 3824*184fdd87SKonrad Dybcio [GCC_VENUS_BCR] = { 0x58078 }, 3825*184fdd87SKonrad Dybcio [GCC_VCODEC0_BCR] = { 0x58094 }, 3826*184fdd87SKonrad Dybcio [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 }, 3827*184fdd87SKonrad Dybcio }; 3828*184fdd87SKonrad Dybcio 3829*184fdd87SKonrad Dybcio 3830*184fdd87SKonrad Dybcio static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3831*184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3832*184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3833*184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3834*184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3835*184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3836*184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3837*184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3838*184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3839*184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 3840*184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3841*184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3842*184fdd87SKonrad Dybcio DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3843*184fdd87SKonrad Dybcio }; 3844*184fdd87SKonrad Dybcio 3845*184fdd87SKonrad Dybcio static struct gdsc *gcc_sm6375_gdscs[] = { 3846*184fdd87SKonrad Dybcio [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3847*184fdd87SKonrad Dybcio [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3848*184fdd87SKonrad Dybcio [CAMSS_TOP_GDSC] = &camss_top_gdsc, 3849*184fdd87SKonrad Dybcio [VENUS_GDSC] = &venus_gdsc, 3850*184fdd87SKonrad Dybcio [VCODEC0_GDSC] = &vcodec0_gdsc, 3851*184fdd87SKonrad Dybcio [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc, 3852*184fdd87SKonrad Dybcio [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc, 3853*184fdd87SKonrad Dybcio [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc, 3854*184fdd87SKonrad Dybcio [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, 3855*184fdd87SKonrad Dybcio }; 3856*184fdd87SKonrad Dybcio 3857*184fdd87SKonrad Dybcio static const struct regmap_config gcc_sm6375_regmap_config = { 3858*184fdd87SKonrad Dybcio .reg_bits = 32, 3859*184fdd87SKonrad Dybcio .reg_stride = 4, 3860*184fdd87SKonrad Dybcio .val_bits = 32, 3861*184fdd87SKonrad Dybcio .max_register = 0xc7000, 3862*184fdd87SKonrad Dybcio .fast_io = true, 3863*184fdd87SKonrad Dybcio }; 3864*184fdd87SKonrad Dybcio 3865*184fdd87SKonrad Dybcio static const struct qcom_cc_desc gcc_sm6375_desc = { 3866*184fdd87SKonrad Dybcio .config = &gcc_sm6375_regmap_config, 3867*184fdd87SKonrad Dybcio .clks = gcc_sm6375_clocks, 3868*184fdd87SKonrad Dybcio .num_clks = ARRAY_SIZE(gcc_sm6375_clocks), 3869*184fdd87SKonrad Dybcio .resets = gcc_sm6375_resets, 3870*184fdd87SKonrad Dybcio .num_resets = ARRAY_SIZE(gcc_sm6375_resets), 3871*184fdd87SKonrad Dybcio .gdscs = gcc_sm6375_gdscs, 3872*184fdd87SKonrad Dybcio .num_gdscs = ARRAY_SIZE(gcc_sm6375_gdscs), 3873*184fdd87SKonrad Dybcio }; 3874*184fdd87SKonrad Dybcio 3875*184fdd87SKonrad Dybcio static const struct of_device_id gcc_sm6375_match_table[] = { 3876*184fdd87SKonrad Dybcio { .compatible = "qcom,sm6375-gcc" }, 3877*184fdd87SKonrad Dybcio { } 3878*184fdd87SKonrad Dybcio }; 3879*184fdd87SKonrad Dybcio MODULE_DEVICE_TABLE(of, gcc_sm6375_match_table); 3880*184fdd87SKonrad Dybcio 3881*184fdd87SKonrad Dybcio static int gcc_sm6375_probe(struct platform_device *pdev) 3882*184fdd87SKonrad Dybcio { 3883*184fdd87SKonrad Dybcio struct regmap *regmap; 3884*184fdd87SKonrad Dybcio int ret; 3885*184fdd87SKonrad Dybcio 3886*184fdd87SKonrad Dybcio regmap = qcom_cc_map(pdev, &gcc_sm6375_desc); 3887*184fdd87SKonrad Dybcio if (IS_ERR(regmap)) 3888*184fdd87SKonrad Dybcio return PTR_ERR(regmap); 3889*184fdd87SKonrad Dybcio 3890*184fdd87SKonrad Dybcio ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); 3891*184fdd87SKonrad Dybcio if (ret) 3892*184fdd87SKonrad Dybcio return ret; 3893*184fdd87SKonrad Dybcio 3894*184fdd87SKonrad Dybcio /* 3895*184fdd87SKonrad Dybcio * Keep the following clocks always on: 3896*184fdd87SKonrad Dybcio * GCC_CAMERA_XO_CLK, GCC_CPUSS_GNOC_CLK, GCC_DISP_XO_CLK 3897*184fdd87SKonrad Dybcio */ 3898*184fdd87SKonrad Dybcio regmap_update_bits(regmap, 0x17028, BIT(0), BIT(0)); 3899*184fdd87SKonrad Dybcio regmap_update_bits(regmap, 0x2b004, BIT(0), BIT(0)); 3900*184fdd87SKonrad Dybcio regmap_update_bits(regmap, 0x1702c, BIT(0), BIT(0)); 3901*184fdd87SKonrad Dybcio 3902*184fdd87SKonrad Dybcio clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config); 3903*184fdd87SKonrad Dybcio clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config); 3904*184fdd87SKonrad Dybcio clk_lucid_pll_configure(&gpll8, regmap, &gpll8_config); 3905*184fdd87SKonrad Dybcio clk_zonda_pll_configure(&gpll9, regmap, &gpll9_config); 3906*184fdd87SKonrad Dybcio 3907*184fdd87SKonrad Dybcio return qcom_cc_really_probe(pdev, &gcc_sm6375_desc, regmap); 3908*184fdd87SKonrad Dybcio } 3909*184fdd87SKonrad Dybcio 3910*184fdd87SKonrad Dybcio static struct platform_driver gcc_sm6375_driver = { 3911*184fdd87SKonrad Dybcio .probe = gcc_sm6375_probe, 3912*184fdd87SKonrad Dybcio .driver = { 3913*184fdd87SKonrad Dybcio .name = "gcc-sm6375", 3914*184fdd87SKonrad Dybcio .of_match_table = gcc_sm6375_match_table, 3915*184fdd87SKonrad Dybcio }, 3916*184fdd87SKonrad Dybcio }; 3917*184fdd87SKonrad Dybcio 3918*184fdd87SKonrad Dybcio static int __init gcc_sm6375_init(void) 3919*184fdd87SKonrad Dybcio { 3920*184fdd87SKonrad Dybcio return platform_driver_register(&gcc_sm6375_driver); 3921*184fdd87SKonrad Dybcio } 3922*184fdd87SKonrad Dybcio subsys_initcall(gcc_sm6375_init); 3923*184fdd87SKonrad Dybcio 3924*184fdd87SKonrad Dybcio static void __exit gcc_sm6375_exit(void) 3925*184fdd87SKonrad Dybcio { 3926*184fdd87SKonrad Dybcio platform_driver_unregister(&gcc_sm6375_driver); 3927*184fdd87SKonrad Dybcio } 3928*184fdd87SKonrad Dybcio module_exit(gcc_sm6375_exit); 3929*184fdd87SKonrad Dybcio 3930*184fdd87SKonrad Dybcio MODULE_DESCRIPTION("QTI GCC SM6375 Driver"); 3931*184fdd87SKonrad Dybcio MODULE_LICENSE("GPL"); 3932