1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,gcc-sm6350.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-rcg.h" 16 #include "clk-regmap.h" 17 #include "clk-regmap-divider.h" 18 #include "clk-regmap-mux.h" 19 #include "common.h" 20 #include "gdsc.h" 21 #include "reset.h" 22 23 enum { 24 P_BI_TCXO, 25 P_GPLL0_OUT_EVEN, 26 P_GPLL0_OUT_MAIN, 27 P_GPLL0_OUT_ODD, 28 P_GPLL6_OUT_EVEN, 29 P_GPLL7_OUT_MAIN, 30 P_SLEEP_CLK, 31 }; 32 33 static struct clk_alpha_pll gpll0 = { 34 .offset = 0x0, 35 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 36 .clkr = { 37 .enable_reg = 0x52010, 38 .enable_mask = BIT(0), 39 .hw.init = &(struct clk_init_data){ 40 .name = "gpll0", 41 .parent_data = &(const struct clk_parent_data){ 42 .fw_name = "bi_tcxo", 43 }, 44 .num_parents = 1, 45 .ops = &clk_alpha_pll_fixed_fabia_ops, 46 }, 47 }, 48 }; 49 50 static const struct clk_div_table post_div_table_gpll0_out_even[] = { 51 { 0x1, 2 }, 52 { } 53 }; 54 55 static struct clk_alpha_pll_postdiv gpll0_out_even = { 56 .offset = 0x0, 57 .post_div_shift = 8, 58 .post_div_table = post_div_table_gpll0_out_even, 59 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even), 60 .width = 4, 61 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 62 .clkr.hw.init = &(struct clk_init_data){ 63 .name = "gpll0_out_even", 64 .parent_hws = (const struct clk_hw*[]){ 65 &gpll0.clkr.hw, 66 }, 67 .num_parents = 1, 68 .ops = &clk_alpha_pll_postdiv_fabia_ops, 69 }, 70 }; 71 72 static const struct clk_div_table post_div_table_gpll0_out_odd[] = { 73 { 0x3, 3 }, 74 { } 75 }; 76 77 static struct clk_alpha_pll_postdiv gpll0_out_odd = { 78 .offset = 0x0, 79 .post_div_shift = 12, 80 .post_div_table = post_div_table_gpll0_out_odd, 81 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_odd), 82 .width = 4, 83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 84 .clkr.hw.init = &(struct clk_init_data){ 85 .name = "gpll0_out_odd", 86 .parent_hws = (const struct clk_hw*[]){ 87 &gpll0.clkr.hw, 88 }, 89 .num_parents = 1, 90 .ops = &clk_alpha_pll_postdiv_fabia_ops, 91 }, 92 }; 93 94 static struct clk_alpha_pll gpll6 = { 95 .offset = 0x6000, 96 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 97 .clkr = { 98 .enable_reg = 0x52010, 99 .enable_mask = BIT(6), 100 .hw.init = &(struct clk_init_data){ 101 .name = "gpll6", 102 .parent_hws = (const struct clk_hw*[]){ 103 &gpll0.clkr.hw, 104 }, 105 .num_parents = 1, 106 .ops = &clk_alpha_pll_fixed_fabia_ops, 107 }, 108 }, 109 }; 110 111 static const struct clk_div_table post_div_table_gpll6_out_even[] = { 112 { 0x1, 2 }, 113 { } 114 }; 115 116 static struct clk_alpha_pll_postdiv gpll6_out_even = { 117 .offset = 0x6000, 118 .post_div_shift = 8, 119 .post_div_table = post_div_table_gpll6_out_even, 120 .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_even), 121 .width = 4, 122 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 123 .clkr.hw.init = &(struct clk_init_data){ 124 .name = "gpll6_out_even", 125 .parent_hws = (const struct clk_hw*[]){ 126 &gpll0.clkr.hw, 127 }, 128 .num_parents = 1, 129 .ops = &clk_alpha_pll_postdiv_fabia_ops, 130 }, 131 }; 132 133 static struct clk_alpha_pll gpll7 = { 134 .offset = 0x7000, 135 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 136 .clkr = { 137 .enable_reg = 0x52010, 138 .enable_mask = BIT(7), 139 .hw.init = &(struct clk_init_data){ 140 .name = "gpll7", 141 .parent_hws = (const struct clk_hw*[]){ 142 &gpll0.clkr.hw, 143 }, 144 .num_parents = 1, 145 .ops = &clk_alpha_pll_fixed_fabia_ops, 146 }, 147 }, 148 }; 149 150 static const struct parent_map gcc_parent_map_0[] = { 151 { P_BI_TCXO, 0 }, 152 { P_GPLL0_OUT_MAIN, 1 }, 153 { P_GPLL6_OUT_EVEN, 2 }, 154 { P_GPLL0_OUT_EVEN, 6 }, 155 }; 156 157 static const struct clk_parent_data gcc_parent_data_0[] = { 158 { .fw_name = "bi_tcxo" }, 159 { .hw = &gpll0.clkr.hw }, 160 { .hw = &gpll6_out_even.clkr.hw }, 161 { .hw = &gpll0_out_even.clkr.hw }, 162 }; 163 164 static const struct parent_map gcc_parent_map_1[] = { 165 { P_BI_TCXO, 0 }, 166 { P_GPLL0_OUT_EVEN, 6 }, 167 }; 168 169 static const struct clk_parent_data gcc_parent_data_1[] = { 170 { .fw_name = "bi_tcxo" }, 171 { .hw = &gpll0_out_even.clkr.hw }, 172 }; 173 174 static const struct parent_map gcc_parent_map_2[] = { 175 { P_BI_TCXO, 0 }, 176 { P_GPLL0_OUT_ODD, 2 }, 177 }; 178 179 static const struct clk_parent_data gcc_parent_data_2_ao[] = { 180 { .fw_name = "bi_tcxo_ao" }, 181 { .hw = &gpll0_out_odd.clkr.hw }, 182 }; 183 184 static const struct parent_map gcc_parent_map_4[] = { 185 { P_BI_TCXO, 0 }, 186 { P_GPLL0_OUT_MAIN, 1 }, 187 { P_GPLL0_OUT_ODD, 2 }, 188 }; 189 190 static const struct clk_parent_data gcc_parent_data_4[] = { 191 { .fw_name = "bi_tcxo" }, 192 { .hw = &gpll0.clkr.hw }, 193 { .hw = &gpll0_out_odd.clkr.hw }, 194 }; 195 196 static const struct parent_map gcc_parent_map_5[] = { 197 { P_BI_TCXO, 0 }, 198 { P_GPLL0_OUT_ODD, 2 }, 199 { P_SLEEP_CLK, 5 }, 200 { P_GPLL0_OUT_EVEN, 6 }, 201 }; 202 203 static const struct clk_parent_data gcc_parent_data_5[] = { 204 { .fw_name = "bi_tcxo" }, 205 { .hw = &gpll0_out_odd.clkr.hw }, 206 { .fw_name = "sleep_clk" }, 207 { .hw = &gpll0_out_even.clkr.hw }, 208 }; 209 210 static const struct parent_map gcc_parent_map_6[] = { 211 { P_BI_TCXO, 0 }, 212 { P_SLEEP_CLK, 5 }, 213 }; 214 215 static const struct clk_parent_data gcc_parent_data_6[] = { 216 { .fw_name = "bi_tcxo" }, 217 { .fw_name = "sleep_clk" } 218 }; 219 220 static const struct parent_map gcc_parent_map_7[] = { 221 { P_BI_TCXO, 0 }, 222 { P_GPLL6_OUT_EVEN, 2 }, 223 { P_GPLL0_OUT_EVEN, 6 }, 224 }; 225 226 static const struct clk_parent_data gcc_parent_data_7[] = { 227 { .fw_name = "bi_tcxo" }, 228 { .hw = &gpll6_out_even.clkr.hw }, 229 { .hw = &gpll0_out_even.clkr.hw }, 230 }; 231 232 static const struct parent_map gcc_parent_map_8[] = { 233 { P_BI_TCXO, 0 }, 234 { P_GPLL0_OUT_ODD, 2 }, 235 { P_GPLL7_OUT_MAIN, 3 }, 236 }; 237 238 static const struct clk_parent_data gcc_parent_data_8[] = { 239 { .fw_name = "bi_tcxo" }, 240 { .hw = &gpll0_out_odd.clkr.hw }, 241 { .hw = &gpll7.clkr.hw }, 242 }; 243 244 static struct clk_regmap_div gcc_gpu_gpll0_main_div_clk_src = { 245 .reg = 0x4514C, 246 .shift = 0, 247 .width = 2, 248 .clkr.hw.init = &(struct clk_init_data) { 249 .name = "gcc_gpu_gpll0_main_div_clk_src", 250 .parent_hws = (const struct clk_hw*[]){ 251 &gpll0.clkr.hw, 252 }, 253 .num_parents = 1, 254 .ops = &clk_regmap_div_ro_ops, 255 }, 256 }; 257 258 static struct clk_regmap_div gcc_npu_pll0_main_div_clk_src = { 259 .reg = 0x4ce00, 260 .shift = 0, 261 .width = 2, 262 .clkr.hw.init = &(struct clk_init_data) { 263 .name = "gcc_npu_pll0_main_div_clk_src", 264 .parent_hws = (const struct clk_hw*[]){ 265 &gpll0.clkr.hw, 266 }, 267 .num_parents = 1, 268 .ops = &clk_regmap_div_ro_ops, 269 }, 270 }; 271 272 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { 273 F(19200000, P_BI_TCXO, 1, 0, 0), 274 { } 275 }; 276 277 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 278 .cmd_rcgr = 0x30014, 279 .mnd_width = 0, 280 .hid_width = 5, 281 .parent_map = gcc_parent_map_2, 282 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, 283 .clkr.hw.init = &(struct clk_init_data){ 284 .name = "gcc_cpuss_ahb_clk_src", 285 .parent_data = gcc_parent_data_2_ao, 286 .num_parents = ARRAY_SIZE(gcc_parent_data_2_ao), 287 .ops = &clk_rcg2_ops, 288 }, 289 }; 290 291 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 292 F(19200000, P_BI_TCXO, 1, 0, 0), 293 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 294 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0), 295 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0), 296 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0), 297 { } 298 }; 299 300 static struct clk_rcg2 gcc_gp1_clk_src = { 301 .cmd_rcgr = 0x37004, 302 .mnd_width = 8, 303 .hid_width = 5, 304 .parent_map = gcc_parent_map_5, 305 .freq_tbl = ftbl_gcc_gp1_clk_src, 306 .clkr.hw.init = &(struct clk_init_data){ 307 .name = "gcc_gp1_clk_src", 308 .parent_data = gcc_parent_data_5, 309 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 310 .ops = &clk_rcg2_ops, 311 }, 312 }; 313 314 static struct clk_rcg2 gcc_gp2_clk_src = { 315 .cmd_rcgr = 0x38004, 316 .mnd_width = 8, 317 .hid_width = 5, 318 .parent_map = gcc_parent_map_5, 319 .freq_tbl = ftbl_gcc_gp1_clk_src, 320 .clkr.hw.init = &(struct clk_init_data){ 321 .name = "gcc_gp2_clk_src", 322 .parent_data = gcc_parent_data_5, 323 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 324 .ops = &clk_rcg2_ops, 325 }, 326 }; 327 328 static struct clk_rcg2 gcc_gp3_clk_src = { 329 .cmd_rcgr = 0x39004, 330 .mnd_width = 8, 331 .hid_width = 5, 332 .parent_map = gcc_parent_map_5, 333 .freq_tbl = ftbl_gcc_gp1_clk_src, 334 .clkr.hw.init = &(struct clk_init_data){ 335 .name = "gcc_gp3_clk_src", 336 .parent_data = gcc_parent_data_5, 337 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 338 .ops = &clk_rcg2_ops, 339 }, 340 }; 341 342 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 343 F(19200000, P_BI_TCXO, 1, 0, 0), 344 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), 345 { } 346 }; 347 348 static struct clk_rcg2 gcc_pdm2_clk_src = { 349 .cmd_rcgr = 0x23010, 350 .mnd_width = 0, 351 .hid_width = 5, 352 .parent_map = gcc_parent_map_1, 353 .freq_tbl = ftbl_gcc_pdm2_clk_src, 354 .clkr.hw.init = &(struct clk_init_data){ 355 .name = "gcc_pdm2_clk_src", 356 .parent_data = gcc_parent_data_1, 357 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 358 .ops = &clk_rcg2_ops, 359 }, 360 }; 361 362 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 363 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 364 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 365 F(19200000, P_BI_TCXO, 1, 0, 0), 366 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 367 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 368 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 369 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 370 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 371 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 372 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 373 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 374 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), 375 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), 376 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), 377 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), 378 F(128000000, P_GPLL6_OUT_EVEN, 3, 0, 0), 379 { } 380 }; 381 382 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 383 .name = "gcc_qupv3_wrap0_s0_clk_src", 384 .parent_data = gcc_parent_data_0, 385 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 386 .ops = &clk_rcg2_ops, 387 }; 388 389 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 390 .cmd_rcgr = 0x21148, 391 .mnd_width = 16, 392 .hid_width = 5, 393 .parent_map = gcc_parent_map_0, 394 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 395 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 396 }; 397 398 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 399 .name = "gcc_qupv3_wrap0_s1_clk_src", 400 .parent_data = gcc_parent_data_0, 401 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 402 .ops = &clk_rcg2_ops, 403 }; 404 405 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 406 .cmd_rcgr = 0x21278, 407 .mnd_width = 16, 408 .hid_width = 5, 409 .parent_map = gcc_parent_map_0, 410 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 411 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 412 }; 413 414 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 415 .name = "gcc_qupv3_wrap0_s2_clk_src", 416 .parent_data = gcc_parent_data_0, 417 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 418 .ops = &clk_rcg2_ops, 419 }; 420 421 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 422 .cmd_rcgr = 0x213a8, 423 .mnd_width = 16, 424 .hid_width = 5, 425 .parent_map = gcc_parent_map_0, 426 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 427 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 428 }; 429 430 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 431 .name = "gcc_qupv3_wrap0_s3_clk_src", 432 .parent_data = gcc_parent_data_0, 433 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 434 .ops = &clk_rcg2_ops, 435 }; 436 437 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 438 .cmd_rcgr = 0x214d8, 439 .mnd_width = 16, 440 .hid_width = 5, 441 .parent_map = gcc_parent_map_0, 442 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 443 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 444 }; 445 446 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 447 .name = "gcc_qupv3_wrap0_s4_clk_src", 448 .parent_data = gcc_parent_data_0, 449 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 450 .ops = &clk_rcg2_ops, 451 }; 452 453 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 454 .cmd_rcgr = 0x21608, 455 .mnd_width = 16, 456 .hid_width = 5, 457 .parent_map = gcc_parent_map_0, 458 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 459 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 460 }; 461 462 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 463 .name = "gcc_qupv3_wrap0_s5_clk_src", 464 .parent_data = gcc_parent_data_0, 465 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 466 .ops = &clk_rcg2_ops, 467 }; 468 469 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 470 .cmd_rcgr = 0x21738, 471 .mnd_width = 16, 472 .hid_width = 5, 473 .parent_map = gcc_parent_map_0, 474 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 475 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 476 }; 477 478 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 479 .name = "gcc_qupv3_wrap1_s0_clk_src", 480 .parent_data = gcc_parent_data_0, 481 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 482 .ops = &clk_rcg2_ops, 483 }; 484 485 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 486 .cmd_rcgr = 0x22018, 487 .mnd_width = 16, 488 .hid_width = 5, 489 .parent_map = gcc_parent_map_0, 490 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 491 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 492 }; 493 494 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 495 .name = "gcc_qupv3_wrap1_s1_clk_src", 496 .parent_data = gcc_parent_data_0, 497 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 498 .ops = &clk_rcg2_ops, 499 }; 500 501 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 502 .cmd_rcgr = 0x22148, 503 .mnd_width = 16, 504 .hid_width = 5, 505 .parent_map = gcc_parent_map_0, 506 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 507 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 508 }; 509 510 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 511 .name = "gcc_qupv3_wrap1_s2_clk_src", 512 .parent_data = gcc_parent_data_0, 513 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 514 .ops = &clk_rcg2_ops, 515 }; 516 517 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 518 .cmd_rcgr = 0x22278, 519 .mnd_width = 16, 520 .hid_width = 5, 521 .parent_map = gcc_parent_map_0, 522 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 523 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 524 }; 525 526 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 527 .name = "gcc_qupv3_wrap1_s3_clk_src", 528 .parent_data = gcc_parent_data_0, 529 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 530 .ops = &clk_rcg2_ops, 531 }; 532 533 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 534 .cmd_rcgr = 0x223a8, 535 .mnd_width = 16, 536 .hid_width = 5, 537 .parent_map = gcc_parent_map_0, 538 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 539 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 540 }; 541 542 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 543 .name = "gcc_qupv3_wrap1_s4_clk_src", 544 .parent_data = gcc_parent_data_0, 545 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 546 .ops = &clk_rcg2_ops, 547 }; 548 549 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 550 .cmd_rcgr = 0x224d8, 551 .mnd_width = 16, 552 .hid_width = 5, 553 .parent_map = gcc_parent_map_0, 554 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 555 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 556 }; 557 558 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 559 .name = "gcc_qupv3_wrap1_s5_clk_src", 560 .parent_data = gcc_parent_data_0, 561 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 562 .ops = &clk_rcg2_ops, 563 }; 564 565 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 566 .cmd_rcgr = 0x22608, 567 .mnd_width = 16, 568 .hid_width = 5, 569 .parent_map = gcc_parent_map_0, 570 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 571 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 572 }; 573 574 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 575 F(144000, P_BI_TCXO, 16, 3, 25), 576 F(400000, P_BI_TCXO, 12, 1, 4), 577 F(19200000, P_BI_TCXO, 1, 0, 0), 578 F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), 579 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 580 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 581 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 582 F(192000000, P_GPLL6_OUT_EVEN, 2, 0, 0), 583 F(384000000, P_GPLL6_OUT_EVEN, 1, 0, 0), 584 { } 585 }; 586 587 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 588 .cmd_rcgr = 0x4b024, 589 .mnd_width = 8, 590 .hid_width = 5, 591 .parent_map = gcc_parent_map_7, 592 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 593 .clkr.hw.init = &(struct clk_init_data){ 594 .name = "gcc_sdcc1_apps_clk_src", 595 .parent_data = gcc_parent_data_7, 596 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 597 .ops = &clk_rcg2_ops, 598 }, 599 }; 600 601 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 602 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 603 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 604 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 605 { } 606 }; 607 608 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 609 .cmd_rcgr = 0x4b00c, 610 .mnd_width = 0, 611 .hid_width = 5, 612 .parent_map = gcc_parent_map_1, 613 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 614 .clkr.hw.init = &(struct clk_init_data){ 615 .name = "gcc_sdcc1_ice_core_clk_src", 616 .parent_data = gcc_parent_data_1, 617 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 618 .ops = &clk_rcg2_ops, 619 }, 620 }; 621 622 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 623 F(400000, P_BI_TCXO, 12, 1, 4), 624 F(9600000, P_BI_TCXO, 2, 0, 0), 625 F(19200000, P_BI_TCXO, 1, 0, 0), 626 F(25000000, P_GPLL0_OUT_ODD, 8, 0, 0), 627 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0), 628 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0), 629 F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0), 630 { } 631 }; 632 633 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 634 .cmd_rcgr = 0x2000c, 635 .mnd_width = 8, 636 .hid_width = 5, 637 .parent_map = gcc_parent_map_8, 638 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 639 .clkr.hw.init = &(struct clk_init_data){ 640 .name = "gcc_sdcc2_apps_clk_src", 641 .parent_data = gcc_parent_data_8, 642 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 643 .ops = &clk_rcg2_floor_ops, 644 }, 645 }; 646 647 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 648 F(25000000, P_GPLL0_OUT_ODD, 8, 0, 0), 649 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0), 650 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0), 651 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0), 652 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 653 { } 654 }; 655 656 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 657 .cmd_rcgr = 0x3a01c, 658 .mnd_width = 8, 659 .hid_width = 5, 660 .parent_map = gcc_parent_map_4, 661 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 662 .clkr.hw.init = &(struct clk_init_data){ 663 .name = "gcc_ufs_phy_axi_clk_src", 664 .parent_data = gcc_parent_data_4, 665 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 666 .ops = &clk_rcg2_ops, 667 }, 668 }; 669 670 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 671 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 672 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 673 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 674 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 675 { } 676 }; 677 678 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 679 .cmd_rcgr = 0x3a048, 680 .mnd_width = 0, 681 .hid_width = 5, 682 .parent_map = gcc_parent_map_1, 683 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 684 .clkr.hw.init = &(struct clk_init_data){ 685 .name = "gcc_ufs_phy_ice_core_clk_src", 686 .parent_data = gcc_parent_data_1, 687 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 688 .ops = &clk_rcg2_ops, 689 }, 690 }; 691 692 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 693 F(9600000, P_BI_TCXO, 2, 0, 0), 694 F(19200000, P_BI_TCXO, 1, 0, 0), 695 { } 696 }; 697 698 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 699 .cmd_rcgr = 0x3a0b0, 700 .mnd_width = 0, 701 .hid_width = 5, 702 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 703 .clkr.hw.init = &(struct clk_init_data){ 704 .name = "gcc_ufs_phy_phy_aux_clk_src", 705 .parent_data = &(const struct clk_parent_data){ 706 .fw_name = "bi_tcxo", 707 }, 708 .num_parents = 1, 709 .ops = &clk_rcg2_ops, 710 }, 711 }; 712 713 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 714 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 715 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 716 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 717 { } 718 }; 719 720 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 721 .cmd_rcgr = 0x3a060, 722 .mnd_width = 0, 723 .hid_width = 5, 724 .parent_map = gcc_parent_map_1, 725 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 726 .clkr.hw.init = &(struct clk_init_data){ 727 .name = "gcc_ufs_phy_unipro_core_clk_src", 728 .parent_data = gcc_parent_data_1, 729 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 730 .ops = &clk_rcg2_ops, 731 }, 732 }; 733 734 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 735 F(66666667, P_GPLL0_OUT_ODD, 3, 0, 0), 736 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 737 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 738 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 739 { } 740 }; 741 742 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 743 .cmd_rcgr = 0x1a01c, 744 .mnd_width = 8, 745 .hid_width = 5, 746 .parent_map = gcc_parent_map_4, 747 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 748 .clkr.hw.init = &(struct clk_init_data){ 749 .name = "gcc_usb30_prim_master_clk_src", 750 .parent_data = gcc_parent_data_4, 751 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 752 .ops = &clk_rcg2_ops, 753 }, 754 }; 755 756 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 757 F(19200000, P_BI_TCXO, 1, 0, 0), 758 { } 759 }; 760 761 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 762 .cmd_rcgr = 0x1a034, 763 .mnd_width = 0, 764 .hid_width = 5, 765 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 766 .clkr.hw.init = &(struct clk_init_data){ 767 .name = "gcc_usb30_prim_mock_utmi_clk_src", 768 .parent_data = &(const struct clk_parent_data){ 769 .fw_name = "bi_tcxo", 770 }, 771 .num_parents = 1, 772 .ops = &clk_rcg2_ops, 773 }, 774 }; 775 776 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 777 .cmd_rcgr = 0x1a060, 778 .mnd_width = 0, 779 .hid_width = 5, 780 .parent_map = gcc_parent_map_6, 781 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 782 .clkr.hw.init = &(struct clk_init_data){ 783 .name = "gcc_usb3_prim_phy_aux_clk_src", 784 .parent_data = gcc_parent_data_6, 785 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 786 .ops = &clk_rcg2_ops, 787 }, 788 }; 789 790 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 791 .halt_reg = 0x3e014, 792 .halt_check = BRANCH_HALT_DELAY, 793 .hwcg_reg = 0x3e014, 794 .hwcg_bit = 1, 795 .clkr = { 796 .enable_reg = 0x3e014, 797 .enable_mask = BIT(0), 798 .hw.init = &(struct clk_init_data){ 799 .name = "gcc_aggre_ufs_phy_axi_clk", 800 .parent_hws = (const struct clk_hw*[]){ 801 &gcc_ufs_phy_axi_clk_src.clkr.hw, 802 }, 803 .num_parents = 1, 804 .flags = CLK_SET_RATE_PARENT, 805 .ops = &clk_branch2_ops, 806 }, 807 }, 808 }; 809 810 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { 811 .halt_reg = 0x3e014, 812 .halt_check = BRANCH_HALT, 813 .hwcg_reg = 0x3e014, 814 .hwcg_bit = 1, 815 .clkr = { 816 .enable_reg = 0x3e014, 817 .enable_mask = BIT(1), 818 .hw.init = &(struct clk_init_data){ 819 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", 820 .parent_hws = (const struct clk_hw*[]){ 821 &gcc_ufs_phy_axi_clk_src.clkr.hw, 822 }, 823 .num_parents = 1, 824 .flags = CLK_SET_RATE_PARENT, 825 .ops = &clk_branch2_ops, 826 }, 827 }, 828 }; 829 830 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { 831 .halt_reg = 0x3e014, 832 .halt_check = BRANCH_HALT, 833 .hwcg_reg = 0x3e014, 834 .hwcg_bit = 1, 835 .clkr = { 836 .enable_reg = 0x3e014, 837 .enable_mask = BIT(1), 838 .hw.init = &(struct clk_init_data){ 839 .name = "gcc_ufs_phy_axi_hw_ctl_clk", 840 .parent_hws = (const struct clk_hw*[]){ 841 &gcc_ufs_phy_axi_clk_src.clkr.hw, 842 }, 843 .num_parents = 1, 844 .flags = CLK_SET_RATE_PARENT, 845 .ops = &clk_branch2_ops, 846 }, 847 }, 848 }; 849 850 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 851 .halt_reg = 0x3e010, 852 .halt_check = BRANCH_HALT, 853 .hwcg_reg = 0x3e010, 854 .hwcg_bit = 1, 855 .clkr = { 856 .enable_reg = 0x3e010, 857 .enable_mask = BIT(0), 858 .hw.init = &(struct clk_init_data){ 859 .name = "gcc_aggre_usb3_prim_axi_clk", 860 .parent_hws = (const struct clk_hw*[]){ 861 &gcc_usb30_prim_master_clk_src.clkr.hw, 862 }, 863 .num_parents = 1, 864 .flags = CLK_SET_RATE_PARENT, 865 .ops = &clk_branch2_ops, 866 }, 867 }, 868 }; 869 870 static struct clk_branch gcc_boot_rom_ahb_clk = { 871 .halt_reg = 0x26004, 872 .halt_check = BRANCH_HALT_VOTED, 873 .hwcg_reg = 0x26004, 874 .hwcg_bit = 1, 875 .clkr = { 876 .enable_reg = 0x52000, 877 .enable_mask = BIT(28), 878 .hw.init = &(struct clk_init_data){ 879 .name = "gcc_boot_rom_ahb_clk", 880 .ops = &clk_branch2_ops, 881 }, 882 }, 883 }; 884 885 static struct clk_branch gcc_camera_ahb_clk = { 886 .halt_reg = 0x17008, 887 .halt_check = BRANCH_HALT, 888 .hwcg_reg = 0x17008, 889 .hwcg_bit = 1, 890 .clkr = { 891 .enable_reg = 0x17008, 892 .enable_mask = BIT(0), 893 .hw.init = &(struct clk_init_data){ 894 .name = "gcc_camera_ahb_clk", 895 .flags = CLK_IS_CRITICAL, 896 .ops = &clk_branch2_ops, 897 }, 898 }, 899 }; 900 901 static struct clk_branch gcc_camera_axi_clk = { 902 .halt_reg = 0x17018, 903 .halt_check = BRANCH_HALT, 904 .hwcg_reg = 0x17018, 905 .hwcg_bit = 1, 906 .clkr = { 907 .enable_reg = 0x17018, 908 .enable_mask = BIT(0), 909 .hw.init = &(struct clk_init_data){ 910 .name = "gcc_camera_axi_clk", 911 .ops = &clk_branch2_ops, 912 }, 913 }, 914 }; 915 916 static struct clk_branch gcc_camera_throttle_nrt_axi_clk = { 917 .halt_reg = 0x17078, 918 .halt_check = BRANCH_VOTED, 919 .hwcg_reg = 0x17078, 920 .hwcg_bit = 1, 921 .clkr = { 922 .enable_reg = 0x17078, 923 .enable_mask = BIT(0), 924 .hw.init = &(struct clk_init_data){ 925 .name = "gcc_camera_throttle_nrt_axi_clk", 926 .ops = &clk_branch2_ops, 927 }, 928 }, 929 }; 930 931 static struct clk_branch gcc_camera_throttle_rt_axi_clk = { 932 .halt_reg = 0x17024, 933 .halt_check = BRANCH_VOTED, 934 .hwcg_reg = 0x17024, 935 .hwcg_bit = 1, 936 .clkr = { 937 .enable_reg = 0x17024, 938 .enable_mask = BIT(0), 939 .hw.init = &(struct clk_init_data){ 940 .name = "gcc_camera_throttle_rt_axi_clk", 941 .ops = &clk_branch2_ops, 942 }, 943 }, 944 }; 945 946 static struct clk_branch gcc_camera_xo_clk = { 947 .halt_reg = 0x17030, 948 .halt_check = BRANCH_HALT, 949 .clkr = { 950 .enable_reg = 0x17030, 951 .enable_mask = BIT(0), 952 .hw.init = &(struct clk_init_data){ 953 .name = "gcc_camera_xo_clk", 954 .flags = CLK_IS_CRITICAL, 955 .ops = &clk_branch2_ops, 956 }, 957 }, 958 }; 959 960 static struct clk_branch gcc_ce1_ahb_clk = { 961 .halt_reg = 0x2b00c, 962 .halt_check = BRANCH_HALT_VOTED, 963 .hwcg_reg = 0x2b00c, 964 .hwcg_bit = 1, 965 .clkr = { 966 .enable_reg = 0x52008, 967 .enable_mask = BIT(3), 968 .hw.init = &(struct clk_init_data){ 969 .name = "gcc_ce1_ahb_clk", 970 .ops = &clk_branch2_ops, 971 }, 972 }, 973 }; 974 975 static struct clk_branch gcc_ce1_axi_clk = { 976 .halt_reg = 0x2b008, 977 .halt_check = BRANCH_HALT_VOTED, 978 .clkr = { 979 .enable_reg = 0x52008, 980 .enable_mask = BIT(2), 981 .hw.init = &(struct clk_init_data){ 982 .name = "gcc_ce1_axi_clk", 983 .ops = &clk_branch2_ops, 984 }, 985 }, 986 }; 987 988 static struct clk_branch gcc_ce1_clk = { 989 .halt_reg = 0x2b004, 990 .halt_check = BRANCH_HALT_VOTED, 991 .clkr = { 992 .enable_reg = 0x52008, 993 .enable_mask = BIT(1), 994 .hw.init = &(struct clk_init_data){ 995 .name = "gcc_ce1_clk", 996 .ops = &clk_branch2_ops, 997 }, 998 }, 999 }; 1000 1001 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1002 .halt_reg = 0x1101c, 1003 .halt_check = BRANCH_HALT, 1004 .hwcg_reg = 0x1101c, 1005 .hwcg_bit = 1, 1006 .clkr = { 1007 .enable_reg = 0x1101c, 1008 .enable_mask = BIT(0), 1009 .hw.init = &(struct clk_init_data){ 1010 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1011 .parent_hws = (const struct clk_hw*[]){ 1012 &gcc_usb30_prim_master_clk_src.clkr.hw, 1013 }, 1014 .num_parents = 1, 1015 .flags = CLK_SET_RATE_PARENT, 1016 .ops = &clk_branch2_ops, 1017 }, 1018 }, 1019 }; 1020 1021 static struct clk_branch gcc_cpuss_ahb_clk = { 1022 .halt_reg = 0x30000, 1023 .halt_check = BRANCH_HALT_VOTED, 1024 .hwcg_reg = 0x30000, 1025 .hwcg_bit = 1, 1026 .clkr = { 1027 .enable_reg = 0x52008, 1028 .enable_mask = BIT(4), 1029 .hw.init = &(struct clk_init_data){ 1030 .name = "gcc_cpuss_ahb_clk", 1031 .parent_hws = (const struct clk_hw*[]){ 1032 &gcc_cpuss_ahb_clk_src.clkr.hw, 1033 }, 1034 .num_parents = 1, 1035 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 1036 .ops = &clk_branch2_ops, 1037 }, 1038 }, 1039 }; 1040 1041 static struct clk_branch gcc_cpuss_gnoc_clk = { 1042 .halt_reg = 0x30004, 1043 .halt_check = BRANCH_HALT_VOTED, 1044 .hwcg_reg = 0x30004, 1045 .hwcg_bit = 1, 1046 .clkr = { 1047 .enable_reg = 0x52008, 1048 .enable_mask = BIT(5), 1049 .hw.init = &(struct clk_init_data){ 1050 .name = "gcc_cpuss_gnoc_clk", 1051 .flags = CLK_IS_CRITICAL, 1052 .ops = &clk_branch2_ops, 1053 }, 1054 }, 1055 }; 1056 1057 static struct clk_branch gcc_cpuss_rbcpr_clk = { 1058 .halt_reg = 0x30008, 1059 .halt_check = BRANCH_HALT, 1060 .clkr = { 1061 .enable_reg = 0x30008, 1062 .enable_mask = BIT(0), 1063 .hw.init = &(struct clk_init_data){ 1064 .name = "gcc_cpuss_rbcpr_clk", 1065 .ops = &clk_branch2_ops, 1066 }, 1067 }, 1068 }; 1069 1070 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1071 .halt_reg = 0x2d038, 1072 .halt_check = BRANCH_VOTED, 1073 .hwcg_reg = 0x2d038, 1074 .hwcg_bit = 1, 1075 .clkr = { 1076 .enable_reg = 0x2d038, 1077 .enable_mask = BIT(0), 1078 .hw.init = &(struct clk_init_data){ 1079 .name = "gcc_ddrss_gpu_axi_clk", 1080 .ops = &clk_branch2_ops, 1081 }, 1082 }, 1083 }; 1084 1085 static struct clk_branch gcc_disp_ahb_clk = { 1086 .halt_reg = 0x1700c, 1087 .halt_check = BRANCH_HALT, 1088 .hwcg_reg = 0x1700c, 1089 .hwcg_bit = 1, 1090 .clkr = { 1091 .enable_reg = 0x1700c, 1092 .enable_mask = BIT(0), 1093 .hw.init = &(struct clk_init_data){ 1094 .name = "gcc_disp_ahb_clk", 1095 .flags = CLK_IS_CRITICAL, 1096 .ops = &clk_branch2_ops, 1097 }, 1098 }, 1099 }; 1100 1101 static struct clk_branch gcc_disp_axi_clk = { 1102 .halt_reg = 0x1701c, 1103 .halt_check = BRANCH_HALT, 1104 .hwcg_reg = 0x1701c, 1105 .hwcg_bit = 1, 1106 .clkr = { 1107 .enable_reg = 0x1701c, 1108 .enable_mask = BIT(0), 1109 .hw.init = &(struct clk_init_data){ 1110 .name = "gcc_disp_axi_clk", 1111 .ops = &clk_branch2_ops, 1112 }, 1113 }, 1114 }; 1115 1116 static struct clk_branch gcc_disp_cc_sleep_clk = { 1117 .halt_reg = 0x17074, 1118 .halt_check = BRANCH_HALT_DELAY, 1119 .hwcg_reg = 0x17074, 1120 .hwcg_bit = 1, 1121 .clkr = { 1122 .enable_reg = 0x17074, 1123 .enable_mask = BIT(0), 1124 .hw.init = &(struct clk_init_data){ 1125 .name = "gcc_disp_cc_sleep_clk", 1126 .ops = &clk_branch2_ops, 1127 }, 1128 }, 1129 }; 1130 1131 static struct clk_branch gcc_disp_cc_xo_clk = { 1132 .halt_reg = 0x17070, 1133 .halt_check = BRANCH_HALT, 1134 .hwcg_reg = 0x17070, 1135 .hwcg_bit = 1, 1136 .clkr = { 1137 .enable_reg = 0x17070, 1138 .enable_mask = BIT(0), 1139 .hw.init = &(struct clk_init_data){ 1140 .name = "gcc_disp_cc_xo_clk", 1141 .flags = CLK_IS_CRITICAL, 1142 .ops = &clk_branch2_ops, 1143 }, 1144 }, 1145 }; 1146 1147 static struct clk_branch gcc_disp_gpll0_clk = { 1148 .halt_check = BRANCH_HALT_DELAY, 1149 .clkr = { 1150 .enable_reg = 0x52000, 1151 .enable_mask = BIT(2), 1152 .hw.init = &(struct clk_init_data){ 1153 .name = "gcc_disp_gpll0_clk", 1154 .parent_hws = (const struct clk_hw*[]){ 1155 &gpll0.clkr.hw, 1156 }, 1157 .num_parents = 1, 1158 .ops = &clk_branch2_ops, 1159 }, 1160 }, 1161 }; 1162 1163 static struct clk_branch gcc_disp_throttle_axi_clk = { 1164 .halt_reg = 0x17028, 1165 .halt_check = BRANCH_HALT, 1166 .hwcg_reg = 0x17028, 1167 .hwcg_bit = 1, 1168 .clkr = { 1169 .enable_reg = 0x17028, 1170 .enable_mask = BIT(0), 1171 .hw.init = &(struct clk_init_data){ 1172 .name = "gcc_disp_throttle_axi_clk", 1173 .ops = &clk_branch2_ops, 1174 }, 1175 }, 1176 }; 1177 1178 static struct clk_branch gcc_disp_xo_clk = { 1179 .halt_reg = 0x17034, 1180 .halt_check = BRANCH_HALT, 1181 .clkr = { 1182 .enable_reg = 0x17034, 1183 .enable_mask = BIT(0), 1184 .hw.init = &(struct clk_init_data){ 1185 .name = "gcc_disp_xo_clk", 1186 .ops = &clk_branch2_ops, 1187 }, 1188 }, 1189 }; 1190 1191 static struct clk_branch gcc_gp1_clk = { 1192 .halt_reg = 0x37000, 1193 .halt_check = BRANCH_HALT, 1194 .clkr = { 1195 .enable_reg = 0x37000, 1196 .enable_mask = BIT(0), 1197 .hw.init = &(struct clk_init_data){ 1198 .name = "gcc_gp1_clk", 1199 .parent_hws = (const struct clk_hw*[]){ 1200 &gcc_gp1_clk_src.clkr.hw, 1201 }, 1202 .num_parents = 1, 1203 .flags = CLK_SET_RATE_PARENT, 1204 .ops = &clk_branch2_ops, 1205 }, 1206 }, 1207 }; 1208 1209 static struct clk_branch gcc_gp2_clk = { 1210 .halt_reg = 0x38000, 1211 .halt_check = BRANCH_HALT, 1212 .clkr = { 1213 .enable_reg = 0x38000, 1214 .enable_mask = BIT(0), 1215 .hw.init = &(struct clk_init_data){ 1216 .name = "gcc_gp2_clk", 1217 .parent_hws = (const struct clk_hw*[]){ 1218 &gcc_gp2_clk_src.clkr.hw, 1219 }, 1220 .num_parents = 1, 1221 .flags = CLK_SET_RATE_PARENT, 1222 .ops = &clk_branch2_ops, 1223 }, 1224 }, 1225 }; 1226 1227 static struct clk_branch gcc_gp3_clk = { 1228 .halt_reg = 0x39000, 1229 .halt_check = BRANCH_HALT, 1230 .clkr = { 1231 .enable_reg = 0x39000, 1232 .enable_mask = BIT(0), 1233 .hw.init = &(struct clk_init_data){ 1234 .name = "gcc_gp3_clk", 1235 .parent_hws = (const struct clk_hw*[]){ 1236 &gcc_gp3_clk_src.clkr.hw, 1237 }, 1238 .num_parents = 1, 1239 .flags = CLK_SET_RATE_PARENT, 1240 .ops = &clk_branch2_ops, 1241 }, 1242 }, 1243 }; 1244 1245 static struct clk_branch gcc_gpu_cfg_ahb_clk = { 1246 .halt_reg = 0x45004, 1247 .halt_check = BRANCH_HALT, 1248 .hwcg_reg = 0x45004, 1249 .hwcg_bit = 1, 1250 .clkr = { 1251 .enable_reg = 0x45004, 1252 .enable_mask = BIT(0), 1253 .hw.init = &(struct clk_init_data){ 1254 .name = "gcc_gpu_cfg_ahb_clk", 1255 .flags = CLK_IS_CRITICAL, 1256 .ops = &clk_branch2_ops, 1257 }, 1258 }, 1259 }; 1260 1261 static struct clk_branch gcc_gpu_gpll0_clk = { 1262 .halt_check = BRANCH_HALT_DELAY, 1263 .clkr = { 1264 .enable_reg = 0x52008, 1265 .enable_mask = BIT(7), 1266 .hw.init = &(struct clk_init_data){ 1267 .name = "gcc_gpu_gpll0_clk", 1268 .parent_hws = (const struct clk_hw*[]){ 1269 &gpll0.clkr.hw, 1270 }, 1271 .num_parents = 1, 1272 .ops = &clk_branch2_ops, 1273 }, 1274 }, 1275 }; 1276 1277 static struct clk_branch gcc_gpu_gpll0_div_clk = { 1278 .halt_check = BRANCH_HALT_DELAY, 1279 .clkr = { 1280 .enable_reg = 0x52008, 1281 .enable_mask = BIT(8), 1282 .hw.init = &(struct clk_init_data){ 1283 .name = "gcc_gpu_gpll0_div_clk", 1284 .parent_hws = (const struct clk_hw*[]){ 1285 &gcc_gpu_gpll0_main_div_clk_src.clkr.hw, 1286 }, 1287 .num_parents = 1, 1288 .ops = &clk_branch2_ops, 1289 }, 1290 }, 1291 }; 1292 1293 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1294 .halt_reg = 0x4500c, 1295 .halt_check = BRANCH_VOTED, 1296 .hwcg_reg = 0x4500c, 1297 .hwcg_bit = 1, 1298 .clkr = { 1299 .enable_reg = 0x4500c, 1300 .enable_mask = BIT(0), 1301 .hw.init = &(struct clk_init_data){ 1302 .name = "gcc_gpu_memnoc_gfx_clk", 1303 .ops = &clk_branch2_ops, 1304 }, 1305 }, 1306 }; 1307 1308 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1309 .halt_reg = 0x45014, 1310 .halt_check = BRANCH_HALT, 1311 .hwcg_reg = 0x45014, 1312 .hwcg_bit = 1, 1313 .clkr = { 1314 .enable_reg = 0x45014, 1315 .enable_mask = BIT(0), 1316 .hw.init = &(struct clk_init_data){ 1317 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1318 .ops = &clk_branch2_ops, 1319 }, 1320 }, 1321 }; 1322 1323 static struct clk_branch gcc_npu_axi_clk = { 1324 .halt_reg = 0x4c008, 1325 .halt_check = BRANCH_VOTED, 1326 .hwcg_reg = 0x4c008, 1327 .hwcg_bit = 1, 1328 .clkr = { 1329 .enable_reg = 0x4c008, 1330 .enable_mask = BIT(0), 1331 .hw.init = &(struct clk_init_data){ 1332 .name = "gcc_npu_axi_clk", 1333 .ops = &clk_branch2_ops, 1334 }, 1335 }, 1336 }; 1337 1338 static struct clk_branch gcc_npu_bwmon_axi_clk = { 1339 .halt_reg = 0x4d004, 1340 .halt_check = BRANCH_HALT_DELAY, 1341 .hwcg_reg = 0x4d004, 1342 .hwcg_bit = 1, 1343 .clkr = { 1344 .enable_reg = 0x4d004, 1345 .enable_mask = BIT(0), 1346 .hw.init = &(struct clk_init_data){ 1347 .name = "gcc_npu_bwmon_axi_clk", 1348 .ops = &clk_branch2_ops, 1349 }, 1350 }, 1351 }; 1352 1353 static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = { 1354 .halt_reg = 0x4d008, 1355 .halt_check = BRANCH_HALT, 1356 .clkr = { 1357 .enable_reg = 0x4d008, 1358 .enable_mask = BIT(0), 1359 .hw.init = &(struct clk_init_data){ 1360 .name = "gcc_npu_bwmon_dma_cfg_ahb_clk", 1361 .ops = &clk_branch2_ops, 1362 }, 1363 }, 1364 }; 1365 1366 static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = { 1367 .halt_reg = 0x4d00c, 1368 .halt_check = BRANCH_HALT, 1369 .clkr = { 1370 .enable_reg = 0x4d00c, 1371 .enable_mask = BIT(0), 1372 .hw.init = &(struct clk_init_data){ 1373 .name = "gcc_npu_bwmon_dsp_cfg_ahb_clk", 1374 .ops = &clk_branch2_ops, 1375 }, 1376 }, 1377 }; 1378 1379 static struct clk_branch gcc_npu_cfg_ahb_clk = { 1380 .halt_reg = 0x4c004, 1381 .halt_check = BRANCH_HALT, 1382 .hwcg_reg = 0x4c004, 1383 .hwcg_bit = 1, 1384 .clkr = { 1385 .enable_reg = 0x4c004, 1386 .enable_mask = BIT(0), 1387 .hw.init = &(struct clk_init_data){ 1388 .name = "gcc_npu_cfg_ahb_clk", 1389 .flags = CLK_IS_CRITICAL, 1390 .ops = &clk_branch2_ops, 1391 }, 1392 }, 1393 }; 1394 1395 static struct clk_branch gcc_npu_dma_clk = { 1396 .halt_reg = 0x4c140, 1397 .halt_check = BRANCH_VOTED, 1398 .hwcg_reg = 0x4c140, 1399 .hwcg_bit = 1, 1400 .clkr = { 1401 .enable_reg = 0x4c140, 1402 .enable_mask = BIT(0), 1403 .hw.init = &(struct clk_init_data){ 1404 .name = "gcc_npu_dma_clk", 1405 .ops = &clk_branch2_ops, 1406 }, 1407 }, 1408 }; 1409 1410 static struct clk_branch gcc_npu_gpll0_clk = { 1411 .halt_check = BRANCH_HALT_DELAY, 1412 .clkr = { 1413 .enable_reg = 0x52008, 1414 .enable_mask = BIT(9), 1415 .hw.init = &(struct clk_init_data){ 1416 .name = "gcc_npu_gpll0_clk", 1417 .parent_hws = (const struct clk_hw*[]){ 1418 &gpll0.clkr.hw, 1419 }, 1420 .num_parents = 1, 1421 .ops = &clk_branch2_ops, 1422 }, 1423 }, 1424 }; 1425 1426 static struct clk_branch gcc_npu_gpll0_div_clk = { 1427 .halt_check = BRANCH_HALT_DELAY, 1428 .clkr = { 1429 .enable_reg = 0x52008, 1430 .enable_mask = BIT(10), 1431 .hw.init = &(struct clk_init_data){ 1432 .name = "gcc_npu_gpll0_div_clk", 1433 .parent_hws = (const struct clk_hw*[]){ 1434 &gcc_npu_pll0_main_div_clk_src.clkr.hw, 1435 }, 1436 .num_parents = 1, 1437 .ops = &clk_branch2_ops, 1438 }, 1439 }, 1440 }; 1441 1442 static struct clk_branch gcc_pdm2_clk = { 1443 .halt_reg = 0x2300c, 1444 .halt_check = BRANCH_HALT, 1445 .clkr = { 1446 .enable_reg = 0x2300c, 1447 .enable_mask = BIT(0), 1448 .hw.init = &(struct clk_init_data){ 1449 .name = "gcc_pdm2_clk", 1450 .parent_hws = (const struct clk_hw*[]){ 1451 &gcc_pdm2_clk_src.clkr.hw, 1452 }, 1453 .num_parents = 1, 1454 .flags = CLK_SET_RATE_PARENT, 1455 .ops = &clk_branch2_ops, 1456 }, 1457 }, 1458 }; 1459 1460 static struct clk_branch gcc_pdm_ahb_clk = { 1461 .halt_reg = 0x23004, 1462 .halt_check = BRANCH_HALT, 1463 .hwcg_reg = 0x23004, 1464 .hwcg_bit = 1, 1465 .clkr = { 1466 .enable_reg = 0x23004, 1467 .enable_mask = BIT(0), 1468 .hw.init = &(struct clk_init_data){ 1469 .name = "gcc_pdm_ahb_clk", 1470 .ops = &clk_branch2_ops, 1471 }, 1472 }, 1473 }; 1474 1475 static struct clk_branch gcc_pdm_xo4_clk = { 1476 .halt_reg = 0x23008, 1477 .halt_check = BRANCH_HALT, 1478 .clkr = { 1479 .enable_reg = 0x23008, 1480 .enable_mask = BIT(0), 1481 .hw.init = &(struct clk_init_data){ 1482 .name = "gcc_pdm_xo4_clk", 1483 .ops = &clk_branch2_ops, 1484 }, 1485 }, 1486 }; 1487 1488 static struct clk_branch gcc_prng_ahb_clk = { 1489 .halt_reg = 0x24004, 1490 .halt_check = BRANCH_HALT_VOTED, 1491 .hwcg_reg = 0x24004, 1492 .hwcg_bit = 1, 1493 .clkr = { 1494 .enable_reg = 0x52000, 1495 .enable_mask = BIT(26), 1496 .hw.init = &(struct clk_init_data){ 1497 .name = "gcc_prng_ahb_clk", 1498 .ops = &clk_branch2_ops, 1499 }, 1500 }, 1501 }; 1502 1503 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 1504 .halt_reg = 0x21014, 1505 .halt_check = BRANCH_HALT_VOTED, 1506 .clkr = { 1507 .enable_reg = 0x52000, 1508 .enable_mask = BIT(9), 1509 .hw.init = &(struct clk_init_data){ 1510 .name = "gcc_qupv3_wrap0_core_2x_clk", 1511 .ops = &clk_branch2_ops, 1512 }, 1513 }, 1514 }; 1515 1516 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 1517 .halt_reg = 0x2100c, 1518 .halt_check = BRANCH_HALT_VOTED, 1519 .clkr = { 1520 .enable_reg = 0x52000, 1521 .enable_mask = BIT(8), 1522 .hw.init = &(struct clk_init_data){ 1523 .name = "gcc_qupv3_wrap0_core_clk", 1524 .ops = &clk_branch2_ops, 1525 }, 1526 }, 1527 }; 1528 1529 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 1530 .halt_reg = 0x21144, 1531 .halt_check = BRANCH_HALT_VOTED, 1532 .clkr = { 1533 .enable_reg = 0x52000, 1534 .enable_mask = BIT(10), 1535 .hw.init = &(struct clk_init_data){ 1536 .name = "gcc_qupv3_wrap0_s0_clk", 1537 .parent_hws = (const struct clk_hw*[]){ 1538 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 1539 }, 1540 .num_parents = 1, 1541 .flags = CLK_SET_RATE_PARENT, 1542 .ops = &clk_branch2_ops, 1543 }, 1544 }, 1545 }; 1546 1547 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 1548 .halt_reg = 0x21274, 1549 .halt_check = BRANCH_HALT_VOTED, 1550 .clkr = { 1551 .enable_reg = 0x52000, 1552 .enable_mask = BIT(11), 1553 .hw.init = &(struct clk_init_data){ 1554 .name = "gcc_qupv3_wrap0_s1_clk", 1555 .parent_hws = (const struct clk_hw*[]){ 1556 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 1557 }, 1558 .num_parents = 1, 1559 .flags = CLK_SET_RATE_PARENT, 1560 .ops = &clk_branch2_ops, 1561 }, 1562 }, 1563 }; 1564 1565 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 1566 .halt_reg = 0x213a4, 1567 .halt_check = BRANCH_HALT_VOTED, 1568 .clkr = { 1569 .enable_reg = 0x52000, 1570 .enable_mask = BIT(12), 1571 .hw.init = &(struct clk_init_data){ 1572 .name = "gcc_qupv3_wrap0_s2_clk", 1573 .parent_hws = (const struct clk_hw*[]){ 1574 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 1575 }, 1576 .num_parents = 1, 1577 .flags = CLK_SET_RATE_PARENT, 1578 .ops = &clk_branch2_ops, 1579 }, 1580 }, 1581 }; 1582 1583 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 1584 .halt_reg = 0x214d4, 1585 .halt_check = BRANCH_HALT_VOTED, 1586 .clkr = { 1587 .enable_reg = 0x52000, 1588 .enable_mask = BIT(13), 1589 .hw.init = &(struct clk_init_data){ 1590 .name = "gcc_qupv3_wrap0_s3_clk", 1591 .parent_hws = (const struct clk_hw*[]){ 1592 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 1593 }, 1594 .num_parents = 1, 1595 .flags = CLK_SET_RATE_PARENT, 1596 .ops = &clk_branch2_ops, 1597 }, 1598 }, 1599 }; 1600 1601 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 1602 .halt_reg = 0x21604, 1603 .halt_check = BRANCH_HALT_VOTED, 1604 .clkr = { 1605 .enable_reg = 0x52000, 1606 .enable_mask = BIT(14), 1607 .hw.init = &(struct clk_init_data){ 1608 .name = "gcc_qupv3_wrap0_s4_clk", 1609 .parent_hws = (const struct clk_hw*[]){ 1610 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 1611 }, 1612 .num_parents = 1, 1613 .flags = CLK_SET_RATE_PARENT, 1614 .ops = &clk_branch2_ops, 1615 }, 1616 }, 1617 }; 1618 1619 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 1620 .halt_reg = 0x21734, 1621 .halt_check = BRANCH_HALT_VOTED, 1622 .clkr = { 1623 .enable_reg = 0x52000, 1624 .enable_mask = BIT(15), 1625 .hw.init = &(struct clk_init_data){ 1626 .name = "gcc_qupv3_wrap0_s5_clk", 1627 .parent_hws = (const struct clk_hw*[]){ 1628 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 1629 }, 1630 .num_parents = 1, 1631 .flags = CLK_SET_RATE_PARENT, 1632 .ops = &clk_branch2_ops, 1633 }, 1634 }, 1635 }; 1636 1637 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 1638 .halt_reg = 0x22004, 1639 .halt_check = BRANCH_HALT_VOTED, 1640 .clkr = { 1641 .enable_reg = 0x52000, 1642 .enable_mask = BIT(16), 1643 .hw.init = &(struct clk_init_data){ 1644 .name = "gcc_qupv3_wrap1_core_2x_clk", 1645 .ops = &clk_branch2_ops, 1646 }, 1647 }, 1648 }; 1649 1650 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 1651 .halt_reg = 0x22008, 1652 .halt_check = BRANCH_HALT_VOTED, 1653 .clkr = { 1654 .enable_reg = 0x52000, 1655 .enable_mask = BIT(17), 1656 .hw.init = &(struct clk_init_data){ 1657 .name = "gcc_qupv3_wrap1_core_clk", 1658 .ops = &clk_branch2_ops, 1659 }, 1660 }, 1661 }; 1662 1663 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 1664 .halt_reg = 0x22014, 1665 .halt_check = BRANCH_HALT_VOTED, 1666 .clkr = { 1667 .enable_reg = 0x52000, 1668 .enable_mask = BIT(20), 1669 .hw.init = &(struct clk_init_data){ 1670 .name = "gcc_qupv3_wrap1_s0_clk", 1671 .parent_hws = (const struct clk_hw*[]){ 1672 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 1673 }, 1674 .num_parents = 1, 1675 .flags = CLK_SET_RATE_PARENT, 1676 .ops = &clk_branch2_ops, 1677 }, 1678 }, 1679 }; 1680 1681 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 1682 .halt_reg = 0x22144, 1683 .halt_check = BRANCH_HALT_VOTED, 1684 .clkr = { 1685 .enable_reg = 0x52000, 1686 .enable_mask = BIT(21), 1687 .hw.init = &(struct clk_init_data){ 1688 .name = "gcc_qupv3_wrap1_s1_clk", 1689 .parent_hws = (const struct clk_hw*[]){ 1690 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 1691 }, 1692 .num_parents = 1, 1693 .flags = CLK_SET_RATE_PARENT, 1694 .ops = &clk_branch2_ops, 1695 }, 1696 }, 1697 }; 1698 1699 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 1700 .halt_reg = 0x22274, 1701 .halt_check = BRANCH_HALT_VOTED, 1702 .clkr = { 1703 .enable_reg = 0x52000, 1704 .enable_mask = BIT(22), 1705 .hw.init = &(struct clk_init_data){ 1706 .name = "gcc_qupv3_wrap1_s2_clk", 1707 .parent_hws = (const struct clk_hw*[]){ 1708 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 1709 }, 1710 .num_parents = 1, 1711 .flags = CLK_SET_RATE_PARENT, 1712 .ops = &clk_branch2_ops, 1713 }, 1714 }, 1715 }; 1716 1717 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 1718 .halt_reg = 0x223a4, 1719 .halt_check = BRANCH_HALT_VOTED, 1720 .clkr = { 1721 .enable_reg = 0x52000, 1722 .enable_mask = BIT(23), 1723 .hw.init = &(struct clk_init_data){ 1724 .name = "gcc_qupv3_wrap1_s3_clk", 1725 .parent_hws = (const struct clk_hw*[]){ 1726 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 1727 }, 1728 .num_parents = 1, 1729 .flags = CLK_SET_RATE_PARENT, 1730 .ops = &clk_branch2_ops, 1731 }, 1732 }, 1733 }; 1734 1735 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 1736 .halt_reg = 0x224d4, 1737 .halt_check = BRANCH_HALT_VOTED, 1738 .clkr = { 1739 .enable_reg = 0x52000, 1740 .enable_mask = BIT(24), 1741 .hw.init = &(struct clk_init_data){ 1742 .name = "gcc_qupv3_wrap1_s4_clk", 1743 .parent_hws = (const struct clk_hw*[]){ 1744 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 1745 }, 1746 .num_parents = 1, 1747 .flags = CLK_SET_RATE_PARENT, 1748 .ops = &clk_branch2_ops, 1749 }, 1750 }, 1751 }; 1752 1753 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 1754 .halt_reg = 0x22604, 1755 .halt_check = BRANCH_HALT_VOTED, 1756 .clkr = { 1757 .enable_reg = 0x52000, 1758 .enable_mask = BIT(25), 1759 .hw.init = &(struct clk_init_data){ 1760 .name = "gcc_qupv3_wrap1_s5_clk", 1761 .parent_hws = (const struct clk_hw*[]){ 1762 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 1763 }, 1764 .num_parents = 1, 1765 .flags = CLK_SET_RATE_PARENT, 1766 .ops = &clk_branch2_ops, 1767 }, 1768 }, 1769 }; 1770 1771 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 1772 .halt_reg = 0x21004, 1773 .halt_check = BRANCH_HALT_VOTED, 1774 .hwcg_reg = 0x21004, 1775 .hwcg_bit = 1, 1776 .clkr = { 1777 .enable_reg = 0x52000, 1778 .enable_mask = BIT(6), 1779 .hw.init = &(struct clk_init_data){ 1780 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 1781 .ops = &clk_branch2_ops, 1782 }, 1783 }, 1784 }; 1785 1786 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 1787 .halt_reg = 0x21008, 1788 .halt_check = BRANCH_HALT_VOTED, 1789 .hwcg_reg = 0x21008, 1790 .hwcg_bit = 1, 1791 .clkr = { 1792 .enable_reg = 0x52000, 1793 .enable_mask = BIT(7), 1794 .hw.init = &(struct clk_init_data){ 1795 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 1796 .ops = &clk_branch2_ops, 1797 }, 1798 }, 1799 }; 1800 1801 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 1802 .halt_reg = 0x2200c, 1803 .halt_check = BRANCH_HALT_VOTED, 1804 .hwcg_reg = 0x2200c, 1805 .hwcg_bit = 1, 1806 .clkr = { 1807 .enable_reg = 0x52000, 1808 .enable_mask = BIT(18), 1809 .hw.init = &(struct clk_init_data){ 1810 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 1811 .ops = &clk_branch2_ops, 1812 }, 1813 }, 1814 }; 1815 1816 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 1817 .halt_reg = 0x22010, 1818 .halt_check = BRANCH_HALT_VOTED, 1819 .hwcg_reg = 0x22010, 1820 .hwcg_bit = 1, 1821 .clkr = { 1822 .enable_reg = 0x52000, 1823 .enable_mask = BIT(19), 1824 .hw.init = &(struct clk_init_data){ 1825 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 1826 .ops = &clk_branch2_ops, 1827 }, 1828 }, 1829 }; 1830 1831 static struct clk_branch gcc_sdcc1_ahb_clk = { 1832 .halt_reg = 0x4b004, 1833 .halt_check = BRANCH_HALT, 1834 .clkr = { 1835 .enable_reg = 0x4b004, 1836 .enable_mask = BIT(0), 1837 .hw.init = &(struct clk_init_data){ 1838 .name = "gcc_sdcc1_ahb_clk", 1839 .ops = &clk_branch2_ops, 1840 }, 1841 }, 1842 }; 1843 1844 static struct clk_branch gcc_sdcc1_apps_clk = { 1845 .halt_reg = 0x4b008, 1846 .halt_check = BRANCH_HALT, 1847 .clkr = { 1848 .enable_reg = 0x4b008, 1849 .enable_mask = BIT(0), 1850 .hw.init = &(struct clk_init_data){ 1851 .name = "gcc_sdcc1_apps_clk", 1852 .parent_hws = (const struct clk_hw*[]){ 1853 &gcc_sdcc1_apps_clk_src.clkr.hw, 1854 }, 1855 .num_parents = 1, 1856 .flags = CLK_SET_RATE_PARENT, 1857 .ops = &clk_branch2_ops, 1858 }, 1859 }, 1860 }; 1861 1862 static struct clk_branch gcc_sdcc1_ice_core_clk = { 1863 .halt_reg = 0x4b03c, 1864 .halt_check = BRANCH_HALT, 1865 .hwcg_reg = 0x4b03c, 1866 .hwcg_bit = 1, 1867 .clkr = { 1868 .enable_reg = 0x4b03c, 1869 .enable_mask = BIT(0), 1870 .hw.init = &(struct clk_init_data){ 1871 .name = "gcc_sdcc1_ice_core_clk", 1872 .parent_hws = (const struct clk_hw*[]){ 1873 &gcc_sdcc1_ice_core_clk_src.clkr.hw, 1874 }, 1875 .num_parents = 1, 1876 .flags = CLK_SET_RATE_PARENT, 1877 .ops = &clk_branch2_ops, 1878 }, 1879 }, 1880 }; 1881 1882 static struct clk_branch gcc_sdcc2_ahb_clk = { 1883 .halt_reg = 0x20008, 1884 .halt_check = BRANCH_HALT, 1885 .clkr = { 1886 .enable_reg = 0x20008, 1887 .enable_mask = BIT(0), 1888 .hw.init = &(struct clk_init_data){ 1889 .name = "gcc_sdcc2_ahb_clk", 1890 .ops = &clk_branch2_ops, 1891 }, 1892 }, 1893 }; 1894 1895 static struct clk_branch gcc_sdcc2_apps_clk = { 1896 .halt_reg = 0x20004, 1897 .halt_check = BRANCH_HALT, 1898 .clkr = { 1899 .enable_reg = 0x20004, 1900 .enable_mask = BIT(0), 1901 .hw.init = &(struct clk_init_data){ 1902 .name = "gcc_sdcc2_apps_clk", 1903 .parent_hws = (const struct clk_hw*[]){ 1904 &gcc_sdcc2_apps_clk_src.clkr.hw, 1905 }, 1906 .num_parents = 1, 1907 .flags = CLK_SET_RATE_PARENT, 1908 .ops = &clk_branch2_ops, 1909 }, 1910 }, 1911 }; 1912 1913 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 1914 .halt_reg = 0x10140, 1915 .halt_check = BRANCH_HALT_VOTED, 1916 .hwcg_reg = 0x10140, 1917 .hwcg_bit = 1, 1918 .clkr = { 1919 .enable_reg = 0x52000, 1920 .enable_mask = BIT(0), 1921 .hw.init = &(struct clk_init_data){ 1922 .name = "gcc_sys_noc_cpuss_ahb_clk", 1923 .parent_hws = (const struct clk_hw*[]){ 1924 &gcc_cpuss_ahb_clk_src.clkr.hw, 1925 }, 1926 .num_parents = 1, 1927 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 1928 .ops = &clk_branch2_ops, 1929 }, 1930 }, 1931 }; 1932 1933 static struct clk_branch gcc_ufs_mem_clkref_clk = { 1934 .halt_reg = 0x8c000, 1935 .halt_check = BRANCH_HALT, 1936 .clkr = { 1937 .enable_reg = 0x8c000, 1938 .enable_mask = BIT(0), 1939 .hw.init = &(struct clk_init_data){ 1940 .name = "gcc_ufs_mem_clkref_clk", 1941 .ops = &clk_branch2_ops, 1942 }, 1943 }, 1944 }; 1945 1946 static struct clk_branch gcc_ufs_phy_ahb_clk = { 1947 .halt_reg = 0x3a00c, 1948 .halt_check = BRANCH_HALT, 1949 .hwcg_reg = 0x3a00c, 1950 .hwcg_bit = 1, 1951 .clkr = { 1952 .enable_reg = 0x3a00c, 1953 .enable_mask = BIT(0), 1954 .hw.init = &(struct clk_init_data){ 1955 .name = "gcc_ufs_phy_ahb_clk", 1956 .ops = &clk_branch2_ops, 1957 }, 1958 }, 1959 }; 1960 1961 static struct clk_branch gcc_ufs_phy_axi_clk = { 1962 .halt_reg = 0x3a034, 1963 .halt_check = BRANCH_HALT, 1964 .hwcg_reg = 0x3a034, 1965 .hwcg_bit = 1, 1966 .clkr = { 1967 .enable_reg = 0x3a034, 1968 .enable_mask = BIT(0), 1969 .hw.init = &(struct clk_init_data){ 1970 .name = "gcc_ufs_phy_axi_clk", 1971 .parent_hws = (const struct clk_hw*[]){ 1972 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1973 }, 1974 .num_parents = 1, 1975 .flags = CLK_SET_RATE_PARENT, 1976 .ops = &clk_branch2_ops, 1977 }, 1978 }, 1979 }; 1980 1981 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 1982 .halt_reg = 0x3a0a4, 1983 .halt_check = BRANCH_HALT, 1984 .hwcg_reg = 0x3a0a4, 1985 .hwcg_bit = 1, 1986 .clkr = { 1987 .enable_reg = 0x3a0a4, 1988 .enable_mask = BIT(0), 1989 .hw.init = &(struct clk_init_data){ 1990 .name = "gcc_ufs_phy_ice_core_clk", 1991 .parent_hws = (const struct clk_hw*[]){ 1992 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 1993 }, 1994 .num_parents = 1, 1995 .flags = CLK_SET_RATE_PARENT, 1996 .ops = &clk_branch2_ops, 1997 }, 1998 }, 1999 }; 2000 2001 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { 2002 .halt_reg = 0x3a0a4, 2003 .halt_check = BRANCH_HALT, 2004 .hwcg_reg = 0x3a0a4, 2005 .hwcg_bit = 1, 2006 .clkr = { 2007 .enable_reg = 0x3a0a4, 2008 .enable_mask = BIT(1), 2009 .hw.init = &(struct clk_init_data){ 2010 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", 2011 .parent_hws = (const struct clk_hw*[]){ 2012 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2013 }, 2014 .num_parents = 1, 2015 .flags = CLK_SET_RATE_PARENT, 2016 .ops = &clk_branch2_ops, 2017 }, 2018 }, 2019 }; 2020 2021 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2022 .halt_reg = 0x3a0ac, 2023 .halt_check = BRANCH_HALT, 2024 .hwcg_reg = 0x3a0ac, 2025 .hwcg_bit = 1, 2026 .clkr = { 2027 .enable_reg = 0x3a0ac, 2028 .enable_mask = BIT(0), 2029 .hw.init = &(struct clk_init_data){ 2030 .name = "gcc_ufs_phy_phy_aux_clk", 2031 .parent_hws = (const struct clk_hw*[]){ 2032 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2033 }, 2034 .num_parents = 1, 2035 .flags = CLK_SET_RATE_PARENT, 2036 .ops = &clk_branch2_ops, 2037 }, 2038 }, 2039 }; 2040 2041 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { 2042 .halt_reg = 0x3a0ac, 2043 .halt_check = BRANCH_HALT, 2044 .hwcg_reg = 0x3a0ac, 2045 .hwcg_bit = 1, 2046 .clkr = { 2047 .enable_reg = 0x3a0ac, 2048 .enable_mask = BIT(1), 2049 .hw.init = &(struct clk_init_data){ 2050 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", 2051 .parent_hws = (const struct clk_hw*[]){ 2052 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2053 }, 2054 .num_parents = 1, 2055 .flags = CLK_SET_RATE_PARENT, 2056 .ops = &clk_branch2_ops, 2057 }, 2058 }, 2059 }; 2060 2061 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2062 .halt_reg = 0x3a014, 2063 .halt_check = BRANCH_HALT_SKIP, 2064 .clkr = { 2065 .enable_reg = 0x3a014, 2066 .enable_mask = BIT(0), 2067 .hw.init = &(struct clk_init_data){ 2068 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2069 .ops = &clk_branch2_ops, 2070 }, 2071 }, 2072 }; 2073 2074 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2075 .halt_reg = 0x3a018, 2076 .halt_check = BRANCH_HALT_SKIP, 2077 .clkr = { 2078 .enable_reg = 0x3a018, 2079 .enable_mask = BIT(0), 2080 .hw.init = &(struct clk_init_data){ 2081 .name = "gcc_ufs_phy_rx_symbol_1_clk", 2082 .ops = &clk_branch2_ops, 2083 }, 2084 }, 2085 }; 2086 2087 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2088 .halt_reg = 0x3a010, 2089 .halt_check = BRANCH_HALT_SKIP, 2090 .clkr = { 2091 .enable_reg = 0x3a010, 2092 .enable_mask = BIT(0), 2093 .hw.init = &(struct clk_init_data){ 2094 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2095 .ops = &clk_branch2_ops, 2096 }, 2097 }, 2098 }; 2099 2100 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2101 .halt_reg = 0x3a09c, 2102 .halt_check = BRANCH_HALT, 2103 .hwcg_reg = 0x3a09c, 2104 .hwcg_bit = 1, 2105 .clkr = { 2106 .enable_reg = 0x3a09c, 2107 .enable_mask = BIT(0), 2108 .hw.init = &(struct clk_init_data){ 2109 .name = "gcc_ufs_phy_unipro_core_clk", 2110 .parent_hws = (const struct clk_hw*[]){ 2111 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2112 }, 2113 .num_parents = 1, 2114 .flags = CLK_SET_RATE_PARENT, 2115 .ops = &clk_branch2_ops, 2116 }, 2117 }, 2118 }; 2119 2120 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { 2121 .halt_reg = 0x3a09c, 2122 .halt_check = BRANCH_HALT, 2123 .hwcg_reg = 0x3a09c, 2124 .hwcg_bit = 1, 2125 .clkr = { 2126 .enable_reg = 0x3a09c, 2127 .enable_mask = BIT(1), 2128 .hw.init = &(struct clk_init_data){ 2129 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", 2130 .parent_hws = (const struct clk_hw*[]){ 2131 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2132 }, 2133 .num_parents = 1, 2134 .flags = CLK_SET_RATE_PARENT, 2135 .ops = &clk_branch2_ops, 2136 }, 2137 }, 2138 }; 2139 2140 static struct clk_branch gcc_usb30_prim_master_clk = { 2141 .halt_reg = 0x1a00c, 2142 .halt_check = BRANCH_HALT, 2143 .clkr = { 2144 .enable_reg = 0x1a00c, 2145 .enable_mask = BIT(0), 2146 .hw.init = &(struct clk_init_data){ 2147 .name = "gcc_usb30_prim_master_clk", 2148 .parent_hws = (const struct clk_hw*[]){ 2149 &gcc_usb30_prim_master_clk_src.clkr.hw, 2150 }, 2151 .num_parents = 1, 2152 .flags = CLK_SET_RATE_PARENT, 2153 .ops = &clk_branch2_ops, 2154 }, 2155 }, 2156 }; 2157 2158 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2159 .halt_reg = 0x1a018, 2160 .halt_check = BRANCH_HALT, 2161 .clkr = { 2162 .enable_reg = 0x1a018, 2163 .enable_mask = BIT(0), 2164 .hw.init = &(struct clk_init_data){ 2165 .name = "gcc_usb30_prim_mock_utmi_clk", 2166 .parent_hws = (const struct clk_hw*[]){ 2167 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 2168 }, 2169 .num_parents = 1, 2170 .flags = CLK_SET_RATE_PARENT, 2171 .ops = &clk_branch2_ops, 2172 }, 2173 }, 2174 }; 2175 2176 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2177 .halt_reg = 0x1a014, 2178 .halt_check = BRANCH_HALT, 2179 .clkr = { 2180 .enable_reg = 0x1a014, 2181 .enable_mask = BIT(0), 2182 .hw.init = &(struct clk_init_data){ 2183 .name = "gcc_usb30_prim_sleep_clk", 2184 .ops = &clk_branch2_ops, 2185 }, 2186 }, 2187 }; 2188 2189 static struct clk_branch gcc_usb3_prim_clkref_clk = { 2190 .halt_reg = 0x8c010, 2191 .halt_check = BRANCH_HALT, 2192 .clkr = { 2193 .enable_reg = 0x8c010, 2194 .enable_mask = BIT(0), 2195 .hw.init = &(struct clk_init_data){ 2196 .name = "gcc_usb3_prim_clkref_clk", 2197 .ops = &clk_branch2_ops, 2198 }, 2199 }, 2200 }; 2201 2202 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2203 .halt_reg = 0x1a050, 2204 .halt_check = BRANCH_HALT, 2205 .clkr = { 2206 .enable_reg = 0x1a050, 2207 .enable_mask = BIT(0), 2208 .hw.init = &(struct clk_init_data){ 2209 .name = "gcc_usb3_prim_phy_aux_clk", 2210 .parent_hws = (const struct clk_hw*[]){ 2211 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2212 }, 2213 .num_parents = 1, 2214 .flags = CLK_SET_RATE_PARENT, 2215 .ops = &clk_branch2_ops, 2216 }, 2217 }, 2218 }; 2219 2220 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2221 .halt_reg = 0x1a054, 2222 .halt_check = BRANCH_HALT, 2223 .clkr = { 2224 .enable_reg = 0x1a054, 2225 .enable_mask = BIT(0), 2226 .hw.init = &(struct clk_init_data){ 2227 .name = "gcc_usb3_prim_phy_com_aux_clk", 2228 .parent_hws = (const struct clk_hw*[]){ 2229 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2230 }, 2231 .num_parents = 1, 2232 .flags = CLK_SET_RATE_PARENT, 2233 .ops = &clk_branch2_ops, 2234 }, 2235 }, 2236 }; 2237 2238 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2239 .halt_reg = 0x1a058, 2240 .halt_check = BRANCH_HALT_SKIP, 2241 .hwcg_reg = 0x1a058, 2242 .hwcg_bit = 1, 2243 .clkr = { 2244 .enable_reg = 0x1a058, 2245 .enable_mask = BIT(0), 2246 .hw.init = &(struct clk_init_data){ 2247 .name = "gcc_usb3_prim_phy_pipe_clk", 2248 .ops = &clk_branch2_ops, 2249 }, 2250 }, 2251 }; 2252 2253 static struct clk_branch gcc_video_ahb_clk = { 2254 .halt_reg = 0x17004, 2255 .halt_check = BRANCH_HALT, 2256 .hwcg_reg = 0x17004, 2257 .hwcg_bit = 1, 2258 .clkr = { 2259 .enable_reg = 0x17004, 2260 .enable_mask = BIT(0), 2261 .hw.init = &(struct clk_init_data){ 2262 .name = "gcc_video_ahb_clk", 2263 .flags = CLK_IS_CRITICAL, 2264 .ops = &clk_branch2_ops, 2265 }, 2266 }, 2267 }; 2268 2269 static struct clk_branch gcc_video_axi_clk = { 2270 .halt_reg = 0x17014, 2271 .halt_check = BRANCH_HALT, 2272 .hwcg_reg = 0x17014, 2273 .hwcg_bit = 1, 2274 .clkr = { 2275 .enable_reg = 0x17014, 2276 .enable_mask = BIT(0), 2277 .hw.init = &(struct clk_init_data){ 2278 .name = "gcc_video_axi_clk", 2279 .ops = &clk_branch2_ops, 2280 }, 2281 }, 2282 }; 2283 2284 static struct clk_branch gcc_video_throttle_axi_clk = { 2285 .halt_reg = 0x17020, 2286 .halt_check = BRANCH_HALT, 2287 .hwcg_reg = 0x17020, 2288 .hwcg_bit = 1, 2289 .clkr = { 2290 .enable_reg = 0x17020, 2291 .enable_mask = BIT(0), 2292 .hw.init = &(struct clk_init_data){ 2293 .name = "gcc_video_throttle_axi_clk", 2294 .ops = &clk_branch2_ops, 2295 }, 2296 }, 2297 }; 2298 2299 static struct clk_branch gcc_video_xo_clk = { 2300 .halt_reg = 0x1702c, 2301 .halt_check = BRANCH_HALT, 2302 .clkr = { 2303 .enable_reg = 0x1702c, 2304 .enable_mask = BIT(0), 2305 .hw.init = &(struct clk_init_data){ 2306 .name = "gcc_video_xo_clk", 2307 .flags = CLK_IS_CRITICAL, 2308 .ops = &clk_branch2_ops, 2309 }, 2310 }, 2311 }; 2312 2313 static struct gdsc usb30_prim_gdsc = { 2314 .gdscr = 0x1a004, 2315 .pd = { 2316 .name = "usb30_prim_gdsc", 2317 }, 2318 .pwrsts = PWRSTS_OFF_ON, 2319 }; 2320 2321 static struct gdsc ufs_phy_gdsc = { 2322 .gdscr = 0x3a004, 2323 .pd = { 2324 .name = "ufs_phy_gdsc", 2325 }, 2326 .pwrsts = PWRSTS_OFF_ON, 2327 }; 2328 2329 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { 2330 .gdscr = 0xb7040, 2331 .pd = { 2332 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", 2333 }, 2334 .pwrsts = PWRSTS_OFF_ON, 2335 .flags = VOTABLE, 2336 }; 2337 2338 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = { 2339 .gdscr = 0xb7044, 2340 .pd = { 2341 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", 2342 }, 2343 .pwrsts = PWRSTS_OFF_ON, 2344 .flags = VOTABLE, 2345 }; 2346 2347 static struct clk_regmap *gcc_sm6350_clocks[] = { 2348 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 2349 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 2350 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2351 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 2352 [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr, 2353 [GCC_CAMERA_THROTTLE_NRT_AXI_CLK] = 2354 &gcc_camera_throttle_nrt_axi_clk.clkr, 2355 [GCC_CAMERA_THROTTLE_RT_AXI_CLK] = &gcc_camera_throttle_rt_axi_clk.clkr, 2356 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 2357 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, 2358 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, 2359 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, 2360 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2361 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, 2362 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, 2363 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, 2364 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, 2365 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 2366 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, 2367 [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr, 2368 [GCC_DISP_CC_SLEEP_CLK] = &gcc_disp_cc_sleep_clk.clkr, 2369 [GCC_DISP_CC_XO_CLK] = &gcc_disp_cc_xo_clk.clkr, 2370 [GCC_DISP_GPLL0_CLK] = &gcc_disp_gpll0_clk.clkr, 2371 [GCC_DISP_THROTTLE_AXI_CLK] = &gcc_disp_throttle_axi_clk.clkr, 2372 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 2373 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2374 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2375 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2376 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2377 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2378 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2379 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 2380 [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr, 2381 [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr, 2382 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 2383 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 2384 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, 2385 [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr, 2386 [GCC_NPU_BWMON_DMA_CFG_AHB_CLK] = &gcc_npu_bwmon_dma_cfg_ahb_clk.clkr, 2387 [GCC_NPU_BWMON_DSP_CFG_AHB_CLK] = &gcc_npu_bwmon_dsp_cfg_ahb_clk.clkr, 2388 [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr, 2389 [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr, 2390 [GCC_NPU_GPLL0_CLK] = &gcc_npu_gpll0_clk.clkr, 2391 [GCC_NPU_GPLL0_DIV_CLK] = &gcc_npu_gpll0_div_clk.clkr, 2392 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2393 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 2394 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2395 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2396 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2397 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 2398 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 2399 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 2400 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 2401 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 2402 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 2403 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 2404 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 2405 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 2406 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 2407 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 2408 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 2409 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 2410 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 2411 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 2412 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 2413 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 2414 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 2415 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 2416 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 2417 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 2418 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 2419 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 2420 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 2421 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 2422 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 2423 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 2424 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 2425 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 2426 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 2427 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 2428 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 2429 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2430 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2431 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 2432 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 2433 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 2434 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2435 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2436 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 2437 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 2438 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, 2439 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 2440 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 2441 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 2442 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 2443 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 2444 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 2445 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 2446 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 2447 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 2448 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 2449 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 2450 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 2451 &gcc_ufs_phy_unipro_core_clk_src.clkr, 2452 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 2453 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 2454 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 2455 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 2456 &gcc_usb30_prim_mock_utmi_clk_src.clkr, 2457 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 2458 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 2459 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 2460 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 2461 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 2462 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 2463 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 2464 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr, 2465 [GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr, 2466 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 2467 [GPLL0] = &gpll0.clkr, 2468 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 2469 [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr, 2470 [GPLL6] = &gpll6.clkr, 2471 [GPLL6_OUT_EVEN] = &gpll6_out_even.clkr, 2472 [GPLL7] = &gpll7.clkr, 2473 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, 2474 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, 2475 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = 2476 &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, 2477 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = 2478 &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, 2479 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = 2480 &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, 2481 [GCC_GPU_GPLL0_MAIN_DIV_CLK_SRC] = &gcc_gpu_gpll0_main_div_clk_src.clkr, 2482 [GCC_NPU_PLL0_MAIN_DIV_CLK_SRC] = &gcc_npu_pll0_main_div_clk_src.clkr, 2483 }; 2484 2485 static struct gdsc *gcc_sm6350_gdscs[] = { 2486 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 2487 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 2488 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, 2489 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, 2490 }; 2491 2492 static const struct qcom_reset_map gcc_sm6350_resets[] = { 2493 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1d000 }, 2494 [GCC_QUSB2PHY_SEC_BCR] = { 0x1e000 }, 2495 [GCC_SDCC1_BCR] = { 0x4b000 }, 2496 [GCC_SDCC2_BCR] = { 0x20000 }, 2497 [GCC_UFS_PHY_BCR] = { 0x3a000 }, 2498 [GCC_USB30_PRIM_BCR] = { 0x1a000 }, 2499 [GCC_USB3_PHY_PRIM_BCR] = { 0x1c000 }, 2500 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1c008 }, 2501 }; 2502 2503 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 2504 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 2505 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 2506 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 2507 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 2508 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 2509 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 2510 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 2511 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 2512 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 2513 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 2514 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 2515 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 2516 }; 2517 2518 static const struct regmap_config gcc_sm6350_regmap_config = { 2519 .reg_bits = 32, 2520 .reg_stride = 4, 2521 .val_bits = 32, 2522 .max_register = 0xbf030, 2523 .fast_io = true, 2524 }; 2525 2526 static const struct qcom_cc_desc gcc_sm6350_desc = { 2527 .config = &gcc_sm6350_regmap_config, 2528 .clks = gcc_sm6350_clocks, 2529 .num_clks = ARRAY_SIZE(gcc_sm6350_clocks), 2530 .resets = gcc_sm6350_resets, 2531 .num_resets = ARRAY_SIZE(gcc_sm6350_resets), 2532 .gdscs = gcc_sm6350_gdscs, 2533 .num_gdscs = ARRAY_SIZE(gcc_sm6350_gdscs), 2534 }; 2535 2536 static const struct of_device_id gcc_sm6350_match_table[] = { 2537 { .compatible = "qcom,gcc-sm6350" }, 2538 { } 2539 }; 2540 MODULE_DEVICE_TABLE(of, gcc_sm6350_match_table); 2541 2542 static int gcc_sm6350_probe(struct platform_device *pdev) 2543 { 2544 struct regmap *regmap; 2545 int ret; 2546 2547 regmap = qcom_cc_map(pdev, &gcc_sm6350_desc); 2548 if (IS_ERR(regmap)) 2549 return PTR_ERR(regmap); 2550 2551 /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ 2552 regmap_update_bits(regmap, 0x4cf00, 0x3, 0x3); 2553 regmap_update_bits(regmap, 0x45f00, 0x3, 0x3); 2554 2555 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 2556 ARRAY_SIZE(gcc_dfs_clocks)); 2557 if (ret) 2558 return ret; 2559 2560 return qcom_cc_really_probe(pdev, &gcc_sm6350_desc, regmap);; 2561 } 2562 2563 static struct platform_driver gcc_sm6350_driver = { 2564 .probe = gcc_sm6350_probe, 2565 .driver = { 2566 .name = "gcc-sm6350", 2567 .of_match_table = gcc_sm6350_match_table, 2568 }, 2569 }; 2570 2571 static int __init gcc_sm6350_init(void) 2572 { 2573 return platform_driver_register(&gcc_sm6350_driver); 2574 } 2575 core_initcall(gcc_sm6350_init); 2576 2577 static void __exit gcc_sm6350_exit(void) 2578 { 2579 platform_driver_unregister(&gcc_sm6350_driver); 2580 } 2581 module_exit(gcc_sm6350_exit); 2582 2583 MODULE_DESCRIPTION("QTI GCC SM6350 Driver"); 2584 MODULE_LICENSE("GPL v2"); 2585