1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/err.h> 7 #include <linux/kernel.h> 8 #include <linux/module.h> 9 #include <linux/of_device.h> 10 #include <linux/clk-provider.h> 11 #include <linux/regmap.h> 12 #include <linux/reset-controller.h> 13 14 #include <dt-bindings/clock/qcom,gcc-sm6115.h> 15 16 #include "clk-alpha-pll.h" 17 #include "clk-branch.h" 18 #include "clk-pll.h" 19 #include "clk-rcg.h" 20 #include "clk-regmap.h" 21 #include "clk-regmap-divider.h" 22 #include "common.h" 23 #include "gdsc.h" 24 #include "reset.h" 25 26 enum { 27 P_BI_TCXO, 28 P_GPLL0_OUT_AUX2, 29 P_GPLL0_OUT_EARLY, 30 P_GPLL10_OUT_MAIN, 31 P_GPLL11_OUT_MAIN, 32 P_GPLL3_OUT_EARLY, 33 P_GPLL4_OUT_MAIN, 34 P_GPLL6_OUT_EARLY, 35 P_GPLL6_OUT_MAIN, 36 P_GPLL7_OUT_MAIN, 37 P_GPLL8_OUT_EARLY, 38 P_GPLL8_OUT_MAIN, 39 P_GPLL9_OUT_EARLY, 40 P_GPLL9_OUT_MAIN, 41 P_SLEEP_CLK, 42 }; 43 44 static struct pll_vco default_vco[] = { 45 { 500000000, 1000000000, 2 }, 46 }; 47 48 static struct pll_vco gpll9_vco[] = { 49 { 500000000, 1250000000, 0 }, 50 }; 51 52 static struct pll_vco gpll10_vco[] = { 53 { 750000000, 1500000000, 1 }, 54 }; 55 56 static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = { 57 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 58 [PLL_OFF_L_VAL] = 0x04, 59 [PLL_OFF_ALPHA_VAL] = 0x08, 60 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 61 [PLL_OFF_TEST_CTL] = 0x10, 62 [PLL_OFF_TEST_CTL_U] = 0x14, 63 [PLL_OFF_USER_CTL] = 0x18, 64 [PLL_OFF_USER_CTL_U] = 0x1c, 65 [PLL_OFF_CONFIG_CTL] = 0x20, 66 [PLL_OFF_STATUS] = 0x24, 67 }, 68 }; 69 70 static struct clk_alpha_pll gpll0 = { 71 .offset = 0x0, 72 .vco_table = default_vco, 73 .num_vco = ARRAY_SIZE(default_vco), 74 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 75 .clkr = { 76 .enable_reg = 0x79000, 77 .enable_mask = BIT(0), 78 .hw.init = &(struct clk_init_data){ 79 .name = "gpll0", 80 .parent_data = &(const struct clk_parent_data){ 81 .fw_name = "bi_tcxo", 82 }, 83 .num_parents = 1, 84 .ops = &clk_alpha_pll_ops, 85 }, 86 }, 87 }; 88 89 static const struct clk_div_table post_div_table_gpll0_out_aux2[] = { 90 { 0x1, 2 }, 91 { } 92 }; 93 94 static struct clk_alpha_pll_postdiv gpll0_out_aux2 = { 95 .offset = 0x0, 96 .post_div_shift = 8, 97 .post_div_table = post_div_table_gpll0_out_aux2, 98 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2), 99 .width = 4, 100 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 101 .clkr.hw.init = &(struct clk_init_data){ 102 .name = "gpll0_out_aux2", 103 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 104 .num_parents = 1, 105 .ops = &clk_alpha_pll_postdiv_ro_ops, 106 }, 107 }; 108 109 /* listed as BRAMMO, but it doesn't really match */ 110 static const u8 clk_gpll9_regs[PLL_OFF_MAX_REGS] = { 111 [PLL_OFF_L_VAL] = 0x04, 112 [PLL_OFF_ALPHA_VAL] = 0x08, 113 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 114 [PLL_OFF_TEST_CTL] = 0x10, 115 [PLL_OFF_TEST_CTL_U] = 0x14, 116 [PLL_OFF_USER_CTL] = 0x18, 117 [PLL_OFF_CONFIG_CTL] = 0x1C, 118 [PLL_OFF_STATUS] = 0x20, 119 }; 120 121 static const struct clk_div_table post_div_table_gpll0_out_main[] = { 122 { 0x0, 1 }, 123 { } 124 }; 125 126 static struct clk_alpha_pll_postdiv gpll0_out_main = { 127 .offset = 0x0, 128 .post_div_shift = 8, 129 .post_div_table = post_div_table_gpll0_out_main, 130 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_main), 131 .width = 4, 132 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 133 .clkr.hw.init = &(struct clk_init_data){ 134 .name = "gpll0_out_main", 135 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 136 .num_parents = 1, 137 .ops = &clk_alpha_pll_postdiv_ro_ops, 138 }, 139 }; 140 141 /* 1152MHz configuration */ 142 static const struct alpha_pll_config gpll10_config = { 143 .l = 0x3c, 144 .vco_val = 0x1 << 20, 145 .vco_mask = GENMASK(21, 20), 146 .main_output_mask = BIT(0), 147 .config_ctl_val = 0x4001055b, 148 }; 149 150 static struct clk_alpha_pll gpll10 = { 151 .offset = 0xa000, 152 .vco_table = gpll10_vco, 153 .num_vco = ARRAY_SIZE(gpll10_vco), 154 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 155 .clkr = { 156 .enable_reg = 0x79000, 157 .enable_mask = BIT(10), 158 .hw.init = &(struct clk_init_data){ 159 .name = "gpll10", 160 .parent_data = &(const struct clk_parent_data){ 161 .fw_name = "bi_tcxo", 162 }, 163 .num_parents = 1, 164 .ops = &clk_alpha_pll_ops, 165 }, 166 }, 167 }; 168 169 static const struct clk_div_table post_div_table_gpll10_out_main[] = { 170 { 0x0, 1 }, 171 { } 172 }; 173 174 static struct clk_alpha_pll_postdiv gpll10_out_main = { 175 .offset = 0xa000, 176 .post_div_shift = 8, 177 .post_div_table = post_div_table_gpll10_out_main, 178 .num_post_div = ARRAY_SIZE(post_div_table_gpll10_out_main), 179 .width = 4, 180 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 181 .clkr.hw.init = &(struct clk_init_data){ 182 .name = "gpll10_out_main", 183 .parent_hws = (const struct clk_hw *[]){ &gpll10.clkr.hw }, 184 .num_parents = 1, 185 .flags = CLK_SET_RATE_PARENT, 186 .ops = &clk_alpha_pll_postdiv_ops, 187 }, 188 }; 189 190 /* 600MHz configuration */ 191 static const struct alpha_pll_config gpll11_config = { 192 .l = 0x1F, 193 .alpha = 0x0, 194 .alpha_hi = 0x40, 195 .alpha_en_mask = BIT(24), 196 .vco_val = 0x2 << 20, 197 .vco_mask = GENMASK(21, 20), 198 .config_ctl_val = 0x4001055b, 199 }; 200 201 static struct clk_alpha_pll gpll11 = { 202 .offset = 0xb000, 203 .vco_table = default_vco, 204 .num_vco = ARRAY_SIZE(default_vco), 205 .flags = SUPPORTS_DYNAMIC_UPDATE, 206 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 207 .clkr = { 208 .enable_reg = 0x79000, 209 .enable_mask = BIT(11), 210 .hw.init = &(struct clk_init_data){ 211 .name = "gpll11", 212 .parent_data = &(const struct clk_parent_data){ 213 .fw_name = "bi_tcxo", 214 }, 215 .num_parents = 1, 216 .ops = &clk_alpha_pll_ops, 217 }, 218 }, 219 }; 220 221 static const struct clk_div_table post_div_table_gpll11_out_main[] = { 222 { 0x0, 1 }, 223 { } 224 }; 225 226 static struct clk_alpha_pll_postdiv gpll11_out_main = { 227 .offset = 0xb000, 228 .post_div_shift = 8, 229 .post_div_table = post_div_table_gpll11_out_main, 230 .num_post_div = ARRAY_SIZE(post_div_table_gpll11_out_main), 231 .width = 4, 232 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 233 .clkr.hw.init = &(struct clk_init_data){ 234 .name = "gpll11_out_main", 235 .parent_hws = (const struct clk_hw *[]){ &gpll11.clkr.hw }, 236 .num_parents = 1, 237 .flags = CLK_SET_RATE_PARENT, 238 .ops = &clk_alpha_pll_postdiv_ops, 239 }, 240 }; 241 242 static struct clk_alpha_pll gpll3 = { 243 .offset = 0x3000, 244 .vco_table = default_vco, 245 .num_vco = ARRAY_SIZE(default_vco), 246 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 247 .clkr = { 248 .enable_reg = 0x79000, 249 .enable_mask = BIT(3), 250 .hw.init = &(struct clk_init_data){ 251 .name = "gpll3", 252 .parent_data = &(const struct clk_parent_data){ 253 .fw_name = "bi_tcxo", 254 }, 255 .num_parents = 1, 256 .ops = &clk_alpha_pll_ops, 257 }, 258 }, 259 }; 260 261 static struct clk_alpha_pll gpll4 = { 262 .offset = 0x4000, 263 .vco_table = default_vco, 264 .num_vco = ARRAY_SIZE(default_vco), 265 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 266 .clkr = { 267 .enable_reg = 0x79000, 268 .enable_mask = BIT(4), 269 .hw.init = &(struct clk_init_data){ 270 .name = "gpll4", 271 .parent_data = &(const struct clk_parent_data){ 272 .fw_name = "bi_tcxo", 273 }, 274 .num_parents = 1, 275 .ops = &clk_alpha_pll_ops, 276 }, 277 }, 278 }; 279 280 static const struct clk_div_table post_div_table_gpll4_out_main[] = { 281 { 0x0, 1 }, 282 { } 283 }; 284 285 static struct clk_alpha_pll_postdiv gpll4_out_main = { 286 .offset = 0x4000, 287 .post_div_shift = 8, 288 .post_div_table = post_div_table_gpll4_out_main, 289 .num_post_div = ARRAY_SIZE(post_div_table_gpll4_out_main), 290 .width = 4, 291 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 292 .clkr.hw.init = &(struct clk_init_data){ 293 .name = "gpll4_out_main", 294 .parent_hws = (const struct clk_hw *[]){ &gpll4.clkr.hw }, 295 .num_parents = 1, 296 .ops = &clk_alpha_pll_postdiv_ro_ops, 297 }, 298 }; 299 300 static struct clk_alpha_pll gpll6 = { 301 .offset = 0x6000, 302 .vco_table = default_vco, 303 .num_vco = ARRAY_SIZE(default_vco), 304 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 305 .clkr = { 306 .enable_reg = 0x79000, 307 .enable_mask = BIT(6), 308 .hw.init = &(struct clk_init_data){ 309 .name = "gpll6", 310 .parent_data = &(const struct clk_parent_data){ 311 .fw_name = "bi_tcxo", 312 }, 313 .num_parents = 1, 314 .ops = &clk_alpha_pll_ops, 315 }, 316 }, 317 }; 318 319 static const struct clk_div_table post_div_table_gpll6_out_main[] = { 320 { 0x1, 2 }, 321 { } 322 }; 323 324 static struct clk_alpha_pll_postdiv gpll6_out_main = { 325 .offset = 0x6000, 326 .post_div_shift = 8, 327 .post_div_table = post_div_table_gpll6_out_main, 328 .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main), 329 .width = 4, 330 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 331 .clkr.hw.init = &(struct clk_init_data){ 332 .name = "gpll6_out_main", 333 .parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw }, 334 .num_parents = 1, 335 .ops = &clk_alpha_pll_postdiv_ro_ops, 336 }, 337 }; 338 339 static struct clk_alpha_pll gpll7 = { 340 .offset = 0x7000, 341 .vco_table = default_vco, 342 .num_vco = ARRAY_SIZE(default_vco), 343 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 344 .clkr = { 345 .enable_reg = 0x79000, 346 .enable_mask = BIT(7), 347 .hw.init = &(struct clk_init_data){ 348 .name = "gpll7", 349 .parent_data = &(const struct clk_parent_data){ 350 .fw_name = "bi_tcxo", 351 }, 352 .num_parents = 1, 353 .ops = &clk_alpha_pll_ops, 354 }, 355 }, 356 }; 357 358 static const struct clk_div_table post_div_table_gpll7_out_main[] = { 359 { 0x0, 1 }, 360 { } 361 }; 362 363 static struct clk_alpha_pll_postdiv gpll7_out_main = { 364 .offset = 0x7000, 365 .post_div_shift = 8, 366 .post_div_table = post_div_table_gpll7_out_main, 367 .num_post_div = ARRAY_SIZE(post_div_table_gpll7_out_main), 368 .width = 4, 369 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 370 .clkr.hw.init = &(struct clk_init_data){ 371 .name = "gpll7_out_main", 372 .parent_hws = (const struct clk_hw *[]){ &gpll7.clkr.hw }, 373 .num_parents = 1, 374 .ops = &clk_alpha_pll_postdiv_ro_ops, 375 }, 376 }; 377 378 /* 800MHz configuration */ 379 static const struct alpha_pll_config gpll8_config = { 380 .l = 0x29, 381 .alpha = 0xAAAAAAAA, 382 .alpha_hi = 0xAA, 383 .alpha_en_mask = BIT(24), 384 .vco_val = 0x2 << 20, 385 .vco_mask = GENMASK(21, 20), 386 .main_output_mask = BIT(0), 387 .early_output_mask = BIT(3), 388 .post_div_val = 0x1 << 8, 389 .post_div_mask = GENMASK(11, 8), 390 .config_ctl_val = 0x4001055b, 391 }; 392 393 static struct clk_alpha_pll gpll8 = { 394 .offset = 0x8000, 395 .vco_table = default_vco, 396 .num_vco = ARRAY_SIZE(default_vco), 397 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 398 .flags = SUPPORTS_DYNAMIC_UPDATE, 399 .clkr = { 400 .enable_reg = 0x79000, 401 .enable_mask = BIT(8), 402 .hw.init = &(struct clk_init_data){ 403 .name = "gpll8", 404 .parent_data = &(const struct clk_parent_data){ 405 .fw_name = "bi_tcxo", 406 }, 407 .num_parents = 1, 408 .ops = &clk_alpha_pll_ops, 409 }, 410 }, 411 }; 412 413 static const struct clk_div_table post_div_table_gpll8_out_main[] = { 414 { 0x1, 2 }, 415 { } 416 }; 417 418 static struct clk_alpha_pll_postdiv gpll8_out_main = { 419 .offset = 0x8000, 420 .post_div_shift = 8, 421 .post_div_table = post_div_table_gpll8_out_main, 422 .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main), 423 .width = 4, 424 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 425 .clkr.hw.init = &(struct clk_init_data){ 426 .name = "gpll8_out_main", 427 .parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw }, 428 .num_parents = 1, 429 .flags = CLK_SET_RATE_PARENT, 430 .ops = &clk_alpha_pll_postdiv_ro_ops, 431 }, 432 }; 433 434 /* 1152MHz configuration */ 435 static const struct alpha_pll_config gpll9_config = { 436 .l = 0x3C, 437 .alpha = 0x0, 438 .post_div_val = 0x1 << 8, 439 .post_div_mask = GENMASK(9, 8), 440 .main_output_mask = BIT(0), 441 .config_ctl_val = 0x00004289, 442 }; 443 444 static struct clk_alpha_pll gpll9 = { 445 .offset = 0x9000, 446 .vco_table = gpll9_vco, 447 .num_vco = ARRAY_SIZE(gpll9_vco), 448 .regs = clk_gpll9_regs, 449 .clkr = { 450 .enable_reg = 0x79000, 451 .enable_mask = BIT(9), 452 .hw.init = &(struct clk_init_data){ 453 .name = "gpll9", 454 .parent_data = &(const struct clk_parent_data){ 455 .fw_name = "bi_tcxo", 456 }, 457 .num_parents = 1, 458 .ops = &clk_alpha_pll_ops, 459 }, 460 }, 461 }; 462 463 static const struct clk_div_table post_div_table_gpll9_out_main[] = { 464 { 0x1, 2 }, 465 { } 466 }; 467 468 static struct clk_alpha_pll_postdiv gpll9_out_main = { 469 .offset = 0x9000, 470 .post_div_shift = 8, 471 .post_div_table = post_div_table_gpll9_out_main, 472 .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main), 473 .width = 2, 474 .regs = clk_gpll9_regs, 475 .clkr.hw.init = &(struct clk_init_data){ 476 .name = "gpll9_out_main", 477 .parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw }, 478 .num_parents = 1, 479 .flags = CLK_SET_RATE_PARENT, 480 .ops = &clk_alpha_pll_postdiv_ops, 481 }, 482 }; 483 484 static const struct parent_map gcc_parent_map_0[] = { 485 { P_BI_TCXO, 0 }, 486 { P_GPLL0_OUT_EARLY, 1 }, 487 { P_GPLL0_OUT_AUX2, 2 }, 488 }; 489 490 static const struct clk_parent_data gcc_parents_0[] = { 491 { .fw_name = "bi_tcxo" }, 492 { .hw = &gpll0.clkr.hw }, 493 { .hw = &gpll0_out_aux2.clkr.hw }, 494 }; 495 496 static const struct parent_map gcc_parent_map_1[] = { 497 { P_BI_TCXO, 0 }, 498 { P_GPLL0_OUT_EARLY, 1 }, 499 { P_GPLL0_OUT_AUX2, 2 }, 500 { P_GPLL6_OUT_MAIN, 4 }, 501 }; 502 503 static const struct clk_parent_data gcc_parents_1[] = { 504 { .fw_name = "bi_tcxo" }, 505 { .hw = &gpll0.clkr.hw }, 506 { .hw = &gpll0_out_aux2.clkr.hw }, 507 { .hw = &gpll6_out_main.clkr.hw }, 508 }; 509 510 static const struct parent_map gcc_parent_map_2[] = { 511 { P_BI_TCXO, 0 }, 512 { P_GPLL0_OUT_EARLY, 1 }, 513 { P_GPLL0_OUT_AUX2, 2 }, 514 { P_SLEEP_CLK, 5 }, 515 }; 516 517 static const struct clk_parent_data gcc_parents_2[] = { 518 { .fw_name = "bi_tcxo" }, 519 { .hw = &gpll0.clkr.hw }, 520 { .hw = &gpll0_out_aux2.clkr.hw }, 521 { .fw_name = "sleep_clk" }, 522 }; 523 524 static const struct parent_map gcc_parent_map_3[] = { 525 { P_BI_TCXO, 0 }, 526 { P_GPLL0_OUT_EARLY, 1 }, 527 { P_GPLL9_OUT_EARLY, 2 }, 528 { P_GPLL10_OUT_MAIN, 3 }, 529 { P_GPLL9_OUT_MAIN, 5 }, 530 }; 531 532 static const struct clk_parent_data gcc_parents_3[] = { 533 { .fw_name = "bi_tcxo" }, 534 { .hw = &gpll0.clkr.hw }, 535 { .hw = &gpll9.clkr.hw }, 536 { .hw = &gpll10_out_main.clkr.hw }, 537 { .hw = &gpll9_out_main.clkr.hw }, 538 }; 539 540 static const struct parent_map gcc_parent_map_4[] = { 541 { P_BI_TCXO, 0 }, 542 { P_GPLL0_OUT_EARLY, 1 }, 543 { P_GPLL0_OUT_AUX2, 2 }, 544 { P_GPLL4_OUT_MAIN, 5 }, 545 }; 546 547 static const struct clk_parent_data gcc_parents_4[] = { 548 { .fw_name = "bi_tcxo" }, 549 { .hw = &gpll0.clkr.hw }, 550 { .hw = &gpll0_out_aux2.clkr.hw }, 551 { .hw = &gpll4_out_main.clkr.hw }, 552 }; 553 554 static const struct parent_map gcc_parent_map_5[] = { 555 { P_BI_TCXO, 0 }, 556 { P_GPLL0_OUT_EARLY, 1 }, 557 { P_GPLL8_OUT_EARLY, 2 }, 558 { P_GPLL10_OUT_MAIN, 3 }, 559 { P_GPLL8_OUT_MAIN, 4 }, 560 { P_GPLL9_OUT_MAIN, 5 }, 561 }; 562 563 static const struct clk_parent_data gcc_parents_5[] = { 564 { .fw_name = "bi_tcxo" }, 565 { .hw = &gpll0.clkr.hw }, 566 { .hw = &gpll8.clkr.hw }, 567 { .hw = &gpll10_out_main.clkr.hw }, 568 { .hw = &gpll8_out_main.clkr.hw }, 569 { .hw = &gpll9_out_main.clkr.hw }, 570 }; 571 572 static const struct parent_map gcc_parent_map_6[] = { 573 { P_BI_TCXO, 0 }, 574 { P_GPLL0_OUT_EARLY, 1 }, 575 { P_GPLL8_OUT_EARLY, 2 }, 576 { P_GPLL10_OUT_MAIN, 3 }, 577 { P_GPLL6_OUT_MAIN, 4 }, 578 { P_GPLL9_OUT_MAIN, 5 }, 579 { P_GPLL3_OUT_EARLY, 6 }, 580 }; 581 582 static const struct clk_parent_data gcc_parents_6[] = { 583 { .fw_name = "bi_tcxo" }, 584 { .hw = &gpll0.clkr.hw }, 585 { .hw = &gpll8.clkr.hw }, 586 { .hw = &gpll10_out_main.clkr.hw }, 587 { .hw = &gpll6_out_main.clkr.hw }, 588 { .hw = &gpll9_out_main.clkr.hw }, 589 { .hw = &gpll3.clkr.hw }, 590 }; 591 592 static const struct parent_map gcc_parent_map_7[] = { 593 { P_BI_TCXO, 0 }, 594 { P_GPLL0_OUT_EARLY, 1 }, 595 { P_GPLL0_OUT_AUX2, 2 }, 596 { P_GPLL10_OUT_MAIN, 3 }, 597 { P_GPLL4_OUT_MAIN, 5 }, 598 { P_GPLL3_OUT_EARLY, 6 }, 599 }; 600 601 static const struct clk_parent_data gcc_parents_7[] = { 602 { .fw_name = "bi_tcxo" }, 603 { .hw = &gpll0.clkr.hw }, 604 { .hw = &gpll0_out_aux2.clkr.hw }, 605 { .hw = &gpll10_out_main.clkr.hw }, 606 { .hw = &gpll4_out_main.clkr.hw }, 607 { .hw = &gpll3.clkr.hw }, 608 }; 609 610 static const struct parent_map gcc_parent_map_8[] = { 611 { P_BI_TCXO, 0 }, 612 { P_GPLL0_OUT_EARLY, 1 }, 613 { P_GPLL8_OUT_EARLY, 2 }, 614 { P_GPLL10_OUT_MAIN, 3 }, 615 { P_GPLL8_OUT_MAIN, 4 }, 616 { P_GPLL9_OUT_MAIN, 5 }, 617 { P_GPLL3_OUT_EARLY, 6 }, 618 }; 619 620 static const struct clk_parent_data gcc_parents_8[] = { 621 { .fw_name = "bi_tcxo" }, 622 { .hw = &gpll0.clkr.hw }, 623 { .hw = &gpll8.clkr.hw }, 624 { .hw = &gpll10_out_main.clkr.hw }, 625 { .hw = &gpll8_out_main.clkr.hw }, 626 { .hw = &gpll9_out_main.clkr.hw }, 627 { .hw = &gpll3.clkr.hw }, 628 }; 629 630 static const struct parent_map gcc_parent_map_9[] = { 631 { P_BI_TCXO, 0 }, 632 { P_GPLL0_OUT_EARLY, 1 }, 633 { P_GPLL0_OUT_AUX2, 2 }, 634 { P_GPLL10_OUT_MAIN, 3 }, 635 { P_GPLL8_OUT_MAIN, 4 }, 636 { P_GPLL9_OUT_MAIN, 5 }, 637 { P_GPLL3_OUT_EARLY, 6 }, 638 }; 639 640 static const struct clk_parent_data gcc_parents_9[] = { 641 { .fw_name = "bi_tcxo" }, 642 { .hw = &gpll0.clkr.hw }, 643 { .hw = &gpll0_out_aux2.clkr.hw }, 644 { .hw = &gpll10_out_main.clkr.hw }, 645 { .hw = &gpll8_out_main.clkr.hw }, 646 { .hw = &gpll9_out_main.clkr.hw }, 647 { .hw = &gpll3.clkr.hw }, 648 }; 649 650 static const struct parent_map gcc_parent_map_10[] = { 651 { P_BI_TCXO, 0 }, 652 { P_GPLL0_OUT_EARLY, 1 }, 653 { P_GPLL8_OUT_EARLY, 2 }, 654 { P_GPLL10_OUT_MAIN, 3 }, 655 { P_GPLL6_OUT_EARLY, 4 }, 656 { P_GPLL9_OUT_MAIN, 5 }, 657 }; 658 659 static const struct clk_parent_data gcc_parents_10[] = { 660 { .fw_name = "bi_tcxo" }, 661 { .hw = &gpll0.clkr.hw }, 662 { .hw = &gpll8.clkr.hw }, 663 { .hw = &gpll10_out_main.clkr.hw }, 664 { .hw = &gpll6.clkr.hw }, 665 { .hw = &gpll9_out_main.clkr.hw }, 666 }; 667 668 static const struct parent_map gcc_parent_map_11[] = { 669 { P_BI_TCXO, 0 }, 670 { P_GPLL0_OUT_EARLY, 1 }, 671 { P_GPLL0_OUT_AUX2, 2 }, 672 { P_GPLL7_OUT_MAIN, 3 }, 673 { P_GPLL4_OUT_MAIN, 5 }, 674 }; 675 676 static const struct clk_parent_data gcc_parents_11[] = { 677 { .fw_name = "bi_tcxo" }, 678 { .hw = &gpll0.clkr.hw }, 679 { .hw = &gpll0_out_aux2.clkr.hw }, 680 { .hw = &gpll7_out_main.clkr.hw }, 681 { .hw = &gpll4_out_main.clkr.hw }, 682 }; 683 684 static const struct parent_map gcc_parent_map_12[] = { 685 { P_BI_TCXO, 0 }, 686 { P_SLEEP_CLK, 5 }, 687 }; 688 689 static const struct clk_parent_data gcc_parents_12[] = { 690 { .fw_name = "bi_tcxo" }, 691 { .fw_name = "sleep_clk" }, 692 }; 693 694 static const struct parent_map gcc_parent_map_13[] = { 695 { P_BI_TCXO, 0 }, 696 { P_GPLL11_OUT_MAIN, 1 }, 697 }; 698 699 static const struct clk_parent_data gcc_parents_13[] = { 700 { .fw_name = "bi_tcxo" }, 701 { .hw = &gpll11_out_main.clkr.hw }, 702 }; 703 704 static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = { 705 F(19200000, P_BI_TCXO, 1, 0, 0), 706 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 707 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 708 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 709 { } 710 }; 711 712 static struct clk_rcg2 gcc_camss_axi_clk_src = { 713 .cmd_rcgr = 0x5802c, 714 .mnd_width = 0, 715 .hid_width = 5, 716 .parent_map = gcc_parent_map_7, 717 .freq_tbl = ftbl_gcc_camss_axi_clk_src, 718 .clkr.hw.init = &(struct clk_init_data){ 719 .name = "gcc_camss_axi_clk_src", 720 .parent_data = gcc_parents_7, 721 .num_parents = ARRAY_SIZE(gcc_parents_7), 722 .flags = CLK_SET_RATE_PARENT, 723 .ops = &clk_rcg2_ops, 724 }, 725 }; 726 727 static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = { 728 F(19200000, P_BI_TCXO, 1, 0, 0), 729 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 730 { } 731 }; 732 733 static struct clk_rcg2 gcc_camss_cci_clk_src = { 734 .cmd_rcgr = 0x56000, 735 .mnd_width = 0, 736 .hid_width = 5, 737 .parent_map = gcc_parent_map_9, 738 .freq_tbl = ftbl_gcc_camss_cci_clk_src, 739 .clkr.hw.init = &(struct clk_init_data){ 740 .name = "gcc_camss_cci_clk_src", 741 .parent_data = gcc_parents_9, 742 .num_parents = ARRAY_SIZE(gcc_parents_9), 743 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 744 .ops = &clk_rcg2_ops, 745 }, 746 }; 747 748 static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = { 749 F(19200000, P_BI_TCXO, 1, 0, 0), 750 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 751 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 752 F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0), 753 { } 754 }; 755 756 static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { 757 .cmd_rcgr = 0x59000, 758 .mnd_width = 0, 759 .hid_width = 5, 760 .parent_map = gcc_parent_map_4, 761 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 762 .clkr.hw.init = &(struct clk_init_data){ 763 .name = "gcc_camss_csi0phytimer_clk_src", 764 .parent_data = gcc_parents_4, 765 .num_parents = ARRAY_SIZE(gcc_parents_4), 766 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 767 .ops = &clk_rcg2_ops, 768 }, 769 }; 770 771 static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { 772 .cmd_rcgr = 0x5901c, 773 .mnd_width = 0, 774 .hid_width = 5, 775 .parent_map = gcc_parent_map_4, 776 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 777 .clkr.hw.init = &(struct clk_init_data){ 778 .name = "gcc_camss_csi1phytimer_clk_src", 779 .parent_data = gcc_parents_4, 780 .num_parents = ARRAY_SIZE(gcc_parents_4), 781 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 782 .ops = &clk_rcg2_ops, 783 }, 784 }; 785 786 static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = { 787 .cmd_rcgr = 0x59038, 788 .mnd_width = 0, 789 .hid_width = 5, 790 .parent_map = gcc_parent_map_4, 791 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 792 .clkr.hw.init = &(struct clk_init_data){ 793 .name = "gcc_camss_csi2phytimer_clk_src", 794 .parent_data = gcc_parents_4, 795 .num_parents = ARRAY_SIZE(gcc_parents_4), 796 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 797 .ops = &clk_rcg2_ops, 798 }, 799 }; 800 801 static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { 802 F(19200000, P_BI_TCXO, 1, 0, 0), 803 F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24), 804 F(64000000, P_GPLL9_OUT_MAIN, 1, 1, 9), 805 { } 806 }; 807 808 static struct clk_rcg2 gcc_camss_mclk0_clk_src = { 809 .cmd_rcgr = 0x51000, 810 .mnd_width = 8, 811 .hid_width = 5, 812 .parent_map = gcc_parent_map_3, 813 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 814 .clkr.hw.init = &(struct clk_init_data){ 815 .name = "gcc_camss_mclk0_clk_src", 816 .parent_data = gcc_parents_3, 817 .num_parents = ARRAY_SIZE(gcc_parents_3), 818 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 819 .ops = &clk_rcg2_ops, 820 }, 821 }; 822 823 static struct clk_rcg2 gcc_camss_mclk1_clk_src = { 824 .cmd_rcgr = 0x5101c, 825 .mnd_width = 8, 826 .hid_width = 5, 827 .parent_map = gcc_parent_map_3, 828 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 829 .clkr.hw.init = &(struct clk_init_data){ 830 .name = "gcc_camss_mclk1_clk_src", 831 .parent_data = gcc_parents_3, 832 .num_parents = ARRAY_SIZE(gcc_parents_3), 833 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 834 .ops = &clk_rcg2_ops, 835 }, 836 }; 837 838 static struct clk_rcg2 gcc_camss_mclk2_clk_src = { 839 .cmd_rcgr = 0x51038, 840 .mnd_width = 8, 841 .hid_width = 5, 842 .parent_map = gcc_parent_map_3, 843 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 844 .clkr.hw.init = &(struct clk_init_data){ 845 .name = "gcc_camss_mclk2_clk_src", 846 .parent_data = gcc_parents_3, 847 .num_parents = ARRAY_SIZE(gcc_parents_3), 848 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 849 .ops = &clk_rcg2_ops, 850 }, 851 }; 852 853 static struct clk_rcg2 gcc_camss_mclk3_clk_src = { 854 .cmd_rcgr = 0x51054, 855 .mnd_width = 8, 856 .hid_width = 5, 857 .parent_map = gcc_parent_map_3, 858 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 859 .clkr.hw.init = &(struct clk_init_data){ 860 .name = "gcc_camss_mclk3_clk_src", 861 .parent_data = gcc_parents_3, 862 .num_parents = ARRAY_SIZE(gcc_parents_3), 863 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 864 .ops = &clk_rcg2_ops, 865 }, 866 }; 867 868 static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = { 869 F(19200000, P_BI_TCXO, 1, 0, 0), 870 F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0), 871 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 872 { } 873 }; 874 875 static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = { 876 .cmd_rcgr = 0x55024, 877 .mnd_width = 0, 878 .hid_width = 5, 879 .parent_map = gcc_parent_map_8, 880 .freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src, 881 .clkr.hw.init = &(struct clk_init_data){ 882 .name = "gcc_camss_ope_ahb_clk_src", 883 .parent_data = gcc_parents_8, 884 .num_parents = ARRAY_SIZE(gcc_parents_8), 885 .flags = CLK_SET_RATE_PARENT, 886 .ops = &clk_rcg2_ops, 887 }, 888 }; 889 890 static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = { 891 F(19200000, P_BI_TCXO, 1, 0, 0), 892 F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0), 893 F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0), 894 F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0), 895 F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0), 896 { } 897 }; 898 899 static struct clk_rcg2 gcc_camss_ope_clk_src = { 900 .cmd_rcgr = 0x55004, 901 .mnd_width = 0, 902 .hid_width = 5, 903 .parent_map = gcc_parent_map_8, 904 .freq_tbl = ftbl_gcc_camss_ope_clk_src, 905 .clkr.hw.init = &(struct clk_init_data){ 906 .name = "gcc_camss_ope_clk_src", 907 .parent_data = gcc_parents_8, 908 .num_parents = ARRAY_SIZE(gcc_parents_8), 909 .flags = CLK_SET_RATE_PARENT, 910 .ops = &clk_rcg2_ops, 911 }, 912 }; 913 914 static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = { 915 F(19200000, P_BI_TCXO, 1, 0, 0), 916 F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0), 917 F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0), 918 F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0), 919 F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0), 920 F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0), 921 F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0), 922 F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0), 923 F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0), 924 F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0), 925 F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0), 926 F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0), 927 F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0), 928 F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0), 929 F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0), 930 F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0), 931 { } 932 }; 933 934 static struct clk_rcg2 gcc_camss_tfe_0_clk_src = { 935 .cmd_rcgr = 0x52004, 936 .mnd_width = 8, 937 .hid_width = 5, 938 .parent_map = gcc_parent_map_5, 939 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 940 .clkr.hw.init = &(struct clk_init_data){ 941 .name = "gcc_camss_tfe_0_clk_src", 942 .parent_data = gcc_parents_5, 943 .num_parents = ARRAY_SIZE(gcc_parents_5), 944 .flags = CLK_SET_RATE_PARENT, 945 .ops = &clk_rcg2_ops, 946 }, 947 }; 948 949 static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = { 950 F(19200000, P_BI_TCXO, 1, 0, 0), 951 F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0), 952 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 953 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 954 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 955 F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0), 956 { } 957 }; 958 959 static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = { 960 .cmd_rcgr = 0x52094, 961 .mnd_width = 0, 962 .hid_width = 5, 963 .parent_map = gcc_parent_map_6, 964 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 965 .clkr.hw.init = &(struct clk_init_data){ 966 .name = "gcc_camss_tfe_0_csid_clk_src", 967 .parent_data = gcc_parents_6, 968 .num_parents = ARRAY_SIZE(gcc_parents_6), 969 .flags = CLK_SET_RATE_PARENT, 970 .ops = &clk_rcg2_ops, 971 }, 972 }; 973 974 static struct clk_rcg2 gcc_camss_tfe_1_clk_src = { 975 .cmd_rcgr = 0x52024, 976 .mnd_width = 8, 977 .hid_width = 5, 978 .parent_map = gcc_parent_map_5, 979 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 980 .clkr.hw.init = &(struct clk_init_data){ 981 .name = "gcc_camss_tfe_1_clk_src", 982 .parent_data = gcc_parents_5, 983 .num_parents = ARRAY_SIZE(gcc_parents_5), 984 .flags = CLK_SET_RATE_PARENT, 985 .ops = &clk_rcg2_ops, 986 }, 987 }; 988 989 static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = { 990 .cmd_rcgr = 0x520b4, 991 .mnd_width = 0, 992 .hid_width = 5, 993 .parent_map = gcc_parent_map_6, 994 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 995 .clkr.hw.init = &(struct clk_init_data){ 996 .name = "gcc_camss_tfe_1_csid_clk_src", 997 .parent_data = gcc_parents_6, 998 .num_parents = ARRAY_SIZE(gcc_parents_6), 999 .flags = CLK_SET_RATE_PARENT, 1000 .ops = &clk_rcg2_ops, 1001 }, 1002 }; 1003 1004 static struct clk_rcg2 gcc_camss_tfe_2_clk_src = { 1005 .cmd_rcgr = 0x52044, 1006 .mnd_width = 8, 1007 .hid_width = 5, 1008 .parent_map = gcc_parent_map_5, 1009 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 1010 .clkr.hw.init = &(struct clk_init_data){ 1011 .name = "gcc_camss_tfe_2_clk_src", 1012 .parent_data = gcc_parents_5, 1013 .num_parents = ARRAY_SIZE(gcc_parents_5), 1014 .flags = CLK_SET_RATE_PARENT, 1015 .ops = &clk_rcg2_ops, 1016 }, 1017 }; 1018 1019 static struct clk_rcg2 gcc_camss_tfe_2_csid_clk_src = { 1020 .cmd_rcgr = 0x520d4, 1021 .mnd_width = 0, 1022 .hid_width = 5, 1023 .parent_map = gcc_parent_map_6, 1024 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 1025 .clkr.hw.init = &(struct clk_init_data){ 1026 .name = "gcc_camss_tfe_2_csid_clk_src", 1027 .parent_data = gcc_parents_6, 1028 .num_parents = ARRAY_SIZE(gcc_parents_6), 1029 .flags = CLK_SET_RATE_PARENT, 1030 .ops = &clk_rcg2_ops, 1031 }, 1032 }; 1033 1034 static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = { 1035 F(19200000, P_BI_TCXO, 1, 0, 0), 1036 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1037 F(341333333, P_GPLL6_OUT_EARLY, 1, 4, 9), 1038 F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0), 1039 { } 1040 }; 1041 1042 static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = { 1043 .cmd_rcgr = 0x52064, 1044 .mnd_width = 16, 1045 .hid_width = 5, 1046 .parent_map = gcc_parent_map_10, 1047 .freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src, 1048 .clkr.hw.init = &(struct clk_init_data){ 1049 .name = "gcc_camss_tfe_cphy_rx_clk_src", 1050 .parent_data = gcc_parents_10, 1051 .num_parents = ARRAY_SIZE(gcc_parents_10), 1052 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 1053 .ops = &clk_rcg2_ops, 1054 }, 1055 }; 1056 1057 static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = { 1058 F(19200000, P_BI_TCXO, 1, 0, 0), 1059 F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0), 1060 F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0), 1061 { } 1062 }; 1063 1064 static struct clk_rcg2 gcc_camss_top_ahb_clk_src = { 1065 .cmd_rcgr = 0x58010, 1066 .mnd_width = 0, 1067 .hid_width = 5, 1068 .parent_map = gcc_parent_map_7, 1069 .freq_tbl = ftbl_gcc_camss_top_ahb_clk_src, 1070 .clkr.hw.init = &(struct clk_init_data){ 1071 .name = "gcc_camss_top_ahb_clk_src", 1072 .parent_data = gcc_parents_7, 1073 .num_parents = ARRAY_SIZE(gcc_parents_7), 1074 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 1075 .ops = &clk_rcg2_ops, 1076 }, 1077 }; 1078 1079 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 1080 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1081 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1082 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1083 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 1084 { } 1085 }; 1086 1087 static struct clk_rcg2 gcc_gp1_clk_src = { 1088 .cmd_rcgr = 0x4d004, 1089 .mnd_width = 8, 1090 .hid_width = 5, 1091 .parent_map = gcc_parent_map_2, 1092 .freq_tbl = ftbl_gcc_gp1_clk_src, 1093 .clkr.hw.init = &(struct clk_init_data){ 1094 .name = "gcc_gp1_clk_src", 1095 .parent_data = gcc_parents_2, 1096 .num_parents = ARRAY_SIZE(gcc_parents_2), 1097 .ops = &clk_rcg2_ops, 1098 }, 1099 }; 1100 1101 static struct clk_rcg2 gcc_gp2_clk_src = { 1102 .cmd_rcgr = 0x4e004, 1103 .mnd_width = 8, 1104 .hid_width = 5, 1105 .parent_map = gcc_parent_map_2, 1106 .freq_tbl = ftbl_gcc_gp1_clk_src, 1107 .clkr.hw.init = &(struct clk_init_data){ 1108 .name = "gcc_gp2_clk_src", 1109 .parent_data = gcc_parents_2, 1110 .num_parents = ARRAY_SIZE(gcc_parents_2), 1111 .ops = &clk_rcg2_ops, 1112 }, 1113 }; 1114 1115 static struct clk_rcg2 gcc_gp3_clk_src = { 1116 .cmd_rcgr = 0x4f004, 1117 .mnd_width = 8, 1118 .hid_width = 5, 1119 .parent_map = gcc_parent_map_2, 1120 .freq_tbl = ftbl_gcc_gp1_clk_src, 1121 .clkr.hw.init = &(struct clk_init_data){ 1122 .name = "gcc_gp3_clk_src", 1123 .parent_data = gcc_parents_2, 1124 .num_parents = ARRAY_SIZE(gcc_parents_2), 1125 .ops = &clk_rcg2_ops, 1126 }, 1127 }; 1128 1129 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 1130 F(19200000, P_BI_TCXO, 1, 0, 0), 1131 F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0), 1132 { } 1133 }; 1134 1135 static struct clk_rcg2 gcc_pdm2_clk_src = { 1136 .cmd_rcgr = 0x20010, 1137 .mnd_width = 0, 1138 .hid_width = 5, 1139 .parent_map = gcc_parent_map_0, 1140 .freq_tbl = ftbl_gcc_pdm2_clk_src, 1141 .clkr.hw.init = &(struct clk_init_data){ 1142 .name = "gcc_pdm2_clk_src", 1143 .parent_data = gcc_parents_0, 1144 .num_parents = ARRAY_SIZE(gcc_parents_0), 1145 .ops = &clk_rcg2_ops, 1146 }, 1147 }; 1148 1149 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 1150 F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625), 1151 F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625), 1152 F(19200000, P_BI_TCXO, 1, 0, 0), 1153 F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625), 1154 F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75), 1155 F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25), 1156 F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75), 1157 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1158 F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15), 1159 F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25), 1160 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1161 F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375), 1162 F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75), 1163 F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625), 1164 F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0), 1165 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0), 1166 { } 1167 }; 1168 1169 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 1170 .name = "gcc_qupv3_wrap0_s0_clk_src", 1171 .parent_data = gcc_parents_1, 1172 .num_parents = ARRAY_SIZE(gcc_parents_1), 1173 .ops = &clk_rcg2_ops, 1174 }; 1175 1176 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 1177 .cmd_rcgr = 0x1f148, 1178 .mnd_width = 16, 1179 .hid_width = 5, 1180 .parent_map = gcc_parent_map_1, 1181 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1182 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 1183 }; 1184 1185 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 1186 .name = "gcc_qupv3_wrap0_s1_clk_src", 1187 .parent_data = gcc_parents_1, 1188 .num_parents = ARRAY_SIZE(gcc_parents_1), 1189 .ops = &clk_rcg2_ops, 1190 }; 1191 1192 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 1193 .cmd_rcgr = 0x1f278, 1194 .mnd_width = 16, 1195 .hid_width = 5, 1196 .parent_map = gcc_parent_map_1, 1197 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1198 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 1199 }; 1200 1201 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 1202 .name = "gcc_qupv3_wrap0_s2_clk_src", 1203 .parent_data = gcc_parents_1, 1204 .num_parents = ARRAY_SIZE(gcc_parents_1), 1205 .ops = &clk_rcg2_ops, 1206 }; 1207 1208 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 1209 .cmd_rcgr = 0x1f3a8, 1210 .mnd_width = 16, 1211 .hid_width = 5, 1212 .parent_map = gcc_parent_map_1, 1213 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1214 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 1215 }; 1216 1217 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 1218 .name = "gcc_qupv3_wrap0_s3_clk_src", 1219 .parent_data = gcc_parents_1, 1220 .num_parents = ARRAY_SIZE(gcc_parents_1), 1221 .ops = &clk_rcg2_ops, 1222 }; 1223 1224 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 1225 .cmd_rcgr = 0x1f4d8, 1226 .mnd_width = 16, 1227 .hid_width = 5, 1228 .parent_map = gcc_parent_map_1, 1229 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1230 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 1231 }; 1232 1233 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 1234 .name = "gcc_qupv3_wrap0_s4_clk_src", 1235 .parent_data = gcc_parents_1, 1236 .num_parents = ARRAY_SIZE(gcc_parents_1), 1237 .ops = &clk_rcg2_ops, 1238 }; 1239 1240 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 1241 .cmd_rcgr = 0x1f608, 1242 .mnd_width = 16, 1243 .hid_width = 5, 1244 .parent_map = gcc_parent_map_1, 1245 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1246 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 1247 }; 1248 1249 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 1250 .name = "gcc_qupv3_wrap0_s5_clk_src", 1251 .parent_data = gcc_parents_1, 1252 .num_parents = ARRAY_SIZE(gcc_parents_1), 1253 .ops = &clk_rcg2_ops, 1254 }; 1255 1256 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 1257 .cmd_rcgr = 0x1f738, 1258 .mnd_width = 16, 1259 .hid_width = 5, 1260 .parent_map = gcc_parent_map_1, 1261 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1262 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 1263 }; 1264 1265 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 1266 F(144000, P_BI_TCXO, 16, 3, 25), 1267 F(400000, P_BI_TCXO, 12, 1, 4), 1268 F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3), 1269 F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2), 1270 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1271 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1272 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 1273 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 1274 { } 1275 }; 1276 1277 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 1278 .cmd_rcgr = 0x38028, 1279 .mnd_width = 8, 1280 .hid_width = 5, 1281 .parent_map = gcc_parent_map_1, 1282 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 1283 .clkr.hw.init = &(struct clk_init_data){ 1284 .name = "gcc_sdcc1_apps_clk_src", 1285 .parent_data = gcc_parents_1, 1286 .num_parents = ARRAY_SIZE(gcc_parents_1), 1287 .ops = &clk_rcg2_ops, 1288 }, 1289 }; 1290 1291 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 1292 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1293 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1294 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1295 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1296 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 1297 { } 1298 }; 1299 1300 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 1301 .cmd_rcgr = 0x38010, 1302 .mnd_width = 0, 1303 .hid_width = 5, 1304 .parent_map = gcc_parent_map_0, 1305 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 1306 .clkr.hw.init = &(struct clk_init_data){ 1307 .name = "gcc_sdcc1_ice_core_clk_src", 1308 .parent_data = gcc_parents_0, 1309 .num_parents = ARRAY_SIZE(gcc_parents_0), 1310 .ops = &clk_rcg2_ops, 1311 }, 1312 }; 1313 1314 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1315 F(400000, P_BI_TCXO, 12, 1, 4), 1316 F(19200000, P_BI_TCXO, 1, 0, 0), 1317 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1318 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1319 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1320 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1321 { } 1322 }; 1323 1324 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1325 .cmd_rcgr = 0x1e00c, 1326 .mnd_width = 8, 1327 .hid_width = 5, 1328 .parent_map = gcc_parent_map_11, 1329 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1330 .clkr.hw.init = &(struct clk_init_data){ 1331 .name = "gcc_sdcc2_apps_clk_src", 1332 .parent_data = gcc_parents_11, 1333 .num_parents = ARRAY_SIZE(gcc_parents_11), 1334 .ops = &clk_rcg2_ops, 1335 .flags = CLK_OPS_PARENT_ENABLE, 1336 }, 1337 }; 1338 1339 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1340 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1341 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1342 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1343 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1344 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1345 { } 1346 }; 1347 1348 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1349 .cmd_rcgr = 0x45020, 1350 .mnd_width = 8, 1351 .hid_width = 5, 1352 .parent_map = gcc_parent_map_0, 1353 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1354 .clkr.hw.init = &(struct clk_init_data){ 1355 .name = "gcc_ufs_phy_axi_clk_src", 1356 .parent_data = gcc_parents_0, 1357 .num_parents = ARRAY_SIZE(gcc_parents_0), 1358 .ops = &clk_rcg2_ops, 1359 }, 1360 }; 1361 1362 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1363 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 1364 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1365 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1366 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 1367 { } 1368 }; 1369 1370 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1371 .cmd_rcgr = 0x45048, 1372 .mnd_width = 0, 1373 .hid_width = 5, 1374 .parent_map = gcc_parent_map_0, 1375 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1376 .clkr.hw.init = &(struct clk_init_data){ 1377 .name = "gcc_ufs_phy_ice_core_clk_src", 1378 .parent_data = gcc_parents_0, 1379 .num_parents = ARRAY_SIZE(gcc_parents_0), 1380 .ops = &clk_rcg2_ops, 1381 }, 1382 }; 1383 1384 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1385 F(9600000, P_BI_TCXO, 2, 0, 0), 1386 F(19200000, P_BI_TCXO, 1, 0, 0), 1387 { } 1388 }; 1389 1390 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1391 .cmd_rcgr = 0x4507c, 1392 .mnd_width = 0, 1393 .hid_width = 5, 1394 .parent_map = gcc_parent_map_0, 1395 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1396 .clkr.hw.init = &(struct clk_init_data){ 1397 .name = "gcc_ufs_phy_phy_aux_clk_src", 1398 .parent_data = gcc_parents_0, 1399 .num_parents = ARRAY_SIZE(gcc_parents_0), 1400 .ops = &clk_rcg2_ops, 1401 }, 1402 }; 1403 1404 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 1405 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 1406 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1407 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1408 { } 1409 }; 1410 1411 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1412 .cmd_rcgr = 0x45060, 1413 .mnd_width = 0, 1414 .hid_width = 5, 1415 .parent_map = gcc_parent_map_0, 1416 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 1417 .clkr.hw.init = &(struct clk_init_data){ 1418 .name = "gcc_ufs_phy_unipro_core_clk_src", 1419 .parent_data = gcc_parents_0, 1420 .num_parents = ARRAY_SIZE(gcc_parents_0), 1421 .ops = &clk_rcg2_ops, 1422 }, 1423 }; 1424 1425 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1426 F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0), 1427 F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0), 1428 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1429 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1430 { } 1431 }; 1432 1433 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1434 .cmd_rcgr = 0x1a01c, 1435 .mnd_width = 8, 1436 .hid_width = 5, 1437 .parent_map = gcc_parent_map_0, 1438 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1439 .clkr.hw.init = &(struct clk_init_data){ 1440 .name = "gcc_usb30_prim_master_clk_src", 1441 .parent_data = gcc_parents_0, 1442 .num_parents = ARRAY_SIZE(gcc_parents_0), 1443 .ops = &clk_rcg2_ops, 1444 }, 1445 }; 1446 1447 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 1448 F(19200000, P_BI_TCXO, 1, 0, 0), 1449 { } 1450 }; 1451 1452 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1453 .cmd_rcgr = 0x1a034, 1454 .mnd_width = 0, 1455 .hid_width = 5, 1456 .parent_map = gcc_parent_map_0, 1457 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1458 .clkr.hw.init = &(struct clk_init_data){ 1459 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1460 .parent_data = gcc_parents_0, 1461 .num_parents = ARRAY_SIZE(gcc_parents_0), 1462 .ops = &clk_rcg2_ops, 1463 }, 1464 }; 1465 1466 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1467 .reg = 0x1a04c, 1468 .shift = 0, 1469 .width = 2, 1470 .clkr.hw.init = &(struct clk_init_data) { 1471 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1472 .parent_hws = (const struct clk_hw *[]) { 1473 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw }, 1474 .num_parents = 1, 1475 .ops = &clk_regmap_div_ro_ops, 1476 }, 1477 }; 1478 1479 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1480 .cmd_rcgr = 0x1a060, 1481 .mnd_width = 0, 1482 .hid_width = 5, 1483 .parent_map = gcc_parent_map_12, 1484 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1485 .clkr.hw.init = &(struct clk_init_data){ 1486 .name = "gcc_usb3_prim_phy_aux_clk_src", 1487 .parent_data = gcc_parents_12, 1488 .num_parents = ARRAY_SIZE(gcc_parents_12), 1489 .ops = &clk_rcg2_ops, 1490 }, 1491 }; 1492 1493 static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = { 1494 F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0), 1495 F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0), 1496 F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0), 1497 F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0), 1498 { } 1499 }; 1500 1501 static struct clk_rcg2 gcc_video_venus_clk_src = { 1502 .cmd_rcgr = 0x58060, 1503 .mnd_width = 0, 1504 .hid_width = 5, 1505 .parent_map = gcc_parent_map_13, 1506 .freq_tbl = ftbl_gcc_video_venus_clk_src, 1507 .clkr.hw.init = &(struct clk_init_data){ 1508 .name = "gcc_video_venus_clk_src", 1509 .parent_data = gcc_parents_13, 1510 .num_parents = ARRAY_SIZE(gcc_parents_13), 1511 .flags = CLK_SET_RATE_PARENT, 1512 .ops = &clk_rcg2_ops, 1513 }, 1514 }; 1515 1516 static struct clk_branch gcc_ahb2phy_csi_clk = { 1517 .halt_reg = 0x1d004, 1518 .halt_check = BRANCH_HALT, 1519 .hwcg_reg = 0x1d004, 1520 .hwcg_bit = 1, 1521 .clkr = { 1522 .enable_reg = 0x1d004, 1523 .enable_mask = BIT(0), 1524 .hw.init = &(struct clk_init_data){ 1525 .name = "gcc_ahb2phy_csi_clk", 1526 .ops = &clk_branch2_ops, 1527 }, 1528 }, 1529 }; 1530 1531 static struct clk_branch gcc_ahb2phy_usb_clk = { 1532 .halt_reg = 0x1d008, 1533 .halt_check = BRANCH_HALT, 1534 .hwcg_reg = 0x1d008, 1535 .hwcg_bit = 1, 1536 .clkr = { 1537 .enable_reg = 0x1d008, 1538 .enable_mask = BIT(0), 1539 .hw.init = &(struct clk_init_data){ 1540 .name = "gcc_ahb2phy_usb_clk", 1541 .ops = &clk_branch2_ops, 1542 }, 1543 }, 1544 }; 1545 1546 static struct clk_branch gcc_bimc_gpu_axi_clk = { 1547 .halt_reg = 0x71154, 1548 .halt_check = BRANCH_HALT_DELAY, 1549 .hwcg_reg = 0x71154, 1550 .hwcg_bit = 1, 1551 .clkr = { 1552 .enable_reg = 0x71154, 1553 .enable_mask = BIT(0), 1554 .hw.init = &(struct clk_init_data){ 1555 .name = "gcc_bimc_gpu_axi_clk", 1556 .ops = &clk_branch2_ops, 1557 }, 1558 }, 1559 }; 1560 1561 static struct clk_branch gcc_boot_rom_ahb_clk = { 1562 .halt_reg = 0x23004, 1563 .halt_check = BRANCH_HALT_VOTED, 1564 .hwcg_reg = 0x23004, 1565 .hwcg_bit = 1, 1566 .clkr = { 1567 .enable_reg = 0x79004, 1568 .enable_mask = BIT(10), 1569 .hw.init = &(struct clk_init_data){ 1570 .name = "gcc_boot_rom_ahb_clk", 1571 .ops = &clk_branch2_ops, 1572 }, 1573 }, 1574 }; 1575 1576 static struct clk_branch gcc_cam_throttle_nrt_clk = { 1577 .halt_reg = 0x17070, 1578 .halt_check = BRANCH_HALT_VOTED, 1579 .hwcg_reg = 0x17070, 1580 .hwcg_bit = 1, 1581 .clkr = { 1582 .enable_reg = 0x79004, 1583 .enable_mask = BIT(27), 1584 .hw.init = &(struct clk_init_data){ 1585 .name = "gcc_cam_throttle_nrt_clk", 1586 .ops = &clk_branch2_ops, 1587 }, 1588 }, 1589 }; 1590 1591 static struct clk_branch gcc_cam_throttle_rt_clk = { 1592 .halt_reg = 0x1706c, 1593 .halt_check = BRANCH_HALT_VOTED, 1594 .hwcg_reg = 0x1706c, 1595 .hwcg_bit = 1, 1596 .clkr = { 1597 .enable_reg = 0x79004, 1598 .enable_mask = BIT(26), 1599 .hw.init = &(struct clk_init_data){ 1600 .name = "gcc_cam_throttle_rt_clk", 1601 .ops = &clk_branch2_ops, 1602 }, 1603 }, 1604 }; 1605 1606 static struct clk_branch gcc_camera_ahb_clk = { 1607 .halt_reg = 0x17008, 1608 .halt_check = BRANCH_HALT_DELAY, 1609 .hwcg_reg = 0x17008, 1610 .hwcg_bit = 1, 1611 .clkr = { 1612 .enable_reg = 0x17008, 1613 .enable_mask = BIT(0), 1614 .hw.init = &(struct clk_init_data){ 1615 .name = "gcc_camera_ahb_clk", 1616 .flags = CLK_IS_CRITICAL, 1617 .ops = &clk_branch2_ops, 1618 }, 1619 }, 1620 }; 1621 1622 static struct clk_branch gcc_camera_xo_clk = { 1623 .halt_reg = 0x17028, 1624 .halt_check = BRANCH_HALT, 1625 .clkr = { 1626 .enable_reg = 0x17028, 1627 .enable_mask = BIT(0), 1628 .hw.init = &(struct clk_init_data){ 1629 .name = "gcc_camera_xo_clk", 1630 .flags = CLK_IS_CRITICAL, 1631 .ops = &clk_branch2_ops, 1632 }, 1633 }, 1634 }; 1635 1636 static struct clk_branch gcc_camss_axi_clk = { 1637 .halt_reg = 0x58044, 1638 .halt_check = BRANCH_HALT, 1639 .clkr = { 1640 .enable_reg = 0x58044, 1641 .enable_mask = BIT(0), 1642 .hw.init = &(struct clk_init_data){ 1643 .name = "gcc_camss_axi_clk", 1644 .parent_hws = (const struct clk_hw *[]){ 1645 &gcc_camss_axi_clk_src.clkr.hw, 1646 }, 1647 .num_parents = 1, 1648 .flags = CLK_SET_RATE_PARENT, 1649 .ops = &clk_branch2_ops, 1650 }, 1651 }, 1652 }; 1653 1654 static struct clk_branch gcc_camss_camnoc_atb_clk = { 1655 .halt_reg = 0x5804c, 1656 .halt_check = BRANCH_HALT_DELAY, 1657 .hwcg_reg = 0x5804c, 1658 .hwcg_bit = 1, 1659 .clkr = { 1660 .enable_reg = 0x5804c, 1661 .enable_mask = BIT(0), 1662 .hw.init = &(struct clk_init_data){ 1663 .name = "gcc_camss_camnoc_atb_clk", 1664 .ops = &clk_branch2_ops, 1665 }, 1666 }, 1667 }; 1668 1669 static struct clk_branch gcc_camss_camnoc_nts_xo_clk = { 1670 .halt_reg = 0x58050, 1671 .halt_check = BRANCH_HALT_DELAY, 1672 .hwcg_reg = 0x58050, 1673 .hwcg_bit = 1, 1674 .clkr = { 1675 .enable_reg = 0x58050, 1676 .enable_mask = BIT(0), 1677 .hw.init = &(struct clk_init_data){ 1678 .name = "gcc_camss_camnoc_nts_xo_clk", 1679 .ops = &clk_branch2_ops, 1680 }, 1681 }, 1682 }; 1683 1684 static struct clk_branch gcc_camss_cci_0_clk = { 1685 .halt_reg = 0x56018, 1686 .halt_check = BRANCH_HALT, 1687 .clkr = { 1688 .enable_reg = 0x56018, 1689 .enable_mask = BIT(0), 1690 .hw.init = &(struct clk_init_data){ 1691 .name = "gcc_camss_cci_0_clk", 1692 .parent_hws = (const struct clk_hw *[]){ 1693 &gcc_camss_cci_clk_src.clkr.hw, 1694 }, 1695 .num_parents = 1, 1696 .flags = CLK_SET_RATE_PARENT, 1697 .ops = &clk_branch2_ops, 1698 }, 1699 }, 1700 }; 1701 1702 static struct clk_branch gcc_camss_cphy_0_clk = { 1703 .halt_reg = 0x52088, 1704 .halt_check = BRANCH_HALT, 1705 .clkr = { 1706 .enable_reg = 0x52088, 1707 .enable_mask = BIT(0), 1708 .hw.init = &(struct clk_init_data){ 1709 .name = "gcc_camss_cphy_0_clk", 1710 .parent_hws = (const struct clk_hw *[]){ 1711 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1712 }, 1713 .num_parents = 1, 1714 .flags = CLK_SET_RATE_PARENT, 1715 .ops = &clk_branch2_ops, 1716 }, 1717 }, 1718 }; 1719 1720 static struct clk_branch gcc_camss_cphy_1_clk = { 1721 .halt_reg = 0x5208c, 1722 .halt_check = BRANCH_HALT, 1723 .clkr = { 1724 .enable_reg = 0x5208c, 1725 .enable_mask = BIT(0), 1726 .hw.init = &(struct clk_init_data){ 1727 .name = "gcc_camss_cphy_1_clk", 1728 .parent_hws = (const struct clk_hw *[]){ 1729 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1730 }, 1731 .num_parents = 1, 1732 .flags = CLK_SET_RATE_PARENT, 1733 .ops = &clk_branch2_ops, 1734 }, 1735 }, 1736 }; 1737 1738 static struct clk_branch gcc_camss_cphy_2_clk = { 1739 .halt_reg = 0x52090, 1740 .halt_check = BRANCH_HALT, 1741 .clkr = { 1742 .enable_reg = 0x52090, 1743 .enable_mask = BIT(0), 1744 .hw.init = &(struct clk_init_data){ 1745 .name = "gcc_camss_cphy_2_clk", 1746 .parent_hws = (const struct clk_hw *[]){ 1747 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1748 }, 1749 .num_parents = 1, 1750 .flags = CLK_SET_RATE_PARENT, 1751 .ops = &clk_branch2_ops, 1752 }, 1753 }, 1754 }; 1755 1756 static struct clk_branch gcc_camss_csi0phytimer_clk = { 1757 .halt_reg = 0x59018, 1758 .halt_check = BRANCH_HALT, 1759 .clkr = { 1760 .enable_reg = 0x59018, 1761 .enable_mask = BIT(0), 1762 .hw.init = &(struct clk_init_data){ 1763 .name = "gcc_camss_csi0phytimer_clk", 1764 .parent_hws = (const struct clk_hw *[]){ 1765 &gcc_camss_csi0phytimer_clk_src.clkr.hw, 1766 }, 1767 .num_parents = 1, 1768 .flags = CLK_SET_RATE_PARENT, 1769 .ops = &clk_branch2_ops, 1770 }, 1771 }, 1772 }; 1773 1774 static struct clk_branch gcc_camss_csi1phytimer_clk = { 1775 .halt_reg = 0x59034, 1776 .halt_check = BRANCH_HALT, 1777 .clkr = { 1778 .enable_reg = 0x59034, 1779 .enable_mask = BIT(0), 1780 .hw.init = &(struct clk_init_data){ 1781 .name = "gcc_camss_csi1phytimer_clk", 1782 .parent_hws = (const struct clk_hw *[]){ 1783 &gcc_camss_csi1phytimer_clk_src.clkr.hw, 1784 }, 1785 .num_parents = 1, 1786 .flags = CLK_SET_RATE_PARENT, 1787 .ops = &clk_branch2_ops, 1788 }, 1789 }, 1790 }; 1791 1792 static struct clk_branch gcc_camss_csi2phytimer_clk = { 1793 .halt_reg = 0x59050, 1794 .halt_check = BRANCH_HALT, 1795 .clkr = { 1796 .enable_reg = 0x59050, 1797 .enable_mask = BIT(0), 1798 .hw.init = &(struct clk_init_data){ 1799 .name = "gcc_camss_csi2phytimer_clk", 1800 .parent_hws = (const struct clk_hw *[]){ 1801 &gcc_camss_csi2phytimer_clk_src.clkr.hw, 1802 }, 1803 .num_parents = 1, 1804 .flags = CLK_SET_RATE_PARENT, 1805 .ops = &clk_branch2_ops, 1806 }, 1807 }, 1808 }; 1809 1810 static struct clk_branch gcc_camss_mclk0_clk = { 1811 .halt_reg = 0x51018, 1812 .halt_check = BRANCH_HALT, 1813 .clkr = { 1814 .enable_reg = 0x51018, 1815 .enable_mask = BIT(0), 1816 .hw.init = &(struct clk_init_data){ 1817 .name = "gcc_camss_mclk0_clk", 1818 .parent_hws = (const struct clk_hw *[]){ 1819 &gcc_camss_mclk0_clk_src.clkr.hw, 1820 }, 1821 .num_parents = 1, 1822 .flags = CLK_SET_RATE_PARENT, 1823 .ops = &clk_branch2_ops, 1824 }, 1825 }, 1826 }; 1827 1828 static struct clk_branch gcc_camss_mclk1_clk = { 1829 .halt_reg = 0x51034, 1830 .halt_check = BRANCH_HALT, 1831 .clkr = { 1832 .enable_reg = 0x51034, 1833 .enable_mask = BIT(0), 1834 .hw.init = &(struct clk_init_data){ 1835 .name = "gcc_camss_mclk1_clk", 1836 .parent_hws = (const struct clk_hw *[]){ 1837 &gcc_camss_mclk1_clk_src.clkr.hw, 1838 }, 1839 .num_parents = 1, 1840 .flags = CLK_SET_RATE_PARENT, 1841 .ops = &clk_branch2_ops, 1842 }, 1843 }, 1844 }; 1845 1846 static struct clk_branch gcc_camss_mclk2_clk = { 1847 .halt_reg = 0x51050, 1848 .halt_check = BRANCH_HALT, 1849 .clkr = { 1850 .enable_reg = 0x51050, 1851 .enable_mask = BIT(0), 1852 .hw.init = &(struct clk_init_data){ 1853 .name = "gcc_camss_mclk2_clk", 1854 .parent_hws = (const struct clk_hw *[]){ 1855 &gcc_camss_mclk2_clk_src.clkr.hw, 1856 }, 1857 .num_parents = 1, 1858 .flags = CLK_SET_RATE_PARENT, 1859 .ops = &clk_branch2_ops, 1860 }, 1861 }, 1862 }; 1863 1864 static struct clk_branch gcc_camss_mclk3_clk = { 1865 .halt_reg = 0x5106c, 1866 .halt_check = BRANCH_HALT, 1867 .clkr = { 1868 .enable_reg = 0x5106c, 1869 .enable_mask = BIT(0), 1870 .hw.init = &(struct clk_init_data){ 1871 .name = "gcc_camss_mclk3_clk", 1872 .parent_hws = (const struct clk_hw *[]){ 1873 &gcc_camss_mclk3_clk_src.clkr.hw, 1874 }, 1875 .num_parents = 1, 1876 .flags = CLK_SET_RATE_PARENT, 1877 .ops = &clk_branch2_ops, 1878 }, 1879 }, 1880 }; 1881 1882 static struct clk_branch gcc_camss_nrt_axi_clk = { 1883 .halt_reg = 0x58054, 1884 .halt_check = BRANCH_HALT, 1885 .clkr = { 1886 .enable_reg = 0x58054, 1887 .enable_mask = BIT(0), 1888 .hw.init = &(struct clk_init_data){ 1889 .name = "gcc_camss_nrt_axi_clk", 1890 .ops = &clk_branch2_ops, 1891 }, 1892 }, 1893 }; 1894 1895 static struct clk_branch gcc_camss_ope_ahb_clk = { 1896 .halt_reg = 0x5503c, 1897 .halt_check = BRANCH_HALT, 1898 .clkr = { 1899 .enable_reg = 0x5503c, 1900 .enable_mask = BIT(0), 1901 .hw.init = &(struct clk_init_data){ 1902 .name = "gcc_camss_ope_ahb_clk", 1903 .parent_hws = (const struct clk_hw *[]){ 1904 &gcc_camss_ope_ahb_clk_src.clkr.hw, 1905 }, 1906 .num_parents = 1, 1907 .flags = CLK_SET_RATE_PARENT, 1908 .ops = &clk_branch2_ops, 1909 }, 1910 }, 1911 }; 1912 1913 static struct clk_branch gcc_camss_ope_clk = { 1914 .halt_reg = 0x5501c, 1915 .halt_check = BRANCH_HALT, 1916 .clkr = { 1917 .enable_reg = 0x5501c, 1918 .enable_mask = BIT(0), 1919 .hw.init = &(struct clk_init_data){ 1920 .name = "gcc_camss_ope_clk", 1921 .parent_hws = (const struct clk_hw *[]){ 1922 &gcc_camss_ope_clk_src.clkr.hw, 1923 }, 1924 .num_parents = 1, 1925 .flags = CLK_SET_RATE_PARENT, 1926 .ops = &clk_branch2_ops, 1927 }, 1928 }, 1929 }; 1930 1931 static struct clk_branch gcc_camss_rt_axi_clk = { 1932 .halt_reg = 0x5805c, 1933 .halt_check = BRANCH_HALT, 1934 .clkr = { 1935 .enable_reg = 0x5805c, 1936 .enable_mask = BIT(0), 1937 .hw.init = &(struct clk_init_data){ 1938 .name = "gcc_camss_rt_axi_clk", 1939 .ops = &clk_branch2_ops, 1940 }, 1941 }, 1942 }; 1943 1944 static struct clk_branch gcc_camss_tfe_0_clk = { 1945 .halt_reg = 0x5201c, 1946 .halt_check = BRANCH_HALT, 1947 .clkr = { 1948 .enable_reg = 0x5201c, 1949 .enable_mask = BIT(0), 1950 .hw.init = &(struct clk_init_data){ 1951 .name = "gcc_camss_tfe_0_clk", 1952 .parent_hws = (const struct clk_hw *[]){ 1953 &gcc_camss_tfe_0_clk_src.clkr.hw, 1954 }, 1955 .num_parents = 1, 1956 .flags = CLK_SET_RATE_PARENT, 1957 .ops = &clk_branch2_ops, 1958 }, 1959 }, 1960 }; 1961 1962 static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = { 1963 .halt_reg = 0x5207c, 1964 .halt_check = BRANCH_HALT, 1965 .clkr = { 1966 .enable_reg = 0x5207c, 1967 .enable_mask = BIT(0), 1968 .hw.init = &(struct clk_init_data){ 1969 .name = "gcc_camss_tfe_0_cphy_rx_clk", 1970 .parent_hws = (const struct clk_hw *[]){ 1971 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1972 }, 1973 .num_parents = 1, 1974 .flags = CLK_SET_RATE_PARENT, 1975 .ops = &clk_branch2_ops, 1976 }, 1977 }, 1978 }; 1979 1980 static struct clk_branch gcc_camss_tfe_0_csid_clk = { 1981 .halt_reg = 0x520ac, 1982 .halt_check = BRANCH_HALT, 1983 .clkr = { 1984 .enable_reg = 0x520ac, 1985 .enable_mask = BIT(0), 1986 .hw.init = &(struct clk_init_data){ 1987 .name = "gcc_camss_tfe_0_csid_clk", 1988 .parent_hws = (const struct clk_hw *[]){ 1989 &gcc_camss_tfe_0_csid_clk_src.clkr.hw, 1990 }, 1991 .num_parents = 1, 1992 .flags = CLK_SET_RATE_PARENT, 1993 .ops = &clk_branch2_ops, 1994 }, 1995 }, 1996 }; 1997 1998 static struct clk_branch gcc_camss_tfe_1_clk = { 1999 .halt_reg = 0x5203c, 2000 .halt_check = BRANCH_HALT, 2001 .clkr = { 2002 .enable_reg = 0x5203c, 2003 .enable_mask = BIT(0), 2004 .hw.init = &(struct clk_init_data){ 2005 .name = "gcc_camss_tfe_1_clk", 2006 .parent_hws = (const struct clk_hw *[]){ 2007 &gcc_camss_tfe_1_clk_src.clkr.hw, 2008 }, 2009 .num_parents = 1, 2010 .flags = CLK_SET_RATE_PARENT, 2011 .ops = &clk_branch2_ops, 2012 }, 2013 }, 2014 }; 2015 2016 static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = { 2017 .halt_reg = 0x52080, 2018 .halt_check = BRANCH_HALT, 2019 .clkr = { 2020 .enable_reg = 0x52080, 2021 .enable_mask = BIT(0), 2022 .hw.init = &(struct clk_init_data){ 2023 .name = "gcc_camss_tfe_1_cphy_rx_clk", 2024 .parent_hws = (const struct clk_hw *[]){ 2025 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2026 }, 2027 .num_parents = 1, 2028 .flags = CLK_SET_RATE_PARENT, 2029 .ops = &clk_branch2_ops, 2030 }, 2031 }, 2032 }; 2033 2034 static struct clk_branch gcc_camss_tfe_1_csid_clk = { 2035 .halt_reg = 0x520cc, 2036 .halt_check = BRANCH_HALT, 2037 .clkr = { 2038 .enable_reg = 0x520cc, 2039 .enable_mask = BIT(0), 2040 .hw.init = &(struct clk_init_data){ 2041 .name = "gcc_camss_tfe_1_csid_clk", 2042 .parent_hws = (const struct clk_hw *[]){ 2043 &gcc_camss_tfe_1_csid_clk_src.clkr.hw, 2044 }, 2045 .num_parents = 1, 2046 .flags = CLK_SET_RATE_PARENT, 2047 .ops = &clk_branch2_ops, 2048 }, 2049 }, 2050 }; 2051 2052 static struct clk_branch gcc_camss_tfe_2_clk = { 2053 .halt_reg = 0x5205c, 2054 .halt_check = BRANCH_HALT, 2055 .clkr = { 2056 .enable_reg = 0x5205c, 2057 .enable_mask = BIT(0), 2058 .hw.init = &(struct clk_init_data){ 2059 .name = "gcc_camss_tfe_2_clk", 2060 .parent_hws = (const struct clk_hw *[]){ 2061 &gcc_camss_tfe_2_clk_src.clkr.hw, 2062 }, 2063 .num_parents = 1, 2064 .flags = CLK_SET_RATE_PARENT, 2065 .ops = &clk_branch2_ops, 2066 }, 2067 }, 2068 }; 2069 2070 static struct clk_branch gcc_camss_tfe_2_cphy_rx_clk = { 2071 .halt_reg = 0x52084, 2072 .halt_check = BRANCH_HALT, 2073 .clkr = { 2074 .enable_reg = 0x52084, 2075 .enable_mask = BIT(0), 2076 .hw.init = &(struct clk_init_data){ 2077 .name = "gcc_camss_tfe_2_cphy_rx_clk", 2078 .parent_hws = (const struct clk_hw *[]){ 2079 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2080 }, 2081 .num_parents = 1, 2082 .flags = CLK_SET_RATE_PARENT, 2083 .ops = &clk_branch2_ops, 2084 }, 2085 }, 2086 }; 2087 2088 static struct clk_branch gcc_camss_tfe_2_csid_clk = { 2089 .halt_reg = 0x520ec, 2090 .halt_check = BRANCH_HALT, 2091 .clkr = { 2092 .enable_reg = 0x520ec, 2093 .enable_mask = BIT(0), 2094 .hw.init = &(struct clk_init_data){ 2095 .name = "gcc_camss_tfe_2_csid_clk", 2096 .parent_hws = (const struct clk_hw *[]){ 2097 &gcc_camss_tfe_2_csid_clk_src.clkr.hw, 2098 }, 2099 .num_parents = 1, 2100 .flags = CLK_SET_RATE_PARENT, 2101 .ops = &clk_branch2_ops, 2102 }, 2103 }, 2104 }; 2105 2106 static struct clk_branch gcc_camss_top_ahb_clk = { 2107 .halt_reg = 0x58028, 2108 .halt_check = BRANCH_HALT, 2109 .clkr = { 2110 .enable_reg = 0x58028, 2111 .enable_mask = BIT(0), 2112 .hw.init = &(struct clk_init_data){ 2113 .name = "gcc_camss_top_ahb_clk", 2114 .parent_hws = (const struct clk_hw *[]){ 2115 &gcc_camss_top_ahb_clk_src.clkr.hw, 2116 }, 2117 .num_parents = 1, 2118 .flags = CLK_SET_RATE_PARENT, 2119 .ops = &clk_branch2_ops, 2120 }, 2121 }, 2122 }; 2123 2124 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 2125 .halt_reg = 0x1a084, 2126 .halt_check = BRANCH_HALT, 2127 .hwcg_reg = 0x1a084, 2128 .hwcg_bit = 1, 2129 .clkr = { 2130 .enable_reg = 0x1a084, 2131 .enable_mask = BIT(0), 2132 .hw.init = &(struct clk_init_data){ 2133 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 2134 .parent_hws = (const struct clk_hw *[]){ 2135 &gcc_usb30_prim_master_clk_src.clkr.hw, 2136 }, 2137 .num_parents = 1, 2138 .flags = CLK_SET_RATE_PARENT, 2139 .ops = &clk_branch2_ops, 2140 }, 2141 }, 2142 }; 2143 2144 static struct clk_branch gcc_cpuss_gnoc_clk = { 2145 .halt_reg = 0x2b004, 2146 .halt_check = BRANCH_HALT_VOTED, 2147 .hwcg_reg = 0x2b004, 2148 .hwcg_bit = 1, 2149 .clkr = { 2150 .enable_reg = 0x79004, 2151 .enable_mask = BIT(22), 2152 .hw.init = &(struct clk_init_data){ 2153 .name = "gcc_cpuss_gnoc_clk", 2154 .flags = CLK_IS_CRITICAL, 2155 .ops = &clk_branch2_ops, 2156 }, 2157 }, 2158 }; 2159 2160 static struct clk_branch gcc_disp_ahb_clk = { 2161 .halt_reg = 0x1700c, 2162 .halt_check = BRANCH_HALT, 2163 .hwcg_reg = 0x1700c, 2164 .hwcg_bit = 1, 2165 .clkr = { 2166 .enable_reg = 0x1700c, 2167 .enable_mask = BIT(0), 2168 .hw.init = &(struct clk_init_data){ 2169 .name = "gcc_disp_ahb_clk", 2170 .flags = CLK_IS_CRITICAL, 2171 .ops = &clk_branch2_ops, 2172 }, 2173 }, 2174 }; 2175 2176 static struct clk_regmap_div gcc_disp_gpll0_clk_src = { 2177 .reg = 0x17058, 2178 .shift = 0, 2179 .width = 2, 2180 .clkr.hw.init = &(struct clk_init_data) { 2181 .name = "gcc_disp_gpll0_clk_src", 2182 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 2183 .num_parents = 1, 2184 .ops = &clk_regmap_div_ops, 2185 }, 2186 }; 2187 2188 static struct clk_branch gcc_disp_gpll0_div_clk_src = { 2189 .halt_check = BRANCH_HALT_DELAY, 2190 .clkr = { 2191 .enable_reg = 0x79004, 2192 .enable_mask = BIT(20), 2193 .hw.init = &(struct clk_init_data){ 2194 .name = "gcc_disp_gpll0_div_clk_src", 2195 .parent_hws = (const struct clk_hw *[]){ 2196 &gcc_disp_gpll0_clk_src.clkr.hw, 2197 }, 2198 .num_parents = 1, 2199 .flags = CLK_SET_RATE_PARENT, 2200 .ops = &clk_branch2_ops, 2201 }, 2202 }, 2203 }; 2204 2205 static struct clk_branch gcc_disp_hf_axi_clk = { 2206 .halt_reg = 0x17020, 2207 .halt_check = BRANCH_HALT, 2208 .hwcg_reg = 0x17020, 2209 .hwcg_bit = 1, 2210 .clkr = { 2211 .enable_reg = 0x17020, 2212 .enable_mask = BIT(0), 2213 .hw.init = &(struct clk_init_data){ 2214 .name = "gcc_disp_hf_axi_clk", 2215 .ops = &clk_branch2_ops, 2216 }, 2217 }, 2218 }; 2219 2220 static struct clk_branch gcc_disp_throttle_core_clk = { 2221 .halt_reg = 0x17064, 2222 .halt_check = BRANCH_HALT_VOTED, 2223 .hwcg_reg = 0x17064, 2224 .hwcg_bit = 1, 2225 .clkr = { 2226 .enable_reg = 0x7900c, 2227 .enable_mask = BIT(5), 2228 .hw.init = &(struct clk_init_data){ 2229 .name = "gcc_disp_throttle_core_clk", 2230 .ops = &clk_branch2_ops, 2231 }, 2232 }, 2233 }; 2234 2235 static struct clk_branch gcc_disp_xo_clk = { 2236 .halt_reg = 0x1702c, 2237 .halt_check = BRANCH_HALT, 2238 .clkr = { 2239 .enable_reg = 0x1702c, 2240 .enable_mask = BIT(0), 2241 .hw.init = &(struct clk_init_data){ 2242 .name = "gcc_disp_xo_clk", 2243 .flags = CLK_IS_CRITICAL, 2244 .ops = &clk_branch2_ops, 2245 }, 2246 }, 2247 }; 2248 2249 static struct clk_branch gcc_gp1_clk = { 2250 .halt_reg = 0x4d000, 2251 .halt_check = BRANCH_HALT, 2252 .clkr = { 2253 .enable_reg = 0x4d000, 2254 .enable_mask = BIT(0), 2255 .hw.init = &(struct clk_init_data){ 2256 .name = "gcc_gp1_clk", 2257 .parent_hws = (const struct clk_hw *[]){ 2258 &gcc_gp1_clk_src.clkr.hw, 2259 }, 2260 .num_parents = 1, 2261 .flags = CLK_SET_RATE_PARENT, 2262 .ops = &clk_branch2_ops, 2263 }, 2264 }, 2265 }; 2266 2267 static struct clk_branch gcc_gp2_clk = { 2268 .halt_reg = 0x4e000, 2269 .halt_check = BRANCH_HALT, 2270 .clkr = { 2271 .enable_reg = 0x4e000, 2272 .enable_mask = BIT(0), 2273 .hw.init = &(struct clk_init_data){ 2274 .name = "gcc_gp2_clk", 2275 .parent_hws = (const struct clk_hw *[]){ 2276 &gcc_gp2_clk_src.clkr.hw, 2277 }, 2278 .num_parents = 1, 2279 .flags = CLK_SET_RATE_PARENT, 2280 .ops = &clk_branch2_ops, 2281 }, 2282 }, 2283 }; 2284 2285 static struct clk_branch gcc_gp3_clk = { 2286 .halt_reg = 0x4f000, 2287 .halt_check = BRANCH_HALT, 2288 .clkr = { 2289 .enable_reg = 0x4f000, 2290 .enable_mask = BIT(0), 2291 .hw.init = &(struct clk_init_data){ 2292 .name = "gcc_gp3_clk", 2293 .parent_hws = (const struct clk_hw *[]){ 2294 &gcc_gp3_clk_src.clkr.hw, 2295 }, 2296 .num_parents = 1, 2297 .flags = CLK_SET_RATE_PARENT, 2298 .ops = &clk_branch2_ops, 2299 }, 2300 }, 2301 }; 2302 2303 static struct clk_branch gcc_gpu_cfg_ahb_clk = { 2304 .halt_reg = 0x36004, 2305 .halt_check = BRANCH_HALT, 2306 .hwcg_reg = 0x36004, 2307 .hwcg_bit = 1, 2308 .clkr = { 2309 .enable_reg = 0x36004, 2310 .enable_mask = BIT(0), 2311 .hw.init = &(struct clk_init_data){ 2312 .name = "gcc_gpu_cfg_ahb_clk", 2313 .flags = CLK_IS_CRITICAL, 2314 .ops = &clk_branch2_ops, 2315 }, 2316 }, 2317 }; 2318 2319 static struct clk_branch gcc_gpu_gpll0_clk_src = { 2320 .halt_check = BRANCH_HALT_DELAY, 2321 .clkr = { 2322 .enable_reg = 0x79004, 2323 .enable_mask = BIT(15), 2324 .hw.init = &(struct clk_init_data){ 2325 .name = "gcc_gpu_gpll0_clk_src", 2326 .parent_hws = (const struct clk_hw *[]){ 2327 &gpll0.clkr.hw, 2328 }, 2329 .num_parents = 1, 2330 .flags = CLK_SET_RATE_PARENT, 2331 .ops = &clk_branch2_ops, 2332 }, 2333 }, 2334 }; 2335 2336 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 2337 .halt_check = BRANCH_HALT_DELAY, 2338 .clkr = { 2339 .enable_reg = 0x79004, 2340 .enable_mask = BIT(16), 2341 .hw.init = &(struct clk_init_data){ 2342 .name = "gcc_gpu_gpll0_div_clk_src", 2343 .parent_hws = (const struct clk_hw *[]){ 2344 &gpll0_out_aux2.clkr.hw, 2345 }, 2346 .num_parents = 1, 2347 .flags = CLK_SET_RATE_PARENT, 2348 .ops = &clk_branch2_ops, 2349 }, 2350 }, 2351 }; 2352 2353 static struct clk_branch gcc_gpu_iref_clk = { 2354 .halt_reg = 0x36100, 2355 .halt_check = BRANCH_HALT_DELAY, 2356 .clkr = { 2357 .enable_reg = 0x36100, 2358 .enable_mask = BIT(0), 2359 .hw.init = &(struct clk_init_data){ 2360 .name = "gcc_gpu_iref_clk", 2361 .ops = &clk_branch2_ops, 2362 }, 2363 }, 2364 }; 2365 2366 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 2367 .halt_reg = 0x3600c, 2368 .halt_check = BRANCH_VOTED, 2369 .hwcg_reg = 0x3600c, 2370 .hwcg_bit = 1, 2371 .clkr = { 2372 .enable_reg = 0x3600c, 2373 .enable_mask = BIT(0), 2374 .hw.init = &(struct clk_init_data){ 2375 .name = "gcc_gpu_memnoc_gfx_clk", 2376 .ops = &clk_branch2_ops, 2377 }, 2378 }, 2379 }; 2380 2381 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2382 .halt_reg = 0x36018, 2383 .halt_check = BRANCH_HALT, 2384 .clkr = { 2385 .enable_reg = 0x36018, 2386 .enable_mask = BIT(0), 2387 .hw.init = &(struct clk_init_data){ 2388 .name = "gcc_gpu_snoc_dvm_gfx_clk", 2389 .ops = &clk_branch2_ops, 2390 }, 2391 }, 2392 }; 2393 2394 static struct clk_branch gcc_gpu_throttle_core_clk = { 2395 .halt_reg = 0x36048, 2396 .halt_check = BRANCH_HALT_VOTED, 2397 .hwcg_reg = 0x36048, 2398 .hwcg_bit = 1, 2399 .clkr = { 2400 .enable_reg = 0x79004, 2401 .enable_mask = BIT(31), 2402 .hw.init = &(struct clk_init_data){ 2403 .name = "gcc_gpu_throttle_core_clk", 2404 .ops = &clk_branch2_ops, 2405 }, 2406 }, 2407 }; 2408 2409 static struct clk_branch gcc_pdm2_clk = { 2410 .halt_reg = 0x2000c, 2411 .halt_check = BRANCH_HALT, 2412 .clkr = { 2413 .enable_reg = 0x2000c, 2414 .enable_mask = BIT(0), 2415 .hw.init = &(struct clk_init_data){ 2416 .name = "gcc_pdm2_clk", 2417 .parent_hws = (const struct clk_hw *[]){ 2418 &gcc_pdm2_clk_src.clkr.hw, 2419 }, 2420 .num_parents = 1, 2421 .flags = CLK_SET_RATE_PARENT, 2422 .ops = &clk_branch2_ops, 2423 }, 2424 }, 2425 }; 2426 2427 static struct clk_branch gcc_pdm_ahb_clk = { 2428 .halt_reg = 0x20004, 2429 .halt_check = BRANCH_HALT, 2430 .hwcg_reg = 0x20004, 2431 .hwcg_bit = 1, 2432 .clkr = { 2433 .enable_reg = 0x20004, 2434 .enable_mask = BIT(0), 2435 .hw.init = &(struct clk_init_data){ 2436 .name = "gcc_pdm_ahb_clk", 2437 .ops = &clk_branch2_ops, 2438 }, 2439 }, 2440 }; 2441 2442 static struct clk_branch gcc_pdm_xo4_clk = { 2443 .halt_reg = 0x20008, 2444 .halt_check = BRANCH_HALT, 2445 .clkr = { 2446 .enable_reg = 0x20008, 2447 .enable_mask = BIT(0), 2448 .hw.init = &(struct clk_init_data){ 2449 .name = "gcc_pdm_xo4_clk", 2450 .ops = &clk_branch2_ops, 2451 }, 2452 }, 2453 }; 2454 2455 static struct clk_branch gcc_prng_ahb_clk = { 2456 .halt_reg = 0x21004, 2457 .halt_check = BRANCH_HALT_VOTED, 2458 .hwcg_reg = 0x21004, 2459 .hwcg_bit = 1, 2460 .clkr = { 2461 .enable_reg = 0x79004, 2462 .enable_mask = BIT(13), 2463 .hw.init = &(struct clk_init_data){ 2464 .name = "gcc_prng_ahb_clk", 2465 .ops = &clk_branch2_ops, 2466 }, 2467 }, 2468 }; 2469 2470 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2471 .halt_reg = 0x17014, 2472 .halt_check = BRANCH_HALT_VOTED, 2473 .hwcg_reg = 0x17014, 2474 .hwcg_bit = 1, 2475 .clkr = { 2476 .enable_reg = 0x7900c, 2477 .enable_mask = BIT(0), 2478 .hw.init = &(struct clk_init_data){ 2479 .name = "gcc_qmip_camera_nrt_ahb_clk", 2480 .ops = &clk_branch2_ops, 2481 }, 2482 }, 2483 }; 2484 2485 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2486 .halt_reg = 0x17060, 2487 .halt_check = BRANCH_HALT_VOTED, 2488 .hwcg_reg = 0x17060, 2489 .hwcg_bit = 1, 2490 .clkr = { 2491 .enable_reg = 0x7900c, 2492 .enable_mask = BIT(2), 2493 .hw.init = &(struct clk_init_data){ 2494 .name = "gcc_qmip_camera_rt_ahb_clk", 2495 .ops = &clk_branch2_ops, 2496 }, 2497 }, 2498 }; 2499 2500 static struct clk_branch gcc_qmip_disp_ahb_clk = { 2501 .halt_reg = 0x17018, 2502 .halt_check = BRANCH_HALT_VOTED, 2503 .hwcg_reg = 0x17018, 2504 .hwcg_bit = 1, 2505 .clkr = { 2506 .enable_reg = 0x7900c, 2507 .enable_mask = BIT(1), 2508 .hw.init = &(struct clk_init_data){ 2509 .name = "gcc_qmip_disp_ahb_clk", 2510 .ops = &clk_branch2_ops, 2511 }, 2512 }, 2513 }; 2514 2515 static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = { 2516 .halt_reg = 0x36040, 2517 .halt_check = BRANCH_HALT_VOTED, 2518 .hwcg_reg = 0x36040, 2519 .hwcg_bit = 1, 2520 .clkr = { 2521 .enable_reg = 0x7900c, 2522 .enable_mask = BIT(4), 2523 .hw.init = &(struct clk_init_data){ 2524 .name = "gcc_qmip_gpu_cfg_ahb_clk", 2525 .ops = &clk_branch2_ops, 2526 }, 2527 }, 2528 }; 2529 2530 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2531 .halt_reg = 0x17010, 2532 .halt_check = BRANCH_HALT_VOTED, 2533 .hwcg_reg = 0x17010, 2534 .hwcg_bit = 1, 2535 .clkr = { 2536 .enable_reg = 0x79004, 2537 .enable_mask = BIT(25), 2538 .hw.init = &(struct clk_init_data){ 2539 .name = "gcc_qmip_video_vcodec_ahb_clk", 2540 .ops = &clk_branch2_ops, 2541 }, 2542 }, 2543 }; 2544 2545 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2546 .halt_reg = 0x1f014, 2547 .halt_check = BRANCH_HALT_VOTED, 2548 .clkr = { 2549 .enable_reg = 0x7900c, 2550 .enable_mask = BIT(9), 2551 .hw.init = &(struct clk_init_data){ 2552 .name = "gcc_qupv3_wrap0_core_2x_clk", 2553 .ops = &clk_branch2_ops, 2554 }, 2555 }, 2556 }; 2557 2558 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2559 .halt_reg = 0x1f00c, 2560 .halt_check = BRANCH_HALT_VOTED, 2561 .clkr = { 2562 .enable_reg = 0x7900c, 2563 .enable_mask = BIT(8), 2564 .hw.init = &(struct clk_init_data){ 2565 .name = "gcc_qupv3_wrap0_core_clk", 2566 .ops = &clk_branch2_ops, 2567 }, 2568 }, 2569 }; 2570 2571 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2572 .halt_reg = 0x1f144, 2573 .halt_check = BRANCH_HALT_VOTED, 2574 .clkr = { 2575 .enable_reg = 0x7900c, 2576 .enable_mask = BIT(10), 2577 .hw.init = &(struct clk_init_data){ 2578 .name = "gcc_qupv3_wrap0_s0_clk", 2579 .parent_hws = (const struct clk_hw *[]){ 2580 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 2581 }, 2582 .num_parents = 1, 2583 .flags = CLK_SET_RATE_PARENT, 2584 .ops = &clk_branch2_ops, 2585 }, 2586 }, 2587 }; 2588 2589 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2590 .halt_reg = 0x1f274, 2591 .halt_check = BRANCH_HALT_VOTED, 2592 .clkr = { 2593 .enable_reg = 0x7900c, 2594 .enable_mask = BIT(11), 2595 .hw.init = &(struct clk_init_data){ 2596 .name = "gcc_qupv3_wrap0_s1_clk", 2597 .parent_hws = (const struct clk_hw *[]){ 2598 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 2599 }, 2600 .num_parents = 1, 2601 .flags = CLK_SET_RATE_PARENT, 2602 .ops = &clk_branch2_ops, 2603 }, 2604 }, 2605 }; 2606 2607 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2608 .halt_reg = 0x1f3a4, 2609 .halt_check = BRANCH_HALT_VOTED, 2610 .clkr = { 2611 .enable_reg = 0x7900c, 2612 .enable_mask = BIT(12), 2613 .hw.init = &(struct clk_init_data){ 2614 .name = "gcc_qupv3_wrap0_s2_clk", 2615 .parent_hws = (const struct clk_hw *[]){ 2616 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2617 }, 2618 .num_parents = 1, 2619 .flags = CLK_SET_RATE_PARENT, 2620 .ops = &clk_branch2_ops, 2621 }, 2622 }, 2623 }; 2624 2625 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2626 .halt_reg = 0x1f4d4, 2627 .halt_check = BRANCH_HALT_VOTED, 2628 .clkr = { 2629 .enable_reg = 0x7900c, 2630 .enable_mask = BIT(13), 2631 .hw.init = &(struct clk_init_data){ 2632 .name = "gcc_qupv3_wrap0_s3_clk", 2633 .parent_hws = (const struct clk_hw *[]){ 2634 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2635 }, 2636 .num_parents = 1, 2637 .flags = CLK_SET_RATE_PARENT, 2638 .ops = &clk_branch2_ops, 2639 }, 2640 }, 2641 }; 2642 2643 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2644 .halt_reg = 0x1f604, 2645 .halt_check = BRANCH_HALT_VOTED, 2646 .clkr = { 2647 .enable_reg = 0x7900c, 2648 .enable_mask = BIT(14), 2649 .hw.init = &(struct clk_init_data){ 2650 .name = "gcc_qupv3_wrap0_s4_clk", 2651 .parent_hws = (const struct clk_hw *[]){ 2652 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2653 }, 2654 .num_parents = 1, 2655 .flags = CLK_SET_RATE_PARENT, 2656 .ops = &clk_branch2_ops, 2657 }, 2658 }, 2659 }; 2660 2661 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2662 .halt_reg = 0x1f734, 2663 .halt_check = BRANCH_HALT_VOTED, 2664 .clkr = { 2665 .enable_reg = 0x7900c, 2666 .enable_mask = BIT(15), 2667 .hw.init = &(struct clk_init_data){ 2668 .name = "gcc_qupv3_wrap0_s5_clk", 2669 .parent_hws = (const struct clk_hw *[]){ 2670 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2671 }, 2672 .num_parents = 1, 2673 .flags = CLK_SET_RATE_PARENT, 2674 .ops = &clk_branch2_ops, 2675 }, 2676 }, 2677 }; 2678 2679 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2680 .halt_reg = 0x1f004, 2681 .halt_check = BRANCH_HALT_VOTED, 2682 .hwcg_reg = 0x1f004, 2683 .hwcg_bit = 1, 2684 .clkr = { 2685 .enable_reg = 0x7900c, 2686 .enable_mask = BIT(6), 2687 .hw.init = &(struct clk_init_data){ 2688 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2689 .ops = &clk_branch2_ops, 2690 }, 2691 }, 2692 }; 2693 2694 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2695 .halt_reg = 0x1f008, 2696 .halt_check = BRANCH_HALT_VOTED, 2697 .hwcg_reg = 0x1f008, 2698 .hwcg_bit = 1, 2699 .clkr = { 2700 .enable_reg = 0x7900c, 2701 .enable_mask = BIT(7), 2702 .hw.init = &(struct clk_init_data){ 2703 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2704 .ops = &clk_branch2_ops, 2705 }, 2706 }, 2707 }; 2708 2709 static struct clk_branch gcc_sdcc1_ahb_clk = { 2710 .halt_reg = 0x38008, 2711 .halt_check = BRANCH_HALT, 2712 .clkr = { 2713 .enable_reg = 0x38008, 2714 .enable_mask = BIT(0), 2715 .hw.init = &(struct clk_init_data){ 2716 .name = "gcc_sdcc1_ahb_clk", 2717 .ops = &clk_branch2_ops, 2718 }, 2719 }, 2720 }; 2721 2722 static struct clk_branch gcc_sdcc1_apps_clk = { 2723 .halt_reg = 0x38004, 2724 .halt_check = BRANCH_HALT, 2725 .clkr = { 2726 .enable_reg = 0x38004, 2727 .enable_mask = BIT(0), 2728 .hw.init = &(struct clk_init_data){ 2729 .name = "gcc_sdcc1_apps_clk", 2730 .parent_hws = (const struct clk_hw *[]){ 2731 &gcc_sdcc1_apps_clk_src.clkr.hw, 2732 }, 2733 .num_parents = 1, 2734 .flags = CLK_SET_RATE_PARENT /* | CLK_ENABLE_HAND_OFF */, 2735 .ops = &clk_branch2_ops, 2736 }, 2737 }, 2738 }; 2739 2740 static struct clk_branch gcc_sdcc1_ice_core_clk = { 2741 .halt_reg = 0x3800c, 2742 .halt_check = BRANCH_HALT, 2743 .hwcg_reg = 0x3800c, 2744 .hwcg_bit = 1, 2745 .clkr = { 2746 .enable_reg = 0x3800c, 2747 .enable_mask = BIT(0), 2748 .hw.init = &(struct clk_init_data){ 2749 .name = "gcc_sdcc1_ice_core_clk", 2750 .parent_hws = (const struct clk_hw *[]){ 2751 &gcc_sdcc1_ice_core_clk_src.clkr.hw, 2752 }, 2753 .num_parents = 1, 2754 .flags = CLK_SET_RATE_PARENT, 2755 .ops = &clk_branch2_ops, 2756 }, 2757 }, 2758 }; 2759 2760 static struct clk_branch gcc_sdcc2_ahb_clk = { 2761 .halt_reg = 0x1e008, 2762 .halt_check = BRANCH_HALT, 2763 .clkr = { 2764 .enable_reg = 0x1e008, 2765 .enable_mask = BIT(0), 2766 .hw.init = &(struct clk_init_data){ 2767 .name = "gcc_sdcc2_ahb_clk", 2768 .ops = &clk_branch2_ops, 2769 }, 2770 }, 2771 }; 2772 2773 static struct clk_branch gcc_sdcc2_apps_clk = { 2774 .halt_reg = 0x1e004, 2775 .halt_check = BRANCH_HALT, 2776 .clkr = { 2777 .enable_reg = 0x1e004, 2778 .enable_mask = BIT(0), 2779 .hw.init = &(struct clk_init_data){ 2780 .name = "gcc_sdcc2_apps_clk", 2781 .parent_hws = (const struct clk_hw *[]){ 2782 &gcc_sdcc2_apps_clk_src.clkr.hw, 2783 }, 2784 .num_parents = 1, 2785 .flags = CLK_SET_RATE_PARENT, 2786 .ops = &clk_branch2_ops, 2787 }, 2788 }, 2789 }; 2790 2791 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 2792 .halt_reg = 0x2b06c, 2793 .halt_check = BRANCH_HALT_VOTED, 2794 .hwcg_reg = 0x2b06c, 2795 .hwcg_bit = 1, 2796 .clkr = { 2797 .enable_reg = 0x79004, 2798 .enable_mask = BIT(0), 2799 .hw.init = &(struct clk_init_data){ 2800 .name = "gcc_sys_noc_cpuss_ahb_clk", 2801 .flags = CLK_IS_CRITICAL, 2802 .ops = &clk_branch2_ops, 2803 }, 2804 }, 2805 }; 2806 2807 static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { 2808 .halt_reg = 0x45098, 2809 .halt_check = BRANCH_HALT, 2810 .clkr = { 2811 .enable_reg = 0x45098, 2812 .enable_mask = BIT(0), 2813 .hw.init = &(struct clk_init_data){ 2814 .name = "gcc_sys_noc_ufs_phy_axi_clk", 2815 .parent_hws = (const struct clk_hw *[]){ 2816 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2817 }, 2818 .num_parents = 1, 2819 .flags = CLK_SET_RATE_PARENT, 2820 .ops = &clk_branch2_ops, 2821 }, 2822 }, 2823 }; 2824 2825 static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { 2826 .halt_reg = 0x1a080, 2827 .halt_check = BRANCH_HALT, 2828 .hwcg_reg = 0x1a080, 2829 .hwcg_bit = 1, 2830 .clkr = { 2831 .enable_reg = 0x1a080, 2832 .enable_mask = BIT(0), 2833 .hw.init = &(struct clk_init_data){ 2834 .name = "gcc_sys_noc_usb3_prim_axi_clk", 2835 .parent_hws = (const struct clk_hw *[]){ 2836 &gcc_usb30_prim_master_clk_src.clkr.hw, 2837 }, 2838 .num_parents = 1, 2839 .flags = CLK_SET_RATE_PARENT, 2840 .ops = &clk_branch2_ops, 2841 }, 2842 }, 2843 }; 2844 2845 static struct clk_branch gcc_ufs_clkref_clk = { 2846 .halt_reg = 0x8c000, 2847 .halt_check = BRANCH_HALT, 2848 .clkr = { 2849 .enable_reg = 0x8c000, 2850 .enable_mask = BIT(0), 2851 .hw.init = &(struct clk_init_data){ 2852 .name = "gcc_ufs_clkref_clk", 2853 .ops = &clk_branch2_ops, 2854 }, 2855 }, 2856 }; 2857 2858 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2859 .halt_reg = 0x45014, 2860 .halt_check = BRANCH_HALT, 2861 .hwcg_reg = 0x45014, 2862 .hwcg_bit = 1, 2863 .clkr = { 2864 .enable_reg = 0x45014, 2865 .enable_mask = BIT(0), 2866 .hw.init = &(struct clk_init_data){ 2867 .name = "gcc_ufs_phy_ahb_clk", 2868 .ops = &clk_branch2_ops, 2869 }, 2870 }, 2871 }; 2872 2873 static struct clk_branch gcc_ufs_phy_axi_clk = { 2874 .halt_reg = 0x45010, 2875 .halt_check = BRANCH_HALT, 2876 .hwcg_reg = 0x45010, 2877 .hwcg_bit = 1, 2878 .clkr = { 2879 .enable_reg = 0x45010, 2880 .enable_mask = BIT(0), 2881 .hw.init = &(struct clk_init_data){ 2882 .name = "gcc_ufs_phy_axi_clk", 2883 .parent_hws = (const struct clk_hw *[]){ 2884 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2885 }, 2886 .num_parents = 1, 2887 .flags = CLK_SET_RATE_PARENT, 2888 .ops = &clk_branch2_ops, 2889 }, 2890 }, 2891 }; 2892 2893 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2894 .halt_reg = 0x45044, 2895 .halt_check = BRANCH_HALT, 2896 .hwcg_reg = 0x45044, 2897 .hwcg_bit = 1, 2898 .clkr = { 2899 .enable_reg = 0x45044, 2900 .enable_mask = BIT(0), 2901 .hw.init = &(struct clk_init_data){ 2902 .name = "gcc_ufs_phy_ice_core_clk", 2903 .parent_hws = (const struct clk_hw *[]){ 2904 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2905 }, 2906 .num_parents = 1, 2907 .flags = CLK_SET_RATE_PARENT, 2908 .ops = &clk_branch2_ops, 2909 }, 2910 }, 2911 }; 2912 2913 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2914 .halt_reg = 0x45078, 2915 .halt_check = BRANCH_HALT, 2916 .hwcg_reg = 0x45078, 2917 .hwcg_bit = 1, 2918 .clkr = { 2919 .enable_reg = 0x45078, 2920 .enable_mask = BIT(0), 2921 .hw.init = &(struct clk_init_data){ 2922 .name = "gcc_ufs_phy_phy_aux_clk", 2923 .parent_hws = (const struct clk_hw *[]){ 2924 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2925 }, 2926 .num_parents = 1, 2927 .flags = CLK_SET_RATE_PARENT, 2928 .ops = &clk_branch2_ops, 2929 }, 2930 }, 2931 }; 2932 2933 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2934 .halt_reg = 0x4501c, 2935 .halt_check = BRANCH_HALT_SKIP, 2936 .clkr = { 2937 .enable_reg = 0x4501c, 2938 .enable_mask = BIT(0), 2939 .hw.init = &(struct clk_init_data){ 2940 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2941 .ops = &clk_branch2_ops, 2942 }, 2943 }, 2944 }; 2945 2946 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2947 .halt_reg = 0x45018, 2948 .halt_check = BRANCH_HALT_SKIP, 2949 .clkr = { 2950 .enable_reg = 0x45018, 2951 .enable_mask = BIT(0), 2952 .hw.init = &(struct clk_init_data){ 2953 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2954 .ops = &clk_branch2_ops, 2955 }, 2956 }, 2957 }; 2958 2959 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2960 .halt_reg = 0x45040, 2961 .halt_check = BRANCH_HALT, 2962 .hwcg_reg = 0x45040, 2963 .hwcg_bit = 1, 2964 .clkr = { 2965 .enable_reg = 0x45040, 2966 .enable_mask = BIT(0), 2967 .hw.init = &(struct clk_init_data){ 2968 .name = "gcc_ufs_phy_unipro_core_clk", 2969 .parent_hws = (const struct clk_hw *[]){ 2970 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2971 }, 2972 .num_parents = 1, 2973 .flags = CLK_SET_RATE_PARENT, 2974 .ops = &clk_branch2_ops, 2975 }, 2976 }, 2977 }; 2978 2979 static struct clk_branch gcc_usb30_prim_master_clk = { 2980 .halt_reg = 0x1a010, 2981 .halt_check = BRANCH_HALT, 2982 .clkr = { 2983 .enable_reg = 0x1a010, 2984 .enable_mask = BIT(0), 2985 .hw.init = &(struct clk_init_data){ 2986 .name = "gcc_usb30_prim_master_clk", 2987 .parent_hws = (const struct clk_hw *[]){ 2988 &gcc_usb30_prim_master_clk_src.clkr.hw, 2989 }, 2990 .num_parents = 1, 2991 .flags = CLK_SET_RATE_PARENT, 2992 .ops = &clk_branch2_ops, 2993 }, 2994 }, 2995 }; 2996 2997 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2998 .halt_reg = 0x1a018, 2999 .halt_check = BRANCH_HALT, 3000 .clkr = { 3001 .enable_reg = 0x1a018, 3002 .enable_mask = BIT(0), 3003 .hw.init = &(struct clk_init_data){ 3004 .name = "gcc_usb30_prim_mock_utmi_clk", 3005 .parent_hws = (const struct clk_hw *[]){ 3006 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 3007 }, 3008 .num_parents = 1, 3009 .flags = CLK_SET_RATE_PARENT, 3010 .ops = &clk_branch2_ops, 3011 }, 3012 }, 3013 }; 3014 3015 static struct clk_branch gcc_usb30_prim_sleep_clk = { 3016 .halt_reg = 0x1a014, 3017 .halt_check = BRANCH_HALT, 3018 .clkr = { 3019 .enable_reg = 0x1a014, 3020 .enable_mask = BIT(0), 3021 .hw.init = &(struct clk_init_data){ 3022 .name = "gcc_usb30_prim_sleep_clk", 3023 .ops = &clk_branch2_ops, 3024 }, 3025 }, 3026 }; 3027 3028 static struct clk_branch gcc_usb3_prim_clkref_clk = { 3029 .halt_reg = 0x9f000, 3030 .halt_check = BRANCH_HALT, 3031 .clkr = { 3032 .enable_reg = 0x9f000, 3033 .enable_mask = BIT(0), 3034 .hw.init = &(struct clk_init_data){ 3035 .name = "gcc_usb3_prim_clkref_clk", 3036 .ops = &clk_branch2_ops, 3037 }, 3038 }, 3039 }; 3040 3041 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3042 .halt_reg = 0x1a054, 3043 .halt_check = BRANCH_HALT, 3044 .clkr = { 3045 .enable_reg = 0x1a054, 3046 .enable_mask = BIT(0), 3047 .hw.init = &(struct clk_init_data){ 3048 .name = "gcc_usb3_prim_phy_com_aux_clk", 3049 .parent_hws = (const struct clk_hw *[]){ 3050 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3051 }, 3052 .num_parents = 1, 3053 .flags = CLK_SET_RATE_PARENT, 3054 .ops = &clk_branch2_ops, 3055 }, 3056 }, 3057 }; 3058 3059 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3060 .halt_reg = 0x1a058, 3061 .halt_check = BRANCH_HALT_SKIP, 3062 .hwcg_reg = 0x1a058, 3063 .hwcg_bit = 1, 3064 .clkr = { 3065 .enable_reg = 0x1a058, 3066 .enable_mask = BIT(0), 3067 .hw.init = &(struct clk_init_data){ 3068 .name = "gcc_usb3_prim_phy_pipe_clk", 3069 .ops = &clk_branch2_ops, 3070 }, 3071 }, 3072 }; 3073 3074 static struct clk_branch gcc_vcodec0_axi_clk = { 3075 .halt_reg = 0x6e008, 3076 .halt_check = BRANCH_HALT, 3077 .clkr = { 3078 .enable_reg = 0x6e008, 3079 .enable_mask = BIT(0), 3080 .hw.init = &(struct clk_init_data){ 3081 .name = "gcc_vcodec0_axi_clk", 3082 .ops = &clk_branch2_ops, 3083 }, 3084 }, 3085 }; 3086 3087 static struct clk_branch gcc_venus_ahb_clk = { 3088 .halt_reg = 0x6e010, 3089 .halt_check = BRANCH_HALT, 3090 .clkr = { 3091 .enable_reg = 0x6e010, 3092 .enable_mask = BIT(0), 3093 .hw.init = &(struct clk_init_data){ 3094 .name = "gcc_venus_ahb_clk", 3095 .ops = &clk_branch2_ops, 3096 }, 3097 }, 3098 }; 3099 3100 static struct clk_branch gcc_venus_ctl_axi_clk = { 3101 .halt_reg = 0x6e004, 3102 .halt_check = BRANCH_HALT, 3103 .clkr = { 3104 .enable_reg = 0x6e004, 3105 .enable_mask = BIT(0), 3106 .hw.init = &(struct clk_init_data){ 3107 .name = "gcc_venus_ctl_axi_clk", 3108 .ops = &clk_branch2_ops, 3109 }, 3110 }, 3111 }; 3112 3113 static struct clk_branch gcc_video_ahb_clk = { 3114 .halt_reg = 0x17004, 3115 .halt_check = BRANCH_HALT, 3116 .hwcg_reg = 0x17004, 3117 .hwcg_bit = 1, 3118 .clkr = { 3119 .enable_reg = 0x17004, 3120 .enable_mask = BIT(0), 3121 .hw.init = &(struct clk_init_data){ 3122 .name = "gcc_video_ahb_clk", 3123 .ops = &clk_branch2_ops, 3124 }, 3125 }, 3126 }; 3127 3128 static struct clk_branch gcc_video_axi0_clk = { 3129 .halt_reg = 0x1701c, 3130 .halt_check = BRANCH_HALT, 3131 .hwcg_reg = 0x1701c, 3132 .hwcg_bit = 1, 3133 .clkr = { 3134 .enable_reg = 0x1701c, 3135 .enable_mask = BIT(0), 3136 .hw.init = &(struct clk_init_data){ 3137 .name = "gcc_video_axi0_clk", 3138 .ops = &clk_branch2_ops, 3139 }, 3140 }, 3141 }; 3142 3143 static struct clk_branch gcc_video_throttle_core_clk = { 3144 .halt_reg = 0x17068, 3145 .halt_check = BRANCH_HALT_VOTED, 3146 .hwcg_reg = 0x17068, 3147 .hwcg_bit = 1, 3148 .clkr = { 3149 .enable_reg = 0x79004, 3150 .enable_mask = BIT(28), 3151 .hw.init = &(struct clk_init_data){ 3152 .name = "gcc_video_throttle_core_clk", 3153 .ops = &clk_branch2_ops, 3154 }, 3155 }, 3156 }; 3157 3158 static struct clk_branch gcc_video_vcodec0_sys_clk = { 3159 .halt_reg = 0x580a4, 3160 .halt_check = BRANCH_HALT_DELAY, 3161 .hwcg_reg = 0x580a4, 3162 .hwcg_bit = 1, 3163 .clkr = { 3164 .enable_reg = 0x580a4, 3165 .enable_mask = BIT(0), 3166 .hw.init = &(struct clk_init_data){ 3167 .name = "gcc_video_vcodec0_sys_clk", 3168 .parent_hws = (const struct clk_hw *[]){ 3169 &gcc_video_venus_clk_src.clkr.hw, 3170 }, 3171 .num_parents = 1, 3172 .flags = CLK_SET_RATE_PARENT, 3173 .ops = &clk_branch2_ops, 3174 }, 3175 }, 3176 }; 3177 3178 static struct clk_branch gcc_video_venus_ctl_clk = { 3179 .halt_reg = 0x5808c, 3180 .halt_check = BRANCH_HALT, 3181 .clkr = { 3182 .enable_reg = 0x5808c, 3183 .enable_mask = BIT(0), 3184 .hw.init = &(struct clk_init_data){ 3185 .name = "gcc_video_venus_ctl_clk", 3186 .parent_hws = (const struct clk_hw *[]){ 3187 &gcc_video_venus_clk_src.clkr.hw, 3188 }, 3189 .num_parents = 1, 3190 .flags = CLK_SET_RATE_PARENT, 3191 .ops = &clk_branch2_ops, 3192 }, 3193 }, 3194 }; 3195 3196 static struct clk_branch gcc_video_xo_clk = { 3197 .halt_reg = 0x17024, 3198 .halt_check = BRANCH_HALT, 3199 .clkr = { 3200 .enable_reg = 0x17024, 3201 .enable_mask = BIT(0), 3202 .hw.init = &(struct clk_init_data){ 3203 .name = "gcc_video_xo_clk", 3204 .ops = &clk_branch2_ops, 3205 }, 3206 }, 3207 }; 3208 3209 static struct gdsc gcc_camss_top_gdsc = { 3210 .gdscr = 0x58004, 3211 .pd = { 3212 .name = "gcc_camss_top", 3213 }, 3214 .pwrsts = PWRSTS_OFF_ON, 3215 }; 3216 3217 static struct gdsc gcc_ufs_phy_gdsc = { 3218 .gdscr = 0x45004, 3219 .pd = { 3220 .name = "gcc_ufs_phy", 3221 }, 3222 .pwrsts = PWRSTS_OFF_ON, 3223 }; 3224 3225 static struct gdsc gcc_usb30_prim_gdsc = { 3226 .gdscr = 0x1a004, 3227 .pd = { 3228 .name = "gcc_usb30_prim", 3229 }, 3230 .pwrsts = PWRSTS_OFF_ON, 3231 }; 3232 3233 static struct gdsc gcc_vcodec0_gdsc = { 3234 .gdscr = 0x58098, 3235 .pd = { 3236 .name = "gcc_vcodec0", 3237 }, 3238 .pwrsts = PWRSTS_OFF_ON, 3239 }; 3240 3241 static struct gdsc gcc_venus_gdsc = { 3242 .gdscr = 0x5807c, 3243 .pd = { 3244 .name = "gcc_venus", 3245 }, 3246 .pwrsts = PWRSTS_OFF_ON, 3247 }; 3248 3249 static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = { 3250 .gdscr = 0x7d060, 3251 .pd = { 3252 .name = "hlos1_vote_turing_mmu_tbu1", 3253 }, 3254 .pwrsts = PWRSTS_OFF_ON, 3255 .flags = VOTABLE, 3256 }; 3257 3258 static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { 3259 .gdscr = 0x7d07c, 3260 .pd = { 3261 .name = "hlos1_vote_turing_mmu_tbu0", 3262 }, 3263 .pwrsts = PWRSTS_OFF_ON, 3264 .flags = VOTABLE, 3265 }; 3266 3267 static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = { 3268 .gdscr = 0x7d074, 3269 .pd = { 3270 .name = "hlos1_vote_mm_snoc_mmu_tbu_rt", 3271 }, 3272 .pwrsts = PWRSTS_OFF_ON, 3273 .flags = VOTABLE, 3274 }; 3275 3276 static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = { 3277 .gdscr = 0x7d078, 3278 .pd = { 3279 .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt", 3280 }, 3281 .pwrsts = PWRSTS_OFF_ON, 3282 .flags = VOTABLE, 3283 }; 3284 3285 static struct clk_regmap *gcc_sm6115_clocks[] = { 3286 [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr, 3287 [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr, 3288 [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr, 3289 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3290 [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, 3291 [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, 3292 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 3293 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 3294 [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, 3295 [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, 3296 [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr, 3297 [GCC_CAMSS_CAMNOC_NTS_XO_CLK] = &gcc_camss_camnoc_nts_xo_clk.clkr, 3298 [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr, 3299 [GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr, 3300 [GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr, 3301 [GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr, 3302 [GCC_CAMSS_CPHY_2_CLK] = &gcc_camss_cphy_2_clk.clkr, 3303 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 3304 [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr, 3305 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, 3306 [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr, 3307 [GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr, 3308 [GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr, 3309 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 3310 [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr, 3311 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 3312 [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr, 3313 [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, 3314 [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr, 3315 [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr, 3316 [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr, 3317 [GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr, 3318 [GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr, 3319 [GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr, 3320 [GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr, 3321 [GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr, 3322 [GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr, 3323 [GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr, 3324 [GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr, 3325 [GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr, 3326 [GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr, 3327 [GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr, 3328 [GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr, 3329 [GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr, 3330 [GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr, 3331 [GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr, 3332 [GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr, 3333 [GCC_CAMSS_TFE_2_CLK] = &gcc_camss_tfe_2_clk.clkr, 3334 [GCC_CAMSS_TFE_2_CLK_SRC] = &gcc_camss_tfe_2_clk_src.clkr, 3335 [GCC_CAMSS_TFE_2_CPHY_RX_CLK] = &gcc_camss_tfe_2_cphy_rx_clk.clkr, 3336 [GCC_CAMSS_TFE_2_CSID_CLK] = &gcc_camss_tfe_2_csid_clk.clkr, 3337 [GCC_CAMSS_TFE_2_CSID_CLK_SRC] = &gcc_camss_tfe_2_csid_clk_src.clkr, 3338 [GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr, 3339 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 3340 [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, 3341 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3342 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, 3343 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, 3344 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 3345 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 3346 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3347 [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, 3348 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 3349 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3350 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3351 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3352 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3353 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3354 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3355 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 3356 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3357 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3358 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, 3359 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3360 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3361 [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, 3362 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3363 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3364 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3365 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3366 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3367 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3368 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3369 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3370 [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr, 3371 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3372 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 3373 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 3374 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3375 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3376 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3377 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3378 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3379 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3380 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3381 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3382 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3383 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3384 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3385 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3386 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3387 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3388 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3389 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3390 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 3391 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 3392 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 3393 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3394 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3395 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3396 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 3397 [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, 3398 [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, 3399 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, 3400 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3401 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3402 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3403 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3404 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3405 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3406 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3407 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3408 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3409 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3410 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 3411 &gcc_ufs_phy_unipro_core_clk_src.clkr, 3412 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3413 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3414 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3415 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 3416 &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3417 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = 3418 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3419 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3420 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 3421 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3422 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3423 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3424 [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr, 3425 [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr, 3426 [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr, 3427 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 3428 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3429 [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, 3430 [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr, 3431 [GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr, 3432 [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr, 3433 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 3434 [GPLL0] = &gpll0.clkr, 3435 [GPLL0_OUT_AUX2] = &gpll0_out_aux2.clkr, 3436 [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr, 3437 [GPLL10] = &gpll10.clkr, 3438 [GPLL10_OUT_MAIN] = &gpll10_out_main.clkr, 3439 [GPLL11] = &gpll11.clkr, 3440 [GPLL11_OUT_MAIN] = &gpll11_out_main.clkr, 3441 [GPLL3] = &gpll3.clkr, 3442 [GPLL4] = &gpll4.clkr, 3443 [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr, 3444 [GPLL6] = &gpll6.clkr, 3445 [GPLL6_OUT_MAIN] = &gpll6_out_main.clkr, 3446 [GPLL7] = &gpll7.clkr, 3447 [GPLL7_OUT_MAIN] = &gpll7_out_main.clkr, 3448 [GPLL8] = &gpll8.clkr, 3449 [GPLL8_OUT_MAIN] = &gpll8_out_main.clkr, 3450 [GPLL9] = &gpll9.clkr, 3451 [GPLL9_OUT_MAIN] = &gpll9_out_main.clkr, 3452 }; 3453 3454 static const struct qcom_reset_map gcc_sm6115_resets[] = { 3455 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, 3456 [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, 3457 [GCC_SDCC1_BCR] = { 0x38000 }, 3458 [GCC_SDCC2_BCR] = { 0x1e000 }, 3459 [GCC_UFS_PHY_BCR] = { 0x45000 }, 3460 [GCC_USB30_PRIM_BCR] = { 0x1a000 }, 3461 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, 3462 [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, 3463 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, 3464 [GCC_VCODEC0_BCR] = { 0x58094 }, 3465 [GCC_VENUS_BCR] = { 0x58078 }, 3466 [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 }, 3467 }; 3468 3469 static struct gdsc *gcc_sm6115_gdscs[] = { 3470 [GCC_CAMSS_TOP_GDSC] = &gcc_camss_top_gdsc, 3471 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, 3472 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 3473 [GCC_VCODEC0_GDSC] = &gcc_vcodec0_gdsc, 3474 [GCC_VENUS_GDSC] = &gcc_venus_gdsc, 3475 [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, 3476 [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc, 3477 [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc, 3478 [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc, 3479 }; 3480 3481 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3482 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3483 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3484 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3485 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3486 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3487 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3488 }; 3489 3490 static const struct regmap_config gcc_sm6115_regmap_config = { 3491 .reg_bits = 32, 3492 .reg_stride = 4, 3493 .val_bits = 32, 3494 .max_register = 0xc7000, 3495 .fast_io = true, 3496 }; 3497 3498 static const struct qcom_cc_desc gcc_sm6115_desc = { 3499 .config = &gcc_sm6115_regmap_config, 3500 .clks = gcc_sm6115_clocks, 3501 .num_clks = ARRAY_SIZE(gcc_sm6115_clocks), 3502 .resets = gcc_sm6115_resets, 3503 .num_resets = ARRAY_SIZE(gcc_sm6115_resets), 3504 .gdscs = gcc_sm6115_gdscs, 3505 .num_gdscs = ARRAY_SIZE(gcc_sm6115_gdscs), 3506 }; 3507 3508 static const struct of_device_id gcc_sm6115_match_table[] = { 3509 { .compatible = "qcom,gcc-sm6115" }, 3510 { } 3511 }; 3512 MODULE_DEVICE_TABLE(of, gcc_sm6115_match_table); 3513 3514 static int gcc_sm6115_probe(struct platform_device *pdev) 3515 { 3516 struct regmap *regmap; 3517 int ret; 3518 3519 regmap = qcom_cc_map(pdev, &gcc_sm6115_desc); 3520 if (IS_ERR(regmap)) 3521 return PTR_ERR(regmap); 3522 3523 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3524 ARRAY_SIZE(gcc_dfs_clocks)); 3525 if (ret) 3526 return ret; 3527 3528 clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config); 3529 clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config); 3530 clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config); 3531 clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config); 3532 3533 return qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap); 3534 } 3535 3536 static struct platform_driver gcc_sm6115_driver = { 3537 .probe = gcc_sm6115_probe, 3538 .driver = { 3539 .name = "gcc-sm6115", 3540 .of_match_table = gcc_sm6115_match_table, 3541 }, 3542 }; 3543 3544 static int __init gcc_sm6115_init(void) 3545 { 3546 return platform_driver_register(&gcc_sm6115_driver); 3547 } 3548 subsys_initcall(gcc_sm6115_init); 3549 3550 static void __exit gcc_sm6115_exit(void) 3551 { 3552 platform_driver_unregister(&gcc_sm6115_driver); 3553 } 3554 module_exit(gcc_sm6115_exit); 3555 3556 MODULE_DESCRIPTION("QTI GCC SM6115 and SM4250 Driver"); 3557 MODULE_LICENSE("GPL v2"); 3558 MODULE_ALIAS("platform:gcc-sm6115"); 3559