1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/err.h> 7 #include <linux/kernel.h> 8 #include <linux/module.h> 9 #include <linux/of_device.h> 10 #include <linux/clk-provider.h> 11 #include <linux/regmap.h> 12 #include <linux/reset-controller.h> 13 14 #include <dt-bindings/clock/qcom,gcc-sm6115.h> 15 16 #include "clk-alpha-pll.h" 17 #include "clk-branch.h" 18 #include "clk-pll.h" 19 #include "clk-rcg.h" 20 #include "clk-regmap.h" 21 #include "clk-regmap-divider.h" 22 #include "common.h" 23 #include "gdsc.h" 24 #include "reset.h" 25 26 enum { 27 P_BI_TCXO, 28 P_GPLL0_OUT_AUX2, 29 P_GPLL0_OUT_EARLY, 30 P_GPLL10_OUT_MAIN, 31 P_GPLL11_OUT_MAIN, 32 P_GPLL3_OUT_EARLY, 33 P_GPLL4_OUT_MAIN, 34 P_GPLL6_OUT_EARLY, 35 P_GPLL6_OUT_MAIN, 36 P_GPLL7_OUT_MAIN, 37 P_GPLL8_OUT_EARLY, 38 P_GPLL8_OUT_MAIN, 39 P_GPLL9_OUT_EARLY, 40 P_GPLL9_OUT_MAIN, 41 P_SLEEP_CLK, 42 }; 43 44 static struct pll_vco default_vco[] = { 45 { 500000000, 1000000000, 2 }, 46 }; 47 48 static struct pll_vco gpll9_vco[] = { 49 { 500000000, 1250000000, 0 }, 50 }; 51 52 static struct pll_vco gpll10_vco[] = { 53 { 750000000, 1500000000, 1 }, 54 }; 55 56 static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = { 57 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 58 [PLL_OFF_L_VAL] = 0x04, 59 [PLL_OFF_ALPHA_VAL] = 0x08, 60 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 61 [PLL_OFF_TEST_CTL] = 0x10, 62 [PLL_OFF_TEST_CTL_U] = 0x14, 63 [PLL_OFF_USER_CTL] = 0x18, 64 [PLL_OFF_USER_CTL_U] = 0x1c, 65 [PLL_OFF_CONFIG_CTL] = 0x20, 66 [PLL_OFF_STATUS] = 0x24, 67 }, 68 [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 69 [PLL_OFF_L_VAL] = 0x04, 70 [PLL_OFF_ALPHA_VAL] = 0x08, 71 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 72 [PLL_OFF_TEST_CTL] = 0x10, 73 [PLL_OFF_TEST_CTL_U] = 0x14, 74 [PLL_OFF_USER_CTL] = 0x18, 75 [PLL_OFF_CONFIG_CTL] = 0x1C, 76 [PLL_OFF_STATUS] = 0x20, 77 }, 78 }; 79 80 static struct clk_alpha_pll gpll0 = { 81 .offset = 0x0, 82 .vco_table = default_vco, 83 .num_vco = ARRAY_SIZE(default_vco), 84 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 85 .clkr = { 86 .enable_reg = 0x79000, 87 .enable_mask = BIT(0), 88 .hw.init = &(struct clk_init_data){ 89 .name = "gpll0", 90 .parent_data = &(const struct clk_parent_data){ 91 .fw_name = "bi_tcxo", 92 }, 93 .num_parents = 1, 94 .ops = &clk_alpha_pll_ops, 95 }, 96 }, 97 }; 98 99 static const struct clk_div_table post_div_table_gpll0_out_aux2[] = { 100 { 0x1, 2 }, 101 { } 102 }; 103 104 static struct clk_alpha_pll_postdiv gpll0_out_aux2 = { 105 .offset = 0x0, 106 .post_div_shift = 8, 107 .post_div_table = post_div_table_gpll0_out_aux2, 108 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2), 109 .width = 4, 110 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 111 .clkr.hw.init = &(struct clk_init_data){ 112 .name = "gpll0_out_aux2", 113 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 114 .num_parents = 1, 115 .ops = &clk_alpha_pll_postdiv_ro_ops, 116 }, 117 }; 118 119 static const struct clk_div_table post_div_table_gpll0_out_main[] = { 120 { 0x0, 1 }, 121 { } 122 }; 123 124 static struct clk_alpha_pll_postdiv gpll0_out_main = { 125 .offset = 0x0, 126 .post_div_shift = 8, 127 .post_div_table = post_div_table_gpll0_out_main, 128 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_main), 129 .width = 4, 130 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 131 .clkr.hw.init = &(struct clk_init_data){ 132 .name = "gpll0_out_main", 133 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 134 .num_parents = 1, 135 .ops = &clk_alpha_pll_postdiv_ro_ops, 136 }, 137 }; 138 139 /* 1152MHz configuration */ 140 static const struct alpha_pll_config gpll10_config = { 141 .l = 0x3c, 142 .vco_val = 0x1 << 20, 143 .vco_mask = GENMASK(21, 20), 144 .main_output_mask = BIT(0), 145 .config_ctl_val = 0x4001055b, 146 }; 147 148 static struct clk_alpha_pll gpll10 = { 149 .offset = 0xa000, 150 .vco_table = gpll10_vco, 151 .num_vco = ARRAY_SIZE(gpll10_vco), 152 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 153 .clkr = { 154 .enable_reg = 0x79000, 155 .enable_mask = BIT(10), 156 .hw.init = &(struct clk_init_data){ 157 .name = "gpll10", 158 .parent_data = &(const struct clk_parent_data){ 159 .fw_name = "bi_tcxo", 160 }, 161 .num_parents = 1, 162 .ops = &clk_alpha_pll_ops, 163 }, 164 }, 165 }; 166 167 static const struct clk_div_table post_div_table_gpll10_out_main[] = { 168 { 0x0, 1 }, 169 { } 170 }; 171 172 static struct clk_alpha_pll_postdiv gpll10_out_main = { 173 .offset = 0xa000, 174 .post_div_shift = 8, 175 .post_div_table = post_div_table_gpll10_out_main, 176 .num_post_div = ARRAY_SIZE(post_div_table_gpll10_out_main), 177 .width = 4, 178 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 179 .clkr.hw.init = &(struct clk_init_data){ 180 .name = "gpll10_out_main", 181 .parent_hws = (const struct clk_hw *[]){ &gpll10.clkr.hw }, 182 .num_parents = 1, 183 .flags = CLK_SET_RATE_PARENT, 184 .ops = &clk_alpha_pll_postdiv_ops, 185 }, 186 }; 187 188 /* 600MHz configuration */ 189 static const struct alpha_pll_config gpll11_config = { 190 .l = 0x1F, 191 .alpha = 0x0, 192 .alpha_hi = 0x40, 193 .alpha_en_mask = BIT(24), 194 .vco_val = 0x2 << 20, 195 .vco_mask = GENMASK(21, 20), 196 .config_ctl_val = 0x4001055b, 197 }; 198 199 static struct clk_alpha_pll gpll11 = { 200 .offset = 0xb000, 201 .vco_table = default_vco, 202 .num_vco = ARRAY_SIZE(default_vco), 203 .flags = SUPPORTS_DYNAMIC_UPDATE, 204 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 205 .clkr = { 206 .enable_reg = 0x79000, 207 .enable_mask = BIT(11), 208 .hw.init = &(struct clk_init_data){ 209 .name = "gpll11", 210 .parent_data = &(const struct clk_parent_data){ 211 .fw_name = "bi_tcxo", 212 }, 213 .num_parents = 1, 214 .ops = &clk_alpha_pll_ops, 215 }, 216 }, 217 }; 218 219 static const struct clk_div_table post_div_table_gpll11_out_main[] = { 220 { 0x0, 1 }, 221 { } 222 }; 223 224 static struct clk_alpha_pll_postdiv gpll11_out_main = { 225 .offset = 0xb000, 226 .post_div_shift = 8, 227 .post_div_table = post_div_table_gpll11_out_main, 228 .num_post_div = ARRAY_SIZE(post_div_table_gpll11_out_main), 229 .width = 4, 230 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 231 .clkr.hw.init = &(struct clk_init_data){ 232 .name = "gpll11_out_main", 233 .parent_hws = (const struct clk_hw *[]){ &gpll11.clkr.hw }, 234 .num_parents = 1, 235 .flags = CLK_SET_RATE_PARENT, 236 .ops = &clk_alpha_pll_postdiv_ops, 237 }, 238 }; 239 240 static struct clk_alpha_pll gpll3 = { 241 .offset = 0x3000, 242 .vco_table = default_vco, 243 .num_vco = ARRAY_SIZE(default_vco), 244 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 245 .clkr = { 246 .enable_reg = 0x79000, 247 .enable_mask = BIT(3), 248 .hw.init = &(struct clk_init_data){ 249 .name = "gpll3", 250 .parent_data = &(const struct clk_parent_data){ 251 .fw_name = "bi_tcxo", 252 }, 253 .num_parents = 1, 254 .ops = &clk_alpha_pll_ops, 255 }, 256 }, 257 }; 258 259 static struct clk_alpha_pll gpll4 = { 260 .offset = 0x4000, 261 .vco_table = default_vco, 262 .num_vco = ARRAY_SIZE(default_vco), 263 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 264 .clkr = { 265 .enable_reg = 0x79000, 266 .enable_mask = BIT(4), 267 .hw.init = &(struct clk_init_data){ 268 .name = "gpll4", 269 .parent_data = &(const struct clk_parent_data){ 270 .fw_name = "bi_tcxo", 271 }, 272 .num_parents = 1, 273 .ops = &clk_alpha_pll_ops, 274 }, 275 }, 276 }; 277 278 static const struct clk_div_table post_div_table_gpll4_out_main[] = { 279 { 0x0, 1 }, 280 { } 281 }; 282 283 static struct clk_alpha_pll_postdiv gpll4_out_main = { 284 .offset = 0x4000, 285 .post_div_shift = 8, 286 .post_div_table = post_div_table_gpll4_out_main, 287 .num_post_div = ARRAY_SIZE(post_div_table_gpll4_out_main), 288 .width = 4, 289 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 290 .clkr.hw.init = &(struct clk_init_data){ 291 .name = "gpll4_out_main", 292 .parent_hws = (const struct clk_hw *[]){ &gpll4.clkr.hw }, 293 .num_parents = 1, 294 .ops = &clk_alpha_pll_postdiv_ro_ops, 295 }, 296 }; 297 298 static struct clk_alpha_pll gpll6 = { 299 .offset = 0x6000, 300 .vco_table = default_vco, 301 .num_vco = ARRAY_SIZE(default_vco), 302 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 303 .clkr = { 304 .enable_reg = 0x79000, 305 .enable_mask = BIT(6), 306 .hw.init = &(struct clk_init_data){ 307 .name = "gpll6", 308 .parent_data = &(const struct clk_parent_data){ 309 .fw_name = "bi_tcxo", 310 }, 311 .num_parents = 1, 312 .ops = &clk_alpha_pll_ops, 313 }, 314 }, 315 }; 316 317 static const struct clk_div_table post_div_table_gpll6_out_main[] = { 318 { 0x1, 2 }, 319 { } 320 }; 321 322 static struct clk_alpha_pll_postdiv gpll6_out_main = { 323 .offset = 0x6000, 324 .post_div_shift = 8, 325 .post_div_table = post_div_table_gpll6_out_main, 326 .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main), 327 .width = 4, 328 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 329 .clkr.hw.init = &(struct clk_init_data){ 330 .name = "gpll6_out_main", 331 .parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw }, 332 .num_parents = 1, 333 .ops = &clk_alpha_pll_postdiv_ro_ops, 334 }, 335 }; 336 337 static struct clk_alpha_pll gpll7 = { 338 .offset = 0x7000, 339 .vco_table = default_vco, 340 .num_vco = ARRAY_SIZE(default_vco), 341 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 342 .clkr = { 343 .enable_reg = 0x79000, 344 .enable_mask = BIT(7), 345 .hw.init = &(struct clk_init_data){ 346 .name = "gpll7", 347 .parent_data = &(const struct clk_parent_data){ 348 .fw_name = "bi_tcxo", 349 }, 350 .num_parents = 1, 351 .ops = &clk_alpha_pll_ops, 352 }, 353 }, 354 }; 355 356 static const struct clk_div_table post_div_table_gpll7_out_main[] = { 357 { 0x0, 1 }, 358 { } 359 }; 360 361 static struct clk_alpha_pll_postdiv gpll7_out_main = { 362 .offset = 0x7000, 363 .post_div_shift = 8, 364 .post_div_table = post_div_table_gpll7_out_main, 365 .num_post_div = ARRAY_SIZE(post_div_table_gpll7_out_main), 366 .width = 4, 367 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 368 .clkr.hw.init = &(struct clk_init_data){ 369 .name = "gpll7_out_main", 370 .parent_hws = (const struct clk_hw *[]){ &gpll7.clkr.hw }, 371 .num_parents = 1, 372 .ops = &clk_alpha_pll_postdiv_ro_ops, 373 }, 374 }; 375 376 /* 800MHz configuration */ 377 static const struct alpha_pll_config gpll8_config = { 378 .l = 0x29, 379 .alpha = 0xAAAAAAAA, 380 .alpha_hi = 0xAA, 381 .alpha_en_mask = BIT(24), 382 .vco_val = 0x2 << 20, 383 .vco_mask = GENMASK(21, 20), 384 .main_output_mask = BIT(0), 385 .early_output_mask = BIT(3), 386 .post_div_val = 0x1 << 8, 387 .post_div_mask = GENMASK(11, 8), 388 .config_ctl_val = 0x4001055b, 389 }; 390 391 static struct clk_alpha_pll gpll8 = { 392 .offset = 0x8000, 393 .vco_table = default_vco, 394 .num_vco = ARRAY_SIZE(default_vco), 395 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 396 .flags = SUPPORTS_DYNAMIC_UPDATE, 397 .clkr = { 398 .enable_reg = 0x79000, 399 .enable_mask = BIT(8), 400 .hw.init = &(struct clk_init_data){ 401 .name = "gpll8", 402 .parent_data = &(const struct clk_parent_data){ 403 .fw_name = "bi_tcxo", 404 }, 405 .num_parents = 1, 406 .ops = &clk_alpha_pll_ops, 407 }, 408 }, 409 }; 410 411 static const struct clk_div_table post_div_table_gpll8_out_main[] = { 412 { 0x1, 2 }, 413 { } 414 }; 415 416 static struct clk_alpha_pll_postdiv gpll8_out_main = { 417 .offset = 0x8000, 418 .post_div_shift = 8, 419 .post_div_table = post_div_table_gpll8_out_main, 420 .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main), 421 .width = 4, 422 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 423 .clkr.hw.init = &(struct clk_init_data){ 424 .name = "gpll8_out_main", 425 .parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw }, 426 .num_parents = 1, 427 .flags = CLK_SET_RATE_PARENT, 428 .ops = &clk_alpha_pll_postdiv_ro_ops, 429 }, 430 }; 431 432 /* 1152MHz configuration */ 433 static const struct alpha_pll_config gpll9_config = { 434 .l = 0x3C, 435 .alpha = 0x0, 436 .post_div_val = 0x1 << 8, 437 .post_div_mask = GENMASK(9, 8), 438 .main_output_mask = BIT(0), 439 .config_ctl_val = 0x00004289, 440 }; 441 442 static struct clk_alpha_pll gpll9 = { 443 .offset = 0x9000, 444 .vco_table = gpll9_vco, 445 .num_vco = ARRAY_SIZE(gpll9_vco), 446 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO], 447 .clkr = { 448 .enable_reg = 0x79000, 449 .enable_mask = BIT(9), 450 .hw.init = &(struct clk_init_data){ 451 .name = "gpll9", 452 .parent_data = &(const struct clk_parent_data){ 453 .fw_name = "bi_tcxo", 454 }, 455 .num_parents = 1, 456 .ops = &clk_alpha_pll_ops, 457 }, 458 }, 459 }; 460 461 static const struct clk_div_table post_div_table_gpll9_out_main[] = { 462 { 0x1, 2 }, 463 { } 464 }; 465 466 static struct clk_alpha_pll_postdiv gpll9_out_main = { 467 .offset = 0x9000, 468 .post_div_shift = 8, 469 .post_div_table = post_div_table_gpll9_out_main, 470 .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main), 471 .width = 2, 472 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO], 473 .clkr.hw.init = &(struct clk_init_data){ 474 .name = "gpll9_out_main", 475 .parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw }, 476 .num_parents = 1, 477 .flags = CLK_SET_RATE_PARENT, 478 .ops = &clk_alpha_pll_postdiv_ops, 479 }, 480 }; 481 482 static const struct parent_map gcc_parent_map_0[] = { 483 { P_BI_TCXO, 0 }, 484 { P_GPLL0_OUT_EARLY, 1 }, 485 { P_GPLL0_OUT_AUX2, 2 }, 486 }; 487 488 static const struct clk_parent_data gcc_parents_0[] = { 489 { .fw_name = "bi_tcxo" }, 490 { .hw = &gpll0.clkr.hw }, 491 { .hw = &gpll0_out_aux2.clkr.hw }, 492 }; 493 494 static const struct parent_map gcc_parent_map_1[] = { 495 { P_BI_TCXO, 0 }, 496 { P_GPLL0_OUT_EARLY, 1 }, 497 { P_GPLL0_OUT_AUX2, 2 }, 498 { P_GPLL6_OUT_MAIN, 4 }, 499 }; 500 501 static const struct clk_parent_data gcc_parents_1[] = { 502 { .fw_name = "bi_tcxo" }, 503 { .hw = &gpll0.clkr.hw }, 504 { .hw = &gpll0_out_aux2.clkr.hw }, 505 { .hw = &gpll6_out_main.clkr.hw }, 506 }; 507 508 static const struct parent_map gcc_parent_map_2[] = { 509 { P_BI_TCXO, 0 }, 510 { P_GPLL0_OUT_EARLY, 1 }, 511 { P_GPLL0_OUT_AUX2, 2 }, 512 { P_SLEEP_CLK, 5 }, 513 }; 514 515 static const struct clk_parent_data gcc_parents_2[] = { 516 { .fw_name = "bi_tcxo" }, 517 { .hw = &gpll0.clkr.hw }, 518 { .hw = &gpll0_out_aux2.clkr.hw }, 519 { .fw_name = "sleep_clk" }, 520 }; 521 522 static const struct parent_map gcc_parent_map_3[] = { 523 { P_BI_TCXO, 0 }, 524 { P_GPLL0_OUT_EARLY, 1 }, 525 { P_GPLL9_OUT_EARLY, 2 }, 526 { P_GPLL10_OUT_MAIN, 3 }, 527 { P_GPLL9_OUT_MAIN, 5 }, 528 }; 529 530 static const struct clk_parent_data gcc_parents_3[] = { 531 { .fw_name = "bi_tcxo" }, 532 { .hw = &gpll0.clkr.hw }, 533 { .hw = &gpll9.clkr.hw }, 534 { .hw = &gpll10_out_main.clkr.hw }, 535 { .hw = &gpll9_out_main.clkr.hw }, 536 }; 537 538 static const struct parent_map gcc_parent_map_4[] = { 539 { P_BI_TCXO, 0 }, 540 { P_GPLL0_OUT_EARLY, 1 }, 541 { P_GPLL0_OUT_AUX2, 2 }, 542 { P_GPLL4_OUT_MAIN, 5 }, 543 }; 544 545 static const struct clk_parent_data gcc_parents_4[] = { 546 { .fw_name = "bi_tcxo" }, 547 { .hw = &gpll0.clkr.hw }, 548 { .hw = &gpll0_out_aux2.clkr.hw }, 549 { .hw = &gpll4_out_main.clkr.hw }, 550 }; 551 552 static const struct parent_map gcc_parent_map_5[] = { 553 { P_BI_TCXO, 0 }, 554 { P_GPLL0_OUT_EARLY, 1 }, 555 { P_GPLL8_OUT_EARLY, 2 }, 556 { P_GPLL10_OUT_MAIN, 3 }, 557 { P_GPLL8_OUT_MAIN, 4 }, 558 { P_GPLL9_OUT_MAIN, 5 }, 559 }; 560 561 static const struct clk_parent_data gcc_parents_5[] = { 562 { .fw_name = "bi_tcxo" }, 563 { .hw = &gpll0.clkr.hw }, 564 { .hw = &gpll8.clkr.hw }, 565 { .hw = &gpll10_out_main.clkr.hw }, 566 { .hw = &gpll8_out_main.clkr.hw }, 567 { .hw = &gpll9_out_main.clkr.hw }, 568 }; 569 570 static const struct parent_map gcc_parent_map_6[] = { 571 { P_BI_TCXO, 0 }, 572 { P_GPLL0_OUT_EARLY, 1 }, 573 { P_GPLL8_OUT_EARLY, 2 }, 574 { P_GPLL10_OUT_MAIN, 3 }, 575 { P_GPLL6_OUT_MAIN, 4 }, 576 { P_GPLL9_OUT_MAIN, 5 }, 577 { P_GPLL3_OUT_EARLY, 6 }, 578 }; 579 580 static const struct clk_parent_data gcc_parents_6[] = { 581 { .fw_name = "bi_tcxo" }, 582 { .hw = &gpll0.clkr.hw }, 583 { .hw = &gpll8.clkr.hw }, 584 { .hw = &gpll10_out_main.clkr.hw }, 585 { .hw = &gpll6_out_main.clkr.hw }, 586 { .hw = &gpll9_out_main.clkr.hw }, 587 { .hw = &gpll3.clkr.hw }, 588 }; 589 590 static const struct parent_map gcc_parent_map_7[] = { 591 { P_BI_TCXO, 0 }, 592 { P_GPLL0_OUT_EARLY, 1 }, 593 { P_GPLL0_OUT_AUX2, 2 }, 594 { P_GPLL10_OUT_MAIN, 3 }, 595 { P_GPLL4_OUT_MAIN, 5 }, 596 { P_GPLL3_OUT_EARLY, 6 }, 597 }; 598 599 static const struct clk_parent_data gcc_parents_7[] = { 600 { .fw_name = "bi_tcxo" }, 601 { .hw = &gpll0.clkr.hw }, 602 { .hw = &gpll0_out_aux2.clkr.hw }, 603 { .hw = &gpll10_out_main.clkr.hw }, 604 { .hw = &gpll4_out_main.clkr.hw }, 605 { .hw = &gpll3.clkr.hw }, 606 }; 607 608 static const struct parent_map gcc_parent_map_8[] = { 609 { P_BI_TCXO, 0 }, 610 { P_GPLL0_OUT_EARLY, 1 }, 611 { P_GPLL8_OUT_EARLY, 2 }, 612 { P_GPLL10_OUT_MAIN, 3 }, 613 { P_GPLL8_OUT_MAIN, 4 }, 614 { P_GPLL9_OUT_MAIN, 5 }, 615 { P_GPLL3_OUT_EARLY, 6 }, 616 }; 617 618 static const struct clk_parent_data gcc_parents_8[] = { 619 { .fw_name = "bi_tcxo" }, 620 { .hw = &gpll0.clkr.hw }, 621 { .hw = &gpll8.clkr.hw }, 622 { .hw = &gpll10_out_main.clkr.hw }, 623 { .hw = &gpll8_out_main.clkr.hw }, 624 { .hw = &gpll9_out_main.clkr.hw }, 625 { .hw = &gpll3.clkr.hw }, 626 }; 627 628 static const struct parent_map gcc_parent_map_9[] = { 629 { P_BI_TCXO, 0 }, 630 { P_GPLL0_OUT_EARLY, 1 }, 631 { P_GPLL0_OUT_AUX2, 2 }, 632 { P_GPLL10_OUT_MAIN, 3 }, 633 { P_GPLL8_OUT_MAIN, 4 }, 634 { P_GPLL9_OUT_MAIN, 5 }, 635 { P_GPLL3_OUT_EARLY, 6 }, 636 }; 637 638 static const struct clk_parent_data gcc_parents_9[] = { 639 { .fw_name = "bi_tcxo" }, 640 { .hw = &gpll0.clkr.hw }, 641 { .hw = &gpll0_out_aux2.clkr.hw }, 642 { .hw = &gpll10_out_main.clkr.hw }, 643 { .hw = &gpll8_out_main.clkr.hw }, 644 { .hw = &gpll9_out_main.clkr.hw }, 645 { .hw = &gpll3.clkr.hw }, 646 }; 647 648 static const struct parent_map gcc_parent_map_10[] = { 649 { P_BI_TCXO, 0 }, 650 { P_GPLL0_OUT_EARLY, 1 }, 651 { P_GPLL8_OUT_EARLY, 2 }, 652 { P_GPLL10_OUT_MAIN, 3 }, 653 { P_GPLL6_OUT_EARLY, 4 }, 654 { P_GPLL9_OUT_MAIN, 5 }, 655 }; 656 657 static const struct clk_parent_data gcc_parents_10[] = { 658 { .fw_name = "bi_tcxo" }, 659 { .hw = &gpll0.clkr.hw }, 660 { .hw = &gpll8.clkr.hw }, 661 { .hw = &gpll10_out_main.clkr.hw }, 662 { .hw = &gpll6.clkr.hw }, 663 { .hw = &gpll9_out_main.clkr.hw }, 664 }; 665 666 static const struct parent_map gcc_parent_map_11[] = { 667 { P_BI_TCXO, 0 }, 668 { P_GPLL0_OUT_EARLY, 1 }, 669 { P_GPLL0_OUT_AUX2, 2 }, 670 { P_GPLL7_OUT_MAIN, 3 }, 671 { P_GPLL4_OUT_MAIN, 5 }, 672 }; 673 674 static const struct clk_parent_data gcc_parents_11[] = { 675 { .fw_name = "bi_tcxo" }, 676 { .hw = &gpll0.clkr.hw }, 677 { .hw = &gpll0_out_aux2.clkr.hw }, 678 { .hw = &gpll7_out_main.clkr.hw }, 679 { .hw = &gpll4_out_main.clkr.hw }, 680 }; 681 682 static const struct parent_map gcc_parent_map_12[] = { 683 { P_BI_TCXO, 0 }, 684 { P_SLEEP_CLK, 5 }, 685 }; 686 687 static const struct clk_parent_data gcc_parents_12[] = { 688 { .fw_name = "bi_tcxo" }, 689 { .fw_name = "sleep_clk" }, 690 }; 691 692 static const struct parent_map gcc_parent_map_13[] = { 693 { P_BI_TCXO, 0 }, 694 { P_GPLL11_OUT_MAIN, 1 }, 695 }; 696 697 static const struct clk_parent_data gcc_parents_13[] = { 698 { .fw_name = "bi_tcxo" }, 699 { .hw = &gpll11_out_main.clkr.hw }, 700 }; 701 702 static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = { 703 F(19200000, P_BI_TCXO, 1, 0, 0), 704 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 705 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 706 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 707 { } 708 }; 709 710 static struct clk_rcg2 gcc_camss_axi_clk_src = { 711 .cmd_rcgr = 0x5802c, 712 .mnd_width = 0, 713 .hid_width = 5, 714 .parent_map = gcc_parent_map_7, 715 .freq_tbl = ftbl_gcc_camss_axi_clk_src, 716 .clkr.hw.init = &(struct clk_init_data){ 717 .name = "gcc_camss_axi_clk_src", 718 .parent_data = gcc_parents_7, 719 .num_parents = ARRAY_SIZE(gcc_parents_7), 720 .flags = CLK_SET_RATE_PARENT, 721 .ops = &clk_rcg2_ops, 722 }, 723 }; 724 725 static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = { 726 F(19200000, P_BI_TCXO, 1, 0, 0), 727 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 728 { } 729 }; 730 731 static struct clk_rcg2 gcc_camss_cci_clk_src = { 732 .cmd_rcgr = 0x56000, 733 .mnd_width = 0, 734 .hid_width = 5, 735 .parent_map = gcc_parent_map_9, 736 .freq_tbl = ftbl_gcc_camss_cci_clk_src, 737 .clkr.hw.init = &(struct clk_init_data){ 738 .name = "gcc_camss_cci_clk_src", 739 .parent_data = gcc_parents_9, 740 .num_parents = ARRAY_SIZE(gcc_parents_9), 741 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 742 .ops = &clk_rcg2_ops, 743 }, 744 }; 745 746 static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = { 747 F(19200000, P_BI_TCXO, 1, 0, 0), 748 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 749 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 750 F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0), 751 { } 752 }; 753 754 static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { 755 .cmd_rcgr = 0x59000, 756 .mnd_width = 0, 757 .hid_width = 5, 758 .parent_map = gcc_parent_map_4, 759 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 760 .clkr.hw.init = &(struct clk_init_data){ 761 .name = "gcc_camss_csi0phytimer_clk_src", 762 .parent_data = gcc_parents_4, 763 .num_parents = ARRAY_SIZE(gcc_parents_4), 764 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 765 .ops = &clk_rcg2_ops, 766 }, 767 }; 768 769 static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { 770 .cmd_rcgr = 0x5901c, 771 .mnd_width = 0, 772 .hid_width = 5, 773 .parent_map = gcc_parent_map_4, 774 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 775 .clkr.hw.init = &(struct clk_init_data){ 776 .name = "gcc_camss_csi1phytimer_clk_src", 777 .parent_data = gcc_parents_4, 778 .num_parents = ARRAY_SIZE(gcc_parents_4), 779 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 780 .ops = &clk_rcg2_ops, 781 }, 782 }; 783 784 static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = { 785 .cmd_rcgr = 0x59038, 786 .mnd_width = 0, 787 .hid_width = 5, 788 .parent_map = gcc_parent_map_4, 789 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 790 .clkr.hw.init = &(struct clk_init_data){ 791 .name = "gcc_camss_csi2phytimer_clk_src", 792 .parent_data = gcc_parents_4, 793 .num_parents = ARRAY_SIZE(gcc_parents_4), 794 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 795 .ops = &clk_rcg2_ops, 796 }, 797 }; 798 799 static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { 800 F(19200000, P_BI_TCXO, 1, 0, 0), 801 F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24), 802 F(64000000, P_GPLL9_OUT_MAIN, 1, 1, 9), 803 { } 804 }; 805 806 static struct clk_rcg2 gcc_camss_mclk0_clk_src = { 807 .cmd_rcgr = 0x51000, 808 .mnd_width = 8, 809 .hid_width = 5, 810 .parent_map = gcc_parent_map_3, 811 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 812 .clkr.hw.init = &(struct clk_init_data){ 813 .name = "gcc_camss_mclk0_clk_src", 814 .parent_data = gcc_parents_3, 815 .num_parents = ARRAY_SIZE(gcc_parents_3), 816 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 817 .ops = &clk_rcg2_ops, 818 }, 819 }; 820 821 static struct clk_rcg2 gcc_camss_mclk1_clk_src = { 822 .cmd_rcgr = 0x5101c, 823 .mnd_width = 8, 824 .hid_width = 5, 825 .parent_map = gcc_parent_map_3, 826 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 827 .clkr.hw.init = &(struct clk_init_data){ 828 .name = "gcc_camss_mclk1_clk_src", 829 .parent_data = gcc_parents_3, 830 .num_parents = ARRAY_SIZE(gcc_parents_3), 831 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 832 .ops = &clk_rcg2_ops, 833 }, 834 }; 835 836 static struct clk_rcg2 gcc_camss_mclk2_clk_src = { 837 .cmd_rcgr = 0x51038, 838 .mnd_width = 8, 839 .hid_width = 5, 840 .parent_map = gcc_parent_map_3, 841 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 842 .clkr.hw.init = &(struct clk_init_data){ 843 .name = "gcc_camss_mclk2_clk_src", 844 .parent_data = gcc_parents_3, 845 .num_parents = ARRAY_SIZE(gcc_parents_3), 846 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 847 .ops = &clk_rcg2_ops, 848 }, 849 }; 850 851 static struct clk_rcg2 gcc_camss_mclk3_clk_src = { 852 .cmd_rcgr = 0x51054, 853 .mnd_width = 8, 854 .hid_width = 5, 855 .parent_map = gcc_parent_map_3, 856 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 857 .clkr.hw.init = &(struct clk_init_data){ 858 .name = "gcc_camss_mclk3_clk_src", 859 .parent_data = gcc_parents_3, 860 .num_parents = ARRAY_SIZE(gcc_parents_3), 861 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 862 .ops = &clk_rcg2_ops, 863 }, 864 }; 865 866 static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = { 867 F(19200000, P_BI_TCXO, 1, 0, 0), 868 F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0), 869 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 870 { } 871 }; 872 873 static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = { 874 .cmd_rcgr = 0x55024, 875 .mnd_width = 0, 876 .hid_width = 5, 877 .parent_map = gcc_parent_map_8, 878 .freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src, 879 .clkr.hw.init = &(struct clk_init_data){ 880 .name = "gcc_camss_ope_ahb_clk_src", 881 .parent_data = gcc_parents_8, 882 .num_parents = ARRAY_SIZE(gcc_parents_8), 883 .flags = CLK_SET_RATE_PARENT, 884 .ops = &clk_rcg2_ops, 885 }, 886 }; 887 888 static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = { 889 F(19200000, P_BI_TCXO, 1, 0, 0), 890 F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0), 891 F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0), 892 F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0), 893 F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0), 894 { } 895 }; 896 897 static struct clk_rcg2 gcc_camss_ope_clk_src = { 898 .cmd_rcgr = 0x55004, 899 .mnd_width = 0, 900 .hid_width = 5, 901 .parent_map = gcc_parent_map_8, 902 .freq_tbl = ftbl_gcc_camss_ope_clk_src, 903 .clkr.hw.init = &(struct clk_init_data){ 904 .name = "gcc_camss_ope_clk_src", 905 .parent_data = gcc_parents_8, 906 .num_parents = ARRAY_SIZE(gcc_parents_8), 907 .flags = CLK_SET_RATE_PARENT, 908 .ops = &clk_rcg2_ops, 909 }, 910 }; 911 912 static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = { 913 F(19200000, P_BI_TCXO, 1, 0, 0), 914 F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0), 915 F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0), 916 F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0), 917 F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0), 918 F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0), 919 F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0), 920 F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0), 921 F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0), 922 F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0), 923 F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0), 924 F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0), 925 F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0), 926 F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0), 927 F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0), 928 F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0), 929 { } 930 }; 931 932 static struct clk_rcg2 gcc_camss_tfe_0_clk_src = { 933 .cmd_rcgr = 0x52004, 934 .mnd_width = 8, 935 .hid_width = 5, 936 .parent_map = gcc_parent_map_5, 937 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 938 .clkr.hw.init = &(struct clk_init_data){ 939 .name = "gcc_camss_tfe_0_clk_src", 940 .parent_data = gcc_parents_5, 941 .num_parents = ARRAY_SIZE(gcc_parents_5), 942 .flags = CLK_SET_RATE_PARENT, 943 .ops = &clk_rcg2_ops, 944 }, 945 }; 946 947 static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = { 948 F(19200000, P_BI_TCXO, 1, 0, 0), 949 F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0), 950 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 951 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 952 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 953 F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0), 954 { } 955 }; 956 957 static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = { 958 .cmd_rcgr = 0x52094, 959 .mnd_width = 0, 960 .hid_width = 5, 961 .parent_map = gcc_parent_map_6, 962 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 963 .clkr.hw.init = &(struct clk_init_data){ 964 .name = "gcc_camss_tfe_0_csid_clk_src", 965 .parent_data = gcc_parents_6, 966 .num_parents = ARRAY_SIZE(gcc_parents_6), 967 .flags = CLK_SET_RATE_PARENT, 968 .ops = &clk_rcg2_ops, 969 }, 970 }; 971 972 static struct clk_rcg2 gcc_camss_tfe_1_clk_src = { 973 .cmd_rcgr = 0x52024, 974 .mnd_width = 8, 975 .hid_width = 5, 976 .parent_map = gcc_parent_map_5, 977 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 978 .clkr.hw.init = &(struct clk_init_data){ 979 .name = "gcc_camss_tfe_1_clk_src", 980 .parent_data = gcc_parents_5, 981 .num_parents = ARRAY_SIZE(gcc_parents_5), 982 .flags = CLK_SET_RATE_PARENT, 983 .ops = &clk_rcg2_ops, 984 }, 985 }; 986 987 static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = { 988 .cmd_rcgr = 0x520b4, 989 .mnd_width = 0, 990 .hid_width = 5, 991 .parent_map = gcc_parent_map_6, 992 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 993 .clkr.hw.init = &(struct clk_init_data){ 994 .name = "gcc_camss_tfe_1_csid_clk_src", 995 .parent_data = gcc_parents_6, 996 .num_parents = ARRAY_SIZE(gcc_parents_6), 997 .flags = CLK_SET_RATE_PARENT, 998 .ops = &clk_rcg2_ops, 999 }, 1000 }; 1001 1002 static struct clk_rcg2 gcc_camss_tfe_2_clk_src = { 1003 .cmd_rcgr = 0x52044, 1004 .mnd_width = 8, 1005 .hid_width = 5, 1006 .parent_map = gcc_parent_map_5, 1007 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 1008 .clkr.hw.init = &(struct clk_init_data){ 1009 .name = "gcc_camss_tfe_2_clk_src", 1010 .parent_data = gcc_parents_5, 1011 .num_parents = ARRAY_SIZE(gcc_parents_5), 1012 .flags = CLK_SET_RATE_PARENT, 1013 .ops = &clk_rcg2_ops, 1014 }, 1015 }; 1016 1017 static struct clk_rcg2 gcc_camss_tfe_2_csid_clk_src = { 1018 .cmd_rcgr = 0x520d4, 1019 .mnd_width = 0, 1020 .hid_width = 5, 1021 .parent_map = gcc_parent_map_6, 1022 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 1023 .clkr.hw.init = &(struct clk_init_data){ 1024 .name = "gcc_camss_tfe_2_csid_clk_src", 1025 .parent_data = gcc_parents_6, 1026 .num_parents = ARRAY_SIZE(gcc_parents_6), 1027 .flags = CLK_SET_RATE_PARENT, 1028 .ops = &clk_rcg2_ops, 1029 }, 1030 }; 1031 1032 static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = { 1033 F(19200000, P_BI_TCXO, 1, 0, 0), 1034 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1035 F(341333333, P_GPLL6_OUT_EARLY, 1, 4, 9), 1036 F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0), 1037 { } 1038 }; 1039 1040 static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = { 1041 .cmd_rcgr = 0x52064, 1042 .mnd_width = 16, 1043 .hid_width = 5, 1044 .parent_map = gcc_parent_map_10, 1045 .freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src, 1046 .clkr.hw.init = &(struct clk_init_data){ 1047 .name = "gcc_camss_tfe_cphy_rx_clk_src", 1048 .parent_data = gcc_parents_10, 1049 .num_parents = ARRAY_SIZE(gcc_parents_10), 1050 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 1051 .ops = &clk_rcg2_ops, 1052 }, 1053 }; 1054 1055 static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = { 1056 F(19200000, P_BI_TCXO, 1, 0, 0), 1057 F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0), 1058 F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0), 1059 { } 1060 }; 1061 1062 static struct clk_rcg2 gcc_camss_top_ahb_clk_src = { 1063 .cmd_rcgr = 0x58010, 1064 .mnd_width = 0, 1065 .hid_width = 5, 1066 .parent_map = gcc_parent_map_7, 1067 .freq_tbl = ftbl_gcc_camss_top_ahb_clk_src, 1068 .clkr.hw.init = &(struct clk_init_data){ 1069 .name = "gcc_camss_top_ahb_clk_src", 1070 .parent_data = gcc_parents_7, 1071 .num_parents = ARRAY_SIZE(gcc_parents_7), 1072 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 1073 .ops = &clk_rcg2_ops, 1074 }, 1075 }; 1076 1077 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 1078 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1079 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1080 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1081 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 1082 { } 1083 }; 1084 1085 static struct clk_rcg2 gcc_gp1_clk_src = { 1086 .cmd_rcgr = 0x4d004, 1087 .mnd_width = 8, 1088 .hid_width = 5, 1089 .parent_map = gcc_parent_map_2, 1090 .freq_tbl = ftbl_gcc_gp1_clk_src, 1091 .clkr.hw.init = &(struct clk_init_data){ 1092 .name = "gcc_gp1_clk_src", 1093 .parent_data = gcc_parents_2, 1094 .num_parents = ARRAY_SIZE(gcc_parents_2), 1095 .ops = &clk_rcg2_ops, 1096 }, 1097 }; 1098 1099 static struct clk_rcg2 gcc_gp2_clk_src = { 1100 .cmd_rcgr = 0x4e004, 1101 .mnd_width = 8, 1102 .hid_width = 5, 1103 .parent_map = gcc_parent_map_2, 1104 .freq_tbl = ftbl_gcc_gp1_clk_src, 1105 .clkr.hw.init = &(struct clk_init_data){ 1106 .name = "gcc_gp2_clk_src", 1107 .parent_data = gcc_parents_2, 1108 .num_parents = ARRAY_SIZE(gcc_parents_2), 1109 .ops = &clk_rcg2_ops, 1110 }, 1111 }; 1112 1113 static struct clk_rcg2 gcc_gp3_clk_src = { 1114 .cmd_rcgr = 0x4f004, 1115 .mnd_width = 8, 1116 .hid_width = 5, 1117 .parent_map = gcc_parent_map_2, 1118 .freq_tbl = ftbl_gcc_gp1_clk_src, 1119 .clkr.hw.init = &(struct clk_init_data){ 1120 .name = "gcc_gp3_clk_src", 1121 .parent_data = gcc_parents_2, 1122 .num_parents = ARRAY_SIZE(gcc_parents_2), 1123 .ops = &clk_rcg2_ops, 1124 }, 1125 }; 1126 1127 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 1128 F(19200000, P_BI_TCXO, 1, 0, 0), 1129 F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0), 1130 { } 1131 }; 1132 1133 static struct clk_rcg2 gcc_pdm2_clk_src = { 1134 .cmd_rcgr = 0x20010, 1135 .mnd_width = 0, 1136 .hid_width = 5, 1137 .parent_map = gcc_parent_map_0, 1138 .freq_tbl = ftbl_gcc_pdm2_clk_src, 1139 .clkr.hw.init = &(struct clk_init_data){ 1140 .name = "gcc_pdm2_clk_src", 1141 .parent_data = gcc_parents_0, 1142 .num_parents = ARRAY_SIZE(gcc_parents_0), 1143 .ops = &clk_rcg2_ops, 1144 }, 1145 }; 1146 1147 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 1148 F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625), 1149 F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625), 1150 F(19200000, P_BI_TCXO, 1, 0, 0), 1151 F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625), 1152 F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75), 1153 F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25), 1154 F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75), 1155 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1156 F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15), 1157 F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25), 1158 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1159 F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375), 1160 F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75), 1161 F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625), 1162 F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0), 1163 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0), 1164 { } 1165 }; 1166 1167 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 1168 .name = "gcc_qupv3_wrap0_s0_clk_src", 1169 .parent_data = gcc_parents_1, 1170 .num_parents = ARRAY_SIZE(gcc_parents_1), 1171 .ops = &clk_rcg2_ops, 1172 }; 1173 1174 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 1175 .cmd_rcgr = 0x1f148, 1176 .mnd_width = 16, 1177 .hid_width = 5, 1178 .parent_map = gcc_parent_map_1, 1179 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1180 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 1181 }; 1182 1183 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 1184 .name = "gcc_qupv3_wrap0_s1_clk_src", 1185 .parent_data = gcc_parents_1, 1186 .num_parents = ARRAY_SIZE(gcc_parents_1), 1187 .ops = &clk_rcg2_ops, 1188 }; 1189 1190 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 1191 .cmd_rcgr = 0x1f278, 1192 .mnd_width = 16, 1193 .hid_width = 5, 1194 .parent_map = gcc_parent_map_1, 1195 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1196 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 1197 }; 1198 1199 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 1200 .name = "gcc_qupv3_wrap0_s2_clk_src", 1201 .parent_data = gcc_parents_1, 1202 .num_parents = ARRAY_SIZE(gcc_parents_1), 1203 .ops = &clk_rcg2_ops, 1204 }; 1205 1206 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 1207 .cmd_rcgr = 0x1f3a8, 1208 .mnd_width = 16, 1209 .hid_width = 5, 1210 .parent_map = gcc_parent_map_1, 1211 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1212 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 1213 }; 1214 1215 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 1216 .name = "gcc_qupv3_wrap0_s3_clk_src", 1217 .parent_data = gcc_parents_1, 1218 .num_parents = ARRAY_SIZE(gcc_parents_1), 1219 .ops = &clk_rcg2_ops, 1220 }; 1221 1222 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 1223 .cmd_rcgr = 0x1f4d8, 1224 .mnd_width = 16, 1225 .hid_width = 5, 1226 .parent_map = gcc_parent_map_1, 1227 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1228 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 1229 }; 1230 1231 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 1232 .name = "gcc_qupv3_wrap0_s4_clk_src", 1233 .parent_data = gcc_parents_1, 1234 .num_parents = ARRAY_SIZE(gcc_parents_1), 1235 .ops = &clk_rcg2_ops, 1236 }; 1237 1238 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 1239 .cmd_rcgr = 0x1f608, 1240 .mnd_width = 16, 1241 .hid_width = 5, 1242 .parent_map = gcc_parent_map_1, 1243 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1244 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 1245 }; 1246 1247 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 1248 .name = "gcc_qupv3_wrap0_s5_clk_src", 1249 .parent_data = gcc_parents_1, 1250 .num_parents = ARRAY_SIZE(gcc_parents_1), 1251 .ops = &clk_rcg2_ops, 1252 }; 1253 1254 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 1255 .cmd_rcgr = 0x1f738, 1256 .mnd_width = 16, 1257 .hid_width = 5, 1258 .parent_map = gcc_parent_map_1, 1259 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1260 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 1261 }; 1262 1263 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 1264 F(144000, P_BI_TCXO, 16, 3, 25), 1265 F(400000, P_BI_TCXO, 12, 1, 4), 1266 F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3), 1267 F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2), 1268 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1269 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1270 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 1271 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 1272 { } 1273 }; 1274 1275 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 1276 .cmd_rcgr = 0x38028, 1277 .mnd_width = 8, 1278 .hid_width = 5, 1279 .parent_map = gcc_parent_map_1, 1280 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 1281 .clkr.hw.init = &(struct clk_init_data){ 1282 .name = "gcc_sdcc1_apps_clk_src", 1283 .parent_data = gcc_parents_1, 1284 .num_parents = ARRAY_SIZE(gcc_parents_1), 1285 .ops = &clk_rcg2_ops, 1286 }, 1287 }; 1288 1289 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 1290 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1291 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1292 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1293 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1294 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 1295 { } 1296 }; 1297 1298 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 1299 .cmd_rcgr = 0x38010, 1300 .mnd_width = 0, 1301 .hid_width = 5, 1302 .parent_map = gcc_parent_map_0, 1303 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 1304 .clkr.hw.init = &(struct clk_init_data){ 1305 .name = "gcc_sdcc1_ice_core_clk_src", 1306 .parent_data = gcc_parents_0, 1307 .num_parents = ARRAY_SIZE(gcc_parents_0), 1308 .ops = &clk_rcg2_ops, 1309 }, 1310 }; 1311 1312 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1313 F(400000, P_BI_TCXO, 12, 1, 4), 1314 F(19200000, P_BI_TCXO, 1, 0, 0), 1315 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1316 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1317 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1318 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1319 { } 1320 }; 1321 1322 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1323 .cmd_rcgr = 0x1e00c, 1324 .mnd_width = 8, 1325 .hid_width = 5, 1326 .parent_map = gcc_parent_map_11, 1327 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1328 .clkr.hw.init = &(struct clk_init_data){ 1329 .name = "gcc_sdcc2_apps_clk_src", 1330 .parent_data = gcc_parents_11, 1331 .num_parents = ARRAY_SIZE(gcc_parents_11), 1332 .ops = &clk_rcg2_ops, 1333 .flags = CLK_OPS_PARENT_ENABLE, 1334 }, 1335 }; 1336 1337 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1338 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1339 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1340 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1341 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1342 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1343 { } 1344 }; 1345 1346 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1347 .cmd_rcgr = 0x45020, 1348 .mnd_width = 8, 1349 .hid_width = 5, 1350 .parent_map = gcc_parent_map_0, 1351 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1352 .clkr.hw.init = &(struct clk_init_data){ 1353 .name = "gcc_ufs_phy_axi_clk_src", 1354 .parent_data = gcc_parents_0, 1355 .num_parents = ARRAY_SIZE(gcc_parents_0), 1356 .ops = &clk_rcg2_ops, 1357 }, 1358 }; 1359 1360 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1361 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 1362 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1363 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1364 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 1365 { } 1366 }; 1367 1368 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1369 .cmd_rcgr = 0x45048, 1370 .mnd_width = 0, 1371 .hid_width = 5, 1372 .parent_map = gcc_parent_map_0, 1373 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1374 .clkr.hw.init = &(struct clk_init_data){ 1375 .name = "gcc_ufs_phy_ice_core_clk_src", 1376 .parent_data = gcc_parents_0, 1377 .num_parents = ARRAY_SIZE(gcc_parents_0), 1378 .ops = &clk_rcg2_ops, 1379 }, 1380 }; 1381 1382 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1383 F(9600000, P_BI_TCXO, 2, 0, 0), 1384 F(19200000, P_BI_TCXO, 1, 0, 0), 1385 { } 1386 }; 1387 1388 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1389 .cmd_rcgr = 0x4507c, 1390 .mnd_width = 0, 1391 .hid_width = 5, 1392 .parent_map = gcc_parent_map_0, 1393 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1394 .clkr.hw.init = &(struct clk_init_data){ 1395 .name = "gcc_ufs_phy_phy_aux_clk_src", 1396 .parent_data = gcc_parents_0, 1397 .num_parents = ARRAY_SIZE(gcc_parents_0), 1398 .ops = &clk_rcg2_ops, 1399 }, 1400 }; 1401 1402 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 1403 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 1404 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1405 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1406 { } 1407 }; 1408 1409 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1410 .cmd_rcgr = 0x45060, 1411 .mnd_width = 0, 1412 .hid_width = 5, 1413 .parent_map = gcc_parent_map_0, 1414 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 1415 .clkr.hw.init = &(struct clk_init_data){ 1416 .name = "gcc_ufs_phy_unipro_core_clk_src", 1417 .parent_data = gcc_parents_0, 1418 .num_parents = ARRAY_SIZE(gcc_parents_0), 1419 .ops = &clk_rcg2_ops, 1420 }, 1421 }; 1422 1423 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1424 F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0), 1425 F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0), 1426 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1427 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1428 { } 1429 }; 1430 1431 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1432 .cmd_rcgr = 0x1a01c, 1433 .mnd_width = 8, 1434 .hid_width = 5, 1435 .parent_map = gcc_parent_map_0, 1436 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1437 .clkr.hw.init = &(struct clk_init_data){ 1438 .name = "gcc_usb30_prim_master_clk_src", 1439 .parent_data = gcc_parents_0, 1440 .num_parents = ARRAY_SIZE(gcc_parents_0), 1441 .ops = &clk_rcg2_ops, 1442 }, 1443 }; 1444 1445 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 1446 F(19200000, P_BI_TCXO, 1, 0, 0), 1447 { } 1448 }; 1449 1450 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1451 .cmd_rcgr = 0x1a034, 1452 .mnd_width = 0, 1453 .hid_width = 5, 1454 .parent_map = gcc_parent_map_0, 1455 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1456 .clkr.hw.init = &(struct clk_init_data){ 1457 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1458 .parent_data = gcc_parents_0, 1459 .num_parents = ARRAY_SIZE(gcc_parents_0), 1460 .ops = &clk_rcg2_ops, 1461 }, 1462 }; 1463 1464 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1465 .reg = 0x1a04c, 1466 .shift = 0, 1467 .width = 2, 1468 .clkr.hw.init = &(struct clk_init_data) { 1469 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1470 .parent_hws = (const struct clk_hw *[]) { 1471 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw }, 1472 .num_parents = 1, 1473 .ops = &clk_regmap_div_ro_ops, 1474 }, 1475 }; 1476 1477 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1478 .cmd_rcgr = 0x1a060, 1479 .mnd_width = 0, 1480 .hid_width = 5, 1481 .parent_map = gcc_parent_map_12, 1482 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1483 .clkr.hw.init = &(struct clk_init_data){ 1484 .name = "gcc_usb3_prim_phy_aux_clk_src", 1485 .parent_data = gcc_parents_12, 1486 .num_parents = ARRAY_SIZE(gcc_parents_12), 1487 .ops = &clk_rcg2_ops, 1488 }, 1489 }; 1490 1491 static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = { 1492 F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0), 1493 F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0), 1494 F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0), 1495 F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0), 1496 { } 1497 }; 1498 1499 static struct clk_rcg2 gcc_video_venus_clk_src = { 1500 .cmd_rcgr = 0x58060, 1501 .mnd_width = 0, 1502 .hid_width = 5, 1503 .parent_map = gcc_parent_map_13, 1504 .freq_tbl = ftbl_gcc_video_venus_clk_src, 1505 .clkr.hw.init = &(struct clk_init_data){ 1506 .name = "gcc_video_venus_clk_src", 1507 .parent_data = gcc_parents_13, 1508 .num_parents = ARRAY_SIZE(gcc_parents_13), 1509 .flags = CLK_SET_RATE_PARENT, 1510 .ops = &clk_rcg2_ops, 1511 }, 1512 }; 1513 1514 static struct clk_branch gcc_ahb2phy_csi_clk = { 1515 .halt_reg = 0x1d004, 1516 .halt_check = BRANCH_HALT, 1517 .hwcg_reg = 0x1d004, 1518 .hwcg_bit = 1, 1519 .clkr = { 1520 .enable_reg = 0x1d004, 1521 .enable_mask = BIT(0), 1522 .hw.init = &(struct clk_init_data){ 1523 .name = "gcc_ahb2phy_csi_clk", 1524 .ops = &clk_branch2_ops, 1525 }, 1526 }, 1527 }; 1528 1529 static struct clk_branch gcc_ahb2phy_usb_clk = { 1530 .halt_reg = 0x1d008, 1531 .halt_check = BRANCH_HALT, 1532 .hwcg_reg = 0x1d008, 1533 .hwcg_bit = 1, 1534 .clkr = { 1535 .enable_reg = 0x1d008, 1536 .enable_mask = BIT(0), 1537 .hw.init = &(struct clk_init_data){ 1538 .name = "gcc_ahb2phy_usb_clk", 1539 .ops = &clk_branch2_ops, 1540 }, 1541 }, 1542 }; 1543 1544 static struct clk_branch gcc_bimc_gpu_axi_clk = { 1545 .halt_reg = 0x71154, 1546 .halt_check = BRANCH_HALT_DELAY, 1547 .hwcg_reg = 0x71154, 1548 .hwcg_bit = 1, 1549 .clkr = { 1550 .enable_reg = 0x71154, 1551 .enable_mask = BIT(0), 1552 .hw.init = &(struct clk_init_data){ 1553 .name = "gcc_bimc_gpu_axi_clk", 1554 .ops = &clk_branch2_ops, 1555 }, 1556 }, 1557 }; 1558 1559 static struct clk_branch gcc_boot_rom_ahb_clk = { 1560 .halt_reg = 0x23004, 1561 .halt_check = BRANCH_HALT_VOTED, 1562 .hwcg_reg = 0x23004, 1563 .hwcg_bit = 1, 1564 .clkr = { 1565 .enable_reg = 0x79004, 1566 .enable_mask = BIT(10), 1567 .hw.init = &(struct clk_init_data){ 1568 .name = "gcc_boot_rom_ahb_clk", 1569 .ops = &clk_branch2_ops, 1570 }, 1571 }, 1572 }; 1573 1574 static struct clk_branch gcc_cam_throttle_nrt_clk = { 1575 .halt_reg = 0x17070, 1576 .halt_check = BRANCH_HALT_VOTED, 1577 .hwcg_reg = 0x17070, 1578 .hwcg_bit = 1, 1579 .clkr = { 1580 .enable_reg = 0x79004, 1581 .enable_mask = BIT(27), 1582 .hw.init = &(struct clk_init_data){ 1583 .name = "gcc_cam_throttle_nrt_clk", 1584 .ops = &clk_branch2_ops, 1585 }, 1586 }, 1587 }; 1588 1589 static struct clk_branch gcc_cam_throttle_rt_clk = { 1590 .halt_reg = 0x1706c, 1591 .halt_check = BRANCH_HALT_VOTED, 1592 .hwcg_reg = 0x1706c, 1593 .hwcg_bit = 1, 1594 .clkr = { 1595 .enable_reg = 0x79004, 1596 .enable_mask = BIT(26), 1597 .hw.init = &(struct clk_init_data){ 1598 .name = "gcc_cam_throttle_rt_clk", 1599 .ops = &clk_branch2_ops, 1600 }, 1601 }, 1602 }; 1603 1604 static struct clk_branch gcc_camera_ahb_clk = { 1605 .halt_reg = 0x17008, 1606 .halt_check = BRANCH_HALT_DELAY, 1607 .hwcg_reg = 0x17008, 1608 .hwcg_bit = 1, 1609 .clkr = { 1610 .enable_reg = 0x17008, 1611 .enable_mask = BIT(0), 1612 .hw.init = &(struct clk_init_data){ 1613 .name = "gcc_camera_ahb_clk", 1614 .flags = CLK_IS_CRITICAL, 1615 .ops = &clk_branch2_ops, 1616 }, 1617 }, 1618 }; 1619 1620 static struct clk_branch gcc_camera_xo_clk = { 1621 .halt_reg = 0x17028, 1622 .halt_check = BRANCH_HALT, 1623 .clkr = { 1624 .enable_reg = 0x17028, 1625 .enable_mask = BIT(0), 1626 .hw.init = &(struct clk_init_data){ 1627 .name = "gcc_camera_xo_clk", 1628 .flags = CLK_IS_CRITICAL, 1629 .ops = &clk_branch2_ops, 1630 }, 1631 }, 1632 }; 1633 1634 static struct clk_branch gcc_camss_axi_clk = { 1635 .halt_reg = 0x58044, 1636 .halt_check = BRANCH_HALT, 1637 .clkr = { 1638 .enable_reg = 0x58044, 1639 .enable_mask = BIT(0), 1640 .hw.init = &(struct clk_init_data){ 1641 .name = "gcc_camss_axi_clk", 1642 .parent_hws = (const struct clk_hw *[]){ 1643 &gcc_camss_axi_clk_src.clkr.hw, 1644 }, 1645 .num_parents = 1, 1646 .flags = CLK_SET_RATE_PARENT, 1647 .ops = &clk_branch2_ops, 1648 }, 1649 }, 1650 }; 1651 1652 static struct clk_branch gcc_camss_camnoc_atb_clk = { 1653 .halt_reg = 0x5804c, 1654 .halt_check = BRANCH_HALT_DELAY, 1655 .hwcg_reg = 0x5804c, 1656 .hwcg_bit = 1, 1657 .clkr = { 1658 .enable_reg = 0x5804c, 1659 .enable_mask = BIT(0), 1660 .hw.init = &(struct clk_init_data){ 1661 .name = "gcc_camss_camnoc_atb_clk", 1662 .ops = &clk_branch2_ops, 1663 }, 1664 }, 1665 }; 1666 1667 static struct clk_branch gcc_camss_camnoc_nts_xo_clk = { 1668 .halt_reg = 0x58050, 1669 .halt_check = BRANCH_HALT_DELAY, 1670 .hwcg_reg = 0x58050, 1671 .hwcg_bit = 1, 1672 .clkr = { 1673 .enable_reg = 0x58050, 1674 .enable_mask = BIT(0), 1675 .hw.init = &(struct clk_init_data){ 1676 .name = "gcc_camss_camnoc_nts_xo_clk", 1677 .ops = &clk_branch2_ops, 1678 }, 1679 }, 1680 }; 1681 1682 static struct clk_branch gcc_camss_cci_0_clk = { 1683 .halt_reg = 0x56018, 1684 .halt_check = BRANCH_HALT, 1685 .clkr = { 1686 .enable_reg = 0x56018, 1687 .enable_mask = BIT(0), 1688 .hw.init = &(struct clk_init_data){ 1689 .name = "gcc_camss_cci_0_clk", 1690 .parent_hws = (const struct clk_hw *[]){ 1691 &gcc_camss_cci_clk_src.clkr.hw, 1692 }, 1693 .num_parents = 1, 1694 .flags = CLK_SET_RATE_PARENT, 1695 .ops = &clk_branch2_ops, 1696 }, 1697 }, 1698 }; 1699 1700 static struct clk_branch gcc_camss_cphy_0_clk = { 1701 .halt_reg = 0x52088, 1702 .halt_check = BRANCH_HALT, 1703 .clkr = { 1704 .enable_reg = 0x52088, 1705 .enable_mask = BIT(0), 1706 .hw.init = &(struct clk_init_data){ 1707 .name = "gcc_camss_cphy_0_clk", 1708 .parent_hws = (const struct clk_hw *[]){ 1709 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1710 }, 1711 .num_parents = 1, 1712 .flags = CLK_SET_RATE_PARENT, 1713 .ops = &clk_branch2_ops, 1714 }, 1715 }, 1716 }; 1717 1718 static struct clk_branch gcc_camss_cphy_1_clk = { 1719 .halt_reg = 0x5208c, 1720 .halt_check = BRANCH_HALT, 1721 .clkr = { 1722 .enable_reg = 0x5208c, 1723 .enable_mask = BIT(0), 1724 .hw.init = &(struct clk_init_data){ 1725 .name = "gcc_camss_cphy_1_clk", 1726 .parent_hws = (const struct clk_hw *[]){ 1727 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1728 }, 1729 .num_parents = 1, 1730 .flags = CLK_SET_RATE_PARENT, 1731 .ops = &clk_branch2_ops, 1732 }, 1733 }, 1734 }; 1735 1736 static struct clk_branch gcc_camss_cphy_2_clk = { 1737 .halt_reg = 0x52090, 1738 .halt_check = BRANCH_HALT, 1739 .clkr = { 1740 .enable_reg = 0x52090, 1741 .enable_mask = BIT(0), 1742 .hw.init = &(struct clk_init_data){ 1743 .name = "gcc_camss_cphy_2_clk", 1744 .parent_hws = (const struct clk_hw *[]){ 1745 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1746 }, 1747 .num_parents = 1, 1748 .flags = CLK_SET_RATE_PARENT, 1749 .ops = &clk_branch2_ops, 1750 }, 1751 }, 1752 }; 1753 1754 static struct clk_branch gcc_camss_csi0phytimer_clk = { 1755 .halt_reg = 0x59018, 1756 .halt_check = BRANCH_HALT, 1757 .clkr = { 1758 .enable_reg = 0x59018, 1759 .enable_mask = BIT(0), 1760 .hw.init = &(struct clk_init_data){ 1761 .name = "gcc_camss_csi0phytimer_clk", 1762 .parent_hws = (const struct clk_hw *[]){ 1763 &gcc_camss_csi0phytimer_clk_src.clkr.hw, 1764 }, 1765 .num_parents = 1, 1766 .flags = CLK_SET_RATE_PARENT, 1767 .ops = &clk_branch2_ops, 1768 }, 1769 }, 1770 }; 1771 1772 static struct clk_branch gcc_camss_csi1phytimer_clk = { 1773 .halt_reg = 0x59034, 1774 .halt_check = BRANCH_HALT, 1775 .clkr = { 1776 .enable_reg = 0x59034, 1777 .enable_mask = BIT(0), 1778 .hw.init = &(struct clk_init_data){ 1779 .name = "gcc_camss_csi1phytimer_clk", 1780 .parent_hws = (const struct clk_hw *[]){ 1781 &gcc_camss_csi1phytimer_clk_src.clkr.hw, 1782 }, 1783 .num_parents = 1, 1784 .flags = CLK_SET_RATE_PARENT, 1785 .ops = &clk_branch2_ops, 1786 }, 1787 }, 1788 }; 1789 1790 static struct clk_branch gcc_camss_csi2phytimer_clk = { 1791 .halt_reg = 0x59050, 1792 .halt_check = BRANCH_HALT, 1793 .clkr = { 1794 .enable_reg = 0x59050, 1795 .enable_mask = BIT(0), 1796 .hw.init = &(struct clk_init_data){ 1797 .name = "gcc_camss_csi2phytimer_clk", 1798 .parent_hws = (const struct clk_hw *[]){ 1799 &gcc_camss_csi2phytimer_clk_src.clkr.hw, 1800 }, 1801 .num_parents = 1, 1802 .flags = CLK_SET_RATE_PARENT, 1803 .ops = &clk_branch2_ops, 1804 }, 1805 }, 1806 }; 1807 1808 static struct clk_branch gcc_camss_mclk0_clk = { 1809 .halt_reg = 0x51018, 1810 .halt_check = BRANCH_HALT, 1811 .clkr = { 1812 .enable_reg = 0x51018, 1813 .enable_mask = BIT(0), 1814 .hw.init = &(struct clk_init_data){ 1815 .name = "gcc_camss_mclk0_clk", 1816 .parent_hws = (const struct clk_hw *[]){ 1817 &gcc_camss_mclk0_clk_src.clkr.hw, 1818 }, 1819 .num_parents = 1, 1820 .flags = CLK_SET_RATE_PARENT, 1821 .ops = &clk_branch2_ops, 1822 }, 1823 }, 1824 }; 1825 1826 static struct clk_branch gcc_camss_mclk1_clk = { 1827 .halt_reg = 0x51034, 1828 .halt_check = BRANCH_HALT, 1829 .clkr = { 1830 .enable_reg = 0x51034, 1831 .enable_mask = BIT(0), 1832 .hw.init = &(struct clk_init_data){ 1833 .name = "gcc_camss_mclk1_clk", 1834 .parent_hws = (const struct clk_hw *[]){ 1835 &gcc_camss_mclk1_clk_src.clkr.hw, 1836 }, 1837 .num_parents = 1, 1838 .flags = CLK_SET_RATE_PARENT, 1839 .ops = &clk_branch2_ops, 1840 }, 1841 }, 1842 }; 1843 1844 static struct clk_branch gcc_camss_mclk2_clk = { 1845 .halt_reg = 0x51050, 1846 .halt_check = BRANCH_HALT, 1847 .clkr = { 1848 .enable_reg = 0x51050, 1849 .enable_mask = BIT(0), 1850 .hw.init = &(struct clk_init_data){ 1851 .name = "gcc_camss_mclk2_clk", 1852 .parent_hws = (const struct clk_hw *[]){ 1853 &gcc_camss_mclk2_clk_src.clkr.hw, 1854 }, 1855 .num_parents = 1, 1856 .flags = CLK_SET_RATE_PARENT, 1857 .ops = &clk_branch2_ops, 1858 }, 1859 }, 1860 }; 1861 1862 static struct clk_branch gcc_camss_mclk3_clk = { 1863 .halt_reg = 0x5106c, 1864 .halt_check = BRANCH_HALT, 1865 .clkr = { 1866 .enable_reg = 0x5106c, 1867 .enable_mask = BIT(0), 1868 .hw.init = &(struct clk_init_data){ 1869 .name = "gcc_camss_mclk3_clk", 1870 .parent_hws = (const struct clk_hw *[]){ 1871 &gcc_camss_mclk3_clk_src.clkr.hw, 1872 }, 1873 .num_parents = 1, 1874 .flags = CLK_SET_RATE_PARENT, 1875 .ops = &clk_branch2_ops, 1876 }, 1877 }, 1878 }; 1879 1880 static struct clk_branch gcc_camss_nrt_axi_clk = { 1881 .halt_reg = 0x58054, 1882 .halt_check = BRANCH_HALT, 1883 .clkr = { 1884 .enable_reg = 0x58054, 1885 .enable_mask = BIT(0), 1886 .hw.init = &(struct clk_init_data){ 1887 .name = "gcc_camss_nrt_axi_clk", 1888 .ops = &clk_branch2_ops, 1889 }, 1890 }, 1891 }; 1892 1893 static struct clk_branch gcc_camss_ope_ahb_clk = { 1894 .halt_reg = 0x5503c, 1895 .halt_check = BRANCH_HALT, 1896 .clkr = { 1897 .enable_reg = 0x5503c, 1898 .enable_mask = BIT(0), 1899 .hw.init = &(struct clk_init_data){ 1900 .name = "gcc_camss_ope_ahb_clk", 1901 .parent_hws = (const struct clk_hw *[]){ 1902 &gcc_camss_ope_ahb_clk_src.clkr.hw, 1903 }, 1904 .num_parents = 1, 1905 .flags = CLK_SET_RATE_PARENT, 1906 .ops = &clk_branch2_ops, 1907 }, 1908 }, 1909 }; 1910 1911 static struct clk_branch gcc_camss_ope_clk = { 1912 .halt_reg = 0x5501c, 1913 .halt_check = BRANCH_HALT, 1914 .clkr = { 1915 .enable_reg = 0x5501c, 1916 .enable_mask = BIT(0), 1917 .hw.init = &(struct clk_init_data){ 1918 .name = "gcc_camss_ope_clk", 1919 .parent_hws = (const struct clk_hw *[]){ 1920 &gcc_camss_ope_clk_src.clkr.hw, 1921 }, 1922 .num_parents = 1, 1923 .flags = CLK_SET_RATE_PARENT, 1924 .ops = &clk_branch2_ops, 1925 }, 1926 }, 1927 }; 1928 1929 static struct clk_branch gcc_camss_rt_axi_clk = { 1930 .halt_reg = 0x5805c, 1931 .halt_check = BRANCH_HALT, 1932 .clkr = { 1933 .enable_reg = 0x5805c, 1934 .enable_mask = BIT(0), 1935 .hw.init = &(struct clk_init_data){ 1936 .name = "gcc_camss_rt_axi_clk", 1937 .ops = &clk_branch2_ops, 1938 }, 1939 }, 1940 }; 1941 1942 static struct clk_branch gcc_camss_tfe_0_clk = { 1943 .halt_reg = 0x5201c, 1944 .halt_check = BRANCH_HALT, 1945 .clkr = { 1946 .enable_reg = 0x5201c, 1947 .enable_mask = BIT(0), 1948 .hw.init = &(struct clk_init_data){ 1949 .name = "gcc_camss_tfe_0_clk", 1950 .parent_hws = (const struct clk_hw *[]){ 1951 &gcc_camss_tfe_0_clk_src.clkr.hw, 1952 }, 1953 .num_parents = 1, 1954 .flags = CLK_SET_RATE_PARENT, 1955 .ops = &clk_branch2_ops, 1956 }, 1957 }, 1958 }; 1959 1960 static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = { 1961 .halt_reg = 0x5207c, 1962 .halt_check = BRANCH_HALT, 1963 .clkr = { 1964 .enable_reg = 0x5207c, 1965 .enable_mask = BIT(0), 1966 .hw.init = &(struct clk_init_data){ 1967 .name = "gcc_camss_tfe_0_cphy_rx_clk", 1968 .parent_hws = (const struct clk_hw *[]){ 1969 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1970 }, 1971 .num_parents = 1, 1972 .flags = CLK_SET_RATE_PARENT, 1973 .ops = &clk_branch2_ops, 1974 }, 1975 }, 1976 }; 1977 1978 static struct clk_branch gcc_camss_tfe_0_csid_clk = { 1979 .halt_reg = 0x520ac, 1980 .halt_check = BRANCH_HALT, 1981 .clkr = { 1982 .enable_reg = 0x520ac, 1983 .enable_mask = BIT(0), 1984 .hw.init = &(struct clk_init_data){ 1985 .name = "gcc_camss_tfe_0_csid_clk", 1986 .parent_hws = (const struct clk_hw *[]){ 1987 &gcc_camss_tfe_0_csid_clk_src.clkr.hw, 1988 }, 1989 .num_parents = 1, 1990 .flags = CLK_SET_RATE_PARENT, 1991 .ops = &clk_branch2_ops, 1992 }, 1993 }, 1994 }; 1995 1996 static struct clk_branch gcc_camss_tfe_1_clk = { 1997 .halt_reg = 0x5203c, 1998 .halt_check = BRANCH_HALT, 1999 .clkr = { 2000 .enable_reg = 0x5203c, 2001 .enable_mask = BIT(0), 2002 .hw.init = &(struct clk_init_data){ 2003 .name = "gcc_camss_tfe_1_clk", 2004 .parent_hws = (const struct clk_hw *[]){ 2005 &gcc_camss_tfe_1_clk_src.clkr.hw, 2006 }, 2007 .num_parents = 1, 2008 .flags = CLK_SET_RATE_PARENT, 2009 .ops = &clk_branch2_ops, 2010 }, 2011 }, 2012 }; 2013 2014 static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = { 2015 .halt_reg = 0x52080, 2016 .halt_check = BRANCH_HALT, 2017 .clkr = { 2018 .enable_reg = 0x52080, 2019 .enable_mask = BIT(0), 2020 .hw.init = &(struct clk_init_data){ 2021 .name = "gcc_camss_tfe_1_cphy_rx_clk", 2022 .parent_hws = (const struct clk_hw *[]){ 2023 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2024 }, 2025 .num_parents = 1, 2026 .flags = CLK_SET_RATE_PARENT, 2027 .ops = &clk_branch2_ops, 2028 }, 2029 }, 2030 }; 2031 2032 static struct clk_branch gcc_camss_tfe_1_csid_clk = { 2033 .halt_reg = 0x520cc, 2034 .halt_check = BRANCH_HALT, 2035 .clkr = { 2036 .enable_reg = 0x520cc, 2037 .enable_mask = BIT(0), 2038 .hw.init = &(struct clk_init_data){ 2039 .name = "gcc_camss_tfe_1_csid_clk", 2040 .parent_hws = (const struct clk_hw *[]){ 2041 &gcc_camss_tfe_1_csid_clk_src.clkr.hw, 2042 }, 2043 .num_parents = 1, 2044 .flags = CLK_SET_RATE_PARENT, 2045 .ops = &clk_branch2_ops, 2046 }, 2047 }, 2048 }; 2049 2050 static struct clk_branch gcc_camss_tfe_2_clk = { 2051 .halt_reg = 0x5205c, 2052 .halt_check = BRANCH_HALT, 2053 .clkr = { 2054 .enable_reg = 0x5205c, 2055 .enable_mask = BIT(0), 2056 .hw.init = &(struct clk_init_data){ 2057 .name = "gcc_camss_tfe_2_clk", 2058 .parent_hws = (const struct clk_hw *[]){ 2059 &gcc_camss_tfe_2_clk_src.clkr.hw, 2060 }, 2061 .num_parents = 1, 2062 .flags = CLK_SET_RATE_PARENT, 2063 .ops = &clk_branch2_ops, 2064 }, 2065 }, 2066 }; 2067 2068 static struct clk_branch gcc_camss_tfe_2_cphy_rx_clk = { 2069 .halt_reg = 0x52084, 2070 .halt_check = BRANCH_HALT, 2071 .clkr = { 2072 .enable_reg = 0x52084, 2073 .enable_mask = BIT(0), 2074 .hw.init = &(struct clk_init_data){ 2075 .name = "gcc_camss_tfe_2_cphy_rx_clk", 2076 .parent_hws = (const struct clk_hw *[]){ 2077 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2078 }, 2079 .num_parents = 1, 2080 .flags = CLK_SET_RATE_PARENT, 2081 .ops = &clk_branch2_ops, 2082 }, 2083 }, 2084 }; 2085 2086 static struct clk_branch gcc_camss_tfe_2_csid_clk = { 2087 .halt_reg = 0x520ec, 2088 .halt_check = BRANCH_HALT, 2089 .clkr = { 2090 .enable_reg = 0x520ec, 2091 .enable_mask = BIT(0), 2092 .hw.init = &(struct clk_init_data){ 2093 .name = "gcc_camss_tfe_2_csid_clk", 2094 .parent_hws = (const struct clk_hw *[]){ 2095 &gcc_camss_tfe_2_csid_clk_src.clkr.hw, 2096 }, 2097 .num_parents = 1, 2098 .flags = CLK_SET_RATE_PARENT, 2099 .ops = &clk_branch2_ops, 2100 }, 2101 }, 2102 }; 2103 2104 static struct clk_branch gcc_camss_top_ahb_clk = { 2105 .halt_reg = 0x58028, 2106 .halt_check = BRANCH_HALT, 2107 .clkr = { 2108 .enable_reg = 0x58028, 2109 .enable_mask = BIT(0), 2110 .hw.init = &(struct clk_init_data){ 2111 .name = "gcc_camss_top_ahb_clk", 2112 .parent_hws = (const struct clk_hw *[]){ 2113 &gcc_camss_top_ahb_clk_src.clkr.hw, 2114 }, 2115 .num_parents = 1, 2116 .flags = CLK_SET_RATE_PARENT, 2117 .ops = &clk_branch2_ops, 2118 }, 2119 }, 2120 }; 2121 2122 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 2123 .halt_reg = 0x1a084, 2124 .halt_check = BRANCH_HALT, 2125 .hwcg_reg = 0x1a084, 2126 .hwcg_bit = 1, 2127 .clkr = { 2128 .enable_reg = 0x1a084, 2129 .enable_mask = BIT(0), 2130 .hw.init = &(struct clk_init_data){ 2131 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 2132 .parent_hws = (const struct clk_hw *[]){ 2133 &gcc_usb30_prim_master_clk_src.clkr.hw, 2134 }, 2135 .num_parents = 1, 2136 .flags = CLK_SET_RATE_PARENT, 2137 .ops = &clk_branch2_ops, 2138 }, 2139 }, 2140 }; 2141 2142 static struct clk_branch gcc_cpuss_gnoc_clk = { 2143 .halt_reg = 0x2b004, 2144 .halt_check = BRANCH_HALT_VOTED, 2145 .hwcg_reg = 0x2b004, 2146 .hwcg_bit = 1, 2147 .clkr = { 2148 .enable_reg = 0x79004, 2149 .enable_mask = BIT(22), 2150 .hw.init = &(struct clk_init_data){ 2151 .name = "gcc_cpuss_gnoc_clk", 2152 .flags = CLK_IS_CRITICAL, 2153 .ops = &clk_branch2_ops, 2154 }, 2155 }, 2156 }; 2157 2158 static struct clk_branch gcc_disp_ahb_clk = { 2159 .halt_reg = 0x1700c, 2160 .halt_check = BRANCH_HALT, 2161 .hwcg_reg = 0x1700c, 2162 .hwcg_bit = 1, 2163 .clkr = { 2164 .enable_reg = 0x1700c, 2165 .enable_mask = BIT(0), 2166 .hw.init = &(struct clk_init_data){ 2167 .name = "gcc_disp_ahb_clk", 2168 .flags = CLK_IS_CRITICAL, 2169 .ops = &clk_branch2_ops, 2170 }, 2171 }, 2172 }; 2173 2174 static struct clk_regmap_div gcc_disp_gpll0_clk_src = { 2175 .reg = 0x17058, 2176 .shift = 0, 2177 .width = 2, 2178 .clkr.hw.init = &(struct clk_init_data) { 2179 .name = "gcc_disp_gpll0_clk_src", 2180 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 2181 .num_parents = 1, 2182 .ops = &clk_regmap_div_ops, 2183 }, 2184 }; 2185 2186 static struct clk_branch gcc_disp_gpll0_div_clk_src = { 2187 .halt_check = BRANCH_HALT_DELAY, 2188 .clkr = { 2189 .enable_reg = 0x79004, 2190 .enable_mask = BIT(20), 2191 .hw.init = &(struct clk_init_data){ 2192 .name = "gcc_disp_gpll0_div_clk_src", 2193 .parent_hws = (const struct clk_hw *[]){ 2194 &gcc_disp_gpll0_clk_src.clkr.hw, 2195 }, 2196 .num_parents = 1, 2197 .flags = CLK_SET_RATE_PARENT, 2198 .ops = &clk_branch2_ops, 2199 }, 2200 }, 2201 }; 2202 2203 static struct clk_branch gcc_disp_hf_axi_clk = { 2204 .halt_reg = 0x17020, 2205 .halt_check = BRANCH_HALT, 2206 .hwcg_reg = 0x17020, 2207 .hwcg_bit = 1, 2208 .clkr = { 2209 .enable_reg = 0x17020, 2210 .enable_mask = BIT(0), 2211 .hw.init = &(struct clk_init_data){ 2212 .name = "gcc_disp_hf_axi_clk", 2213 .ops = &clk_branch2_ops, 2214 }, 2215 }, 2216 }; 2217 2218 static struct clk_branch gcc_disp_throttle_core_clk = { 2219 .halt_reg = 0x17064, 2220 .halt_check = BRANCH_HALT_VOTED, 2221 .hwcg_reg = 0x17064, 2222 .hwcg_bit = 1, 2223 .clkr = { 2224 .enable_reg = 0x7900c, 2225 .enable_mask = BIT(5), 2226 .hw.init = &(struct clk_init_data){ 2227 .name = "gcc_disp_throttle_core_clk", 2228 .ops = &clk_branch2_ops, 2229 }, 2230 }, 2231 }; 2232 2233 static struct clk_branch gcc_disp_xo_clk = { 2234 .halt_reg = 0x1702c, 2235 .halt_check = BRANCH_HALT, 2236 .clkr = { 2237 .enable_reg = 0x1702c, 2238 .enable_mask = BIT(0), 2239 .hw.init = &(struct clk_init_data){ 2240 .name = "gcc_disp_xo_clk", 2241 .flags = CLK_IS_CRITICAL, 2242 .ops = &clk_branch2_ops, 2243 }, 2244 }, 2245 }; 2246 2247 static struct clk_branch gcc_gp1_clk = { 2248 .halt_reg = 0x4d000, 2249 .halt_check = BRANCH_HALT, 2250 .clkr = { 2251 .enable_reg = 0x4d000, 2252 .enable_mask = BIT(0), 2253 .hw.init = &(struct clk_init_data){ 2254 .name = "gcc_gp1_clk", 2255 .parent_hws = (const struct clk_hw *[]){ 2256 &gcc_gp1_clk_src.clkr.hw, 2257 }, 2258 .num_parents = 1, 2259 .flags = CLK_SET_RATE_PARENT, 2260 .ops = &clk_branch2_ops, 2261 }, 2262 }, 2263 }; 2264 2265 static struct clk_branch gcc_gp2_clk = { 2266 .halt_reg = 0x4e000, 2267 .halt_check = BRANCH_HALT, 2268 .clkr = { 2269 .enable_reg = 0x4e000, 2270 .enable_mask = BIT(0), 2271 .hw.init = &(struct clk_init_data){ 2272 .name = "gcc_gp2_clk", 2273 .parent_hws = (const struct clk_hw *[]){ 2274 &gcc_gp2_clk_src.clkr.hw, 2275 }, 2276 .num_parents = 1, 2277 .flags = CLK_SET_RATE_PARENT, 2278 .ops = &clk_branch2_ops, 2279 }, 2280 }, 2281 }; 2282 2283 static struct clk_branch gcc_gp3_clk = { 2284 .halt_reg = 0x4f000, 2285 .halt_check = BRANCH_HALT, 2286 .clkr = { 2287 .enable_reg = 0x4f000, 2288 .enable_mask = BIT(0), 2289 .hw.init = &(struct clk_init_data){ 2290 .name = "gcc_gp3_clk", 2291 .parent_hws = (const struct clk_hw *[]){ 2292 &gcc_gp3_clk_src.clkr.hw, 2293 }, 2294 .num_parents = 1, 2295 .flags = CLK_SET_RATE_PARENT, 2296 .ops = &clk_branch2_ops, 2297 }, 2298 }, 2299 }; 2300 2301 static struct clk_branch gcc_gpu_cfg_ahb_clk = { 2302 .halt_reg = 0x36004, 2303 .halt_check = BRANCH_HALT, 2304 .hwcg_reg = 0x36004, 2305 .hwcg_bit = 1, 2306 .clkr = { 2307 .enable_reg = 0x36004, 2308 .enable_mask = BIT(0), 2309 .hw.init = &(struct clk_init_data){ 2310 .name = "gcc_gpu_cfg_ahb_clk", 2311 .flags = CLK_IS_CRITICAL, 2312 .ops = &clk_branch2_ops, 2313 }, 2314 }, 2315 }; 2316 2317 static struct clk_branch gcc_gpu_gpll0_clk_src = { 2318 .halt_check = BRANCH_HALT_DELAY, 2319 .clkr = { 2320 .enable_reg = 0x79004, 2321 .enable_mask = BIT(15), 2322 .hw.init = &(struct clk_init_data){ 2323 .name = "gcc_gpu_gpll0_clk_src", 2324 .parent_hws = (const struct clk_hw *[]){ 2325 &gpll0.clkr.hw, 2326 }, 2327 .num_parents = 1, 2328 .flags = CLK_SET_RATE_PARENT, 2329 .ops = &clk_branch2_ops, 2330 }, 2331 }, 2332 }; 2333 2334 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 2335 .halt_check = BRANCH_HALT_DELAY, 2336 .clkr = { 2337 .enable_reg = 0x79004, 2338 .enable_mask = BIT(16), 2339 .hw.init = &(struct clk_init_data){ 2340 .name = "gcc_gpu_gpll0_div_clk_src", 2341 .parent_hws = (const struct clk_hw *[]){ 2342 &gpll0_out_aux2.clkr.hw, 2343 }, 2344 .num_parents = 1, 2345 .flags = CLK_SET_RATE_PARENT, 2346 .ops = &clk_branch2_ops, 2347 }, 2348 }, 2349 }; 2350 2351 static struct clk_branch gcc_gpu_iref_clk = { 2352 .halt_reg = 0x36100, 2353 .halt_check = BRANCH_HALT_DELAY, 2354 .clkr = { 2355 .enable_reg = 0x36100, 2356 .enable_mask = BIT(0), 2357 .hw.init = &(struct clk_init_data){ 2358 .name = "gcc_gpu_iref_clk", 2359 .ops = &clk_branch2_ops, 2360 }, 2361 }, 2362 }; 2363 2364 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 2365 .halt_reg = 0x3600c, 2366 .halt_check = BRANCH_VOTED, 2367 .hwcg_reg = 0x3600c, 2368 .hwcg_bit = 1, 2369 .clkr = { 2370 .enable_reg = 0x3600c, 2371 .enable_mask = BIT(0), 2372 .hw.init = &(struct clk_init_data){ 2373 .name = "gcc_gpu_memnoc_gfx_clk", 2374 .ops = &clk_branch2_ops, 2375 }, 2376 }, 2377 }; 2378 2379 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2380 .halt_reg = 0x36018, 2381 .halt_check = BRANCH_HALT, 2382 .clkr = { 2383 .enable_reg = 0x36018, 2384 .enable_mask = BIT(0), 2385 .hw.init = &(struct clk_init_data){ 2386 .name = "gcc_gpu_snoc_dvm_gfx_clk", 2387 .ops = &clk_branch2_ops, 2388 }, 2389 }, 2390 }; 2391 2392 static struct clk_branch gcc_gpu_throttle_core_clk = { 2393 .halt_reg = 0x36048, 2394 .halt_check = BRANCH_HALT_VOTED, 2395 .hwcg_reg = 0x36048, 2396 .hwcg_bit = 1, 2397 .clkr = { 2398 .enable_reg = 0x79004, 2399 .enable_mask = BIT(31), 2400 .hw.init = &(struct clk_init_data){ 2401 .name = "gcc_gpu_throttle_core_clk", 2402 .ops = &clk_branch2_ops, 2403 }, 2404 }, 2405 }; 2406 2407 static struct clk_branch gcc_pdm2_clk = { 2408 .halt_reg = 0x2000c, 2409 .halt_check = BRANCH_HALT, 2410 .clkr = { 2411 .enable_reg = 0x2000c, 2412 .enable_mask = BIT(0), 2413 .hw.init = &(struct clk_init_data){ 2414 .name = "gcc_pdm2_clk", 2415 .parent_hws = (const struct clk_hw *[]){ 2416 &gcc_pdm2_clk_src.clkr.hw, 2417 }, 2418 .num_parents = 1, 2419 .flags = CLK_SET_RATE_PARENT, 2420 .ops = &clk_branch2_ops, 2421 }, 2422 }, 2423 }; 2424 2425 static struct clk_branch gcc_pdm_ahb_clk = { 2426 .halt_reg = 0x20004, 2427 .halt_check = BRANCH_HALT, 2428 .hwcg_reg = 0x20004, 2429 .hwcg_bit = 1, 2430 .clkr = { 2431 .enable_reg = 0x20004, 2432 .enable_mask = BIT(0), 2433 .hw.init = &(struct clk_init_data){ 2434 .name = "gcc_pdm_ahb_clk", 2435 .ops = &clk_branch2_ops, 2436 }, 2437 }, 2438 }; 2439 2440 static struct clk_branch gcc_pdm_xo4_clk = { 2441 .halt_reg = 0x20008, 2442 .halt_check = BRANCH_HALT, 2443 .clkr = { 2444 .enable_reg = 0x20008, 2445 .enable_mask = BIT(0), 2446 .hw.init = &(struct clk_init_data){ 2447 .name = "gcc_pdm_xo4_clk", 2448 .ops = &clk_branch2_ops, 2449 }, 2450 }, 2451 }; 2452 2453 static struct clk_branch gcc_prng_ahb_clk = { 2454 .halt_reg = 0x21004, 2455 .halt_check = BRANCH_HALT_VOTED, 2456 .hwcg_reg = 0x21004, 2457 .hwcg_bit = 1, 2458 .clkr = { 2459 .enable_reg = 0x79004, 2460 .enable_mask = BIT(13), 2461 .hw.init = &(struct clk_init_data){ 2462 .name = "gcc_prng_ahb_clk", 2463 .ops = &clk_branch2_ops, 2464 }, 2465 }, 2466 }; 2467 2468 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2469 .halt_reg = 0x17014, 2470 .halt_check = BRANCH_HALT_VOTED, 2471 .hwcg_reg = 0x17014, 2472 .hwcg_bit = 1, 2473 .clkr = { 2474 .enable_reg = 0x7900c, 2475 .enable_mask = BIT(0), 2476 .hw.init = &(struct clk_init_data){ 2477 .name = "gcc_qmip_camera_nrt_ahb_clk", 2478 .ops = &clk_branch2_ops, 2479 }, 2480 }, 2481 }; 2482 2483 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2484 .halt_reg = 0x17060, 2485 .halt_check = BRANCH_HALT_VOTED, 2486 .hwcg_reg = 0x17060, 2487 .hwcg_bit = 1, 2488 .clkr = { 2489 .enable_reg = 0x7900c, 2490 .enable_mask = BIT(2), 2491 .hw.init = &(struct clk_init_data){ 2492 .name = "gcc_qmip_camera_rt_ahb_clk", 2493 .ops = &clk_branch2_ops, 2494 }, 2495 }, 2496 }; 2497 2498 static struct clk_branch gcc_qmip_disp_ahb_clk = { 2499 .halt_reg = 0x17018, 2500 .halt_check = BRANCH_HALT_VOTED, 2501 .hwcg_reg = 0x17018, 2502 .hwcg_bit = 1, 2503 .clkr = { 2504 .enable_reg = 0x7900c, 2505 .enable_mask = BIT(1), 2506 .hw.init = &(struct clk_init_data){ 2507 .name = "gcc_qmip_disp_ahb_clk", 2508 .ops = &clk_branch2_ops, 2509 }, 2510 }, 2511 }; 2512 2513 static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = { 2514 .halt_reg = 0x36040, 2515 .halt_check = BRANCH_HALT_VOTED, 2516 .hwcg_reg = 0x36040, 2517 .hwcg_bit = 1, 2518 .clkr = { 2519 .enable_reg = 0x7900c, 2520 .enable_mask = BIT(4), 2521 .hw.init = &(struct clk_init_data){ 2522 .name = "gcc_qmip_gpu_cfg_ahb_clk", 2523 .ops = &clk_branch2_ops, 2524 }, 2525 }, 2526 }; 2527 2528 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2529 .halt_reg = 0x17010, 2530 .halt_check = BRANCH_HALT_VOTED, 2531 .hwcg_reg = 0x17010, 2532 .hwcg_bit = 1, 2533 .clkr = { 2534 .enable_reg = 0x79004, 2535 .enable_mask = BIT(25), 2536 .hw.init = &(struct clk_init_data){ 2537 .name = "gcc_qmip_video_vcodec_ahb_clk", 2538 .ops = &clk_branch2_ops, 2539 }, 2540 }, 2541 }; 2542 2543 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2544 .halt_reg = 0x1f014, 2545 .halt_check = BRANCH_HALT_VOTED, 2546 .clkr = { 2547 .enable_reg = 0x7900c, 2548 .enable_mask = BIT(9), 2549 .hw.init = &(struct clk_init_data){ 2550 .name = "gcc_qupv3_wrap0_core_2x_clk", 2551 .ops = &clk_branch2_ops, 2552 }, 2553 }, 2554 }; 2555 2556 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2557 .halt_reg = 0x1f00c, 2558 .halt_check = BRANCH_HALT_VOTED, 2559 .clkr = { 2560 .enable_reg = 0x7900c, 2561 .enable_mask = BIT(8), 2562 .hw.init = &(struct clk_init_data){ 2563 .name = "gcc_qupv3_wrap0_core_clk", 2564 .ops = &clk_branch2_ops, 2565 }, 2566 }, 2567 }; 2568 2569 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2570 .halt_reg = 0x1f144, 2571 .halt_check = BRANCH_HALT_VOTED, 2572 .clkr = { 2573 .enable_reg = 0x7900c, 2574 .enable_mask = BIT(10), 2575 .hw.init = &(struct clk_init_data){ 2576 .name = "gcc_qupv3_wrap0_s0_clk", 2577 .parent_hws = (const struct clk_hw *[]){ 2578 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 2579 }, 2580 .num_parents = 1, 2581 .flags = CLK_SET_RATE_PARENT, 2582 .ops = &clk_branch2_ops, 2583 }, 2584 }, 2585 }; 2586 2587 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2588 .halt_reg = 0x1f274, 2589 .halt_check = BRANCH_HALT_VOTED, 2590 .clkr = { 2591 .enable_reg = 0x7900c, 2592 .enable_mask = BIT(11), 2593 .hw.init = &(struct clk_init_data){ 2594 .name = "gcc_qupv3_wrap0_s1_clk", 2595 .parent_hws = (const struct clk_hw *[]){ 2596 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 2597 }, 2598 .num_parents = 1, 2599 .flags = CLK_SET_RATE_PARENT, 2600 .ops = &clk_branch2_ops, 2601 }, 2602 }, 2603 }; 2604 2605 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2606 .halt_reg = 0x1f3a4, 2607 .halt_check = BRANCH_HALT_VOTED, 2608 .clkr = { 2609 .enable_reg = 0x7900c, 2610 .enable_mask = BIT(12), 2611 .hw.init = &(struct clk_init_data){ 2612 .name = "gcc_qupv3_wrap0_s2_clk", 2613 .parent_hws = (const struct clk_hw *[]){ 2614 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2615 }, 2616 .num_parents = 1, 2617 .flags = CLK_SET_RATE_PARENT, 2618 .ops = &clk_branch2_ops, 2619 }, 2620 }, 2621 }; 2622 2623 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2624 .halt_reg = 0x1f4d4, 2625 .halt_check = BRANCH_HALT_VOTED, 2626 .clkr = { 2627 .enable_reg = 0x7900c, 2628 .enable_mask = BIT(13), 2629 .hw.init = &(struct clk_init_data){ 2630 .name = "gcc_qupv3_wrap0_s3_clk", 2631 .parent_hws = (const struct clk_hw *[]){ 2632 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2633 }, 2634 .num_parents = 1, 2635 .flags = CLK_SET_RATE_PARENT, 2636 .ops = &clk_branch2_ops, 2637 }, 2638 }, 2639 }; 2640 2641 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2642 .halt_reg = 0x1f604, 2643 .halt_check = BRANCH_HALT_VOTED, 2644 .clkr = { 2645 .enable_reg = 0x7900c, 2646 .enable_mask = BIT(14), 2647 .hw.init = &(struct clk_init_data){ 2648 .name = "gcc_qupv3_wrap0_s4_clk", 2649 .parent_hws = (const struct clk_hw *[]){ 2650 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2651 }, 2652 .num_parents = 1, 2653 .flags = CLK_SET_RATE_PARENT, 2654 .ops = &clk_branch2_ops, 2655 }, 2656 }, 2657 }; 2658 2659 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2660 .halt_reg = 0x1f734, 2661 .halt_check = BRANCH_HALT_VOTED, 2662 .clkr = { 2663 .enable_reg = 0x7900c, 2664 .enable_mask = BIT(15), 2665 .hw.init = &(struct clk_init_data){ 2666 .name = "gcc_qupv3_wrap0_s5_clk", 2667 .parent_hws = (const struct clk_hw *[]){ 2668 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2669 }, 2670 .num_parents = 1, 2671 .flags = CLK_SET_RATE_PARENT, 2672 .ops = &clk_branch2_ops, 2673 }, 2674 }, 2675 }; 2676 2677 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2678 .halt_reg = 0x1f004, 2679 .halt_check = BRANCH_HALT_VOTED, 2680 .hwcg_reg = 0x1f004, 2681 .hwcg_bit = 1, 2682 .clkr = { 2683 .enable_reg = 0x7900c, 2684 .enable_mask = BIT(6), 2685 .hw.init = &(struct clk_init_data){ 2686 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2687 .ops = &clk_branch2_ops, 2688 }, 2689 }, 2690 }; 2691 2692 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2693 .halt_reg = 0x1f008, 2694 .halt_check = BRANCH_HALT_VOTED, 2695 .hwcg_reg = 0x1f008, 2696 .hwcg_bit = 1, 2697 .clkr = { 2698 .enable_reg = 0x7900c, 2699 .enable_mask = BIT(7), 2700 .hw.init = &(struct clk_init_data){ 2701 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2702 .ops = &clk_branch2_ops, 2703 }, 2704 }, 2705 }; 2706 2707 static struct clk_branch gcc_sdcc1_ahb_clk = { 2708 .halt_reg = 0x38008, 2709 .halt_check = BRANCH_HALT, 2710 .clkr = { 2711 .enable_reg = 0x38008, 2712 .enable_mask = BIT(0), 2713 .hw.init = &(struct clk_init_data){ 2714 .name = "gcc_sdcc1_ahb_clk", 2715 .ops = &clk_branch2_ops, 2716 }, 2717 }, 2718 }; 2719 2720 static struct clk_branch gcc_sdcc1_apps_clk = { 2721 .halt_reg = 0x38004, 2722 .halt_check = BRANCH_HALT, 2723 .clkr = { 2724 .enable_reg = 0x38004, 2725 .enable_mask = BIT(0), 2726 .hw.init = &(struct clk_init_data){ 2727 .name = "gcc_sdcc1_apps_clk", 2728 .parent_hws = (const struct clk_hw *[]){ 2729 &gcc_sdcc1_apps_clk_src.clkr.hw, 2730 }, 2731 .num_parents = 1, 2732 .flags = CLK_SET_RATE_PARENT /* | CLK_ENABLE_HAND_OFF */, 2733 .ops = &clk_branch2_ops, 2734 }, 2735 }, 2736 }; 2737 2738 static struct clk_branch gcc_sdcc1_ice_core_clk = { 2739 .halt_reg = 0x3800c, 2740 .halt_check = BRANCH_HALT, 2741 .hwcg_reg = 0x3800c, 2742 .hwcg_bit = 1, 2743 .clkr = { 2744 .enable_reg = 0x3800c, 2745 .enable_mask = BIT(0), 2746 .hw.init = &(struct clk_init_data){ 2747 .name = "gcc_sdcc1_ice_core_clk", 2748 .parent_hws = (const struct clk_hw *[]){ 2749 &gcc_sdcc1_ice_core_clk_src.clkr.hw, 2750 }, 2751 .num_parents = 1, 2752 .flags = CLK_SET_RATE_PARENT, 2753 .ops = &clk_branch2_ops, 2754 }, 2755 }, 2756 }; 2757 2758 static struct clk_branch gcc_sdcc2_ahb_clk = { 2759 .halt_reg = 0x1e008, 2760 .halt_check = BRANCH_HALT, 2761 .clkr = { 2762 .enable_reg = 0x1e008, 2763 .enable_mask = BIT(0), 2764 .hw.init = &(struct clk_init_data){ 2765 .name = "gcc_sdcc2_ahb_clk", 2766 .ops = &clk_branch2_ops, 2767 }, 2768 }, 2769 }; 2770 2771 static struct clk_branch gcc_sdcc2_apps_clk = { 2772 .halt_reg = 0x1e004, 2773 .halt_check = BRANCH_HALT, 2774 .clkr = { 2775 .enable_reg = 0x1e004, 2776 .enable_mask = BIT(0), 2777 .hw.init = &(struct clk_init_data){ 2778 .name = "gcc_sdcc2_apps_clk", 2779 .parent_hws = (const struct clk_hw *[]){ 2780 &gcc_sdcc2_apps_clk_src.clkr.hw, 2781 }, 2782 .num_parents = 1, 2783 .flags = CLK_SET_RATE_PARENT, 2784 .ops = &clk_branch2_ops, 2785 }, 2786 }, 2787 }; 2788 2789 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 2790 .halt_reg = 0x2b06c, 2791 .halt_check = BRANCH_HALT_VOTED, 2792 .hwcg_reg = 0x2b06c, 2793 .hwcg_bit = 1, 2794 .clkr = { 2795 .enable_reg = 0x79004, 2796 .enable_mask = BIT(0), 2797 .hw.init = &(struct clk_init_data){ 2798 .name = "gcc_sys_noc_cpuss_ahb_clk", 2799 .flags = CLK_IS_CRITICAL, 2800 .ops = &clk_branch2_ops, 2801 }, 2802 }, 2803 }; 2804 2805 static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { 2806 .halt_reg = 0x45098, 2807 .halt_check = BRANCH_HALT, 2808 .clkr = { 2809 .enable_reg = 0x45098, 2810 .enable_mask = BIT(0), 2811 .hw.init = &(struct clk_init_data){ 2812 .name = "gcc_sys_noc_ufs_phy_axi_clk", 2813 .parent_hws = (const struct clk_hw *[]){ 2814 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2815 }, 2816 .num_parents = 1, 2817 .flags = CLK_SET_RATE_PARENT, 2818 .ops = &clk_branch2_ops, 2819 }, 2820 }, 2821 }; 2822 2823 static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { 2824 .halt_reg = 0x1a080, 2825 .halt_check = BRANCH_HALT, 2826 .hwcg_reg = 0x1a080, 2827 .hwcg_bit = 1, 2828 .clkr = { 2829 .enable_reg = 0x1a080, 2830 .enable_mask = BIT(0), 2831 .hw.init = &(struct clk_init_data){ 2832 .name = "gcc_sys_noc_usb3_prim_axi_clk", 2833 .parent_hws = (const struct clk_hw *[]){ 2834 &gcc_usb30_prim_master_clk_src.clkr.hw, 2835 }, 2836 .num_parents = 1, 2837 .flags = CLK_SET_RATE_PARENT, 2838 .ops = &clk_branch2_ops, 2839 }, 2840 }, 2841 }; 2842 2843 static struct clk_branch gcc_ufs_clkref_clk = { 2844 .halt_reg = 0x8c000, 2845 .halt_check = BRANCH_HALT, 2846 .clkr = { 2847 .enable_reg = 0x8c000, 2848 .enable_mask = BIT(0), 2849 .hw.init = &(struct clk_init_data){ 2850 .name = "gcc_ufs_clkref_clk", 2851 .ops = &clk_branch2_ops, 2852 }, 2853 }, 2854 }; 2855 2856 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2857 .halt_reg = 0x45014, 2858 .halt_check = BRANCH_HALT, 2859 .hwcg_reg = 0x45014, 2860 .hwcg_bit = 1, 2861 .clkr = { 2862 .enable_reg = 0x45014, 2863 .enable_mask = BIT(0), 2864 .hw.init = &(struct clk_init_data){ 2865 .name = "gcc_ufs_phy_ahb_clk", 2866 .ops = &clk_branch2_ops, 2867 }, 2868 }, 2869 }; 2870 2871 static struct clk_branch gcc_ufs_phy_axi_clk = { 2872 .halt_reg = 0x45010, 2873 .halt_check = BRANCH_HALT, 2874 .hwcg_reg = 0x45010, 2875 .hwcg_bit = 1, 2876 .clkr = { 2877 .enable_reg = 0x45010, 2878 .enable_mask = BIT(0), 2879 .hw.init = &(struct clk_init_data){ 2880 .name = "gcc_ufs_phy_axi_clk", 2881 .parent_hws = (const struct clk_hw *[]){ 2882 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2883 }, 2884 .num_parents = 1, 2885 .flags = CLK_SET_RATE_PARENT, 2886 .ops = &clk_branch2_ops, 2887 }, 2888 }, 2889 }; 2890 2891 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2892 .halt_reg = 0x45044, 2893 .halt_check = BRANCH_HALT, 2894 .hwcg_reg = 0x45044, 2895 .hwcg_bit = 1, 2896 .clkr = { 2897 .enable_reg = 0x45044, 2898 .enable_mask = BIT(0), 2899 .hw.init = &(struct clk_init_data){ 2900 .name = "gcc_ufs_phy_ice_core_clk", 2901 .parent_hws = (const struct clk_hw *[]){ 2902 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2903 }, 2904 .num_parents = 1, 2905 .flags = CLK_SET_RATE_PARENT, 2906 .ops = &clk_branch2_ops, 2907 }, 2908 }, 2909 }; 2910 2911 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2912 .halt_reg = 0x45078, 2913 .halt_check = BRANCH_HALT, 2914 .hwcg_reg = 0x45078, 2915 .hwcg_bit = 1, 2916 .clkr = { 2917 .enable_reg = 0x45078, 2918 .enable_mask = BIT(0), 2919 .hw.init = &(struct clk_init_data){ 2920 .name = "gcc_ufs_phy_phy_aux_clk", 2921 .parent_hws = (const struct clk_hw *[]){ 2922 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2923 }, 2924 .num_parents = 1, 2925 .flags = CLK_SET_RATE_PARENT, 2926 .ops = &clk_branch2_ops, 2927 }, 2928 }, 2929 }; 2930 2931 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2932 .halt_reg = 0x4501c, 2933 .halt_check = BRANCH_HALT_SKIP, 2934 .clkr = { 2935 .enable_reg = 0x4501c, 2936 .enable_mask = BIT(0), 2937 .hw.init = &(struct clk_init_data){ 2938 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2939 .ops = &clk_branch2_ops, 2940 }, 2941 }, 2942 }; 2943 2944 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2945 .halt_reg = 0x45018, 2946 .halt_check = BRANCH_HALT_SKIP, 2947 .clkr = { 2948 .enable_reg = 0x45018, 2949 .enable_mask = BIT(0), 2950 .hw.init = &(struct clk_init_data){ 2951 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2952 .ops = &clk_branch2_ops, 2953 }, 2954 }, 2955 }; 2956 2957 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2958 .halt_reg = 0x45040, 2959 .halt_check = BRANCH_HALT, 2960 .hwcg_reg = 0x45040, 2961 .hwcg_bit = 1, 2962 .clkr = { 2963 .enable_reg = 0x45040, 2964 .enable_mask = BIT(0), 2965 .hw.init = &(struct clk_init_data){ 2966 .name = "gcc_ufs_phy_unipro_core_clk", 2967 .parent_hws = (const struct clk_hw *[]){ 2968 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2969 }, 2970 .num_parents = 1, 2971 .flags = CLK_SET_RATE_PARENT, 2972 .ops = &clk_branch2_ops, 2973 }, 2974 }, 2975 }; 2976 2977 static struct clk_branch gcc_usb30_prim_master_clk = { 2978 .halt_reg = 0x1a010, 2979 .halt_check = BRANCH_HALT, 2980 .clkr = { 2981 .enable_reg = 0x1a010, 2982 .enable_mask = BIT(0), 2983 .hw.init = &(struct clk_init_data){ 2984 .name = "gcc_usb30_prim_master_clk", 2985 .parent_hws = (const struct clk_hw *[]){ 2986 &gcc_usb30_prim_master_clk_src.clkr.hw, 2987 }, 2988 .num_parents = 1, 2989 .flags = CLK_SET_RATE_PARENT, 2990 .ops = &clk_branch2_ops, 2991 }, 2992 }, 2993 }; 2994 2995 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2996 .halt_reg = 0x1a018, 2997 .halt_check = BRANCH_HALT, 2998 .clkr = { 2999 .enable_reg = 0x1a018, 3000 .enable_mask = BIT(0), 3001 .hw.init = &(struct clk_init_data){ 3002 .name = "gcc_usb30_prim_mock_utmi_clk", 3003 .parent_hws = (const struct clk_hw *[]){ 3004 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 3005 }, 3006 .num_parents = 1, 3007 .flags = CLK_SET_RATE_PARENT, 3008 .ops = &clk_branch2_ops, 3009 }, 3010 }, 3011 }; 3012 3013 static struct clk_branch gcc_usb30_prim_sleep_clk = { 3014 .halt_reg = 0x1a014, 3015 .halt_check = BRANCH_HALT, 3016 .clkr = { 3017 .enable_reg = 0x1a014, 3018 .enable_mask = BIT(0), 3019 .hw.init = &(struct clk_init_data){ 3020 .name = "gcc_usb30_prim_sleep_clk", 3021 .ops = &clk_branch2_ops, 3022 }, 3023 }, 3024 }; 3025 3026 static struct clk_branch gcc_usb3_prim_clkref_clk = { 3027 .halt_reg = 0x9f000, 3028 .halt_check = BRANCH_HALT, 3029 .clkr = { 3030 .enable_reg = 0x9f000, 3031 .enable_mask = BIT(0), 3032 .hw.init = &(struct clk_init_data){ 3033 .name = "gcc_usb3_prim_clkref_clk", 3034 .ops = &clk_branch2_ops, 3035 }, 3036 }, 3037 }; 3038 3039 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3040 .halt_reg = 0x1a054, 3041 .halt_check = BRANCH_HALT, 3042 .clkr = { 3043 .enable_reg = 0x1a054, 3044 .enable_mask = BIT(0), 3045 .hw.init = &(struct clk_init_data){ 3046 .name = "gcc_usb3_prim_phy_com_aux_clk", 3047 .parent_hws = (const struct clk_hw *[]){ 3048 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3049 }, 3050 .num_parents = 1, 3051 .flags = CLK_SET_RATE_PARENT, 3052 .ops = &clk_branch2_ops, 3053 }, 3054 }, 3055 }; 3056 3057 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3058 .halt_reg = 0x1a058, 3059 .halt_check = BRANCH_HALT_SKIP, 3060 .hwcg_reg = 0x1a058, 3061 .hwcg_bit = 1, 3062 .clkr = { 3063 .enable_reg = 0x1a058, 3064 .enable_mask = BIT(0), 3065 .hw.init = &(struct clk_init_data){ 3066 .name = "gcc_usb3_prim_phy_pipe_clk", 3067 .ops = &clk_branch2_ops, 3068 }, 3069 }, 3070 }; 3071 3072 static struct clk_branch gcc_vcodec0_axi_clk = { 3073 .halt_reg = 0x6e008, 3074 .halt_check = BRANCH_HALT, 3075 .clkr = { 3076 .enable_reg = 0x6e008, 3077 .enable_mask = BIT(0), 3078 .hw.init = &(struct clk_init_data){ 3079 .name = "gcc_vcodec0_axi_clk", 3080 .ops = &clk_branch2_ops, 3081 }, 3082 }, 3083 }; 3084 3085 static struct clk_branch gcc_venus_ahb_clk = { 3086 .halt_reg = 0x6e010, 3087 .halt_check = BRANCH_HALT, 3088 .clkr = { 3089 .enable_reg = 0x6e010, 3090 .enable_mask = BIT(0), 3091 .hw.init = &(struct clk_init_data){ 3092 .name = "gcc_venus_ahb_clk", 3093 .ops = &clk_branch2_ops, 3094 }, 3095 }, 3096 }; 3097 3098 static struct clk_branch gcc_venus_ctl_axi_clk = { 3099 .halt_reg = 0x6e004, 3100 .halt_check = BRANCH_HALT, 3101 .clkr = { 3102 .enable_reg = 0x6e004, 3103 .enable_mask = BIT(0), 3104 .hw.init = &(struct clk_init_data){ 3105 .name = "gcc_venus_ctl_axi_clk", 3106 .ops = &clk_branch2_ops, 3107 }, 3108 }, 3109 }; 3110 3111 static struct clk_branch gcc_video_ahb_clk = { 3112 .halt_reg = 0x17004, 3113 .halt_check = BRANCH_HALT, 3114 .hwcg_reg = 0x17004, 3115 .hwcg_bit = 1, 3116 .clkr = { 3117 .enable_reg = 0x17004, 3118 .enable_mask = BIT(0), 3119 .hw.init = &(struct clk_init_data){ 3120 .name = "gcc_video_ahb_clk", 3121 .ops = &clk_branch2_ops, 3122 }, 3123 }, 3124 }; 3125 3126 static struct clk_branch gcc_video_axi0_clk = { 3127 .halt_reg = 0x1701c, 3128 .halt_check = BRANCH_HALT, 3129 .hwcg_reg = 0x1701c, 3130 .hwcg_bit = 1, 3131 .clkr = { 3132 .enable_reg = 0x1701c, 3133 .enable_mask = BIT(0), 3134 .hw.init = &(struct clk_init_data){ 3135 .name = "gcc_video_axi0_clk", 3136 .ops = &clk_branch2_ops, 3137 }, 3138 }, 3139 }; 3140 3141 static struct clk_branch gcc_video_throttle_core_clk = { 3142 .halt_reg = 0x17068, 3143 .halt_check = BRANCH_HALT_VOTED, 3144 .hwcg_reg = 0x17068, 3145 .hwcg_bit = 1, 3146 .clkr = { 3147 .enable_reg = 0x79004, 3148 .enable_mask = BIT(28), 3149 .hw.init = &(struct clk_init_data){ 3150 .name = "gcc_video_throttle_core_clk", 3151 .ops = &clk_branch2_ops, 3152 }, 3153 }, 3154 }; 3155 3156 static struct clk_branch gcc_video_vcodec0_sys_clk = { 3157 .halt_reg = 0x580a4, 3158 .halt_check = BRANCH_HALT_DELAY, 3159 .hwcg_reg = 0x580a4, 3160 .hwcg_bit = 1, 3161 .clkr = { 3162 .enable_reg = 0x580a4, 3163 .enable_mask = BIT(0), 3164 .hw.init = &(struct clk_init_data){ 3165 .name = "gcc_video_vcodec0_sys_clk", 3166 .parent_hws = (const struct clk_hw *[]){ 3167 &gcc_video_venus_clk_src.clkr.hw, 3168 }, 3169 .num_parents = 1, 3170 .flags = CLK_SET_RATE_PARENT, 3171 .ops = &clk_branch2_ops, 3172 }, 3173 }, 3174 }; 3175 3176 static struct clk_branch gcc_video_venus_ctl_clk = { 3177 .halt_reg = 0x5808c, 3178 .halt_check = BRANCH_HALT, 3179 .clkr = { 3180 .enable_reg = 0x5808c, 3181 .enable_mask = BIT(0), 3182 .hw.init = &(struct clk_init_data){ 3183 .name = "gcc_video_venus_ctl_clk", 3184 .parent_hws = (const struct clk_hw *[]){ 3185 &gcc_video_venus_clk_src.clkr.hw, 3186 }, 3187 .num_parents = 1, 3188 .flags = CLK_SET_RATE_PARENT, 3189 .ops = &clk_branch2_ops, 3190 }, 3191 }, 3192 }; 3193 3194 static struct clk_branch gcc_video_xo_clk = { 3195 .halt_reg = 0x17024, 3196 .halt_check = BRANCH_HALT, 3197 .clkr = { 3198 .enable_reg = 0x17024, 3199 .enable_mask = BIT(0), 3200 .hw.init = &(struct clk_init_data){ 3201 .name = "gcc_video_xo_clk", 3202 .ops = &clk_branch2_ops, 3203 }, 3204 }, 3205 }; 3206 3207 static struct gdsc gcc_camss_top_gdsc = { 3208 .gdscr = 0x58004, 3209 .pd = { 3210 .name = "gcc_camss_top", 3211 }, 3212 .pwrsts = PWRSTS_OFF_ON, 3213 }; 3214 3215 static struct gdsc gcc_ufs_phy_gdsc = { 3216 .gdscr = 0x45004, 3217 .pd = { 3218 .name = "gcc_ufs_phy", 3219 }, 3220 .pwrsts = PWRSTS_OFF_ON, 3221 }; 3222 3223 static struct gdsc gcc_usb30_prim_gdsc = { 3224 .gdscr = 0x1a004, 3225 .pd = { 3226 .name = "gcc_usb30_prim", 3227 }, 3228 .pwrsts = PWRSTS_OFF_ON, 3229 }; 3230 3231 static struct gdsc gcc_vcodec0_gdsc = { 3232 .gdscr = 0x58098, 3233 .pd = { 3234 .name = "gcc_vcodec0", 3235 }, 3236 .pwrsts = PWRSTS_OFF_ON, 3237 }; 3238 3239 static struct gdsc gcc_venus_gdsc = { 3240 .gdscr = 0x5807c, 3241 .pd = { 3242 .name = "gcc_venus", 3243 }, 3244 .pwrsts = PWRSTS_OFF_ON, 3245 }; 3246 3247 static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = { 3248 .gdscr = 0x7d060, 3249 .pd = { 3250 .name = "hlos1_vote_turing_mmu_tbu1", 3251 }, 3252 .pwrsts = PWRSTS_OFF_ON, 3253 .flags = VOTABLE, 3254 }; 3255 3256 static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { 3257 .gdscr = 0x7d07c, 3258 .pd = { 3259 .name = "hlos1_vote_turing_mmu_tbu0", 3260 }, 3261 .pwrsts = PWRSTS_OFF_ON, 3262 .flags = VOTABLE, 3263 }; 3264 3265 static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = { 3266 .gdscr = 0x7d074, 3267 .pd = { 3268 .name = "hlos1_vote_mm_snoc_mmu_tbu_rt", 3269 }, 3270 .pwrsts = PWRSTS_OFF_ON, 3271 .flags = VOTABLE, 3272 }; 3273 3274 static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = { 3275 .gdscr = 0x7d078, 3276 .pd = { 3277 .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt", 3278 }, 3279 .pwrsts = PWRSTS_OFF_ON, 3280 .flags = VOTABLE, 3281 }; 3282 3283 static struct clk_regmap *gcc_sm6115_clocks[] = { 3284 [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr, 3285 [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr, 3286 [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr, 3287 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3288 [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, 3289 [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, 3290 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 3291 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 3292 [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, 3293 [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, 3294 [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr, 3295 [GCC_CAMSS_CAMNOC_NTS_XO_CLK] = &gcc_camss_camnoc_nts_xo_clk.clkr, 3296 [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr, 3297 [GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr, 3298 [GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr, 3299 [GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr, 3300 [GCC_CAMSS_CPHY_2_CLK] = &gcc_camss_cphy_2_clk.clkr, 3301 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 3302 [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr, 3303 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, 3304 [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr, 3305 [GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr, 3306 [GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr, 3307 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 3308 [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr, 3309 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 3310 [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr, 3311 [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, 3312 [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr, 3313 [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr, 3314 [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr, 3315 [GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr, 3316 [GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr, 3317 [GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr, 3318 [GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr, 3319 [GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr, 3320 [GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr, 3321 [GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr, 3322 [GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr, 3323 [GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr, 3324 [GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr, 3325 [GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr, 3326 [GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr, 3327 [GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr, 3328 [GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr, 3329 [GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr, 3330 [GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr, 3331 [GCC_CAMSS_TFE_2_CLK] = &gcc_camss_tfe_2_clk.clkr, 3332 [GCC_CAMSS_TFE_2_CLK_SRC] = &gcc_camss_tfe_2_clk_src.clkr, 3333 [GCC_CAMSS_TFE_2_CPHY_RX_CLK] = &gcc_camss_tfe_2_cphy_rx_clk.clkr, 3334 [GCC_CAMSS_TFE_2_CSID_CLK] = &gcc_camss_tfe_2_csid_clk.clkr, 3335 [GCC_CAMSS_TFE_2_CSID_CLK_SRC] = &gcc_camss_tfe_2_csid_clk_src.clkr, 3336 [GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr, 3337 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 3338 [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, 3339 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3340 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, 3341 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, 3342 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 3343 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 3344 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3345 [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, 3346 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 3347 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3348 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3349 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3350 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3351 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3352 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3353 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 3354 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3355 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3356 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, 3357 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3358 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3359 [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, 3360 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3361 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3362 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3363 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3364 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3365 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3366 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3367 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3368 [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr, 3369 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3370 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 3371 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 3372 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3373 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3374 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3375 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3376 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3377 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3378 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3379 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3380 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3381 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3382 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3383 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3384 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3385 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3386 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3387 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3388 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 3389 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 3390 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 3391 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3392 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3393 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3394 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 3395 [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, 3396 [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, 3397 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, 3398 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3399 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3400 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3401 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3402 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3403 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3404 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3405 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3406 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3407 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3408 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 3409 &gcc_ufs_phy_unipro_core_clk_src.clkr, 3410 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3411 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3412 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3413 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 3414 &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3415 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = 3416 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3417 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3418 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 3419 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3420 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3421 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3422 [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr, 3423 [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr, 3424 [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr, 3425 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 3426 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3427 [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, 3428 [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr, 3429 [GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr, 3430 [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr, 3431 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 3432 [GPLL0] = &gpll0.clkr, 3433 [GPLL0_OUT_AUX2] = &gpll0_out_aux2.clkr, 3434 [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr, 3435 [GPLL10] = &gpll10.clkr, 3436 [GPLL10_OUT_MAIN] = &gpll10_out_main.clkr, 3437 [GPLL11] = &gpll11.clkr, 3438 [GPLL11_OUT_MAIN] = &gpll11_out_main.clkr, 3439 [GPLL3] = &gpll3.clkr, 3440 [GPLL4] = &gpll4.clkr, 3441 [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr, 3442 [GPLL6] = &gpll6.clkr, 3443 [GPLL6_OUT_MAIN] = &gpll6_out_main.clkr, 3444 [GPLL7] = &gpll7.clkr, 3445 [GPLL7_OUT_MAIN] = &gpll7_out_main.clkr, 3446 [GPLL8] = &gpll8.clkr, 3447 [GPLL8_OUT_MAIN] = &gpll8_out_main.clkr, 3448 [GPLL9] = &gpll9.clkr, 3449 [GPLL9_OUT_MAIN] = &gpll9_out_main.clkr, 3450 }; 3451 3452 static const struct qcom_reset_map gcc_sm6115_resets[] = { 3453 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, 3454 [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, 3455 [GCC_SDCC1_BCR] = { 0x38000 }, 3456 [GCC_SDCC2_BCR] = { 0x1e000 }, 3457 [GCC_UFS_PHY_BCR] = { 0x45000 }, 3458 [GCC_USB30_PRIM_BCR] = { 0x1a000 }, 3459 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, 3460 [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, 3461 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, 3462 [GCC_VCODEC0_BCR] = { 0x58094 }, 3463 [GCC_VENUS_BCR] = { 0x58078 }, 3464 [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 }, 3465 }; 3466 3467 static struct gdsc *gcc_sm6115_gdscs[] = { 3468 [GCC_CAMSS_TOP_GDSC] = &gcc_camss_top_gdsc, 3469 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, 3470 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 3471 [GCC_VCODEC0_GDSC] = &gcc_vcodec0_gdsc, 3472 [GCC_VENUS_GDSC] = &gcc_venus_gdsc, 3473 [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, 3474 [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc, 3475 [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc, 3476 [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc, 3477 }; 3478 3479 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3480 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3481 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3482 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3483 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3484 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3485 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3486 }; 3487 3488 static const struct regmap_config gcc_sm6115_regmap_config = { 3489 .reg_bits = 32, 3490 .reg_stride = 4, 3491 .val_bits = 32, 3492 .max_register = 0xc7000, 3493 .fast_io = true, 3494 }; 3495 3496 static const struct qcom_cc_desc gcc_sm6115_desc = { 3497 .config = &gcc_sm6115_regmap_config, 3498 .clks = gcc_sm6115_clocks, 3499 .num_clks = ARRAY_SIZE(gcc_sm6115_clocks), 3500 .resets = gcc_sm6115_resets, 3501 .num_resets = ARRAY_SIZE(gcc_sm6115_resets), 3502 .gdscs = gcc_sm6115_gdscs, 3503 .num_gdscs = ARRAY_SIZE(gcc_sm6115_gdscs), 3504 }; 3505 3506 static const struct of_device_id gcc_sm6115_match_table[] = { 3507 { .compatible = "qcom,gcc-sm6115" }, 3508 { } 3509 }; 3510 MODULE_DEVICE_TABLE(of, gcc_sm6115_match_table); 3511 3512 static int gcc_sm6115_probe(struct platform_device *pdev) 3513 { 3514 struct regmap *regmap; 3515 int ret; 3516 3517 regmap = qcom_cc_map(pdev, &gcc_sm6115_desc); 3518 if (IS_ERR(regmap)) 3519 return PTR_ERR(regmap); 3520 3521 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3522 ARRAY_SIZE(gcc_dfs_clocks)); 3523 if (ret) 3524 return ret; 3525 3526 clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config); 3527 clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config); 3528 clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config); 3529 clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config); 3530 3531 return qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap); 3532 } 3533 3534 static struct platform_driver gcc_sm6115_driver = { 3535 .probe = gcc_sm6115_probe, 3536 .driver = { 3537 .name = "gcc-sm6115", 3538 .of_match_table = gcc_sm6115_match_table, 3539 }, 3540 }; 3541 3542 static int __init gcc_sm6115_init(void) 3543 { 3544 return platform_driver_register(&gcc_sm6115_driver); 3545 } 3546 subsys_initcall(gcc_sm6115_init); 3547 3548 static void __exit gcc_sm6115_exit(void) 3549 { 3550 platform_driver_unregister(&gcc_sm6115_driver); 3551 } 3552 module_exit(gcc_sm6115_exit); 3553 3554 MODULE_DESCRIPTION("QTI GCC SM6115 and SM4250 Driver"); 3555 MODULE_LICENSE("GPL v2"); 3556 MODULE_ALIAS("platform:gcc-sm6115"); 3557