1cbe63bfdSIskren Chernev // SPDX-License-Identifier: GPL-2.0-only 2cbe63bfdSIskren Chernev /* 3cbe63bfdSIskren Chernev * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. 4cbe63bfdSIskren Chernev */ 5cbe63bfdSIskren Chernev 6cbe63bfdSIskren Chernev #include <linux/err.h> 7cbe63bfdSIskren Chernev #include <linux/kernel.h> 8cbe63bfdSIskren Chernev #include <linux/module.h> 9cbe63bfdSIskren Chernev #include <linux/of_device.h> 10cbe63bfdSIskren Chernev #include <linux/clk-provider.h> 11cbe63bfdSIskren Chernev #include <linux/regmap.h> 12cbe63bfdSIskren Chernev #include <linux/reset-controller.h> 13cbe63bfdSIskren Chernev 14cbe63bfdSIskren Chernev #include <dt-bindings/clock/qcom,gcc-sm6115.h> 15cbe63bfdSIskren Chernev 16cbe63bfdSIskren Chernev #include "clk-alpha-pll.h" 17cbe63bfdSIskren Chernev #include "clk-branch.h" 18cbe63bfdSIskren Chernev #include "clk-pll.h" 19cbe63bfdSIskren Chernev #include "clk-rcg.h" 20cbe63bfdSIskren Chernev #include "clk-regmap.h" 21cbe63bfdSIskren Chernev #include "clk-regmap-divider.h" 22cbe63bfdSIskren Chernev #include "common.h" 23cbe63bfdSIskren Chernev #include "gdsc.h" 24cbe63bfdSIskren Chernev #include "reset.h" 25cbe63bfdSIskren Chernev 26cbe63bfdSIskren Chernev enum { 27cbe63bfdSIskren Chernev P_BI_TCXO, 28cbe63bfdSIskren Chernev P_GPLL0_OUT_AUX2, 29cbe63bfdSIskren Chernev P_GPLL0_OUT_EARLY, 30cbe63bfdSIskren Chernev P_GPLL10_OUT_MAIN, 31cbe63bfdSIskren Chernev P_GPLL11_OUT_MAIN, 32cbe63bfdSIskren Chernev P_GPLL3_OUT_EARLY, 33cbe63bfdSIskren Chernev P_GPLL4_OUT_MAIN, 34cbe63bfdSIskren Chernev P_GPLL6_OUT_EARLY, 35cbe63bfdSIskren Chernev P_GPLL6_OUT_MAIN, 36cbe63bfdSIskren Chernev P_GPLL7_OUT_MAIN, 37cbe63bfdSIskren Chernev P_GPLL8_OUT_EARLY, 38cbe63bfdSIskren Chernev P_GPLL8_OUT_MAIN, 39cbe63bfdSIskren Chernev P_GPLL9_OUT_EARLY, 40cbe63bfdSIskren Chernev P_GPLL9_OUT_MAIN, 41cbe63bfdSIskren Chernev P_SLEEP_CLK, 42cbe63bfdSIskren Chernev }; 43cbe63bfdSIskren Chernev 44cbe63bfdSIskren Chernev static struct pll_vco default_vco[] = { 45cbe63bfdSIskren Chernev { 500000000, 1000000000, 2 }, 46cbe63bfdSIskren Chernev }; 47cbe63bfdSIskren Chernev 48cbe63bfdSIskren Chernev static struct pll_vco gpll9_vco[] = { 49cbe63bfdSIskren Chernev { 500000000, 1250000000, 0 }, 50cbe63bfdSIskren Chernev }; 51cbe63bfdSIskren Chernev 52cbe63bfdSIskren Chernev static struct pll_vco gpll10_vco[] = { 53cbe63bfdSIskren Chernev { 750000000, 1500000000, 1 }, 54cbe63bfdSIskren Chernev }; 55cbe63bfdSIskren Chernev 56cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll0 = { 57cbe63bfdSIskren Chernev .offset = 0x0, 58cbe63bfdSIskren Chernev .vco_table = default_vco, 59cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 609e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 61cbe63bfdSIskren Chernev .clkr = { 62cbe63bfdSIskren Chernev .enable_reg = 0x79000, 63cbe63bfdSIskren Chernev .enable_mask = BIT(0), 64cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 65cbe63bfdSIskren Chernev .name = "gpll0", 66cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 67cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 68cbe63bfdSIskren Chernev }, 69cbe63bfdSIskren Chernev .num_parents = 1, 70cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 71cbe63bfdSIskren Chernev }, 72cbe63bfdSIskren Chernev }, 73cbe63bfdSIskren Chernev }; 74cbe63bfdSIskren Chernev 75cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll0_out_aux2[] = { 76cbe63bfdSIskren Chernev { 0x1, 2 }, 77cbe63bfdSIskren Chernev { } 78cbe63bfdSIskren Chernev }; 79cbe63bfdSIskren Chernev 80cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll0_out_aux2 = { 81cbe63bfdSIskren Chernev .offset = 0x0, 82cbe63bfdSIskren Chernev .post_div_shift = 8, 83cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll0_out_aux2, 84cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2), 85cbe63bfdSIskren Chernev .width = 4, 869e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 87cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 88cbe63bfdSIskren Chernev .name = "gpll0_out_aux2", 89cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 90cbe63bfdSIskren Chernev .num_parents = 1, 91cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 92cbe63bfdSIskren Chernev }, 93cbe63bfdSIskren Chernev }; 94cbe63bfdSIskren Chernev 95cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll0_out_main[] = { 96cbe63bfdSIskren Chernev { 0x0, 1 }, 97cbe63bfdSIskren Chernev { } 98cbe63bfdSIskren Chernev }; 99cbe63bfdSIskren Chernev 100cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll0_out_main = { 101cbe63bfdSIskren Chernev .offset = 0x0, 102cbe63bfdSIskren Chernev .post_div_shift = 8, 103cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll0_out_main, 104cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_main), 105cbe63bfdSIskren Chernev .width = 4, 1069e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 107cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 108cbe63bfdSIskren Chernev .name = "gpll0_out_main", 109cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 110cbe63bfdSIskren Chernev .num_parents = 1, 111cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 112cbe63bfdSIskren Chernev }, 113cbe63bfdSIskren Chernev }; 114cbe63bfdSIskren Chernev 115cbe63bfdSIskren Chernev /* 1152MHz configuration */ 116cbe63bfdSIskren Chernev static const struct alpha_pll_config gpll10_config = { 117cbe63bfdSIskren Chernev .l = 0x3c, 118cbe63bfdSIskren Chernev .vco_val = 0x1 << 20, 119cbe63bfdSIskren Chernev .vco_mask = GENMASK(21, 20), 120cbe63bfdSIskren Chernev .main_output_mask = BIT(0), 121cbe63bfdSIskren Chernev .config_ctl_val = 0x4001055b, 122*e88c533dSKonrad Dybcio .test_ctl_hi1_val = 0x1, 123*e88c533dSKonrad Dybcio .test_ctl_hi_mask = 0x1, 124cbe63bfdSIskren Chernev }; 125cbe63bfdSIskren Chernev 126cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll10 = { 127cbe63bfdSIskren Chernev .offset = 0xa000, 128cbe63bfdSIskren Chernev .vco_table = gpll10_vco, 129cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(gpll10_vco), 1309e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 131cbe63bfdSIskren Chernev .clkr = { 132cbe63bfdSIskren Chernev .enable_reg = 0x79000, 133cbe63bfdSIskren Chernev .enable_mask = BIT(10), 134cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 135cbe63bfdSIskren Chernev .name = "gpll10", 136cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 137cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 138cbe63bfdSIskren Chernev }, 139cbe63bfdSIskren Chernev .num_parents = 1, 140cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 141cbe63bfdSIskren Chernev }, 142cbe63bfdSIskren Chernev }, 143cbe63bfdSIskren Chernev }; 144cbe63bfdSIskren Chernev 145cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll10_out_main[] = { 146cbe63bfdSIskren Chernev { 0x0, 1 }, 147cbe63bfdSIskren Chernev { } 148cbe63bfdSIskren Chernev }; 149cbe63bfdSIskren Chernev 150cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll10_out_main = { 151cbe63bfdSIskren Chernev .offset = 0xa000, 152cbe63bfdSIskren Chernev .post_div_shift = 8, 153cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll10_out_main, 154cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll10_out_main), 155cbe63bfdSIskren Chernev .width = 4, 1569e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 157cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 158cbe63bfdSIskren Chernev .name = "gpll10_out_main", 159cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll10.clkr.hw }, 160cbe63bfdSIskren Chernev .num_parents = 1, 161cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 162cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ops, 163cbe63bfdSIskren Chernev }, 164cbe63bfdSIskren Chernev }; 165cbe63bfdSIskren Chernev 166cbe63bfdSIskren Chernev /* 600MHz configuration */ 167cbe63bfdSIskren Chernev static const struct alpha_pll_config gpll11_config = { 168cbe63bfdSIskren Chernev .l = 0x1F, 169cbe63bfdSIskren Chernev .alpha = 0x0, 170cbe63bfdSIskren Chernev .alpha_hi = 0x40, 171cbe63bfdSIskren Chernev .alpha_en_mask = BIT(24), 172cbe63bfdSIskren Chernev .vco_val = 0x2 << 20, 173cbe63bfdSIskren Chernev .vco_mask = GENMASK(21, 20), 174cbe63bfdSIskren Chernev .config_ctl_val = 0x4001055b, 175*e88c533dSKonrad Dybcio .test_ctl_hi1_val = 0x1, 176*e88c533dSKonrad Dybcio .test_ctl_hi_mask = 0x1, 177cbe63bfdSIskren Chernev }; 178cbe63bfdSIskren Chernev 179cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll11 = { 180cbe63bfdSIskren Chernev .offset = 0xb000, 181cbe63bfdSIskren Chernev .vco_table = default_vco, 182cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 183cbe63bfdSIskren Chernev .flags = SUPPORTS_DYNAMIC_UPDATE, 1849e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 185cbe63bfdSIskren Chernev .clkr = { 186cbe63bfdSIskren Chernev .enable_reg = 0x79000, 187cbe63bfdSIskren Chernev .enable_mask = BIT(11), 188cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 189cbe63bfdSIskren Chernev .name = "gpll11", 190cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 191cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 192cbe63bfdSIskren Chernev }, 193cbe63bfdSIskren Chernev .num_parents = 1, 194cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 195cbe63bfdSIskren Chernev }, 196cbe63bfdSIskren Chernev }, 197cbe63bfdSIskren Chernev }; 198cbe63bfdSIskren Chernev 199cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll11_out_main[] = { 200cbe63bfdSIskren Chernev { 0x0, 1 }, 201cbe63bfdSIskren Chernev { } 202cbe63bfdSIskren Chernev }; 203cbe63bfdSIskren Chernev 204cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll11_out_main = { 205cbe63bfdSIskren Chernev .offset = 0xb000, 206cbe63bfdSIskren Chernev .post_div_shift = 8, 207cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll11_out_main, 208cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll11_out_main), 209cbe63bfdSIskren Chernev .width = 4, 2109e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 211cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 212cbe63bfdSIskren Chernev .name = "gpll11_out_main", 213cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll11.clkr.hw }, 214cbe63bfdSIskren Chernev .num_parents = 1, 215cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 216cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ops, 217cbe63bfdSIskren Chernev }, 218cbe63bfdSIskren Chernev }; 219cbe63bfdSIskren Chernev 220cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll3 = { 221cbe63bfdSIskren Chernev .offset = 0x3000, 222cbe63bfdSIskren Chernev .vco_table = default_vco, 223cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 2249e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 225cbe63bfdSIskren Chernev .clkr = { 226cbe63bfdSIskren Chernev .enable_reg = 0x79000, 227cbe63bfdSIskren Chernev .enable_mask = BIT(3), 228cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 229cbe63bfdSIskren Chernev .name = "gpll3", 230cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 231cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 232cbe63bfdSIskren Chernev }, 233cbe63bfdSIskren Chernev .num_parents = 1, 234cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 235cbe63bfdSIskren Chernev }, 236cbe63bfdSIskren Chernev }, 237cbe63bfdSIskren Chernev }; 238cbe63bfdSIskren Chernev 239cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll4 = { 240cbe63bfdSIskren Chernev .offset = 0x4000, 241cbe63bfdSIskren Chernev .vco_table = default_vco, 242cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 2439e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 244cbe63bfdSIskren Chernev .clkr = { 245cbe63bfdSIskren Chernev .enable_reg = 0x79000, 246cbe63bfdSIskren Chernev .enable_mask = BIT(4), 247cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 248cbe63bfdSIskren Chernev .name = "gpll4", 249cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 250cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 251cbe63bfdSIskren Chernev }, 252cbe63bfdSIskren Chernev .num_parents = 1, 253cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 254cbe63bfdSIskren Chernev }, 255cbe63bfdSIskren Chernev }, 256cbe63bfdSIskren Chernev }; 257cbe63bfdSIskren Chernev 258cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll4_out_main[] = { 259cbe63bfdSIskren Chernev { 0x0, 1 }, 260cbe63bfdSIskren Chernev { } 261cbe63bfdSIskren Chernev }; 262cbe63bfdSIskren Chernev 263cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll4_out_main = { 264cbe63bfdSIskren Chernev .offset = 0x4000, 265cbe63bfdSIskren Chernev .post_div_shift = 8, 266cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll4_out_main, 267cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll4_out_main), 268cbe63bfdSIskren Chernev .width = 4, 2699e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 270cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 271cbe63bfdSIskren Chernev .name = "gpll4_out_main", 272cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll4.clkr.hw }, 273cbe63bfdSIskren Chernev .num_parents = 1, 274cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 275cbe63bfdSIskren Chernev }, 276cbe63bfdSIskren Chernev }; 277cbe63bfdSIskren Chernev 278cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll6 = { 279cbe63bfdSIskren Chernev .offset = 0x6000, 280cbe63bfdSIskren Chernev .vco_table = default_vco, 281cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 2829e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 283cbe63bfdSIskren Chernev .clkr = { 284cbe63bfdSIskren Chernev .enable_reg = 0x79000, 285cbe63bfdSIskren Chernev .enable_mask = BIT(6), 286cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 287cbe63bfdSIskren Chernev .name = "gpll6", 288cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 289cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 290cbe63bfdSIskren Chernev }, 291cbe63bfdSIskren Chernev .num_parents = 1, 292cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 293cbe63bfdSIskren Chernev }, 294cbe63bfdSIskren Chernev }, 295cbe63bfdSIskren Chernev }; 296cbe63bfdSIskren Chernev 297cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll6_out_main[] = { 298cbe63bfdSIskren Chernev { 0x1, 2 }, 299cbe63bfdSIskren Chernev { } 300cbe63bfdSIskren Chernev }; 301cbe63bfdSIskren Chernev 302cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll6_out_main = { 303cbe63bfdSIskren Chernev .offset = 0x6000, 304cbe63bfdSIskren Chernev .post_div_shift = 8, 305cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll6_out_main, 306cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main), 307cbe63bfdSIskren Chernev .width = 4, 3089e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 309cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 310cbe63bfdSIskren Chernev .name = "gpll6_out_main", 311cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw }, 312cbe63bfdSIskren Chernev .num_parents = 1, 313cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 314cbe63bfdSIskren Chernev }, 315cbe63bfdSIskren Chernev }; 316cbe63bfdSIskren Chernev 317cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll7 = { 318cbe63bfdSIskren Chernev .offset = 0x7000, 319cbe63bfdSIskren Chernev .vco_table = default_vco, 320cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 3219e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 322cbe63bfdSIskren Chernev .clkr = { 323cbe63bfdSIskren Chernev .enable_reg = 0x79000, 324cbe63bfdSIskren Chernev .enable_mask = BIT(7), 325cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 326cbe63bfdSIskren Chernev .name = "gpll7", 327cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 328cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 329cbe63bfdSIskren Chernev }, 330cbe63bfdSIskren Chernev .num_parents = 1, 331cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 332cbe63bfdSIskren Chernev }, 333cbe63bfdSIskren Chernev }, 334cbe63bfdSIskren Chernev }; 335cbe63bfdSIskren Chernev 336cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll7_out_main[] = { 337cbe63bfdSIskren Chernev { 0x0, 1 }, 338cbe63bfdSIskren Chernev { } 339cbe63bfdSIskren Chernev }; 340cbe63bfdSIskren Chernev 341cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll7_out_main = { 342cbe63bfdSIskren Chernev .offset = 0x7000, 343cbe63bfdSIskren Chernev .post_div_shift = 8, 344cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll7_out_main, 345cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll7_out_main), 346cbe63bfdSIskren Chernev .width = 4, 3479e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 348cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 349cbe63bfdSIskren Chernev .name = "gpll7_out_main", 350cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll7.clkr.hw }, 351cbe63bfdSIskren Chernev .num_parents = 1, 352cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 353cbe63bfdSIskren Chernev }, 354cbe63bfdSIskren Chernev }; 355cbe63bfdSIskren Chernev 356cbe63bfdSIskren Chernev /* 800MHz configuration */ 357cbe63bfdSIskren Chernev static const struct alpha_pll_config gpll8_config = { 358cbe63bfdSIskren Chernev .l = 0x29, 359cbe63bfdSIskren Chernev .alpha = 0xAAAAAAAA, 360cbe63bfdSIskren Chernev .alpha_hi = 0xAA, 361cbe63bfdSIskren Chernev .alpha_en_mask = BIT(24), 362cbe63bfdSIskren Chernev .vco_val = 0x2 << 20, 363cbe63bfdSIskren Chernev .vco_mask = GENMASK(21, 20), 364cbe63bfdSIskren Chernev .main_output_mask = BIT(0), 365cbe63bfdSIskren Chernev .early_output_mask = BIT(3), 366cbe63bfdSIskren Chernev .post_div_val = 0x1 << 8, 367cbe63bfdSIskren Chernev .post_div_mask = GENMASK(11, 8), 368cbe63bfdSIskren Chernev .config_ctl_val = 0x4001055b, 369*e88c533dSKonrad Dybcio .test_ctl_hi1_val = 0x1, 370*e88c533dSKonrad Dybcio .test_ctl_hi_mask = 0x1, 371cbe63bfdSIskren Chernev }; 372cbe63bfdSIskren Chernev 373cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll8 = { 374cbe63bfdSIskren Chernev .offset = 0x8000, 375cbe63bfdSIskren Chernev .vco_table = default_vco, 376cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 3779e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 378cbe63bfdSIskren Chernev .flags = SUPPORTS_DYNAMIC_UPDATE, 379cbe63bfdSIskren Chernev .clkr = { 380cbe63bfdSIskren Chernev .enable_reg = 0x79000, 381cbe63bfdSIskren Chernev .enable_mask = BIT(8), 382cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 383cbe63bfdSIskren Chernev .name = "gpll8", 384cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 385cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 386cbe63bfdSIskren Chernev }, 387cbe63bfdSIskren Chernev .num_parents = 1, 388cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 389cbe63bfdSIskren Chernev }, 390cbe63bfdSIskren Chernev }, 391cbe63bfdSIskren Chernev }; 392cbe63bfdSIskren Chernev 393cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll8_out_main[] = { 394cbe63bfdSIskren Chernev { 0x1, 2 }, 395cbe63bfdSIskren Chernev { } 396cbe63bfdSIskren Chernev }; 397cbe63bfdSIskren Chernev 398cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll8_out_main = { 399cbe63bfdSIskren Chernev .offset = 0x8000, 400cbe63bfdSIskren Chernev .post_div_shift = 8, 401cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll8_out_main, 402cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main), 403cbe63bfdSIskren Chernev .width = 4, 4049e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 405cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 406cbe63bfdSIskren Chernev .name = "gpll8_out_main", 407cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw }, 408cbe63bfdSIskren Chernev .num_parents = 1, 409cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 410cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 411cbe63bfdSIskren Chernev }, 412cbe63bfdSIskren Chernev }; 413cbe63bfdSIskren Chernev 414cbe63bfdSIskren Chernev /* 1152MHz configuration */ 415cbe63bfdSIskren Chernev static const struct alpha_pll_config gpll9_config = { 416cbe63bfdSIskren Chernev .l = 0x3C, 417cbe63bfdSIskren Chernev .alpha = 0x0, 418cbe63bfdSIskren Chernev .post_div_val = 0x1 << 8, 419cbe63bfdSIskren Chernev .post_div_mask = GENMASK(9, 8), 420cbe63bfdSIskren Chernev .main_output_mask = BIT(0), 421cbe63bfdSIskren Chernev .config_ctl_val = 0x00004289, 422*e88c533dSKonrad Dybcio .test_ctl_mask = GENMASK(31, 0), 423*e88c533dSKonrad Dybcio .test_ctl_val = 0x08000000, 424cbe63bfdSIskren Chernev }; 425cbe63bfdSIskren Chernev 426cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll9 = { 427cbe63bfdSIskren Chernev .offset = 0x9000, 428cbe63bfdSIskren Chernev .vco_table = gpll9_vco, 429cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(gpll9_vco), 4309e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO], 431cbe63bfdSIskren Chernev .clkr = { 432cbe63bfdSIskren Chernev .enable_reg = 0x79000, 433cbe63bfdSIskren Chernev .enable_mask = BIT(9), 434cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 435cbe63bfdSIskren Chernev .name = "gpll9", 436cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 437cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 438cbe63bfdSIskren Chernev }, 439cbe63bfdSIskren Chernev .num_parents = 1, 440cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 441cbe63bfdSIskren Chernev }, 442cbe63bfdSIskren Chernev }, 443cbe63bfdSIskren Chernev }; 444cbe63bfdSIskren Chernev 445cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll9_out_main[] = { 446cbe63bfdSIskren Chernev { 0x1, 2 }, 447cbe63bfdSIskren Chernev { } 448cbe63bfdSIskren Chernev }; 449cbe63bfdSIskren Chernev 450cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll9_out_main = { 451cbe63bfdSIskren Chernev .offset = 0x9000, 452cbe63bfdSIskren Chernev .post_div_shift = 8, 453cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll9_out_main, 454cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main), 455cbe63bfdSIskren Chernev .width = 2, 4569e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO], 457cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 458cbe63bfdSIskren Chernev .name = "gpll9_out_main", 459cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw }, 460cbe63bfdSIskren Chernev .num_parents = 1, 461cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 462cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ops, 463cbe63bfdSIskren Chernev }, 464cbe63bfdSIskren Chernev }; 465cbe63bfdSIskren Chernev 466cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_0[] = { 467cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 468cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 469cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 470cbe63bfdSIskren Chernev }; 471cbe63bfdSIskren Chernev 472cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_0[] = { 473cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 474cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 475cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 476cbe63bfdSIskren Chernev }; 477cbe63bfdSIskren Chernev 478cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_1[] = { 479cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 480cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 481cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 482cbe63bfdSIskren Chernev { P_GPLL6_OUT_MAIN, 4 }, 483cbe63bfdSIskren Chernev }; 484cbe63bfdSIskren Chernev 485cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_1[] = { 486cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 487cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 488cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 489cbe63bfdSIskren Chernev { .hw = &gpll6_out_main.clkr.hw }, 490cbe63bfdSIskren Chernev }; 491cbe63bfdSIskren Chernev 492cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_2[] = { 493cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 494cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 495cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 496cbe63bfdSIskren Chernev { P_SLEEP_CLK, 5 }, 497cbe63bfdSIskren Chernev }; 498cbe63bfdSIskren Chernev 499cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_2[] = { 500cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 501cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 502cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 503cbe63bfdSIskren Chernev { .fw_name = "sleep_clk" }, 504cbe63bfdSIskren Chernev }; 505cbe63bfdSIskren Chernev 506cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_3[] = { 507cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 508cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 509cbe63bfdSIskren Chernev { P_GPLL9_OUT_EARLY, 2 }, 510cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 511cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 512cbe63bfdSIskren Chernev }; 513cbe63bfdSIskren Chernev 514cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_3[] = { 515cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 516cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 517cbe63bfdSIskren Chernev { .hw = &gpll9.clkr.hw }, 518cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 519cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 520cbe63bfdSIskren Chernev }; 521cbe63bfdSIskren Chernev 522cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_4[] = { 523cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 524cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 525cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 526cbe63bfdSIskren Chernev { P_GPLL4_OUT_MAIN, 5 }, 527cbe63bfdSIskren Chernev }; 528cbe63bfdSIskren Chernev 529cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_4[] = { 530cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 531cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 532cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 533cbe63bfdSIskren Chernev { .hw = &gpll4_out_main.clkr.hw }, 534cbe63bfdSIskren Chernev }; 535cbe63bfdSIskren Chernev 536cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_5[] = { 537cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 538cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 539cbe63bfdSIskren Chernev { P_GPLL8_OUT_EARLY, 2 }, 540cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 541cbe63bfdSIskren Chernev { P_GPLL8_OUT_MAIN, 4 }, 542cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 543cbe63bfdSIskren Chernev }; 544cbe63bfdSIskren Chernev 545cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_5[] = { 546cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 547cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 548cbe63bfdSIskren Chernev { .hw = &gpll8.clkr.hw }, 549cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 550cbe63bfdSIskren Chernev { .hw = &gpll8_out_main.clkr.hw }, 551cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 552cbe63bfdSIskren Chernev }; 553cbe63bfdSIskren Chernev 554cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_6[] = { 555cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 556cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 557cbe63bfdSIskren Chernev { P_GPLL8_OUT_EARLY, 2 }, 558cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 559cbe63bfdSIskren Chernev { P_GPLL6_OUT_MAIN, 4 }, 560cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 561cbe63bfdSIskren Chernev { P_GPLL3_OUT_EARLY, 6 }, 562cbe63bfdSIskren Chernev }; 563cbe63bfdSIskren Chernev 564cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_6[] = { 565cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 566cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 567cbe63bfdSIskren Chernev { .hw = &gpll8.clkr.hw }, 568cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 569cbe63bfdSIskren Chernev { .hw = &gpll6_out_main.clkr.hw }, 570cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 571cbe63bfdSIskren Chernev { .hw = &gpll3.clkr.hw }, 572cbe63bfdSIskren Chernev }; 573cbe63bfdSIskren Chernev 574cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_7[] = { 575cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 576cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 577cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 578cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 579cbe63bfdSIskren Chernev { P_GPLL4_OUT_MAIN, 5 }, 580cbe63bfdSIskren Chernev { P_GPLL3_OUT_EARLY, 6 }, 581cbe63bfdSIskren Chernev }; 582cbe63bfdSIskren Chernev 583cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_7[] = { 584cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 585cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 586cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 587cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 588cbe63bfdSIskren Chernev { .hw = &gpll4_out_main.clkr.hw }, 589cbe63bfdSIskren Chernev { .hw = &gpll3.clkr.hw }, 590cbe63bfdSIskren Chernev }; 591cbe63bfdSIskren Chernev 592cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_8[] = { 593cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 594cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 595cbe63bfdSIskren Chernev { P_GPLL8_OUT_EARLY, 2 }, 596cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 597cbe63bfdSIskren Chernev { P_GPLL8_OUT_MAIN, 4 }, 598cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 599cbe63bfdSIskren Chernev { P_GPLL3_OUT_EARLY, 6 }, 600cbe63bfdSIskren Chernev }; 601cbe63bfdSIskren Chernev 602cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_8[] = { 603cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 604cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 605cbe63bfdSIskren Chernev { .hw = &gpll8.clkr.hw }, 606cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 607cbe63bfdSIskren Chernev { .hw = &gpll8_out_main.clkr.hw }, 608cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 609cbe63bfdSIskren Chernev { .hw = &gpll3.clkr.hw }, 610cbe63bfdSIskren Chernev }; 611cbe63bfdSIskren Chernev 612cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_9[] = { 613cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 614cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 615cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 616cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 617cbe63bfdSIskren Chernev { P_GPLL8_OUT_MAIN, 4 }, 618cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 619cbe63bfdSIskren Chernev { P_GPLL3_OUT_EARLY, 6 }, 620cbe63bfdSIskren Chernev }; 621cbe63bfdSIskren Chernev 622cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_9[] = { 623cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 624cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 625cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 626cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 627cbe63bfdSIskren Chernev { .hw = &gpll8_out_main.clkr.hw }, 628cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 629cbe63bfdSIskren Chernev { .hw = &gpll3.clkr.hw }, 630cbe63bfdSIskren Chernev }; 631cbe63bfdSIskren Chernev 632cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_10[] = { 633cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 634cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 635cbe63bfdSIskren Chernev { P_GPLL8_OUT_EARLY, 2 }, 636cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 637cbe63bfdSIskren Chernev { P_GPLL6_OUT_EARLY, 4 }, 638cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 639cbe63bfdSIskren Chernev }; 640cbe63bfdSIskren Chernev 641cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_10[] = { 642cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 643cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 644cbe63bfdSIskren Chernev { .hw = &gpll8.clkr.hw }, 645cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 646cbe63bfdSIskren Chernev { .hw = &gpll6.clkr.hw }, 647cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 648cbe63bfdSIskren Chernev }; 649cbe63bfdSIskren Chernev 650cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_11[] = { 651cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 652cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 653cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 654cbe63bfdSIskren Chernev { P_GPLL7_OUT_MAIN, 3 }, 655cbe63bfdSIskren Chernev { P_GPLL4_OUT_MAIN, 5 }, 656cbe63bfdSIskren Chernev }; 657cbe63bfdSIskren Chernev 658cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_11[] = { 659cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 660cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 661cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 662cbe63bfdSIskren Chernev { .hw = &gpll7_out_main.clkr.hw }, 663cbe63bfdSIskren Chernev { .hw = &gpll4_out_main.clkr.hw }, 664cbe63bfdSIskren Chernev }; 665cbe63bfdSIskren Chernev 666cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_12[] = { 667cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 668cbe63bfdSIskren Chernev { P_SLEEP_CLK, 5 }, 669cbe63bfdSIskren Chernev }; 670cbe63bfdSIskren Chernev 671cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_12[] = { 672cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 673cbe63bfdSIskren Chernev { .fw_name = "sleep_clk" }, 674cbe63bfdSIskren Chernev }; 675cbe63bfdSIskren Chernev 676cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_13[] = { 677cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 678cbe63bfdSIskren Chernev { P_GPLL11_OUT_MAIN, 1 }, 679cbe63bfdSIskren Chernev }; 680cbe63bfdSIskren Chernev 681cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_13[] = { 682cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 683cbe63bfdSIskren Chernev { .hw = &gpll11_out_main.clkr.hw }, 684cbe63bfdSIskren Chernev }; 685cbe63bfdSIskren Chernev 686cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = { 687cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 688cbe63bfdSIskren Chernev F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 689cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 690cbe63bfdSIskren Chernev F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 691cbe63bfdSIskren Chernev { } 692cbe63bfdSIskren Chernev }; 693cbe63bfdSIskren Chernev 694cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_axi_clk_src = { 695cbe63bfdSIskren Chernev .cmd_rcgr = 0x5802c, 696cbe63bfdSIskren Chernev .mnd_width = 0, 697cbe63bfdSIskren Chernev .hid_width = 5, 698cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_7, 699cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_axi_clk_src, 700cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 701cbe63bfdSIskren Chernev .name = "gcc_camss_axi_clk_src", 702cbe63bfdSIskren Chernev .parent_data = gcc_parents_7, 703cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_7), 704cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 705996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 706cbe63bfdSIskren Chernev }, 707cbe63bfdSIskren Chernev }; 708cbe63bfdSIskren Chernev 709cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = { 710cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 711cbe63bfdSIskren Chernev F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 712cbe63bfdSIskren Chernev { } 713cbe63bfdSIskren Chernev }; 714cbe63bfdSIskren Chernev 715cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_cci_clk_src = { 716cbe63bfdSIskren Chernev .cmd_rcgr = 0x56000, 717cbe63bfdSIskren Chernev .mnd_width = 0, 718cbe63bfdSIskren Chernev .hid_width = 5, 719cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_9, 720cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_cci_clk_src, 721cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 722cbe63bfdSIskren Chernev .name = "gcc_camss_cci_clk_src", 723cbe63bfdSIskren Chernev .parent_data = gcc_parents_9, 724cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_9), 725cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 726996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 727cbe63bfdSIskren Chernev }, 728cbe63bfdSIskren Chernev }; 729cbe63bfdSIskren Chernev 730cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = { 731cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 732cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 733cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 734cbe63bfdSIskren Chernev F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0), 735cbe63bfdSIskren Chernev { } 736cbe63bfdSIskren Chernev }; 737cbe63bfdSIskren Chernev 738cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { 739cbe63bfdSIskren Chernev .cmd_rcgr = 0x59000, 740cbe63bfdSIskren Chernev .mnd_width = 0, 741cbe63bfdSIskren Chernev .hid_width = 5, 742cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_4, 743cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 744cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 745cbe63bfdSIskren Chernev .name = "gcc_camss_csi0phytimer_clk_src", 746cbe63bfdSIskren Chernev .parent_data = gcc_parents_4, 747cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_4), 748cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 749996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 750cbe63bfdSIskren Chernev }, 751cbe63bfdSIskren Chernev }; 752cbe63bfdSIskren Chernev 753cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { 754cbe63bfdSIskren Chernev .cmd_rcgr = 0x5901c, 755cbe63bfdSIskren Chernev .mnd_width = 0, 756cbe63bfdSIskren Chernev .hid_width = 5, 757cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_4, 758cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 759cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 760cbe63bfdSIskren Chernev .name = "gcc_camss_csi1phytimer_clk_src", 761cbe63bfdSIskren Chernev .parent_data = gcc_parents_4, 762cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_4), 763cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 764996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 765cbe63bfdSIskren Chernev }, 766cbe63bfdSIskren Chernev }; 767cbe63bfdSIskren Chernev 768cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = { 769cbe63bfdSIskren Chernev .cmd_rcgr = 0x59038, 770cbe63bfdSIskren Chernev .mnd_width = 0, 771cbe63bfdSIskren Chernev .hid_width = 5, 772cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_4, 773cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 774cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 775cbe63bfdSIskren Chernev .name = "gcc_camss_csi2phytimer_clk_src", 776cbe63bfdSIskren Chernev .parent_data = gcc_parents_4, 777cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_4), 778cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 779996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 780cbe63bfdSIskren Chernev }, 781cbe63bfdSIskren Chernev }; 782cbe63bfdSIskren Chernev 783cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { 784cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 785cbe63bfdSIskren Chernev F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24), 786cbe63bfdSIskren Chernev F(64000000, P_GPLL9_OUT_MAIN, 1, 1, 9), 787cbe63bfdSIskren Chernev { } 788cbe63bfdSIskren Chernev }; 789cbe63bfdSIskren Chernev 790cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_mclk0_clk_src = { 791cbe63bfdSIskren Chernev .cmd_rcgr = 0x51000, 792cbe63bfdSIskren Chernev .mnd_width = 8, 793cbe63bfdSIskren Chernev .hid_width = 5, 794cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_3, 795cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 796cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 797cbe63bfdSIskren Chernev .name = "gcc_camss_mclk0_clk_src", 798cbe63bfdSIskren Chernev .parent_data = gcc_parents_3, 799cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_3), 800cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 801996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 802cbe63bfdSIskren Chernev }, 803cbe63bfdSIskren Chernev }; 804cbe63bfdSIskren Chernev 805cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_mclk1_clk_src = { 806cbe63bfdSIskren Chernev .cmd_rcgr = 0x5101c, 807cbe63bfdSIskren Chernev .mnd_width = 8, 808cbe63bfdSIskren Chernev .hid_width = 5, 809cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_3, 810cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 811cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 812cbe63bfdSIskren Chernev .name = "gcc_camss_mclk1_clk_src", 813cbe63bfdSIskren Chernev .parent_data = gcc_parents_3, 814cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_3), 815cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 816996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 817cbe63bfdSIskren Chernev }, 818cbe63bfdSIskren Chernev }; 819cbe63bfdSIskren Chernev 820cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_mclk2_clk_src = { 821cbe63bfdSIskren Chernev .cmd_rcgr = 0x51038, 822cbe63bfdSIskren Chernev .mnd_width = 8, 823cbe63bfdSIskren Chernev .hid_width = 5, 824cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_3, 825cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 826cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 827cbe63bfdSIskren Chernev .name = "gcc_camss_mclk2_clk_src", 828cbe63bfdSIskren Chernev .parent_data = gcc_parents_3, 829cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_3), 830cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 831996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 832cbe63bfdSIskren Chernev }, 833cbe63bfdSIskren Chernev }; 834cbe63bfdSIskren Chernev 835cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_mclk3_clk_src = { 836cbe63bfdSIskren Chernev .cmd_rcgr = 0x51054, 837cbe63bfdSIskren Chernev .mnd_width = 8, 838cbe63bfdSIskren Chernev .hid_width = 5, 839cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_3, 840cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 841cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 842cbe63bfdSIskren Chernev .name = "gcc_camss_mclk3_clk_src", 843cbe63bfdSIskren Chernev .parent_data = gcc_parents_3, 844cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_3), 845cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 846996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 847cbe63bfdSIskren Chernev }, 848cbe63bfdSIskren Chernev }; 849cbe63bfdSIskren Chernev 850cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = { 851cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 852cbe63bfdSIskren Chernev F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0), 853cbe63bfdSIskren Chernev F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 854cbe63bfdSIskren Chernev { } 855cbe63bfdSIskren Chernev }; 856cbe63bfdSIskren Chernev 857cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = { 858cbe63bfdSIskren Chernev .cmd_rcgr = 0x55024, 859cbe63bfdSIskren Chernev .mnd_width = 0, 860cbe63bfdSIskren Chernev .hid_width = 5, 861cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_8, 862cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src, 863cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 864cbe63bfdSIskren Chernev .name = "gcc_camss_ope_ahb_clk_src", 865cbe63bfdSIskren Chernev .parent_data = gcc_parents_8, 866cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_8), 867cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 868996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 869cbe63bfdSIskren Chernev }, 870cbe63bfdSIskren Chernev }; 871cbe63bfdSIskren Chernev 872cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = { 873cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 874cbe63bfdSIskren Chernev F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0), 875cbe63bfdSIskren Chernev F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0), 876cbe63bfdSIskren Chernev F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0), 877cbe63bfdSIskren Chernev F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0), 878cbe63bfdSIskren Chernev { } 879cbe63bfdSIskren Chernev }; 880cbe63bfdSIskren Chernev 881cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_ope_clk_src = { 882cbe63bfdSIskren Chernev .cmd_rcgr = 0x55004, 883cbe63bfdSIskren Chernev .mnd_width = 0, 884cbe63bfdSIskren Chernev .hid_width = 5, 885cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_8, 886cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_ope_clk_src, 887cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 888cbe63bfdSIskren Chernev .name = "gcc_camss_ope_clk_src", 889cbe63bfdSIskren Chernev .parent_data = gcc_parents_8, 890cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_8), 891cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 892996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 893cbe63bfdSIskren Chernev }, 894cbe63bfdSIskren Chernev }; 895cbe63bfdSIskren Chernev 896cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = { 897cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 898cbe63bfdSIskren Chernev F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0), 899cbe63bfdSIskren Chernev F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0), 900cbe63bfdSIskren Chernev F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0), 901cbe63bfdSIskren Chernev F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0), 902cbe63bfdSIskren Chernev F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0), 903cbe63bfdSIskren Chernev F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0), 904cbe63bfdSIskren Chernev F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0), 905cbe63bfdSIskren Chernev F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0), 906cbe63bfdSIskren Chernev F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0), 907cbe63bfdSIskren Chernev F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0), 908cbe63bfdSIskren Chernev F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0), 909cbe63bfdSIskren Chernev F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0), 910cbe63bfdSIskren Chernev F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0), 911cbe63bfdSIskren Chernev F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0), 912cbe63bfdSIskren Chernev F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0), 913cbe63bfdSIskren Chernev { } 914cbe63bfdSIskren Chernev }; 915cbe63bfdSIskren Chernev 916cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_0_clk_src = { 917cbe63bfdSIskren Chernev .cmd_rcgr = 0x52004, 918cbe63bfdSIskren Chernev .mnd_width = 8, 919cbe63bfdSIskren Chernev .hid_width = 5, 920cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_5, 921cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 922cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 923cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_0_clk_src", 924cbe63bfdSIskren Chernev .parent_data = gcc_parents_5, 925cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_5), 926cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 927996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 928cbe63bfdSIskren Chernev }, 929cbe63bfdSIskren Chernev }; 930cbe63bfdSIskren Chernev 931cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = { 932cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 933cbe63bfdSIskren Chernev F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0), 934cbe63bfdSIskren Chernev F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 935cbe63bfdSIskren Chernev F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 936cbe63bfdSIskren Chernev F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 937cbe63bfdSIskren Chernev F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0), 938cbe63bfdSIskren Chernev { } 939cbe63bfdSIskren Chernev }; 940cbe63bfdSIskren Chernev 941cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = { 942cbe63bfdSIskren Chernev .cmd_rcgr = 0x52094, 943cbe63bfdSIskren Chernev .mnd_width = 0, 944cbe63bfdSIskren Chernev .hid_width = 5, 945cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_6, 946cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 947cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 948cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_0_csid_clk_src", 949cbe63bfdSIskren Chernev .parent_data = gcc_parents_6, 950cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_6), 951cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 952996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 953cbe63bfdSIskren Chernev }, 954cbe63bfdSIskren Chernev }; 955cbe63bfdSIskren Chernev 956cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_1_clk_src = { 957cbe63bfdSIskren Chernev .cmd_rcgr = 0x52024, 958cbe63bfdSIskren Chernev .mnd_width = 8, 959cbe63bfdSIskren Chernev .hid_width = 5, 960cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_5, 961cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 962cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 963cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_1_clk_src", 964cbe63bfdSIskren Chernev .parent_data = gcc_parents_5, 965cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_5), 966cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 967996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 968cbe63bfdSIskren Chernev }, 969cbe63bfdSIskren Chernev }; 970cbe63bfdSIskren Chernev 971cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = { 972cbe63bfdSIskren Chernev .cmd_rcgr = 0x520b4, 973cbe63bfdSIskren Chernev .mnd_width = 0, 974cbe63bfdSIskren Chernev .hid_width = 5, 975cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_6, 976cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 977cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 978cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_1_csid_clk_src", 979cbe63bfdSIskren Chernev .parent_data = gcc_parents_6, 980cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_6), 981cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 982996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 983cbe63bfdSIskren Chernev }, 984cbe63bfdSIskren Chernev }; 985cbe63bfdSIskren Chernev 986cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_2_clk_src = { 987cbe63bfdSIskren Chernev .cmd_rcgr = 0x52044, 988cbe63bfdSIskren Chernev .mnd_width = 8, 989cbe63bfdSIskren Chernev .hid_width = 5, 990cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_5, 991cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 992cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 993cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_2_clk_src", 994cbe63bfdSIskren Chernev .parent_data = gcc_parents_5, 995cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_5), 996cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 997996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 998cbe63bfdSIskren Chernev }, 999cbe63bfdSIskren Chernev }; 1000cbe63bfdSIskren Chernev 1001cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_2_csid_clk_src = { 1002cbe63bfdSIskren Chernev .cmd_rcgr = 0x520d4, 1003cbe63bfdSIskren Chernev .mnd_width = 0, 1004cbe63bfdSIskren Chernev .hid_width = 5, 1005cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_6, 1006cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 1007cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1008cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_2_csid_clk_src", 1009cbe63bfdSIskren Chernev .parent_data = gcc_parents_6, 1010cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_6), 1011cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1012996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1013cbe63bfdSIskren Chernev }, 1014cbe63bfdSIskren Chernev }; 1015cbe63bfdSIskren Chernev 1016cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = { 1017cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1018cbe63bfdSIskren Chernev F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1019cbe63bfdSIskren Chernev F(341333333, P_GPLL6_OUT_EARLY, 1, 4, 9), 1020cbe63bfdSIskren Chernev F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0), 1021cbe63bfdSIskren Chernev { } 1022cbe63bfdSIskren Chernev }; 1023cbe63bfdSIskren Chernev 1024cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = { 1025cbe63bfdSIskren Chernev .cmd_rcgr = 0x52064, 1026cbe63bfdSIskren Chernev .mnd_width = 16, 1027cbe63bfdSIskren Chernev .hid_width = 5, 1028cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_10, 1029cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src, 1030cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1031cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_cphy_rx_clk_src", 1032cbe63bfdSIskren Chernev .parent_data = gcc_parents_10, 1033cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_10), 1034cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 1035996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1036cbe63bfdSIskren Chernev }, 1037cbe63bfdSIskren Chernev }; 1038cbe63bfdSIskren Chernev 1039cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = { 1040cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1041cbe63bfdSIskren Chernev F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0), 1042cbe63bfdSIskren Chernev F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0), 1043cbe63bfdSIskren Chernev { } 1044cbe63bfdSIskren Chernev }; 1045cbe63bfdSIskren Chernev 1046cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_top_ahb_clk_src = { 1047cbe63bfdSIskren Chernev .cmd_rcgr = 0x58010, 1048cbe63bfdSIskren Chernev .mnd_width = 0, 1049cbe63bfdSIskren Chernev .hid_width = 5, 1050cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_7, 1051cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_top_ahb_clk_src, 1052cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1053cbe63bfdSIskren Chernev .name = "gcc_camss_top_ahb_clk_src", 1054cbe63bfdSIskren Chernev .parent_data = gcc_parents_7, 1055cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_7), 1056cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 1057996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1058cbe63bfdSIskren Chernev }, 1059cbe63bfdSIskren Chernev }; 1060cbe63bfdSIskren Chernev 1061cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 1062cbe63bfdSIskren Chernev F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1063cbe63bfdSIskren Chernev F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1064cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1065cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 1066cbe63bfdSIskren Chernev { } 1067cbe63bfdSIskren Chernev }; 1068cbe63bfdSIskren Chernev 1069cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_gp1_clk_src = { 1070cbe63bfdSIskren Chernev .cmd_rcgr = 0x4d004, 1071cbe63bfdSIskren Chernev .mnd_width = 8, 1072cbe63bfdSIskren Chernev .hid_width = 5, 1073cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_2, 1074cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_gp1_clk_src, 1075cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1076cbe63bfdSIskren Chernev .name = "gcc_gp1_clk_src", 1077cbe63bfdSIskren Chernev .parent_data = gcc_parents_2, 1078cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_2), 1079cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1080cbe63bfdSIskren Chernev }, 1081cbe63bfdSIskren Chernev }; 1082cbe63bfdSIskren Chernev 1083cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_gp2_clk_src = { 1084cbe63bfdSIskren Chernev .cmd_rcgr = 0x4e004, 1085cbe63bfdSIskren Chernev .mnd_width = 8, 1086cbe63bfdSIskren Chernev .hid_width = 5, 1087cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_2, 1088cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_gp1_clk_src, 1089cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1090cbe63bfdSIskren Chernev .name = "gcc_gp2_clk_src", 1091cbe63bfdSIskren Chernev .parent_data = gcc_parents_2, 1092cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_2), 1093cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1094cbe63bfdSIskren Chernev }, 1095cbe63bfdSIskren Chernev }; 1096cbe63bfdSIskren Chernev 1097cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_gp3_clk_src = { 1098cbe63bfdSIskren Chernev .cmd_rcgr = 0x4f004, 1099cbe63bfdSIskren Chernev .mnd_width = 8, 1100cbe63bfdSIskren Chernev .hid_width = 5, 1101cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_2, 1102cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_gp1_clk_src, 1103cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1104cbe63bfdSIskren Chernev .name = "gcc_gp3_clk_src", 1105cbe63bfdSIskren Chernev .parent_data = gcc_parents_2, 1106cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_2), 1107cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1108cbe63bfdSIskren Chernev }, 1109cbe63bfdSIskren Chernev }; 1110cbe63bfdSIskren Chernev 1111cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 1112cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1113cbe63bfdSIskren Chernev F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0), 1114cbe63bfdSIskren Chernev { } 1115cbe63bfdSIskren Chernev }; 1116cbe63bfdSIskren Chernev 1117cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_pdm2_clk_src = { 1118cbe63bfdSIskren Chernev .cmd_rcgr = 0x20010, 1119cbe63bfdSIskren Chernev .mnd_width = 0, 1120cbe63bfdSIskren Chernev .hid_width = 5, 1121cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1122cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_pdm2_clk_src, 1123cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1124cbe63bfdSIskren Chernev .name = "gcc_pdm2_clk_src", 1125cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1126cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1127996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1128cbe63bfdSIskren Chernev }, 1129cbe63bfdSIskren Chernev }; 1130cbe63bfdSIskren Chernev 1131cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 1132cbe63bfdSIskren Chernev F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625), 1133cbe63bfdSIskren Chernev F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625), 1134cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1135cbe63bfdSIskren Chernev F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625), 1136cbe63bfdSIskren Chernev F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75), 1137cbe63bfdSIskren Chernev F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25), 1138cbe63bfdSIskren Chernev F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75), 1139cbe63bfdSIskren Chernev F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1140cbe63bfdSIskren Chernev F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15), 1141cbe63bfdSIskren Chernev F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25), 1142cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1143cbe63bfdSIskren Chernev F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375), 1144cbe63bfdSIskren Chernev F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75), 1145cbe63bfdSIskren Chernev F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625), 1146cbe63bfdSIskren Chernev F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0), 1147cbe63bfdSIskren Chernev F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0), 1148cbe63bfdSIskren Chernev { } 1149cbe63bfdSIskren Chernev }; 1150cbe63bfdSIskren Chernev 1151cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 1152cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s0_clk_src", 1153cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1154cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1155cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1156cbe63bfdSIskren Chernev }; 1157cbe63bfdSIskren Chernev 1158cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 1159cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f148, 1160cbe63bfdSIskren Chernev .mnd_width = 16, 1161cbe63bfdSIskren Chernev .hid_width = 5, 1162cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1163cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1164cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 1165cbe63bfdSIskren Chernev }; 1166cbe63bfdSIskren Chernev 1167cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 1168cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s1_clk_src", 1169cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1170cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1171cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1172cbe63bfdSIskren Chernev }; 1173cbe63bfdSIskren Chernev 1174cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 1175cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f278, 1176cbe63bfdSIskren Chernev .mnd_width = 16, 1177cbe63bfdSIskren Chernev .hid_width = 5, 1178cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1179cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1180cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 1181cbe63bfdSIskren Chernev }; 1182cbe63bfdSIskren Chernev 1183cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 1184cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s2_clk_src", 1185cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1186cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1187cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1188cbe63bfdSIskren Chernev }; 1189cbe63bfdSIskren Chernev 1190cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 1191cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f3a8, 1192cbe63bfdSIskren Chernev .mnd_width = 16, 1193cbe63bfdSIskren Chernev .hid_width = 5, 1194cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1195cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1196cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 1197cbe63bfdSIskren Chernev }; 1198cbe63bfdSIskren Chernev 1199cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 1200cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s3_clk_src", 1201cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1202cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1203cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1204cbe63bfdSIskren Chernev }; 1205cbe63bfdSIskren Chernev 1206cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 1207cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f4d8, 1208cbe63bfdSIskren Chernev .mnd_width = 16, 1209cbe63bfdSIskren Chernev .hid_width = 5, 1210cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1211cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1212cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 1213cbe63bfdSIskren Chernev }; 1214cbe63bfdSIskren Chernev 1215cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 1216cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s4_clk_src", 1217cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1218cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1219cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1220cbe63bfdSIskren Chernev }; 1221cbe63bfdSIskren Chernev 1222cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 1223cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f608, 1224cbe63bfdSIskren Chernev .mnd_width = 16, 1225cbe63bfdSIskren Chernev .hid_width = 5, 1226cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1227cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1228cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 1229cbe63bfdSIskren Chernev }; 1230cbe63bfdSIskren Chernev 1231cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 1232cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s5_clk_src", 1233cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1234cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1235cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1236cbe63bfdSIskren Chernev }; 1237cbe63bfdSIskren Chernev 1238cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 1239cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f738, 1240cbe63bfdSIskren Chernev .mnd_width = 16, 1241cbe63bfdSIskren Chernev .hid_width = 5, 1242cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1243cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1244cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 1245cbe63bfdSIskren Chernev }; 1246cbe63bfdSIskren Chernev 1247cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 1248cbe63bfdSIskren Chernev F(144000, P_BI_TCXO, 16, 3, 25), 1249cbe63bfdSIskren Chernev F(400000, P_BI_TCXO, 12, 1, 4), 1250cbe63bfdSIskren Chernev F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3), 1251cbe63bfdSIskren Chernev F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2), 1252cbe63bfdSIskren Chernev F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1253cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1254cbe63bfdSIskren Chernev F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 1255cbe63bfdSIskren Chernev F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 1256cbe63bfdSIskren Chernev { } 1257cbe63bfdSIskren Chernev }; 1258cbe63bfdSIskren Chernev 1259cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 1260cbe63bfdSIskren Chernev .cmd_rcgr = 0x38028, 1261cbe63bfdSIskren Chernev .mnd_width = 8, 1262cbe63bfdSIskren Chernev .hid_width = 5, 1263cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1264cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 1265cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1266cbe63bfdSIskren Chernev .name = "gcc_sdcc1_apps_clk_src", 1267cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1268cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 126985d4e6eaSKonrad Dybcio .ops = &clk_rcg2_floor_ops, 1270cbe63bfdSIskren Chernev }, 1271cbe63bfdSIskren Chernev }; 1272cbe63bfdSIskren Chernev 1273cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 1274cbe63bfdSIskren Chernev F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1275cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1276cbe63bfdSIskren Chernev F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1277cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1278cbe63bfdSIskren Chernev F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 1279cbe63bfdSIskren Chernev { } 1280cbe63bfdSIskren Chernev }; 1281cbe63bfdSIskren Chernev 1282cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 1283cbe63bfdSIskren Chernev .cmd_rcgr = 0x38010, 1284cbe63bfdSIskren Chernev .mnd_width = 0, 1285cbe63bfdSIskren Chernev .hid_width = 5, 1286cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1287cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 1288cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1289cbe63bfdSIskren Chernev .name = "gcc_sdcc1_ice_core_clk_src", 1290cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1291cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1292cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1293cbe63bfdSIskren Chernev }, 1294cbe63bfdSIskren Chernev }; 1295cbe63bfdSIskren Chernev 1296cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1297cbe63bfdSIskren Chernev F(400000, P_BI_TCXO, 12, 1, 4), 1298cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1299cbe63bfdSIskren Chernev F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1300cbe63bfdSIskren Chernev F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1301cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1302cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1303cbe63bfdSIskren Chernev { } 1304cbe63bfdSIskren Chernev }; 1305cbe63bfdSIskren Chernev 1306cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1307cbe63bfdSIskren Chernev .cmd_rcgr = 0x1e00c, 1308cbe63bfdSIskren Chernev .mnd_width = 8, 1309cbe63bfdSIskren Chernev .hid_width = 5, 1310cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_11, 1311cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1312cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1313cbe63bfdSIskren Chernev .name = "gcc_sdcc2_apps_clk_src", 1314cbe63bfdSIskren Chernev .parent_data = gcc_parents_11, 1315cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_11), 131685d4e6eaSKonrad Dybcio .ops = &clk_rcg2_floor_ops, 1317cbe63bfdSIskren Chernev .flags = CLK_OPS_PARENT_ENABLE, 1318cbe63bfdSIskren Chernev }, 1319cbe63bfdSIskren Chernev }; 1320cbe63bfdSIskren Chernev 1321cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1322cbe63bfdSIskren Chernev F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1323cbe63bfdSIskren Chernev F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1324cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1325cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1326cbe63bfdSIskren Chernev F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1327cbe63bfdSIskren Chernev { } 1328cbe63bfdSIskren Chernev }; 1329cbe63bfdSIskren Chernev 1330cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1331cbe63bfdSIskren Chernev .cmd_rcgr = 0x45020, 1332cbe63bfdSIskren Chernev .mnd_width = 8, 1333cbe63bfdSIskren Chernev .hid_width = 5, 1334cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1335cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1336cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1337cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_axi_clk_src", 1338cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1339cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1340996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1341cbe63bfdSIskren Chernev }, 1342cbe63bfdSIskren Chernev }; 1343cbe63bfdSIskren Chernev 1344cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1345cbe63bfdSIskren Chernev F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 1346cbe63bfdSIskren Chernev F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1347cbe63bfdSIskren Chernev F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1348cbe63bfdSIskren Chernev F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 1349cbe63bfdSIskren Chernev { } 1350cbe63bfdSIskren Chernev }; 1351cbe63bfdSIskren Chernev 1352cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1353cbe63bfdSIskren Chernev .cmd_rcgr = 0x45048, 1354cbe63bfdSIskren Chernev .mnd_width = 0, 1355cbe63bfdSIskren Chernev .hid_width = 5, 1356cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1357cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1358cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1359cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_ice_core_clk_src", 1360cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1361cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1362996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1363cbe63bfdSIskren Chernev }, 1364cbe63bfdSIskren Chernev }; 1365cbe63bfdSIskren Chernev 1366cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1367cbe63bfdSIskren Chernev F(9600000, P_BI_TCXO, 2, 0, 0), 1368cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1369cbe63bfdSIskren Chernev { } 1370cbe63bfdSIskren Chernev }; 1371cbe63bfdSIskren Chernev 1372cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1373cbe63bfdSIskren Chernev .cmd_rcgr = 0x4507c, 1374cbe63bfdSIskren Chernev .mnd_width = 0, 1375cbe63bfdSIskren Chernev .hid_width = 5, 1376cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1377cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1378cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1379cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_phy_aux_clk_src", 1380cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1381cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1382cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1383cbe63bfdSIskren Chernev }, 1384cbe63bfdSIskren Chernev }; 1385cbe63bfdSIskren Chernev 1386cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 1387cbe63bfdSIskren Chernev F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 1388cbe63bfdSIskren Chernev F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1389cbe63bfdSIskren Chernev F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1390cbe63bfdSIskren Chernev { } 1391cbe63bfdSIskren Chernev }; 1392cbe63bfdSIskren Chernev 1393cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1394cbe63bfdSIskren Chernev .cmd_rcgr = 0x45060, 1395cbe63bfdSIskren Chernev .mnd_width = 0, 1396cbe63bfdSIskren Chernev .hid_width = 5, 1397cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1398cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 1399cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1400cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_unipro_core_clk_src", 1401cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1402cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1403996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1404cbe63bfdSIskren Chernev }, 1405cbe63bfdSIskren Chernev }; 1406cbe63bfdSIskren Chernev 1407cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1408cbe63bfdSIskren Chernev F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0), 1409cbe63bfdSIskren Chernev F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0), 1410cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1411cbe63bfdSIskren Chernev F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1412cbe63bfdSIskren Chernev { } 1413cbe63bfdSIskren Chernev }; 1414cbe63bfdSIskren Chernev 1415cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1416cbe63bfdSIskren Chernev .cmd_rcgr = 0x1a01c, 1417cbe63bfdSIskren Chernev .mnd_width = 8, 1418cbe63bfdSIskren Chernev .hid_width = 5, 1419cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1420cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1421cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1422cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_master_clk_src", 1423cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1424cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1425996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1426cbe63bfdSIskren Chernev }, 1427cbe63bfdSIskren Chernev }; 1428cbe63bfdSIskren Chernev 1429cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 1430cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1431cbe63bfdSIskren Chernev { } 1432cbe63bfdSIskren Chernev }; 1433cbe63bfdSIskren Chernev 1434cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1435cbe63bfdSIskren Chernev .cmd_rcgr = 0x1a034, 1436cbe63bfdSIskren Chernev .mnd_width = 0, 1437cbe63bfdSIskren Chernev .hid_width = 5, 1438cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1439cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1440cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1441cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_mock_utmi_clk_src", 1442cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1443cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1444cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1445cbe63bfdSIskren Chernev }, 1446cbe63bfdSIskren Chernev }; 1447cbe63bfdSIskren Chernev 1448cbe63bfdSIskren Chernev static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1449cbe63bfdSIskren Chernev .reg = 0x1a04c, 1450cbe63bfdSIskren Chernev .shift = 0, 1451cbe63bfdSIskren Chernev .width = 2, 1452cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data) { 1453cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1454cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]) { 1455cbe63bfdSIskren Chernev &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw }, 1456cbe63bfdSIskren Chernev .num_parents = 1, 1457cbe63bfdSIskren Chernev .ops = &clk_regmap_div_ro_ops, 1458cbe63bfdSIskren Chernev }, 1459cbe63bfdSIskren Chernev }; 1460cbe63bfdSIskren Chernev 1461cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1462cbe63bfdSIskren Chernev .cmd_rcgr = 0x1a060, 1463cbe63bfdSIskren Chernev .mnd_width = 0, 1464cbe63bfdSIskren Chernev .hid_width = 5, 1465cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_12, 1466cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1467cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1468cbe63bfdSIskren Chernev .name = "gcc_usb3_prim_phy_aux_clk_src", 1469cbe63bfdSIskren Chernev .parent_data = gcc_parents_12, 1470cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_12), 1471cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1472cbe63bfdSIskren Chernev }, 1473cbe63bfdSIskren Chernev }; 1474cbe63bfdSIskren Chernev 1475cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = { 1476cbe63bfdSIskren Chernev F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0), 1477cbe63bfdSIskren Chernev F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0), 1478cbe63bfdSIskren Chernev F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0), 1479cbe63bfdSIskren Chernev F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0), 1480cbe63bfdSIskren Chernev { } 1481cbe63bfdSIskren Chernev }; 1482cbe63bfdSIskren Chernev 1483cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_video_venus_clk_src = { 1484cbe63bfdSIskren Chernev .cmd_rcgr = 0x58060, 1485cbe63bfdSIskren Chernev .mnd_width = 0, 1486cbe63bfdSIskren Chernev .hid_width = 5, 1487cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_13, 1488cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_video_venus_clk_src, 1489cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1490cbe63bfdSIskren Chernev .name = "gcc_video_venus_clk_src", 1491cbe63bfdSIskren Chernev .parent_data = gcc_parents_13, 1492cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_13), 1493cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1494996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1495cbe63bfdSIskren Chernev }, 1496cbe63bfdSIskren Chernev }; 1497cbe63bfdSIskren Chernev 1498cbe63bfdSIskren Chernev static struct clk_branch gcc_ahb2phy_csi_clk = { 1499cbe63bfdSIskren Chernev .halt_reg = 0x1d004, 1500cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1501cbe63bfdSIskren Chernev .hwcg_reg = 0x1d004, 1502cbe63bfdSIskren Chernev .hwcg_bit = 1, 1503cbe63bfdSIskren Chernev .clkr = { 1504cbe63bfdSIskren Chernev .enable_reg = 0x1d004, 1505cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1506cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1507cbe63bfdSIskren Chernev .name = "gcc_ahb2phy_csi_clk", 1508cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1509cbe63bfdSIskren Chernev }, 1510cbe63bfdSIskren Chernev }, 1511cbe63bfdSIskren Chernev }; 1512cbe63bfdSIskren Chernev 1513cbe63bfdSIskren Chernev static struct clk_branch gcc_ahb2phy_usb_clk = { 1514cbe63bfdSIskren Chernev .halt_reg = 0x1d008, 1515cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1516cbe63bfdSIskren Chernev .hwcg_reg = 0x1d008, 1517cbe63bfdSIskren Chernev .hwcg_bit = 1, 1518cbe63bfdSIskren Chernev .clkr = { 1519cbe63bfdSIskren Chernev .enable_reg = 0x1d008, 1520cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1521cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1522cbe63bfdSIskren Chernev .name = "gcc_ahb2phy_usb_clk", 1523cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1524cbe63bfdSIskren Chernev }, 1525cbe63bfdSIskren Chernev }, 1526cbe63bfdSIskren Chernev }; 1527cbe63bfdSIskren Chernev 1528cbe63bfdSIskren Chernev static struct clk_branch gcc_bimc_gpu_axi_clk = { 1529cbe63bfdSIskren Chernev .halt_reg = 0x71154, 1530cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 1531cbe63bfdSIskren Chernev .hwcg_reg = 0x71154, 1532cbe63bfdSIskren Chernev .hwcg_bit = 1, 1533cbe63bfdSIskren Chernev .clkr = { 1534cbe63bfdSIskren Chernev .enable_reg = 0x71154, 1535cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1536cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1537cbe63bfdSIskren Chernev .name = "gcc_bimc_gpu_axi_clk", 1538cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1539cbe63bfdSIskren Chernev }, 1540cbe63bfdSIskren Chernev }, 1541cbe63bfdSIskren Chernev }; 1542cbe63bfdSIskren Chernev 1543cbe63bfdSIskren Chernev static struct clk_branch gcc_boot_rom_ahb_clk = { 1544cbe63bfdSIskren Chernev .halt_reg = 0x23004, 1545cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 1546cbe63bfdSIskren Chernev .hwcg_reg = 0x23004, 1547cbe63bfdSIskren Chernev .hwcg_bit = 1, 1548cbe63bfdSIskren Chernev .clkr = { 1549cbe63bfdSIskren Chernev .enable_reg = 0x79004, 1550cbe63bfdSIskren Chernev .enable_mask = BIT(10), 1551cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1552cbe63bfdSIskren Chernev .name = "gcc_boot_rom_ahb_clk", 1553cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1554cbe63bfdSIskren Chernev }, 1555cbe63bfdSIskren Chernev }, 1556cbe63bfdSIskren Chernev }; 1557cbe63bfdSIskren Chernev 1558cbe63bfdSIskren Chernev static struct clk_branch gcc_cam_throttle_nrt_clk = { 1559cbe63bfdSIskren Chernev .halt_reg = 0x17070, 1560cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 1561cbe63bfdSIskren Chernev .hwcg_reg = 0x17070, 1562cbe63bfdSIskren Chernev .hwcg_bit = 1, 1563cbe63bfdSIskren Chernev .clkr = { 1564cbe63bfdSIskren Chernev .enable_reg = 0x79004, 1565cbe63bfdSIskren Chernev .enable_mask = BIT(27), 1566cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1567cbe63bfdSIskren Chernev .name = "gcc_cam_throttle_nrt_clk", 1568cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1569cbe63bfdSIskren Chernev }, 1570cbe63bfdSIskren Chernev }, 1571cbe63bfdSIskren Chernev }; 1572cbe63bfdSIskren Chernev 1573cbe63bfdSIskren Chernev static struct clk_branch gcc_cam_throttle_rt_clk = { 1574cbe63bfdSIskren Chernev .halt_reg = 0x1706c, 1575cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 1576cbe63bfdSIskren Chernev .hwcg_reg = 0x1706c, 1577cbe63bfdSIskren Chernev .hwcg_bit = 1, 1578cbe63bfdSIskren Chernev .clkr = { 1579cbe63bfdSIskren Chernev .enable_reg = 0x79004, 1580cbe63bfdSIskren Chernev .enable_mask = BIT(26), 1581cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1582cbe63bfdSIskren Chernev .name = "gcc_cam_throttle_rt_clk", 1583cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1584cbe63bfdSIskren Chernev }, 1585cbe63bfdSIskren Chernev }, 1586cbe63bfdSIskren Chernev }; 1587cbe63bfdSIskren Chernev 1588cbe63bfdSIskren Chernev static struct clk_branch gcc_camera_ahb_clk = { 1589cbe63bfdSIskren Chernev .halt_reg = 0x17008, 1590cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 1591cbe63bfdSIskren Chernev .hwcg_reg = 0x17008, 1592cbe63bfdSIskren Chernev .hwcg_bit = 1, 1593cbe63bfdSIskren Chernev .clkr = { 1594cbe63bfdSIskren Chernev .enable_reg = 0x17008, 1595cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1596cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1597cbe63bfdSIskren Chernev .name = "gcc_camera_ahb_clk", 1598cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 1599cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1600cbe63bfdSIskren Chernev }, 1601cbe63bfdSIskren Chernev }, 1602cbe63bfdSIskren Chernev }; 1603cbe63bfdSIskren Chernev 1604cbe63bfdSIskren Chernev static struct clk_branch gcc_camera_xo_clk = { 1605cbe63bfdSIskren Chernev .halt_reg = 0x17028, 1606cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1607cbe63bfdSIskren Chernev .clkr = { 1608cbe63bfdSIskren Chernev .enable_reg = 0x17028, 1609cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1610cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1611cbe63bfdSIskren Chernev .name = "gcc_camera_xo_clk", 1612cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 1613cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1614cbe63bfdSIskren Chernev }, 1615cbe63bfdSIskren Chernev }, 1616cbe63bfdSIskren Chernev }; 1617cbe63bfdSIskren Chernev 1618cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_axi_clk = { 1619cbe63bfdSIskren Chernev .halt_reg = 0x58044, 1620cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1621cbe63bfdSIskren Chernev .clkr = { 1622cbe63bfdSIskren Chernev .enable_reg = 0x58044, 1623cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1624cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1625cbe63bfdSIskren Chernev .name = "gcc_camss_axi_clk", 1626cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1627cbe63bfdSIskren Chernev &gcc_camss_axi_clk_src.clkr.hw, 1628cbe63bfdSIskren Chernev }, 1629cbe63bfdSIskren Chernev .num_parents = 1, 1630cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1631cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1632cbe63bfdSIskren Chernev }, 1633cbe63bfdSIskren Chernev }, 1634cbe63bfdSIskren Chernev }; 1635cbe63bfdSIskren Chernev 1636cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_camnoc_atb_clk = { 1637cbe63bfdSIskren Chernev .halt_reg = 0x5804c, 1638cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 1639cbe63bfdSIskren Chernev .hwcg_reg = 0x5804c, 1640cbe63bfdSIskren Chernev .hwcg_bit = 1, 1641cbe63bfdSIskren Chernev .clkr = { 1642cbe63bfdSIskren Chernev .enable_reg = 0x5804c, 1643cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1644cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1645cbe63bfdSIskren Chernev .name = "gcc_camss_camnoc_atb_clk", 1646cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1647cbe63bfdSIskren Chernev }, 1648cbe63bfdSIskren Chernev }, 1649cbe63bfdSIskren Chernev }; 1650cbe63bfdSIskren Chernev 1651cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_camnoc_nts_xo_clk = { 1652cbe63bfdSIskren Chernev .halt_reg = 0x58050, 1653cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 1654cbe63bfdSIskren Chernev .hwcg_reg = 0x58050, 1655cbe63bfdSIskren Chernev .hwcg_bit = 1, 1656cbe63bfdSIskren Chernev .clkr = { 1657cbe63bfdSIskren Chernev .enable_reg = 0x58050, 1658cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1659cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1660cbe63bfdSIskren Chernev .name = "gcc_camss_camnoc_nts_xo_clk", 1661cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1662cbe63bfdSIskren Chernev }, 1663cbe63bfdSIskren Chernev }, 1664cbe63bfdSIskren Chernev }; 1665cbe63bfdSIskren Chernev 1666cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_cci_0_clk = { 1667cbe63bfdSIskren Chernev .halt_reg = 0x56018, 1668cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1669cbe63bfdSIskren Chernev .clkr = { 1670cbe63bfdSIskren Chernev .enable_reg = 0x56018, 1671cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1672cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1673cbe63bfdSIskren Chernev .name = "gcc_camss_cci_0_clk", 1674cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1675cbe63bfdSIskren Chernev &gcc_camss_cci_clk_src.clkr.hw, 1676cbe63bfdSIskren Chernev }, 1677cbe63bfdSIskren Chernev .num_parents = 1, 1678cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1679cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1680cbe63bfdSIskren Chernev }, 1681cbe63bfdSIskren Chernev }, 1682cbe63bfdSIskren Chernev }; 1683cbe63bfdSIskren Chernev 1684cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_cphy_0_clk = { 1685cbe63bfdSIskren Chernev .halt_reg = 0x52088, 1686cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1687cbe63bfdSIskren Chernev .clkr = { 1688cbe63bfdSIskren Chernev .enable_reg = 0x52088, 1689cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1690cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1691cbe63bfdSIskren Chernev .name = "gcc_camss_cphy_0_clk", 1692cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1693cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1694cbe63bfdSIskren Chernev }, 1695cbe63bfdSIskren Chernev .num_parents = 1, 1696cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1697cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1698cbe63bfdSIskren Chernev }, 1699cbe63bfdSIskren Chernev }, 1700cbe63bfdSIskren Chernev }; 1701cbe63bfdSIskren Chernev 1702cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_cphy_1_clk = { 1703cbe63bfdSIskren Chernev .halt_reg = 0x5208c, 1704cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1705cbe63bfdSIskren Chernev .clkr = { 1706cbe63bfdSIskren Chernev .enable_reg = 0x5208c, 1707cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1708cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1709cbe63bfdSIskren Chernev .name = "gcc_camss_cphy_1_clk", 1710cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1711cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1712cbe63bfdSIskren Chernev }, 1713cbe63bfdSIskren Chernev .num_parents = 1, 1714cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1715cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1716cbe63bfdSIskren Chernev }, 1717cbe63bfdSIskren Chernev }, 1718cbe63bfdSIskren Chernev }; 1719cbe63bfdSIskren Chernev 1720cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_cphy_2_clk = { 1721cbe63bfdSIskren Chernev .halt_reg = 0x52090, 1722cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1723cbe63bfdSIskren Chernev .clkr = { 1724cbe63bfdSIskren Chernev .enable_reg = 0x52090, 1725cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1726cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1727cbe63bfdSIskren Chernev .name = "gcc_camss_cphy_2_clk", 1728cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1729cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1730cbe63bfdSIskren Chernev }, 1731cbe63bfdSIskren Chernev .num_parents = 1, 1732cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1733cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1734cbe63bfdSIskren Chernev }, 1735cbe63bfdSIskren Chernev }, 1736cbe63bfdSIskren Chernev }; 1737cbe63bfdSIskren Chernev 1738cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_csi0phytimer_clk = { 1739cbe63bfdSIskren Chernev .halt_reg = 0x59018, 1740cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1741cbe63bfdSIskren Chernev .clkr = { 1742cbe63bfdSIskren Chernev .enable_reg = 0x59018, 1743cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1744cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1745cbe63bfdSIskren Chernev .name = "gcc_camss_csi0phytimer_clk", 1746cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1747cbe63bfdSIskren Chernev &gcc_camss_csi0phytimer_clk_src.clkr.hw, 1748cbe63bfdSIskren Chernev }, 1749cbe63bfdSIskren Chernev .num_parents = 1, 1750cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1751cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1752cbe63bfdSIskren Chernev }, 1753cbe63bfdSIskren Chernev }, 1754cbe63bfdSIskren Chernev }; 1755cbe63bfdSIskren Chernev 1756cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_csi1phytimer_clk = { 1757cbe63bfdSIskren Chernev .halt_reg = 0x59034, 1758cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1759cbe63bfdSIskren Chernev .clkr = { 1760cbe63bfdSIskren Chernev .enable_reg = 0x59034, 1761cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1762cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1763cbe63bfdSIskren Chernev .name = "gcc_camss_csi1phytimer_clk", 1764cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1765cbe63bfdSIskren Chernev &gcc_camss_csi1phytimer_clk_src.clkr.hw, 1766cbe63bfdSIskren Chernev }, 1767cbe63bfdSIskren Chernev .num_parents = 1, 1768cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1769cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1770cbe63bfdSIskren Chernev }, 1771cbe63bfdSIskren Chernev }, 1772cbe63bfdSIskren Chernev }; 1773cbe63bfdSIskren Chernev 1774cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_csi2phytimer_clk = { 1775cbe63bfdSIskren Chernev .halt_reg = 0x59050, 1776cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1777cbe63bfdSIskren Chernev .clkr = { 1778cbe63bfdSIskren Chernev .enable_reg = 0x59050, 1779cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1780cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1781cbe63bfdSIskren Chernev .name = "gcc_camss_csi2phytimer_clk", 1782cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1783cbe63bfdSIskren Chernev &gcc_camss_csi2phytimer_clk_src.clkr.hw, 1784cbe63bfdSIskren Chernev }, 1785cbe63bfdSIskren Chernev .num_parents = 1, 1786cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1787cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1788cbe63bfdSIskren Chernev }, 1789cbe63bfdSIskren Chernev }, 1790cbe63bfdSIskren Chernev }; 1791cbe63bfdSIskren Chernev 1792cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_mclk0_clk = { 1793cbe63bfdSIskren Chernev .halt_reg = 0x51018, 1794cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1795cbe63bfdSIskren Chernev .clkr = { 1796cbe63bfdSIskren Chernev .enable_reg = 0x51018, 1797cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1798cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1799cbe63bfdSIskren Chernev .name = "gcc_camss_mclk0_clk", 1800cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1801cbe63bfdSIskren Chernev &gcc_camss_mclk0_clk_src.clkr.hw, 1802cbe63bfdSIskren Chernev }, 1803cbe63bfdSIskren Chernev .num_parents = 1, 1804cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1805cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1806cbe63bfdSIskren Chernev }, 1807cbe63bfdSIskren Chernev }, 1808cbe63bfdSIskren Chernev }; 1809cbe63bfdSIskren Chernev 1810cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_mclk1_clk = { 1811cbe63bfdSIskren Chernev .halt_reg = 0x51034, 1812cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1813cbe63bfdSIskren Chernev .clkr = { 1814cbe63bfdSIskren Chernev .enable_reg = 0x51034, 1815cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1816cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1817cbe63bfdSIskren Chernev .name = "gcc_camss_mclk1_clk", 1818cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1819cbe63bfdSIskren Chernev &gcc_camss_mclk1_clk_src.clkr.hw, 1820cbe63bfdSIskren Chernev }, 1821cbe63bfdSIskren Chernev .num_parents = 1, 1822cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1823cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1824cbe63bfdSIskren Chernev }, 1825cbe63bfdSIskren Chernev }, 1826cbe63bfdSIskren Chernev }; 1827cbe63bfdSIskren Chernev 1828cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_mclk2_clk = { 1829cbe63bfdSIskren Chernev .halt_reg = 0x51050, 1830cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1831cbe63bfdSIskren Chernev .clkr = { 1832cbe63bfdSIskren Chernev .enable_reg = 0x51050, 1833cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1834cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1835cbe63bfdSIskren Chernev .name = "gcc_camss_mclk2_clk", 1836cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1837cbe63bfdSIskren Chernev &gcc_camss_mclk2_clk_src.clkr.hw, 1838cbe63bfdSIskren Chernev }, 1839cbe63bfdSIskren Chernev .num_parents = 1, 1840cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1841cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1842cbe63bfdSIskren Chernev }, 1843cbe63bfdSIskren Chernev }, 1844cbe63bfdSIskren Chernev }; 1845cbe63bfdSIskren Chernev 1846cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_mclk3_clk = { 1847cbe63bfdSIskren Chernev .halt_reg = 0x5106c, 1848cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1849cbe63bfdSIskren Chernev .clkr = { 1850cbe63bfdSIskren Chernev .enable_reg = 0x5106c, 1851cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1852cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1853cbe63bfdSIskren Chernev .name = "gcc_camss_mclk3_clk", 1854cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1855cbe63bfdSIskren Chernev &gcc_camss_mclk3_clk_src.clkr.hw, 1856cbe63bfdSIskren Chernev }, 1857cbe63bfdSIskren Chernev .num_parents = 1, 1858cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1859cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1860cbe63bfdSIskren Chernev }, 1861cbe63bfdSIskren Chernev }, 1862cbe63bfdSIskren Chernev }; 1863cbe63bfdSIskren Chernev 1864cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_nrt_axi_clk = { 1865cbe63bfdSIskren Chernev .halt_reg = 0x58054, 1866cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1867cbe63bfdSIskren Chernev .clkr = { 1868cbe63bfdSIskren Chernev .enable_reg = 0x58054, 1869cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1870cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1871cbe63bfdSIskren Chernev .name = "gcc_camss_nrt_axi_clk", 1872cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1873cbe63bfdSIskren Chernev }, 1874cbe63bfdSIskren Chernev }, 1875cbe63bfdSIskren Chernev }; 1876cbe63bfdSIskren Chernev 1877cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_ope_ahb_clk = { 1878cbe63bfdSIskren Chernev .halt_reg = 0x5503c, 1879cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1880cbe63bfdSIskren Chernev .clkr = { 1881cbe63bfdSIskren Chernev .enable_reg = 0x5503c, 1882cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1883cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1884cbe63bfdSIskren Chernev .name = "gcc_camss_ope_ahb_clk", 1885cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1886cbe63bfdSIskren Chernev &gcc_camss_ope_ahb_clk_src.clkr.hw, 1887cbe63bfdSIskren Chernev }, 1888cbe63bfdSIskren Chernev .num_parents = 1, 1889cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1890cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1891cbe63bfdSIskren Chernev }, 1892cbe63bfdSIskren Chernev }, 1893cbe63bfdSIskren Chernev }; 1894cbe63bfdSIskren Chernev 1895cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_ope_clk = { 1896cbe63bfdSIskren Chernev .halt_reg = 0x5501c, 1897cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1898cbe63bfdSIskren Chernev .clkr = { 1899cbe63bfdSIskren Chernev .enable_reg = 0x5501c, 1900cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1901cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1902cbe63bfdSIskren Chernev .name = "gcc_camss_ope_clk", 1903cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1904cbe63bfdSIskren Chernev &gcc_camss_ope_clk_src.clkr.hw, 1905cbe63bfdSIskren Chernev }, 1906cbe63bfdSIskren Chernev .num_parents = 1, 1907cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1908cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1909cbe63bfdSIskren Chernev }, 1910cbe63bfdSIskren Chernev }, 1911cbe63bfdSIskren Chernev }; 1912cbe63bfdSIskren Chernev 1913cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_rt_axi_clk = { 1914cbe63bfdSIskren Chernev .halt_reg = 0x5805c, 1915cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1916cbe63bfdSIskren Chernev .clkr = { 1917cbe63bfdSIskren Chernev .enable_reg = 0x5805c, 1918cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1919cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1920cbe63bfdSIskren Chernev .name = "gcc_camss_rt_axi_clk", 1921cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1922cbe63bfdSIskren Chernev }, 1923cbe63bfdSIskren Chernev }, 1924cbe63bfdSIskren Chernev }; 1925cbe63bfdSIskren Chernev 1926cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_0_clk = { 1927cbe63bfdSIskren Chernev .halt_reg = 0x5201c, 1928cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1929cbe63bfdSIskren Chernev .clkr = { 1930cbe63bfdSIskren Chernev .enable_reg = 0x5201c, 1931cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1932cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1933cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_0_clk", 1934cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1935cbe63bfdSIskren Chernev &gcc_camss_tfe_0_clk_src.clkr.hw, 1936cbe63bfdSIskren Chernev }, 1937cbe63bfdSIskren Chernev .num_parents = 1, 1938cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1939cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1940cbe63bfdSIskren Chernev }, 1941cbe63bfdSIskren Chernev }, 1942cbe63bfdSIskren Chernev }; 1943cbe63bfdSIskren Chernev 1944cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = { 1945cbe63bfdSIskren Chernev .halt_reg = 0x5207c, 1946cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1947cbe63bfdSIskren Chernev .clkr = { 1948cbe63bfdSIskren Chernev .enable_reg = 0x5207c, 1949cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1950cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1951cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_0_cphy_rx_clk", 1952cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1953cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1954cbe63bfdSIskren Chernev }, 1955cbe63bfdSIskren Chernev .num_parents = 1, 1956cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1957cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1958cbe63bfdSIskren Chernev }, 1959cbe63bfdSIskren Chernev }, 1960cbe63bfdSIskren Chernev }; 1961cbe63bfdSIskren Chernev 1962cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_0_csid_clk = { 1963cbe63bfdSIskren Chernev .halt_reg = 0x520ac, 1964cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1965cbe63bfdSIskren Chernev .clkr = { 1966cbe63bfdSIskren Chernev .enable_reg = 0x520ac, 1967cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1968cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1969cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_0_csid_clk", 1970cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1971cbe63bfdSIskren Chernev &gcc_camss_tfe_0_csid_clk_src.clkr.hw, 1972cbe63bfdSIskren Chernev }, 1973cbe63bfdSIskren Chernev .num_parents = 1, 1974cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1975cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1976cbe63bfdSIskren Chernev }, 1977cbe63bfdSIskren Chernev }, 1978cbe63bfdSIskren Chernev }; 1979cbe63bfdSIskren Chernev 1980cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_1_clk = { 1981cbe63bfdSIskren Chernev .halt_reg = 0x5203c, 1982cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1983cbe63bfdSIskren Chernev .clkr = { 1984cbe63bfdSIskren Chernev .enable_reg = 0x5203c, 1985cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1986cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1987cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_1_clk", 1988cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1989cbe63bfdSIskren Chernev &gcc_camss_tfe_1_clk_src.clkr.hw, 1990cbe63bfdSIskren Chernev }, 1991cbe63bfdSIskren Chernev .num_parents = 1, 1992cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1993cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1994cbe63bfdSIskren Chernev }, 1995cbe63bfdSIskren Chernev }, 1996cbe63bfdSIskren Chernev }; 1997cbe63bfdSIskren Chernev 1998cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = { 1999cbe63bfdSIskren Chernev .halt_reg = 0x52080, 2000cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2001cbe63bfdSIskren Chernev .clkr = { 2002cbe63bfdSIskren Chernev .enable_reg = 0x52080, 2003cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2004cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2005cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_1_cphy_rx_clk", 2006cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2007cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2008cbe63bfdSIskren Chernev }, 2009cbe63bfdSIskren Chernev .num_parents = 1, 2010cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2011cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2012cbe63bfdSIskren Chernev }, 2013cbe63bfdSIskren Chernev }, 2014cbe63bfdSIskren Chernev }; 2015cbe63bfdSIskren Chernev 2016cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_1_csid_clk = { 2017cbe63bfdSIskren Chernev .halt_reg = 0x520cc, 2018cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2019cbe63bfdSIskren Chernev .clkr = { 2020cbe63bfdSIskren Chernev .enable_reg = 0x520cc, 2021cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2022cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2023cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_1_csid_clk", 2024cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2025cbe63bfdSIskren Chernev &gcc_camss_tfe_1_csid_clk_src.clkr.hw, 2026cbe63bfdSIskren Chernev }, 2027cbe63bfdSIskren Chernev .num_parents = 1, 2028cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2029cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2030cbe63bfdSIskren Chernev }, 2031cbe63bfdSIskren Chernev }, 2032cbe63bfdSIskren Chernev }; 2033cbe63bfdSIskren Chernev 2034cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_2_clk = { 2035cbe63bfdSIskren Chernev .halt_reg = 0x5205c, 2036cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2037cbe63bfdSIskren Chernev .clkr = { 2038cbe63bfdSIskren Chernev .enable_reg = 0x5205c, 2039cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2040cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2041cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_2_clk", 2042cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2043cbe63bfdSIskren Chernev &gcc_camss_tfe_2_clk_src.clkr.hw, 2044cbe63bfdSIskren Chernev }, 2045cbe63bfdSIskren Chernev .num_parents = 1, 2046cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2047cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2048cbe63bfdSIskren Chernev }, 2049cbe63bfdSIskren Chernev }, 2050cbe63bfdSIskren Chernev }; 2051cbe63bfdSIskren Chernev 2052cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_2_cphy_rx_clk = { 2053cbe63bfdSIskren Chernev .halt_reg = 0x52084, 2054cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2055cbe63bfdSIskren Chernev .clkr = { 2056cbe63bfdSIskren Chernev .enable_reg = 0x52084, 2057cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2058cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2059cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_2_cphy_rx_clk", 2060cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2061cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2062cbe63bfdSIskren Chernev }, 2063cbe63bfdSIskren Chernev .num_parents = 1, 2064cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2065cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2066cbe63bfdSIskren Chernev }, 2067cbe63bfdSIskren Chernev }, 2068cbe63bfdSIskren Chernev }; 2069cbe63bfdSIskren Chernev 2070cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_2_csid_clk = { 2071cbe63bfdSIskren Chernev .halt_reg = 0x520ec, 2072cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2073cbe63bfdSIskren Chernev .clkr = { 2074cbe63bfdSIskren Chernev .enable_reg = 0x520ec, 2075cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2076cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2077cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_2_csid_clk", 2078cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2079cbe63bfdSIskren Chernev &gcc_camss_tfe_2_csid_clk_src.clkr.hw, 2080cbe63bfdSIskren Chernev }, 2081cbe63bfdSIskren Chernev .num_parents = 1, 2082cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2083cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2084cbe63bfdSIskren Chernev }, 2085cbe63bfdSIskren Chernev }, 2086cbe63bfdSIskren Chernev }; 2087cbe63bfdSIskren Chernev 2088cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_top_ahb_clk = { 2089cbe63bfdSIskren Chernev .halt_reg = 0x58028, 2090cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2091cbe63bfdSIskren Chernev .clkr = { 2092cbe63bfdSIskren Chernev .enable_reg = 0x58028, 2093cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2094cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2095cbe63bfdSIskren Chernev .name = "gcc_camss_top_ahb_clk", 2096cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2097cbe63bfdSIskren Chernev &gcc_camss_top_ahb_clk_src.clkr.hw, 2098cbe63bfdSIskren Chernev }, 2099cbe63bfdSIskren Chernev .num_parents = 1, 2100cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2101cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2102cbe63bfdSIskren Chernev }, 2103cbe63bfdSIskren Chernev }, 2104cbe63bfdSIskren Chernev }; 2105cbe63bfdSIskren Chernev 2106cbe63bfdSIskren Chernev static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 2107cbe63bfdSIskren Chernev .halt_reg = 0x1a084, 2108cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2109cbe63bfdSIskren Chernev .hwcg_reg = 0x1a084, 2110cbe63bfdSIskren Chernev .hwcg_bit = 1, 2111cbe63bfdSIskren Chernev .clkr = { 2112cbe63bfdSIskren Chernev .enable_reg = 0x1a084, 2113cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2114cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2115cbe63bfdSIskren Chernev .name = "gcc_cfg_noc_usb3_prim_axi_clk", 2116cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2117cbe63bfdSIskren Chernev &gcc_usb30_prim_master_clk_src.clkr.hw, 2118cbe63bfdSIskren Chernev }, 2119cbe63bfdSIskren Chernev .num_parents = 1, 2120cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2121cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2122cbe63bfdSIskren Chernev }, 2123cbe63bfdSIskren Chernev }, 2124cbe63bfdSIskren Chernev }; 2125cbe63bfdSIskren Chernev 2126cbe63bfdSIskren Chernev static struct clk_branch gcc_cpuss_gnoc_clk = { 2127cbe63bfdSIskren Chernev .halt_reg = 0x2b004, 2128cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2129cbe63bfdSIskren Chernev .hwcg_reg = 0x2b004, 2130cbe63bfdSIskren Chernev .hwcg_bit = 1, 2131cbe63bfdSIskren Chernev .clkr = { 2132cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2133cbe63bfdSIskren Chernev .enable_mask = BIT(22), 2134cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2135cbe63bfdSIskren Chernev .name = "gcc_cpuss_gnoc_clk", 2136cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 2137cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2138cbe63bfdSIskren Chernev }, 2139cbe63bfdSIskren Chernev }, 2140cbe63bfdSIskren Chernev }; 2141cbe63bfdSIskren Chernev 2142cbe63bfdSIskren Chernev static struct clk_branch gcc_disp_ahb_clk = { 2143cbe63bfdSIskren Chernev .halt_reg = 0x1700c, 2144cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2145cbe63bfdSIskren Chernev .hwcg_reg = 0x1700c, 2146cbe63bfdSIskren Chernev .hwcg_bit = 1, 2147cbe63bfdSIskren Chernev .clkr = { 2148cbe63bfdSIskren Chernev .enable_reg = 0x1700c, 2149cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2150cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2151cbe63bfdSIskren Chernev .name = "gcc_disp_ahb_clk", 2152cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 2153cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2154cbe63bfdSIskren Chernev }, 2155cbe63bfdSIskren Chernev }, 2156cbe63bfdSIskren Chernev }; 2157cbe63bfdSIskren Chernev 2158cbe63bfdSIskren Chernev static struct clk_regmap_div gcc_disp_gpll0_clk_src = { 2159cbe63bfdSIskren Chernev .reg = 0x17058, 2160cbe63bfdSIskren Chernev .shift = 0, 2161cbe63bfdSIskren Chernev .width = 2, 2162cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data) { 2163cbe63bfdSIskren Chernev .name = "gcc_disp_gpll0_clk_src", 2164cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 2165cbe63bfdSIskren Chernev .num_parents = 1, 2166cbe63bfdSIskren Chernev .ops = &clk_regmap_div_ops, 2167cbe63bfdSIskren Chernev }, 2168cbe63bfdSIskren Chernev }; 2169cbe63bfdSIskren Chernev 2170cbe63bfdSIskren Chernev static struct clk_branch gcc_disp_gpll0_div_clk_src = { 2171cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 2172cbe63bfdSIskren Chernev .clkr = { 2173cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2174cbe63bfdSIskren Chernev .enable_mask = BIT(20), 2175cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2176cbe63bfdSIskren Chernev .name = "gcc_disp_gpll0_div_clk_src", 2177cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2178cbe63bfdSIskren Chernev &gcc_disp_gpll0_clk_src.clkr.hw, 2179cbe63bfdSIskren Chernev }, 2180cbe63bfdSIskren Chernev .num_parents = 1, 2181cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2182cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2183cbe63bfdSIskren Chernev }, 2184cbe63bfdSIskren Chernev }, 2185cbe63bfdSIskren Chernev }; 2186cbe63bfdSIskren Chernev 2187cbe63bfdSIskren Chernev static struct clk_branch gcc_disp_hf_axi_clk = { 2188cbe63bfdSIskren Chernev .halt_reg = 0x17020, 2189cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2190cbe63bfdSIskren Chernev .hwcg_reg = 0x17020, 2191cbe63bfdSIskren Chernev .hwcg_bit = 1, 2192cbe63bfdSIskren Chernev .clkr = { 2193cbe63bfdSIskren Chernev .enable_reg = 0x17020, 2194cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2195cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2196cbe63bfdSIskren Chernev .name = "gcc_disp_hf_axi_clk", 2197cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2198cbe63bfdSIskren Chernev }, 2199cbe63bfdSIskren Chernev }, 2200cbe63bfdSIskren Chernev }; 2201cbe63bfdSIskren Chernev 2202cbe63bfdSIskren Chernev static struct clk_branch gcc_disp_throttle_core_clk = { 2203cbe63bfdSIskren Chernev .halt_reg = 0x17064, 2204cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2205cbe63bfdSIskren Chernev .hwcg_reg = 0x17064, 2206cbe63bfdSIskren Chernev .hwcg_bit = 1, 2207cbe63bfdSIskren Chernev .clkr = { 2208cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2209cbe63bfdSIskren Chernev .enable_mask = BIT(5), 2210cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2211cbe63bfdSIskren Chernev .name = "gcc_disp_throttle_core_clk", 2212cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2213cbe63bfdSIskren Chernev }, 2214cbe63bfdSIskren Chernev }, 2215cbe63bfdSIskren Chernev }; 2216cbe63bfdSIskren Chernev 2217cbe63bfdSIskren Chernev static struct clk_branch gcc_disp_xo_clk = { 2218cbe63bfdSIskren Chernev .halt_reg = 0x1702c, 2219cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2220cbe63bfdSIskren Chernev .clkr = { 2221cbe63bfdSIskren Chernev .enable_reg = 0x1702c, 2222cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2223cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2224cbe63bfdSIskren Chernev .name = "gcc_disp_xo_clk", 2225cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 2226cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2227cbe63bfdSIskren Chernev }, 2228cbe63bfdSIskren Chernev }, 2229cbe63bfdSIskren Chernev }; 2230cbe63bfdSIskren Chernev 2231cbe63bfdSIskren Chernev static struct clk_branch gcc_gp1_clk = { 2232cbe63bfdSIskren Chernev .halt_reg = 0x4d000, 2233cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2234cbe63bfdSIskren Chernev .clkr = { 2235cbe63bfdSIskren Chernev .enable_reg = 0x4d000, 2236cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2237cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2238cbe63bfdSIskren Chernev .name = "gcc_gp1_clk", 2239cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2240cbe63bfdSIskren Chernev &gcc_gp1_clk_src.clkr.hw, 2241cbe63bfdSIskren Chernev }, 2242cbe63bfdSIskren Chernev .num_parents = 1, 2243cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2244cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2245cbe63bfdSIskren Chernev }, 2246cbe63bfdSIskren Chernev }, 2247cbe63bfdSIskren Chernev }; 2248cbe63bfdSIskren Chernev 2249cbe63bfdSIskren Chernev static struct clk_branch gcc_gp2_clk = { 2250cbe63bfdSIskren Chernev .halt_reg = 0x4e000, 2251cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2252cbe63bfdSIskren Chernev .clkr = { 2253cbe63bfdSIskren Chernev .enable_reg = 0x4e000, 2254cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2255cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2256cbe63bfdSIskren Chernev .name = "gcc_gp2_clk", 2257cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2258cbe63bfdSIskren Chernev &gcc_gp2_clk_src.clkr.hw, 2259cbe63bfdSIskren Chernev }, 2260cbe63bfdSIskren Chernev .num_parents = 1, 2261cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2262cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2263cbe63bfdSIskren Chernev }, 2264cbe63bfdSIskren Chernev }, 2265cbe63bfdSIskren Chernev }; 2266cbe63bfdSIskren Chernev 2267cbe63bfdSIskren Chernev static struct clk_branch gcc_gp3_clk = { 2268cbe63bfdSIskren Chernev .halt_reg = 0x4f000, 2269cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2270cbe63bfdSIskren Chernev .clkr = { 2271cbe63bfdSIskren Chernev .enable_reg = 0x4f000, 2272cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2273cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2274cbe63bfdSIskren Chernev .name = "gcc_gp3_clk", 2275cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2276cbe63bfdSIskren Chernev &gcc_gp3_clk_src.clkr.hw, 2277cbe63bfdSIskren Chernev }, 2278cbe63bfdSIskren Chernev .num_parents = 1, 2279cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2280cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2281cbe63bfdSIskren Chernev }, 2282cbe63bfdSIskren Chernev }, 2283cbe63bfdSIskren Chernev }; 2284cbe63bfdSIskren Chernev 2285cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_cfg_ahb_clk = { 2286cbe63bfdSIskren Chernev .halt_reg = 0x36004, 2287cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2288cbe63bfdSIskren Chernev .hwcg_reg = 0x36004, 2289cbe63bfdSIskren Chernev .hwcg_bit = 1, 2290cbe63bfdSIskren Chernev .clkr = { 2291cbe63bfdSIskren Chernev .enable_reg = 0x36004, 2292cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2293cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2294cbe63bfdSIskren Chernev .name = "gcc_gpu_cfg_ahb_clk", 2295cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 2296cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2297cbe63bfdSIskren Chernev }, 2298cbe63bfdSIskren Chernev }, 2299cbe63bfdSIskren Chernev }; 2300cbe63bfdSIskren Chernev 2301cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_gpll0_clk_src = { 2302cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 2303cbe63bfdSIskren Chernev .clkr = { 2304cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2305cbe63bfdSIskren Chernev .enable_mask = BIT(15), 2306cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2307cbe63bfdSIskren Chernev .name = "gcc_gpu_gpll0_clk_src", 2308cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2309cbe63bfdSIskren Chernev &gpll0.clkr.hw, 2310cbe63bfdSIskren Chernev }, 2311cbe63bfdSIskren Chernev .num_parents = 1, 2312cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2313cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2314cbe63bfdSIskren Chernev }, 2315cbe63bfdSIskren Chernev }, 2316cbe63bfdSIskren Chernev }; 2317cbe63bfdSIskren Chernev 2318cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 2319cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 2320cbe63bfdSIskren Chernev .clkr = { 2321cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2322cbe63bfdSIskren Chernev .enable_mask = BIT(16), 2323cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2324cbe63bfdSIskren Chernev .name = "gcc_gpu_gpll0_div_clk_src", 2325cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2326cbe63bfdSIskren Chernev &gpll0_out_aux2.clkr.hw, 2327cbe63bfdSIskren Chernev }, 2328cbe63bfdSIskren Chernev .num_parents = 1, 2329cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2330cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2331cbe63bfdSIskren Chernev }, 2332cbe63bfdSIskren Chernev }, 2333cbe63bfdSIskren Chernev }; 2334cbe63bfdSIskren Chernev 2335cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_iref_clk = { 2336cbe63bfdSIskren Chernev .halt_reg = 0x36100, 2337cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 2338cbe63bfdSIskren Chernev .clkr = { 2339cbe63bfdSIskren Chernev .enable_reg = 0x36100, 2340cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2341cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2342cbe63bfdSIskren Chernev .name = "gcc_gpu_iref_clk", 2343cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2344cbe63bfdSIskren Chernev }, 2345cbe63bfdSIskren Chernev }, 2346cbe63bfdSIskren Chernev }; 2347cbe63bfdSIskren Chernev 2348cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 2349cbe63bfdSIskren Chernev .halt_reg = 0x3600c, 2350cbe63bfdSIskren Chernev .halt_check = BRANCH_VOTED, 2351cbe63bfdSIskren Chernev .hwcg_reg = 0x3600c, 2352cbe63bfdSIskren Chernev .hwcg_bit = 1, 2353cbe63bfdSIskren Chernev .clkr = { 2354cbe63bfdSIskren Chernev .enable_reg = 0x3600c, 2355cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2356cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2357cbe63bfdSIskren Chernev .name = "gcc_gpu_memnoc_gfx_clk", 2358cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2359cbe63bfdSIskren Chernev }, 2360cbe63bfdSIskren Chernev }, 2361cbe63bfdSIskren Chernev }; 2362cbe63bfdSIskren Chernev 2363cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2364cbe63bfdSIskren Chernev .halt_reg = 0x36018, 2365cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2366cbe63bfdSIskren Chernev .clkr = { 2367cbe63bfdSIskren Chernev .enable_reg = 0x36018, 2368cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2369cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2370cbe63bfdSIskren Chernev .name = "gcc_gpu_snoc_dvm_gfx_clk", 2371cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2372cbe63bfdSIskren Chernev }, 2373cbe63bfdSIskren Chernev }, 2374cbe63bfdSIskren Chernev }; 2375cbe63bfdSIskren Chernev 2376cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_throttle_core_clk = { 2377cbe63bfdSIskren Chernev .halt_reg = 0x36048, 2378cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2379cbe63bfdSIskren Chernev .hwcg_reg = 0x36048, 2380cbe63bfdSIskren Chernev .hwcg_bit = 1, 2381cbe63bfdSIskren Chernev .clkr = { 2382cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2383cbe63bfdSIskren Chernev .enable_mask = BIT(31), 2384cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2385cbe63bfdSIskren Chernev .name = "gcc_gpu_throttle_core_clk", 2386cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2387cbe63bfdSIskren Chernev }, 2388cbe63bfdSIskren Chernev }, 2389cbe63bfdSIskren Chernev }; 2390cbe63bfdSIskren Chernev 2391cbe63bfdSIskren Chernev static struct clk_branch gcc_pdm2_clk = { 2392cbe63bfdSIskren Chernev .halt_reg = 0x2000c, 2393cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2394cbe63bfdSIskren Chernev .clkr = { 2395cbe63bfdSIskren Chernev .enable_reg = 0x2000c, 2396cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2397cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2398cbe63bfdSIskren Chernev .name = "gcc_pdm2_clk", 2399cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2400cbe63bfdSIskren Chernev &gcc_pdm2_clk_src.clkr.hw, 2401cbe63bfdSIskren Chernev }, 2402cbe63bfdSIskren Chernev .num_parents = 1, 2403cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2404cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2405cbe63bfdSIskren Chernev }, 2406cbe63bfdSIskren Chernev }, 2407cbe63bfdSIskren Chernev }; 2408cbe63bfdSIskren Chernev 2409cbe63bfdSIskren Chernev static struct clk_branch gcc_pdm_ahb_clk = { 2410cbe63bfdSIskren Chernev .halt_reg = 0x20004, 2411cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2412cbe63bfdSIskren Chernev .hwcg_reg = 0x20004, 2413cbe63bfdSIskren Chernev .hwcg_bit = 1, 2414cbe63bfdSIskren Chernev .clkr = { 2415cbe63bfdSIskren Chernev .enable_reg = 0x20004, 2416cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2417cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2418cbe63bfdSIskren Chernev .name = "gcc_pdm_ahb_clk", 2419cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2420cbe63bfdSIskren Chernev }, 2421cbe63bfdSIskren Chernev }, 2422cbe63bfdSIskren Chernev }; 2423cbe63bfdSIskren Chernev 2424cbe63bfdSIskren Chernev static struct clk_branch gcc_pdm_xo4_clk = { 2425cbe63bfdSIskren Chernev .halt_reg = 0x20008, 2426cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2427cbe63bfdSIskren Chernev .clkr = { 2428cbe63bfdSIskren Chernev .enable_reg = 0x20008, 2429cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2430cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2431cbe63bfdSIskren Chernev .name = "gcc_pdm_xo4_clk", 2432cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2433cbe63bfdSIskren Chernev }, 2434cbe63bfdSIskren Chernev }, 2435cbe63bfdSIskren Chernev }; 2436cbe63bfdSIskren Chernev 2437cbe63bfdSIskren Chernev static struct clk_branch gcc_prng_ahb_clk = { 2438cbe63bfdSIskren Chernev .halt_reg = 0x21004, 2439cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2440cbe63bfdSIskren Chernev .hwcg_reg = 0x21004, 2441cbe63bfdSIskren Chernev .hwcg_bit = 1, 2442cbe63bfdSIskren Chernev .clkr = { 2443cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2444cbe63bfdSIskren Chernev .enable_mask = BIT(13), 2445cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2446cbe63bfdSIskren Chernev .name = "gcc_prng_ahb_clk", 2447cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2448cbe63bfdSIskren Chernev }, 2449cbe63bfdSIskren Chernev }, 2450cbe63bfdSIskren Chernev }; 2451cbe63bfdSIskren Chernev 2452cbe63bfdSIskren Chernev static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2453cbe63bfdSIskren Chernev .halt_reg = 0x17014, 2454cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2455cbe63bfdSIskren Chernev .hwcg_reg = 0x17014, 2456cbe63bfdSIskren Chernev .hwcg_bit = 1, 2457cbe63bfdSIskren Chernev .clkr = { 2458cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2459cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2460cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2461cbe63bfdSIskren Chernev .name = "gcc_qmip_camera_nrt_ahb_clk", 2462cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2463cbe63bfdSIskren Chernev }, 2464cbe63bfdSIskren Chernev }, 2465cbe63bfdSIskren Chernev }; 2466cbe63bfdSIskren Chernev 2467cbe63bfdSIskren Chernev static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2468cbe63bfdSIskren Chernev .halt_reg = 0x17060, 2469cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2470cbe63bfdSIskren Chernev .hwcg_reg = 0x17060, 2471cbe63bfdSIskren Chernev .hwcg_bit = 1, 2472cbe63bfdSIskren Chernev .clkr = { 2473cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2474cbe63bfdSIskren Chernev .enable_mask = BIT(2), 2475cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2476cbe63bfdSIskren Chernev .name = "gcc_qmip_camera_rt_ahb_clk", 2477cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2478cbe63bfdSIskren Chernev }, 2479cbe63bfdSIskren Chernev }, 2480cbe63bfdSIskren Chernev }; 2481cbe63bfdSIskren Chernev 2482cbe63bfdSIskren Chernev static struct clk_branch gcc_qmip_disp_ahb_clk = { 2483cbe63bfdSIskren Chernev .halt_reg = 0x17018, 2484cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2485cbe63bfdSIskren Chernev .hwcg_reg = 0x17018, 2486cbe63bfdSIskren Chernev .hwcg_bit = 1, 2487cbe63bfdSIskren Chernev .clkr = { 2488cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2489cbe63bfdSIskren Chernev .enable_mask = BIT(1), 2490cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2491cbe63bfdSIskren Chernev .name = "gcc_qmip_disp_ahb_clk", 2492cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2493cbe63bfdSIskren Chernev }, 2494cbe63bfdSIskren Chernev }, 2495cbe63bfdSIskren Chernev }; 2496cbe63bfdSIskren Chernev 2497cbe63bfdSIskren Chernev static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = { 2498cbe63bfdSIskren Chernev .halt_reg = 0x36040, 2499cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2500cbe63bfdSIskren Chernev .hwcg_reg = 0x36040, 2501cbe63bfdSIskren Chernev .hwcg_bit = 1, 2502cbe63bfdSIskren Chernev .clkr = { 2503cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2504cbe63bfdSIskren Chernev .enable_mask = BIT(4), 2505cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2506cbe63bfdSIskren Chernev .name = "gcc_qmip_gpu_cfg_ahb_clk", 2507cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2508cbe63bfdSIskren Chernev }, 2509cbe63bfdSIskren Chernev }, 2510cbe63bfdSIskren Chernev }; 2511cbe63bfdSIskren Chernev 2512cbe63bfdSIskren Chernev static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2513cbe63bfdSIskren Chernev .halt_reg = 0x17010, 2514cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2515cbe63bfdSIskren Chernev .hwcg_reg = 0x17010, 2516cbe63bfdSIskren Chernev .hwcg_bit = 1, 2517cbe63bfdSIskren Chernev .clkr = { 2518cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2519cbe63bfdSIskren Chernev .enable_mask = BIT(25), 2520cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2521cbe63bfdSIskren Chernev .name = "gcc_qmip_video_vcodec_ahb_clk", 2522cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2523cbe63bfdSIskren Chernev }, 2524cbe63bfdSIskren Chernev }, 2525cbe63bfdSIskren Chernev }; 2526cbe63bfdSIskren Chernev 2527cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2528cbe63bfdSIskren Chernev .halt_reg = 0x1f014, 2529cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2530cbe63bfdSIskren Chernev .clkr = { 2531cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2532cbe63bfdSIskren Chernev .enable_mask = BIT(9), 2533cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2534cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_core_2x_clk", 2535cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2536cbe63bfdSIskren Chernev }, 2537cbe63bfdSIskren Chernev }, 2538cbe63bfdSIskren Chernev }; 2539cbe63bfdSIskren Chernev 2540cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2541cbe63bfdSIskren Chernev .halt_reg = 0x1f00c, 2542cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2543cbe63bfdSIskren Chernev .clkr = { 2544cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2545cbe63bfdSIskren Chernev .enable_mask = BIT(8), 2546cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2547cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_core_clk", 2548cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2549cbe63bfdSIskren Chernev }, 2550cbe63bfdSIskren Chernev }, 2551cbe63bfdSIskren Chernev }; 2552cbe63bfdSIskren Chernev 2553cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2554cbe63bfdSIskren Chernev .halt_reg = 0x1f144, 2555cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2556cbe63bfdSIskren Chernev .clkr = { 2557cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2558cbe63bfdSIskren Chernev .enable_mask = BIT(10), 2559cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2560cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s0_clk", 2561cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2562cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 2563cbe63bfdSIskren Chernev }, 2564cbe63bfdSIskren Chernev .num_parents = 1, 2565cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2566cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2567cbe63bfdSIskren Chernev }, 2568cbe63bfdSIskren Chernev }, 2569cbe63bfdSIskren Chernev }; 2570cbe63bfdSIskren Chernev 2571cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2572cbe63bfdSIskren Chernev .halt_reg = 0x1f274, 2573cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2574cbe63bfdSIskren Chernev .clkr = { 2575cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2576cbe63bfdSIskren Chernev .enable_mask = BIT(11), 2577cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2578cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s1_clk", 2579cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2580cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 2581cbe63bfdSIskren Chernev }, 2582cbe63bfdSIskren Chernev .num_parents = 1, 2583cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2584cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2585cbe63bfdSIskren Chernev }, 2586cbe63bfdSIskren Chernev }, 2587cbe63bfdSIskren Chernev }; 2588cbe63bfdSIskren Chernev 2589cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2590cbe63bfdSIskren Chernev .halt_reg = 0x1f3a4, 2591cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2592cbe63bfdSIskren Chernev .clkr = { 2593cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2594cbe63bfdSIskren Chernev .enable_mask = BIT(12), 2595cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2596cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s2_clk", 2597cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2598cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2599cbe63bfdSIskren Chernev }, 2600cbe63bfdSIskren Chernev .num_parents = 1, 2601cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2602cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2603cbe63bfdSIskren Chernev }, 2604cbe63bfdSIskren Chernev }, 2605cbe63bfdSIskren Chernev }; 2606cbe63bfdSIskren Chernev 2607cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2608cbe63bfdSIskren Chernev .halt_reg = 0x1f4d4, 2609cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2610cbe63bfdSIskren Chernev .clkr = { 2611cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2612cbe63bfdSIskren Chernev .enable_mask = BIT(13), 2613cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2614cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s3_clk", 2615cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2616cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2617cbe63bfdSIskren Chernev }, 2618cbe63bfdSIskren Chernev .num_parents = 1, 2619cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2620cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2621cbe63bfdSIskren Chernev }, 2622cbe63bfdSIskren Chernev }, 2623cbe63bfdSIskren Chernev }; 2624cbe63bfdSIskren Chernev 2625cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2626cbe63bfdSIskren Chernev .halt_reg = 0x1f604, 2627cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2628cbe63bfdSIskren Chernev .clkr = { 2629cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2630cbe63bfdSIskren Chernev .enable_mask = BIT(14), 2631cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2632cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s4_clk", 2633cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2634cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2635cbe63bfdSIskren Chernev }, 2636cbe63bfdSIskren Chernev .num_parents = 1, 2637cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2638cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2639cbe63bfdSIskren Chernev }, 2640cbe63bfdSIskren Chernev }, 2641cbe63bfdSIskren Chernev }; 2642cbe63bfdSIskren Chernev 2643cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2644cbe63bfdSIskren Chernev .halt_reg = 0x1f734, 2645cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2646cbe63bfdSIskren Chernev .clkr = { 2647cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2648cbe63bfdSIskren Chernev .enable_mask = BIT(15), 2649cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2650cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s5_clk", 2651cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2652cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2653cbe63bfdSIskren Chernev }, 2654cbe63bfdSIskren Chernev .num_parents = 1, 2655cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2656cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2657cbe63bfdSIskren Chernev }, 2658cbe63bfdSIskren Chernev }, 2659cbe63bfdSIskren Chernev }; 2660cbe63bfdSIskren Chernev 2661cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2662cbe63bfdSIskren Chernev .halt_reg = 0x1f004, 2663cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2664cbe63bfdSIskren Chernev .hwcg_reg = 0x1f004, 2665cbe63bfdSIskren Chernev .hwcg_bit = 1, 2666cbe63bfdSIskren Chernev .clkr = { 2667cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2668cbe63bfdSIskren Chernev .enable_mask = BIT(6), 2669cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2670cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2671cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2672cbe63bfdSIskren Chernev }, 2673cbe63bfdSIskren Chernev }, 2674cbe63bfdSIskren Chernev }; 2675cbe63bfdSIskren Chernev 2676cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2677cbe63bfdSIskren Chernev .halt_reg = 0x1f008, 2678cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2679cbe63bfdSIskren Chernev .hwcg_reg = 0x1f008, 2680cbe63bfdSIskren Chernev .hwcg_bit = 1, 2681cbe63bfdSIskren Chernev .clkr = { 2682cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2683cbe63bfdSIskren Chernev .enable_mask = BIT(7), 2684cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2685cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2686cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2687cbe63bfdSIskren Chernev }, 2688cbe63bfdSIskren Chernev }, 2689cbe63bfdSIskren Chernev }; 2690cbe63bfdSIskren Chernev 2691cbe63bfdSIskren Chernev static struct clk_branch gcc_sdcc1_ahb_clk = { 2692cbe63bfdSIskren Chernev .halt_reg = 0x38008, 2693cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2694cbe63bfdSIskren Chernev .clkr = { 2695cbe63bfdSIskren Chernev .enable_reg = 0x38008, 2696cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2697cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2698cbe63bfdSIskren Chernev .name = "gcc_sdcc1_ahb_clk", 2699cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2700cbe63bfdSIskren Chernev }, 2701cbe63bfdSIskren Chernev }, 2702cbe63bfdSIskren Chernev }; 2703cbe63bfdSIskren Chernev 2704cbe63bfdSIskren Chernev static struct clk_branch gcc_sdcc1_apps_clk = { 2705cbe63bfdSIskren Chernev .halt_reg = 0x38004, 2706cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2707cbe63bfdSIskren Chernev .clkr = { 2708cbe63bfdSIskren Chernev .enable_reg = 0x38004, 2709cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2710cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2711cbe63bfdSIskren Chernev .name = "gcc_sdcc1_apps_clk", 2712cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2713cbe63bfdSIskren Chernev &gcc_sdcc1_apps_clk_src.clkr.hw, 2714cbe63bfdSIskren Chernev }, 2715cbe63bfdSIskren Chernev .num_parents = 1, 2716cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT /* | CLK_ENABLE_HAND_OFF */, 2717cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2718cbe63bfdSIskren Chernev }, 2719cbe63bfdSIskren Chernev }, 2720cbe63bfdSIskren Chernev }; 2721cbe63bfdSIskren Chernev 2722cbe63bfdSIskren Chernev static struct clk_branch gcc_sdcc1_ice_core_clk = { 2723cbe63bfdSIskren Chernev .halt_reg = 0x3800c, 2724cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2725cbe63bfdSIskren Chernev .hwcg_reg = 0x3800c, 2726cbe63bfdSIskren Chernev .hwcg_bit = 1, 2727cbe63bfdSIskren Chernev .clkr = { 2728cbe63bfdSIskren Chernev .enable_reg = 0x3800c, 2729cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2730cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2731cbe63bfdSIskren Chernev .name = "gcc_sdcc1_ice_core_clk", 2732cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2733cbe63bfdSIskren Chernev &gcc_sdcc1_ice_core_clk_src.clkr.hw, 2734cbe63bfdSIskren Chernev }, 2735cbe63bfdSIskren Chernev .num_parents = 1, 2736cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2737cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2738cbe63bfdSIskren Chernev }, 2739cbe63bfdSIskren Chernev }, 2740cbe63bfdSIskren Chernev }; 2741cbe63bfdSIskren Chernev 2742cbe63bfdSIskren Chernev static struct clk_branch gcc_sdcc2_ahb_clk = { 2743cbe63bfdSIskren Chernev .halt_reg = 0x1e008, 2744cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2745cbe63bfdSIskren Chernev .clkr = { 2746cbe63bfdSIskren Chernev .enable_reg = 0x1e008, 2747cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2748cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2749cbe63bfdSIskren Chernev .name = "gcc_sdcc2_ahb_clk", 2750cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2751cbe63bfdSIskren Chernev }, 2752cbe63bfdSIskren Chernev }, 2753cbe63bfdSIskren Chernev }; 2754cbe63bfdSIskren Chernev 2755cbe63bfdSIskren Chernev static struct clk_branch gcc_sdcc2_apps_clk = { 2756cbe63bfdSIskren Chernev .halt_reg = 0x1e004, 2757cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2758cbe63bfdSIskren Chernev .clkr = { 2759cbe63bfdSIskren Chernev .enable_reg = 0x1e004, 2760cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2761cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2762cbe63bfdSIskren Chernev .name = "gcc_sdcc2_apps_clk", 2763cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2764cbe63bfdSIskren Chernev &gcc_sdcc2_apps_clk_src.clkr.hw, 2765cbe63bfdSIskren Chernev }, 2766cbe63bfdSIskren Chernev .num_parents = 1, 2767cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2768cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2769cbe63bfdSIskren Chernev }, 2770cbe63bfdSIskren Chernev }, 2771cbe63bfdSIskren Chernev }; 2772cbe63bfdSIskren Chernev 2773cbe63bfdSIskren Chernev static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 2774cbe63bfdSIskren Chernev .halt_reg = 0x2b06c, 2775cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2776cbe63bfdSIskren Chernev .hwcg_reg = 0x2b06c, 2777cbe63bfdSIskren Chernev .hwcg_bit = 1, 2778cbe63bfdSIskren Chernev .clkr = { 2779cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2780cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2781cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2782cbe63bfdSIskren Chernev .name = "gcc_sys_noc_cpuss_ahb_clk", 2783cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 2784cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2785cbe63bfdSIskren Chernev }, 2786cbe63bfdSIskren Chernev }, 2787cbe63bfdSIskren Chernev }; 2788cbe63bfdSIskren Chernev 2789cbe63bfdSIskren Chernev static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { 2790cbe63bfdSIskren Chernev .halt_reg = 0x45098, 2791cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2792cbe63bfdSIskren Chernev .clkr = { 2793cbe63bfdSIskren Chernev .enable_reg = 0x45098, 2794cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2795cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2796cbe63bfdSIskren Chernev .name = "gcc_sys_noc_ufs_phy_axi_clk", 2797cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2798cbe63bfdSIskren Chernev &gcc_ufs_phy_axi_clk_src.clkr.hw, 2799cbe63bfdSIskren Chernev }, 2800cbe63bfdSIskren Chernev .num_parents = 1, 2801cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2802cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2803cbe63bfdSIskren Chernev }, 2804cbe63bfdSIskren Chernev }, 2805cbe63bfdSIskren Chernev }; 2806cbe63bfdSIskren Chernev 2807cbe63bfdSIskren Chernev static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { 2808cbe63bfdSIskren Chernev .halt_reg = 0x1a080, 2809cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2810cbe63bfdSIskren Chernev .hwcg_reg = 0x1a080, 2811cbe63bfdSIskren Chernev .hwcg_bit = 1, 2812cbe63bfdSIskren Chernev .clkr = { 2813cbe63bfdSIskren Chernev .enable_reg = 0x1a080, 2814cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2815cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2816cbe63bfdSIskren Chernev .name = "gcc_sys_noc_usb3_prim_axi_clk", 2817cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2818cbe63bfdSIskren Chernev &gcc_usb30_prim_master_clk_src.clkr.hw, 2819cbe63bfdSIskren Chernev }, 2820cbe63bfdSIskren Chernev .num_parents = 1, 2821cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2822cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2823cbe63bfdSIskren Chernev }, 2824cbe63bfdSIskren Chernev }, 2825cbe63bfdSIskren Chernev }; 2826cbe63bfdSIskren Chernev 2827cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_clkref_clk = { 2828cbe63bfdSIskren Chernev .halt_reg = 0x8c000, 2829cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2830cbe63bfdSIskren Chernev .clkr = { 2831cbe63bfdSIskren Chernev .enable_reg = 0x8c000, 2832cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2833cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2834cbe63bfdSIskren Chernev .name = "gcc_ufs_clkref_clk", 2835cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2836cbe63bfdSIskren Chernev }, 2837cbe63bfdSIskren Chernev }, 2838cbe63bfdSIskren Chernev }; 2839cbe63bfdSIskren Chernev 2840cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_ahb_clk = { 2841cbe63bfdSIskren Chernev .halt_reg = 0x45014, 2842cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2843cbe63bfdSIskren Chernev .hwcg_reg = 0x45014, 2844cbe63bfdSIskren Chernev .hwcg_bit = 1, 2845cbe63bfdSIskren Chernev .clkr = { 2846cbe63bfdSIskren Chernev .enable_reg = 0x45014, 2847cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2848cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2849cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_ahb_clk", 2850cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2851cbe63bfdSIskren Chernev }, 2852cbe63bfdSIskren Chernev }, 2853cbe63bfdSIskren Chernev }; 2854cbe63bfdSIskren Chernev 2855cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_axi_clk = { 2856cbe63bfdSIskren Chernev .halt_reg = 0x45010, 2857cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2858cbe63bfdSIskren Chernev .hwcg_reg = 0x45010, 2859cbe63bfdSIskren Chernev .hwcg_bit = 1, 2860cbe63bfdSIskren Chernev .clkr = { 2861cbe63bfdSIskren Chernev .enable_reg = 0x45010, 2862cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2863cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2864cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_axi_clk", 2865cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2866cbe63bfdSIskren Chernev &gcc_ufs_phy_axi_clk_src.clkr.hw, 2867cbe63bfdSIskren Chernev }, 2868cbe63bfdSIskren Chernev .num_parents = 1, 2869cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2870cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2871cbe63bfdSIskren Chernev }, 2872cbe63bfdSIskren Chernev }, 2873cbe63bfdSIskren Chernev }; 2874cbe63bfdSIskren Chernev 2875cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2876cbe63bfdSIskren Chernev .halt_reg = 0x45044, 2877cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2878cbe63bfdSIskren Chernev .hwcg_reg = 0x45044, 2879cbe63bfdSIskren Chernev .hwcg_bit = 1, 2880cbe63bfdSIskren Chernev .clkr = { 2881cbe63bfdSIskren Chernev .enable_reg = 0x45044, 2882cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2883cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2884cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_ice_core_clk", 2885cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2886cbe63bfdSIskren Chernev &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2887cbe63bfdSIskren Chernev }, 2888cbe63bfdSIskren Chernev .num_parents = 1, 2889cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2890cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2891cbe63bfdSIskren Chernev }, 2892cbe63bfdSIskren Chernev }, 2893cbe63bfdSIskren Chernev }; 2894cbe63bfdSIskren Chernev 2895cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2896cbe63bfdSIskren Chernev .halt_reg = 0x45078, 2897cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2898cbe63bfdSIskren Chernev .hwcg_reg = 0x45078, 2899cbe63bfdSIskren Chernev .hwcg_bit = 1, 2900cbe63bfdSIskren Chernev .clkr = { 2901cbe63bfdSIskren Chernev .enable_reg = 0x45078, 2902cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2903cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2904cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_phy_aux_clk", 2905cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2906cbe63bfdSIskren Chernev &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2907cbe63bfdSIskren Chernev }, 2908cbe63bfdSIskren Chernev .num_parents = 1, 2909cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2910cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2911cbe63bfdSIskren Chernev }, 2912cbe63bfdSIskren Chernev }, 2913cbe63bfdSIskren Chernev }; 2914cbe63bfdSIskren Chernev 2915cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2916cbe63bfdSIskren Chernev .halt_reg = 0x4501c, 2917cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_SKIP, 2918cbe63bfdSIskren Chernev .clkr = { 2919cbe63bfdSIskren Chernev .enable_reg = 0x4501c, 2920cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2921cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2922cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_rx_symbol_0_clk", 2923cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2924cbe63bfdSIskren Chernev }, 2925cbe63bfdSIskren Chernev }, 2926cbe63bfdSIskren Chernev }; 2927cbe63bfdSIskren Chernev 2928cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2929cbe63bfdSIskren Chernev .halt_reg = 0x45018, 2930cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_SKIP, 2931cbe63bfdSIskren Chernev .clkr = { 2932cbe63bfdSIskren Chernev .enable_reg = 0x45018, 2933cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2934cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2935cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_tx_symbol_0_clk", 2936cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2937cbe63bfdSIskren Chernev }, 2938cbe63bfdSIskren Chernev }, 2939cbe63bfdSIskren Chernev }; 2940cbe63bfdSIskren Chernev 2941cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2942cbe63bfdSIskren Chernev .halt_reg = 0x45040, 2943cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2944cbe63bfdSIskren Chernev .hwcg_reg = 0x45040, 2945cbe63bfdSIskren Chernev .hwcg_bit = 1, 2946cbe63bfdSIskren Chernev .clkr = { 2947cbe63bfdSIskren Chernev .enable_reg = 0x45040, 2948cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2949cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2950cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_unipro_core_clk", 2951cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2952cbe63bfdSIskren Chernev &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2953cbe63bfdSIskren Chernev }, 2954cbe63bfdSIskren Chernev .num_parents = 1, 2955cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2956cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2957cbe63bfdSIskren Chernev }, 2958cbe63bfdSIskren Chernev }, 2959cbe63bfdSIskren Chernev }; 2960cbe63bfdSIskren Chernev 2961cbe63bfdSIskren Chernev static struct clk_branch gcc_usb30_prim_master_clk = { 2962cbe63bfdSIskren Chernev .halt_reg = 0x1a010, 2963cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2964cbe63bfdSIskren Chernev .clkr = { 2965cbe63bfdSIskren Chernev .enable_reg = 0x1a010, 2966cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2967cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2968cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_master_clk", 2969cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2970cbe63bfdSIskren Chernev &gcc_usb30_prim_master_clk_src.clkr.hw, 2971cbe63bfdSIskren Chernev }, 2972cbe63bfdSIskren Chernev .num_parents = 1, 2973cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2974cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2975cbe63bfdSIskren Chernev }, 2976cbe63bfdSIskren Chernev }, 2977cbe63bfdSIskren Chernev }; 2978cbe63bfdSIskren Chernev 2979cbe63bfdSIskren Chernev static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2980cbe63bfdSIskren Chernev .halt_reg = 0x1a018, 2981cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2982cbe63bfdSIskren Chernev .clkr = { 2983cbe63bfdSIskren Chernev .enable_reg = 0x1a018, 2984cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2985cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2986cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_mock_utmi_clk", 2987cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2988cbe63bfdSIskren Chernev &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2989cbe63bfdSIskren Chernev }, 2990cbe63bfdSIskren Chernev .num_parents = 1, 2991cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2992cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2993cbe63bfdSIskren Chernev }, 2994cbe63bfdSIskren Chernev }, 2995cbe63bfdSIskren Chernev }; 2996cbe63bfdSIskren Chernev 2997cbe63bfdSIskren Chernev static struct clk_branch gcc_usb30_prim_sleep_clk = { 2998cbe63bfdSIskren Chernev .halt_reg = 0x1a014, 2999cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3000cbe63bfdSIskren Chernev .clkr = { 3001cbe63bfdSIskren Chernev .enable_reg = 0x1a014, 3002cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3003cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3004cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_sleep_clk", 3005cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3006cbe63bfdSIskren Chernev }, 3007cbe63bfdSIskren Chernev }, 3008cbe63bfdSIskren Chernev }; 3009cbe63bfdSIskren Chernev 3010cbe63bfdSIskren Chernev static struct clk_branch gcc_usb3_prim_clkref_clk = { 3011cbe63bfdSIskren Chernev .halt_reg = 0x9f000, 3012cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3013cbe63bfdSIskren Chernev .clkr = { 3014cbe63bfdSIskren Chernev .enable_reg = 0x9f000, 3015cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3016cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3017cbe63bfdSIskren Chernev .name = "gcc_usb3_prim_clkref_clk", 3018cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3019cbe63bfdSIskren Chernev }, 3020cbe63bfdSIskren Chernev }, 3021cbe63bfdSIskren Chernev }; 3022cbe63bfdSIskren Chernev 3023cbe63bfdSIskren Chernev static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3024cbe63bfdSIskren Chernev .halt_reg = 0x1a054, 3025cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3026cbe63bfdSIskren Chernev .clkr = { 3027cbe63bfdSIskren Chernev .enable_reg = 0x1a054, 3028cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3029cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3030cbe63bfdSIskren Chernev .name = "gcc_usb3_prim_phy_com_aux_clk", 3031cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 3032cbe63bfdSIskren Chernev &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3033cbe63bfdSIskren Chernev }, 3034cbe63bfdSIskren Chernev .num_parents = 1, 3035cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 3036cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3037cbe63bfdSIskren Chernev }, 3038cbe63bfdSIskren Chernev }, 3039cbe63bfdSIskren Chernev }; 3040cbe63bfdSIskren Chernev 3041cbe63bfdSIskren Chernev static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3042cbe63bfdSIskren Chernev .halt_reg = 0x1a058, 3043cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_SKIP, 3044cbe63bfdSIskren Chernev .hwcg_reg = 0x1a058, 3045cbe63bfdSIskren Chernev .hwcg_bit = 1, 3046cbe63bfdSIskren Chernev .clkr = { 3047cbe63bfdSIskren Chernev .enable_reg = 0x1a058, 3048cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3049cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3050cbe63bfdSIskren Chernev .name = "gcc_usb3_prim_phy_pipe_clk", 3051cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3052cbe63bfdSIskren Chernev }, 3053cbe63bfdSIskren Chernev }, 3054cbe63bfdSIskren Chernev }; 3055cbe63bfdSIskren Chernev 3056cbe63bfdSIskren Chernev static struct clk_branch gcc_vcodec0_axi_clk = { 3057cbe63bfdSIskren Chernev .halt_reg = 0x6e008, 3058cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3059cbe63bfdSIskren Chernev .clkr = { 3060cbe63bfdSIskren Chernev .enable_reg = 0x6e008, 3061cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3062cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3063cbe63bfdSIskren Chernev .name = "gcc_vcodec0_axi_clk", 3064cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3065cbe63bfdSIskren Chernev }, 3066cbe63bfdSIskren Chernev }, 3067cbe63bfdSIskren Chernev }; 3068cbe63bfdSIskren Chernev 3069cbe63bfdSIskren Chernev static struct clk_branch gcc_venus_ahb_clk = { 3070cbe63bfdSIskren Chernev .halt_reg = 0x6e010, 3071cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3072cbe63bfdSIskren Chernev .clkr = { 3073cbe63bfdSIskren Chernev .enable_reg = 0x6e010, 3074cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3075cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3076cbe63bfdSIskren Chernev .name = "gcc_venus_ahb_clk", 3077cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3078cbe63bfdSIskren Chernev }, 3079cbe63bfdSIskren Chernev }, 3080cbe63bfdSIskren Chernev }; 3081cbe63bfdSIskren Chernev 3082cbe63bfdSIskren Chernev static struct clk_branch gcc_venus_ctl_axi_clk = { 3083cbe63bfdSIskren Chernev .halt_reg = 0x6e004, 3084cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3085cbe63bfdSIskren Chernev .clkr = { 3086cbe63bfdSIskren Chernev .enable_reg = 0x6e004, 3087cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3088cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3089cbe63bfdSIskren Chernev .name = "gcc_venus_ctl_axi_clk", 3090cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3091cbe63bfdSIskren Chernev }, 3092cbe63bfdSIskren Chernev }, 3093cbe63bfdSIskren Chernev }; 3094cbe63bfdSIskren Chernev 3095cbe63bfdSIskren Chernev static struct clk_branch gcc_video_ahb_clk = { 3096cbe63bfdSIskren Chernev .halt_reg = 0x17004, 3097cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3098cbe63bfdSIskren Chernev .hwcg_reg = 0x17004, 3099cbe63bfdSIskren Chernev .hwcg_bit = 1, 3100cbe63bfdSIskren Chernev .clkr = { 3101cbe63bfdSIskren Chernev .enable_reg = 0x17004, 3102cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3103cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3104cbe63bfdSIskren Chernev .name = "gcc_video_ahb_clk", 3105cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3106cbe63bfdSIskren Chernev }, 3107cbe63bfdSIskren Chernev }, 3108cbe63bfdSIskren Chernev }; 3109cbe63bfdSIskren Chernev 3110cbe63bfdSIskren Chernev static struct clk_branch gcc_video_axi0_clk = { 3111cbe63bfdSIskren Chernev .halt_reg = 0x1701c, 3112cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3113cbe63bfdSIskren Chernev .hwcg_reg = 0x1701c, 3114cbe63bfdSIskren Chernev .hwcg_bit = 1, 3115cbe63bfdSIskren Chernev .clkr = { 3116cbe63bfdSIskren Chernev .enable_reg = 0x1701c, 3117cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3118cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3119cbe63bfdSIskren Chernev .name = "gcc_video_axi0_clk", 3120cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3121cbe63bfdSIskren Chernev }, 3122cbe63bfdSIskren Chernev }, 3123cbe63bfdSIskren Chernev }; 3124cbe63bfdSIskren Chernev 3125cbe63bfdSIskren Chernev static struct clk_branch gcc_video_throttle_core_clk = { 3126cbe63bfdSIskren Chernev .halt_reg = 0x17068, 3127cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 3128cbe63bfdSIskren Chernev .hwcg_reg = 0x17068, 3129cbe63bfdSIskren Chernev .hwcg_bit = 1, 3130cbe63bfdSIskren Chernev .clkr = { 3131cbe63bfdSIskren Chernev .enable_reg = 0x79004, 3132cbe63bfdSIskren Chernev .enable_mask = BIT(28), 3133cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3134cbe63bfdSIskren Chernev .name = "gcc_video_throttle_core_clk", 3135cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3136cbe63bfdSIskren Chernev }, 3137cbe63bfdSIskren Chernev }, 3138cbe63bfdSIskren Chernev }; 3139cbe63bfdSIskren Chernev 3140cbe63bfdSIskren Chernev static struct clk_branch gcc_video_vcodec0_sys_clk = { 3141cbe63bfdSIskren Chernev .halt_reg = 0x580a4, 3142cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 3143cbe63bfdSIskren Chernev .hwcg_reg = 0x580a4, 3144cbe63bfdSIskren Chernev .hwcg_bit = 1, 3145cbe63bfdSIskren Chernev .clkr = { 3146cbe63bfdSIskren Chernev .enable_reg = 0x580a4, 3147cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3148cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3149cbe63bfdSIskren Chernev .name = "gcc_video_vcodec0_sys_clk", 3150cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 3151cbe63bfdSIskren Chernev &gcc_video_venus_clk_src.clkr.hw, 3152cbe63bfdSIskren Chernev }, 3153cbe63bfdSIskren Chernev .num_parents = 1, 3154cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 3155cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3156cbe63bfdSIskren Chernev }, 3157cbe63bfdSIskren Chernev }, 3158cbe63bfdSIskren Chernev }; 3159cbe63bfdSIskren Chernev 3160cbe63bfdSIskren Chernev static struct clk_branch gcc_video_venus_ctl_clk = { 3161cbe63bfdSIskren Chernev .halt_reg = 0x5808c, 3162cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3163cbe63bfdSIskren Chernev .clkr = { 3164cbe63bfdSIskren Chernev .enable_reg = 0x5808c, 3165cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3166cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3167cbe63bfdSIskren Chernev .name = "gcc_video_venus_ctl_clk", 3168cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 3169cbe63bfdSIskren Chernev &gcc_video_venus_clk_src.clkr.hw, 3170cbe63bfdSIskren Chernev }, 3171cbe63bfdSIskren Chernev .num_parents = 1, 3172cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 3173cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3174cbe63bfdSIskren Chernev }, 3175cbe63bfdSIskren Chernev }, 3176cbe63bfdSIskren Chernev }; 3177cbe63bfdSIskren Chernev 3178cbe63bfdSIskren Chernev static struct clk_branch gcc_video_xo_clk = { 3179cbe63bfdSIskren Chernev .halt_reg = 0x17024, 3180cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3181cbe63bfdSIskren Chernev .clkr = { 3182cbe63bfdSIskren Chernev .enable_reg = 0x17024, 3183cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3184cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3185cbe63bfdSIskren Chernev .name = "gcc_video_xo_clk", 3186cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3187cbe63bfdSIskren Chernev }, 3188cbe63bfdSIskren Chernev }, 3189cbe63bfdSIskren Chernev }; 3190cbe63bfdSIskren Chernev 3191cbe63bfdSIskren Chernev static struct gdsc gcc_camss_top_gdsc = { 3192cbe63bfdSIskren Chernev .gdscr = 0x58004, 3193cbe63bfdSIskren Chernev .pd = { 3194cbe63bfdSIskren Chernev .name = "gcc_camss_top", 3195cbe63bfdSIskren Chernev }, 3196cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3197cbe63bfdSIskren Chernev }; 3198cbe63bfdSIskren Chernev 3199cbe63bfdSIskren Chernev static struct gdsc gcc_ufs_phy_gdsc = { 3200cbe63bfdSIskren Chernev .gdscr = 0x45004, 3201cbe63bfdSIskren Chernev .pd = { 3202cbe63bfdSIskren Chernev .name = "gcc_ufs_phy", 3203cbe63bfdSIskren Chernev }, 3204cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3205cbe63bfdSIskren Chernev }; 3206cbe63bfdSIskren Chernev 3207cbe63bfdSIskren Chernev static struct gdsc gcc_usb30_prim_gdsc = { 3208cbe63bfdSIskren Chernev .gdscr = 0x1a004, 3209cbe63bfdSIskren Chernev .pd = { 3210cbe63bfdSIskren Chernev .name = "gcc_usb30_prim", 3211cbe63bfdSIskren Chernev }, 3212cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3213cbe63bfdSIskren Chernev }; 3214cbe63bfdSIskren Chernev 3215cbe63bfdSIskren Chernev static struct gdsc gcc_vcodec0_gdsc = { 3216cbe63bfdSIskren Chernev .gdscr = 0x58098, 3217cbe63bfdSIskren Chernev .pd = { 3218cbe63bfdSIskren Chernev .name = "gcc_vcodec0", 3219cbe63bfdSIskren Chernev }, 3220cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3221cbe63bfdSIskren Chernev }; 3222cbe63bfdSIskren Chernev 3223cbe63bfdSIskren Chernev static struct gdsc gcc_venus_gdsc = { 3224cbe63bfdSIskren Chernev .gdscr = 0x5807c, 3225cbe63bfdSIskren Chernev .pd = { 3226cbe63bfdSIskren Chernev .name = "gcc_venus", 3227cbe63bfdSIskren Chernev }, 3228cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3229cbe63bfdSIskren Chernev }; 3230cbe63bfdSIskren Chernev 3231cbe63bfdSIskren Chernev static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = { 3232cbe63bfdSIskren Chernev .gdscr = 0x7d060, 3233cbe63bfdSIskren Chernev .pd = { 3234cbe63bfdSIskren Chernev .name = "hlos1_vote_turing_mmu_tbu1", 3235cbe63bfdSIskren Chernev }, 3236cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3237cbe63bfdSIskren Chernev .flags = VOTABLE, 3238cbe63bfdSIskren Chernev }; 3239cbe63bfdSIskren Chernev 3240cbe63bfdSIskren Chernev static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { 3241e41bdd18SShawn Guo .gdscr = 0x7d07c, 3242cbe63bfdSIskren Chernev .pd = { 3243cbe63bfdSIskren Chernev .name = "hlos1_vote_turing_mmu_tbu0", 3244cbe63bfdSIskren Chernev }, 3245cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3246cbe63bfdSIskren Chernev .flags = VOTABLE, 3247cbe63bfdSIskren Chernev }; 3248cbe63bfdSIskren Chernev 3249cbe63bfdSIskren Chernev static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = { 3250cbe63bfdSIskren Chernev .gdscr = 0x7d074, 3251cbe63bfdSIskren Chernev .pd = { 3252cbe63bfdSIskren Chernev .name = "hlos1_vote_mm_snoc_mmu_tbu_rt", 3253cbe63bfdSIskren Chernev }, 3254cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3255cbe63bfdSIskren Chernev .flags = VOTABLE, 3256cbe63bfdSIskren Chernev }; 3257cbe63bfdSIskren Chernev 3258cbe63bfdSIskren Chernev static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = { 3259cbe63bfdSIskren Chernev .gdscr = 0x7d078, 3260cbe63bfdSIskren Chernev .pd = { 3261cbe63bfdSIskren Chernev .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt", 3262cbe63bfdSIskren Chernev }, 3263cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3264cbe63bfdSIskren Chernev .flags = VOTABLE, 3265cbe63bfdSIskren Chernev }; 3266cbe63bfdSIskren Chernev 3267cbe63bfdSIskren Chernev static struct clk_regmap *gcc_sm6115_clocks[] = { 3268cbe63bfdSIskren Chernev [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr, 3269cbe63bfdSIskren Chernev [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr, 3270cbe63bfdSIskren Chernev [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr, 3271cbe63bfdSIskren Chernev [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3272cbe63bfdSIskren Chernev [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, 3273cbe63bfdSIskren Chernev [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, 3274cbe63bfdSIskren Chernev [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 3275cbe63bfdSIskren Chernev [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 3276cbe63bfdSIskren Chernev [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, 3277cbe63bfdSIskren Chernev [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, 3278cbe63bfdSIskren Chernev [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr, 3279cbe63bfdSIskren Chernev [GCC_CAMSS_CAMNOC_NTS_XO_CLK] = &gcc_camss_camnoc_nts_xo_clk.clkr, 3280cbe63bfdSIskren Chernev [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr, 3281cbe63bfdSIskren Chernev [GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr, 3282cbe63bfdSIskren Chernev [GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr, 3283cbe63bfdSIskren Chernev [GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr, 3284cbe63bfdSIskren Chernev [GCC_CAMSS_CPHY_2_CLK] = &gcc_camss_cphy_2_clk.clkr, 3285cbe63bfdSIskren Chernev [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 3286cbe63bfdSIskren Chernev [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr, 3287cbe63bfdSIskren Chernev [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, 3288cbe63bfdSIskren Chernev [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr, 3289cbe63bfdSIskren Chernev [GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr, 3290cbe63bfdSIskren Chernev [GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr, 3291cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 3292cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr, 3293cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 3294cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr, 3295cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, 3296cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr, 3297cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr, 3298cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr, 3299cbe63bfdSIskren Chernev [GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr, 3300cbe63bfdSIskren Chernev [GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr, 3301cbe63bfdSIskren Chernev [GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr, 3302cbe63bfdSIskren Chernev [GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr, 3303cbe63bfdSIskren Chernev [GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr, 3304cbe63bfdSIskren Chernev [GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr, 3305cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr, 3306cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr, 3307cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr, 3308cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr, 3309cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr, 3310cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr, 3311cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr, 3312cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr, 3313cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr, 3314cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr, 3315cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_2_CLK] = &gcc_camss_tfe_2_clk.clkr, 3316cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_2_CLK_SRC] = &gcc_camss_tfe_2_clk_src.clkr, 3317cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_2_CPHY_RX_CLK] = &gcc_camss_tfe_2_cphy_rx_clk.clkr, 3318cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_2_CSID_CLK] = &gcc_camss_tfe_2_csid_clk.clkr, 3319cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_2_CSID_CLK_SRC] = &gcc_camss_tfe_2_csid_clk_src.clkr, 3320cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr, 3321cbe63bfdSIskren Chernev [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 3322cbe63bfdSIskren Chernev [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, 3323cbe63bfdSIskren Chernev [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3324cbe63bfdSIskren Chernev [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, 3325cbe63bfdSIskren Chernev [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, 3326cbe63bfdSIskren Chernev [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 3327cbe63bfdSIskren Chernev [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 3328cbe63bfdSIskren Chernev [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3329cbe63bfdSIskren Chernev [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, 3330cbe63bfdSIskren Chernev [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 3331cbe63bfdSIskren Chernev [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3332cbe63bfdSIskren Chernev [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3333cbe63bfdSIskren Chernev [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3334cbe63bfdSIskren Chernev [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3335cbe63bfdSIskren Chernev [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3336cbe63bfdSIskren Chernev [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3337cbe63bfdSIskren Chernev [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 3338cbe63bfdSIskren Chernev [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3339cbe63bfdSIskren Chernev [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3340cbe63bfdSIskren Chernev [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, 3341cbe63bfdSIskren Chernev [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3342cbe63bfdSIskren Chernev [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3343cbe63bfdSIskren Chernev [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, 3344cbe63bfdSIskren Chernev [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3345cbe63bfdSIskren Chernev [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3346cbe63bfdSIskren Chernev [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3347cbe63bfdSIskren Chernev [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3348cbe63bfdSIskren Chernev [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3349cbe63bfdSIskren Chernev [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3350cbe63bfdSIskren Chernev [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3351cbe63bfdSIskren Chernev [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3352cbe63bfdSIskren Chernev [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr, 3353cbe63bfdSIskren Chernev [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3354cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 3355cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 3356cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3357cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3358cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3359cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3360cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3361cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3362cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3363cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3364cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3365cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3366cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3367cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3368cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3369cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3370cbe63bfdSIskren Chernev [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3371cbe63bfdSIskren Chernev [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3372cbe63bfdSIskren Chernev [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 3373cbe63bfdSIskren Chernev [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 3374cbe63bfdSIskren Chernev [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 3375cbe63bfdSIskren Chernev [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3376cbe63bfdSIskren Chernev [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3377cbe63bfdSIskren Chernev [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3378cbe63bfdSIskren Chernev [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 3379cbe63bfdSIskren Chernev [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, 3380cbe63bfdSIskren Chernev [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, 3381cbe63bfdSIskren Chernev [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, 3382cbe63bfdSIskren Chernev [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3383cbe63bfdSIskren Chernev [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3384cbe63bfdSIskren Chernev [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3385cbe63bfdSIskren Chernev [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3386cbe63bfdSIskren Chernev [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3387cbe63bfdSIskren Chernev [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3388cbe63bfdSIskren Chernev [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3389cbe63bfdSIskren Chernev [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3390cbe63bfdSIskren Chernev [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3391cbe63bfdSIskren Chernev [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3392cbe63bfdSIskren Chernev [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 3393cbe63bfdSIskren Chernev &gcc_ufs_phy_unipro_core_clk_src.clkr, 3394cbe63bfdSIskren Chernev [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3395cbe63bfdSIskren Chernev [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3396cbe63bfdSIskren Chernev [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3397cbe63bfdSIskren Chernev [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 3398cbe63bfdSIskren Chernev &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3399cbe63bfdSIskren Chernev [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = 3400cbe63bfdSIskren Chernev &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3401cbe63bfdSIskren Chernev [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3402cbe63bfdSIskren Chernev [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 3403cbe63bfdSIskren Chernev [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3404cbe63bfdSIskren Chernev [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3405cbe63bfdSIskren Chernev [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3406cbe63bfdSIskren Chernev [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr, 3407cbe63bfdSIskren Chernev [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr, 3408cbe63bfdSIskren Chernev [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr, 3409cbe63bfdSIskren Chernev [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 3410cbe63bfdSIskren Chernev [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3411cbe63bfdSIskren Chernev [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, 3412cbe63bfdSIskren Chernev [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr, 3413cbe63bfdSIskren Chernev [GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr, 3414cbe63bfdSIskren Chernev [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr, 3415cbe63bfdSIskren Chernev [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 3416cbe63bfdSIskren Chernev [GPLL0] = &gpll0.clkr, 3417cbe63bfdSIskren Chernev [GPLL0_OUT_AUX2] = &gpll0_out_aux2.clkr, 3418cbe63bfdSIskren Chernev [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr, 3419cbe63bfdSIskren Chernev [GPLL10] = &gpll10.clkr, 3420cbe63bfdSIskren Chernev [GPLL10_OUT_MAIN] = &gpll10_out_main.clkr, 3421cbe63bfdSIskren Chernev [GPLL11] = &gpll11.clkr, 3422cbe63bfdSIskren Chernev [GPLL11_OUT_MAIN] = &gpll11_out_main.clkr, 3423cbe63bfdSIskren Chernev [GPLL3] = &gpll3.clkr, 3424cbe63bfdSIskren Chernev [GPLL4] = &gpll4.clkr, 3425cbe63bfdSIskren Chernev [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr, 3426cbe63bfdSIskren Chernev [GPLL6] = &gpll6.clkr, 3427cbe63bfdSIskren Chernev [GPLL6_OUT_MAIN] = &gpll6_out_main.clkr, 3428cbe63bfdSIskren Chernev [GPLL7] = &gpll7.clkr, 3429cbe63bfdSIskren Chernev [GPLL7_OUT_MAIN] = &gpll7_out_main.clkr, 3430cbe63bfdSIskren Chernev [GPLL8] = &gpll8.clkr, 3431cbe63bfdSIskren Chernev [GPLL8_OUT_MAIN] = &gpll8_out_main.clkr, 3432cbe63bfdSIskren Chernev [GPLL9] = &gpll9.clkr, 3433cbe63bfdSIskren Chernev [GPLL9_OUT_MAIN] = &gpll9_out_main.clkr, 3434cbe63bfdSIskren Chernev }; 3435cbe63bfdSIskren Chernev 3436cbe63bfdSIskren Chernev static const struct qcom_reset_map gcc_sm6115_resets[] = { 3437cbe63bfdSIskren Chernev [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, 3438cbe63bfdSIskren Chernev [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, 3439cbe63bfdSIskren Chernev [GCC_SDCC1_BCR] = { 0x38000 }, 3440cbe63bfdSIskren Chernev [GCC_SDCC2_BCR] = { 0x1e000 }, 3441cbe63bfdSIskren Chernev [GCC_UFS_PHY_BCR] = { 0x45000 }, 3442cbe63bfdSIskren Chernev [GCC_USB30_PRIM_BCR] = { 0x1a000 }, 3443cbe63bfdSIskren Chernev [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, 3444cbe63bfdSIskren Chernev [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, 3445cbe63bfdSIskren Chernev [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, 3446cbe63bfdSIskren Chernev [GCC_VCODEC0_BCR] = { 0x58094 }, 3447cbe63bfdSIskren Chernev [GCC_VENUS_BCR] = { 0x58078 }, 3448cbe63bfdSIskren Chernev [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 }, 3449cbe63bfdSIskren Chernev }; 3450cbe63bfdSIskren Chernev 3451cbe63bfdSIskren Chernev static struct gdsc *gcc_sm6115_gdscs[] = { 3452cbe63bfdSIskren Chernev [GCC_CAMSS_TOP_GDSC] = &gcc_camss_top_gdsc, 3453cbe63bfdSIskren Chernev [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, 3454cbe63bfdSIskren Chernev [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 3455cbe63bfdSIskren Chernev [GCC_VCODEC0_GDSC] = &gcc_vcodec0_gdsc, 3456cbe63bfdSIskren Chernev [GCC_VENUS_GDSC] = &gcc_venus_gdsc, 3457cbe63bfdSIskren Chernev [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, 3458cbe63bfdSIskren Chernev [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc, 3459cbe63bfdSIskren Chernev [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc, 3460cbe63bfdSIskren Chernev [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc, 3461cbe63bfdSIskren Chernev }; 3462cbe63bfdSIskren Chernev 3463cbe63bfdSIskren Chernev static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3464cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3465cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3466cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3467cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3468cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3469cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3470cbe63bfdSIskren Chernev }; 3471cbe63bfdSIskren Chernev 3472cbe63bfdSIskren Chernev static const struct regmap_config gcc_sm6115_regmap_config = { 3473cbe63bfdSIskren Chernev .reg_bits = 32, 3474cbe63bfdSIskren Chernev .reg_stride = 4, 3475cbe63bfdSIskren Chernev .val_bits = 32, 3476cbe63bfdSIskren Chernev .max_register = 0xc7000, 3477cbe63bfdSIskren Chernev .fast_io = true, 3478cbe63bfdSIskren Chernev }; 3479cbe63bfdSIskren Chernev 3480cbe63bfdSIskren Chernev static const struct qcom_cc_desc gcc_sm6115_desc = { 3481cbe63bfdSIskren Chernev .config = &gcc_sm6115_regmap_config, 3482cbe63bfdSIskren Chernev .clks = gcc_sm6115_clocks, 3483cbe63bfdSIskren Chernev .num_clks = ARRAY_SIZE(gcc_sm6115_clocks), 3484cbe63bfdSIskren Chernev .resets = gcc_sm6115_resets, 3485cbe63bfdSIskren Chernev .num_resets = ARRAY_SIZE(gcc_sm6115_resets), 3486cbe63bfdSIskren Chernev .gdscs = gcc_sm6115_gdscs, 3487cbe63bfdSIskren Chernev .num_gdscs = ARRAY_SIZE(gcc_sm6115_gdscs), 3488cbe63bfdSIskren Chernev }; 3489cbe63bfdSIskren Chernev 3490cbe63bfdSIskren Chernev static const struct of_device_id gcc_sm6115_match_table[] = { 3491cbe63bfdSIskren Chernev { .compatible = "qcom,gcc-sm6115" }, 3492cbe63bfdSIskren Chernev { } 3493cbe63bfdSIskren Chernev }; 3494cbe63bfdSIskren Chernev MODULE_DEVICE_TABLE(of, gcc_sm6115_match_table); 3495cbe63bfdSIskren Chernev 3496cbe63bfdSIskren Chernev static int gcc_sm6115_probe(struct platform_device *pdev) 3497cbe63bfdSIskren Chernev { 3498cbe63bfdSIskren Chernev struct regmap *regmap; 3499cbe63bfdSIskren Chernev int ret; 3500cbe63bfdSIskren Chernev 3501cbe63bfdSIskren Chernev regmap = qcom_cc_map(pdev, &gcc_sm6115_desc); 3502cbe63bfdSIskren Chernev if (IS_ERR(regmap)) 3503cbe63bfdSIskren Chernev return PTR_ERR(regmap); 3504cbe63bfdSIskren Chernev 3505cbe63bfdSIskren Chernev ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3506cbe63bfdSIskren Chernev ARRAY_SIZE(gcc_dfs_clocks)); 3507cbe63bfdSIskren Chernev if (ret) 3508cbe63bfdSIskren Chernev return ret; 3509cbe63bfdSIskren Chernev 3510cbe63bfdSIskren Chernev clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config); 3511cbe63bfdSIskren Chernev clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config); 3512cbe63bfdSIskren Chernev clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config); 3513cbe63bfdSIskren Chernev clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config); 3514cbe63bfdSIskren Chernev 3515cbe63bfdSIskren Chernev return qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap); 3516cbe63bfdSIskren Chernev } 3517cbe63bfdSIskren Chernev 3518cbe63bfdSIskren Chernev static struct platform_driver gcc_sm6115_driver = { 3519cbe63bfdSIskren Chernev .probe = gcc_sm6115_probe, 3520cbe63bfdSIskren Chernev .driver = { 3521cbe63bfdSIskren Chernev .name = "gcc-sm6115", 3522cbe63bfdSIskren Chernev .of_match_table = gcc_sm6115_match_table, 3523cbe63bfdSIskren Chernev }, 3524cbe63bfdSIskren Chernev }; 3525cbe63bfdSIskren Chernev 3526cbe63bfdSIskren Chernev static int __init gcc_sm6115_init(void) 3527cbe63bfdSIskren Chernev { 3528cbe63bfdSIskren Chernev return platform_driver_register(&gcc_sm6115_driver); 3529cbe63bfdSIskren Chernev } 3530cbe63bfdSIskren Chernev subsys_initcall(gcc_sm6115_init); 3531cbe63bfdSIskren Chernev 3532cbe63bfdSIskren Chernev static void __exit gcc_sm6115_exit(void) 3533cbe63bfdSIskren Chernev { 3534cbe63bfdSIskren Chernev platform_driver_unregister(&gcc_sm6115_driver); 3535cbe63bfdSIskren Chernev } 3536cbe63bfdSIskren Chernev module_exit(gcc_sm6115_exit); 3537cbe63bfdSIskren Chernev 3538cbe63bfdSIskren Chernev MODULE_DESCRIPTION("QTI GCC SM6115 and SM4250 Driver"); 3539cbe63bfdSIskren Chernev MODULE_LICENSE("GPL v2"); 3540cbe63bfdSIskren Chernev MODULE_ALIAS("platform:gcc-sm6115"); 3541