1cbe63bfdSIskren Chernev // SPDX-License-Identifier: GPL-2.0-only 2cbe63bfdSIskren Chernev /* 3cbe63bfdSIskren Chernev * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. 4cbe63bfdSIskren Chernev */ 5cbe63bfdSIskren Chernev 6cbe63bfdSIskren Chernev #include <linux/err.h> 7cbe63bfdSIskren Chernev #include <linux/kernel.h> 8cbe63bfdSIskren Chernev #include <linux/module.h> 9cbe63bfdSIskren Chernev #include <linux/of_device.h> 10cbe63bfdSIskren Chernev #include <linux/clk-provider.h> 11cbe63bfdSIskren Chernev #include <linux/regmap.h> 12cbe63bfdSIskren Chernev #include <linux/reset-controller.h> 13cbe63bfdSIskren Chernev 14cbe63bfdSIskren Chernev #include <dt-bindings/clock/qcom,gcc-sm6115.h> 15cbe63bfdSIskren Chernev 16cbe63bfdSIskren Chernev #include "clk-alpha-pll.h" 17cbe63bfdSIskren Chernev #include "clk-branch.h" 18cbe63bfdSIskren Chernev #include "clk-pll.h" 19cbe63bfdSIskren Chernev #include "clk-rcg.h" 20cbe63bfdSIskren Chernev #include "clk-regmap.h" 21cbe63bfdSIskren Chernev #include "clk-regmap-divider.h" 22cbe63bfdSIskren Chernev #include "common.h" 23cbe63bfdSIskren Chernev #include "gdsc.h" 24cbe63bfdSIskren Chernev #include "reset.h" 25cbe63bfdSIskren Chernev 26cbe63bfdSIskren Chernev enum { 27cbe63bfdSIskren Chernev P_BI_TCXO, 28cbe63bfdSIskren Chernev P_GPLL0_OUT_AUX2, 29cbe63bfdSIskren Chernev P_GPLL0_OUT_EARLY, 30cbe63bfdSIskren Chernev P_GPLL10_OUT_MAIN, 31cbe63bfdSIskren Chernev P_GPLL11_OUT_MAIN, 32cbe63bfdSIskren Chernev P_GPLL3_OUT_EARLY, 33cbe63bfdSIskren Chernev P_GPLL4_OUT_MAIN, 34cbe63bfdSIskren Chernev P_GPLL6_OUT_EARLY, 35cbe63bfdSIskren Chernev P_GPLL6_OUT_MAIN, 36cbe63bfdSIskren Chernev P_GPLL7_OUT_MAIN, 37cbe63bfdSIskren Chernev P_GPLL8_OUT_EARLY, 38cbe63bfdSIskren Chernev P_GPLL8_OUT_MAIN, 39cbe63bfdSIskren Chernev P_GPLL9_OUT_EARLY, 40cbe63bfdSIskren Chernev P_GPLL9_OUT_MAIN, 41cbe63bfdSIskren Chernev P_SLEEP_CLK, 42cbe63bfdSIskren Chernev }; 43cbe63bfdSIskren Chernev 44cbe63bfdSIskren Chernev static struct pll_vco default_vco[] = { 45cbe63bfdSIskren Chernev { 500000000, 1000000000, 2 }, 46cbe63bfdSIskren Chernev }; 47cbe63bfdSIskren Chernev 48cbe63bfdSIskren Chernev static struct pll_vco gpll9_vco[] = { 49cbe63bfdSIskren Chernev { 500000000, 1250000000, 0 }, 50cbe63bfdSIskren Chernev }; 51cbe63bfdSIskren Chernev 52cbe63bfdSIskren Chernev static struct pll_vco gpll10_vco[] = { 53cbe63bfdSIskren Chernev { 750000000, 1500000000, 1 }, 54cbe63bfdSIskren Chernev }; 55cbe63bfdSIskren Chernev 56cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll0 = { 57cbe63bfdSIskren Chernev .offset = 0x0, 58cbe63bfdSIskren Chernev .vco_table = default_vco, 59cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 60cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 61cbe63bfdSIskren Chernev .clkr = { 62cbe63bfdSIskren Chernev .enable_reg = 0x79000, 63cbe63bfdSIskren Chernev .enable_mask = BIT(0), 64cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 65cbe63bfdSIskren Chernev .name = "gpll0", 66cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 67cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 68cbe63bfdSIskren Chernev }, 69cbe63bfdSIskren Chernev .num_parents = 1, 70cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 71cbe63bfdSIskren Chernev }, 72cbe63bfdSIskren Chernev }, 73cbe63bfdSIskren Chernev }; 74cbe63bfdSIskren Chernev 75cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll0_out_aux2[] = { 76cbe63bfdSIskren Chernev { 0x1, 2 }, 77cbe63bfdSIskren Chernev { } 78cbe63bfdSIskren Chernev }; 79cbe63bfdSIskren Chernev 80cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll0_out_aux2 = { 81cbe63bfdSIskren Chernev .offset = 0x0, 82cbe63bfdSIskren Chernev .post_div_shift = 8, 83cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll0_out_aux2, 84cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2), 85cbe63bfdSIskren Chernev .width = 4, 86cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 87cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 88cbe63bfdSIskren Chernev .name = "gpll0_out_aux2", 89cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 90cbe63bfdSIskren Chernev .num_parents = 1, 91cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 92cbe63bfdSIskren Chernev }, 93cbe63bfdSIskren Chernev }; 94cbe63bfdSIskren Chernev 95cbe63bfdSIskren Chernev /* listed as BRAMMO, but it doesn't really match */ 96cbe63bfdSIskren Chernev static const u8 clk_gpll9_regs[PLL_OFF_MAX_REGS] = { 97cbe63bfdSIskren Chernev [PLL_OFF_L_VAL] = 0x04, 98cbe63bfdSIskren Chernev [PLL_OFF_ALPHA_VAL] = 0x08, 99cbe63bfdSIskren Chernev [PLL_OFF_ALPHA_VAL_U] = 0x0c, 100cbe63bfdSIskren Chernev [PLL_OFF_TEST_CTL] = 0x10, 101cbe63bfdSIskren Chernev [PLL_OFF_TEST_CTL_U] = 0x14, 102cbe63bfdSIskren Chernev [PLL_OFF_USER_CTL] = 0x18, 103cbe63bfdSIskren Chernev [PLL_OFF_CONFIG_CTL] = 0x1C, 104cbe63bfdSIskren Chernev [PLL_OFF_STATUS] = 0x20, 105cbe63bfdSIskren Chernev }; 106cbe63bfdSIskren Chernev 107cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll0_out_main[] = { 108cbe63bfdSIskren Chernev { 0x0, 1 }, 109cbe63bfdSIskren Chernev { } 110cbe63bfdSIskren Chernev }; 111cbe63bfdSIskren Chernev 112cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll0_out_main = { 113cbe63bfdSIskren Chernev .offset = 0x0, 114cbe63bfdSIskren Chernev .post_div_shift = 8, 115cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll0_out_main, 116cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_main), 117cbe63bfdSIskren Chernev .width = 4, 118cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 119cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 120cbe63bfdSIskren Chernev .name = "gpll0_out_main", 121cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 122cbe63bfdSIskren Chernev .num_parents = 1, 123cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 124cbe63bfdSIskren Chernev }, 125cbe63bfdSIskren Chernev }; 126cbe63bfdSIskren Chernev 127cbe63bfdSIskren Chernev /* 1152MHz configuration */ 128cbe63bfdSIskren Chernev static const struct alpha_pll_config gpll10_config = { 129cbe63bfdSIskren Chernev .l = 0x3c, 130cbe63bfdSIskren Chernev .vco_val = 0x1 << 20, 131cbe63bfdSIskren Chernev .vco_mask = GENMASK(21, 20), 132cbe63bfdSIskren Chernev .main_output_mask = BIT(0), 133cbe63bfdSIskren Chernev .config_ctl_val = 0x4001055b, 134cbe63bfdSIskren Chernev }; 135cbe63bfdSIskren Chernev 136cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll10 = { 137cbe63bfdSIskren Chernev .offset = 0xa000, 138cbe63bfdSIskren Chernev .vco_table = gpll10_vco, 139cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(gpll10_vco), 140cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 141cbe63bfdSIskren Chernev .clkr = { 142cbe63bfdSIskren Chernev .enable_reg = 0x79000, 143cbe63bfdSIskren Chernev .enable_mask = BIT(10), 144cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 145cbe63bfdSIskren Chernev .name = "gpll10", 146cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 147cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 148cbe63bfdSIskren Chernev }, 149cbe63bfdSIskren Chernev .num_parents = 1, 150cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 151cbe63bfdSIskren Chernev }, 152cbe63bfdSIskren Chernev }, 153cbe63bfdSIskren Chernev }; 154cbe63bfdSIskren Chernev 155cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll10_out_main[] = { 156cbe63bfdSIskren Chernev { 0x0, 1 }, 157cbe63bfdSIskren Chernev { } 158cbe63bfdSIskren Chernev }; 159cbe63bfdSIskren Chernev 160cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll10_out_main = { 161cbe63bfdSIskren Chernev .offset = 0xa000, 162cbe63bfdSIskren Chernev .post_div_shift = 8, 163cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll10_out_main, 164cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll10_out_main), 165cbe63bfdSIskren Chernev .width = 4, 166cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 167cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 168cbe63bfdSIskren Chernev .name = "gpll10_out_main", 169cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll10.clkr.hw }, 170cbe63bfdSIskren Chernev .num_parents = 1, 171cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 172cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ops, 173cbe63bfdSIskren Chernev }, 174cbe63bfdSIskren Chernev }; 175cbe63bfdSIskren Chernev 176cbe63bfdSIskren Chernev /* 600MHz configuration */ 177cbe63bfdSIskren Chernev static const struct alpha_pll_config gpll11_config = { 178cbe63bfdSIskren Chernev .l = 0x1F, 179cbe63bfdSIskren Chernev .alpha = 0x0, 180cbe63bfdSIskren Chernev .alpha_hi = 0x40, 181cbe63bfdSIskren Chernev .alpha_en_mask = BIT(24), 182cbe63bfdSIskren Chernev .vco_val = 0x2 << 20, 183cbe63bfdSIskren Chernev .vco_mask = GENMASK(21, 20), 184cbe63bfdSIskren Chernev .config_ctl_val = 0x4001055b, 185cbe63bfdSIskren Chernev }; 186cbe63bfdSIskren Chernev 187cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll11 = { 188cbe63bfdSIskren Chernev .offset = 0xb000, 189cbe63bfdSIskren Chernev .vco_table = default_vco, 190cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 191cbe63bfdSIskren Chernev .flags = SUPPORTS_DYNAMIC_UPDATE, 192cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 193cbe63bfdSIskren Chernev .clkr = { 194cbe63bfdSIskren Chernev .enable_reg = 0x79000, 195cbe63bfdSIskren Chernev .enable_mask = BIT(11), 196cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 197cbe63bfdSIskren Chernev .name = "gpll11", 198cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 199cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 200cbe63bfdSIskren Chernev }, 201cbe63bfdSIskren Chernev .num_parents = 1, 202cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 203cbe63bfdSIskren Chernev }, 204cbe63bfdSIskren Chernev }, 205cbe63bfdSIskren Chernev }; 206cbe63bfdSIskren Chernev 207cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll11_out_main[] = { 208cbe63bfdSIskren Chernev { 0x0, 1 }, 209cbe63bfdSIskren Chernev { } 210cbe63bfdSIskren Chernev }; 211cbe63bfdSIskren Chernev 212cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll11_out_main = { 213cbe63bfdSIskren Chernev .offset = 0xb000, 214cbe63bfdSIskren Chernev .post_div_shift = 8, 215cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll11_out_main, 216cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll11_out_main), 217cbe63bfdSIskren Chernev .width = 4, 218cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 219cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 220cbe63bfdSIskren Chernev .name = "gpll11_out_main", 221cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll11.clkr.hw }, 222cbe63bfdSIskren Chernev .num_parents = 1, 223cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 224cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ops, 225cbe63bfdSIskren Chernev }, 226cbe63bfdSIskren Chernev }; 227cbe63bfdSIskren Chernev 228cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll3 = { 229cbe63bfdSIskren Chernev .offset = 0x3000, 230cbe63bfdSIskren Chernev .vco_table = default_vco, 231cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 232cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 233cbe63bfdSIskren Chernev .clkr = { 234cbe63bfdSIskren Chernev .enable_reg = 0x79000, 235cbe63bfdSIskren Chernev .enable_mask = BIT(3), 236cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 237cbe63bfdSIskren Chernev .name = "gpll3", 238cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 239cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 240cbe63bfdSIskren Chernev }, 241cbe63bfdSIskren Chernev .num_parents = 1, 242cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 243cbe63bfdSIskren Chernev }, 244cbe63bfdSIskren Chernev }, 245cbe63bfdSIskren Chernev }; 246cbe63bfdSIskren Chernev 247cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll4 = { 248cbe63bfdSIskren Chernev .offset = 0x4000, 249cbe63bfdSIskren Chernev .vco_table = default_vco, 250cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 251cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 252cbe63bfdSIskren Chernev .clkr = { 253cbe63bfdSIskren Chernev .enable_reg = 0x79000, 254cbe63bfdSIskren Chernev .enable_mask = BIT(4), 255cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 256cbe63bfdSIskren Chernev .name = "gpll4", 257cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 258cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 259cbe63bfdSIskren Chernev }, 260cbe63bfdSIskren Chernev .num_parents = 1, 261cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 262cbe63bfdSIskren Chernev }, 263cbe63bfdSIskren Chernev }, 264cbe63bfdSIskren Chernev }; 265cbe63bfdSIskren Chernev 266cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll4_out_main[] = { 267cbe63bfdSIskren Chernev { 0x0, 1 }, 268cbe63bfdSIskren Chernev { } 269cbe63bfdSIskren Chernev }; 270cbe63bfdSIskren Chernev 271cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll4_out_main = { 272cbe63bfdSIskren Chernev .offset = 0x4000, 273cbe63bfdSIskren Chernev .post_div_shift = 8, 274cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll4_out_main, 275cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll4_out_main), 276cbe63bfdSIskren Chernev .width = 4, 277cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 278cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 279cbe63bfdSIskren Chernev .name = "gpll4_out_main", 280cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll4.clkr.hw }, 281cbe63bfdSIskren Chernev .num_parents = 1, 282cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 283cbe63bfdSIskren Chernev }, 284cbe63bfdSIskren Chernev }; 285cbe63bfdSIskren Chernev 286cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll6 = { 287cbe63bfdSIskren Chernev .offset = 0x6000, 288cbe63bfdSIskren Chernev .vco_table = default_vco, 289cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 290cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 291cbe63bfdSIskren Chernev .clkr = { 292cbe63bfdSIskren Chernev .enable_reg = 0x79000, 293cbe63bfdSIskren Chernev .enable_mask = BIT(6), 294cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 295cbe63bfdSIskren Chernev .name = "gpll6", 296cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 297cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 298cbe63bfdSIskren Chernev }, 299cbe63bfdSIskren Chernev .num_parents = 1, 300cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 301cbe63bfdSIskren Chernev }, 302cbe63bfdSIskren Chernev }, 303cbe63bfdSIskren Chernev }; 304cbe63bfdSIskren Chernev 305cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll6_out_main[] = { 306cbe63bfdSIskren Chernev { 0x1, 2 }, 307cbe63bfdSIskren Chernev { } 308cbe63bfdSIskren Chernev }; 309cbe63bfdSIskren Chernev 310cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll6_out_main = { 311cbe63bfdSIskren Chernev .offset = 0x6000, 312cbe63bfdSIskren Chernev .post_div_shift = 8, 313cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll6_out_main, 314cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main), 315cbe63bfdSIskren Chernev .width = 4, 316cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 317cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 318cbe63bfdSIskren Chernev .name = "gpll6_out_main", 319cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw }, 320cbe63bfdSIskren Chernev .num_parents = 1, 321cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 322cbe63bfdSIskren Chernev }, 323cbe63bfdSIskren Chernev }; 324cbe63bfdSIskren Chernev 325cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll7 = { 326cbe63bfdSIskren Chernev .offset = 0x7000, 327cbe63bfdSIskren Chernev .vco_table = default_vco, 328cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 329cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 330cbe63bfdSIskren Chernev .clkr = { 331cbe63bfdSIskren Chernev .enable_reg = 0x79000, 332cbe63bfdSIskren Chernev .enable_mask = BIT(7), 333cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 334cbe63bfdSIskren Chernev .name = "gpll7", 335cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 336cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 337cbe63bfdSIskren Chernev }, 338cbe63bfdSIskren Chernev .num_parents = 1, 339cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 340cbe63bfdSIskren Chernev }, 341cbe63bfdSIskren Chernev }, 342cbe63bfdSIskren Chernev }; 343cbe63bfdSIskren Chernev 344cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll7_out_main[] = { 345cbe63bfdSIskren Chernev { 0x0, 1 }, 346cbe63bfdSIskren Chernev { } 347cbe63bfdSIskren Chernev }; 348cbe63bfdSIskren Chernev 349cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll7_out_main = { 350cbe63bfdSIskren Chernev .offset = 0x7000, 351cbe63bfdSIskren Chernev .post_div_shift = 8, 352cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll7_out_main, 353cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll7_out_main), 354cbe63bfdSIskren Chernev .width = 4, 355cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 356cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 357cbe63bfdSIskren Chernev .name = "gpll7_out_main", 358cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll7.clkr.hw }, 359cbe63bfdSIskren Chernev .num_parents = 1, 360cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 361cbe63bfdSIskren Chernev }, 362cbe63bfdSIskren Chernev }; 363cbe63bfdSIskren Chernev 364cbe63bfdSIskren Chernev /* 800MHz configuration */ 365cbe63bfdSIskren Chernev static const struct alpha_pll_config gpll8_config = { 366cbe63bfdSIskren Chernev .l = 0x29, 367cbe63bfdSIskren Chernev .alpha = 0xAAAAAAAA, 368cbe63bfdSIskren Chernev .alpha_hi = 0xAA, 369cbe63bfdSIskren Chernev .alpha_en_mask = BIT(24), 370cbe63bfdSIskren Chernev .vco_val = 0x2 << 20, 371cbe63bfdSIskren Chernev .vco_mask = GENMASK(21, 20), 372cbe63bfdSIskren Chernev .main_output_mask = BIT(0), 373cbe63bfdSIskren Chernev .early_output_mask = BIT(3), 374cbe63bfdSIskren Chernev .post_div_val = 0x1 << 8, 375cbe63bfdSIskren Chernev .post_div_mask = GENMASK(11, 8), 376cbe63bfdSIskren Chernev .config_ctl_val = 0x4001055b, 377cbe63bfdSIskren Chernev }; 378cbe63bfdSIskren Chernev 379cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll8 = { 380cbe63bfdSIskren Chernev .offset = 0x8000, 381cbe63bfdSIskren Chernev .vco_table = default_vco, 382cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 383cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 384cbe63bfdSIskren Chernev .flags = SUPPORTS_DYNAMIC_UPDATE, 385cbe63bfdSIskren Chernev .clkr = { 386cbe63bfdSIskren Chernev .enable_reg = 0x79000, 387cbe63bfdSIskren Chernev .enable_mask = BIT(8), 388cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 389cbe63bfdSIskren Chernev .name = "gpll8", 390cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 391cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 392cbe63bfdSIskren Chernev }, 393cbe63bfdSIskren Chernev .num_parents = 1, 394cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 395cbe63bfdSIskren Chernev }, 396cbe63bfdSIskren Chernev }, 397cbe63bfdSIskren Chernev }; 398cbe63bfdSIskren Chernev 399cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll8_out_main[] = { 400cbe63bfdSIskren Chernev { 0x1, 2 }, 401cbe63bfdSIskren Chernev { } 402cbe63bfdSIskren Chernev }; 403cbe63bfdSIskren Chernev 404cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll8_out_main = { 405cbe63bfdSIskren Chernev .offset = 0x8000, 406cbe63bfdSIskren Chernev .post_div_shift = 8, 407cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll8_out_main, 408cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main), 409cbe63bfdSIskren Chernev .width = 4, 410cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 411cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 412cbe63bfdSIskren Chernev .name = "gpll8_out_main", 413cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw }, 414cbe63bfdSIskren Chernev .num_parents = 1, 415cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 416cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 417cbe63bfdSIskren Chernev }, 418cbe63bfdSIskren Chernev }; 419cbe63bfdSIskren Chernev 420cbe63bfdSIskren Chernev /* 1152MHz configuration */ 421cbe63bfdSIskren Chernev static const struct alpha_pll_config gpll9_config = { 422cbe63bfdSIskren Chernev .l = 0x3C, 423cbe63bfdSIskren Chernev .alpha = 0x0, 424cbe63bfdSIskren Chernev .post_div_val = 0x1 << 8, 425cbe63bfdSIskren Chernev .post_div_mask = GENMASK(9, 8), 426cbe63bfdSIskren Chernev .main_output_mask = BIT(0), 427cbe63bfdSIskren Chernev .config_ctl_val = 0x00004289, 428cbe63bfdSIskren Chernev }; 429cbe63bfdSIskren Chernev 430cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll9 = { 431cbe63bfdSIskren Chernev .offset = 0x9000, 432cbe63bfdSIskren Chernev .vco_table = gpll9_vco, 433cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(gpll9_vco), 434cbe63bfdSIskren Chernev .regs = clk_gpll9_regs, 435cbe63bfdSIskren Chernev .clkr = { 436cbe63bfdSIskren Chernev .enable_reg = 0x79000, 437cbe63bfdSIskren Chernev .enable_mask = BIT(9), 438cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 439cbe63bfdSIskren Chernev .name = "gpll9", 440cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 441cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 442cbe63bfdSIskren Chernev }, 443cbe63bfdSIskren Chernev .num_parents = 1, 444cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 445cbe63bfdSIskren Chernev }, 446cbe63bfdSIskren Chernev }, 447cbe63bfdSIskren Chernev }; 448cbe63bfdSIskren Chernev 449cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll9_out_main[] = { 450cbe63bfdSIskren Chernev { 0x1, 2 }, 451cbe63bfdSIskren Chernev { } 452cbe63bfdSIskren Chernev }; 453cbe63bfdSIskren Chernev 454cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll9_out_main = { 455cbe63bfdSIskren Chernev .offset = 0x9000, 456cbe63bfdSIskren Chernev .post_div_shift = 8, 457cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll9_out_main, 458cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main), 459cbe63bfdSIskren Chernev .width = 2, 460cbe63bfdSIskren Chernev .regs = clk_gpll9_regs, 461cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 462cbe63bfdSIskren Chernev .name = "gpll9_out_main", 463cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw }, 464cbe63bfdSIskren Chernev .num_parents = 1, 465cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 466cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ops, 467cbe63bfdSIskren Chernev }, 468cbe63bfdSIskren Chernev }; 469cbe63bfdSIskren Chernev 470cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_0[] = { 471cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 472cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 473cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 474cbe63bfdSIskren Chernev }; 475cbe63bfdSIskren Chernev 476cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_0[] = { 477cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 478cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 479cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 480cbe63bfdSIskren Chernev }; 481cbe63bfdSIskren Chernev 482cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_1[] = { 483cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 484cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 485cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 486cbe63bfdSIskren Chernev { P_GPLL6_OUT_MAIN, 4 }, 487cbe63bfdSIskren Chernev }; 488cbe63bfdSIskren Chernev 489cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_1[] = { 490cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 491cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 492cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 493cbe63bfdSIskren Chernev { .hw = &gpll6_out_main.clkr.hw }, 494cbe63bfdSIskren Chernev }; 495cbe63bfdSIskren Chernev 496cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_2[] = { 497cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 498cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 499cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 500cbe63bfdSIskren Chernev { P_SLEEP_CLK, 5 }, 501cbe63bfdSIskren Chernev }; 502cbe63bfdSIskren Chernev 503cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_2[] = { 504cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 505cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 506cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 507cbe63bfdSIskren Chernev { .fw_name = "sleep_clk" }, 508cbe63bfdSIskren Chernev }; 509cbe63bfdSIskren Chernev 510cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_3[] = { 511cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 512cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 513cbe63bfdSIskren Chernev { P_GPLL9_OUT_EARLY, 2 }, 514cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 515cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 516cbe63bfdSIskren Chernev }; 517cbe63bfdSIskren Chernev 518cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_3[] = { 519cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 520cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 521cbe63bfdSIskren Chernev { .hw = &gpll9.clkr.hw }, 522cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 523cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 524cbe63bfdSIskren Chernev }; 525cbe63bfdSIskren Chernev 526cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_4[] = { 527cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 528cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 529cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 530cbe63bfdSIskren Chernev { P_GPLL4_OUT_MAIN, 5 }, 531cbe63bfdSIskren Chernev }; 532cbe63bfdSIskren Chernev 533cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_4[] = { 534cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 535cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 536cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 537cbe63bfdSIskren Chernev { .hw = &gpll4_out_main.clkr.hw }, 538cbe63bfdSIskren Chernev }; 539cbe63bfdSIskren Chernev 540cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_5[] = { 541cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 542cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 543cbe63bfdSIskren Chernev { P_GPLL8_OUT_EARLY, 2 }, 544cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 545cbe63bfdSIskren Chernev { P_GPLL8_OUT_MAIN, 4 }, 546cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 547cbe63bfdSIskren Chernev }; 548cbe63bfdSIskren Chernev 549cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_5[] = { 550cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 551cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 552cbe63bfdSIskren Chernev { .hw = &gpll8.clkr.hw }, 553cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 554cbe63bfdSIskren Chernev { .hw = &gpll8_out_main.clkr.hw }, 555cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 556cbe63bfdSIskren Chernev }; 557cbe63bfdSIskren Chernev 558cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_6[] = { 559cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 560cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 561cbe63bfdSIskren Chernev { P_GPLL8_OUT_EARLY, 2 }, 562cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 563cbe63bfdSIskren Chernev { P_GPLL6_OUT_MAIN, 4 }, 564cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 565cbe63bfdSIskren Chernev { P_GPLL3_OUT_EARLY, 6 }, 566cbe63bfdSIskren Chernev }; 567cbe63bfdSIskren Chernev 568cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_6[] = { 569cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 570cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 571cbe63bfdSIskren Chernev { .hw = &gpll8.clkr.hw }, 572cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 573cbe63bfdSIskren Chernev { .hw = &gpll6_out_main.clkr.hw }, 574cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 575cbe63bfdSIskren Chernev { .hw = &gpll3.clkr.hw }, 576cbe63bfdSIskren Chernev }; 577cbe63bfdSIskren Chernev 578cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_7[] = { 579cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 580cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 581cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 582cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 583cbe63bfdSIskren Chernev { P_GPLL4_OUT_MAIN, 5 }, 584cbe63bfdSIskren Chernev { P_GPLL3_OUT_EARLY, 6 }, 585cbe63bfdSIskren Chernev }; 586cbe63bfdSIskren Chernev 587cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_7[] = { 588cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 589cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 590cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 591cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 592cbe63bfdSIskren Chernev { .hw = &gpll4_out_main.clkr.hw }, 593cbe63bfdSIskren Chernev { .hw = &gpll3.clkr.hw }, 594cbe63bfdSIskren Chernev }; 595cbe63bfdSIskren Chernev 596cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_8[] = { 597cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 598cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 599cbe63bfdSIskren Chernev { P_GPLL8_OUT_EARLY, 2 }, 600cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 601cbe63bfdSIskren Chernev { P_GPLL8_OUT_MAIN, 4 }, 602cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 603cbe63bfdSIskren Chernev { P_GPLL3_OUT_EARLY, 6 }, 604cbe63bfdSIskren Chernev }; 605cbe63bfdSIskren Chernev 606cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_8[] = { 607cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 608cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 609cbe63bfdSIskren Chernev { .hw = &gpll8.clkr.hw }, 610cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 611cbe63bfdSIskren Chernev { .hw = &gpll8_out_main.clkr.hw }, 612cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 613cbe63bfdSIskren Chernev { .hw = &gpll3.clkr.hw }, 614cbe63bfdSIskren Chernev }; 615cbe63bfdSIskren Chernev 616cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_9[] = { 617cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 618cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 619cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 620cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 621cbe63bfdSIskren Chernev { P_GPLL8_OUT_MAIN, 4 }, 622cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 623cbe63bfdSIskren Chernev { P_GPLL3_OUT_EARLY, 6 }, 624cbe63bfdSIskren Chernev }; 625cbe63bfdSIskren Chernev 626cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_9[] = { 627cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 628cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 629cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 630cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 631cbe63bfdSIskren Chernev { .hw = &gpll8_out_main.clkr.hw }, 632cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 633cbe63bfdSIskren Chernev { .hw = &gpll3.clkr.hw }, 634cbe63bfdSIskren Chernev }; 635cbe63bfdSIskren Chernev 636cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_10[] = { 637cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 638cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 639cbe63bfdSIskren Chernev { P_GPLL8_OUT_EARLY, 2 }, 640cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 641cbe63bfdSIskren Chernev { P_GPLL6_OUT_EARLY, 4 }, 642cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 643cbe63bfdSIskren Chernev }; 644cbe63bfdSIskren Chernev 645cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_10[] = { 646cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 647cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 648cbe63bfdSIskren Chernev { .hw = &gpll8.clkr.hw }, 649cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 650cbe63bfdSIskren Chernev { .hw = &gpll6.clkr.hw }, 651cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 652cbe63bfdSIskren Chernev }; 653cbe63bfdSIskren Chernev 654cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_11[] = { 655cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 656cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 657cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 658cbe63bfdSIskren Chernev { P_GPLL7_OUT_MAIN, 3 }, 659cbe63bfdSIskren Chernev { P_GPLL4_OUT_MAIN, 5 }, 660cbe63bfdSIskren Chernev }; 661cbe63bfdSIskren Chernev 662cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_11[] = { 663cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 664cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 665cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 666cbe63bfdSIskren Chernev { .hw = &gpll7_out_main.clkr.hw }, 667cbe63bfdSIskren Chernev { .hw = &gpll4_out_main.clkr.hw }, 668cbe63bfdSIskren Chernev }; 669cbe63bfdSIskren Chernev 670cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_12[] = { 671cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 672cbe63bfdSIskren Chernev { P_SLEEP_CLK, 5 }, 673cbe63bfdSIskren Chernev }; 674cbe63bfdSIskren Chernev 675cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_12[] = { 676cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 677cbe63bfdSIskren Chernev { .fw_name = "sleep_clk" }, 678cbe63bfdSIskren Chernev }; 679cbe63bfdSIskren Chernev 680cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_13[] = { 681cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 682cbe63bfdSIskren Chernev { P_GPLL11_OUT_MAIN, 1 }, 683cbe63bfdSIskren Chernev }; 684cbe63bfdSIskren Chernev 685cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_13[] = { 686cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 687cbe63bfdSIskren Chernev { .hw = &gpll11_out_main.clkr.hw }, 688cbe63bfdSIskren Chernev }; 689cbe63bfdSIskren Chernev 690cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = { 691cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 692cbe63bfdSIskren Chernev F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 693cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 694cbe63bfdSIskren Chernev F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 695cbe63bfdSIskren Chernev { } 696cbe63bfdSIskren Chernev }; 697cbe63bfdSIskren Chernev 698cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_axi_clk_src = { 699cbe63bfdSIskren Chernev .cmd_rcgr = 0x5802c, 700cbe63bfdSIskren Chernev .mnd_width = 0, 701cbe63bfdSIskren Chernev .hid_width = 5, 702cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_7, 703cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_axi_clk_src, 704cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 705cbe63bfdSIskren Chernev .name = "gcc_camss_axi_clk_src", 706cbe63bfdSIskren Chernev .parent_data = gcc_parents_7, 707cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_7), 708cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 709cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 710cbe63bfdSIskren Chernev }, 711cbe63bfdSIskren Chernev }; 712cbe63bfdSIskren Chernev 713cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = { 714cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 715cbe63bfdSIskren Chernev F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 716cbe63bfdSIskren Chernev { } 717cbe63bfdSIskren Chernev }; 718cbe63bfdSIskren Chernev 719cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_cci_clk_src = { 720cbe63bfdSIskren Chernev .cmd_rcgr = 0x56000, 721cbe63bfdSIskren Chernev .mnd_width = 0, 722cbe63bfdSIskren Chernev .hid_width = 5, 723cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_9, 724cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_cci_clk_src, 725cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 726cbe63bfdSIskren Chernev .name = "gcc_camss_cci_clk_src", 727cbe63bfdSIskren Chernev .parent_data = gcc_parents_9, 728cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_9), 729cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 730cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 731cbe63bfdSIskren Chernev }, 732cbe63bfdSIskren Chernev }; 733cbe63bfdSIskren Chernev 734cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = { 735cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 736cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 737cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 738cbe63bfdSIskren Chernev F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0), 739cbe63bfdSIskren Chernev { } 740cbe63bfdSIskren Chernev }; 741cbe63bfdSIskren Chernev 742cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { 743cbe63bfdSIskren Chernev .cmd_rcgr = 0x59000, 744cbe63bfdSIskren Chernev .mnd_width = 0, 745cbe63bfdSIskren Chernev .hid_width = 5, 746cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_4, 747cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 748cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 749cbe63bfdSIskren Chernev .name = "gcc_camss_csi0phytimer_clk_src", 750cbe63bfdSIskren Chernev .parent_data = gcc_parents_4, 751cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_4), 752cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 753cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 754cbe63bfdSIskren Chernev }, 755cbe63bfdSIskren Chernev }; 756cbe63bfdSIskren Chernev 757cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { 758cbe63bfdSIskren Chernev .cmd_rcgr = 0x5901c, 759cbe63bfdSIskren Chernev .mnd_width = 0, 760cbe63bfdSIskren Chernev .hid_width = 5, 761cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_4, 762cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 763cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 764cbe63bfdSIskren Chernev .name = "gcc_camss_csi1phytimer_clk_src", 765cbe63bfdSIskren Chernev .parent_data = gcc_parents_4, 766cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_4), 767cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 768cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 769cbe63bfdSIskren Chernev }, 770cbe63bfdSIskren Chernev }; 771cbe63bfdSIskren Chernev 772cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = { 773cbe63bfdSIskren Chernev .cmd_rcgr = 0x59038, 774cbe63bfdSIskren Chernev .mnd_width = 0, 775cbe63bfdSIskren Chernev .hid_width = 5, 776cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_4, 777cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 778cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 779cbe63bfdSIskren Chernev .name = "gcc_camss_csi2phytimer_clk_src", 780cbe63bfdSIskren Chernev .parent_data = gcc_parents_4, 781cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_4), 782cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 783cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 784cbe63bfdSIskren Chernev }, 785cbe63bfdSIskren Chernev }; 786cbe63bfdSIskren Chernev 787cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { 788cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 789cbe63bfdSIskren Chernev F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24), 790cbe63bfdSIskren Chernev F(64000000, P_GPLL9_OUT_MAIN, 1, 1, 9), 791cbe63bfdSIskren Chernev { } 792cbe63bfdSIskren Chernev }; 793cbe63bfdSIskren Chernev 794cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_mclk0_clk_src = { 795cbe63bfdSIskren Chernev .cmd_rcgr = 0x51000, 796cbe63bfdSIskren Chernev .mnd_width = 8, 797cbe63bfdSIskren Chernev .hid_width = 5, 798cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_3, 799cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 800cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 801cbe63bfdSIskren Chernev .name = "gcc_camss_mclk0_clk_src", 802cbe63bfdSIskren Chernev .parent_data = gcc_parents_3, 803cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_3), 804cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 805cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 806cbe63bfdSIskren Chernev }, 807cbe63bfdSIskren Chernev }; 808cbe63bfdSIskren Chernev 809cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_mclk1_clk_src = { 810cbe63bfdSIskren Chernev .cmd_rcgr = 0x5101c, 811cbe63bfdSIskren Chernev .mnd_width = 8, 812cbe63bfdSIskren Chernev .hid_width = 5, 813cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_3, 814cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 815cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 816cbe63bfdSIskren Chernev .name = "gcc_camss_mclk1_clk_src", 817cbe63bfdSIskren Chernev .parent_data = gcc_parents_3, 818cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_3), 819cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 820cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 821cbe63bfdSIskren Chernev }, 822cbe63bfdSIskren Chernev }; 823cbe63bfdSIskren Chernev 824cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_mclk2_clk_src = { 825cbe63bfdSIskren Chernev .cmd_rcgr = 0x51038, 826cbe63bfdSIskren Chernev .mnd_width = 8, 827cbe63bfdSIskren Chernev .hid_width = 5, 828cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_3, 829cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 830cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 831cbe63bfdSIskren Chernev .name = "gcc_camss_mclk2_clk_src", 832cbe63bfdSIskren Chernev .parent_data = gcc_parents_3, 833cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_3), 834cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 835cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 836cbe63bfdSIskren Chernev }, 837cbe63bfdSIskren Chernev }; 838cbe63bfdSIskren Chernev 839cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_mclk3_clk_src = { 840cbe63bfdSIskren Chernev .cmd_rcgr = 0x51054, 841cbe63bfdSIskren Chernev .mnd_width = 8, 842cbe63bfdSIskren Chernev .hid_width = 5, 843cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_3, 844cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 845cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 846cbe63bfdSIskren Chernev .name = "gcc_camss_mclk3_clk_src", 847cbe63bfdSIskren Chernev .parent_data = gcc_parents_3, 848cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_3), 849cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 850cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 851cbe63bfdSIskren Chernev }, 852cbe63bfdSIskren Chernev }; 853cbe63bfdSIskren Chernev 854cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = { 855cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 856cbe63bfdSIskren Chernev F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0), 857cbe63bfdSIskren Chernev F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 858cbe63bfdSIskren Chernev { } 859cbe63bfdSIskren Chernev }; 860cbe63bfdSIskren Chernev 861cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = { 862cbe63bfdSIskren Chernev .cmd_rcgr = 0x55024, 863cbe63bfdSIskren Chernev .mnd_width = 0, 864cbe63bfdSIskren Chernev .hid_width = 5, 865cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_8, 866cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src, 867cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 868cbe63bfdSIskren Chernev .name = "gcc_camss_ope_ahb_clk_src", 869cbe63bfdSIskren Chernev .parent_data = gcc_parents_8, 870cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_8), 871cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 872cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 873cbe63bfdSIskren Chernev }, 874cbe63bfdSIskren Chernev }; 875cbe63bfdSIskren Chernev 876cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = { 877cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 878cbe63bfdSIskren Chernev F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0), 879cbe63bfdSIskren Chernev F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0), 880cbe63bfdSIskren Chernev F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0), 881cbe63bfdSIskren Chernev F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0), 882cbe63bfdSIskren Chernev { } 883cbe63bfdSIskren Chernev }; 884cbe63bfdSIskren Chernev 885cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_ope_clk_src = { 886cbe63bfdSIskren Chernev .cmd_rcgr = 0x55004, 887cbe63bfdSIskren Chernev .mnd_width = 0, 888cbe63bfdSIskren Chernev .hid_width = 5, 889cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_8, 890cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_ope_clk_src, 891cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 892cbe63bfdSIskren Chernev .name = "gcc_camss_ope_clk_src", 893cbe63bfdSIskren Chernev .parent_data = gcc_parents_8, 894cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_8), 895cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 896cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 897cbe63bfdSIskren Chernev }, 898cbe63bfdSIskren Chernev }; 899cbe63bfdSIskren Chernev 900cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = { 901cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 902cbe63bfdSIskren Chernev F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0), 903cbe63bfdSIskren Chernev F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0), 904cbe63bfdSIskren Chernev F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0), 905cbe63bfdSIskren Chernev F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0), 906cbe63bfdSIskren Chernev F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0), 907cbe63bfdSIskren Chernev F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0), 908cbe63bfdSIskren Chernev F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0), 909cbe63bfdSIskren Chernev F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0), 910cbe63bfdSIskren Chernev F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0), 911cbe63bfdSIskren Chernev F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0), 912cbe63bfdSIskren Chernev F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0), 913cbe63bfdSIskren Chernev F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0), 914cbe63bfdSIskren Chernev F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0), 915cbe63bfdSIskren Chernev F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0), 916cbe63bfdSIskren Chernev F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0), 917cbe63bfdSIskren Chernev { } 918cbe63bfdSIskren Chernev }; 919cbe63bfdSIskren Chernev 920cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_0_clk_src = { 921cbe63bfdSIskren Chernev .cmd_rcgr = 0x52004, 922cbe63bfdSIskren Chernev .mnd_width = 8, 923cbe63bfdSIskren Chernev .hid_width = 5, 924cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_5, 925cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 926cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 927cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_0_clk_src", 928cbe63bfdSIskren Chernev .parent_data = gcc_parents_5, 929cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_5), 930cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 931cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 932cbe63bfdSIskren Chernev }, 933cbe63bfdSIskren Chernev }; 934cbe63bfdSIskren Chernev 935cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = { 936cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 937cbe63bfdSIskren Chernev F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0), 938cbe63bfdSIskren Chernev F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 939cbe63bfdSIskren Chernev F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 940cbe63bfdSIskren Chernev F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 941cbe63bfdSIskren Chernev F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0), 942cbe63bfdSIskren Chernev { } 943cbe63bfdSIskren Chernev }; 944cbe63bfdSIskren Chernev 945cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = { 946cbe63bfdSIskren Chernev .cmd_rcgr = 0x52094, 947cbe63bfdSIskren Chernev .mnd_width = 0, 948cbe63bfdSIskren Chernev .hid_width = 5, 949cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_6, 950cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 951cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 952cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_0_csid_clk_src", 953cbe63bfdSIskren Chernev .parent_data = gcc_parents_6, 954cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_6), 955cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 956cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 957cbe63bfdSIskren Chernev }, 958cbe63bfdSIskren Chernev }; 959cbe63bfdSIskren Chernev 960cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_1_clk_src = { 961cbe63bfdSIskren Chernev .cmd_rcgr = 0x52024, 962cbe63bfdSIskren Chernev .mnd_width = 8, 963cbe63bfdSIskren Chernev .hid_width = 5, 964cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_5, 965cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 966cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 967cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_1_clk_src", 968cbe63bfdSIskren Chernev .parent_data = gcc_parents_5, 969cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_5), 970cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 971cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 972cbe63bfdSIskren Chernev }, 973cbe63bfdSIskren Chernev }; 974cbe63bfdSIskren Chernev 975cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = { 976cbe63bfdSIskren Chernev .cmd_rcgr = 0x520b4, 977cbe63bfdSIskren Chernev .mnd_width = 0, 978cbe63bfdSIskren Chernev .hid_width = 5, 979cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_6, 980cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 981cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 982cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_1_csid_clk_src", 983cbe63bfdSIskren Chernev .parent_data = gcc_parents_6, 984cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_6), 985cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 986cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 987cbe63bfdSIskren Chernev }, 988cbe63bfdSIskren Chernev }; 989cbe63bfdSIskren Chernev 990cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_2_clk_src = { 991cbe63bfdSIskren Chernev .cmd_rcgr = 0x52044, 992cbe63bfdSIskren Chernev .mnd_width = 8, 993cbe63bfdSIskren Chernev .hid_width = 5, 994cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_5, 995cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 996cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 997cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_2_clk_src", 998cbe63bfdSIskren Chernev .parent_data = gcc_parents_5, 999cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_5), 1000cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1001cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1002cbe63bfdSIskren Chernev }, 1003cbe63bfdSIskren Chernev }; 1004cbe63bfdSIskren Chernev 1005cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_2_csid_clk_src = { 1006cbe63bfdSIskren Chernev .cmd_rcgr = 0x520d4, 1007cbe63bfdSIskren Chernev .mnd_width = 0, 1008cbe63bfdSIskren Chernev .hid_width = 5, 1009cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_6, 1010cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 1011cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1012cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_2_csid_clk_src", 1013cbe63bfdSIskren Chernev .parent_data = gcc_parents_6, 1014cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_6), 1015cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1016cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1017cbe63bfdSIskren Chernev }, 1018cbe63bfdSIskren Chernev }; 1019cbe63bfdSIskren Chernev 1020cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = { 1021cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1022cbe63bfdSIskren Chernev F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1023cbe63bfdSIskren Chernev F(341333333, P_GPLL6_OUT_EARLY, 1, 4, 9), 1024cbe63bfdSIskren Chernev F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0), 1025cbe63bfdSIskren Chernev { } 1026cbe63bfdSIskren Chernev }; 1027cbe63bfdSIskren Chernev 1028cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = { 1029cbe63bfdSIskren Chernev .cmd_rcgr = 0x52064, 1030cbe63bfdSIskren Chernev .mnd_width = 16, 1031cbe63bfdSIskren Chernev .hid_width = 5, 1032cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_10, 1033cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src, 1034cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1035cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_cphy_rx_clk_src", 1036cbe63bfdSIskren Chernev .parent_data = gcc_parents_10, 1037cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_10), 1038cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 1039cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1040cbe63bfdSIskren Chernev }, 1041cbe63bfdSIskren Chernev }; 1042cbe63bfdSIskren Chernev 1043cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = { 1044cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1045cbe63bfdSIskren Chernev F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0), 1046cbe63bfdSIskren Chernev F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0), 1047cbe63bfdSIskren Chernev { } 1048cbe63bfdSIskren Chernev }; 1049cbe63bfdSIskren Chernev 1050cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_top_ahb_clk_src = { 1051cbe63bfdSIskren Chernev .cmd_rcgr = 0x58010, 1052cbe63bfdSIskren Chernev .mnd_width = 0, 1053cbe63bfdSIskren Chernev .hid_width = 5, 1054cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_7, 1055cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_top_ahb_clk_src, 1056cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1057cbe63bfdSIskren Chernev .name = "gcc_camss_top_ahb_clk_src", 1058cbe63bfdSIskren Chernev .parent_data = gcc_parents_7, 1059cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_7), 1060cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 1061cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1062cbe63bfdSIskren Chernev }, 1063cbe63bfdSIskren Chernev }; 1064cbe63bfdSIskren Chernev 1065cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 1066cbe63bfdSIskren Chernev F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1067cbe63bfdSIskren Chernev F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1068cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1069cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 1070cbe63bfdSIskren Chernev { } 1071cbe63bfdSIskren Chernev }; 1072cbe63bfdSIskren Chernev 1073cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_gp1_clk_src = { 1074cbe63bfdSIskren Chernev .cmd_rcgr = 0x4d004, 1075cbe63bfdSIskren Chernev .mnd_width = 8, 1076cbe63bfdSIskren Chernev .hid_width = 5, 1077cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_2, 1078cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_gp1_clk_src, 1079cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1080cbe63bfdSIskren Chernev .name = "gcc_gp1_clk_src", 1081cbe63bfdSIskren Chernev .parent_data = gcc_parents_2, 1082cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_2), 1083cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1084cbe63bfdSIskren Chernev }, 1085cbe63bfdSIskren Chernev }; 1086cbe63bfdSIskren Chernev 1087cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_gp2_clk_src = { 1088cbe63bfdSIskren Chernev .cmd_rcgr = 0x4e004, 1089cbe63bfdSIskren Chernev .mnd_width = 8, 1090cbe63bfdSIskren Chernev .hid_width = 5, 1091cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_2, 1092cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_gp1_clk_src, 1093cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1094cbe63bfdSIskren Chernev .name = "gcc_gp2_clk_src", 1095cbe63bfdSIskren Chernev .parent_data = gcc_parents_2, 1096cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_2), 1097cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1098cbe63bfdSIskren Chernev }, 1099cbe63bfdSIskren Chernev }; 1100cbe63bfdSIskren Chernev 1101cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_gp3_clk_src = { 1102cbe63bfdSIskren Chernev .cmd_rcgr = 0x4f004, 1103cbe63bfdSIskren Chernev .mnd_width = 8, 1104cbe63bfdSIskren Chernev .hid_width = 5, 1105cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_2, 1106cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_gp1_clk_src, 1107cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1108cbe63bfdSIskren Chernev .name = "gcc_gp3_clk_src", 1109cbe63bfdSIskren Chernev .parent_data = gcc_parents_2, 1110cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_2), 1111cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1112cbe63bfdSIskren Chernev }, 1113cbe63bfdSIskren Chernev }; 1114cbe63bfdSIskren Chernev 1115cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 1116cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1117cbe63bfdSIskren Chernev F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0), 1118cbe63bfdSIskren Chernev { } 1119cbe63bfdSIskren Chernev }; 1120cbe63bfdSIskren Chernev 1121cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_pdm2_clk_src = { 1122cbe63bfdSIskren Chernev .cmd_rcgr = 0x20010, 1123cbe63bfdSIskren Chernev .mnd_width = 0, 1124cbe63bfdSIskren Chernev .hid_width = 5, 1125cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1126cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_pdm2_clk_src, 1127cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1128cbe63bfdSIskren Chernev .name = "gcc_pdm2_clk_src", 1129cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1130cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1131cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1132cbe63bfdSIskren Chernev }, 1133cbe63bfdSIskren Chernev }; 1134cbe63bfdSIskren Chernev 1135cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 1136cbe63bfdSIskren Chernev F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625), 1137cbe63bfdSIskren Chernev F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625), 1138cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1139cbe63bfdSIskren Chernev F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625), 1140cbe63bfdSIskren Chernev F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75), 1141cbe63bfdSIskren Chernev F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25), 1142cbe63bfdSIskren Chernev F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75), 1143cbe63bfdSIskren Chernev F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1144cbe63bfdSIskren Chernev F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15), 1145cbe63bfdSIskren Chernev F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25), 1146cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1147cbe63bfdSIskren Chernev F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375), 1148cbe63bfdSIskren Chernev F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75), 1149cbe63bfdSIskren Chernev F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625), 1150cbe63bfdSIskren Chernev F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0), 1151cbe63bfdSIskren Chernev F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0), 1152cbe63bfdSIskren Chernev { } 1153cbe63bfdSIskren Chernev }; 1154cbe63bfdSIskren Chernev 1155cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 1156cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s0_clk_src", 1157cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1158cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1159cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1160cbe63bfdSIskren Chernev }; 1161cbe63bfdSIskren Chernev 1162cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 1163cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f148, 1164cbe63bfdSIskren Chernev .mnd_width = 16, 1165cbe63bfdSIskren Chernev .hid_width = 5, 1166cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1167cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1168cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 1169cbe63bfdSIskren Chernev }; 1170cbe63bfdSIskren Chernev 1171cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 1172cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s1_clk_src", 1173cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1174cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1175cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1176cbe63bfdSIskren Chernev }; 1177cbe63bfdSIskren Chernev 1178cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 1179cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f278, 1180cbe63bfdSIskren Chernev .mnd_width = 16, 1181cbe63bfdSIskren Chernev .hid_width = 5, 1182cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1183cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1184cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 1185cbe63bfdSIskren Chernev }; 1186cbe63bfdSIskren Chernev 1187cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 1188cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s2_clk_src", 1189cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1190cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1191cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1192cbe63bfdSIskren Chernev }; 1193cbe63bfdSIskren Chernev 1194cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 1195cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f3a8, 1196cbe63bfdSIskren Chernev .mnd_width = 16, 1197cbe63bfdSIskren Chernev .hid_width = 5, 1198cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1199cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1200cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 1201cbe63bfdSIskren Chernev }; 1202cbe63bfdSIskren Chernev 1203cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 1204cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s3_clk_src", 1205cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1206cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1207cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1208cbe63bfdSIskren Chernev }; 1209cbe63bfdSIskren Chernev 1210cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 1211cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f4d8, 1212cbe63bfdSIskren Chernev .mnd_width = 16, 1213cbe63bfdSIskren Chernev .hid_width = 5, 1214cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1215cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1216cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 1217cbe63bfdSIskren Chernev }; 1218cbe63bfdSIskren Chernev 1219cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 1220cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s4_clk_src", 1221cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1222cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1223cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1224cbe63bfdSIskren Chernev }; 1225cbe63bfdSIskren Chernev 1226cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 1227cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f608, 1228cbe63bfdSIskren Chernev .mnd_width = 16, 1229cbe63bfdSIskren Chernev .hid_width = 5, 1230cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1231cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1232cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 1233cbe63bfdSIskren Chernev }; 1234cbe63bfdSIskren Chernev 1235cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 1236cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s5_clk_src", 1237cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1238cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1239cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1240cbe63bfdSIskren Chernev }; 1241cbe63bfdSIskren Chernev 1242cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 1243cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f738, 1244cbe63bfdSIskren Chernev .mnd_width = 16, 1245cbe63bfdSIskren Chernev .hid_width = 5, 1246cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1247cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1248cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 1249cbe63bfdSIskren Chernev }; 1250cbe63bfdSIskren Chernev 1251cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 1252cbe63bfdSIskren Chernev F(144000, P_BI_TCXO, 16, 3, 25), 1253cbe63bfdSIskren Chernev F(400000, P_BI_TCXO, 12, 1, 4), 1254cbe63bfdSIskren Chernev F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3), 1255cbe63bfdSIskren Chernev F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2), 1256cbe63bfdSIskren Chernev F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1257cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1258cbe63bfdSIskren Chernev F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 1259cbe63bfdSIskren Chernev F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 1260cbe63bfdSIskren Chernev { } 1261cbe63bfdSIskren Chernev }; 1262cbe63bfdSIskren Chernev 1263cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 1264cbe63bfdSIskren Chernev .cmd_rcgr = 0x38028, 1265cbe63bfdSIskren Chernev .mnd_width = 8, 1266cbe63bfdSIskren Chernev .hid_width = 5, 1267cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1268cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 1269cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1270cbe63bfdSIskren Chernev .name = "gcc_sdcc1_apps_clk_src", 1271cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1272cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1273cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1274cbe63bfdSIskren Chernev }, 1275cbe63bfdSIskren Chernev }; 1276cbe63bfdSIskren Chernev 1277cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 1278cbe63bfdSIskren Chernev F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1279cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1280cbe63bfdSIskren Chernev F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1281cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1282cbe63bfdSIskren Chernev F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 1283cbe63bfdSIskren Chernev { } 1284cbe63bfdSIskren Chernev }; 1285cbe63bfdSIskren Chernev 1286cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 1287cbe63bfdSIskren Chernev .cmd_rcgr = 0x38010, 1288cbe63bfdSIskren Chernev .mnd_width = 0, 1289cbe63bfdSIskren Chernev .hid_width = 5, 1290cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1291cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 1292cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1293cbe63bfdSIskren Chernev .name = "gcc_sdcc1_ice_core_clk_src", 1294cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1295cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1296cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1297cbe63bfdSIskren Chernev }, 1298cbe63bfdSIskren Chernev }; 1299cbe63bfdSIskren Chernev 1300cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1301cbe63bfdSIskren Chernev F(400000, P_BI_TCXO, 12, 1, 4), 1302cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1303cbe63bfdSIskren Chernev F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1304cbe63bfdSIskren Chernev F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1305cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1306cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1307cbe63bfdSIskren Chernev { } 1308cbe63bfdSIskren Chernev }; 1309cbe63bfdSIskren Chernev 1310cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1311cbe63bfdSIskren Chernev .cmd_rcgr = 0x1e00c, 1312cbe63bfdSIskren Chernev .mnd_width = 8, 1313cbe63bfdSIskren Chernev .hid_width = 5, 1314cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_11, 1315cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1316cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1317cbe63bfdSIskren Chernev .name = "gcc_sdcc2_apps_clk_src", 1318cbe63bfdSIskren Chernev .parent_data = gcc_parents_11, 1319cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_11), 1320cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1321cbe63bfdSIskren Chernev .flags = CLK_OPS_PARENT_ENABLE, 1322cbe63bfdSIskren Chernev }, 1323cbe63bfdSIskren Chernev }; 1324cbe63bfdSIskren Chernev 1325cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1326cbe63bfdSIskren Chernev F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1327cbe63bfdSIskren Chernev F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1328cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1329cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1330cbe63bfdSIskren Chernev F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1331cbe63bfdSIskren Chernev { } 1332cbe63bfdSIskren Chernev }; 1333cbe63bfdSIskren Chernev 1334cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1335cbe63bfdSIskren Chernev .cmd_rcgr = 0x45020, 1336cbe63bfdSIskren Chernev .mnd_width = 8, 1337cbe63bfdSIskren Chernev .hid_width = 5, 1338cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1339cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1340cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1341cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_axi_clk_src", 1342cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1343cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1344cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1345cbe63bfdSIskren Chernev }, 1346cbe63bfdSIskren Chernev }; 1347cbe63bfdSIskren Chernev 1348cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1349cbe63bfdSIskren Chernev F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 1350cbe63bfdSIskren Chernev F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1351cbe63bfdSIskren Chernev F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1352cbe63bfdSIskren Chernev F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 1353cbe63bfdSIskren Chernev { } 1354cbe63bfdSIskren Chernev }; 1355cbe63bfdSIskren Chernev 1356cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1357cbe63bfdSIskren Chernev .cmd_rcgr = 0x45048, 1358cbe63bfdSIskren Chernev .mnd_width = 0, 1359cbe63bfdSIskren Chernev .hid_width = 5, 1360cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1361cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1362cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1363cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_ice_core_clk_src", 1364cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1365cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1366cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1367cbe63bfdSIskren Chernev }, 1368cbe63bfdSIskren Chernev }; 1369cbe63bfdSIskren Chernev 1370cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1371cbe63bfdSIskren Chernev F(9600000, P_BI_TCXO, 2, 0, 0), 1372cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1373cbe63bfdSIskren Chernev { } 1374cbe63bfdSIskren Chernev }; 1375cbe63bfdSIskren Chernev 1376cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1377cbe63bfdSIskren Chernev .cmd_rcgr = 0x4507c, 1378cbe63bfdSIskren Chernev .mnd_width = 0, 1379cbe63bfdSIskren Chernev .hid_width = 5, 1380cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1381cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1382cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1383cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_phy_aux_clk_src", 1384cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1385cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1386cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1387cbe63bfdSIskren Chernev }, 1388cbe63bfdSIskren Chernev }; 1389cbe63bfdSIskren Chernev 1390cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 1391cbe63bfdSIskren Chernev F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 1392cbe63bfdSIskren Chernev F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1393cbe63bfdSIskren Chernev F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1394cbe63bfdSIskren Chernev { } 1395cbe63bfdSIskren Chernev }; 1396cbe63bfdSIskren Chernev 1397cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1398cbe63bfdSIskren Chernev .cmd_rcgr = 0x45060, 1399cbe63bfdSIskren Chernev .mnd_width = 0, 1400cbe63bfdSIskren Chernev .hid_width = 5, 1401cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1402cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 1403cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1404cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_unipro_core_clk_src", 1405cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1406cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1407cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1408cbe63bfdSIskren Chernev }, 1409cbe63bfdSIskren Chernev }; 1410cbe63bfdSIskren Chernev 1411cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1412cbe63bfdSIskren Chernev F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0), 1413cbe63bfdSIskren Chernev F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0), 1414cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1415cbe63bfdSIskren Chernev F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1416cbe63bfdSIskren Chernev { } 1417cbe63bfdSIskren Chernev }; 1418cbe63bfdSIskren Chernev 1419cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1420cbe63bfdSIskren Chernev .cmd_rcgr = 0x1a01c, 1421cbe63bfdSIskren Chernev .mnd_width = 8, 1422cbe63bfdSIskren Chernev .hid_width = 5, 1423cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1424cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1425cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1426cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_master_clk_src", 1427cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1428cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1429cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1430cbe63bfdSIskren Chernev }, 1431cbe63bfdSIskren Chernev }; 1432cbe63bfdSIskren Chernev 1433cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 1434cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1435cbe63bfdSIskren Chernev { } 1436cbe63bfdSIskren Chernev }; 1437cbe63bfdSIskren Chernev 1438cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1439cbe63bfdSIskren Chernev .cmd_rcgr = 0x1a034, 1440cbe63bfdSIskren Chernev .mnd_width = 0, 1441cbe63bfdSIskren Chernev .hid_width = 5, 1442cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1443cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1444cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1445cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_mock_utmi_clk_src", 1446cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1447cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1448cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1449cbe63bfdSIskren Chernev }, 1450cbe63bfdSIskren Chernev }; 1451cbe63bfdSIskren Chernev 1452cbe63bfdSIskren Chernev static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1453cbe63bfdSIskren Chernev .reg = 0x1a04c, 1454cbe63bfdSIskren Chernev .shift = 0, 1455cbe63bfdSIskren Chernev .width = 2, 1456cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data) { 1457cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1458cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]) { 1459cbe63bfdSIskren Chernev &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw }, 1460cbe63bfdSIskren Chernev .num_parents = 1, 1461cbe63bfdSIskren Chernev .ops = &clk_regmap_div_ro_ops, 1462cbe63bfdSIskren Chernev }, 1463cbe63bfdSIskren Chernev }; 1464cbe63bfdSIskren Chernev 1465cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1466cbe63bfdSIskren Chernev .cmd_rcgr = 0x1a060, 1467cbe63bfdSIskren Chernev .mnd_width = 0, 1468cbe63bfdSIskren Chernev .hid_width = 5, 1469cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_12, 1470cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1471cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1472cbe63bfdSIskren Chernev .name = "gcc_usb3_prim_phy_aux_clk_src", 1473cbe63bfdSIskren Chernev .parent_data = gcc_parents_12, 1474cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_12), 1475cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1476cbe63bfdSIskren Chernev }, 1477cbe63bfdSIskren Chernev }; 1478cbe63bfdSIskren Chernev 1479cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = { 1480cbe63bfdSIskren Chernev F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0), 1481cbe63bfdSIskren Chernev F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0), 1482cbe63bfdSIskren Chernev F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0), 1483cbe63bfdSIskren Chernev F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0), 1484cbe63bfdSIskren Chernev { } 1485cbe63bfdSIskren Chernev }; 1486cbe63bfdSIskren Chernev 1487cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_video_venus_clk_src = { 1488cbe63bfdSIskren Chernev .cmd_rcgr = 0x58060, 1489cbe63bfdSIskren Chernev .mnd_width = 0, 1490cbe63bfdSIskren Chernev .hid_width = 5, 1491cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_13, 1492cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_video_venus_clk_src, 1493cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1494cbe63bfdSIskren Chernev .name = "gcc_video_venus_clk_src", 1495cbe63bfdSIskren Chernev .parent_data = gcc_parents_13, 1496cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_13), 1497cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1498cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1499cbe63bfdSIskren Chernev }, 1500cbe63bfdSIskren Chernev }; 1501cbe63bfdSIskren Chernev 1502cbe63bfdSIskren Chernev static struct clk_branch gcc_ahb2phy_csi_clk = { 1503cbe63bfdSIskren Chernev .halt_reg = 0x1d004, 1504cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1505cbe63bfdSIskren Chernev .hwcg_reg = 0x1d004, 1506cbe63bfdSIskren Chernev .hwcg_bit = 1, 1507cbe63bfdSIskren Chernev .clkr = { 1508cbe63bfdSIskren Chernev .enable_reg = 0x1d004, 1509cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1510cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1511cbe63bfdSIskren Chernev .name = "gcc_ahb2phy_csi_clk", 1512cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1513cbe63bfdSIskren Chernev }, 1514cbe63bfdSIskren Chernev }, 1515cbe63bfdSIskren Chernev }; 1516cbe63bfdSIskren Chernev 1517cbe63bfdSIskren Chernev static struct clk_branch gcc_ahb2phy_usb_clk = { 1518cbe63bfdSIskren Chernev .halt_reg = 0x1d008, 1519cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1520cbe63bfdSIskren Chernev .hwcg_reg = 0x1d008, 1521cbe63bfdSIskren Chernev .hwcg_bit = 1, 1522cbe63bfdSIskren Chernev .clkr = { 1523cbe63bfdSIskren Chernev .enable_reg = 0x1d008, 1524cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1525cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1526cbe63bfdSIskren Chernev .name = "gcc_ahb2phy_usb_clk", 1527cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1528cbe63bfdSIskren Chernev }, 1529cbe63bfdSIskren Chernev }, 1530cbe63bfdSIskren Chernev }; 1531cbe63bfdSIskren Chernev 1532cbe63bfdSIskren Chernev static struct clk_branch gcc_bimc_gpu_axi_clk = { 1533cbe63bfdSIskren Chernev .halt_reg = 0x71154, 1534cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 1535cbe63bfdSIskren Chernev .hwcg_reg = 0x71154, 1536cbe63bfdSIskren Chernev .hwcg_bit = 1, 1537cbe63bfdSIskren Chernev .clkr = { 1538cbe63bfdSIskren Chernev .enable_reg = 0x71154, 1539cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1540cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1541cbe63bfdSIskren Chernev .name = "gcc_bimc_gpu_axi_clk", 1542cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1543cbe63bfdSIskren Chernev }, 1544cbe63bfdSIskren Chernev }, 1545cbe63bfdSIskren Chernev }; 1546cbe63bfdSIskren Chernev 1547cbe63bfdSIskren Chernev static struct clk_branch gcc_boot_rom_ahb_clk = { 1548cbe63bfdSIskren Chernev .halt_reg = 0x23004, 1549cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 1550cbe63bfdSIskren Chernev .hwcg_reg = 0x23004, 1551cbe63bfdSIskren Chernev .hwcg_bit = 1, 1552cbe63bfdSIskren Chernev .clkr = { 1553cbe63bfdSIskren Chernev .enable_reg = 0x79004, 1554cbe63bfdSIskren Chernev .enable_mask = BIT(10), 1555cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1556cbe63bfdSIskren Chernev .name = "gcc_boot_rom_ahb_clk", 1557cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1558cbe63bfdSIskren Chernev }, 1559cbe63bfdSIskren Chernev }, 1560cbe63bfdSIskren Chernev }; 1561cbe63bfdSIskren Chernev 1562cbe63bfdSIskren Chernev static struct clk_branch gcc_cam_throttle_nrt_clk = { 1563cbe63bfdSIskren Chernev .halt_reg = 0x17070, 1564cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 1565cbe63bfdSIskren Chernev .hwcg_reg = 0x17070, 1566cbe63bfdSIskren Chernev .hwcg_bit = 1, 1567cbe63bfdSIskren Chernev .clkr = { 1568cbe63bfdSIskren Chernev .enable_reg = 0x79004, 1569cbe63bfdSIskren Chernev .enable_mask = BIT(27), 1570cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1571cbe63bfdSIskren Chernev .name = "gcc_cam_throttle_nrt_clk", 1572cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1573cbe63bfdSIskren Chernev }, 1574cbe63bfdSIskren Chernev }, 1575cbe63bfdSIskren Chernev }; 1576cbe63bfdSIskren Chernev 1577cbe63bfdSIskren Chernev static struct clk_branch gcc_cam_throttle_rt_clk = { 1578cbe63bfdSIskren Chernev .halt_reg = 0x1706c, 1579cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 1580cbe63bfdSIskren Chernev .hwcg_reg = 0x1706c, 1581cbe63bfdSIskren Chernev .hwcg_bit = 1, 1582cbe63bfdSIskren Chernev .clkr = { 1583cbe63bfdSIskren Chernev .enable_reg = 0x79004, 1584cbe63bfdSIskren Chernev .enable_mask = BIT(26), 1585cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1586cbe63bfdSIskren Chernev .name = "gcc_cam_throttle_rt_clk", 1587cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1588cbe63bfdSIskren Chernev }, 1589cbe63bfdSIskren Chernev }, 1590cbe63bfdSIskren Chernev }; 1591cbe63bfdSIskren Chernev 1592cbe63bfdSIskren Chernev static struct clk_branch gcc_camera_ahb_clk = { 1593cbe63bfdSIskren Chernev .halt_reg = 0x17008, 1594cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 1595cbe63bfdSIskren Chernev .hwcg_reg = 0x17008, 1596cbe63bfdSIskren Chernev .hwcg_bit = 1, 1597cbe63bfdSIskren Chernev .clkr = { 1598cbe63bfdSIskren Chernev .enable_reg = 0x17008, 1599cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1600cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1601cbe63bfdSIskren Chernev .name = "gcc_camera_ahb_clk", 1602cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 1603cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1604cbe63bfdSIskren Chernev }, 1605cbe63bfdSIskren Chernev }, 1606cbe63bfdSIskren Chernev }; 1607cbe63bfdSIskren Chernev 1608cbe63bfdSIskren Chernev static struct clk_branch gcc_camera_xo_clk = { 1609cbe63bfdSIskren Chernev .halt_reg = 0x17028, 1610cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1611cbe63bfdSIskren Chernev .clkr = { 1612cbe63bfdSIskren Chernev .enable_reg = 0x17028, 1613cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1614cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1615cbe63bfdSIskren Chernev .name = "gcc_camera_xo_clk", 1616cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 1617cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1618cbe63bfdSIskren Chernev }, 1619cbe63bfdSIskren Chernev }, 1620cbe63bfdSIskren Chernev }; 1621cbe63bfdSIskren Chernev 1622cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_axi_clk = { 1623cbe63bfdSIskren Chernev .halt_reg = 0x58044, 1624cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1625cbe63bfdSIskren Chernev .clkr = { 1626cbe63bfdSIskren Chernev .enable_reg = 0x58044, 1627cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1628cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1629cbe63bfdSIskren Chernev .name = "gcc_camss_axi_clk", 1630cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1631cbe63bfdSIskren Chernev &gcc_camss_axi_clk_src.clkr.hw, 1632cbe63bfdSIskren Chernev }, 1633cbe63bfdSIskren Chernev .num_parents = 1, 1634cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1635cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1636cbe63bfdSIskren Chernev }, 1637cbe63bfdSIskren Chernev }, 1638cbe63bfdSIskren Chernev }; 1639cbe63bfdSIskren Chernev 1640cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_camnoc_atb_clk = { 1641cbe63bfdSIskren Chernev .halt_reg = 0x5804c, 1642cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 1643cbe63bfdSIskren Chernev .hwcg_reg = 0x5804c, 1644cbe63bfdSIskren Chernev .hwcg_bit = 1, 1645cbe63bfdSIskren Chernev .clkr = { 1646cbe63bfdSIskren Chernev .enable_reg = 0x5804c, 1647cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1648cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1649cbe63bfdSIskren Chernev .name = "gcc_camss_camnoc_atb_clk", 1650cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1651cbe63bfdSIskren Chernev }, 1652cbe63bfdSIskren Chernev }, 1653cbe63bfdSIskren Chernev }; 1654cbe63bfdSIskren Chernev 1655cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_camnoc_nts_xo_clk = { 1656cbe63bfdSIskren Chernev .halt_reg = 0x58050, 1657cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 1658cbe63bfdSIskren Chernev .hwcg_reg = 0x58050, 1659cbe63bfdSIskren Chernev .hwcg_bit = 1, 1660cbe63bfdSIskren Chernev .clkr = { 1661cbe63bfdSIskren Chernev .enable_reg = 0x58050, 1662cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1663cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1664cbe63bfdSIskren Chernev .name = "gcc_camss_camnoc_nts_xo_clk", 1665cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1666cbe63bfdSIskren Chernev }, 1667cbe63bfdSIskren Chernev }, 1668cbe63bfdSIskren Chernev }; 1669cbe63bfdSIskren Chernev 1670cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_cci_0_clk = { 1671cbe63bfdSIskren Chernev .halt_reg = 0x56018, 1672cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1673cbe63bfdSIskren Chernev .clkr = { 1674cbe63bfdSIskren Chernev .enable_reg = 0x56018, 1675cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1676cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1677cbe63bfdSIskren Chernev .name = "gcc_camss_cci_0_clk", 1678cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1679cbe63bfdSIskren Chernev &gcc_camss_cci_clk_src.clkr.hw, 1680cbe63bfdSIskren Chernev }, 1681cbe63bfdSIskren Chernev .num_parents = 1, 1682cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1683cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1684cbe63bfdSIskren Chernev }, 1685cbe63bfdSIskren Chernev }, 1686cbe63bfdSIskren Chernev }; 1687cbe63bfdSIskren Chernev 1688cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_cphy_0_clk = { 1689cbe63bfdSIskren Chernev .halt_reg = 0x52088, 1690cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1691cbe63bfdSIskren Chernev .clkr = { 1692cbe63bfdSIskren Chernev .enable_reg = 0x52088, 1693cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1694cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1695cbe63bfdSIskren Chernev .name = "gcc_camss_cphy_0_clk", 1696cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1697cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1698cbe63bfdSIskren Chernev }, 1699cbe63bfdSIskren Chernev .num_parents = 1, 1700cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1701cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1702cbe63bfdSIskren Chernev }, 1703cbe63bfdSIskren Chernev }, 1704cbe63bfdSIskren Chernev }; 1705cbe63bfdSIskren Chernev 1706cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_cphy_1_clk = { 1707cbe63bfdSIskren Chernev .halt_reg = 0x5208c, 1708cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1709cbe63bfdSIskren Chernev .clkr = { 1710cbe63bfdSIskren Chernev .enable_reg = 0x5208c, 1711cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1712cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1713cbe63bfdSIskren Chernev .name = "gcc_camss_cphy_1_clk", 1714cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1715cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1716cbe63bfdSIskren Chernev }, 1717cbe63bfdSIskren Chernev .num_parents = 1, 1718cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1719cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1720cbe63bfdSIskren Chernev }, 1721cbe63bfdSIskren Chernev }, 1722cbe63bfdSIskren Chernev }; 1723cbe63bfdSIskren Chernev 1724cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_cphy_2_clk = { 1725cbe63bfdSIskren Chernev .halt_reg = 0x52090, 1726cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1727cbe63bfdSIskren Chernev .clkr = { 1728cbe63bfdSIskren Chernev .enable_reg = 0x52090, 1729cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1730cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1731cbe63bfdSIskren Chernev .name = "gcc_camss_cphy_2_clk", 1732cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1733cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1734cbe63bfdSIskren Chernev }, 1735cbe63bfdSIskren Chernev .num_parents = 1, 1736cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1737cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1738cbe63bfdSIskren Chernev }, 1739cbe63bfdSIskren Chernev }, 1740cbe63bfdSIskren Chernev }; 1741cbe63bfdSIskren Chernev 1742cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_csi0phytimer_clk = { 1743cbe63bfdSIskren Chernev .halt_reg = 0x59018, 1744cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1745cbe63bfdSIskren Chernev .clkr = { 1746cbe63bfdSIskren Chernev .enable_reg = 0x59018, 1747cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1748cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1749cbe63bfdSIskren Chernev .name = "gcc_camss_csi0phytimer_clk", 1750cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1751cbe63bfdSIskren Chernev &gcc_camss_csi0phytimer_clk_src.clkr.hw, 1752cbe63bfdSIskren Chernev }, 1753cbe63bfdSIskren Chernev .num_parents = 1, 1754cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1755cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1756cbe63bfdSIskren Chernev }, 1757cbe63bfdSIskren Chernev }, 1758cbe63bfdSIskren Chernev }; 1759cbe63bfdSIskren Chernev 1760cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_csi1phytimer_clk = { 1761cbe63bfdSIskren Chernev .halt_reg = 0x59034, 1762cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1763cbe63bfdSIskren Chernev .clkr = { 1764cbe63bfdSIskren Chernev .enable_reg = 0x59034, 1765cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1766cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1767cbe63bfdSIskren Chernev .name = "gcc_camss_csi1phytimer_clk", 1768cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1769cbe63bfdSIskren Chernev &gcc_camss_csi1phytimer_clk_src.clkr.hw, 1770cbe63bfdSIskren Chernev }, 1771cbe63bfdSIskren Chernev .num_parents = 1, 1772cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1773cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1774cbe63bfdSIskren Chernev }, 1775cbe63bfdSIskren Chernev }, 1776cbe63bfdSIskren Chernev }; 1777cbe63bfdSIskren Chernev 1778cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_csi2phytimer_clk = { 1779cbe63bfdSIskren Chernev .halt_reg = 0x59050, 1780cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1781cbe63bfdSIskren Chernev .clkr = { 1782cbe63bfdSIskren Chernev .enable_reg = 0x59050, 1783cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1784cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1785cbe63bfdSIskren Chernev .name = "gcc_camss_csi2phytimer_clk", 1786cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1787cbe63bfdSIskren Chernev &gcc_camss_csi2phytimer_clk_src.clkr.hw, 1788cbe63bfdSIskren Chernev }, 1789cbe63bfdSIskren Chernev .num_parents = 1, 1790cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1791cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1792cbe63bfdSIskren Chernev }, 1793cbe63bfdSIskren Chernev }, 1794cbe63bfdSIskren Chernev }; 1795cbe63bfdSIskren Chernev 1796cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_mclk0_clk = { 1797cbe63bfdSIskren Chernev .halt_reg = 0x51018, 1798cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1799cbe63bfdSIskren Chernev .clkr = { 1800cbe63bfdSIskren Chernev .enable_reg = 0x51018, 1801cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1802cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1803cbe63bfdSIskren Chernev .name = "gcc_camss_mclk0_clk", 1804cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1805cbe63bfdSIskren Chernev &gcc_camss_mclk0_clk_src.clkr.hw, 1806cbe63bfdSIskren Chernev }, 1807cbe63bfdSIskren Chernev .num_parents = 1, 1808cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1809cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1810cbe63bfdSIskren Chernev }, 1811cbe63bfdSIskren Chernev }, 1812cbe63bfdSIskren Chernev }; 1813cbe63bfdSIskren Chernev 1814cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_mclk1_clk = { 1815cbe63bfdSIskren Chernev .halt_reg = 0x51034, 1816cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1817cbe63bfdSIskren Chernev .clkr = { 1818cbe63bfdSIskren Chernev .enable_reg = 0x51034, 1819cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1820cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1821cbe63bfdSIskren Chernev .name = "gcc_camss_mclk1_clk", 1822cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1823cbe63bfdSIskren Chernev &gcc_camss_mclk1_clk_src.clkr.hw, 1824cbe63bfdSIskren Chernev }, 1825cbe63bfdSIskren Chernev .num_parents = 1, 1826cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1827cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1828cbe63bfdSIskren Chernev }, 1829cbe63bfdSIskren Chernev }, 1830cbe63bfdSIskren Chernev }; 1831cbe63bfdSIskren Chernev 1832cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_mclk2_clk = { 1833cbe63bfdSIskren Chernev .halt_reg = 0x51050, 1834cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1835cbe63bfdSIskren Chernev .clkr = { 1836cbe63bfdSIskren Chernev .enable_reg = 0x51050, 1837cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1838cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1839cbe63bfdSIskren Chernev .name = "gcc_camss_mclk2_clk", 1840cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1841cbe63bfdSIskren Chernev &gcc_camss_mclk2_clk_src.clkr.hw, 1842cbe63bfdSIskren Chernev }, 1843cbe63bfdSIskren Chernev .num_parents = 1, 1844cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1845cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1846cbe63bfdSIskren Chernev }, 1847cbe63bfdSIskren Chernev }, 1848cbe63bfdSIskren Chernev }; 1849cbe63bfdSIskren Chernev 1850cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_mclk3_clk = { 1851cbe63bfdSIskren Chernev .halt_reg = 0x5106c, 1852cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1853cbe63bfdSIskren Chernev .clkr = { 1854cbe63bfdSIskren Chernev .enable_reg = 0x5106c, 1855cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1856cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1857cbe63bfdSIskren Chernev .name = "gcc_camss_mclk3_clk", 1858cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1859cbe63bfdSIskren Chernev &gcc_camss_mclk3_clk_src.clkr.hw, 1860cbe63bfdSIskren Chernev }, 1861cbe63bfdSIskren Chernev .num_parents = 1, 1862cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1863cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1864cbe63bfdSIskren Chernev }, 1865cbe63bfdSIskren Chernev }, 1866cbe63bfdSIskren Chernev }; 1867cbe63bfdSIskren Chernev 1868cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_nrt_axi_clk = { 1869cbe63bfdSIskren Chernev .halt_reg = 0x58054, 1870cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1871cbe63bfdSIskren Chernev .clkr = { 1872cbe63bfdSIskren Chernev .enable_reg = 0x58054, 1873cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1874cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1875cbe63bfdSIskren Chernev .name = "gcc_camss_nrt_axi_clk", 1876cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1877cbe63bfdSIskren Chernev }, 1878cbe63bfdSIskren Chernev }, 1879cbe63bfdSIskren Chernev }; 1880cbe63bfdSIskren Chernev 1881cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_ope_ahb_clk = { 1882cbe63bfdSIskren Chernev .halt_reg = 0x5503c, 1883cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1884cbe63bfdSIskren Chernev .clkr = { 1885cbe63bfdSIskren Chernev .enable_reg = 0x5503c, 1886cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1887cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1888cbe63bfdSIskren Chernev .name = "gcc_camss_ope_ahb_clk", 1889cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1890cbe63bfdSIskren Chernev &gcc_camss_ope_ahb_clk_src.clkr.hw, 1891cbe63bfdSIskren Chernev }, 1892cbe63bfdSIskren Chernev .num_parents = 1, 1893cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1894cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1895cbe63bfdSIskren Chernev }, 1896cbe63bfdSIskren Chernev }, 1897cbe63bfdSIskren Chernev }; 1898cbe63bfdSIskren Chernev 1899cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_ope_clk = { 1900cbe63bfdSIskren Chernev .halt_reg = 0x5501c, 1901cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1902cbe63bfdSIskren Chernev .clkr = { 1903cbe63bfdSIskren Chernev .enable_reg = 0x5501c, 1904cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1905cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1906cbe63bfdSIskren Chernev .name = "gcc_camss_ope_clk", 1907cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1908cbe63bfdSIskren Chernev &gcc_camss_ope_clk_src.clkr.hw, 1909cbe63bfdSIskren Chernev }, 1910cbe63bfdSIskren Chernev .num_parents = 1, 1911cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1912cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1913cbe63bfdSIskren Chernev }, 1914cbe63bfdSIskren Chernev }, 1915cbe63bfdSIskren Chernev }; 1916cbe63bfdSIskren Chernev 1917cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_rt_axi_clk = { 1918cbe63bfdSIskren Chernev .halt_reg = 0x5805c, 1919cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1920cbe63bfdSIskren Chernev .clkr = { 1921cbe63bfdSIskren Chernev .enable_reg = 0x5805c, 1922cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1923cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1924cbe63bfdSIskren Chernev .name = "gcc_camss_rt_axi_clk", 1925cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1926cbe63bfdSIskren Chernev }, 1927cbe63bfdSIskren Chernev }, 1928cbe63bfdSIskren Chernev }; 1929cbe63bfdSIskren Chernev 1930cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_0_clk = { 1931cbe63bfdSIskren Chernev .halt_reg = 0x5201c, 1932cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1933cbe63bfdSIskren Chernev .clkr = { 1934cbe63bfdSIskren Chernev .enable_reg = 0x5201c, 1935cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1936cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1937cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_0_clk", 1938cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1939cbe63bfdSIskren Chernev &gcc_camss_tfe_0_clk_src.clkr.hw, 1940cbe63bfdSIskren Chernev }, 1941cbe63bfdSIskren Chernev .num_parents = 1, 1942cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1943cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1944cbe63bfdSIskren Chernev }, 1945cbe63bfdSIskren Chernev }, 1946cbe63bfdSIskren Chernev }; 1947cbe63bfdSIskren Chernev 1948cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = { 1949cbe63bfdSIskren Chernev .halt_reg = 0x5207c, 1950cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1951cbe63bfdSIskren Chernev .clkr = { 1952cbe63bfdSIskren Chernev .enable_reg = 0x5207c, 1953cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1954cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1955cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_0_cphy_rx_clk", 1956cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1957cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1958cbe63bfdSIskren Chernev }, 1959cbe63bfdSIskren Chernev .num_parents = 1, 1960cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1961cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1962cbe63bfdSIskren Chernev }, 1963cbe63bfdSIskren Chernev }, 1964cbe63bfdSIskren Chernev }; 1965cbe63bfdSIskren Chernev 1966cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_0_csid_clk = { 1967cbe63bfdSIskren Chernev .halt_reg = 0x520ac, 1968cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1969cbe63bfdSIskren Chernev .clkr = { 1970cbe63bfdSIskren Chernev .enable_reg = 0x520ac, 1971cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1972cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1973cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_0_csid_clk", 1974cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1975cbe63bfdSIskren Chernev &gcc_camss_tfe_0_csid_clk_src.clkr.hw, 1976cbe63bfdSIskren Chernev }, 1977cbe63bfdSIskren Chernev .num_parents = 1, 1978cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1979cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1980cbe63bfdSIskren Chernev }, 1981cbe63bfdSIskren Chernev }, 1982cbe63bfdSIskren Chernev }; 1983cbe63bfdSIskren Chernev 1984cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_1_clk = { 1985cbe63bfdSIskren Chernev .halt_reg = 0x5203c, 1986cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1987cbe63bfdSIskren Chernev .clkr = { 1988cbe63bfdSIskren Chernev .enable_reg = 0x5203c, 1989cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1990cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1991cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_1_clk", 1992cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1993cbe63bfdSIskren Chernev &gcc_camss_tfe_1_clk_src.clkr.hw, 1994cbe63bfdSIskren Chernev }, 1995cbe63bfdSIskren Chernev .num_parents = 1, 1996cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1997cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1998cbe63bfdSIskren Chernev }, 1999cbe63bfdSIskren Chernev }, 2000cbe63bfdSIskren Chernev }; 2001cbe63bfdSIskren Chernev 2002cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = { 2003cbe63bfdSIskren Chernev .halt_reg = 0x52080, 2004cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2005cbe63bfdSIskren Chernev .clkr = { 2006cbe63bfdSIskren Chernev .enable_reg = 0x52080, 2007cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2008cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2009cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_1_cphy_rx_clk", 2010cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2011cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2012cbe63bfdSIskren Chernev }, 2013cbe63bfdSIskren Chernev .num_parents = 1, 2014cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2015cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2016cbe63bfdSIskren Chernev }, 2017cbe63bfdSIskren Chernev }, 2018cbe63bfdSIskren Chernev }; 2019cbe63bfdSIskren Chernev 2020cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_1_csid_clk = { 2021cbe63bfdSIskren Chernev .halt_reg = 0x520cc, 2022cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2023cbe63bfdSIskren Chernev .clkr = { 2024cbe63bfdSIskren Chernev .enable_reg = 0x520cc, 2025cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2026cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2027cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_1_csid_clk", 2028cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2029cbe63bfdSIskren Chernev &gcc_camss_tfe_1_csid_clk_src.clkr.hw, 2030cbe63bfdSIskren Chernev }, 2031cbe63bfdSIskren Chernev .num_parents = 1, 2032cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2033cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2034cbe63bfdSIskren Chernev }, 2035cbe63bfdSIskren Chernev }, 2036cbe63bfdSIskren Chernev }; 2037cbe63bfdSIskren Chernev 2038cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_2_clk = { 2039cbe63bfdSIskren Chernev .halt_reg = 0x5205c, 2040cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2041cbe63bfdSIskren Chernev .clkr = { 2042cbe63bfdSIskren Chernev .enable_reg = 0x5205c, 2043cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2044cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2045cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_2_clk", 2046cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2047cbe63bfdSIskren Chernev &gcc_camss_tfe_2_clk_src.clkr.hw, 2048cbe63bfdSIskren Chernev }, 2049cbe63bfdSIskren Chernev .num_parents = 1, 2050cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2051cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2052cbe63bfdSIskren Chernev }, 2053cbe63bfdSIskren Chernev }, 2054cbe63bfdSIskren Chernev }; 2055cbe63bfdSIskren Chernev 2056cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_2_cphy_rx_clk = { 2057cbe63bfdSIskren Chernev .halt_reg = 0x52084, 2058cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2059cbe63bfdSIskren Chernev .clkr = { 2060cbe63bfdSIskren Chernev .enable_reg = 0x52084, 2061cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2062cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2063cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_2_cphy_rx_clk", 2064cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2065cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2066cbe63bfdSIskren Chernev }, 2067cbe63bfdSIskren Chernev .num_parents = 1, 2068cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2069cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2070cbe63bfdSIskren Chernev }, 2071cbe63bfdSIskren Chernev }, 2072cbe63bfdSIskren Chernev }; 2073cbe63bfdSIskren Chernev 2074cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_2_csid_clk = { 2075cbe63bfdSIskren Chernev .halt_reg = 0x520ec, 2076cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2077cbe63bfdSIskren Chernev .clkr = { 2078cbe63bfdSIskren Chernev .enable_reg = 0x520ec, 2079cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2080cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2081cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_2_csid_clk", 2082cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2083cbe63bfdSIskren Chernev &gcc_camss_tfe_2_csid_clk_src.clkr.hw, 2084cbe63bfdSIskren Chernev }, 2085cbe63bfdSIskren Chernev .num_parents = 1, 2086cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2087cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2088cbe63bfdSIskren Chernev }, 2089cbe63bfdSIskren Chernev }, 2090cbe63bfdSIskren Chernev }; 2091cbe63bfdSIskren Chernev 2092cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_top_ahb_clk = { 2093cbe63bfdSIskren Chernev .halt_reg = 0x58028, 2094cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2095cbe63bfdSIskren Chernev .clkr = { 2096cbe63bfdSIskren Chernev .enable_reg = 0x58028, 2097cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2098cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2099cbe63bfdSIskren Chernev .name = "gcc_camss_top_ahb_clk", 2100cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2101cbe63bfdSIskren Chernev &gcc_camss_top_ahb_clk_src.clkr.hw, 2102cbe63bfdSIskren Chernev }, 2103cbe63bfdSIskren Chernev .num_parents = 1, 2104cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2105cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2106cbe63bfdSIskren Chernev }, 2107cbe63bfdSIskren Chernev }, 2108cbe63bfdSIskren Chernev }; 2109cbe63bfdSIskren Chernev 2110cbe63bfdSIskren Chernev static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 2111cbe63bfdSIskren Chernev .halt_reg = 0x1a084, 2112cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2113cbe63bfdSIskren Chernev .hwcg_reg = 0x1a084, 2114cbe63bfdSIskren Chernev .hwcg_bit = 1, 2115cbe63bfdSIskren Chernev .clkr = { 2116cbe63bfdSIskren Chernev .enable_reg = 0x1a084, 2117cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2118cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2119cbe63bfdSIskren Chernev .name = "gcc_cfg_noc_usb3_prim_axi_clk", 2120cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2121cbe63bfdSIskren Chernev &gcc_usb30_prim_master_clk_src.clkr.hw, 2122cbe63bfdSIskren Chernev }, 2123cbe63bfdSIskren Chernev .num_parents = 1, 2124cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2125cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2126cbe63bfdSIskren Chernev }, 2127cbe63bfdSIskren Chernev }, 2128cbe63bfdSIskren Chernev }; 2129cbe63bfdSIskren Chernev 2130cbe63bfdSIskren Chernev static struct clk_branch gcc_cpuss_gnoc_clk = { 2131cbe63bfdSIskren Chernev .halt_reg = 0x2b004, 2132cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2133cbe63bfdSIskren Chernev .hwcg_reg = 0x2b004, 2134cbe63bfdSIskren Chernev .hwcg_bit = 1, 2135cbe63bfdSIskren Chernev .clkr = { 2136cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2137cbe63bfdSIskren Chernev .enable_mask = BIT(22), 2138cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2139cbe63bfdSIskren Chernev .name = "gcc_cpuss_gnoc_clk", 2140cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 2141cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2142cbe63bfdSIskren Chernev }, 2143cbe63bfdSIskren Chernev }, 2144cbe63bfdSIskren Chernev }; 2145cbe63bfdSIskren Chernev 2146cbe63bfdSIskren Chernev static struct clk_branch gcc_disp_ahb_clk = { 2147cbe63bfdSIskren Chernev .halt_reg = 0x1700c, 2148cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2149cbe63bfdSIskren Chernev .hwcg_reg = 0x1700c, 2150cbe63bfdSIskren Chernev .hwcg_bit = 1, 2151cbe63bfdSIskren Chernev .clkr = { 2152cbe63bfdSIskren Chernev .enable_reg = 0x1700c, 2153cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2154cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2155cbe63bfdSIskren Chernev .name = "gcc_disp_ahb_clk", 2156cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 2157cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2158cbe63bfdSIskren Chernev }, 2159cbe63bfdSIskren Chernev }, 2160cbe63bfdSIskren Chernev }; 2161cbe63bfdSIskren Chernev 2162cbe63bfdSIskren Chernev static struct clk_regmap_div gcc_disp_gpll0_clk_src = { 2163cbe63bfdSIskren Chernev .reg = 0x17058, 2164cbe63bfdSIskren Chernev .shift = 0, 2165cbe63bfdSIskren Chernev .width = 2, 2166cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data) { 2167cbe63bfdSIskren Chernev .name = "gcc_disp_gpll0_clk_src", 2168cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 2169cbe63bfdSIskren Chernev .num_parents = 1, 2170cbe63bfdSIskren Chernev .ops = &clk_regmap_div_ops, 2171cbe63bfdSIskren Chernev }, 2172cbe63bfdSIskren Chernev }; 2173cbe63bfdSIskren Chernev 2174cbe63bfdSIskren Chernev static struct clk_branch gcc_disp_gpll0_div_clk_src = { 2175cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 2176cbe63bfdSIskren Chernev .clkr = { 2177cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2178cbe63bfdSIskren Chernev .enable_mask = BIT(20), 2179cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2180cbe63bfdSIskren Chernev .name = "gcc_disp_gpll0_div_clk_src", 2181cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2182cbe63bfdSIskren Chernev &gcc_disp_gpll0_clk_src.clkr.hw, 2183cbe63bfdSIskren Chernev }, 2184cbe63bfdSIskren Chernev .num_parents = 1, 2185cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2186cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2187cbe63bfdSIskren Chernev }, 2188cbe63bfdSIskren Chernev }, 2189cbe63bfdSIskren Chernev }; 2190cbe63bfdSIskren Chernev 2191cbe63bfdSIskren Chernev static struct clk_branch gcc_disp_hf_axi_clk = { 2192cbe63bfdSIskren Chernev .halt_reg = 0x17020, 2193cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2194cbe63bfdSIskren Chernev .hwcg_reg = 0x17020, 2195cbe63bfdSIskren Chernev .hwcg_bit = 1, 2196cbe63bfdSIskren Chernev .clkr = { 2197cbe63bfdSIskren Chernev .enable_reg = 0x17020, 2198cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2199cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2200cbe63bfdSIskren Chernev .name = "gcc_disp_hf_axi_clk", 2201cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2202cbe63bfdSIskren Chernev }, 2203cbe63bfdSIskren Chernev }, 2204cbe63bfdSIskren Chernev }; 2205cbe63bfdSIskren Chernev 2206cbe63bfdSIskren Chernev static struct clk_branch gcc_disp_throttle_core_clk = { 2207cbe63bfdSIskren Chernev .halt_reg = 0x17064, 2208cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2209cbe63bfdSIskren Chernev .hwcg_reg = 0x17064, 2210cbe63bfdSIskren Chernev .hwcg_bit = 1, 2211cbe63bfdSIskren Chernev .clkr = { 2212cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2213cbe63bfdSIskren Chernev .enable_mask = BIT(5), 2214cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2215cbe63bfdSIskren Chernev .name = "gcc_disp_throttle_core_clk", 2216cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2217cbe63bfdSIskren Chernev }, 2218cbe63bfdSIskren Chernev }, 2219cbe63bfdSIskren Chernev }; 2220cbe63bfdSIskren Chernev 2221cbe63bfdSIskren Chernev static struct clk_branch gcc_disp_xo_clk = { 2222cbe63bfdSIskren Chernev .halt_reg = 0x1702c, 2223cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2224cbe63bfdSIskren Chernev .clkr = { 2225cbe63bfdSIskren Chernev .enable_reg = 0x1702c, 2226cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2227cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2228cbe63bfdSIskren Chernev .name = "gcc_disp_xo_clk", 2229cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 2230cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2231cbe63bfdSIskren Chernev }, 2232cbe63bfdSIskren Chernev }, 2233cbe63bfdSIskren Chernev }; 2234cbe63bfdSIskren Chernev 2235cbe63bfdSIskren Chernev static struct clk_branch gcc_gp1_clk = { 2236cbe63bfdSIskren Chernev .halt_reg = 0x4d000, 2237cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2238cbe63bfdSIskren Chernev .clkr = { 2239cbe63bfdSIskren Chernev .enable_reg = 0x4d000, 2240cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2241cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2242cbe63bfdSIskren Chernev .name = "gcc_gp1_clk", 2243cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2244cbe63bfdSIskren Chernev &gcc_gp1_clk_src.clkr.hw, 2245cbe63bfdSIskren Chernev }, 2246cbe63bfdSIskren Chernev .num_parents = 1, 2247cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2248cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2249cbe63bfdSIskren Chernev }, 2250cbe63bfdSIskren Chernev }, 2251cbe63bfdSIskren Chernev }; 2252cbe63bfdSIskren Chernev 2253cbe63bfdSIskren Chernev static struct clk_branch gcc_gp2_clk = { 2254cbe63bfdSIskren Chernev .halt_reg = 0x4e000, 2255cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2256cbe63bfdSIskren Chernev .clkr = { 2257cbe63bfdSIskren Chernev .enable_reg = 0x4e000, 2258cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2259cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2260cbe63bfdSIskren Chernev .name = "gcc_gp2_clk", 2261cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2262cbe63bfdSIskren Chernev &gcc_gp2_clk_src.clkr.hw, 2263cbe63bfdSIskren Chernev }, 2264cbe63bfdSIskren Chernev .num_parents = 1, 2265cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2266cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2267cbe63bfdSIskren Chernev }, 2268cbe63bfdSIskren Chernev }, 2269cbe63bfdSIskren Chernev }; 2270cbe63bfdSIskren Chernev 2271cbe63bfdSIskren Chernev static struct clk_branch gcc_gp3_clk = { 2272cbe63bfdSIskren Chernev .halt_reg = 0x4f000, 2273cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2274cbe63bfdSIskren Chernev .clkr = { 2275cbe63bfdSIskren Chernev .enable_reg = 0x4f000, 2276cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2277cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2278cbe63bfdSIskren Chernev .name = "gcc_gp3_clk", 2279cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2280cbe63bfdSIskren Chernev &gcc_gp3_clk_src.clkr.hw, 2281cbe63bfdSIskren Chernev }, 2282cbe63bfdSIskren Chernev .num_parents = 1, 2283cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2284cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2285cbe63bfdSIskren Chernev }, 2286cbe63bfdSIskren Chernev }, 2287cbe63bfdSIskren Chernev }; 2288cbe63bfdSIskren Chernev 2289cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_cfg_ahb_clk = { 2290cbe63bfdSIskren Chernev .halt_reg = 0x36004, 2291cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2292cbe63bfdSIskren Chernev .hwcg_reg = 0x36004, 2293cbe63bfdSIskren Chernev .hwcg_bit = 1, 2294cbe63bfdSIskren Chernev .clkr = { 2295cbe63bfdSIskren Chernev .enable_reg = 0x36004, 2296cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2297cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2298cbe63bfdSIskren Chernev .name = "gcc_gpu_cfg_ahb_clk", 2299cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 2300cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2301cbe63bfdSIskren Chernev }, 2302cbe63bfdSIskren Chernev }, 2303cbe63bfdSIskren Chernev }; 2304cbe63bfdSIskren Chernev 2305cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_gpll0_clk_src = { 2306cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 2307cbe63bfdSIskren Chernev .clkr = { 2308cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2309cbe63bfdSIskren Chernev .enable_mask = BIT(15), 2310cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2311cbe63bfdSIskren Chernev .name = "gcc_gpu_gpll0_clk_src", 2312cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2313cbe63bfdSIskren Chernev &gpll0.clkr.hw, 2314cbe63bfdSIskren Chernev }, 2315cbe63bfdSIskren Chernev .num_parents = 1, 2316cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2317cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2318cbe63bfdSIskren Chernev }, 2319cbe63bfdSIskren Chernev }, 2320cbe63bfdSIskren Chernev }; 2321cbe63bfdSIskren Chernev 2322cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 2323cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 2324cbe63bfdSIskren Chernev .clkr = { 2325cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2326cbe63bfdSIskren Chernev .enable_mask = BIT(16), 2327cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2328cbe63bfdSIskren Chernev .name = "gcc_gpu_gpll0_div_clk_src", 2329cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2330cbe63bfdSIskren Chernev &gpll0_out_aux2.clkr.hw, 2331cbe63bfdSIskren Chernev }, 2332cbe63bfdSIskren Chernev .num_parents = 1, 2333cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2334cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2335cbe63bfdSIskren Chernev }, 2336cbe63bfdSIskren Chernev }, 2337cbe63bfdSIskren Chernev }; 2338cbe63bfdSIskren Chernev 2339cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_iref_clk = { 2340cbe63bfdSIskren Chernev .halt_reg = 0x36100, 2341cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 2342cbe63bfdSIskren Chernev .clkr = { 2343cbe63bfdSIskren Chernev .enable_reg = 0x36100, 2344cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2345cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2346cbe63bfdSIskren Chernev .name = "gcc_gpu_iref_clk", 2347cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2348cbe63bfdSIskren Chernev }, 2349cbe63bfdSIskren Chernev }, 2350cbe63bfdSIskren Chernev }; 2351cbe63bfdSIskren Chernev 2352cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 2353cbe63bfdSIskren Chernev .halt_reg = 0x3600c, 2354cbe63bfdSIskren Chernev .halt_check = BRANCH_VOTED, 2355cbe63bfdSIskren Chernev .hwcg_reg = 0x3600c, 2356cbe63bfdSIskren Chernev .hwcg_bit = 1, 2357cbe63bfdSIskren Chernev .clkr = { 2358cbe63bfdSIskren Chernev .enable_reg = 0x3600c, 2359cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2360cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2361cbe63bfdSIskren Chernev .name = "gcc_gpu_memnoc_gfx_clk", 2362cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2363cbe63bfdSIskren Chernev }, 2364cbe63bfdSIskren Chernev }, 2365cbe63bfdSIskren Chernev }; 2366cbe63bfdSIskren Chernev 2367cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2368cbe63bfdSIskren Chernev .halt_reg = 0x36018, 2369cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2370cbe63bfdSIskren Chernev .clkr = { 2371cbe63bfdSIskren Chernev .enable_reg = 0x36018, 2372cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2373cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2374cbe63bfdSIskren Chernev .name = "gcc_gpu_snoc_dvm_gfx_clk", 2375cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2376cbe63bfdSIskren Chernev }, 2377cbe63bfdSIskren Chernev }, 2378cbe63bfdSIskren Chernev }; 2379cbe63bfdSIskren Chernev 2380cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_throttle_core_clk = { 2381cbe63bfdSIskren Chernev .halt_reg = 0x36048, 2382cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2383cbe63bfdSIskren Chernev .hwcg_reg = 0x36048, 2384cbe63bfdSIskren Chernev .hwcg_bit = 1, 2385cbe63bfdSIskren Chernev .clkr = { 2386cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2387cbe63bfdSIskren Chernev .enable_mask = BIT(31), 2388cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2389cbe63bfdSIskren Chernev .name = "gcc_gpu_throttle_core_clk", 2390cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2391cbe63bfdSIskren Chernev }, 2392cbe63bfdSIskren Chernev }, 2393cbe63bfdSIskren Chernev }; 2394cbe63bfdSIskren Chernev 2395cbe63bfdSIskren Chernev static struct clk_branch gcc_pdm2_clk = { 2396cbe63bfdSIskren Chernev .halt_reg = 0x2000c, 2397cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2398cbe63bfdSIskren Chernev .clkr = { 2399cbe63bfdSIskren Chernev .enable_reg = 0x2000c, 2400cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2401cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2402cbe63bfdSIskren Chernev .name = "gcc_pdm2_clk", 2403cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2404cbe63bfdSIskren Chernev &gcc_pdm2_clk_src.clkr.hw, 2405cbe63bfdSIskren Chernev }, 2406cbe63bfdSIskren Chernev .num_parents = 1, 2407cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2408cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2409cbe63bfdSIskren Chernev }, 2410cbe63bfdSIskren Chernev }, 2411cbe63bfdSIskren Chernev }; 2412cbe63bfdSIskren Chernev 2413cbe63bfdSIskren Chernev static struct clk_branch gcc_pdm_ahb_clk = { 2414cbe63bfdSIskren Chernev .halt_reg = 0x20004, 2415cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2416cbe63bfdSIskren Chernev .hwcg_reg = 0x20004, 2417cbe63bfdSIskren Chernev .hwcg_bit = 1, 2418cbe63bfdSIskren Chernev .clkr = { 2419cbe63bfdSIskren Chernev .enable_reg = 0x20004, 2420cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2421cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2422cbe63bfdSIskren Chernev .name = "gcc_pdm_ahb_clk", 2423cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2424cbe63bfdSIskren Chernev }, 2425cbe63bfdSIskren Chernev }, 2426cbe63bfdSIskren Chernev }; 2427cbe63bfdSIskren Chernev 2428cbe63bfdSIskren Chernev static struct clk_branch gcc_pdm_xo4_clk = { 2429cbe63bfdSIskren Chernev .halt_reg = 0x20008, 2430cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2431cbe63bfdSIskren Chernev .clkr = { 2432cbe63bfdSIskren Chernev .enable_reg = 0x20008, 2433cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2434cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2435cbe63bfdSIskren Chernev .name = "gcc_pdm_xo4_clk", 2436cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2437cbe63bfdSIskren Chernev }, 2438cbe63bfdSIskren Chernev }, 2439cbe63bfdSIskren Chernev }; 2440cbe63bfdSIskren Chernev 2441cbe63bfdSIskren Chernev static struct clk_branch gcc_prng_ahb_clk = { 2442cbe63bfdSIskren Chernev .halt_reg = 0x21004, 2443cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2444cbe63bfdSIskren Chernev .hwcg_reg = 0x21004, 2445cbe63bfdSIskren Chernev .hwcg_bit = 1, 2446cbe63bfdSIskren Chernev .clkr = { 2447cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2448cbe63bfdSIskren Chernev .enable_mask = BIT(13), 2449cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2450cbe63bfdSIskren Chernev .name = "gcc_prng_ahb_clk", 2451cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2452cbe63bfdSIskren Chernev }, 2453cbe63bfdSIskren Chernev }, 2454cbe63bfdSIskren Chernev }; 2455cbe63bfdSIskren Chernev 2456cbe63bfdSIskren Chernev static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2457cbe63bfdSIskren Chernev .halt_reg = 0x17014, 2458cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2459cbe63bfdSIskren Chernev .hwcg_reg = 0x17014, 2460cbe63bfdSIskren Chernev .hwcg_bit = 1, 2461cbe63bfdSIskren Chernev .clkr = { 2462cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2463cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2464cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2465cbe63bfdSIskren Chernev .name = "gcc_qmip_camera_nrt_ahb_clk", 2466cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2467cbe63bfdSIskren Chernev }, 2468cbe63bfdSIskren Chernev }, 2469cbe63bfdSIskren Chernev }; 2470cbe63bfdSIskren Chernev 2471cbe63bfdSIskren Chernev static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2472cbe63bfdSIskren Chernev .halt_reg = 0x17060, 2473cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2474cbe63bfdSIskren Chernev .hwcg_reg = 0x17060, 2475cbe63bfdSIskren Chernev .hwcg_bit = 1, 2476cbe63bfdSIskren Chernev .clkr = { 2477cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2478cbe63bfdSIskren Chernev .enable_mask = BIT(2), 2479cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2480cbe63bfdSIskren Chernev .name = "gcc_qmip_camera_rt_ahb_clk", 2481cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2482cbe63bfdSIskren Chernev }, 2483cbe63bfdSIskren Chernev }, 2484cbe63bfdSIskren Chernev }; 2485cbe63bfdSIskren Chernev 2486cbe63bfdSIskren Chernev static struct clk_branch gcc_qmip_disp_ahb_clk = { 2487cbe63bfdSIskren Chernev .halt_reg = 0x17018, 2488cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2489cbe63bfdSIskren Chernev .hwcg_reg = 0x17018, 2490cbe63bfdSIskren Chernev .hwcg_bit = 1, 2491cbe63bfdSIskren Chernev .clkr = { 2492cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2493cbe63bfdSIskren Chernev .enable_mask = BIT(1), 2494cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2495cbe63bfdSIskren Chernev .name = "gcc_qmip_disp_ahb_clk", 2496cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2497cbe63bfdSIskren Chernev }, 2498cbe63bfdSIskren Chernev }, 2499cbe63bfdSIskren Chernev }; 2500cbe63bfdSIskren Chernev 2501cbe63bfdSIskren Chernev static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = { 2502cbe63bfdSIskren Chernev .halt_reg = 0x36040, 2503cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2504cbe63bfdSIskren Chernev .hwcg_reg = 0x36040, 2505cbe63bfdSIskren Chernev .hwcg_bit = 1, 2506cbe63bfdSIskren Chernev .clkr = { 2507cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2508cbe63bfdSIskren Chernev .enable_mask = BIT(4), 2509cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2510cbe63bfdSIskren Chernev .name = "gcc_qmip_gpu_cfg_ahb_clk", 2511cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2512cbe63bfdSIskren Chernev }, 2513cbe63bfdSIskren Chernev }, 2514cbe63bfdSIskren Chernev }; 2515cbe63bfdSIskren Chernev 2516cbe63bfdSIskren Chernev static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2517cbe63bfdSIskren Chernev .halt_reg = 0x17010, 2518cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2519cbe63bfdSIskren Chernev .hwcg_reg = 0x17010, 2520cbe63bfdSIskren Chernev .hwcg_bit = 1, 2521cbe63bfdSIskren Chernev .clkr = { 2522cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2523cbe63bfdSIskren Chernev .enable_mask = BIT(25), 2524cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2525cbe63bfdSIskren Chernev .name = "gcc_qmip_video_vcodec_ahb_clk", 2526cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2527cbe63bfdSIskren Chernev }, 2528cbe63bfdSIskren Chernev }, 2529cbe63bfdSIskren Chernev }; 2530cbe63bfdSIskren Chernev 2531cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2532cbe63bfdSIskren Chernev .halt_reg = 0x1f014, 2533cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2534cbe63bfdSIskren Chernev .clkr = { 2535cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2536cbe63bfdSIskren Chernev .enable_mask = BIT(9), 2537cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2538cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_core_2x_clk", 2539cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2540cbe63bfdSIskren Chernev }, 2541cbe63bfdSIskren Chernev }, 2542cbe63bfdSIskren Chernev }; 2543cbe63bfdSIskren Chernev 2544cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2545cbe63bfdSIskren Chernev .halt_reg = 0x1f00c, 2546cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2547cbe63bfdSIskren Chernev .clkr = { 2548cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2549cbe63bfdSIskren Chernev .enable_mask = BIT(8), 2550cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2551cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_core_clk", 2552cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2553cbe63bfdSIskren Chernev }, 2554cbe63bfdSIskren Chernev }, 2555cbe63bfdSIskren Chernev }; 2556cbe63bfdSIskren Chernev 2557cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2558cbe63bfdSIskren Chernev .halt_reg = 0x1f144, 2559cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2560cbe63bfdSIskren Chernev .clkr = { 2561cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2562cbe63bfdSIskren Chernev .enable_mask = BIT(10), 2563cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2564cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s0_clk", 2565cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2566cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 2567cbe63bfdSIskren Chernev }, 2568cbe63bfdSIskren Chernev .num_parents = 1, 2569cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2570cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2571cbe63bfdSIskren Chernev }, 2572cbe63bfdSIskren Chernev }, 2573cbe63bfdSIskren Chernev }; 2574cbe63bfdSIskren Chernev 2575cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2576cbe63bfdSIskren Chernev .halt_reg = 0x1f274, 2577cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2578cbe63bfdSIskren Chernev .clkr = { 2579cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2580cbe63bfdSIskren Chernev .enable_mask = BIT(11), 2581cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2582cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s1_clk", 2583cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2584cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 2585cbe63bfdSIskren Chernev }, 2586cbe63bfdSIskren Chernev .num_parents = 1, 2587cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2588cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2589cbe63bfdSIskren Chernev }, 2590cbe63bfdSIskren Chernev }, 2591cbe63bfdSIskren Chernev }; 2592cbe63bfdSIskren Chernev 2593cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2594cbe63bfdSIskren Chernev .halt_reg = 0x1f3a4, 2595cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2596cbe63bfdSIskren Chernev .clkr = { 2597cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2598cbe63bfdSIskren Chernev .enable_mask = BIT(12), 2599cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2600cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s2_clk", 2601cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2602cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2603cbe63bfdSIskren Chernev }, 2604cbe63bfdSIskren Chernev .num_parents = 1, 2605cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2606cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2607cbe63bfdSIskren Chernev }, 2608cbe63bfdSIskren Chernev }, 2609cbe63bfdSIskren Chernev }; 2610cbe63bfdSIskren Chernev 2611cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2612cbe63bfdSIskren Chernev .halt_reg = 0x1f4d4, 2613cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2614cbe63bfdSIskren Chernev .clkr = { 2615cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2616cbe63bfdSIskren Chernev .enable_mask = BIT(13), 2617cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2618cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s3_clk", 2619cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2620cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2621cbe63bfdSIskren Chernev }, 2622cbe63bfdSIskren Chernev .num_parents = 1, 2623cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2624cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2625cbe63bfdSIskren Chernev }, 2626cbe63bfdSIskren Chernev }, 2627cbe63bfdSIskren Chernev }; 2628cbe63bfdSIskren Chernev 2629cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2630cbe63bfdSIskren Chernev .halt_reg = 0x1f604, 2631cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2632cbe63bfdSIskren Chernev .clkr = { 2633cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2634cbe63bfdSIskren Chernev .enable_mask = BIT(14), 2635cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2636cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s4_clk", 2637cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2638cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2639cbe63bfdSIskren Chernev }, 2640cbe63bfdSIskren Chernev .num_parents = 1, 2641cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2642cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2643cbe63bfdSIskren Chernev }, 2644cbe63bfdSIskren Chernev }, 2645cbe63bfdSIskren Chernev }; 2646cbe63bfdSIskren Chernev 2647cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2648cbe63bfdSIskren Chernev .halt_reg = 0x1f734, 2649cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2650cbe63bfdSIskren Chernev .clkr = { 2651cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2652cbe63bfdSIskren Chernev .enable_mask = BIT(15), 2653cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2654cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s5_clk", 2655cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2656cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2657cbe63bfdSIskren Chernev }, 2658cbe63bfdSIskren Chernev .num_parents = 1, 2659cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2660cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2661cbe63bfdSIskren Chernev }, 2662cbe63bfdSIskren Chernev }, 2663cbe63bfdSIskren Chernev }; 2664cbe63bfdSIskren Chernev 2665cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2666cbe63bfdSIskren Chernev .halt_reg = 0x1f004, 2667cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2668cbe63bfdSIskren Chernev .hwcg_reg = 0x1f004, 2669cbe63bfdSIskren Chernev .hwcg_bit = 1, 2670cbe63bfdSIskren Chernev .clkr = { 2671cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2672cbe63bfdSIskren Chernev .enable_mask = BIT(6), 2673cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2674cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2675cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2676cbe63bfdSIskren Chernev }, 2677cbe63bfdSIskren Chernev }, 2678cbe63bfdSIskren Chernev }; 2679cbe63bfdSIskren Chernev 2680cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2681cbe63bfdSIskren Chernev .halt_reg = 0x1f008, 2682cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2683cbe63bfdSIskren Chernev .hwcg_reg = 0x1f008, 2684cbe63bfdSIskren Chernev .hwcg_bit = 1, 2685cbe63bfdSIskren Chernev .clkr = { 2686cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2687cbe63bfdSIskren Chernev .enable_mask = BIT(7), 2688cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2689cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2690cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2691cbe63bfdSIskren Chernev }, 2692cbe63bfdSIskren Chernev }, 2693cbe63bfdSIskren Chernev }; 2694cbe63bfdSIskren Chernev 2695cbe63bfdSIskren Chernev static struct clk_branch gcc_sdcc1_ahb_clk = { 2696cbe63bfdSIskren Chernev .halt_reg = 0x38008, 2697cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2698cbe63bfdSIskren Chernev .clkr = { 2699cbe63bfdSIskren Chernev .enable_reg = 0x38008, 2700cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2701cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2702cbe63bfdSIskren Chernev .name = "gcc_sdcc1_ahb_clk", 2703cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2704cbe63bfdSIskren Chernev }, 2705cbe63bfdSIskren Chernev }, 2706cbe63bfdSIskren Chernev }; 2707cbe63bfdSIskren Chernev 2708cbe63bfdSIskren Chernev static struct clk_branch gcc_sdcc1_apps_clk = { 2709cbe63bfdSIskren Chernev .halt_reg = 0x38004, 2710cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2711cbe63bfdSIskren Chernev .clkr = { 2712cbe63bfdSIskren Chernev .enable_reg = 0x38004, 2713cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2714cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2715cbe63bfdSIskren Chernev .name = "gcc_sdcc1_apps_clk", 2716cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2717cbe63bfdSIskren Chernev &gcc_sdcc1_apps_clk_src.clkr.hw, 2718cbe63bfdSIskren Chernev }, 2719cbe63bfdSIskren Chernev .num_parents = 1, 2720cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT /* | CLK_ENABLE_HAND_OFF */, 2721cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2722cbe63bfdSIskren Chernev }, 2723cbe63bfdSIskren Chernev }, 2724cbe63bfdSIskren Chernev }; 2725cbe63bfdSIskren Chernev 2726cbe63bfdSIskren Chernev static struct clk_branch gcc_sdcc1_ice_core_clk = { 2727cbe63bfdSIskren Chernev .halt_reg = 0x3800c, 2728cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2729cbe63bfdSIskren Chernev .hwcg_reg = 0x3800c, 2730cbe63bfdSIskren Chernev .hwcg_bit = 1, 2731cbe63bfdSIskren Chernev .clkr = { 2732cbe63bfdSIskren Chernev .enable_reg = 0x3800c, 2733cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2734cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2735cbe63bfdSIskren Chernev .name = "gcc_sdcc1_ice_core_clk", 2736cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2737cbe63bfdSIskren Chernev &gcc_sdcc1_ice_core_clk_src.clkr.hw, 2738cbe63bfdSIskren Chernev }, 2739cbe63bfdSIskren Chernev .num_parents = 1, 2740cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2741cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2742cbe63bfdSIskren Chernev }, 2743cbe63bfdSIskren Chernev }, 2744cbe63bfdSIskren Chernev }; 2745cbe63bfdSIskren Chernev 2746cbe63bfdSIskren Chernev static struct clk_branch gcc_sdcc2_ahb_clk = { 2747cbe63bfdSIskren Chernev .halt_reg = 0x1e008, 2748cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2749cbe63bfdSIskren Chernev .clkr = { 2750cbe63bfdSIskren Chernev .enable_reg = 0x1e008, 2751cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2752cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2753cbe63bfdSIskren Chernev .name = "gcc_sdcc2_ahb_clk", 2754cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2755cbe63bfdSIskren Chernev }, 2756cbe63bfdSIskren Chernev }, 2757cbe63bfdSIskren Chernev }; 2758cbe63bfdSIskren Chernev 2759cbe63bfdSIskren Chernev static struct clk_branch gcc_sdcc2_apps_clk = { 2760cbe63bfdSIskren Chernev .halt_reg = 0x1e004, 2761cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2762cbe63bfdSIskren Chernev .clkr = { 2763cbe63bfdSIskren Chernev .enable_reg = 0x1e004, 2764cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2765cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2766cbe63bfdSIskren Chernev .name = "gcc_sdcc2_apps_clk", 2767cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2768cbe63bfdSIskren Chernev &gcc_sdcc2_apps_clk_src.clkr.hw, 2769cbe63bfdSIskren Chernev }, 2770cbe63bfdSIskren Chernev .num_parents = 1, 2771cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2772cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2773cbe63bfdSIskren Chernev }, 2774cbe63bfdSIskren Chernev }, 2775cbe63bfdSIskren Chernev }; 2776cbe63bfdSIskren Chernev 2777cbe63bfdSIskren Chernev static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 2778cbe63bfdSIskren Chernev .halt_reg = 0x2b06c, 2779cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2780cbe63bfdSIskren Chernev .hwcg_reg = 0x2b06c, 2781cbe63bfdSIskren Chernev .hwcg_bit = 1, 2782cbe63bfdSIskren Chernev .clkr = { 2783cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2784cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2785cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2786cbe63bfdSIskren Chernev .name = "gcc_sys_noc_cpuss_ahb_clk", 2787cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 2788cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2789cbe63bfdSIskren Chernev }, 2790cbe63bfdSIskren Chernev }, 2791cbe63bfdSIskren Chernev }; 2792cbe63bfdSIskren Chernev 2793cbe63bfdSIskren Chernev static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { 2794cbe63bfdSIskren Chernev .halt_reg = 0x45098, 2795cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2796cbe63bfdSIskren Chernev .clkr = { 2797cbe63bfdSIskren Chernev .enable_reg = 0x45098, 2798cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2799cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2800cbe63bfdSIskren Chernev .name = "gcc_sys_noc_ufs_phy_axi_clk", 2801cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2802cbe63bfdSIskren Chernev &gcc_ufs_phy_axi_clk_src.clkr.hw, 2803cbe63bfdSIskren Chernev }, 2804cbe63bfdSIskren Chernev .num_parents = 1, 2805cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2806cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2807cbe63bfdSIskren Chernev }, 2808cbe63bfdSIskren Chernev }, 2809cbe63bfdSIskren Chernev }; 2810cbe63bfdSIskren Chernev 2811cbe63bfdSIskren Chernev static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { 2812cbe63bfdSIskren Chernev .halt_reg = 0x1a080, 2813cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2814cbe63bfdSIskren Chernev .hwcg_reg = 0x1a080, 2815cbe63bfdSIskren Chernev .hwcg_bit = 1, 2816cbe63bfdSIskren Chernev .clkr = { 2817cbe63bfdSIskren Chernev .enable_reg = 0x1a080, 2818cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2819cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2820cbe63bfdSIskren Chernev .name = "gcc_sys_noc_usb3_prim_axi_clk", 2821cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2822cbe63bfdSIskren Chernev &gcc_usb30_prim_master_clk_src.clkr.hw, 2823cbe63bfdSIskren Chernev }, 2824cbe63bfdSIskren Chernev .num_parents = 1, 2825cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2826cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2827cbe63bfdSIskren Chernev }, 2828cbe63bfdSIskren Chernev }, 2829cbe63bfdSIskren Chernev }; 2830cbe63bfdSIskren Chernev 2831cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_clkref_clk = { 2832cbe63bfdSIskren Chernev .halt_reg = 0x8c000, 2833cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2834cbe63bfdSIskren Chernev .clkr = { 2835cbe63bfdSIskren Chernev .enable_reg = 0x8c000, 2836cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2837cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2838cbe63bfdSIskren Chernev .name = "gcc_ufs_clkref_clk", 2839cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2840cbe63bfdSIskren Chernev }, 2841cbe63bfdSIskren Chernev }, 2842cbe63bfdSIskren Chernev }; 2843cbe63bfdSIskren Chernev 2844cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_ahb_clk = { 2845cbe63bfdSIskren Chernev .halt_reg = 0x45014, 2846cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2847cbe63bfdSIskren Chernev .hwcg_reg = 0x45014, 2848cbe63bfdSIskren Chernev .hwcg_bit = 1, 2849cbe63bfdSIskren Chernev .clkr = { 2850cbe63bfdSIskren Chernev .enable_reg = 0x45014, 2851cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2852cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2853cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_ahb_clk", 2854cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2855cbe63bfdSIskren Chernev }, 2856cbe63bfdSIskren Chernev }, 2857cbe63bfdSIskren Chernev }; 2858cbe63bfdSIskren Chernev 2859cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_axi_clk = { 2860cbe63bfdSIskren Chernev .halt_reg = 0x45010, 2861cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2862cbe63bfdSIskren Chernev .hwcg_reg = 0x45010, 2863cbe63bfdSIskren Chernev .hwcg_bit = 1, 2864cbe63bfdSIskren Chernev .clkr = { 2865cbe63bfdSIskren Chernev .enable_reg = 0x45010, 2866cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2867cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2868cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_axi_clk", 2869cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2870cbe63bfdSIskren Chernev &gcc_ufs_phy_axi_clk_src.clkr.hw, 2871cbe63bfdSIskren Chernev }, 2872cbe63bfdSIskren Chernev .num_parents = 1, 2873cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2874cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2875cbe63bfdSIskren Chernev }, 2876cbe63bfdSIskren Chernev }, 2877cbe63bfdSIskren Chernev }; 2878cbe63bfdSIskren Chernev 2879cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2880cbe63bfdSIskren Chernev .halt_reg = 0x45044, 2881cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2882cbe63bfdSIskren Chernev .hwcg_reg = 0x45044, 2883cbe63bfdSIskren Chernev .hwcg_bit = 1, 2884cbe63bfdSIskren Chernev .clkr = { 2885cbe63bfdSIskren Chernev .enable_reg = 0x45044, 2886cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2887cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2888cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_ice_core_clk", 2889cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2890cbe63bfdSIskren Chernev &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2891cbe63bfdSIskren Chernev }, 2892cbe63bfdSIskren Chernev .num_parents = 1, 2893cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2894cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2895cbe63bfdSIskren Chernev }, 2896cbe63bfdSIskren Chernev }, 2897cbe63bfdSIskren Chernev }; 2898cbe63bfdSIskren Chernev 2899cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2900cbe63bfdSIskren Chernev .halt_reg = 0x45078, 2901cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2902cbe63bfdSIskren Chernev .hwcg_reg = 0x45078, 2903cbe63bfdSIskren Chernev .hwcg_bit = 1, 2904cbe63bfdSIskren Chernev .clkr = { 2905cbe63bfdSIskren Chernev .enable_reg = 0x45078, 2906cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2907cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2908cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_phy_aux_clk", 2909cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2910cbe63bfdSIskren Chernev &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2911cbe63bfdSIskren Chernev }, 2912cbe63bfdSIskren Chernev .num_parents = 1, 2913cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2914cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2915cbe63bfdSIskren Chernev }, 2916cbe63bfdSIskren Chernev }, 2917cbe63bfdSIskren Chernev }; 2918cbe63bfdSIskren Chernev 2919cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2920cbe63bfdSIskren Chernev .halt_reg = 0x4501c, 2921cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_SKIP, 2922cbe63bfdSIskren Chernev .clkr = { 2923cbe63bfdSIskren Chernev .enable_reg = 0x4501c, 2924cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2925cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2926cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_rx_symbol_0_clk", 2927cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2928cbe63bfdSIskren Chernev }, 2929cbe63bfdSIskren Chernev }, 2930cbe63bfdSIskren Chernev }; 2931cbe63bfdSIskren Chernev 2932cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2933cbe63bfdSIskren Chernev .halt_reg = 0x45018, 2934cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_SKIP, 2935cbe63bfdSIskren Chernev .clkr = { 2936cbe63bfdSIskren Chernev .enable_reg = 0x45018, 2937cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2938cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2939cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_tx_symbol_0_clk", 2940cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2941cbe63bfdSIskren Chernev }, 2942cbe63bfdSIskren Chernev }, 2943cbe63bfdSIskren Chernev }; 2944cbe63bfdSIskren Chernev 2945cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2946cbe63bfdSIskren Chernev .halt_reg = 0x45040, 2947cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2948cbe63bfdSIskren Chernev .hwcg_reg = 0x45040, 2949cbe63bfdSIskren Chernev .hwcg_bit = 1, 2950cbe63bfdSIskren Chernev .clkr = { 2951cbe63bfdSIskren Chernev .enable_reg = 0x45040, 2952cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2953cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2954cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_unipro_core_clk", 2955cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2956cbe63bfdSIskren Chernev &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2957cbe63bfdSIskren Chernev }, 2958cbe63bfdSIskren Chernev .num_parents = 1, 2959cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2960cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2961cbe63bfdSIskren Chernev }, 2962cbe63bfdSIskren Chernev }, 2963cbe63bfdSIskren Chernev }; 2964cbe63bfdSIskren Chernev 2965cbe63bfdSIskren Chernev static struct clk_branch gcc_usb30_prim_master_clk = { 2966cbe63bfdSIskren Chernev .halt_reg = 0x1a010, 2967cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2968cbe63bfdSIskren Chernev .clkr = { 2969cbe63bfdSIskren Chernev .enable_reg = 0x1a010, 2970cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2971cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2972cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_master_clk", 2973cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2974cbe63bfdSIskren Chernev &gcc_usb30_prim_master_clk_src.clkr.hw, 2975cbe63bfdSIskren Chernev }, 2976cbe63bfdSIskren Chernev .num_parents = 1, 2977cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2978cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2979cbe63bfdSIskren Chernev }, 2980cbe63bfdSIskren Chernev }, 2981cbe63bfdSIskren Chernev }; 2982cbe63bfdSIskren Chernev 2983cbe63bfdSIskren Chernev static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2984cbe63bfdSIskren Chernev .halt_reg = 0x1a018, 2985cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2986cbe63bfdSIskren Chernev .clkr = { 2987cbe63bfdSIskren Chernev .enable_reg = 0x1a018, 2988cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2989cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2990cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_mock_utmi_clk", 2991cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2992cbe63bfdSIskren Chernev &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2993cbe63bfdSIskren Chernev }, 2994cbe63bfdSIskren Chernev .num_parents = 1, 2995cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2996cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2997cbe63bfdSIskren Chernev }, 2998cbe63bfdSIskren Chernev }, 2999cbe63bfdSIskren Chernev }; 3000cbe63bfdSIskren Chernev 3001cbe63bfdSIskren Chernev static struct clk_branch gcc_usb30_prim_sleep_clk = { 3002cbe63bfdSIskren Chernev .halt_reg = 0x1a014, 3003cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3004cbe63bfdSIskren Chernev .clkr = { 3005cbe63bfdSIskren Chernev .enable_reg = 0x1a014, 3006cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3007cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3008cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_sleep_clk", 3009cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3010cbe63bfdSIskren Chernev }, 3011cbe63bfdSIskren Chernev }, 3012cbe63bfdSIskren Chernev }; 3013cbe63bfdSIskren Chernev 3014cbe63bfdSIskren Chernev static struct clk_branch gcc_usb3_prim_clkref_clk = { 3015cbe63bfdSIskren Chernev .halt_reg = 0x9f000, 3016cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3017cbe63bfdSIskren Chernev .clkr = { 3018cbe63bfdSIskren Chernev .enable_reg = 0x9f000, 3019cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3020cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3021cbe63bfdSIskren Chernev .name = "gcc_usb3_prim_clkref_clk", 3022cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3023cbe63bfdSIskren Chernev }, 3024cbe63bfdSIskren Chernev }, 3025cbe63bfdSIskren Chernev }; 3026cbe63bfdSIskren Chernev 3027cbe63bfdSIskren Chernev static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3028cbe63bfdSIskren Chernev .halt_reg = 0x1a054, 3029cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3030cbe63bfdSIskren Chernev .clkr = { 3031cbe63bfdSIskren Chernev .enable_reg = 0x1a054, 3032cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3033cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3034cbe63bfdSIskren Chernev .name = "gcc_usb3_prim_phy_com_aux_clk", 3035cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 3036cbe63bfdSIskren Chernev &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3037cbe63bfdSIskren Chernev }, 3038cbe63bfdSIskren Chernev .num_parents = 1, 3039cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 3040cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3041cbe63bfdSIskren Chernev }, 3042cbe63bfdSIskren Chernev }, 3043cbe63bfdSIskren Chernev }; 3044cbe63bfdSIskren Chernev 3045cbe63bfdSIskren Chernev static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3046cbe63bfdSIskren Chernev .halt_reg = 0x1a058, 3047cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_SKIP, 3048cbe63bfdSIskren Chernev .hwcg_reg = 0x1a058, 3049cbe63bfdSIskren Chernev .hwcg_bit = 1, 3050cbe63bfdSIskren Chernev .clkr = { 3051cbe63bfdSIskren Chernev .enable_reg = 0x1a058, 3052cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3053cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3054cbe63bfdSIskren Chernev .name = "gcc_usb3_prim_phy_pipe_clk", 3055cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3056cbe63bfdSIskren Chernev }, 3057cbe63bfdSIskren Chernev }, 3058cbe63bfdSIskren Chernev }; 3059cbe63bfdSIskren Chernev 3060cbe63bfdSIskren Chernev static struct clk_branch gcc_vcodec0_axi_clk = { 3061cbe63bfdSIskren Chernev .halt_reg = 0x6e008, 3062cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3063cbe63bfdSIskren Chernev .clkr = { 3064cbe63bfdSIskren Chernev .enable_reg = 0x6e008, 3065cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3066cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3067cbe63bfdSIskren Chernev .name = "gcc_vcodec0_axi_clk", 3068cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3069cbe63bfdSIskren Chernev }, 3070cbe63bfdSIskren Chernev }, 3071cbe63bfdSIskren Chernev }; 3072cbe63bfdSIskren Chernev 3073cbe63bfdSIskren Chernev static struct clk_branch gcc_venus_ahb_clk = { 3074cbe63bfdSIskren Chernev .halt_reg = 0x6e010, 3075cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3076cbe63bfdSIskren Chernev .clkr = { 3077cbe63bfdSIskren Chernev .enable_reg = 0x6e010, 3078cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3079cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3080cbe63bfdSIskren Chernev .name = "gcc_venus_ahb_clk", 3081cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3082cbe63bfdSIskren Chernev }, 3083cbe63bfdSIskren Chernev }, 3084cbe63bfdSIskren Chernev }; 3085cbe63bfdSIskren Chernev 3086cbe63bfdSIskren Chernev static struct clk_branch gcc_venus_ctl_axi_clk = { 3087cbe63bfdSIskren Chernev .halt_reg = 0x6e004, 3088cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3089cbe63bfdSIskren Chernev .clkr = { 3090cbe63bfdSIskren Chernev .enable_reg = 0x6e004, 3091cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3092cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3093cbe63bfdSIskren Chernev .name = "gcc_venus_ctl_axi_clk", 3094cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3095cbe63bfdSIskren Chernev }, 3096cbe63bfdSIskren Chernev }, 3097cbe63bfdSIskren Chernev }; 3098cbe63bfdSIskren Chernev 3099cbe63bfdSIskren Chernev static struct clk_branch gcc_video_ahb_clk = { 3100cbe63bfdSIskren Chernev .halt_reg = 0x17004, 3101cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3102cbe63bfdSIskren Chernev .hwcg_reg = 0x17004, 3103cbe63bfdSIskren Chernev .hwcg_bit = 1, 3104cbe63bfdSIskren Chernev .clkr = { 3105cbe63bfdSIskren Chernev .enable_reg = 0x17004, 3106cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3107cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3108cbe63bfdSIskren Chernev .name = "gcc_video_ahb_clk", 3109cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3110cbe63bfdSIskren Chernev }, 3111cbe63bfdSIskren Chernev }, 3112cbe63bfdSIskren Chernev }; 3113cbe63bfdSIskren Chernev 3114cbe63bfdSIskren Chernev static struct clk_branch gcc_video_axi0_clk = { 3115cbe63bfdSIskren Chernev .halt_reg = 0x1701c, 3116cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3117cbe63bfdSIskren Chernev .hwcg_reg = 0x1701c, 3118cbe63bfdSIskren Chernev .hwcg_bit = 1, 3119cbe63bfdSIskren Chernev .clkr = { 3120cbe63bfdSIskren Chernev .enable_reg = 0x1701c, 3121cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3122cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3123cbe63bfdSIskren Chernev .name = "gcc_video_axi0_clk", 3124cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3125cbe63bfdSIskren Chernev }, 3126cbe63bfdSIskren Chernev }, 3127cbe63bfdSIskren Chernev }; 3128cbe63bfdSIskren Chernev 3129cbe63bfdSIskren Chernev static struct clk_branch gcc_video_throttle_core_clk = { 3130cbe63bfdSIskren Chernev .halt_reg = 0x17068, 3131cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 3132cbe63bfdSIskren Chernev .hwcg_reg = 0x17068, 3133cbe63bfdSIskren Chernev .hwcg_bit = 1, 3134cbe63bfdSIskren Chernev .clkr = { 3135cbe63bfdSIskren Chernev .enable_reg = 0x79004, 3136cbe63bfdSIskren Chernev .enable_mask = BIT(28), 3137cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3138cbe63bfdSIskren Chernev .name = "gcc_video_throttle_core_clk", 3139cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3140cbe63bfdSIskren Chernev }, 3141cbe63bfdSIskren Chernev }, 3142cbe63bfdSIskren Chernev }; 3143cbe63bfdSIskren Chernev 3144cbe63bfdSIskren Chernev static struct clk_branch gcc_video_vcodec0_sys_clk = { 3145cbe63bfdSIskren Chernev .halt_reg = 0x580a4, 3146cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 3147cbe63bfdSIskren Chernev .hwcg_reg = 0x580a4, 3148cbe63bfdSIskren Chernev .hwcg_bit = 1, 3149cbe63bfdSIskren Chernev .clkr = { 3150cbe63bfdSIskren Chernev .enable_reg = 0x580a4, 3151cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3152cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3153cbe63bfdSIskren Chernev .name = "gcc_video_vcodec0_sys_clk", 3154cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 3155cbe63bfdSIskren Chernev &gcc_video_venus_clk_src.clkr.hw, 3156cbe63bfdSIskren Chernev }, 3157cbe63bfdSIskren Chernev .num_parents = 1, 3158cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 3159cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3160cbe63bfdSIskren Chernev }, 3161cbe63bfdSIskren Chernev }, 3162cbe63bfdSIskren Chernev }; 3163cbe63bfdSIskren Chernev 3164cbe63bfdSIskren Chernev static struct clk_branch gcc_video_venus_ctl_clk = { 3165cbe63bfdSIskren Chernev .halt_reg = 0x5808c, 3166cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3167cbe63bfdSIskren Chernev .clkr = { 3168cbe63bfdSIskren Chernev .enable_reg = 0x5808c, 3169cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3170cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3171cbe63bfdSIskren Chernev .name = "gcc_video_venus_ctl_clk", 3172cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 3173cbe63bfdSIskren Chernev &gcc_video_venus_clk_src.clkr.hw, 3174cbe63bfdSIskren Chernev }, 3175cbe63bfdSIskren Chernev .num_parents = 1, 3176cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 3177cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3178cbe63bfdSIskren Chernev }, 3179cbe63bfdSIskren Chernev }, 3180cbe63bfdSIskren Chernev }; 3181cbe63bfdSIskren Chernev 3182cbe63bfdSIskren Chernev static struct clk_branch gcc_video_xo_clk = { 3183cbe63bfdSIskren Chernev .halt_reg = 0x17024, 3184cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3185cbe63bfdSIskren Chernev .clkr = { 3186cbe63bfdSIskren Chernev .enable_reg = 0x17024, 3187cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3188cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3189cbe63bfdSIskren Chernev .name = "gcc_video_xo_clk", 3190cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3191cbe63bfdSIskren Chernev }, 3192cbe63bfdSIskren Chernev }, 3193cbe63bfdSIskren Chernev }; 3194cbe63bfdSIskren Chernev 3195cbe63bfdSIskren Chernev static struct gdsc gcc_camss_top_gdsc = { 3196cbe63bfdSIskren Chernev .gdscr = 0x58004, 3197cbe63bfdSIskren Chernev .pd = { 3198cbe63bfdSIskren Chernev .name = "gcc_camss_top", 3199cbe63bfdSIskren Chernev }, 3200cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3201cbe63bfdSIskren Chernev }; 3202cbe63bfdSIskren Chernev 3203cbe63bfdSIskren Chernev static struct gdsc gcc_ufs_phy_gdsc = { 3204cbe63bfdSIskren Chernev .gdscr = 0x45004, 3205cbe63bfdSIskren Chernev .pd = { 3206cbe63bfdSIskren Chernev .name = "gcc_ufs_phy", 3207cbe63bfdSIskren Chernev }, 3208cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3209cbe63bfdSIskren Chernev }; 3210cbe63bfdSIskren Chernev 3211cbe63bfdSIskren Chernev static struct gdsc gcc_usb30_prim_gdsc = { 3212cbe63bfdSIskren Chernev .gdscr = 0x1a004, 3213cbe63bfdSIskren Chernev .pd = { 3214cbe63bfdSIskren Chernev .name = "gcc_usb30_prim", 3215cbe63bfdSIskren Chernev }, 3216cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3217cbe63bfdSIskren Chernev }; 3218cbe63bfdSIskren Chernev 3219cbe63bfdSIskren Chernev static struct gdsc gcc_vcodec0_gdsc = { 3220cbe63bfdSIskren Chernev .gdscr = 0x58098, 3221cbe63bfdSIskren Chernev .pd = { 3222cbe63bfdSIskren Chernev .name = "gcc_vcodec0", 3223cbe63bfdSIskren Chernev }, 3224cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3225cbe63bfdSIskren Chernev }; 3226cbe63bfdSIskren Chernev 3227cbe63bfdSIskren Chernev static struct gdsc gcc_venus_gdsc = { 3228cbe63bfdSIskren Chernev .gdscr = 0x5807c, 3229cbe63bfdSIskren Chernev .pd = { 3230cbe63bfdSIskren Chernev .name = "gcc_venus", 3231cbe63bfdSIskren Chernev }, 3232cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3233cbe63bfdSIskren Chernev }; 3234cbe63bfdSIskren Chernev 3235cbe63bfdSIskren Chernev static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = { 3236cbe63bfdSIskren Chernev .gdscr = 0x7d060, 3237cbe63bfdSIskren Chernev .pd = { 3238cbe63bfdSIskren Chernev .name = "hlos1_vote_turing_mmu_tbu1", 3239cbe63bfdSIskren Chernev }, 3240cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3241cbe63bfdSIskren Chernev .flags = VOTABLE, 3242cbe63bfdSIskren Chernev }; 3243cbe63bfdSIskren Chernev 3244cbe63bfdSIskren Chernev static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { 3245*e41bdd18SShawn Guo .gdscr = 0x7d07c, 3246cbe63bfdSIskren Chernev .pd = { 3247cbe63bfdSIskren Chernev .name = "hlos1_vote_turing_mmu_tbu0", 3248cbe63bfdSIskren Chernev }, 3249cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3250cbe63bfdSIskren Chernev .flags = VOTABLE, 3251cbe63bfdSIskren Chernev }; 3252cbe63bfdSIskren Chernev 3253cbe63bfdSIskren Chernev static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = { 3254cbe63bfdSIskren Chernev .gdscr = 0x7d074, 3255cbe63bfdSIskren Chernev .pd = { 3256cbe63bfdSIskren Chernev .name = "hlos1_vote_mm_snoc_mmu_tbu_rt", 3257cbe63bfdSIskren Chernev }, 3258cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3259cbe63bfdSIskren Chernev .flags = VOTABLE, 3260cbe63bfdSIskren Chernev }; 3261cbe63bfdSIskren Chernev 3262cbe63bfdSIskren Chernev static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = { 3263cbe63bfdSIskren Chernev .gdscr = 0x7d078, 3264cbe63bfdSIskren Chernev .pd = { 3265cbe63bfdSIskren Chernev .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt", 3266cbe63bfdSIskren Chernev }, 3267cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3268cbe63bfdSIskren Chernev .flags = VOTABLE, 3269cbe63bfdSIskren Chernev }; 3270cbe63bfdSIskren Chernev 3271cbe63bfdSIskren Chernev static struct clk_regmap *gcc_sm6115_clocks[] = { 3272cbe63bfdSIskren Chernev [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr, 3273cbe63bfdSIskren Chernev [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr, 3274cbe63bfdSIskren Chernev [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr, 3275cbe63bfdSIskren Chernev [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3276cbe63bfdSIskren Chernev [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, 3277cbe63bfdSIskren Chernev [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, 3278cbe63bfdSIskren Chernev [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 3279cbe63bfdSIskren Chernev [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 3280cbe63bfdSIskren Chernev [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, 3281cbe63bfdSIskren Chernev [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, 3282cbe63bfdSIskren Chernev [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr, 3283cbe63bfdSIskren Chernev [GCC_CAMSS_CAMNOC_NTS_XO_CLK] = &gcc_camss_camnoc_nts_xo_clk.clkr, 3284cbe63bfdSIskren Chernev [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr, 3285cbe63bfdSIskren Chernev [GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr, 3286cbe63bfdSIskren Chernev [GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr, 3287cbe63bfdSIskren Chernev [GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr, 3288cbe63bfdSIskren Chernev [GCC_CAMSS_CPHY_2_CLK] = &gcc_camss_cphy_2_clk.clkr, 3289cbe63bfdSIskren Chernev [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 3290cbe63bfdSIskren Chernev [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr, 3291cbe63bfdSIskren Chernev [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, 3292cbe63bfdSIskren Chernev [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr, 3293cbe63bfdSIskren Chernev [GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr, 3294cbe63bfdSIskren Chernev [GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr, 3295cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 3296cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr, 3297cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 3298cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr, 3299cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, 3300cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr, 3301cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr, 3302cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr, 3303cbe63bfdSIskren Chernev [GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr, 3304cbe63bfdSIskren Chernev [GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr, 3305cbe63bfdSIskren Chernev [GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr, 3306cbe63bfdSIskren Chernev [GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr, 3307cbe63bfdSIskren Chernev [GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr, 3308cbe63bfdSIskren Chernev [GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr, 3309cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr, 3310cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr, 3311cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr, 3312cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr, 3313cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr, 3314cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr, 3315cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr, 3316cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr, 3317cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr, 3318cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr, 3319cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_2_CLK] = &gcc_camss_tfe_2_clk.clkr, 3320cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_2_CLK_SRC] = &gcc_camss_tfe_2_clk_src.clkr, 3321cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_2_CPHY_RX_CLK] = &gcc_camss_tfe_2_cphy_rx_clk.clkr, 3322cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_2_CSID_CLK] = &gcc_camss_tfe_2_csid_clk.clkr, 3323cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_2_CSID_CLK_SRC] = &gcc_camss_tfe_2_csid_clk_src.clkr, 3324cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr, 3325cbe63bfdSIskren Chernev [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 3326cbe63bfdSIskren Chernev [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, 3327cbe63bfdSIskren Chernev [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3328cbe63bfdSIskren Chernev [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, 3329cbe63bfdSIskren Chernev [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, 3330cbe63bfdSIskren Chernev [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 3331cbe63bfdSIskren Chernev [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 3332cbe63bfdSIskren Chernev [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3333cbe63bfdSIskren Chernev [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, 3334cbe63bfdSIskren Chernev [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 3335cbe63bfdSIskren Chernev [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3336cbe63bfdSIskren Chernev [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3337cbe63bfdSIskren Chernev [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3338cbe63bfdSIskren Chernev [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3339cbe63bfdSIskren Chernev [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3340cbe63bfdSIskren Chernev [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3341cbe63bfdSIskren Chernev [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 3342cbe63bfdSIskren Chernev [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3343cbe63bfdSIskren Chernev [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3344cbe63bfdSIskren Chernev [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, 3345cbe63bfdSIskren Chernev [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3346cbe63bfdSIskren Chernev [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3347cbe63bfdSIskren Chernev [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, 3348cbe63bfdSIskren Chernev [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3349cbe63bfdSIskren Chernev [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3350cbe63bfdSIskren Chernev [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3351cbe63bfdSIskren Chernev [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3352cbe63bfdSIskren Chernev [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3353cbe63bfdSIskren Chernev [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3354cbe63bfdSIskren Chernev [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3355cbe63bfdSIskren Chernev [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3356cbe63bfdSIskren Chernev [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr, 3357cbe63bfdSIskren Chernev [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3358cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 3359cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 3360cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3361cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3362cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3363cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3364cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3365cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3366cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3367cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3368cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3369cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3370cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3371cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3372cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3373cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3374cbe63bfdSIskren Chernev [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3375cbe63bfdSIskren Chernev [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3376cbe63bfdSIskren Chernev [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 3377cbe63bfdSIskren Chernev [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 3378cbe63bfdSIskren Chernev [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 3379cbe63bfdSIskren Chernev [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3380cbe63bfdSIskren Chernev [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3381cbe63bfdSIskren Chernev [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3382cbe63bfdSIskren Chernev [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 3383cbe63bfdSIskren Chernev [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, 3384cbe63bfdSIskren Chernev [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, 3385cbe63bfdSIskren Chernev [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, 3386cbe63bfdSIskren Chernev [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3387cbe63bfdSIskren Chernev [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3388cbe63bfdSIskren Chernev [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3389cbe63bfdSIskren Chernev [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3390cbe63bfdSIskren Chernev [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3391cbe63bfdSIskren Chernev [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3392cbe63bfdSIskren Chernev [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3393cbe63bfdSIskren Chernev [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3394cbe63bfdSIskren Chernev [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3395cbe63bfdSIskren Chernev [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3396cbe63bfdSIskren Chernev [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 3397cbe63bfdSIskren Chernev &gcc_ufs_phy_unipro_core_clk_src.clkr, 3398cbe63bfdSIskren Chernev [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3399cbe63bfdSIskren Chernev [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3400cbe63bfdSIskren Chernev [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3401cbe63bfdSIskren Chernev [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 3402cbe63bfdSIskren Chernev &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3403cbe63bfdSIskren Chernev [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = 3404cbe63bfdSIskren Chernev &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3405cbe63bfdSIskren Chernev [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3406cbe63bfdSIskren Chernev [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 3407cbe63bfdSIskren Chernev [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3408cbe63bfdSIskren Chernev [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3409cbe63bfdSIskren Chernev [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3410cbe63bfdSIskren Chernev [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr, 3411cbe63bfdSIskren Chernev [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr, 3412cbe63bfdSIskren Chernev [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr, 3413cbe63bfdSIskren Chernev [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 3414cbe63bfdSIskren Chernev [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3415cbe63bfdSIskren Chernev [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, 3416cbe63bfdSIskren Chernev [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr, 3417cbe63bfdSIskren Chernev [GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr, 3418cbe63bfdSIskren Chernev [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr, 3419cbe63bfdSIskren Chernev [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 3420cbe63bfdSIskren Chernev [GPLL0] = &gpll0.clkr, 3421cbe63bfdSIskren Chernev [GPLL0_OUT_AUX2] = &gpll0_out_aux2.clkr, 3422cbe63bfdSIskren Chernev [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr, 3423cbe63bfdSIskren Chernev [GPLL10] = &gpll10.clkr, 3424cbe63bfdSIskren Chernev [GPLL10_OUT_MAIN] = &gpll10_out_main.clkr, 3425cbe63bfdSIskren Chernev [GPLL11] = &gpll11.clkr, 3426cbe63bfdSIskren Chernev [GPLL11_OUT_MAIN] = &gpll11_out_main.clkr, 3427cbe63bfdSIskren Chernev [GPLL3] = &gpll3.clkr, 3428cbe63bfdSIskren Chernev [GPLL4] = &gpll4.clkr, 3429cbe63bfdSIskren Chernev [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr, 3430cbe63bfdSIskren Chernev [GPLL6] = &gpll6.clkr, 3431cbe63bfdSIskren Chernev [GPLL6_OUT_MAIN] = &gpll6_out_main.clkr, 3432cbe63bfdSIskren Chernev [GPLL7] = &gpll7.clkr, 3433cbe63bfdSIskren Chernev [GPLL7_OUT_MAIN] = &gpll7_out_main.clkr, 3434cbe63bfdSIskren Chernev [GPLL8] = &gpll8.clkr, 3435cbe63bfdSIskren Chernev [GPLL8_OUT_MAIN] = &gpll8_out_main.clkr, 3436cbe63bfdSIskren Chernev [GPLL9] = &gpll9.clkr, 3437cbe63bfdSIskren Chernev [GPLL9_OUT_MAIN] = &gpll9_out_main.clkr, 3438cbe63bfdSIskren Chernev }; 3439cbe63bfdSIskren Chernev 3440cbe63bfdSIskren Chernev static const struct qcom_reset_map gcc_sm6115_resets[] = { 3441cbe63bfdSIskren Chernev [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, 3442cbe63bfdSIskren Chernev [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, 3443cbe63bfdSIskren Chernev [GCC_SDCC1_BCR] = { 0x38000 }, 3444cbe63bfdSIskren Chernev [GCC_SDCC2_BCR] = { 0x1e000 }, 3445cbe63bfdSIskren Chernev [GCC_UFS_PHY_BCR] = { 0x45000 }, 3446cbe63bfdSIskren Chernev [GCC_USB30_PRIM_BCR] = { 0x1a000 }, 3447cbe63bfdSIskren Chernev [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, 3448cbe63bfdSIskren Chernev [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, 3449cbe63bfdSIskren Chernev [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, 3450cbe63bfdSIskren Chernev [GCC_VCODEC0_BCR] = { 0x58094 }, 3451cbe63bfdSIskren Chernev [GCC_VENUS_BCR] = { 0x58078 }, 3452cbe63bfdSIskren Chernev [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 }, 3453cbe63bfdSIskren Chernev }; 3454cbe63bfdSIskren Chernev 3455cbe63bfdSIskren Chernev static struct gdsc *gcc_sm6115_gdscs[] = { 3456cbe63bfdSIskren Chernev [GCC_CAMSS_TOP_GDSC] = &gcc_camss_top_gdsc, 3457cbe63bfdSIskren Chernev [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, 3458cbe63bfdSIskren Chernev [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 3459cbe63bfdSIskren Chernev [GCC_VCODEC0_GDSC] = &gcc_vcodec0_gdsc, 3460cbe63bfdSIskren Chernev [GCC_VENUS_GDSC] = &gcc_venus_gdsc, 3461cbe63bfdSIskren Chernev [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, 3462cbe63bfdSIskren Chernev [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc, 3463cbe63bfdSIskren Chernev [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc, 3464cbe63bfdSIskren Chernev [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc, 3465cbe63bfdSIskren Chernev }; 3466cbe63bfdSIskren Chernev 3467cbe63bfdSIskren Chernev static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3468cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3469cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3470cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3471cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3472cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3473cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3474cbe63bfdSIskren Chernev }; 3475cbe63bfdSIskren Chernev 3476cbe63bfdSIskren Chernev static const struct regmap_config gcc_sm6115_regmap_config = { 3477cbe63bfdSIskren Chernev .reg_bits = 32, 3478cbe63bfdSIskren Chernev .reg_stride = 4, 3479cbe63bfdSIskren Chernev .val_bits = 32, 3480cbe63bfdSIskren Chernev .max_register = 0xc7000, 3481cbe63bfdSIskren Chernev .fast_io = true, 3482cbe63bfdSIskren Chernev }; 3483cbe63bfdSIskren Chernev 3484cbe63bfdSIskren Chernev static const struct qcom_cc_desc gcc_sm6115_desc = { 3485cbe63bfdSIskren Chernev .config = &gcc_sm6115_regmap_config, 3486cbe63bfdSIskren Chernev .clks = gcc_sm6115_clocks, 3487cbe63bfdSIskren Chernev .num_clks = ARRAY_SIZE(gcc_sm6115_clocks), 3488cbe63bfdSIskren Chernev .resets = gcc_sm6115_resets, 3489cbe63bfdSIskren Chernev .num_resets = ARRAY_SIZE(gcc_sm6115_resets), 3490cbe63bfdSIskren Chernev .gdscs = gcc_sm6115_gdscs, 3491cbe63bfdSIskren Chernev .num_gdscs = ARRAY_SIZE(gcc_sm6115_gdscs), 3492cbe63bfdSIskren Chernev }; 3493cbe63bfdSIskren Chernev 3494cbe63bfdSIskren Chernev static const struct of_device_id gcc_sm6115_match_table[] = { 3495cbe63bfdSIskren Chernev { .compatible = "qcom,gcc-sm6115" }, 3496cbe63bfdSIskren Chernev { } 3497cbe63bfdSIskren Chernev }; 3498cbe63bfdSIskren Chernev MODULE_DEVICE_TABLE(of, gcc_sm6115_match_table); 3499cbe63bfdSIskren Chernev 3500cbe63bfdSIskren Chernev static int gcc_sm6115_probe(struct platform_device *pdev) 3501cbe63bfdSIskren Chernev { 3502cbe63bfdSIskren Chernev struct regmap *regmap; 3503cbe63bfdSIskren Chernev int ret; 3504cbe63bfdSIskren Chernev 3505cbe63bfdSIskren Chernev regmap = qcom_cc_map(pdev, &gcc_sm6115_desc); 3506cbe63bfdSIskren Chernev if (IS_ERR(regmap)) 3507cbe63bfdSIskren Chernev return PTR_ERR(regmap); 3508cbe63bfdSIskren Chernev 3509cbe63bfdSIskren Chernev ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3510cbe63bfdSIskren Chernev ARRAY_SIZE(gcc_dfs_clocks)); 3511cbe63bfdSIskren Chernev if (ret) 3512cbe63bfdSIskren Chernev return ret; 3513cbe63bfdSIskren Chernev 3514cbe63bfdSIskren Chernev clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config); 3515cbe63bfdSIskren Chernev clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config); 3516cbe63bfdSIskren Chernev clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config); 3517cbe63bfdSIskren Chernev clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config); 3518cbe63bfdSIskren Chernev 3519cbe63bfdSIskren Chernev return qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap); 3520cbe63bfdSIskren Chernev } 3521cbe63bfdSIskren Chernev 3522cbe63bfdSIskren Chernev static struct platform_driver gcc_sm6115_driver = { 3523cbe63bfdSIskren Chernev .probe = gcc_sm6115_probe, 3524cbe63bfdSIskren Chernev .driver = { 3525cbe63bfdSIskren Chernev .name = "gcc-sm6115", 3526cbe63bfdSIskren Chernev .of_match_table = gcc_sm6115_match_table, 3527cbe63bfdSIskren Chernev }, 3528cbe63bfdSIskren Chernev }; 3529cbe63bfdSIskren Chernev 3530cbe63bfdSIskren Chernev static int __init gcc_sm6115_init(void) 3531cbe63bfdSIskren Chernev { 3532cbe63bfdSIskren Chernev return platform_driver_register(&gcc_sm6115_driver); 3533cbe63bfdSIskren Chernev } 3534cbe63bfdSIskren Chernev subsys_initcall(gcc_sm6115_init); 3535cbe63bfdSIskren Chernev 3536cbe63bfdSIskren Chernev static void __exit gcc_sm6115_exit(void) 3537cbe63bfdSIskren Chernev { 3538cbe63bfdSIskren Chernev platform_driver_unregister(&gcc_sm6115_driver); 3539cbe63bfdSIskren Chernev } 3540cbe63bfdSIskren Chernev module_exit(gcc_sm6115_exit); 3541cbe63bfdSIskren Chernev 3542cbe63bfdSIskren Chernev MODULE_DESCRIPTION("QTI GCC SM6115 and SM4250 Driver"); 3543cbe63bfdSIskren Chernev MODULE_LICENSE("GPL v2"); 3544cbe63bfdSIskren Chernev MODULE_ALIAS("platform:gcc-sm6115"); 3545