1*cbe63bfdSIskren Chernev // SPDX-License-Identifier: GPL-2.0-only 2*cbe63bfdSIskren Chernev /* 3*cbe63bfdSIskren Chernev * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. 4*cbe63bfdSIskren Chernev */ 5*cbe63bfdSIskren Chernev 6*cbe63bfdSIskren Chernev #include <linux/err.h> 7*cbe63bfdSIskren Chernev #include <linux/kernel.h> 8*cbe63bfdSIskren Chernev #include <linux/module.h> 9*cbe63bfdSIskren Chernev #include <linux/of_device.h> 10*cbe63bfdSIskren Chernev #include <linux/clk-provider.h> 11*cbe63bfdSIskren Chernev #include <linux/regmap.h> 12*cbe63bfdSIskren Chernev #include <linux/reset-controller.h> 13*cbe63bfdSIskren Chernev 14*cbe63bfdSIskren Chernev #include <dt-bindings/clock/qcom,gcc-sm6115.h> 15*cbe63bfdSIskren Chernev 16*cbe63bfdSIskren Chernev #include "clk-alpha-pll.h" 17*cbe63bfdSIskren Chernev #include "clk-branch.h" 18*cbe63bfdSIskren Chernev #include "clk-pll.h" 19*cbe63bfdSIskren Chernev #include "clk-rcg.h" 20*cbe63bfdSIskren Chernev #include "clk-regmap.h" 21*cbe63bfdSIskren Chernev #include "clk-regmap-divider.h" 22*cbe63bfdSIskren Chernev #include "common.h" 23*cbe63bfdSIskren Chernev #include "gdsc.h" 24*cbe63bfdSIskren Chernev #include "reset.h" 25*cbe63bfdSIskren Chernev 26*cbe63bfdSIskren Chernev enum { 27*cbe63bfdSIskren Chernev P_BI_TCXO, 28*cbe63bfdSIskren Chernev P_GPLL0_OUT_AUX2, 29*cbe63bfdSIskren Chernev P_GPLL0_OUT_EARLY, 30*cbe63bfdSIskren Chernev P_GPLL10_OUT_MAIN, 31*cbe63bfdSIskren Chernev P_GPLL11_OUT_MAIN, 32*cbe63bfdSIskren Chernev P_GPLL3_OUT_EARLY, 33*cbe63bfdSIskren Chernev P_GPLL4_OUT_MAIN, 34*cbe63bfdSIskren Chernev P_GPLL6_OUT_EARLY, 35*cbe63bfdSIskren Chernev P_GPLL6_OUT_MAIN, 36*cbe63bfdSIskren Chernev P_GPLL7_OUT_MAIN, 37*cbe63bfdSIskren Chernev P_GPLL8_OUT_EARLY, 38*cbe63bfdSIskren Chernev P_GPLL8_OUT_MAIN, 39*cbe63bfdSIskren Chernev P_GPLL9_OUT_EARLY, 40*cbe63bfdSIskren Chernev P_GPLL9_OUT_MAIN, 41*cbe63bfdSIskren Chernev P_SLEEP_CLK, 42*cbe63bfdSIskren Chernev }; 43*cbe63bfdSIskren Chernev 44*cbe63bfdSIskren Chernev static struct pll_vco default_vco[] = { 45*cbe63bfdSIskren Chernev { 500000000, 1000000000, 2 }, 46*cbe63bfdSIskren Chernev }; 47*cbe63bfdSIskren Chernev 48*cbe63bfdSIskren Chernev static struct pll_vco gpll9_vco[] = { 49*cbe63bfdSIskren Chernev { 500000000, 1250000000, 0 }, 50*cbe63bfdSIskren Chernev }; 51*cbe63bfdSIskren Chernev 52*cbe63bfdSIskren Chernev static struct pll_vco gpll10_vco[] = { 53*cbe63bfdSIskren Chernev { 750000000, 1500000000, 1 }, 54*cbe63bfdSIskren Chernev }; 55*cbe63bfdSIskren Chernev 56*cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll0 = { 57*cbe63bfdSIskren Chernev .offset = 0x0, 58*cbe63bfdSIskren Chernev .vco_table = default_vco, 59*cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 60*cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 61*cbe63bfdSIskren Chernev .clkr = { 62*cbe63bfdSIskren Chernev .enable_reg = 0x79000, 63*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 64*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 65*cbe63bfdSIskren Chernev .name = "gpll0", 66*cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 67*cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 68*cbe63bfdSIskren Chernev }, 69*cbe63bfdSIskren Chernev .num_parents = 1, 70*cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 71*cbe63bfdSIskren Chernev }, 72*cbe63bfdSIskren Chernev }, 73*cbe63bfdSIskren Chernev }; 74*cbe63bfdSIskren Chernev 75*cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll0_out_aux2[] = { 76*cbe63bfdSIskren Chernev { 0x1, 2 }, 77*cbe63bfdSIskren Chernev { } 78*cbe63bfdSIskren Chernev }; 79*cbe63bfdSIskren Chernev 80*cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll0_out_aux2 = { 81*cbe63bfdSIskren Chernev .offset = 0x0, 82*cbe63bfdSIskren Chernev .post_div_shift = 8, 83*cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll0_out_aux2, 84*cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2), 85*cbe63bfdSIskren Chernev .width = 4, 86*cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 87*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 88*cbe63bfdSIskren Chernev .name = "gpll0_out_aux2", 89*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 90*cbe63bfdSIskren Chernev .num_parents = 1, 91*cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 92*cbe63bfdSIskren Chernev }, 93*cbe63bfdSIskren Chernev }; 94*cbe63bfdSIskren Chernev 95*cbe63bfdSIskren Chernev /* listed as BRAMMO, but it doesn't really match */ 96*cbe63bfdSIskren Chernev static const u8 clk_gpll9_regs[PLL_OFF_MAX_REGS] = { 97*cbe63bfdSIskren Chernev [PLL_OFF_L_VAL] = 0x04, 98*cbe63bfdSIskren Chernev [PLL_OFF_ALPHA_VAL] = 0x08, 99*cbe63bfdSIskren Chernev [PLL_OFF_ALPHA_VAL_U] = 0x0c, 100*cbe63bfdSIskren Chernev [PLL_OFF_TEST_CTL] = 0x10, 101*cbe63bfdSIskren Chernev [PLL_OFF_TEST_CTL_U] = 0x14, 102*cbe63bfdSIskren Chernev [PLL_OFF_USER_CTL] = 0x18, 103*cbe63bfdSIskren Chernev [PLL_OFF_CONFIG_CTL] = 0x1C, 104*cbe63bfdSIskren Chernev [PLL_OFF_STATUS] = 0x20, 105*cbe63bfdSIskren Chernev }; 106*cbe63bfdSIskren Chernev 107*cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll0_out_main[] = { 108*cbe63bfdSIskren Chernev { 0x0, 1 }, 109*cbe63bfdSIskren Chernev { } 110*cbe63bfdSIskren Chernev }; 111*cbe63bfdSIskren Chernev 112*cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll0_out_main = { 113*cbe63bfdSIskren Chernev .offset = 0x0, 114*cbe63bfdSIskren Chernev .post_div_shift = 8, 115*cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll0_out_main, 116*cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_main), 117*cbe63bfdSIskren Chernev .width = 4, 118*cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 119*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 120*cbe63bfdSIskren Chernev .name = "gpll0_out_main", 121*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 122*cbe63bfdSIskren Chernev .num_parents = 1, 123*cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 124*cbe63bfdSIskren Chernev }, 125*cbe63bfdSIskren Chernev }; 126*cbe63bfdSIskren Chernev 127*cbe63bfdSIskren Chernev /* 1152MHz configuration */ 128*cbe63bfdSIskren Chernev static const struct alpha_pll_config gpll10_config = { 129*cbe63bfdSIskren Chernev .l = 0x3c, 130*cbe63bfdSIskren Chernev .vco_val = 0x1 << 20, 131*cbe63bfdSIskren Chernev .vco_mask = GENMASK(21, 20), 132*cbe63bfdSIskren Chernev .main_output_mask = BIT(0), 133*cbe63bfdSIskren Chernev .config_ctl_val = 0x4001055b, 134*cbe63bfdSIskren Chernev }; 135*cbe63bfdSIskren Chernev 136*cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll10 = { 137*cbe63bfdSIskren Chernev .offset = 0xa000, 138*cbe63bfdSIskren Chernev .vco_table = gpll10_vco, 139*cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(gpll10_vco), 140*cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 141*cbe63bfdSIskren Chernev .clkr = { 142*cbe63bfdSIskren Chernev .enable_reg = 0x79000, 143*cbe63bfdSIskren Chernev .enable_mask = BIT(10), 144*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 145*cbe63bfdSIskren Chernev .name = "gpll10", 146*cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 147*cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 148*cbe63bfdSIskren Chernev }, 149*cbe63bfdSIskren Chernev .num_parents = 1, 150*cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 151*cbe63bfdSIskren Chernev }, 152*cbe63bfdSIskren Chernev }, 153*cbe63bfdSIskren Chernev }; 154*cbe63bfdSIskren Chernev 155*cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll10_out_main[] = { 156*cbe63bfdSIskren Chernev { 0x0, 1 }, 157*cbe63bfdSIskren Chernev { } 158*cbe63bfdSIskren Chernev }; 159*cbe63bfdSIskren Chernev 160*cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll10_out_main = { 161*cbe63bfdSIskren Chernev .offset = 0xa000, 162*cbe63bfdSIskren Chernev .post_div_shift = 8, 163*cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll10_out_main, 164*cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll10_out_main), 165*cbe63bfdSIskren Chernev .width = 4, 166*cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 167*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 168*cbe63bfdSIskren Chernev .name = "gpll10_out_main", 169*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll10.clkr.hw }, 170*cbe63bfdSIskren Chernev .num_parents = 1, 171*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 172*cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ops, 173*cbe63bfdSIskren Chernev }, 174*cbe63bfdSIskren Chernev }; 175*cbe63bfdSIskren Chernev 176*cbe63bfdSIskren Chernev /* 600MHz configuration */ 177*cbe63bfdSIskren Chernev static const struct alpha_pll_config gpll11_config = { 178*cbe63bfdSIskren Chernev .l = 0x1F, 179*cbe63bfdSIskren Chernev .alpha = 0x0, 180*cbe63bfdSIskren Chernev .alpha_hi = 0x40, 181*cbe63bfdSIskren Chernev .alpha_en_mask = BIT(24), 182*cbe63bfdSIskren Chernev .vco_val = 0x2 << 20, 183*cbe63bfdSIskren Chernev .vco_mask = GENMASK(21, 20), 184*cbe63bfdSIskren Chernev .config_ctl_val = 0x4001055b, 185*cbe63bfdSIskren Chernev }; 186*cbe63bfdSIskren Chernev 187*cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll11 = { 188*cbe63bfdSIskren Chernev .offset = 0xb000, 189*cbe63bfdSIskren Chernev .vco_table = default_vco, 190*cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 191*cbe63bfdSIskren Chernev .flags = SUPPORTS_DYNAMIC_UPDATE, 192*cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 193*cbe63bfdSIskren Chernev .clkr = { 194*cbe63bfdSIskren Chernev .enable_reg = 0x79000, 195*cbe63bfdSIskren Chernev .enable_mask = BIT(11), 196*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 197*cbe63bfdSIskren Chernev .name = "gpll11", 198*cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 199*cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 200*cbe63bfdSIskren Chernev }, 201*cbe63bfdSIskren Chernev .num_parents = 1, 202*cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 203*cbe63bfdSIskren Chernev }, 204*cbe63bfdSIskren Chernev }, 205*cbe63bfdSIskren Chernev }; 206*cbe63bfdSIskren Chernev 207*cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll11_out_main[] = { 208*cbe63bfdSIskren Chernev { 0x0, 1 }, 209*cbe63bfdSIskren Chernev { } 210*cbe63bfdSIskren Chernev }; 211*cbe63bfdSIskren Chernev 212*cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll11_out_main = { 213*cbe63bfdSIskren Chernev .offset = 0xb000, 214*cbe63bfdSIskren Chernev .post_div_shift = 8, 215*cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll11_out_main, 216*cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll11_out_main), 217*cbe63bfdSIskren Chernev .width = 4, 218*cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 219*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 220*cbe63bfdSIskren Chernev .name = "gpll11_out_main", 221*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll11.clkr.hw }, 222*cbe63bfdSIskren Chernev .num_parents = 1, 223*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 224*cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ops, 225*cbe63bfdSIskren Chernev }, 226*cbe63bfdSIskren Chernev }; 227*cbe63bfdSIskren Chernev 228*cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll3 = { 229*cbe63bfdSIskren Chernev .offset = 0x3000, 230*cbe63bfdSIskren Chernev .vco_table = default_vco, 231*cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 232*cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 233*cbe63bfdSIskren Chernev .clkr = { 234*cbe63bfdSIskren Chernev .enable_reg = 0x79000, 235*cbe63bfdSIskren Chernev .enable_mask = BIT(3), 236*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 237*cbe63bfdSIskren Chernev .name = "gpll3", 238*cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 239*cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 240*cbe63bfdSIskren Chernev }, 241*cbe63bfdSIskren Chernev .num_parents = 1, 242*cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 243*cbe63bfdSIskren Chernev }, 244*cbe63bfdSIskren Chernev }, 245*cbe63bfdSIskren Chernev }; 246*cbe63bfdSIskren Chernev 247*cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll4 = { 248*cbe63bfdSIskren Chernev .offset = 0x4000, 249*cbe63bfdSIskren Chernev .vco_table = default_vco, 250*cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 251*cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 252*cbe63bfdSIskren Chernev .clkr = { 253*cbe63bfdSIskren Chernev .enable_reg = 0x79000, 254*cbe63bfdSIskren Chernev .enable_mask = BIT(4), 255*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 256*cbe63bfdSIskren Chernev .name = "gpll4", 257*cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 258*cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 259*cbe63bfdSIskren Chernev }, 260*cbe63bfdSIskren Chernev .num_parents = 1, 261*cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 262*cbe63bfdSIskren Chernev }, 263*cbe63bfdSIskren Chernev }, 264*cbe63bfdSIskren Chernev }; 265*cbe63bfdSIskren Chernev 266*cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll4_out_main[] = { 267*cbe63bfdSIskren Chernev { 0x0, 1 }, 268*cbe63bfdSIskren Chernev { } 269*cbe63bfdSIskren Chernev }; 270*cbe63bfdSIskren Chernev 271*cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll4_out_main = { 272*cbe63bfdSIskren Chernev .offset = 0x4000, 273*cbe63bfdSIskren Chernev .post_div_shift = 8, 274*cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll4_out_main, 275*cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll4_out_main), 276*cbe63bfdSIskren Chernev .width = 4, 277*cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 278*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 279*cbe63bfdSIskren Chernev .name = "gpll4_out_main", 280*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll4.clkr.hw }, 281*cbe63bfdSIskren Chernev .num_parents = 1, 282*cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 283*cbe63bfdSIskren Chernev }, 284*cbe63bfdSIskren Chernev }; 285*cbe63bfdSIskren Chernev 286*cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll6 = { 287*cbe63bfdSIskren Chernev .offset = 0x6000, 288*cbe63bfdSIskren Chernev .vco_table = default_vco, 289*cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 290*cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 291*cbe63bfdSIskren Chernev .clkr = { 292*cbe63bfdSIskren Chernev .enable_reg = 0x79000, 293*cbe63bfdSIskren Chernev .enable_mask = BIT(6), 294*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 295*cbe63bfdSIskren Chernev .name = "gpll6", 296*cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 297*cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 298*cbe63bfdSIskren Chernev }, 299*cbe63bfdSIskren Chernev .num_parents = 1, 300*cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 301*cbe63bfdSIskren Chernev }, 302*cbe63bfdSIskren Chernev }, 303*cbe63bfdSIskren Chernev }; 304*cbe63bfdSIskren Chernev 305*cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll6_out_main[] = { 306*cbe63bfdSIskren Chernev { 0x1, 2 }, 307*cbe63bfdSIskren Chernev { } 308*cbe63bfdSIskren Chernev }; 309*cbe63bfdSIskren Chernev 310*cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll6_out_main = { 311*cbe63bfdSIskren Chernev .offset = 0x6000, 312*cbe63bfdSIskren Chernev .post_div_shift = 8, 313*cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll6_out_main, 314*cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main), 315*cbe63bfdSIskren Chernev .width = 4, 316*cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 317*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 318*cbe63bfdSIskren Chernev .name = "gpll6_out_main", 319*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw }, 320*cbe63bfdSIskren Chernev .num_parents = 1, 321*cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 322*cbe63bfdSIskren Chernev }, 323*cbe63bfdSIskren Chernev }; 324*cbe63bfdSIskren Chernev 325*cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll7 = { 326*cbe63bfdSIskren Chernev .offset = 0x7000, 327*cbe63bfdSIskren Chernev .vco_table = default_vco, 328*cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 329*cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 330*cbe63bfdSIskren Chernev .clkr = { 331*cbe63bfdSIskren Chernev .enable_reg = 0x79000, 332*cbe63bfdSIskren Chernev .enable_mask = BIT(7), 333*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 334*cbe63bfdSIskren Chernev .name = "gpll7", 335*cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 336*cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 337*cbe63bfdSIskren Chernev }, 338*cbe63bfdSIskren Chernev .num_parents = 1, 339*cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 340*cbe63bfdSIskren Chernev }, 341*cbe63bfdSIskren Chernev }, 342*cbe63bfdSIskren Chernev }; 343*cbe63bfdSIskren Chernev 344*cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll7_out_main[] = { 345*cbe63bfdSIskren Chernev { 0x0, 1 }, 346*cbe63bfdSIskren Chernev { } 347*cbe63bfdSIskren Chernev }; 348*cbe63bfdSIskren Chernev 349*cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll7_out_main = { 350*cbe63bfdSIskren Chernev .offset = 0x7000, 351*cbe63bfdSIskren Chernev .post_div_shift = 8, 352*cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll7_out_main, 353*cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll7_out_main), 354*cbe63bfdSIskren Chernev .width = 4, 355*cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 356*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 357*cbe63bfdSIskren Chernev .name = "gpll7_out_main", 358*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll7.clkr.hw }, 359*cbe63bfdSIskren Chernev .num_parents = 1, 360*cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 361*cbe63bfdSIskren Chernev }, 362*cbe63bfdSIskren Chernev }; 363*cbe63bfdSIskren Chernev 364*cbe63bfdSIskren Chernev /* 800MHz configuration */ 365*cbe63bfdSIskren Chernev static const struct alpha_pll_config gpll8_config = { 366*cbe63bfdSIskren Chernev .l = 0x29, 367*cbe63bfdSIskren Chernev .alpha = 0xAAAAAAAA, 368*cbe63bfdSIskren Chernev .alpha_hi = 0xAA, 369*cbe63bfdSIskren Chernev .alpha_en_mask = BIT(24), 370*cbe63bfdSIskren Chernev .vco_val = 0x2 << 20, 371*cbe63bfdSIskren Chernev .vco_mask = GENMASK(21, 20), 372*cbe63bfdSIskren Chernev .main_output_mask = BIT(0), 373*cbe63bfdSIskren Chernev .early_output_mask = BIT(3), 374*cbe63bfdSIskren Chernev .post_div_val = 0x1 << 8, 375*cbe63bfdSIskren Chernev .post_div_mask = GENMASK(11, 8), 376*cbe63bfdSIskren Chernev .config_ctl_val = 0x4001055b, 377*cbe63bfdSIskren Chernev }; 378*cbe63bfdSIskren Chernev 379*cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll8 = { 380*cbe63bfdSIskren Chernev .offset = 0x8000, 381*cbe63bfdSIskren Chernev .vco_table = default_vco, 382*cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 383*cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 384*cbe63bfdSIskren Chernev .flags = SUPPORTS_DYNAMIC_UPDATE, 385*cbe63bfdSIskren Chernev .clkr = { 386*cbe63bfdSIskren Chernev .enable_reg = 0x79000, 387*cbe63bfdSIskren Chernev .enable_mask = BIT(8), 388*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 389*cbe63bfdSIskren Chernev .name = "gpll8", 390*cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 391*cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 392*cbe63bfdSIskren Chernev }, 393*cbe63bfdSIskren Chernev .num_parents = 1, 394*cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 395*cbe63bfdSIskren Chernev }, 396*cbe63bfdSIskren Chernev }, 397*cbe63bfdSIskren Chernev }; 398*cbe63bfdSIskren Chernev 399*cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll8_out_main[] = { 400*cbe63bfdSIskren Chernev { 0x1, 2 }, 401*cbe63bfdSIskren Chernev { } 402*cbe63bfdSIskren Chernev }; 403*cbe63bfdSIskren Chernev 404*cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll8_out_main = { 405*cbe63bfdSIskren Chernev .offset = 0x8000, 406*cbe63bfdSIskren Chernev .post_div_shift = 8, 407*cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll8_out_main, 408*cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main), 409*cbe63bfdSIskren Chernev .width = 4, 410*cbe63bfdSIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 411*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 412*cbe63bfdSIskren Chernev .name = "gpll8_out_main", 413*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw }, 414*cbe63bfdSIskren Chernev .num_parents = 1, 415*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 416*cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 417*cbe63bfdSIskren Chernev }, 418*cbe63bfdSIskren Chernev }; 419*cbe63bfdSIskren Chernev 420*cbe63bfdSIskren Chernev /* 1152MHz configuration */ 421*cbe63bfdSIskren Chernev static const struct alpha_pll_config gpll9_config = { 422*cbe63bfdSIskren Chernev .l = 0x3C, 423*cbe63bfdSIskren Chernev .alpha = 0x0, 424*cbe63bfdSIskren Chernev .post_div_val = 0x1 << 8, 425*cbe63bfdSIskren Chernev .post_div_mask = GENMASK(9, 8), 426*cbe63bfdSIskren Chernev .main_output_mask = BIT(0), 427*cbe63bfdSIskren Chernev .config_ctl_val = 0x00004289, 428*cbe63bfdSIskren Chernev }; 429*cbe63bfdSIskren Chernev 430*cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll9 = { 431*cbe63bfdSIskren Chernev .offset = 0x9000, 432*cbe63bfdSIskren Chernev .vco_table = gpll9_vco, 433*cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(gpll9_vco), 434*cbe63bfdSIskren Chernev .regs = clk_gpll9_regs, 435*cbe63bfdSIskren Chernev .clkr = { 436*cbe63bfdSIskren Chernev .enable_reg = 0x79000, 437*cbe63bfdSIskren Chernev .enable_mask = BIT(9), 438*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 439*cbe63bfdSIskren Chernev .name = "gpll9", 440*cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 441*cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 442*cbe63bfdSIskren Chernev }, 443*cbe63bfdSIskren Chernev .num_parents = 1, 444*cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 445*cbe63bfdSIskren Chernev }, 446*cbe63bfdSIskren Chernev }, 447*cbe63bfdSIskren Chernev }; 448*cbe63bfdSIskren Chernev 449*cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll9_out_main[] = { 450*cbe63bfdSIskren Chernev { 0x1, 2 }, 451*cbe63bfdSIskren Chernev { } 452*cbe63bfdSIskren Chernev }; 453*cbe63bfdSIskren Chernev 454*cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll9_out_main = { 455*cbe63bfdSIskren Chernev .offset = 0x9000, 456*cbe63bfdSIskren Chernev .post_div_shift = 8, 457*cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll9_out_main, 458*cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main), 459*cbe63bfdSIskren Chernev .width = 2, 460*cbe63bfdSIskren Chernev .regs = clk_gpll9_regs, 461*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 462*cbe63bfdSIskren Chernev .name = "gpll9_out_main", 463*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw }, 464*cbe63bfdSIskren Chernev .num_parents = 1, 465*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 466*cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ops, 467*cbe63bfdSIskren Chernev }, 468*cbe63bfdSIskren Chernev }; 469*cbe63bfdSIskren Chernev 470*cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_0[] = { 471*cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 472*cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 473*cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 474*cbe63bfdSIskren Chernev }; 475*cbe63bfdSIskren Chernev 476*cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_0[] = { 477*cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 478*cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 479*cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 480*cbe63bfdSIskren Chernev }; 481*cbe63bfdSIskren Chernev 482*cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_1[] = { 483*cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 484*cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 485*cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 486*cbe63bfdSIskren Chernev { P_GPLL6_OUT_MAIN, 4 }, 487*cbe63bfdSIskren Chernev }; 488*cbe63bfdSIskren Chernev 489*cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_1[] = { 490*cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 491*cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 492*cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 493*cbe63bfdSIskren Chernev { .hw = &gpll6_out_main.clkr.hw }, 494*cbe63bfdSIskren Chernev }; 495*cbe63bfdSIskren Chernev 496*cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_2[] = { 497*cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 498*cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 499*cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 500*cbe63bfdSIskren Chernev { P_SLEEP_CLK, 5 }, 501*cbe63bfdSIskren Chernev }; 502*cbe63bfdSIskren Chernev 503*cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_2[] = { 504*cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 505*cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 506*cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 507*cbe63bfdSIskren Chernev { .fw_name = "sleep_clk" }, 508*cbe63bfdSIskren Chernev }; 509*cbe63bfdSIskren Chernev 510*cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_3[] = { 511*cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 512*cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 513*cbe63bfdSIskren Chernev { P_GPLL9_OUT_EARLY, 2 }, 514*cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 515*cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 516*cbe63bfdSIskren Chernev }; 517*cbe63bfdSIskren Chernev 518*cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_3[] = { 519*cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 520*cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 521*cbe63bfdSIskren Chernev { .hw = &gpll9.clkr.hw }, 522*cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 523*cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 524*cbe63bfdSIskren Chernev }; 525*cbe63bfdSIskren Chernev 526*cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_4[] = { 527*cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 528*cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 529*cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 530*cbe63bfdSIskren Chernev { P_GPLL4_OUT_MAIN, 5 }, 531*cbe63bfdSIskren Chernev }; 532*cbe63bfdSIskren Chernev 533*cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_4[] = { 534*cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 535*cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 536*cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 537*cbe63bfdSIskren Chernev { .hw = &gpll4_out_main.clkr.hw }, 538*cbe63bfdSIskren Chernev }; 539*cbe63bfdSIskren Chernev 540*cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_5[] = { 541*cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 542*cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 543*cbe63bfdSIskren Chernev { P_GPLL8_OUT_EARLY, 2 }, 544*cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 545*cbe63bfdSIskren Chernev { P_GPLL8_OUT_MAIN, 4 }, 546*cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 547*cbe63bfdSIskren Chernev }; 548*cbe63bfdSIskren Chernev 549*cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_5[] = { 550*cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 551*cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 552*cbe63bfdSIskren Chernev { .hw = &gpll8.clkr.hw }, 553*cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 554*cbe63bfdSIskren Chernev { .hw = &gpll8_out_main.clkr.hw }, 555*cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 556*cbe63bfdSIskren Chernev }; 557*cbe63bfdSIskren Chernev 558*cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_6[] = { 559*cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 560*cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 561*cbe63bfdSIskren Chernev { P_GPLL8_OUT_EARLY, 2 }, 562*cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 563*cbe63bfdSIskren Chernev { P_GPLL6_OUT_MAIN, 4 }, 564*cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 565*cbe63bfdSIskren Chernev { P_GPLL3_OUT_EARLY, 6 }, 566*cbe63bfdSIskren Chernev }; 567*cbe63bfdSIskren Chernev 568*cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_6[] = { 569*cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 570*cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 571*cbe63bfdSIskren Chernev { .hw = &gpll8.clkr.hw }, 572*cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 573*cbe63bfdSIskren Chernev { .hw = &gpll6_out_main.clkr.hw }, 574*cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 575*cbe63bfdSIskren Chernev { .hw = &gpll3.clkr.hw }, 576*cbe63bfdSIskren Chernev }; 577*cbe63bfdSIskren Chernev 578*cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_7[] = { 579*cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 580*cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 581*cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 582*cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 583*cbe63bfdSIskren Chernev { P_GPLL4_OUT_MAIN, 5 }, 584*cbe63bfdSIskren Chernev { P_GPLL3_OUT_EARLY, 6 }, 585*cbe63bfdSIskren Chernev }; 586*cbe63bfdSIskren Chernev 587*cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_7[] = { 588*cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 589*cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 590*cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 591*cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 592*cbe63bfdSIskren Chernev { .hw = &gpll4_out_main.clkr.hw }, 593*cbe63bfdSIskren Chernev { .hw = &gpll3.clkr.hw }, 594*cbe63bfdSIskren Chernev }; 595*cbe63bfdSIskren Chernev 596*cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_8[] = { 597*cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 598*cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 599*cbe63bfdSIskren Chernev { P_GPLL8_OUT_EARLY, 2 }, 600*cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 601*cbe63bfdSIskren Chernev { P_GPLL8_OUT_MAIN, 4 }, 602*cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 603*cbe63bfdSIskren Chernev { P_GPLL3_OUT_EARLY, 6 }, 604*cbe63bfdSIskren Chernev }; 605*cbe63bfdSIskren Chernev 606*cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_8[] = { 607*cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 608*cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 609*cbe63bfdSIskren Chernev { .hw = &gpll8.clkr.hw }, 610*cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 611*cbe63bfdSIskren Chernev { .hw = &gpll8_out_main.clkr.hw }, 612*cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 613*cbe63bfdSIskren Chernev { .hw = &gpll3.clkr.hw }, 614*cbe63bfdSIskren Chernev }; 615*cbe63bfdSIskren Chernev 616*cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_9[] = { 617*cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 618*cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 619*cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 620*cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 621*cbe63bfdSIskren Chernev { P_GPLL8_OUT_MAIN, 4 }, 622*cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 623*cbe63bfdSIskren Chernev { P_GPLL3_OUT_EARLY, 6 }, 624*cbe63bfdSIskren Chernev }; 625*cbe63bfdSIskren Chernev 626*cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_9[] = { 627*cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 628*cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 629*cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 630*cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 631*cbe63bfdSIskren Chernev { .hw = &gpll8_out_main.clkr.hw }, 632*cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 633*cbe63bfdSIskren Chernev { .hw = &gpll3.clkr.hw }, 634*cbe63bfdSIskren Chernev }; 635*cbe63bfdSIskren Chernev 636*cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_10[] = { 637*cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 638*cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 639*cbe63bfdSIskren Chernev { P_GPLL8_OUT_EARLY, 2 }, 640*cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 641*cbe63bfdSIskren Chernev { P_GPLL6_OUT_EARLY, 4 }, 642*cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 643*cbe63bfdSIskren Chernev }; 644*cbe63bfdSIskren Chernev 645*cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_10[] = { 646*cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 647*cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 648*cbe63bfdSIskren Chernev { .hw = &gpll8.clkr.hw }, 649*cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 650*cbe63bfdSIskren Chernev { .hw = &gpll6.clkr.hw }, 651*cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 652*cbe63bfdSIskren Chernev }; 653*cbe63bfdSIskren Chernev 654*cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_11[] = { 655*cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 656*cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 657*cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 658*cbe63bfdSIskren Chernev { P_GPLL7_OUT_MAIN, 3 }, 659*cbe63bfdSIskren Chernev { P_GPLL4_OUT_MAIN, 5 }, 660*cbe63bfdSIskren Chernev }; 661*cbe63bfdSIskren Chernev 662*cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_11[] = { 663*cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 664*cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 665*cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 666*cbe63bfdSIskren Chernev { .hw = &gpll7_out_main.clkr.hw }, 667*cbe63bfdSIskren Chernev { .hw = &gpll4_out_main.clkr.hw }, 668*cbe63bfdSIskren Chernev }; 669*cbe63bfdSIskren Chernev 670*cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_12[] = { 671*cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 672*cbe63bfdSIskren Chernev { P_SLEEP_CLK, 5 }, 673*cbe63bfdSIskren Chernev }; 674*cbe63bfdSIskren Chernev 675*cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_12[] = { 676*cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 677*cbe63bfdSIskren Chernev { .fw_name = "sleep_clk" }, 678*cbe63bfdSIskren Chernev }; 679*cbe63bfdSIskren Chernev 680*cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_13[] = { 681*cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 682*cbe63bfdSIskren Chernev { P_GPLL11_OUT_MAIN, 1 }, 683*cbe63bfdSIskren Chernev }; 684*cbe63bfdSIskren Chernev 685*cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_13[] = { 686*cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 687*cbe63bfdSIskren Chernev { .hw = &gpll11_out_main.clkr.hw }, 688*cbe63bfdSIskren Chernev }; 689*cbe63bfdSIskren Chernev 690*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = { 691*cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 692*cbe63bfdSIskren Chernev F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 693*cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 694*cbe63bfdSIskren Chernev F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 695*cbe63bfdSIskren Chernev { } 696*cbe63bfdSIskren Chernev }; 697*cbe63bfdSIskren Chernev 698*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_axi_clk_src = { 699*cbe63bfdSIskren Chernev .cmd_rcgr = 0x5802c, 700*cbe63bfdSIskren Chernev .mnd_width = 0, 701*cbe63bfdSIskren Chernev .hid_width = 5, 702*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_7, 703*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_axi_clk_src, 704*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 705*cbe63bfdSIskren Chernev .name = "gcc_camss_axi_clk_src", 706*cbe63bfdSIskren Chernev .parent_data = gcc_parents_7, 707*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_7), 708*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 709*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 710*cbe63bfdSIskren Chernev }, 711*cbe63bfdSIskren Chernev }; 712*cbe63bfdSIskren Chernev 713*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = { 714*cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 715*cbe63bfdSIskren Chernev F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 716*cbe63bfdSIskren Chernev { } 717*cbe63bfdSIskren Chernev }; 718*cbe63bfdSIskren Chernev 719*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_cci_clk_src = { 720*cbe63bfdSIskren Chernev .cmd_rcgr = 0x56000, 721*cbe63bfdSIskren Chernev .mnd_width = 0, 722*cbe63bfdSIskren Chernev .hid_width = 5, 723*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_9, 724*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_cci_clk_src, 725*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 726*cbe63bfdSIskren Chernev .name = "gcc_camss_cci_clk_src", 727*cbe63bfdSIskren Chernev .parent_data = gcc_parents_9, 728*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_9), 729*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 730*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 731*cbe63bfdSIskren Chernev }, 732*cbe63bfdSIskren Chernev }; 733*cbe63bfdSIskren Chernev 734*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = { 735*cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 736*cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 737*cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 738*cbe63bfdSIskren Chernev F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0), 739*cbe63bfdSIskren Chernev { } 740*cbe63bfdSIskren Chernev }; 741*cbe63bfdSIskren Chernev 742*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { 743*cbe63bfdSIskren Chernev .cmd_rcgr = 0x59000, 744*cbe63bfdSIskren Chernev .mnd_width = 0, 745*cbe63bfdSIskren Chernev .hid_width = 5, 746*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_4, 747*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 748*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 749*cbe63bfdSIskren Chernev .name = "gcc_camss_csi0phytimer_clk_src", 750*cbe63bfdSIskren Chernev .parent_data = gcc_parents_4, 751*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_4), 752*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 753*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 754*cbe63bfdSIskren Chernev }, 755*cbe63bfdSIskren Chernev }; 756*cbe63bfdSIskren Chernev 757*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { 758*cbe63bfdSIskren Chernev .cmd_rcgr = 0x5901c, 759*cbe63bfdSIskren Chernev .mnd_width = 0, 760*cbe63bfdSIskren Chernev .hid_width = 5, 761*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_4, 762*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 763*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 764*cbe63bfdSIskren Chernev .name = "gcc_camss_csi1phytimer_clk_src", 765*cbe63bfdSIskren Chernev .parent_data = gcc_parents_4, 766*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_4), 767*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 768*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 769*cbe63bfdSIskren Chernev }, 770*cbe63bfdSIskren Chernev }; 771*cbe63bfdSIskren Chernev 772*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = { 773*cbe63bfdSIskren Chernev .cmd_rcgr = 0x59038, 774*cbe63bfdSIskren Chernev .mnd_width = 0, 775*cbe63bfdSIskren Chernev .hid_width = 5, 776*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_4, 777*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 778*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 779*cbe63bfdSIskren Chernev .name = "gcc_camss_csi2phytimer_clk_src", 780*cbe63bfdSIskren Chernev .parent_data = gcc_parents_4, 781*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_4), 782*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 783*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 784*cbe63bfdSIskren Chernev }, 785*cbe63bfdSIskren Chernev }; 786*cbe63bfdSIskren Chernev 787*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { 788*cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 789*cbe63bfdSIskren Chernev F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24), 790*cbe63bfdSIskren Chernev F(64000000, P_GPLL9_OUT_MAIN, 1, 1, 9), 791*cbe63bfdSIskren Chernev { } 792*cbe63bfdSIskren Chernev }; 793*cbe63bfdSIskren Chernev 794*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_mclk0_clk_src = { 795*cbe63bfdSIskren Chernev .cmd_rcgr = 0x51000, 796*cbe63bfdSIskren Chernev .mnd_width = 8, 797*cbe63bfdSIskren Chernev .hid_width = 5, 798*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_3, 799*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 800*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 801*cbe63bfdSIskren Chernev .name = "gcc_camss_mclk0_clk_src", 802*cbe63bfdSIskren Chernev .parent_data = gcc_parents_3, 803*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_3), 804*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 805*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 806*cbe63bfdSIskren Chernev }, 807*cbe63bfdSIskren Chernev }; 808*cbe63bfdSIskren Chernev 809*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_mclk1_clk_src = { 810*cbe63bfdSIskren Chernev .cmd_rcgr = 0x5101c, 811*cbe63bfdSIskren Chernev .mnd_width = 8, 812*cbe63bfdSIskren Chernev .hid_width = 5, 813*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_3, 814*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 815*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 816*cbe63bfdSIskren Chernev .name = "gcc_camss_mclk1_clk_src", 817*cbe63bfdSIskren Chernev .parent_data = gcc_parents_3, 818*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_3), 819*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 820*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 821*cbe63bfdSIskren Chernev }, 822*cbe63bfdSIskren Chernev }; 823*cbe63bfdSIskren Chernev 824*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_mclk2_clk_src = { 825*cbe63bfdSIskren Chernev .cmd_rcgr = 0x51038, 826*cbe63bfdSIskren Chernev .mnd_width = 8, 827*cbe63bfdSIskren Chernev .hid_width = 5, 828*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_3, 829*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 830*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 831*cbe63bfdSIskren Chernev .name = "gcc_camss_mclk2_clk_src", 832*cbe63bfdSIskren Chernev .parent_data = gcc_parents_3, 833*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_3), 834*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 835*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 836*cbe63bfdSIskren Chernev }, 837*cbe63bfdSIskren Chernev }; 838*cbe63bfdSIskren Chernev 839*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_mclk3_clk_src = { 840*cbe63bfdSIskren Chernev .cmd_rcgr = 0x51054, 841*cbe63bfdSIskren Chernev .mnd_width = 8, 842*cbe63bfdSIskren Chernev .hid_width = 5, 843*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_3, 844*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 845*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 846*cbe63bfdSIskren Chernev .name = "gcc_camss_mclk3_clk_src", 847*cbe63bfdSIskren Chernev .parent_data = gcc_parents_3, 848*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_3), 849*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 850*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 851*cbe63bfdSIskren Chernev }, 852*cbe63bfdSIskren Chernev }; 853*cbe63bfdSIskren Chernev 854*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = { 855*cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 856*cbe63bfdSIskren Chernev F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0), 857*cbe63bfdSIskren Chernev F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 858*cbe63bfdSIskren Chernev { } 859*cbe63bfdSIskren Chernev }; 860*cbe63bfdSIskren Chernev 861*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = { 862*cbe63bfdSIskren Chernev .cmd_rcgr = 0x55024, 863*cbe63bfdSIskren Chernev .mnd_width = 0, 864*cbe63bfdSIskren Chernev .hid_width = 5, 865*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_8, 866*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src, 867*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 868*cbe63bfdSIskren Chernev .name = "gcc_camss_ope_ahb_clk_src", 869*cbe63bfdSIskren Chernev .parent_data = gcc_parents_8, 870*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_8), 871*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 872*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 873*cbe63bfdSIskren Chernev }, 874*cbe63bfdSIskren Chernev }; 875*cbe63bfdSIskren Chernev 876*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = { 877*cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 878*cbe63bfdSIskren Chernev F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0), 879*cbe63bfdSIskren Chernev F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0), 880*cbe63bfdSIskren Chernev F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0), 881*cbe63bfdSIskren Chernev F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0), 882*cbe63bfdSIskren Chernev { } 883*cbe63bfdSIskren Chernev }; 884*cbe63bfdSIskren Chernev 885*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_ope_clk_src = { 886*cbe63bfdSIskren Chernev .cmd_rcgr = 0x55004, 887*cbe63bfdSIskren Chernev .mnd_width = 0, 888*cbe63bfdSIskren Chernev .hid_width = 5, 889*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_8, 890*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_ope_clk_src, 891*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 892*cbe63bfdSIskren Chernev .name = "gcc_camss_ope_clk_src", 893*cbe63bfdSIskren Chernev .parent_data = gcc_parents_8, 894*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_8), 895*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 896*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 897*cbe63bfdSIskren Chernev }, 898*cbe63bfdSIskren Chernev }; 899*cbe63bfdSIskren Chernev 900*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = { 901*cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 902*cbe63bfdSIskren Chernev F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0), 903*cbe63bfdSIskren Chernev F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0), 904*cbe63bfdSIskren Chernev F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0), 905*cbe63bfdSIskren Chernev F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0), 906*cbe63bfdSIskren Chernev F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0), 907*cbe63bfdSIskren Chernev F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0), 908*cbe63bfdSIskren Chernev F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0), 909*cbe63bfdSIskren Chernev F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0), 910*cbe63bfdSIskren Chernev F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0), 911*cbe63bfdSIskren Chernev F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0), 912*cbe63bfdSIskren Chernev F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0), 913*cbe63bfdSIskren Chernev F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0), 914*cbe63bfdSIskren Chernev F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0), 915*cbe63bfdSIskren Chernev F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0), 916*cbe63bfdSIskren Chernev F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0), 917*cbe63bfdSIskren Chernev { } 918*cbe63bfdSIskren Chernev }; 919*cbe63bfdSIskren Chernev 920*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_0_clk_src = { 921*cbe63bfdSIskren Chernev .cmd_rcgr = 0x52004, 922*cbe63bfdSIskren Chernev .mnd_width = 8, 923*cbe63bfdSIskren Chernev .hid_width = 5, 924*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_5, 925*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 926*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 927*cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_0_clk_src", 928*cbe63bfdSIskren Chernev .parent_data = gcc_parents_5, 929*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_5), 930*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 931*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 932*cbe63bfdSIskren Chernev }, 933*cbe63bfdSIskren Chernev }; 934*cbe63bfdSIskren Chernev 935*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = { 936*cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 937*cbe63bfdSIskren Chernev F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0), 938*cbe63bfdSIskren Chernev F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 939*cbe63bfdSIskren Chernev F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 940*cbe63bfdSIskren Chernev F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 941*cbe63bfdSIskren Chernev F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0), 942*cbe63bfdSIskren Chernev { } 943*cbe63bfdSIskren Chernev }; 944*cbe63bfdSIskren Chernev 945*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = { 946*cbe63bfdSIskren Chernev .cmd_rcgr = 0x52094, 947*cbe63bfdSIskren Chernev .mnd_width = 0, 948*cbe63bfdSIskren Chernev .hid_width = 5, 949*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_6, 950*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 951*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 952*cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_0_csid_clk_src", 953*cbe63bfdSIskren Chernev .parent_data = gcc_parents_6, 954*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_6), 955*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 956*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 957*cbe63bfdSIskren Chernev }, 958*cbe63bfdSIskren Chernev }; 959*cbe63bfdSIskren Chernev 960*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_1_clk_src = { 961*cbe63bfdSIskren Chernev .cmd_rcgr = 0x52024, 962*cbe63bfdSIskren Chernev .mnd_width = 8, 963*cbe63bfdSIskren Chernev .hid_width = 5, 964*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_5, 965*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 966*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 967*cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_1_clk_src", 968*cbe63bfdSIskren Chernev .parent_data = gcc_parents_5, 969*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_5), 970*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 971*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 972*cbe63bfdSIskren Chernev }, 973*cbe63bfdSIskren Chernev }; 974*cbe63bfdSIskren Chernev 975*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = { 976*cbe63bfdSIskren Chernev .cmd_rcgr = 0x520b4, 977*cbe63bfdSIskren Chernev .mnd_width = 0, 978*cbe63bfdSIskren Chernev .hid_width = 5, 979*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_6, 980*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 981*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 982*cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_1_csid_clk_src", 983*cbe63bfdSIskren Chernev .parent_data = gcc_parents_6, 984*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_6), 985*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 986*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 987*cbe63bfdSIskren Chernev }, 988*cbe63bfdSIskren Chernev }; 989*cbe63bfdSIskren Chernev 990*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_2_clk_src = { 991*cbe63bfdSIskren Chernev .cmd_rcgr = 0x52044, 992*cbe63bfdSIskren Chernev .mnd_width = 8, 993*cbe63bfdSIskren Chernev .hid_width = 5, 994*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_5, 995*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 996*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 997*cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_2_clk_src", 998*cbe63bfdSIskren Chernev .parent_data = gcc_parents_5, 999*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_5), 1000*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1001*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1002*cbe63bfdSIskren Chernev }, 1003*cbe63bfdSIskren Chernev }; 1004*cbe63bfdSIskren Chernev 1005*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_2_csid_clk_src = { 1006*cbe63bfdSIskren Chernev .cmd_rcgr = 0x520d4, 1007*cbe63bfdSIskren Chernev .mnd_width = 0, 1008*cbe63bfdSIskren Chernev .hid_width = 5, 1009*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_6, 1010*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 1011*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1012*cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_2_csid_clk_src", 1013*cbe63bfdSIskren Chernev .parent_data = gcc_parents_6, 1014*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_6), 1015*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1016*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1017*cbe63bfdSIskren Chernev }, 1018*cbe63bfdSIskren Chernev }; 1019*cbe63bfdSIskren Chernev 1020*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = { 1021*cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1022*cbe63bfdSIskren Chernev F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1023*cbe63bfdSIskren Chernev F(341333333, P_GPLL6_OUT_EARLY, 1, 4, 9), 1024*cbe63bfdSIskren Chernev F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0), 1025*cbe63bfdSIskren Chernev { } 1026*cbe63bfdSIskren Chernev }; 1027*cbe63bfdSIskren Chernev 1028*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = { 1029*cbe63bfdSIskren Chernev .cmd_rcgr = 0x52064, 1030*cbe63bfdSIskren Chernev .mnd_width = 16, 1031*cbe63bfdSIskren Chernev .hid_width = 5, 1032*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_10, 1033*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src, 1034*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1035*cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_cphy_rx_clk_src", 1036*cbe63bfdSIskren Chernev .parent_data = gcc_parents_10, 1037*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_10), 1038*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 1039*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1040*cbe63bfdSIskren Chernev }, 1041*cbe63bfdSIskren Chernev }; 1042*cbe63bfdSIskren Chernev 1043*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = { 1044*cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1045*cbe63bfdSIskren Chernev F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0), 1046*cbe63bfdSIskren Chernev F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0), 1047*cbe63bfdSIskren Chernev { } 1048*cbe63bfdSIskren Chernev }; 1049*cbe63bfdSIskren Chernev 1050*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_top_ahb_clk_src = { 1051*cbe63bfdSIskren Chernev .cmd_rcgr = 0x58010, 1052*cbe63bfdSIskren Chernev .mnd_width = 0, 1053*cbe63bfdSIskren Chernev .hid_width = 5, 1054*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_7, 1055*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_top_ahb_clk_src, 1056*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1057*cbe63bfdSIskren Chernev .name = "gcc_camss_top_ahb_clk_src", 1058*cbe63bfdSIskren Chernev .parent_data = gcc_parents_7, 1059*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_7), 1060*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 1061*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1062*cbe63bfdSIskren Chernev }, 1063*cbe63bfdSIskren Chernev }; 1064*cbe63bfdSIskren Chernev 1065*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 1066*cbe63bfdSIskren Chernev F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1067*cbe63bfdSIskren Chernev F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1068*cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1069*cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 1070*cbe63bfdSIskren Chernev { } 1071*cbe63bfdSIskren Chernev }; 1072*cbe63bfdSIskren Chernev 1073*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_gp1_clk_src = { 1074*cbe63bfdSIskren Chernev .cmd_rcgr = 0x4d004, 1075*cbe63bfdSIskren Chernev .mnd_width = 8, 1076*cbe63bfdSIskren Chernev .hid_width = 5, 1077*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_2, 1078*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_gp1_clk_src, 1079*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1080*cbe63bfdSIskren Chernev .name = "gcc_gp1_clk_src", 1081*cbe63bfdSIskren Chernev .parent_data = gcc_parents_2, 1082*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_2), 1083*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1084*cbe63bfdSIskren Chernev }, 1085*cbe63bfdSIskren Chernev }; 1086*cbe63bfdSIskren Chernev 1087*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_gp2_clk_src = { 1088*cbe63bfdSIskren Chernev .cmd_rcgr = 0x4e004, 1089*cbe63bfdSIskren Chernev .mnd_width = 8, 1090*cbe63bfdSIskren Chernev .hid_width = 5, 1091*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_2, 1092*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_gp1_clk_src, 1093*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1094*cbe63bfdSIskren Chernev .name = "gcc_gp2_clk_src", 1095*cbe63bfdSIskren Chernev .parent_data = gcc_parents_2, 1096*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_2), 1097*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1098*cbe63bfdSIskren Chernev }, 1099*cbe63bfdSIskren Chernev }; 1100*cbe63bfdSIskren Chernev 1101*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_gp3_clk_src = { 1102*cbe63bfdSIskren Chernev .cmd_rcgr = 0x4f004, 1103*cbe63bfdSIskren Chernev .mnd_width = 8, 1104*cbe63bfdSIskren Chernev .hid_width = 5, 1105*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_2, 1106*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_gp1_clk_src, 1107*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1108*cbe63bfdSIskren Chernev .name = "gcc_gp3_clk_src", 1109*cbe63bfdSIskren Chernev .parent_data = gcc_parents_2, 1110*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_2), 1111*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1112*cbe63bfdSIskren Chernev }, 1113*cbe63bfdSIskren Chernev }; 1114*cbe63bfdSIskren Chernev 1115*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 1116*cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1117*cbe63bfdSIskren Chernev F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0), 1118*cbe63bfdSIskren Chernev { } 1119*cbe63bfdSIskren Chernev }; 1120*cbe63bfdSIskren Chernev 1121*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_pdm2_clk_src = { 1122*cbe63bfdSIskren Chernev .cmd_rcgr = 0x20010, 1123*cbe63bfdSIskren Chernev .mnd_width = 0, 1124*cbe63bfdSIskren Chernev .hid_width = 5, 1125*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1126*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_pdm2_clk_src, 1127*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1128*cbe63bfdSIskren Chernev .name = "gcc_pdm2_clk_src", 1129*cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1130*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1131*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1132*cbe63bfdSIskren Chernev }, 1133*cbe63bfdSIskren Chernev }; 1134*cbe63bfdSIskren Chernev 1135*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 1136*cbe63bfdSIskren Chernev F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625), 1137*cbe63bfdSIskren Chernev F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625), 1138*cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1139*cbe63bfdSIskren Chernev F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625), 1140*cbe63bfdSIskren Chernev F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75), 1141*cbe63bfdSIskren Chernev F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25), 1142*cbe63bfdSIskren Chernev F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75), 1143*cbe63bfdSIskren Chernev F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1144*cbe63bfdSIskren Chernev F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15), 1145*cbe63bfdSIskren Chernev F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25), 1146*cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1147*cbe63bfdSIskren Chernev F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375), 1148*cbe63bfdSIskren Chernev F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75), 1149*cbe63bfdSIskren Chernev F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625), 1150*cbe63bfdSIskren Chernev F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0), 1151*cbe63bfdSIskren Chernev F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0), 1152*cbe63bfdSIskren Chernev { } 1153*cbe63bfdSIskren Chernev }; 1154*cbe63bfdSIskren Chernev 1155*cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 1156*cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s0_clk_src", 1157*cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1158*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1159*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1160*cbe63bfdSIskren Chernev }; 1161*cbe63bfdSIskren Chernev 1162*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 1163*cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f148, 1164*cbe63bfdSIskren Chernev .mnd_width = 16, 1165*cbe63bfdSIskren Chernev .hid_width = 5, 1166*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1167*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1168*cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 1169*cbe63bfdSIskren Chernev }; 1170*cbe63bfdSIskren Chernev 1171*cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 1172*cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s1_clk_src", 1173*cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1174*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1175*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1176*cbe63bfdSIskren Chernev }; 1177*cbe63bfdSIskren Chernev 1178*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 1179*cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f278, 1180*cbe63bfdSIskren Chernev .mnd_width = 16, 1181*cbe63bfdSIskren Chernev .hid_width = 5, 1182*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1183*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1184*cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 1185*cbe63bfdSIskren Chernev }; 1186*cbe63bfdSIskren Chernev 1187*cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 1188*cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s2_clk_src", 1189*cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1190*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1191*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1192*cbe63bfdSIskren Chernev }; 1193*cbe63bfdSIskren Chernev 1194*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 1195*cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f3a8, 1196*cbe63bfdSIskren Chernev .mnd_width = 16, 1197*cbe63bfdSIskren Chernev .hid_width = 5, 1198*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1199*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1200*cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 1201*cbe63bfdSIskren Chernev }; 1202*cbe63bfdSIskren Chernev 1203*cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 1204*cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s3_clk_src", 1205*cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1206*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1207*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1208*cbe63bfdSIskren Chernev }; 1209*cbe63bfdSIskren Chernev 1210*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 1211*cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f4d8, 1212*cbe63bfdSIskren Chernev .mnd_width = 16, 1213*cbe63bfdSIskren Chernev .hid_width = 5, 1214*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1215*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1216*cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 1217*cbe63bfdSIskren Chernev }; 1218*cbe63bfdSIskren Chernev 1219*cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 1220*cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s4_clk_src", 1221*cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1222*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1223*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1224*cbe63bfdSIskren Chernev }; 1225*cbe63bfdSIskren Chernev 1226*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 1227*cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f608, 1228*cbe63bfdSIskren Chernev .mnd_width = 16, 1229*cbe63bfdSIskren Chernev .hid_width = 5, 1230*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1231*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1232*cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 1233*cbe63bfdSIskren Chernev }; 1234*cbe63bfdSIskren Chernev 1235*cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 1236*cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s5_clk_src", 1237*cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1238*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1239*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1240*cbe63bfdSIskren Chernev }; 1241*cbe63bfdSIskren Chernev 1242*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 1243*cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f738, 1244*cbe63bfdSIskren Chernev .mnd_width = 16, 1245*cbe63bfdSIskren Chernev .hid_width = 5, 1246*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1247*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1248*cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 1249*cbe63bfdSIskren Chernev }; 1250*cbe63bfdSIskren Chernev 1251*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 1252*cbe63bfdSIskren Chernev F(144000, P_BI_TCXO, 16, 3, 25), 1253*cbe63bfdSIskren Chernev F(400000, P_BI_TCXO, 12, 1, 4), 1254*cbe63bfdSIskren Chernev F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3), 1255*cbe63bfdSIskren Chernev F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2), 1256*cbe63bfdSIskren Chernev F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1257*cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1258*cbe63bfdSIskren Chernev F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 1259*cbe63bfdSIskren Chernev F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 1260*cbe63bfdSIskren Chernev { } 1261*cbe63bfdSIskren Chernev }; 1262*cbe63bfdSIskren Chernev 1263*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 1264*cbe63bfdSIskren Chernev .cmd_rcgr = 0x38028, 1265*cbe63bfdSIskren Chernev .mnd_width = 8, 1266*cbe63bfdSIskren Chernev .hid_width = 5, 1267*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1268*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 1269*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1270*cbe63bfdSIskren Chernev .name = "gcc_sdcc1_apps_clk_src", 1271*cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1272*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1273*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1274*cbe63bfdSIskren Chernev }, 1275*cbe63bfdSIskren Chernev }; 1276*cbe63bfdSIskren Chernev 1277*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 1278*cbe63bfdSIskren Chernev F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1279*cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1280*cbe63bfdSIskren Chernev F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1281*cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1282*cbe63bfdSIskren Chernev F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 1283*cbe63bfdSIskren Chernev { } 1284*cbe63bfdSIskren Chernev }; 1285*cbe63bfdSIskren Chernev 1286*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 1287*cbe63bfdSIskren Chernev .cmd_rcgr = 0x38010, 1288*cbe63bfdSIskren Chernev .mnd_width = 0, 1289*cbe63bfdSIskren Chernev .hid_width = 5, 1290*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1291*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 1292*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1293*cbe63bfdSIskren Chernev .name = "gcc_sdcc1_ice_core_clk_src", 1294*cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1295*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1296*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1297*cbe63bfdSIskren Chernev }, 1298*cbe63bfdSIskren Chernev }; 1299*cbe63bfdSIskren Chernev 1300*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1301*cbe63bfdSIskren Chernev F(400000, P_BI_TCXO, 12, 1, 4), 1302*cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1303*cbe63bfdSIskren Chernev F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1304*cbe63bfdSIskren Chernev F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1305*cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1306*cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1307*cbe63bfdSIskren Chernev { } 1308*cbe63bfdSIskren Chernev }; 1309*cbe63bfdSIskren Chernev 1310*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1311*cbe63bfdSIskren Chernev .cmd_rcgr = 0x1e00c, 1312*cbe63bfdSIskren Chernev .mnd_width = 8, 1313*cbe63bfdSIskren Chernev .hid_width = 5, 1314*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_11, 1315*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1316*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1317*cbe63bfdSIskren Chernev .name = "gcc_sdcc2_apps_clk_src", 1318*cbe63bfdSIskren Chernev .parent_data = gcc_parents_11, 1319*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_11), 1320*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1321*cbe63bfdSIskren Chernev .flags = CLK_OPS_PARENT_ENABLE, 1322*cbe63bfdSIskren Chernev }, 1323*cbe63bfdSIskren Chernev }; 1324*cbe63bfdSIskren Chernev 1325*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1326*cbe63bfdSIskren Chernev F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1327*cbe63bfdSIskren Chernev F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1328*cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1329*cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1330*cbe63bfdSIskren Chernev F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1331*cbe63bfdSIskren Chernev { } 1332*cbe63bfdSIskren Chernev }; 1333*cbe63bfdSIskren Chernev 1334*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1335*cbe63bfdSIskren Chernev .cmd_rcgr = 0x45020, 1336*cbe63bfdSIskren Chernev .mnd_width = 8, 1337*cbe63bfdSIskren Chernev .hid_width = 5, 1338*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1339*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1340*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1341*cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_axi_clk_src", 1342*cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1343*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1344*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1345*cbe63bfdSIskren Chernev }, 1346*cbe63bfdSIskren Chernev }; 1347*cbe63bfdSIskren Chernev 1348*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1349*cbe63bfdSIskren Chernev F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 1350*cbe63bfdSIskren Chernev F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1351*cbe63bfdSIskren Chernev F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1352*cbe63bfdSIskren Chernev F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 1353*cbe63bfdSIskren Chernev { } 1354*cbe63bfdSIskren Chernev }; 1355*cbe63bfdSIskren Chernev 1356*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1357*cbe63bfdSIskren Chernev .cmd_rcgr = 0x45048, 1358*cbe63bfdSIskren Chernev .mnd_width = 0, 1359*cbe63bfdSIskren Chernev .hid_width = 5, 1360*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1361*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1362*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1363*cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_ice_core_clk_src", 1364*cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1365*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1366*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1367*cbe63bfdSIskren Chernev }, 1368*cbe63bfdSIskren Chernev }; 1369*cbe63bfdSIskren Chernev 1370*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1371*cbe63bfdSIskren Chernev F(9600000, P_BI_TCXO, 2, 0, 0), 1372*cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1373*cbe63bfdSIskren Chernev { } 1374*cbe63bfdSIskren Chernev }; 1375*cbe63bfdSIskren Chernev 1376*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1377*cbe63bfdSIskren Chernev .cmd_rcgr = 0x4507c, 1378*cbe63bfdSIskren Chernev .mnd_width = 0, 1379*cbe63bfdSIskren Chernev .hid_width = 5, 1380*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1381*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1382*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1383*cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_phy_aux_clk_src", 1384*cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1385*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1386*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1387*cbe63bfdSIskren Chernev }, 1388*cbe63bfdSIskren Chernev }; 1389*cbe63bfdSIskren Chernev 1390*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 1391*cbe63bfdSIskren Chernev F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 1392*cbe63bfdSIskren Chernev F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1393*cbe63bfdSIskren Chernev F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1394*cbe63bfdSIskren Chernev { } 1395*cbe63bfdSIskren Chernev }; 1396*cbe63bfdSIskren Chernev 1397*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1398*cbe63bfdSIskren Chernev .cmd_rcgr = 0x45060, 1399*cbe63bfdSIskren Chernev .mnd_width = 0, 1400*cbe63bfdSIskren Chernev .hid_width = 5, 1401*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1402*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 1403*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1404*cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_unipro_core_clk_src", 1405*cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1406*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1407*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1408*cbe63bfdSIskren Chernev }, 1409*cbe63bfdSIskren Chernev }; 1410*cbe63bfdSIskren Chernev 1411*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1412*cbe63bfdSIskren Chernev F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0), 1413*cbe63bfdSIskren Chernev F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0), 1414*cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1415*cbe63bfdSIskren Chernev F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1416*cbe63bfdSIskren Chernev { } 1417*cbe63bfdSIskren Chernev }; 1418*cbe63bfdSIskren Chernev 1419*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1420*cbe63bfdSIskren Chernev .cmd_rcgr = 0x1a01c, 1421*cbe63bfdSIskren Chernev .mnd_width = 8, 1422*cbe63bfdSIskren Chernev .hid_width = 5, 1423*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1424*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1425*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1426*cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_master_clk_src", 1427*cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1428*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1429*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1430*cbe63bfdSIskren Chernev }, 1431*cbe63bfdSIskren Chernev }; 1432*cbe63bfdSIskren Chernev 1433*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 1434*cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1435*cbe63bfdSIskren Chernev { } 1436*cbe63bfdSIskren Chernev }; 1437*cbe63bfdSIskren Chernev 1438*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1439*cbe63bfdSIskren Chernev .cmd_rcgr = 0x1a034, 1440*cbe63bfdSIskren Chernev .mnd_width = 0, 1441*cbe63bfdSIskren Chernev .hid_width = 5, 1442*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1443*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1444*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1445*cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_mock_utmi_clk_src", 1446*cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1447*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1448*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1449*cbe63bfdSIskren Chernev }, 1450*cbe63bfdSIskren Chernev }; 1451*cbe63bfdSIskren Chernev 1452*cbe63bfdSIskren Chernev static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1453*cbe63bfdSIskren Chernev .reg = 0x1a04c, 1454*cbe63bfdSIskren Chernev .shift = 0, 1455*cbe63bfdSIskren Chernev .width = 2, 1456*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data) { 1457*cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1458*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]) { 1459*cbe63bfdSIskren Chernev &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw }, 1460*cbe63bfdSIskren Chernev .num_parents = 1, 1461*cbe63bfdSIskren Chernev .ops = &clk_regmap_div_ro_ops, 1462*cbe63bfdSIskren Chernev }, 1463*cbe63bfdSIskren Chernev }; 1464*cbe63bfdSIskren Chernev 1465*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1466*cbe63bfdSIskren Chernev .cmd_rcgr = 0x1a060, 1467*cbe63bfdSIskren Chernev .mnd_width = 0, 1468*cbe63bfdSIskren Chernev .hid_width = 5, 1469*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_12, 1470*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1471*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1472*cbe63bfdSIskren Chernev .name = "gcc_usb3_prim_phy_aux_clk_src", 1473*cbe63bfdSIskren Chernev .parent_data = gcc_parents_12, 1474*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_12), 1475*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1476*cbe63bfdSIskren Chernev }, 1477*cbe63bfdSIskren Chernev }; 1478*cbe63bfdSIskren Chernev 1479*cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = { 1480*cbe63bfdSIskren Chernev F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0), 1481*cbe63bfdSIskren Chernev F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0), 1482*cbe63bfdSIskren Chernev F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0), 1483*cbe63bfdSIskren Chernev F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0), 1484*cbe63bfdSIskren Chernev { } 1485*cbe63bfdSIskren Chernev }; 1486*cbe63bfdSIskren Chernev 1487*cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_video_venus_clk_src = { 1488*cbe63bfdSIskren Chernev .cmd_rcgr = 0x58060, 1489*cbe63bfdSIskren Chernev .mnd_width = 0, 1490*cbe63bfdSIskren Chernev .hid_width = 5, 1491*cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_13, 1492*cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_video_venus_clk_src, 1493*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1494*cbe63bfdSIskren Chernev .name = "gcc_video_venus_clk_src", 1495*cbe63bfdSIskren Chernev .parent_data = gcc_parents_13, 1496*cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_13), 1497*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1498*cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1499*cbe63bfdSIskren Chernev }, 1500*cbe63bfdSIskren Chernev }; 1501*cbe63bfdSIskren Chernev 1502*cbe63bfdSIskren Chernev static struct clk_branch gcc_ahb2phy_csi_clk = { 1503*cbe63bfdSIskren Chernev .halt_reg = 0x1d004, 1504*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1505*cbe63bfdSIskren Chernev .hwcg_reg = 0x1d004, 1506*cbe63bfdSIskren Chernev .hwcg_bit = 1, 1507*cbe63bfdSIskren Chernev .clkr = { 1508*cbe63bfdSIskren Chernev .enable_reg = 0x1d004, 1509*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1510*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1511*cbe63bfdSIskren Chernev .name = "gcc_ahb2phy_csi_clk", 1512*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1513*cbe63bfdSIskren Chernev }, 1514*cbe63bfdSIskren Chernev }, 1515*cbe63bfdSIskren Chernev }; 1516*cbe63bfdSIskren Chernev 1517*cbe63bfdSIskren Chernev static struct clk_branch gcc_ahb2phy_usb_clk = { 1518*cbe63bfdSIskren Chernev .halt_reg = 0x1d008, 1519*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1520*cbe63bfdSIskren Chernev .hwcg_reg = 0x1d008, 1521*cbe63bfdSIskren Chernev .hwcg_bit = 1, 1522*cbe63bfdSIskren Chernev .clkr = { 1523*cbe63bfdSIskren Chernev .enable_reg = 0x1d008, 1524*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1525*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1526*cbe63bfdSIskren Chernev .name = "gcc_ahb2phy_usb_clk", 1527*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1528*cbe63bfdSIskren Chernev }, 1529*cbe63bfdSIskren Chernev }, 1530*cbe63bfdSIskren Chernev }; 1531*cbe63bfdSIskren Chernev 1532*cbe63bfdSIskren Chernev static struct clk_branch gcc_bimc_gpu_axi_clk = { 1533*cbe63bfdSIskren Chernev .halt_reg = 0x71154, 1534*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 1535*cbe63bfdSIskren Chernev .hwcg_reg = 0x71154, 1536*cbe63bfdSIskren Chernev .hwcg_bit = 1, 1537*cbe63bfdSIskren Chernev .clkr = { 1538*cbe63bfdSIskren Chernev .enable_reg = 0x71154, 1539*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1540*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1541*cbe63bfdSIskren Chernev .name = "gcc_bimc_gpu_axi_clk", 1542*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1543*cbe63bfdSIskren Chernev }, 1544*cbe63bfdSIskren Chernev }, 1545*cbe63bfdSIskren Chernev }; 1546*cbe63bfdSIskren Chernev 1547*cbe63bfdSIskren Chernev static struct clk_branch gcc_boot_rom_ahb_clk = { 1548*cbe63bfdSIskren Chernev .halt_reg = 0x23004, 1549*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 1550*cbe63bfdSIskren Chernev .hwcg_reg = 0x23004, 1551*cbe63bfdSIskren Chernev .hwcg_bit = 1, 1552*cbe63bfdSIskren Chernev .clkr = { 1553*cbe63bfdSIskren Chernev .enable_reg = 0x79004, 1554*cbe63bfdSIskren Chernev .enable_mask = BIT(10), 1555*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1556*cbe63bfdSIskren Chernev .name = "gcc_boot_rom_ahb_clk", 1557*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1558*cbe63bfdSIskren Chernev }, 1559*cbe63bfdSIskren Chernev }, 1560*cbe63bfdSIskren Chernev }; 1561*cbe63bfdSIskren Chernev 1562*cbe63bfdSIskren Chernev static struct clk_branch gcc_cam_throttle_nrt_clk = { 1563*cbe63bfdSIskren Chernev .halt_reg = 0x17070, 1564*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 1565*cbe63bfdSIskren Chernev .hwcg_reg = 0x17070, 1566*cbe63bfdSIskren Chernev .hwcg_bit = 1, 1567*cbe63bfdSIskren Chernev .clkr = { 1568*cbe63bfdSIskren Chernev .enable_reg = 0x79004, 1569*cbe63bfdSIskren Chernev .enable_mask = BIT(27), 1570*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1571*cbe63bfdSIskren Chernev .name = "gcc_cam_throttle_nrt_clk", 1572*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1573*cbe63bfdSIskren Chernev }, 1574*cbe63bfdSIskren Chernev }, 1575*cbe63bfdSIskren Chernev }; 1576*cbe63bfdSIskren Chernev 1577*cbe63bfdSIskren Chernev static struct clk_branch gcc_cam_throttle_rt_clk = { 1578*cbe63bfdSIskren Chernev .halt_reg = 0x1706c, 1579*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 1580*cbe63bfdSIskren Chernev .hwcg_reg = 0x1706c, 1581*cbe63bfdSIskren Chernev .hwcg_bit = 1, 1582*cbe63bfdSIskren Chernev .clkr = { 1583*cbe63bfdSIskren Chernev .enable_reg = 0x79004, 1584*cbe63bfdSIskren Chernev .enable_mask = BIT(26), 1585*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1586*cbe63bfdSIskren Chernev .name = "gcc_cam_throttle_rt_clk", 1587*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1588*cbe63bfdSIskren Chernev }, 1589*cbe63bfdSIskren Chernev }, 1590*cbe63bfdSIskren Chernev }; 1591*cbe63bfdSIskren Chernev 1592*cbe63bfdSIskren Chernev static struct clk_branch gcc_camera_ahb_clk = { 1593*cbe63bfdSIskren Chernev .halt_reg = 0x17008, 1594*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 1595*cbe63bfdSIskren Chernev .hwcg_reg = 0x17008, 1596*cbe63bfdSIskren Chernev .hwcg_bit = 1, 1597*cbe63bfdSIskren Chernev .clkr = { 1598*cbe63bfdSIskren Chernev .enable_reg = 0x17008, 1599*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1600*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1601*cbe63bfdSIskren Chernev .name = "gcc_camera_ahb_clk", 1602*cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 1603*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1604*cbe63bfdSIskren Chernev }, 1605*cbe63bfdSIskren Chernev }, 1606*cbe63bfdSIskren Chernev }; 1607*cbe63bfdSIskren Chernev 1608*cbe63bfdSIskren Chernev static struct clk_branch gcc_camera_xo_clk = { 1609*cbe63bfdSIskren Chernev .halt_reg = 0x17028, 1610*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1611*cbe63bfdSIskren Chernev .clkr = { 1612*cbe63bfdSIskren Chernev .enable_reg = 0x17028, 1613*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1614*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1615*cbe63bfdSIskren Chernev .name = "gcc_camera_xo_clk", 1616*cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 1617*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1618*cbe63bfdSIskren Chernev }, 1619*cbe63bfdSIskren Chernev }, 1620*cbe63bfdSIskren Chernev }; 1621*cbe63bfdSIskren Chernev 1622*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_axi_clk = { 1623*cbe63bfdSIskren Chernev .halt_reg = 0x58044, 1624*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1625*cbe63bfdSIskren Chernev .clkr = { 1626*cbe63bfdSIskren Chernev .enable_reg = 0x58044, 1627*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1628*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1629*cbe63bfdSIskren Chernev .name = "gcc_camss_axi_clk", 1630*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1631*cbe63bfdSIskren Chernev &gcc_camss_axi_clk_src.clkr.hw, 1632*cbe63bfdSIskren Chernev }, 1633*cbe63bfdSIskren Chernev .num_parents = 1, 1634*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1635*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1636*cbe63bfdSIskren Chernev }, 1637*cbe63bfdSIskren Chernev }, 1638*cbe63bfdSIskren Chernev }; 1639*cbe63bfdSIskren Chernev 1640*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_camnoc_atb_clk = { 1641*cbe63bfdSIskren Chernev .halt_reg = 0x5804c, 1642*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 1643*cbe63bfdSIskren Chernev .hwcg_reg = 0x5804c, 1644*cbe63bfdSIskren Chernev .hwcg_bit = 1, 1645*cbe63bfdSIskren Chernev .clkr = { 1646*cbe63bfdSIskren Chernev .enable_reg = 0x5804c, 1647*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1648*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1649*cbe63bfdSIskren Chernev .name = "gcc_camss_camnoc_atb_clk", 1650*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1651*cbe63bfdSIskren Chernev }, 1652*cbe63bfdSIskren Chernev }, 1653*cbe63bfdSIskren Chernev }; 1654*cbe63bfdSIskren Chernev 1655*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_camnoc_nts_xo_clk = { 1656*cbe63bfdSIskren Chernev .halt_reg = 0x58050, 1657*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 1658*cbe63bfdSIskren Chernev .hwcg_reg = 0x58050, 1659*cbe63bfdSIskren Chernev .hwcg_bit = 1, 1660*cbe63bfdSIskren Chernev .clkr = { 1661*cbe63bfdSIskren Chernev .enable_reg = 0x58050, 1662*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1663*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1664*cbe63bfdSIskren Chernev .name = "gcc_camss_camnoc_nts_xo_clk", 1665*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1666*cbe63bfdSIskren Chernev }, 1667*cbe63bfdSIskren Chernev }, 1668*cbe63bfdSIskren Chernev }; 1669*cbe63bfdSIskren Chernev 1670*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_cci_0_clk = { 1671*cbe63bfdSIskren Chernev .halt_reg = 0x56018, 1672*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1673*cbe63bfdSIskren Chernev .clkr = { 1674*cbe63bfdSIskren Chernev .enable_reg = 0x56018, 1675*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1676*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1677*cbe63bfdSIskren Chernev .name = "gcc_camss_cci_0_clk", 1678*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1679*cbe63bfdSIskren Chernev &gcc_camss_cci_clk_src.clkr.hw, 1680*cbe63bfdSIskren Chernev }, 1681*cbe63bfdSIskren Chernev .num_parents = 1, 1682*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1683*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1684*cbe63bfdSIskren Chernev }, 1685*cbe63bfdSIskren Chernev }, 1686*cbe63bfdSIskren Chernev }; 1687*cbe63bfdSIskren Chernev 1688*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_cphy_0_clk = { 1689*cbe63bfdSIskren Chernev .halt_reg = 0x52088, 1690*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1691*cbe63bfdSIskren Chernev .clkr = { 1692*cbe63bfdSIskren Chernev .enable_reg = 0x52088, 1693*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1694*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1695*cbe63bfdSIskren Chernev .name = "gcc_camss_cphy_0_clk", 1696*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1697*cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1698*cbe63bfdSIskren Chernev }, 1699*cbe63bfdSIskren Chernev .num_parents = 1, 1700*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1701*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1702*cbe63bfdSIskren Chernev }, 1703*cbe63bfdSIskren Chernev }, 1704*cbe63bfdSIskren Chernev }; 1705*cbe63bfdSIskren Chernev 1706*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_cphy_1_clk = { 1707*cbe63bfdSIskren Chernev .halt_reg = 0x5208c, 1708*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1709*cbe63bfdSIskren Chernev .clkr = { 1710*cbe63bfdSIskren Chernev .enable_reg = 0x5208c, 1711*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1712*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1713*cbe63bfdSIskren Chernev .name = "gcc_camss_cphy_1_clk", 1714*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1715*cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1716*cbe63bfdSIskren Chernev }, 1717*cbe63bfdSIskren Chernev .num_parents = 1, 1718*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1719*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1720*cbe63bfdSIskren Chernev }, 1721*cbe63bfdSIskren Chernev }, 1722*cbe63bfdSIskren Chernev }; 1723*cbe63bfdSIskren Chernev 1724*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_cphy_2_clk = { 1725*cbe63bfdSIskren Chernev .halt_reg = 0x52090, 1726*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1727*cbe63bfdSIskren Chernev .clkr = { 1728*cbe63bfdSIskren Chernev .enable_reg = 0x52090, 1729*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1730*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1731*cbe63bfdSIskren Chernev .name = "gcc_camss_cphy_2_clk", 1732*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1733*cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1734*cbe63bfdSIskren Chernev }, 1735*cbe63bfdSIskren Chernev .num_parents = 1, 1736*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1737*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1738*cbe63bfdSIskren Chernev }, 1739*cbe63bfdSIskren Chernev }, 1740*cbe63bfdSIskren Chernev }; 1741*cbe63bfdSIskren Chernev 1742*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_csi0phytimer_clk = { 1743*cbe63bfdSIskren Chernev .halt_reg = 0x59018, 1744*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1745*cbe63bfdSIskren Chernev .clkr = { 1746*cbe63bfdSIskren Chernev .enable_reg = 0x59018, 1747*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1748*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1749*cbe63bfdSIskren Chernev .name = "gcc_camss_csi0phytimer_clk", 1750*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1751*cbe63bfdSIskren Chernev &gcc_camss_csi0phytimer_clk_src.clkr.hw, 1752*cbe63bfdSIskren Chernev }, 1753*cbe63bfdSIskren Chernev .num_parents = 1, 1754*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1755*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1756*cbe63bfdSIskren Chernev }, 1757*cbe63bfdSIskren Chernev }, 1758*cbe63bfdSIskren Chernev }; 1759*cbe63bfdSIskren Chernev 1760*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_csi1phytimer_clk = { 1761*cbe63bfdSIskren Chernev .halt_reg = 0x59034, 1762*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1763*cbe63bfdSIskren Chernev .clkr = { 1764*cbe63bfdSIskren Chernev .enable_reg = 0x59034, 1765*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1766*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1767*cbe63bfdSIskren Chernev .name = "gcc_camss_csi1phytimer_clk", 1768*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1769*cbe63bfdSIskren Chernev &gcc_camss_csi1phytimer_clk_src.clkr.hw, 1770*cbe63bfdSIskren Chernev }, 1771*cbe63bfdSIskren Chernev .num_parents = 1, 1772*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1773*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1774*cbe63bfdSIskren Chernev }, 1775*cbe63bfdSIskren Chernev }, 1776*cbe63bfdSIskren Chernev }; 1777*cbe63bfdSIskren Chernev 1778*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_csi2phytimer_clk = { 1779*cbe63bfdSIskren Chernev .halt_reg = 0x59050, 1780*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1781*cbe63bfdSIskren Chernev .clkr = { 1782*cbe63bfdSIskren Chernev .enable_reg = 0x59050, 1783*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1784*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1785*cbe63bfdSIskren Chernev .name = "gcc_camss_csi2phytimer_clk", 1786*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1787*cbe63bfdSIskren Chernev &gcc_camss_csi2phytimer_clk_src.clkr.hw, 1788*cbe63bfdSIskren Chernev }, 1789*cbe63bfdSIskren Chernev .num_parents = 1, 1790*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1791*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1792*cbe63bfdSIskren Chernev }, 1793*cbe63bfdSIskren Chernev }, 1794*cbe63bfdSIskren Chernev }; 1795*cbe63bfdSIskren Chernev 1796*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_mclk0_clk = { 1797*cbe63bfdSIskren Chernev .halt_reg = 0x51018, 1798*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1799*cbe63bfdSIskren Chernev .clkr = { 1800*cbe63bfdSIskren Chernev .enable_reg = 0x51018, 1801*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1802*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1803*cbe63bfdSIskren Chernev .name = "gcc_camss_mclk0_clk", 1804*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1805*cbe63bfdSIskren Chernev &gcc_camss_mclk0_clk_src.clkr.hw, 1806*cbe63bfdSIskren Chernev }, 1807*cbe63bfdSIskren Chernev .num_parents = 1, 1808*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1809*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1810*cbe63bfdSIskren Chernev }, 1811*cbe63bfdSIskren Chernev }, 1812*cbe63bfdSIskren Chernev }; 1813*cbe63bfdSIskren Chernev 1814*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_mclk1_clk = { 1815*cbe63bfdSIskren Chernev .halt_reg = 0x51034, 1816*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1817*cbe63bfdSIskren Chernev .clkr = { 1818*cbe63bfdSIskren Chernev .enable_reg = 0x51034, 1819*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1820*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1821*cbe63bfdSIskren Chernev .name = "gcc_camss_mclk1_clk", 1822*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1823*cbe63bfdSIskren Chernev &gcc_camss_mclk1_clk_src.clkr.hw, 1824*cbe63bfdSIskren Chernev }, 1825*cbe63bfdSIskren Chernev .num_parents = 1, 1826*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1827*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1828*cbe63bfdSIskren Chernev }, 1829*cbe63bfdSIskren Chernev }, 1830*cbe63bfdSIskren Chernev }; 1831*cbe63bfdSIskren Chernev 1832*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_mclk2_clk = { 1833*cbe63bfdSIskren Chernev .halt_reg = 0x51050, 1834*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1835*cbe63bfdSIskren Chernev .clkr = { 1836*cbe63bfdSIskren Chernev .enable_reg = 0x51050, 1837*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1838*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1839*cbe63bfdSIskren Chernev .name = "gcc_camss_mclk2_clk", 1840*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1841*cbe63bfdSIskren Chernev &gcc_camss_mclk2_clk_src.clkr.hw, 1842*cbe63bfdSIskren Chernev }, 1843*cbe63bfdSIskren Chernev .num_parents = 1, 1844*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1845*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1846*cbe63bfdSIskren Chernev }, 1847*cbe63bfdSIskren Chernev }, 1848*cbe63bfdSIskren Chernev }; 1849*cbe63bfdSIskren Chernev 1850*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_mclk3_clk = { 1851*cbe63bfdSIskren Chernev .halt_reg = 0x5106c, 1852*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1853*cbe63bfdSIskren Chernev .clkr = { 1854*cbe63bfdSIskren Chernev .enable_reg = 0x5106c, 1855*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1856*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1857*cbe63bfdSIskren Chernev .name = "gcc_camss_mclk3_clk", 1858*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1859*cbe63bfdSIskren Chernev &gcc_camss_mclk3_clk_src.clkr.hw, 1860*cbe63bfdSIskren Chernev }, 1861*cbe63bfdSIskren Chernev .num_parents = 1, 1862*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1863*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1864*cbe63bfdSIskren Chernev }, 1865*cbe63bfdSIskren Chernev }, 1866*cbe63bfdSIskren Chernev }; 1867*cbe63bfdSIskren Chernev 1868*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_nrt_axi_clk = { 1869*cbe63bfdSIskren Chernev .halt_reg = 0x58054, 1870*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1871*cbe63bfdSIskren Chernev .clkr = { 1872*cbe63bfdSIskren Chernev .enable_reg = 0x58054, 1873*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1874*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1875*cbe63bfdSIskren Chernev .name = "gcc_camss_nrt_axi_clk", 1876*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1877*cbe63bfdSIskren Chernev }, 1878*cbe63bfdSIskren Chernev }, 1879*cbe63bfdSIskren Chernev }; 1880*cbe63bfdSIskren Chernev 1881*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_ope_ahb_clk = { 1882*cbe63bfdSIskren Chernev .halt_reg = 0x5503c, 1883*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1884*cbe63bfdSIskren Chernev .clkr = { 1885*cbe63bfdSIskren Chernev .enable_reg = 0x5503c, 1886*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1887*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1888*cbe63bfdSIskren Chernev .name = "gcc_camss_ope_ahb_clk", 1889*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1890*cbe63bfdSIskren Chernev &gcc_camss_ope_ahb_clk_src.clkr.hw, 1891*cbe63bfdSIskren Chernev }, 1892*cbe63bfdSIskren Chernev .num_parents = 1, 1893*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1894*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1895*cbe63bfdSIskren Chernev }, 1896*cbe63bfdSIskren Chernev }, 1897*cbe63bfdSIskren Chernev }; 1898*cbe63bfdSIskren Chernev 1899*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_ope_clk = { 1900*cbe63bfdSIskren Chernev .halt_reg = 0x5501c, 1901*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1902*cbe63bfdSIskren Chernev .clkr = { 1903*cbe63bfdSIskren Chernev .enable_reg = 0x5501c, 1904*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1905*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1906*cbe63bfdSIskren Chernev .name = "gcc_camss_ope_clk", 1907*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1908*cbe63bfdSIskren Chernev &gcc_camss_ope_clk_src.clkr.hw, 1909*cbe63bfdSIskren Chernev }, 1910*cbe63bfdSIskren Chernev .num_parents = 1, 1911*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1912*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1913*cbe63bfdSIskren Chernev }, 1914*cbe63bfdSIskren Chernev }, 1915*cbe63bfdSIskren Chernev }; 1916*cbe63bfdSIskren Chernev 1917*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_rt_axi_clk = { 1918*cbe63bfdSIskren Chernev .halt_reg = 0x5805c, 1919*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1920*cbe63bfdSIskren Chernev .clkr = { 1921*cbe63bfdSIskren Chernev .enable_reg = 0x5805c, 1922*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1923*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1924*cbe63bfdSIskren Chernev .name = "gcc_camss_rt_axi_clk", 1925*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1926*cbe63bfdSIskren Chernev }, 1927*cbe63bfdSIskren Chernev }, 1928*cbe63bfdSIskren Chernev }; 1929*cbe63bfdSIskren Chernev 1930*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_0_clk = { 1931*cbe63bfdSIskren Chernev .halt_reg = 0x5201c, 1932*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1933*cbe63bfdSIskren Chernev .clkr = { 1934*cbe63bfdSIskren Chernev .enable_reg = 0x5201c, 1935*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1936*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1937*cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_0_clk", 1938*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1939*cbe63bfdSIskren Chernev &gcc_camss_tfe_0_clk_src.clkr.hw, 1940*cbe63bfdSIskren Chernev }, 1941*cbe63bfdSIskren Chernev .num_parents = 1, 1942*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1943*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1944*cbe63bfdSIskren Chernev }, 1945*cbe63bfdSIskren Chernev }, 1946*cbe63bfdSIskren Chernev }; 1947*cbe63bfdSIskren Chernev 1948*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = { 1949*cbe63bfdSIskren Chernev .halt_reg = 0x5207c, 1950*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1951*cbe63bfdSIskren Chernev .clkr = { 1952*cbe63bfdSIskren Chernev .enable_reg = 0x5207c, 1953*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1954*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1955*cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_0_cphy_rx_clk", 1956*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1957*cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1958*cbe63bfdSIskren Chernev }, 1959*cbe63bfdSIskren Chernev .num_parents = 1, 1960*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1961*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1962*cbe63bfdSIskren Chernev }, 1963*cbe63bfdSIskren Chernev }, 1964*cbe63bfdSIskren Chernev }; 1965*cbe63bfdSIskren Chernev 1966*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_0_csid_clk = { 1967*cbe63bfdSIskren Chernev .halt_reg = 0x520ac, 1968*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1969*cbe63bfdSIskren Chernev .clkr = { 1970*cbe63bfdSIskren Chernev .enable_reg = 0x520ac, 1971*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1972*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1973*cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_0_csid_clk", 1974*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1975*cbe63bfdSIskren Chernev &gcc_camss_tfe_0_csid_clk_src.clkr.hw, 1976*cbe63bfdSIskren Chernev }, 1977*cbe63bfdSIskren Chernev .num_parents = 1, 1978*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1979*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1980*cbe63bfdSIskren Chernev }, 1981*cbe63bfdSIskren Chernev }, 1982*cbe63bfdSIskren Chernev }; 1983*cbe63bfdSIskren Chernev 1984*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_1_clk = { 1985*cbe63bfdSIskren Chernev .halt_reg = 0x5203c, 1986*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1987*cbe63bfdSIskren Chernev .clkr = { 1988*cbe63bfdSIskren Chernev .enable_reg = 0x5203c, 1989*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1990*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1991*cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_1_clk", 1992*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1993*cbe63bfdSIskren Chernev &gcc_camss_tfe_1_clk_src.clkr.hw, 1994*cbe63bfdSIskren Chernev }, 1995*cbe63bfdSIskren Chernev .num_parents = 1, 1996*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1997*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1998*cbe63bfdSIskren Chernev }, 1999*cbe63bfdSIskren Chernev }, 2000*cbe63bfdSIskren Chernev }; 2001*cbe63bfdSIskren Chernev 2002*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = { 2003*cbe63bfdSIskren Chernev .halt_reg = 0x52080, 2004*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2005*cbe63bfdSIskren Chernev .clkr = { 2006*cbe63bfdSIskren Chernev .enable_reg = 0x52080, 2007*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2008*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2009*cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_1_cphy_rx_clk", 2010*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2011*cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2012*cbe63bfdSIskren Chernev }, 2013*cbe63bfdSIskren Chernev .num_parents = 1, 2014*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2015*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2016*cbe63bfdSIskren Chernev }, 2017*cbe63bfdSIskren Chernev }, 2018*cbe63bfdSIskren Chernev }; 2019*cbe63bfdSIskren Chernev 2020*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_1_csid_clk = { 2021*cbe63bfdSIskren Chernev .halt_reg = 0x520cc, 2022*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2023*cbe63bfdSIskren Chernev .clkr = { 2024*cbe63bfdSIskren Chernev .enable_reg = 0x520cc, 2025*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2026*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2027*cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_1_csid_clk", 2028*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2029*cbe63bfdSIskren Chernev &gcc_camss_tfe_1_csid_clk_src.clkr.hw, 2030*cbe63bfdSIskren Chernev }, 2031*cbe63bfdSIskren Chernev .num_parents = 1, 2032*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2033*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2034*cbe63bfdSIskren Chernev }, 2035*cbe63bfdSIskren Chernev }, 2036*cbe63bfdSIskren Chernev }; 2037*cbe63bfdSIskren Chernev 2038*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_2_clk = { 2039*cbe63bfdSIskren Chernev .halt_reg = 0x5205c, 2040*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2041*cbe63bfdSIskren Chernev .clkr = { 2042*cbe63bfdSIskren Chernev .enable_reg = 0x5205c, 2043*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2044*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2045*cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_2_clk", 2046*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2047*cbe63bfdSIskren Chernev &gcc_camss_tfe_2_clk_src.clkr.hw, 2048*cbe63bfdSIskren Chernev }, 2049*cbe63bfdSIskren Chernev .num_parents = 1, 2050*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2051*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2052*cbe63bfdSIskren Chernev }, 2053*cbe63bfdSIskren Chernev }, 2054*cbe63bfdSIskren Chernev }; 2055*cbe63bfdSIskren Chernev 2056*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_2_cphy_rx_clk = { 2057*cbe63bfdSIskren Chernev .halt_reg = 0x52084, 2058*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2059*cbe63bfdSIskren Chernev .clkr = { 2060*cbe63bfdSIskren Chernev .enable_reg = 0x52084, 2061*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2062*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2063*cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_2_cphy_rx_clk", 2064*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2065*cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2066*cbe63bfdSIskren Chernev }, 2067*cbe63bfdSIskren Chernev .num_parents = 1, 2068*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2069*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2070*cbe63bfdSIskren Chernev }, 2071*cbe63bfdSIskren Chernev }, 2072*cbe63bfdSIskren Chernev }; 2073*cbe63bfdSIskren Chernev 2074*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_2_csid_clk = { 2075*cbe63bfdSIskren Chernev .halt_reg = 0x520ec, 2076*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2077*cbe63bfdSIskren Chernev .clkr = { 2078*cbe63bfdSIskren Chernev .enable_reg = 0x520ec, 2079*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2080*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2081*cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_2_csid_clk", 2082*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2083*cbe63bfdSIskren Chernev &gcc_camss_tfe_2_csid_clk_src.clkr.hw, 2084*cbe63bfdSIskren Chernev }, 2085*cbe63bfdSIskren Chernev .num_parents = 1, 2086*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2087*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2088*cbe63bfdSIskren Chernev }, 2089*cbe63bfdSIskren Chernev }, 2090*cbe63bfdSIskren Chernev }; 2091*cbe63bfdSIskren Chernev 2092*cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_top_ahb_clk = { 2093*cbe63bfdSIskren Chernev .halt_reg = 0x58028, 2094*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2095*cbe63bfdSIskren Chernev .clkr = { 2096*cbe63bfdSIskren Chernev .enable_reg = 0x58028, 2097*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2098*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2099*cbe63bfdSIskren Chernev .name = "gcc_camss_top_ahb_clk", 2100*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2101*cbe63bfdSIskren Chernev &gcc_camss_top_ahb_clk_src.clkr.hw, 2102*cbe63bfdSIskren Chernev }, 2103*cbe63bfdSIskren Chernev .num_parents = 1, 2104*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2105*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2106*cbe63bfdSIskren Chernev }, 2107*cbe63bfdSIskren Chernev }, 2108*cbe63bfdSIskren Chernev }; 2109*cbe63bfdSIskren Chernev 2110*cbe63bfdSIskren Chernev static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 2111*cbe63bfdSIskren Chernev .halt_reg = 0x1a084, 2112*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2113*cbe63bfdSIskren Chernev .hwcg_reg = 0x1a084, 2114*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2115*cbe63bfdSIskren Chernev .clkr = { 2116*cbe63bfdSIskren Chernev .enable_reg = 0x1a084, 2117*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2118*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2119*cbe63bfdSIskren Chernev .name = "gcc_cfg_noc_usb3_prim_axi_clk", 2120*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2121*cbe63bfdSIskren Chernev &gcc_usb30_prim_master_clk_src.clkr.hw, 2122*cbe63bfdSIskren Chernev }, 2123*cbe63bfdSIskren Chernev .num_parents = 1, 2124*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2125*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2126*cbe63bfdSIskren Chernev }, 2127*cbe63bfdSIskren Chernev }, 2128*cbe63bfdSIskren Chernev }; 2129*cbe63bfdSIskren Chernev 2130*cbe63bfdSIskren Chernev static struct clk_branch gcc_cpuss_gnoc_clk = { 2131*cbe63bfdSIskren Chernev .halt_reg = 0x2b004, 2132*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2133*cbe63bfdSIskren Chernev .hwcg_reg = 0x2b004, 2134*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2135*cbe63bfdSIskren Chernev .clkr = { 2136*cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2137*cbe63bfdSIskren Chernev .enable_mask = BIT(22), 2138*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2139*cbe63bfdSIskren Chernev .name = "gcc_cpuss_gnoc_clk", 2140*cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 2141*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2142*cbe63bfdSIskren Chernev }, 2143*cbe63bfdSIskren Chernev }, 2144*cbe63bfdSIskren Chernev }; 2145*cbe63bfdSIskren Chernev 2146*cbe63bfdSIskren Chernev static struct clk_branch gcc_disp_ahb_clk = { 2147*cbe63bfdSIskren Chernev .halt_reg = 0x1700c, 2148*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2149*cbe63bfdSIskren Chernev .hwcg_reg = 0x1700c, 2150*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2151*cbe63bfdSIskren Chernev .clkr = { 2152*cbe63bfdSIskren Chernev .enable_reg = 0x1700c, 2153*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2154*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2155*cbe63bfdSIskren Chernev .name = "gcc_disp_ahb_clk", 2156*cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 2157*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2158*cbe63bfdSIskren Chernev }, 2159*cbe63bfdSIskren Chernev }, 2160*cbe63bfdSIskren Chernev }; 2161*cbe63bfdSIskren Chernev 2162*cbe63bfdSIskren Chernev static struct clk_regmap_div gcc_disp_gpll0_clk_src = { 2163*cbe63bfdSIskren Chernev .reg = 0x17058, 2164*cbe63bfdSIskren Chernev .shift = 0, 2165*cbe63bfdSIskren Chernev .width = 2, 2166*cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data) { 2167*cbe63bfdSIskren Chernev .name = "gcc_disp_gpll0_clk_src", 2168*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 2169*cbe63bfdSIskren Chernev .num_parents = 1, 2170*cbe63bfdSIskren Chernev .ops = &clk_regmap_div_ops, 2171*cbe63bfdSIskren Chernev }, 2172*cbe63bfdSIskren Chernev }; 2173*cbe63bfdSIskren Chernev 2174*cbe63bfdSIskren Chernev static struct clk_branch gcc_disp_gpll0_div_clk_src = { 2175*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 2176*cbe63bfdSIskren Chernev .clkr = { 2177*cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2178*cbe63bfdSIskren Chernev .enable_mask = BIT(20), 2179*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2180*cbe63bfdSIskren Chernev .name = "gcc_disp_gpll0_div_clk_src", 2181*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2182*cbe63bfdSIskren Chernev &gcc_disp_gpll0_clk_src.clkr.hw, 2183*cbe63bfdSIskren Chernev }, 2184*cbe63bfdSIskren Chernev .num_parents = 1, 2185*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2186*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2187*cbe63bfdSIskren Chernev }, 2188*cbe63bfdSIskren Chernev }, 2189*cbe63bfdSIskren Chernev }; 2190*cbe63bfdSIskren Chernev 2191*cbe63bfdSIskren Chernev static struct clk_branch gcc_disp_hf_axi_clk = { 2192*cbe63bfdSIskren Chernev .halt_reg = 0x17020, 2193*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2194*cbe63bfdSIskren Chernev .hwcg_reg = 0x17020, 2195*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2196*cbe63bfdSIskren Chernev .clkr = { 2197*cbe63bfdSIskren Chernev .enable_reg = 0x17020, 2198*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2199*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2200*cbe63bfdSIskren Chernev .name = "gcc_disp_hf_axi_clk", 2201*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2202*cbe63bfdSIskren Chernev }, 2203*cbe63bfdSIskren Chernev }, 2204*cbe63bfdSIskren Chernev }; 2205*cbe63bfdSIskren Chernev 2206*cbe63bfdSIskren Chernev static struct clk_branch gcc_disp_throttle_core_clk = { 2207*cbe63bfdSIskren Chernev .halt_reg = 0x17064, 2208*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2209*cbe63bfdSIskren Chernev .hwcg_reg = 0x17064, 2210*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2211*cbe63bfdSIskren Chernev .clkr = { 2212*cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2213*cbe63bfdSIskren Chernev .enable_mask = BIT(5), 2214*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2215*cbe63bfdSIskren Chernev .name = "gcc_disp_throttle_core_clk", 2216*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2217*cbe63bfdSIskren Chernev }, 2218*cbe63bfdSIskren Chernev }, 2219*cbe63bfdSIskren Chernev }; 2220*cbe63bfdSIskren Chernev 2221*cbe63bfdSIskren Chernev static struct clk_branch gcc_disp_xo_clk = { 2222*cbe63bfdSIskren Chernev .halt_reg = 0x1702c, 2223*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2224*cbe63bfdSIskren Chernev .clkr = { 2225*cbe63bfdSIskren Chernev .enable_reg = 0x1702c, 2226*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2227*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2228*cbe63bfdSIskren Chernev .name = "gcc_disp_xo_clk", 2229*cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 2230*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2231*cbe63bfdSIskren Chernev }, 2232*cbe63bfdSIskren Chernev }, 2233*cbe63bfdSIskren Chernev }; 2234*cbe63bfdSIskren Chernev 2235*cbe63bfdSIskren Chernev static struct clk_branch gcc_gp1_clk = { 2236*cbe63bfdSIskren Chernev .halt_reg = 0x4d000, 2237*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2238*cbe63bfdSIskren Chernev .clkr = { 2239*cbe63bfdSIskren Chernev .enable_reg = 0x4d000, 2240*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2241*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2242*cbe63bfdSIskren Chernev .name = "gcc_gp1_clk", 2243*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2244*cbe63bfdSIskren Chernev &gcc_gp1_clk_src.clkr.hw, 2245*cbe63bfdSIskren Chernev }, 2246*cbe63bfdSIskren Chernev .num_parents = 1, 2247*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2248*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2249*cbe63bfdSIskren Chernev }, 2250*cbe63bfdSIskren Chernev }, 2251*cbe63bfdSIskren Chernev }; 2252*cbe63bfdSIskren Chernev 2253*cbe63bfdSIskren Chernev static struct clk_branch gcc_gp2_clk = { 2254*cbe63bfdSIskren Chernev .halt_reg = 0x4e000, 2255*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2256*cbe63bfdSIskren Chernev .clkr = { 2257*cbe63bfdSIskren Chernev .enable_reg = 0x4e000, 2258*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2259*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2260*cbe63bfdSIskren Chernev .name = "gcc_gp2_clk", 2261*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2262*cbe63bfdSIskren Chernev &gcc_gp2_clk_src.clkr.hw, 2263*cbe63bfdSIskren Chernev }, 2264*cbe63bfdSIskren Chernev .num_parents = 1, 2265*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2266*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2267*cbe63bfdSIskren Chernev }, 2268*cbe63bfdSIskren Chernev }, 2269*cbe63bfdSIskren Chernev }; 2270*cbe63bfdSIskren Chernev 2271*cbe63bfdSIskren Chernev static struct clk_branch gcc_gp3_clk = { 2272*cbe63bfdSIskren Chernev .halt_reg = 0x4f000, 2273*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2274*cbe63bfdSIskren Chernev .clkr = { 2275*cbe63bfdSIskren Chernev .enable_reg = 0x4f000, 2276*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2277*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2278*cbe63bfdSIskren Chernev .name = "gcc_gp3_clk", 2279*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2280*cbe63bfdSIskren Chernev &gcc_gp3_clk_src.clkr.hw, 2281*cbe63bfdSIskren Chernev }, 2282*cbe63bfdSIskren Chernev .num_parents = 1, 2283*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2284*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2285*cbe63bfdSIskren Chernev }, 2286*cbe63bfdSIskren Chernev }, 2287*cbe63bfdSIskren Chernev }; 2288*cbe63bfdSIskren Chernev 2289*cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_cfg_ahb_clk = { 2290*cbe63bfdSIskren Chernev .halt_reg = 0x36004, 2291*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2292*cbe63bfdSIskren Chernev .hwcg_reg = 0x36004, 2293*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2294*cbe63bfdSIskren Chernev .clkr = { 2295*cbe63bfdSIskren Chernev .enable_reg = 0x36004, 2296*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2297*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2298*cbe63bfdSIskren Chernev .name = "gcc_gpu_cfg_ahb_clk", 2299*cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 2300*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2301*cbe63bfdSIskren Chernev }, 2302*cbe63bfdSIskren Chernev }, 2303*cbe63bfdSIskren Chernev }; 2304*cbe63bfdSIskren Chernev 2305*cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_gpll0_clk_src = { 2306*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 2307*cbe63bfdSIskren Chernev .clkr = { 2308*cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2309*cbe63bfdSIskren Chernev .enable_mask = BIT(15), 2310*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2311*cbe63bfdSIskren Chernev .name = "gcc_gpu_gpll0_clk_src", 2312*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2313*cbe63bfdSIskren Chernev &gpll0.clkr.hw, 2314*cbe63bfdSIskren Chernev }, 2315*cbe63bfdSIskren Chernev .num_parents = 1, 2316*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2317*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2318*cbe63bfdSIskren Chernev }, 2319*cbe63bfdSIskren Chernev }, 2320*cbe63bfdSIskren Chernev }; 2321*cbe63bfdSIskren Chernev 2322*cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 2323*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 2324*cbe63bfdSIskren Chernev .clkr = { 2325*cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2326*cbe63bfdSIskren Chernev .enable_mask = BIT(16), 2327*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2328*cbe63bfdSIskren Chernev .name = "gcc_gpu_gpll0_div_clk_src", 2329*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2330*cbe63bfdSIskren Chernev &gpll0_out_aux2.clkr.hw, 2331*cbe63bfdSIskren Chernev }, 2332*cbe63bfdSIskren Chernev .num_parents = 1, 2333*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2334*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2335*cbe63bfdSIskren Chernev }, 2336*cbe63bfdSIskren Chernev }, 2337*cbe63bfdSIskren Chernev }; 2338*cbe63bfdSIskren Chernev 2339*cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_iref_clk = { 2340*cbe63bfdSIskren Chernev .halt_reg = 0x36100, 2341*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 2342*cbe63bfdSIskren Chernev .clkr = { 2343*cbe63bfdSIskren Chernev .enable_reg = 0x36100, 2344*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2345*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2346*cbe63bfdSIskren Chernev .name = "gcc_gpu_iref_clk", 2347*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2348*cbe63bfdSIskren Chernev }, 2349*cbe63bfdSIskren Chernev }, 2350*cbe63bfdSIskren Chernev }; 2351*cbe63bfdSIskren Chernev 2352*cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 2353*cbe63bfdSIskren Chernev .halt_reg = 0x3600c, 2354*cbe63bfdSIskren Chernev .halt_check = BRANCH_VOTED, 2355*cbe63bfdSIskren Chernev .hwcg_reg = 0x3600c, 2356*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2357*cbe63bfdSIskren Chernev .clkr = { 2358*cbe63bfdSIskren Chernev .enable_reg = 0x3600c, 2359*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2360*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2361*cbe63bfdSIskren Chernev .name = "gcc_gpu_memnoc_gfx_clk", 2362*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2363*cbe63bfdSIskren Chernev }, 2364*cbe63bfdSIskren Chernev }, 2365*cbe63bfdSIskren Chernev }; 2366*cbe63bfdSIskren Chernev 2367*cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2368*cbe63bfdSIskren Chernev .halt_reg = 0x36018, 2369*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2370*cbe63bfdSIskren Chernev .clkr = { 2371*cbe63bfdSIskren Chernev .enable_reg = 0x36018, 2372*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2373*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2374*cbe63bfdSIskren Chernev .name = "gcc_gpu_snoc_dvm_gfx_clk", 2375*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2376*cbe63bfdSIskren Chernev }, 2377*cbe63bfdSIskren Chernev }, 2378*cbe63bfdSIskren Chernev }; 2379*cbe63bfdSIskren Chernev 2380*cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_throttle_core_clk = { 2381*cbe63bfdSIskren Chernev .halt_reg = 0x36048, 2382*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2383*cbe63bfdSIskren Chernev .hwcg_reg = 0x36048, 2384*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2385*cbe63bfdSIskren Chernev .clkr = { 2386*cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2387*cbe63bfdSIskren Chernev .enable_mask = BIT(31), 2388*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2389*cbe63bfdSIskren Chernev .name = "gcc_gpu_throttle_core_clk", 2390*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2391*cbe63bfdSIskren Chernev }, 2392*cbe63bfdSIskren Chernev }, 2393*cbe63bfdSIskren Chernev }; 2394*cbe63bfdSIskren Chernev 2395*cbe63bfdSIskren Chernev static struct clk_branch gcc_pdm2_clk = { 2396*cbe63bfdSIskren Chernev .halt_reg = 0x2000c, 2397*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2398*cbe63bfdSIskren Chernev .clkr = { 2399*cbe63bfdSIskren Chernev .enable_reg = 0x2000c, 2400*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2401*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2402*cbe63bfdSIskren Chernev .name = "gcc_pdm2_clk", 2403*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2404*cbe63bfdSIskren Chernev &gcc_pdm2_clk_src.clkr.hw, 2405*cbe63bfdSIskren Chernev }, 2406*cbe63bfdSIskren Chernev .num_parents = 1, 2407*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2408*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2409*cbe63bfdSIskren Chernev }, 2410*cbe63bfdSIskren Chernev }, 2411*cbe63bfdSIskren Chernev }; 2412*cbe63bfdSIskren Chernev 2413*cbe63bfdSIskren Chernev static struct clk_branch gcc_pdm_ahb_clk = { 2414*cbe63bfdSIskren Chernev .halt_reg = 0x20004, 2415*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2416*cbe63bfdSIskren Chernev .hwcg_reg = 0x20004, 2417*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2418*cbe63bfdSIskren Chernev .clkr = { 2419*cbe63bfdSIskren Chernev .enable_reg = 0x20004, 2420*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2421*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2422*cbe63bfdSIskren Chernev .name = "gcc_pdm_ahb_clk", 2423*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2424*cbe63bfdSIskren Chernev }, 2425*cbe63bfdSIskren Chernev }, 2426*cbe63bfdSIskren Chernev }; 2427*cbe63bfdSIskren Chernev 2428*cbe63bfdSIskren Chernev static struct clk_branch gcc_pdm_xo4_clk = { 2429*cbe63bfdSIskren Chernev .halt_reg = 0x20008, 2430*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2431*cbe63bfdSIskren Chernev .clkr = { 2432*cbe63bfdSIskren Chernev .enable_reg = 0x20008, 2433*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2434*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2435*cbe63bfdSIskren Chernev .name = "gcc_pdm_xo4_clk", 2436*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2437*cbe63bfdSIskren Chernev }, 2438*cbe63bfdSIskren Chernev }, 2439*cbe63bfdSIskren Chernev }; 2440*cbe63bfdSIskren Chernev 2441*cbe63bfdSIskren Chernev static struct clk_branch gcc_prng_ahb_clk = { 2442*cbe63bfdSIskren Chernev .halt_reg = 0x21004, 2443*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2444*cbe63bfdSIskren Chernev .hwcg_reg = 0x21004, 2445*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2446*cbe63bfdSIskren Chernev .clkr = { 2447*cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2448*cbe63bfdSIskren Chernev .enable_mask = BIT(13), 2449*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2450*cbe63bfdSIskren Chernev .name = "gcc_prng_ahb_clk", 2451*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2452*cbe63bfdSIskren Chernev }, 2453*cbe63bfdSIskren Chernev }, 2454*cbe63bfdSIskren Chernev }; 2455*cbe63bfdSIskren Chernev 2456*cbe63bfdSIskren Chernev static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2457*cbe63bfdSIskren Chernev .halt_reg = 0x17014, 2458*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2459*cbe63bfdSIskren Chernev .hwcg_reg = 0x17014, 2460*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2461*cbe63bfdSIskren Chernev .clkr = { 2462*cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2463*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2464*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2465*cbe63bfdSIskren Chernev .name = "gcc_qmip_camera_nrt_ahb_clk", 2466*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2467*cbe63bfdSIskren Chernev }, 2468*cbe63bfdSIskren Chernev }, 2469*cbe63bfdSIskren Chernev }; 2470*cbe63bfdSIskren Chernev 2471*cbe63bfdSIskren Chernev static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2472*cbe63bfdSIskren Chernev .halt_reg = 0x17060, 2473*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2474*cbe63bfdSIskren Chernev .hwcg_reg = 0x17060, 2475*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2476*cbe63bfdSIskren Chernev .clkr = { 2477*cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2478*cbe63bfdSIskren Chernev .enable_mask = BIT(2), 2479*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2480*cbe63bfdSIskren Chernev .name = "gcc_qmip_camera_rt_ahb_clk", 2481*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2482*cbe63bfdSIskren Chernev }, 2483*cbe63bfdSIskren Chernev }, 2484*cbe63bfdSIskren Chernev }; 2485*cbe63bfdSIskren Chernev 2486*cbe63bfdSIskren Chernev static struct clk_branch gcc_qmip_disp_ahb_clk = { 2487*cbe63bfdSIskren Chernev .halt_reg = 0x17018, 2488*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2489*cbe63bfdSIskren Chernev .hwcg_reg = 0x17018, 2490*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2491*cbe63bfdSIskren Chernev .clkr = { 2492*cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2493*cbe63bfdSIskren Chernev .enable_mask = BIT(1), 2494*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2495*cbe63bfdSIskren Chernev .name = "gcc_qmip_disp_ahb_clk", 2496*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2497*cbe63bfdSIskren Chernev }, 2498*cbe63bfdSIskren Chernev }, 2499*cbe63bfdSIskren Chernev }; 2500*cbe63bfdSIskren Chernev 2501*cbe63bfdSIskren Chernev static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = { 2502*cbe63bfdSIskren Chernev .halt_reg = 0x36040, 2503*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2504*cbe63bfdSIskren Chernev .hwcg_reg = 0x36040, 2505*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2506*cbe63bfdSIskren Chernev .clkr = { 2507*cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2508*cbe63bfdSIskren Chernev .enable_mask = BIT(4), 2509*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2510*cbe63bfdSIskren Chernev .name = "gcc_qmip_gpu_cfg_ahb_clk", 2511*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2512*cbe63bfdSIskren Chernev }, 2513*cbe63bfdSIskren Chernev }, 2514*cbe63bfdSIskren Chernev }; 2515*cbe63bfdSIskren Chernev 2516*cbe63bfdSIskren Chernev static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2517*cbe63bfdSIskren Chernev .halt_reg = 0x17010, 2518*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2519*cbe63bfdSIskren Chernev .hwcg_reg = 0x17010, 2520*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2521*cbe63bfdSIskren Chernev .clkr = { 2522*cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2523*cbe63bfdSIskren Chernev .enable_mask = BIT(25), 2524*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2525*cbe63bfdSIskren Chernev .name = "gcc_qmip_video_vcodec_ahb_clk", 2526*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2527*cbe63bfdSIskren Chernev }, 2528*cbe63bfdSIskren Chernev }, 2529*cbe63bfdSIskren Chernev }; 2530*cbe63bfdSIskren Chernev 2531*cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2532*cbe63bfdSIskren Chernev .halt_reg = 0x1f014, 2533*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2534*cbe63bfdSIskren Chernev .clkr = { 2535*cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2536*cbe63bfdSIskren Chernev .enable_mask = BIT(9), 2537*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2538*cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_core_2x_clk", 2539*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2540*cbe63bfdSIskren Chernev }, 2541*cbe63bfdSIskren Chernev }, 2542*cbe63bfdSIskren Chernev }; 2543*cbe63bfdSIskren Chernev 2544*cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2545*cbe63bfdSIskren Chernev .halt_reg = 0x1f00c, 2546*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2547*cbe63bfdSIskren Chernev .clkr = { 2548*cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2549*cbe63bfdSIskren Chernev .enable_mask = BIT(8), 2550*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2551*cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_core_clk", 2552*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2553*cbe63bfdSIskren Chernev }, 2554*cbe63bfdSIskren Chernev }, 2555*cbe63bfdSIskren Chernev }; 2556*cbe63bfdSIskren Chernev 2557*cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2558*cbe63bfdSIskren Chernev .halt_reg = 0x1f144, 2559*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2560*cbe63bfdSIskren Chernev .clkr = { 2561*cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2562*cbe63bfdSIskren Chernev .enable_mask = BIT(10), 2563*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2564*cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s0_clk", 2565*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2566*cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 2567*cbe63bfdSIskren Chernev }, 2568*cbe63bfdSIskren Chernev .num_parents = 1, 2569*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2570*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2571*cbe63bfdSIskren Chernev }, 2572*cbe63bfdSIskren Chernev }, 2573*cbe63bfdSIskren Chernev }; 2574*cbe63bfdSIskren Chernev 2575*cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2576*cbe63bfdSIskren Chernev .halt_reg = 0x1f274, 2577*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2578*cbe63bfdSIskren Chernev .clkr = { 2579*cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2580*cbe63bfdSIskren Chernev .enable_mask = BIT(11), 2581*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2582*cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s1_clk", 2583*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2584*cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 2585*cbe63bfdSIskren Chernev }, 2586*cbe63bfdSIskren Chernev .num_parents = 1, 2587*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2588*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2589*cbe63bfdSIskren Chernev }, 2590*cbe63bfdSIskren Chernev }, 2591*cbe63bfdSIskren Chernev }; 2592*cbe63bfdSIskren Chernev 2593*cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2594*cbe63bfdSIskren Chernev .halt_reg = 0x1f3a4, 2595*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2596*cbe63bfdSIskren Chernev .clkr = { 2597*cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2598*cbe63bfdSIskren Chernev .enable_mask = BIT(12), 2599*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2600*cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s2_clk", 2601*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2602*cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2603*cbe63bfdSIskren Chernev }, 2604*cbe63bfdSIskren Chernev .num_parents = 1, 2605*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2606*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2607*cbe63bfdSIskren Chernev }, 2608*cbe63bfdSIskren Chernev }, 2609*cbe63bfdSIskren Chernev }; 2610*cbe63bfdSIskren Chernev 2611*cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2612*cbe63bfdSIskren Chernev .halt_reg = 0x1f4d4, 2613*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2614*cbe63bfdSIskren Chernev .clkr = { 2615*cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2616*cbe63bfdSIskren Chernev .enable_mask = BIT(13), 2617*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2618*cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s3_clk", 2619*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2620*cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2621*cbe63bfdSIskren Chernev }, 2622*cbe63bfdSIskren Chernev .num_parents = 1, 2623*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2624*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2625*cbe63bfdSIskren Chernev }, 2626*cbe63bfdSIskren Chernev }, 2627*cbe63bfdSIskren Chernev }; 2628*cbe63bfdSIskren Chernev 2629*cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2630*cbe63bfdSIskren Chernev .halt_reg = 0x1f604, 2631*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2632*cbe63bfdSIskren Chernev .clkr = { 2633*cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2634*cbe63bfdSIskren Chernev .enable_mask = BIT(14), 2635*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2636*cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s4_clk", 2637*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2638*cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2639*cbe63bfdSIskren Chernev }, 2640*cbe63bfdSIskren Chernev .num_parents = 1, 2641*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2642*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2643*cbe63bfdSIskren Chernev }, 2644*cbe63bfdSIskren Chernev }, 2645*cbe63bfdSIskren Chernev }; 2646*cbe63bfdSIskren Chernev 2647*cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2648*cbe63bfdSIskren Chernev .halt_reg = 0x1f734, 2649*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2650*cbe63bfdSIskren Chernev .clkr = { 2651*cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2652*cbe63bfdSIskren Chernev .enable_mask = BIT(15), 2653*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2654*cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s5_clk", 2655*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2656*cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2657*cbe63bfdSIskren Chernev }, 2658*cbe63bfdSIskren Chernev .num_parents = 1, 2659*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2660*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2661*cbe63bfdSIskren Chernev }, 2662*cbe63bfdSIskren Chernev }, 2663*cbe63bfdSIskren Chernev }; 2664*cbe63bfdSIskren Chernev 2665*cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2666*cbe63bfdSIskren Chernev .halt_reg = 0x1f004, 2667*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2668*cbe63bfdSIskren Chernev .hwcg_reg = 0x1f004, 2669*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2670*cbe63bfdSIskren Chernev .clkr = { 2671*cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2672*cbe63bfdSIskren Chernev .enable_mask = BIT(6), 2673*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2674*cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2675*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2676*cbe63bfdSIskren Chernev }, 2677*cbe63bfdSIskren Chernev }, 2678*cbe63bfdSIskren Chernev }; 2679*cbe63bfdSIskren Chernev 2680*cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2681*cbe63bfdSIskren Chernev .halt_reg = 0x1f008, 2682*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2683*cbe63bfdSIskren Chernev .hwcg_reg = 0x1f008, 2684*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2685*cbe63bfdSIskren Chernev .clkr = { 2686*cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2687*cbe63bfdSIskren Chernev .enable_mask = BIT(7), 2688*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2689*cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2690*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2691*cbe63bfdSIskren Chernev }, 2692*cbe63bfdSIskren Chernev }, 2693*cbe63bfdSIskren Chernev }; 2694*cbe63bfdSIskren Chernev 2695*cbe63bfdSIskren Chernev static struct clk_branch gcc_sdcc1_ahb_clk = { 2696*cbe63bfdSIskren Chernev .halt_reg = 0x38008, 2697*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2698*cbe63bfdSIskren Chernev .clkr = { 2699*cbe63bfdSIskren Chernev .enable_reg = 0x38008, 2700*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2701*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2702*cbe63bfdSIskren Chernev .name = "gcc_sdcc1_ahb_clk", 2703*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2704*cbe63bfdSIskren Chernev }, 2705*cbe63bfdSIskren Chernev }, 2706*cbe63bfdSIskren Chernev }; 2707*cbe63bfdSIskren Chernev 2708*cbe63bfdSIskren Chernev static struct clk_branch gcc_sdcc1_apps_clk = { 2709*cbe63bfdSIskren Chernev .halt_reg = 0x38004, 2710*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2711*cbe63bfdSIskren Chernev .clkr = { 2712*cbe63bfdSIskren Chernev .enable_reg = 0x38004, 2713*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2714*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2715*cbe63bfdSIskren Chernev .name = "gcc_sdcc1_apps_clk", 2716*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2717*cbe63bfdSIskren Chernev &gcc_sdcc1_apps_clk_src.clkr.hw, 2718*cbe63bfdSIskren Chernev }, 2719*cbe63bfdSIskren Chernev .num_parents = 1, 2720*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT /* | CLK_ENABLE_HAND_OFF */, 2721*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2722*cbe63bfdSIskren Chernev }, 2723*cbe63bfdSIskren Chernev }, 2724*cbe63bfdSIskren Chernev }; 2725*cbe63bfdSIskren Chernev 2726*cbe63bfdSIskren Chernev static struct clk_branch gcc_sdcc1_ice_core_clk = { 2727*cbe63bfdSIskren Chernev .halt_reg = 0x3800c, 2728*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2729*cbe63bfdSIskren Chernev .hwcg_reg = 0x3800c, 2730*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2731*cbe63bfdSIskren Chernev .clkr = { 2732*cbe63bfdSIskren Chernev .enable_reg = 0x3800c, 2733*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2734*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2735*cbe63bfdSIskren Chernev .name = "gcc_sdcc1_ice_core_clk", 2736*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2737*cbe63bfdSIskren Chernev &gcc_sdcc1_ice_core_clk_src.clkr.hw, 2738*cbe63bfdSIskren Chernev }, 2739*cbe63bfdSIskren Chernev .num_parents = 1, 2740*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2741*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2742*cbe63bfdSIskren Chernev }, 2743*cbe63bfdSIskren Chernev }, 2744*cbe63bfdSIskren Chernev }; 2745*cbe63bfdSIskren Chernev 2746*cbe63bfdSIskren Chernev static struct clk_branch gcc_sdcc2_ahb_clk = { 2747*cbe63bfdSIskren Chernev .halt_reg = 0x1e008, 2748*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2749*cbe63bfdSIskren Chernev .clkr = { 2750*cbe63bfdSIskren Chernev .enable_reg = 0x1e008, 2751*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2752*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2753*cbe63bfdSIskren Chernev .name = "gcc_sdcc2_ahb_clk", 2754*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2755*cbe63bfdSIskren Chernev }, 2756*cbe63bfdSIskren Chernev }, 2757*cbe63bfdSIskren Chernev }; 2758*cbe63bfdSIskren Chernev 2759*cbe63bfdSIskren Chernev static struct clk_branch gcc_sdcc2_apps_clk = { 2760*cbe63bfdSIskren Chernev .halt_reg = 0x1e004, 2761*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2762*cbe63bfdSIskren Chernev .clkr = { 2763*cbe63bfdSIskren Chernev .enable_reg = 0x1e004, 2764*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2765*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2766*cbe63bfdSIskren Chernev .name = "gcc_sdcc2_apps_clk", 2767*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2768*cbe63bfdSIskren Chernev &gcc_sdcc2_apps_clk_src.clkr.hw, 2769*cbe63bfdSIskren Chernev }, 2770*cbe63bfdSIskren Chernev .num_parents = 1, 2771*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2772*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2773*cbe63bfdSIskren Chernev }, 2774*cbe63bfdSIskren Chernev }, 2775*cbe63bfdSIskren Chernev }; 2776*cbe63bfdSIskren Chernev 2777*cbe63bfdSIskren Chernev static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 2778*cbe63bfdSIskren Chernev .halt_reg = 0x2b06c, 2779*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2780*cbe63bfdSIskren Chernev .hwcg_reg = 0x2b06c, 2781*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2782*cbe63bfdSIskren Chernev .clkr = { 2783*cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2784*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2785*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2786*cbe63bfdSIskren Chernev .name = "gcc_sys_noc_cpuss_ahb_clk", 2787*cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 2788*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2789*cbe63bfdSIskren Chernev }, 2790*cbe63bfdSIskren Chernev }, 2791*cbe63bfdSIskren Chernev }; 2792*cbe63bfdSIskren Chernev 2793*cbe63bfdSIskren Chernev static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { 2794*cbe63bfdSIskren Chernev .halt_reg = 0x45098, 2795*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2796*cbe63bfdSIskren Chernev .clkr = { 2797*cbe63bfdSIskren Chernev .enable_reg = 0x45098, 2798*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2799*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2800*cbe63bfdSIskren Chernev .name = "gcc_sys_noc_ufs_phy_axi_clk", 2801*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2802*cbe63bfdSIskren Chernev &gcc_ufs_phy_axi_clk_src.clkr.hw, 2803*cbe63bfdSIskren Chernev }, 2804*cbe63bfdSIskren Chernev .num_parents = 1, 2805*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2806*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2807*cbe63bfdSIskren Chernev }, 2808*cbe63bfdSIskren Chernev }, 2809*cbe63bfdSIskren Chernev }; 2810*cbe63bfdSIskren Chernev 2811*cbe63bfdSIskren Chernev static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { 2812*cbe63bfdSIskren Chernev .halt_reg = 0x1a080, 2813*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2814*cbe63bfdSIskren Chernev .hwcg_reg = 0x1a080, 2815*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2816*cbe63bfdSIskren Chernev .clkr = { 2817*cbe63bfdSIskren Chernev .enable_reg = 0x1a080, 2818*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2819*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2820*cbe63bfdSIskren Chernev .name = "gcc_sys_noc_usb3_prim_axi_clk", 2821*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2822*cbe63bfdSIskren Chernev &gcc_usb30_prim_master_clk_src.clkr.hw, 2823*cbe63bfdSIskren Chernev }, 2824*cbe63bfdSIskren Chernev .num_parents = 1, 2825*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2826*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2827*cbe63bfdSIskren Chernev }, 2828*cbe63bfdSIskren Chernev }, 2829*cbe63bfdSIskren Chernev }; 2830*cbe63bfdSIskren Chernev 2831*cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_clkref_clk = { 2832*cbe63bfdSIskren Chernev .halt_reg = 0x8c000, 2833*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2834*cbe63bfdSIskren Chernev .clkr = { 2835*cbe63bfdSIskren Chernev .enable_reg = 0x8c000, 2836*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2837*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2838*cbe63bfdSIskren Chernev .name = "gcc_ufs_clkref_clk", 2839*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2840*cbe63bfdSIskren Chernev }, 2841*cbe63bfdSIskren Chernev }, 2842*cbe63bfdSIskren Chernev }; 2843*cbe63bfdSIskren Chernev 2844*cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_ahb_clk = { 2845*cbe63bfdSIskren Chernev .halt_reg = 0x45014, 2846*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2847*cbe63bfdSIskren Chernev .hwcg_reg = 0x45014, 2848*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2849*cbe63bfdSIskren Chernev .clkr = { 2850*cbe63bfdSIskren Chernev .enable_reg = 0x45014, 2851*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2852*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2853*cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_ahb_clk", 2854*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2855*cbe63bfdSIskren Chernev }, 2856*cbe63bfdSIskren Chernev }, 2857*cbe63bfdSIskren Chernev }; 2858*cbe63bfdSIskren Chernev 2859*cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_axi_clk = { 2860*cbe63bfdSIskren Chernev .halt_reg = 0x45010, 2861*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2862*cbe63bfdSIskren Chernev .hwcg_reg = 0x45010, 2863*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2864*cbe63bfdSIskren Chernev .clkr = { 2865*cbe63bfdSIskren Chernev .enable_reg = 0x45010, 2866*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2867*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2868*cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_axi_clk", 2869*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2870*cbe63bfdSIskren Chernev &gcc_ufs_phy_axi_clk_src.clkr.hw, 2871*cbe63bfdSIskren Chernev }, 2872*cbe63bfdSIskren Chernev .num_parents = 1, 2873*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2874*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2875*cbe63bfdSIskren Chernev }, 2876*cbe63bfdSIskren Chernev }, 2877*cbe63bfdSIskren Chernev }; 2878*cbe63bfdSIskren Chernev 2879*cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2880*cbe63bfdSIskren Chernev .halt_reg = 0x45044, 2881*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2882*cbe63bfdSIskren Chernev .hwcg_reg = 0x45044, 2883*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2884*cbe63bfdSIskren Chernev .clkr = { 2885*cbe63bfdSIskren Chernev .enable_reg = 0x45044, 2886*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2887*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2888*cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_ice_core_clk", 2889*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2890*cbe63bfdSIskren Chernev &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2891*cbe63bfdSIskren Chernev }, 2892*cbe63bfdSIskren Chernev .num_parents = 1, 2893*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2894*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2895*cbe63bfdSIskren Chernev }, 2896*cbe63bfdSIskren Chernev }, 2897*cbe63bfdSIskren Chernev }; 2898*cbe63bfdSIskren Chernev 2899*cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2900*cbe63bfdSIskren Chernev .halt_reg = 0x45078, 2901*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2902*cbe63bfdSIskren Chernev .hwcg_reg = 0x45078, 2903*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2904*cbe63bfdSIskren Chernev .clkr = { 2905*cbe63bfdSIskren Chernev .enable_reg = 0x45078, 2906*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2907*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2908*cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_phy_aux_clk", 2909*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2910*cbe63bfdSIskren Chernev &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2911*cbe63bfdSIskren Chernev }, 2912*cbe63bfdSIskren Chernev .num_parents = 1, 2913*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2914*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2915*cbe63bfdSIskren Chernev }, 2916*cbe63bfdSIskren Chernev }, 2917*cbe63bfdSIskren Chernev }; 2918*cbe63bfdSIskren Chernev 2919*cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2920*cbe63bfdSIskren Chernev .halt_reg = 0x4501c, 2921*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_SKIP, 2922*cbe63bfdSIskren Chernev .clkr = { 2923*cbe63bfdSIskren Chernev .enable_reg = 0x4501c, 2924*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2925*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2926*cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_rx_symbol_0_clk", 2927*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2928*cbe63bfdSIskren Chernev }, 2929*cbe63bfdSIskren Chernev }, 2930*cbe63bfdSIskren Chernev }; 2931*cbe63bfdSIskren Chernev 2932*cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2933*cbe63bfdSIskren Chernev .halt_reg = 0x45018, 2934*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_SKIP, 2935*cbe63bfdSIskren Chernev .clkr = { 2936*cbe63bfdSIskren Chernev .enable_reg = 0x45018, 2937*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2938*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2939*cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_tx_symbol_0_clk", 2940*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2941*cbe63bfdSIskren Chernev }, 2942*cbe63bfdSIskren Chernev }, 2943*cbe63bfdSIskren Chernev }; 2944*cbe63bfdSIskren Chernev 2945*cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2946*cbe63bfdSIskren Chernev .halt_reg = 0x45040, 2947*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2948*cbe63bfdSIskren Chernev .hwcg_reg = 0x45040, 2949*cbe63bfdSIskren Chernev .hwcg_bit = 1, 2950*cbe63bfdSIskren Chernev .clkr = { 2951*cbe63bfdSIskren Chernev .enable_reg = 0x45040, 2952*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2953*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2954*cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_unipro_core_clk", 2955*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2956*cbe63bfdSIskren Chernev &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2957*cbe63bfdSIskren Chernev }, 2958*cbe63bfdSIskren Chernev .num_parents = 1, 2959*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2960*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2961*cbe63bfdSIskren Chernev }, 2962*cbe63bfdSIskren Chernev }, 2963*cbe63bfdSIskren Chernev }; 2964*cbe63bfdSIskren Chernev 2965*cbe63bfdSIskren Chernev static struct clk_branch gcc_usb30_prim_master_clk = { 2966*cbe63bfdSIskren Chernev .halt_reg = 0x1a010, 2967*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2968*cbe63bfdSIskren Chernev .clkr = { 2969*cbe63bfdSIskren Chernev .enable_reg = 0x1a010, 2970*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2971*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2972*cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_master_clk", 2973*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2974*cbe63bfdSIskren Chernev &gcc_usb30_prim_master_clk_src.clkr.hw, 2975*cbe63bfdSIskren Chernev }, 2976*cbe63bfdSIskren Chernev .num_parents = 1, 2977*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2978*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2979*cbe63bfdSIskren Chernev }, 2980*cbe63bfdSIskren Chernev }, 2981*cbe63bfdSIskren Chernev }; 2982*cbe63bfdSIskren Chernev 2983*cbe63bfdSIskren Chernev static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2984*cbe63bfdSIskren Chernev .halt_reg = 0x1a018, 2985*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2986*cbe63bfdSIskren Chernev .clkr = { 2987*cbe63bfdSIskren Chernev .enable_reg = 0x1a018, 2988*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2989*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2990*cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_mock_utmi_clk", 2991*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2992*cbe63bfdSIskren Chernev &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2993*cbe63bfdSIskren Chernev }, 2994*cbe63bfdSIskren Chernev .num_parents = 1, 2995*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2996*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2997*cbe63bfdSIskren Chernev }, 2998*cbe63bfdSIskren Chernev }, 2999*cbe63bfdSIskren Chernev }; 3000*cbe63bfdSIskren Chernev 3001*cbe63bfdSIskren Chernev static struct clk_branch gcc_usb30_prim_sleep_clk = { 3002*cbe63bfdSIskren Chernev .halt_reg = 0x1a014, 3003*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3004*cbe63bfdSIskren Chernev .clkr = { 3005*cbe63bfdSIskren Chernev .enable_reg = 0x1a014, 3006*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3007*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3008*cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_sleep_clk", 3009*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3010*cbe63bfdSIskren Chernev }, 3011*cbe63bfdSIskren Chernev }, 3012*cbe63bfdSIskren Chernev }; 3013*cbe63bfdSIskren Chernev 3014*cbe63bfdSIskren Chernev static struct clk_branch gcc_usb3_prim_clkref_clk = { 3015*cbe63bfdSIskren Chernev .halt_reg = 0x9f000, 3016*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3017*cbe63bfdSIskren Chernev .clkr = { 3018*cbe63bfdSIskren Chernev .enable_reg = 0x9f000, 3019*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3020*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3021*cbe63bfdSIskren Chernev .name = "gcc_usb3_prim_clkref_clk", 3022*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3023*cbe63bfdSIskren Chernev }, 3024*cbe63bfdSIskren Chernev }, 3025*cbe63bfdSIskren Chernev }; 3026*cbe63bfdSIskren Chernev 3027*cbe63bfdSIskren Chernev static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3028*cbe63bfdSIskren Chernev .halt_reg = 0x1a054, 3029*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3030*cbe63bfdSIskren Chernev .clkr = { 3031*cbe63bfdSIskren Chernev .enable_reg = 0x1a054, 3032*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3033*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3034*cbe63bfdSIskren Chernev .name = "gcc_usb3_prim_phy_com_aux_clk", 3035*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 3036*cbe63bfdSIskren Chernev &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3037*cbe63bfdSIskren Chernev }, 3038*cbe63bfdSIskren Chernev .num_parents = 1, 3039*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 3040*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3041*cbe63bfdSIskren Chernev }, 3042*cbe63bfdSIskren Chernev }, 3043*cbe63bfdSIskren Chernev }; 3044*cbe63bfdSIskren Chernev 3045*cbe63bfdSIskren Chernev static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3046*cbe63bfdSIskren Chernev .halt_reg = 0x1a058, 3047*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_SKIP, 3048*cbe63bfdSIskren Chernev .hwcg_reg = 0x1a058, 3049*cbe63bfdSIskren Chernev .hwcg_bit = 1, 3050*cbe63bfdSIskren Chernev .clkr = { 3051*cbe63bfdSIskren Chernev .enable_reg = 0x1a058, 3052*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3053*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3054*cbe63bfdSIskren Chernev .name = "gcc_usb3_prim_phy_pipe_clk", 3055*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3056*cbe63bfdSIskren Chernev }, 3057*cbe63bfdSIskren Chernev }, 3058*cbe63bfdSIskren Chernev }; 3059*cbe63bfdSIskren Chernev 3060*cbe63bfdSIskren Chernev static struct clk_branch gcc_vcodec0_axi_clk = { 3061*cbe63bfdSIskren Chernev .halt_reg = 0x6e008, 3062*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3063*cbe63bfdSIskren Chernev .clkr = { 3064*cbe63bfdSIskren Chernev .enable_reg = 0x6e008, 3065*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3066*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3067*cbe63bfdSIskren Chernev .name = "gcc_vcodec0_axi_clk", 3068*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3069*cbe63bfdSIskren Chernev }, 3070*cbe63bfdSIskren Chernev }, 3071*cbe63bfdSIskren Chernev }; 3072*cbe63bfdSIskren Chernev 3073*cbe63bfdSIskren Chernev static struct clk_branch gcc_venus_ahb_clk = { 3074*cbe63bfdSIskren Chernev .halt_reg = 0x6e010, 3075*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3076*cbe63bfdSIskren Chernev .clkr = { 3077*cbe63bfdSIskren Chernev .enable_reg = 0x6e010, 3078*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3079*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3080*cbe63bfdSIskren Chernev .name = "gcc_venus_ahb_clk", 3081*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3082*cbe63bfdSIskren Chernev }, 3083*cbe63bfdSIskren Chernev }, 3084*cbe63bfdSIskren Chernev }; 3085*cbe63bfdSIskren Chernev 3086*cbe63bfdSIskren Chernev static struct clk_branch gcc_venus_ctl_axi_clk = { 3087*cbe63bfdSIskren Chernev .halt_reg = 0x6e004, 3088*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3089*cbe63bfdSIskren Chernev .clkr = { 3090*cbe63bfdSIskren Chernev .enable_reg = 0x6e004, 3091*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3092*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3093*cbe63bfdSIskren Chernev .name = "gcc_venus_ctl_axi_clk", 3094*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3095*cbe63bfdSIskren Chernev }, 3096*cbe63bfdSIskren Chernev }, 3097*cbe63bfdSIskren Chernev }; 3098*cbe63bfdSIskren Chernev 3099*cbe63bfdSIskren Chernev static struct clk_branch gcc_video_ahb_clk = { 3100*cbe63bfdSIskren Chernev .halt_reg = 0x17004, 3101*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3102*cbe63bfdSIskren Chernev .hwcg_reg = 0x17004, 3103*cbe63bfdSIskren Chernev .hwcg_bit = 1, 3104*cbe63bfdSIskren Chernev .clkr = { 3105*cbe63bfdSIskren Chernev .enable_reg = 0x17004, 3106*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3107*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3108*cbe63bfdSIskren Chernev .name = "gcc_video_ahb_clk", 3109*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3110*cbe63bfdSIskren Chernev }, 3111*cbe63bfdSIskren Chernev }, 3112*cbe63bfdSIskren Chernev }; 3113*cbe63bfdSIskren Chernev 3114*cbe63bfdSIskren Chernev static struct clk_branch gcc_video_axi0_clk = { 3115*cbe63bfdSIskren Chernev .halt_reg = 0x1701c, 3116*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3117*cbe63bfdSIskren Chernev .hwcg_reg = 0x1701c, 3118*cbe63bfdSIskren Chernev .hwcg_bit = 1, 3119*cbe63bfdSIskren Chernev .clkr = { 3120*cbe63bfdSIskren Chernev .enable_reg = 0x1701c, 3121*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3122*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3123*cbe63bfdSIskren Chernev .name = "gcc_video_axi0_clk", 3124*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3125*cbe63bfdSIskren Chernev }, 3126*cbe63bfdSIskren Chernev }, 3127*cbe63bfdSIskren Chernev }; 3128*cbe63bfdSIskren Chernev 3129*cbe63bfdSIskren Chernev static struct clk_branch gcc_video_throttle_core_clk = { 3130*cbe63bfdSIskren Chernev .halt_reg = 0x17068, 3131*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 3132*cbe63bfdSIskren Chernev .hwcg_reg = 0x17068, 3133*cbe63bfdSIskren Chernev .hwcg_bit = 1, 3134*cbe63bfdSIskren Chernev .clkr = { 3135*cbe63bfdSIskren Chernev .enable_reg = 0x79004, 3136*cbe63bfdSIskren Chernev .enable_mask = BIT(28), 3137*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3138*cbe63bfdSIskren Chernev .name = "gcc_video_throttle_core_clk", 3139*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3140*cbe63bfdSIskren Chernev }, 3141*cbe63bfdSIskren Chernev }, 3142*cbe63bfdSIskren Chernev }; 3143*cbe63bfdSIskren Chernev 3144*cbe63bfdSIskren Chernev static struct clk_branch gcc_video_vcodec0_sys_clk = { 3145*cbe63bfdSIskren Chernev .halt_reg = 0x580a4, 3146*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 3147*cbe63bfdSIskren Chernev .hwcg_reg = 0x580a4, 3148*cbe63bfdSIskren Chernev .hwcg_bit = 1, 3149*cbe63bfdSIskren Chernev .clkr = { 3150*cbe63bfdSIskren Chernev .enable_reg = 0x580a4, 3151*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3152*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3153*cbe63bfdSIskren Chernev .name = "gcc_video_vcodec0_sys_clk", 3154*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 3155*cbe63bfdSIskren Chernev &gcc_video_venus_clk_src.clkr.hw, 3156*cbe63bfdSIskren Chernev }, 3157*cbe63bfdSIskren Chernev .num_parents = 1, 3158*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 3159*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3160*cbe63bfdSIskren Chernev }, 3161*cbe63bfdSIskren Chernev }, 3162*cbe63bfdSIskren Chernev }; 3163*cbe63bfdSIskren Chernev 3164*cbe63bfdSIskren Chernev static struct clk_branch gcc_video_venus_ctl_clk = { 3165*cbe63bfdSIskren Chernev .halt_reg = 0x5808c, 3166*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3167*cbe63bfdSIskren Chernev .clkr = { 3168*cbe63bfdSIskren Chernev .enable_reg = 0x5808c, 3169*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3170*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3171*cbe63bfdSIskren Chernev .name = "gcc_video_venus_ctl_clk", 3172*cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 3173*cbe63bfdSIskren Chernev &gcc_video_venus_clk_src.clkr.hw, 3174*cbe63bfdSIskren Chernev }, 3175*cbe63bfdSIskren Chernev .num_parents = 1, 3176*cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 3177*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3178*cbe63bfdSIskren Chernev }, 3179*cbe63bfdSIskren Chernev }, 3180*cbe63bfdSIskren Chernev }; 3181*cbe63bfdSIskren Chernev 3182*cbe63bfdSIskren Chernev static struct clk_branch gcc_video_xo_clk = { 3183*cbe63bfdSIskren Chernev .halt_reg = 0x17024, 3184*cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3185*cbe63bfdSIskren Chernev .clkr = { 3186*cbe63bfdSIskren Chernev .enable_reg = 0x17024, 3187*cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3188*cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3189*cbe63bfdSIskren Chernev .name = "gcc_video_xo_clk", 3190*cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3191*cbe63bfdSIskren Chernev }, 3192*cbe63bfdSIskren Chernev }, 3193*cbe63bfdSIskren Chernev }; 3194*cbe63bfdSIskren Chernev 3195*cbe63bfdSIskren Chernev static struct gdsc gcc_camss_top_gdsc = { 3196*cbe63bfdSIskren Chernev .gdscr = 0x58004, 3197*cbe63bfdSIskren Chernev .pd = { 3198*cbe63bfdSIskren Chernev .name = "gcc_camss_top", 3199*cbe63bfdSIskren Chernev }, 3200*cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3201*cbe63bfdSIskren Chernev }; 3202*cbe63bfdSIskren Chernev 3203*cbe63bfdSIskren Chernev static struct gdsc gcc_ufs_phy_gdsc = { 3204*cbe63bfdSIskren Chernev .gdscr = 0x45004, 3205*cbe63bfdSIskren Chernev .pd = { 3206*cbe63bfdSIskren Chernev .name = "gcc_ufs_phy", 3207*cbe63bfdSIskren Chernev }, 3208*cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3209*cbe63bfdSIskren Chernev }; 3210*cbe63bfdSIskren Chernev 3211*cbe63bfdSIskren Chernev static struct gdsc gcc_usb30_prim_gdsc = { 3212*cbe63bfdSIskren Chernev .gdscr = 0x1a004, 3213*cbe63bfdSIskren Chernev .pd = { 3214*cbe63bfdSIskren Chernev .name = "gcc_usb30_prim", 3215*cbe63bfdSIskren Chernev }, 3216*cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3217*cbe63bfdSIskren Chernev }; 3218*cbe63bfdSIskren Chernev 3219*cbe63bfdSIskren Chernev static struct gdsc gcc_vcodec0_gdsc = { 3220*cbe63bfdSIskren Chernev .gdscr = 0x58098, 3221*cbe63bfdSIskren Chernev .pd = { 3222*cbe63bfdSIskren Chernev .name = "gcc_vcodec0", 3223*cbe63bfdSIskren Chernev }, 3224*cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3225*cbe63bfdSIskren Chernev }; 3226*cbe63bfdSIskren Chernev 3227*cbe63bfdSIskren Chernev static struct gdsc gcc_venus_gdsc = { 3228*cbe63bfdSIskren Chernev .gdscr = 0x5807c, 3229*cbe63bfdSIskren Chernev .pd = { 3230*cbe63bfdSIskren Chernev .name = "gcc_venus", 3231*cbe63bfdSIskren Chernev }, 3232*cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3233*cbe63bfdSIskren Chernev }; 3234*cbe63bfdSIskren Chernev 3235*cbe63bfdSIskren Chernev static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = { 3236*cbe63bfdSIskren Chernev .gdscr = 0x7d060, 3237*cbe63bfdSIskren Chernev .pd = { 3238*cbe63bfdSIskren Chernev .name = "hlos1_vote_turing_mmu_tbu1", 3239*cbe63bfdSIskren Chernev }, 3240*cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3241*cbe63bfdSIskren Chernev .flags = VOTABLE, 3242*cbe63bfdSIskren Chernev }; 3243*cbe63bfdSIskren Chernev 3244*cbe63bfdSIskren Chernev static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { 3245*cbe63bfdSIskren Chernev .gdscr = 0x7d060, 3246*cbe63bfdSIskren Chernev .pd = { 3247*cbe63bfdSIskren Chernev .name = "hlos1_vote_turing_mmu_tbu0", 3248*cbe63bfdSIskren Chernev }, 3249*cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3250*cbe63bfdSIskren Chernev .flags = VOTABLE, 3251*cbe63bfdSIskren Chernev }; 3252*cbe63bfdSIskren Chernev 3253*cbe63bfdSIskren Chernev static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = { 3254*cbe63bfdSIskren Chernev .gdscr = 0x7d074, 3255*cbe63bfdSIskren Chernev .pd = { 3256*cbe63bfdSIskren Chernev .name = "hlos1_vote_mm_snoc_mmu_tbu_rt", 3257*cbe63bfdSIskren Chernev }, 3258*cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3259*cbe63bfdSIskren Chernev .flags = VOTABLE, 3260*cbe63bfdSIskren Chernev }; 3261*cbe63bfdSIskren Chernev 3262*cbe63bfdSIskren Chernev static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = { 3263*cbe63bfdSIskren Chernev .gdscr = 0x7d078, 3264*cbe63bfdSIskren Chernev .pd = { 3265*cbe63bfdSIskren Chernev .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt", 3266*cbe63bfdSIskren Chernev }, 3267*cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3268*cbe63bfdSIskren Chernev .flags = VOTABLE, 3269*cbe63bfdSIskren Chernev }; 3270*cbe63bfdSIskren Chernev 3271*cbe63bfdSIskren Chernev static struct clk_regmap *gcc_sm6115_clocks[] = { 3272*cbe63bfdSIskren Chernev [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr, 3273*cbe63bfdSIskren Chernev [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr, 3274*cbe63bfdSIskren Chernev [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr, 3275*cbe63bfdSIskren Chernev [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3276*cbe63bfdSIskren Chernev [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, 3277*cbe63bfdSIskren Chernev [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, 3278*cbe63bfdSIskren Chernev [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 3279*cbe63bfdSIskren Chernev [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 3280*cbe63bfdSIskren Chernev [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, 3281*cbe63bfdSIskren Chernev [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, 3282*cbe63bfdSIskren Chernev [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr, 3283*cbe63bfdSIskren Chernev [GCC_CAMSS_CAMNOC_NTS_XO_CLK] = &gcc_camss_camnoc_nts_xo_clk.clkr, 3284*cbe63bfdSIskren Chernev [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr, 3285*cbe63bfdSIskren Chernev [GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr, 3286*cbe63bfdSIskren Chernev [GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr, 3287*cbe63bfdSIskren Chernev [GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr, 3288*cbe63bfdSIskren Chernev [GCC_CAMSS_CPHY_2_CLK] = &gcc_camss_cphy_2_clk.clkr, 3289*cbe63bfdSIskren Chernev [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 3290*cbe63bfdSIskren Chernev [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr, 3291*cbe63bfdSIskren Chernev [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, 3292*cbe63bfdSIskren Chernev [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr, 3293*cbe63bfdSIskren Chernev [GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr, 3294*cbe63bfdSIskren Chernev [GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr, 3295*cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 3296*cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr, 3297*cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 3298*cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr, 3299*cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, 3300*cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr, 3301*cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr, 3302*cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr, 3303*cbe63bfdSIskren Chernev [GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr, 3304*cbe63bfdSIskren Chernev [GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr, 3305*cbe63bfdSIskren Chernev [GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr, 3306*cbe63bfdSIskren Chernev [GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr, 3307*cbe63bfdSIskren Chernev [GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr, 3308*cbe63bfdSIskren Chernev [GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr, 3309*cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr, 3310*cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr, 3311*cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr, 3312*cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr, 3313*cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr, 3314*cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr, 3315*cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr, 3316*cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr, 3317*cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr, 3318*cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr, 3319*cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_2_CLK] = &gcc_camss_tfe_2_clk.clkr, 3320*cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_2_CLK_SRC] = &gcc_camss_tfe_2_clk_src.clkr, 3321*cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_2_CPHY_RX_CLK] = &gcc_camss_tfe_2_cphy_rx_clk.clkr, 3322*cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_2_CSID_CLK] = &gcc_camss_tfe_2_csid_clk.clkr, 3323*cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_2_CSID_CLK_SRC] = &gcc_camss_tfe_2_csid_clk_src.clkr, 3324*cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr, 3325*cbe63bfdSIskren Chernev [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 3326*cbe63bfdSIskren Chernev [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, 3327*cbe63bfdSIskren Chernev [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3328*cbe63bfdSIskren Chernev [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, 3329*cbe63bfdSIskren Chernev [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, 3330*cbe63bfdSIskren Chernev [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 3331*cbe63bfdSIskren Chernev [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 3332*cbe63bfdSIskren Chernev [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3333*cbe63bfdSIskren Chernev [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, 3334*cbe63bfdSIskren Chernev [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 3335*cbe63bfdSIskren Chernev [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3336*cbe63bfdSIskren Chernev [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3337*cbe63bfdSIskren Chernev [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3338*cbe63bfdSIskren Chernev [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3339*cbe63bfdSIskren Chernev [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3340*cbe63bfdSIskren Chernev [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3341*cbe63bfdSIskren Chernev [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 3342*cbe63bfdSIskren Chernev [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3343*cbe63bfdSIskren Chernev [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3344*cbe63bfdSIskren Chernev [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, 3345*cbe63bfdSIskren Chernev [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3346*cbe63bfdSIskren Chernev [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3347*cbe63bfdSIskren Chernev [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, 3348*cbe63bfdSIskren Chernev [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3349*cbe63bfdSIskren Chernev [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3350*cbe63bfdSIskren Chernev [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3351*cbe63bfdSIskren Chernev [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3352*cbe63bfdSIskren Chernev [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3353*cbe63bfdSIskren Chernev [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3354*cbe63bfdSIskren Chernev [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3355*cbe63bfdSIskren Chernev [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3356*cbe63bfdSIskren Chernev [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr, 3357*cbe63bfdSIskren Chernev [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3358*cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 3359*cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 3360*cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3361*cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3362*cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3363*cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3364*cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3365*cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3366*cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3367*cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3368*cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3369*cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3370*cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3371*cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3372*cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3373*cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3374*cbe63bfdSIskren Chernev [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3375*cbe63bfdSIskren Chernev [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3376*cbe63bfdSIskren Chernev [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 3377*cbe63bfdSIskren Chernev [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 3378*cbe63bfdSIskren Chernev [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 3379*cbe63bfdSIskren Chernev [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3380*cbe63bfdSIskren Chernev [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3381*cbe63bfdSIskren Chernev [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3382*cbe63bfdSIskren Chernev [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 3383*cbe63bfdSIskren Chernev [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, 3384*cbe63bfdSIskren Chernev [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, 3385*cbe63bfdSIskren Chernev [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, 3386*cbe63bfdSIskren Chernev [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3387*cbe63bfdSIskren Chernev [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3388*cbe63bfdSIskren Chernev [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3389*cbe63bfdSIskren Chernev [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3390*cbe63bfdSIskren Chernev [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3391*cbe63bfdSIskren Chernev [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3392*cbe63bfdSIskren Chernev [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3393*cbe63bfdSIskren Chernev [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3394*cbe63bfdSIskren Chernev [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3395*cbe63bfdSIskren Chernev [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3396*cbe63bfdSIskren Chernev [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 3397*cbe63bfdSIskren Chernev &gcc_ufs_phy_unipro_core_clk_src.clkr, 3398*cbe63bfdSIskren Chernev [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3399*cbe63bfdSIskren Chernev [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3400*cbe63bfdSIskren Chernev [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3401*cbe63bfdSIskren Chernev [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 3402*cbe63bfdSIskren Chernev &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3403*cbe63bfdSIskren Chernev [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = 3404*cbe63bfdSIskren Chernev &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3405*cbe63bfdSIskren Chernev [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3406*cbe63bfdSIskren Chernev [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 3407*cbe63bfdSIskren Chernev [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3408*cbe63bfdSIskren Chernev [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3409*cbe63bfdSIskren Chernev [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3410*cbe63bfdSIskren Chernev [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr, 3411*cbe63bfdSIskren Chernev [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr, 3412*cbe63bfdSIskren Chernev [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr, 3413*cbe63bfdSIskren Chernev [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 3414*cbe63bfdSIskren Chernev [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3415*cbe63bfdSIskren Chernev [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, 3416*cbe63bfdSIskren Chernev [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr, 3417*cbe63bfdSIskren Chernev [GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr, 3418*cbe63bfdSIskren Chernev [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr, 3419*cbe63bfdSIskren Chernev [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 3420*cbe63bfdSIskren Chernev [GPLL0] = &gpll0.clkr, 3421*cbe63bfdSIskren Chernev [GPLL0_OUT_AUX2] = &gpll0_out_aux2.clkr, 3422*cbe63bfdSIskren Chernev [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr, 3423*cbe63bfdSIskren Chernev [GPLL10] = &gpll10.clkr, 3424*cbe63bfdSIskren Chernev [GPLL10_OUT_MAIN] = &gpll10_out_main.clkr, 3425*cbe63bfdSIskren Chernev [GPLL11] = &gpll11.clkr, 3426*cbe63bfdSIskren Chernev [GPLL11_OUT_MAIN] = &gpll11_out_main.clkr, 3427*cbe63bfdSIskren Chernev [GPLL3] = &gpll3.clkr, 3428*cbe63bfdSIskren Chernev [GPLL4] = &gpll4.clkr, 3429*cbe63bfdSIskren Chernev [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr, 3430*cbe63bfdSIskren Chernev [GPLL6] = &gpll6.clkr, 3431*cbe63bfdSIskren Chernev [GPLL6_OUT_MAIN] = &gpll6_out_main.clkr, 3432*cbe63bfdSIskren Chernev [GPLL7] = &gpll7.clkr, 3433*cbe63bfdSIskren Chernev [GPLL7_OUT_MAIN] = &gpll7_out_main.clkr, 3434*cbe63bfdSIskren Chernev [GPLL8] = &gpll8.clkr, 3435*cbe63bfdSIskren Chernev [GPLL8_OUT_MAIN] = &gpll8_out_main.clkr, 3436*cbe63bfdSIskren Chernev [GPLL9] = &gpll9.clkr, 3437*cbe63bfdSIskren Chernev [GPLL9_OUT_MAIN] = &gpll9_out_main.clkr, 3438*cbe63bfdSIskren Chernev }; 3439*cbe63bfdSIskren Chernev 3440*cbe63bfdSIskren Chernev static const struct qcom_reset_map gcc_sm6115_resets[] = { 3441*cbe63bfdSIskren Chernev [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, 3442*cbe63bfdSIskren Chernev [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, 3443*cbe63bfdSIskren Chernev [GCC_SDCC1_BCR] = { 0x38000 }, 3444*cbe63bfdSIskren Chernev [GCC_SDCC2_BCR] = { 0x1e000 }, 3445*cbe63bfdSIskren Chernev [GCC_UFS_PHY_BCR] = { 0x45000 }, 3446*cbe63bfdSIskren Chernev [GCC_USB30_PRIM_BCR] = { 0x1a000 }, 3447*cbe63bfdSIskren Chernev [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, 3448*cbe63bfdSIskren Chernev [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, 3449*cbe63bfdSIskren Chernev [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, 3450*cbe63bfdSIskren Chernev [GCC_VCODEC0_BCR] = { 0x58094 }, 3451*cbe63bfdSIskren Chernev [GCC_VENUS_BCR] = { 0x58078 }, 3452*cbe63bfdSIskren Chernev [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 }, 3453*cbe63bfdSIskren Chernev }; 3454*cbe63bfdSIskren Chernev 3455*cbe63bfdSIskren Chernev static struct gdsc *gcc_sm6115_gdscs[] = { 3456*cbe63bfdSIskren Chernev [GCC_CAMSS_TOP_GDSC] = &gcc_camss_top_gdsc, 3457*cbe63bfdSIskren Chernev [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, 3458*cbe63bfdSIskren Chernev [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 3459*cbe63bfdSIskren Chernev [GCC_VCODEC0_GDSC] = &gcc_vcodec0_gdsc, 3460*cbe63bfdSIskren Chernev [GCC_VENUS_GDSC] = &gcc_venus_gdsc, 3461*cbe63bfdSIskren Chernev [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, 3462*cbe63bfdSIskren Chernev [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc, 3463*cbe63bfdSIskren Chernev [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc, 3464*cbe63bfdSIskren Chernev [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc, 3465*cbe63bfdSIskren Chernev }; 3466*cbe63bfdSIskren Chernev 3467*cbe63bfdSIskren Chernev static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3468*cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3469*cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3470*cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3471*cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3472*cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3473*cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3474*cbe63bfdSIskren Chernev }; 3475*cbe63bfdSIskren Chernev 3476*cbe63bfdSIskren Chernev static const struct regmap_config gcc_sm6115_regmap_config = { 3477*cbe63bfdSIskren Chernev .reg_bits = 32, 3478*cbe63bfdSIskren Chernev .reg_stride = 4, 3479*cbe63bfdSIskren Chernev .val_bits = 32, 3480*cbe63bfdSIskren Chernev .max_register = 0xc7000, 3481*cbe63bfdSIskren Chernev .fast_io = true, 3482*cbe63bfdSIskren Chernev }; 3483*cbe63bfdSIskren Chernev 3484*cbe63bfdSIskren Chernev static const struct qcom_cc_desc gcc_sm6115_desc = { 3485*cbe63bfdSIskren Chernev .config = &gcc_sm6115_regmap_config, 3486*cbe63bfdSIskren Chernev .clks = gcc_sm6115_clocks, 3487*cbe63bfdSIskren Chernev .num_clks = ARRAY_SIZE(gcc_sm6115_clocks), 3488*cbe63bfdSIskren Chernev .resets = gcc_sm6115_resets, 3489*cbe63bfdSIskren Chernev .num_resets = ARRAY_SIZE(gcc_sm6115_resets), 3490*cbe63bfdSIskren Chernev .gdscs = gcc_sm6115_gdscs, 3491*cbe63bfdSIskren Chernev .num_gdscs = ARRAY_SIZE(gcc_sm6115_gdscs), 3492*cbe63bfdSIskren Chernev }; 3493*cbe63bfdSIskren Chernev 3494*cbe63bfdSIskren Chernev static const struct of_device_id gcc_sm6115_match_table[] = { 3495*cbe63bfdSIskren Chernev { .compatible = "qcom,gcc-sm6115" }, 3496*cbe63bfdSIskren Chernev { } 3497*cbe63bfdSIskren Chernev }; 3498*cbe63bfdSIskren Chernev MODULE_DEVICE_TABLE(of, gcc_sm6115_match_table); 3499*cbe63bfdSIskren Chernev 3500*cbe63bfdSIskren Chernev static int gcc_sm6115_probe(struct platform_device *pdev) 3501*cbe63bfdSIskren Chernev { 3502*cbe63bfdSIskren Chernev struct regmap *regmap; 3503*cbe63bfdSIskren Chernev int ret; 3504*cbe63bfdSIskren Chernev 3505*cbe63bfdSIskren Chernev regmap = qcom_cc_map(pdev, &gcc_sm6115_desc); 3506*cbe63bfdSIskren Chernev if (IS_ERR(regmap)) 3507*cbe63bfdSIskren Chernev return PTR_ERR(regmap); 3508*cbe63bfdSIskren Chernev 3509*cbe63bfdSIskren Chernev ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3510*cbe63bfdSIskren Chernev ARRAY_SIZE(gcc_dfs_clocks)); 3511*cbe63bfdSIskren Chernev if (ret) 3512*cbe63bfdSIskren Chernev return ret; 3513*cbe63bfdSIskren Chernev 3514*cbe63bfdSIskren Chernev clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config); 3515*cbe63bfdSIskren Chernev clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config); 3516*cbe63bfdSIskren Chernev clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config); 3517*cbe63bfdSIskren Chernev clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config); 3518*cbe63bfdSIskren Chernev 3519*cbe63bfdSIskren Chernev return qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap); 3520*cbe63bfdSIskren Chernev } 3521*cbe63bfdSIskren Chernev 3522*cbe63bfdSIskren Chernev static struct platform_driver gcc_sm6115_driver = { 3523*cbe63bfdSIskren Chernev .probe = gcc_sm6115_probe, 3524*cbe63bfdSIskren Chernev .driver = { 3525*cbe63bfdSIskren Chernev .name = "gcc-sm6115", 3526*cbe63bfdSIskren Chernev .of_match_table = gcc_sm6115_match_table, 3527*cbe63bfdSIskren Chernev }, 3528*cbe63bfdSIskren Chernev }; 3529*cbe63bfdSIskren Chernev 3530*cbe63bfdSIskren Chernev static int __init gcc_sm6115_init(void) 3531*cbe63bfdSIskren Chernev { 3532*cbe63bfdSIskren Chernev return platform_driver_register(&gcc_sm6115_driver); 3533*cbe63bfdSIskren Chernev } 3534*cbe63bfdSIskren Chernev subsys_initcall(gcc_sm6115_init); 3535*cbe63bfdSIskren Chernev 3536*cbe63bfdSIskren Chernev static void __exit gcc_sm6115_exit(void) 3537*cbe63bfdSIskren Chernev { 3538*cbe63bfdSIskren Chernev platform_driver_unregister(&gcc_sm6115_driver); 3539*cbe63bfdSIskren Chernev } 3540*cbe63bfdSIskren Chernev module_exit(gcc_sm6115_exit); 3541*cbe63bfdSIskren Chernev 3542*cbe63bfdSIskren Chernev MODULE_DESCRIPTION("QTI GCC SM6115 and SM4250 Driver"); 3543*cbe63bfdSIskren Chernev MODULE_LICENSE("GPL v2"); 3544*cbe63bfdSIskren Chernev MODULE_ALIAS("platform:gcc-sm6115"); 3545