1cbe63bfdSIskren Chernev // SPDX-License-Identifier: GPL-2.0-only 2cbe63bfdSIskren Chernev /* 3cbe63bfdSIskren Chernev * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. 4cbe63bfdSIskren Chernev */ 5cbe63bfdSIskren Chernev 6cbe63bfdSIskren Chernev #include <linux/err.h> 7cbe63bfdSIskren Chernev #include <linux/kernel.h> 8cbe63bfdSIskren Chernev #include <linux/module.h> 9cbe63bfdSIskren Chernev #include <linux/of_device.h> 10cbe63bfdSIskren Chernev #include <linux/clk-provider.h> 11cbe63bfdSIskren Chernev #include <linux/regmap.h> 12cbe63bfdSIskren Chernev #include <linux/reset-controller.h> 13cbe63bfdSIskren Chernev 14cbe63bfdSIskren Chernev #include <dt-bindings/clock/qcom,gcc-sm6115.h> 15cbe63bfdSIskren Chernev 16cbe63bfdSIskren Chernev #include "clk-alpha-pll.h" 17cbe63bfdSIskren Chernev #include "clk-branch.h" 18cbe63bfdSIskren Chernev #include "clk-pll.h" 19cbe63bfdSIskren Chernev #include "clk-rcg.h" 20cbe63bfdSIskren Chernev #include "clk-regmap.h" 21cbe63bfdSIskren Chernev #include "clk-regmap-divider.h" 22cbe63bfdSIskren Chernev #include "common.h" 23cbe63bfdSIskren Chernev #include "gdsc.h" 24cbe63bfdSIskren Chernev #include "reset.h" 25cbe63bfdSIskren Chernev 26cbe63bfdSIskren Chernev enum { 27cbe63bfdSIskren Chernev P_BI_TCXO, 28cbe63bfdSIskren Chernev P_GPLL0_OUT_AUX2, 29cbe63bfdSIskren Chernev P_GPLL0_OUT_EARLY, 30cbe63bfdSIskren Chernev P_GPLL10_OUT_MAIN, 31cbe63bfdSIskren Chernev P_GPLL11_OUT_MAIN, 32cbe63bfdSIskren Chernev P_GPLL3_OUT_EARLY, 33cbe63bfdSIskren Chernev P_GPLL4_OUT_MAIN, 34cbe63bfdSIskren Chernev P_GPLL6_OUT_EARLY, 35cbe63bfdSIskren Chernev P_GPLL6_OUT_MAIN, 36cbe63bfdSIskren Chernev P_GPLL7_OUT_MAIN, 37cbe63bfdSIskren Chernev P_GPLL8_OUT_EARLY, 38cbe63bfdSIskren Chernev P_GPLL8_OUT_MAIN, 39cbe63bfdSIskren Chernev P_GPLL9_OUT_EARLY, 40cbe63bfdSIskren Chernev P_GPLL9_OUT_MAIN, 41cbe63bfdSIskren Chernev P_SLEEP_CLK, 42cbe63bfdSIskren Chernev }; 43cbe63bfdSIskren Chernev 44cbe63bfdSIskren Chernev static struct pll_vco default_vco[] = { 45cbe63bfdSIskren Chernev { 500000000, 1000000000, 2 }, 46cbe63bfdSIskren Chernev }; 47cbe63bfdSIskren Chernev 48cbe63bfdSIskren Chernev static struct pll_vco gpll9_vco[] = { 49cbe63bfdSIskren Chernev { 500000000, 1250000000, 0 }, 50cbe63bfdSIskren Chernev }; 51cbe63bfdSIskren Chernev 52cbe63bfdSIskren Chernev static struct pll_vco gpll10_vco[] = { 53cbe63bfdSIskren Chernev { 750000000, 1500000000, 1 }, 54cbe63bfdSIskren Chernev }; 55cbe63bfdSIskren Chernev 56cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll0 = { 57cbe63bfdSIskren Chernev .offset = 0x0, 58cbe63bfdSIskren Chernev .vco_table = default_vco, 59cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 609e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 61cbe63bfdSIskren Chernev .clkr = { 62cbe63bfdSIskren Chernev .enable_reg = 0x79000, 63cbe63bfdSIskren Chernev .enable_mask = BIT(0), 64cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 65cbe63bfdSIskren Chernev .name = "gpll0", 66cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 67cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 68cbe63bfdSIskren Chernev }, 69cbe63bfdSIskren Chernev .num_parents = 1, 70cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 71cbe63bfdSIskren Chernev }, 72cbe63bfdSIskren Chernev }, 73cbe63bfdSIskren Chernev }; 74cbe63bfdSIskren Chernev 75cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll0_out_aux2[] = { 76cbe63bfdSIskren Chernev { 0x1, 2 }, 77cbe63bfdSIskren Chernev { } 78cbe63bfdSIskren Chernev }; 79cbe63bfdSIskren Chernev 80cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll0_out_aux2 = { 81cbe63bfdSIskren Chernev .offset = 0x0, 82cbe63bfdSIskren Chernev .post_div_shift = 8, 83cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll0_out_aux2, 84cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2), 85cbe63bfdSIskren Chernev .width = 4, 869e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 87cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 88cbe63bfdSIskren Chernev .name = "gpll0_out_aux2", 89cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 90cbe63bfdSIskren Chernev .num_parents = 1, 91cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 92cbe63bfdSIskren Chernev }, 93cbe63bfdSIskren Chernev }; 94cbe63bfdSIskren Chernev 95cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll0_out_main[] = { 96cbe63bfdSIskren Chernev { 0x0, 1 }, 97cbe63bfdSIskren Chernev { } 98cbe63bfdSIskren Chernev }; 99cbe63bfdSIskren Chernev 100cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll0_out_main = { 101cbe63bfdSIskren Chernev .offset = 0x0, 102cbe63bfdSIskren Chernev .post_div_shift = 8, 103cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll0_out_main, 104cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_main), 105cbe63bfdSIskren Chernev .width = 4, 1069e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 107cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 108cbe63bfdSIskren Chernev .name = "gpll0_out_main", 109cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 110cbe63bfdSIskren Chernev .num_parents = 1, 111cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 112cbe63bfdSIskren Chernev }, 113cbe63bfdSIskren Chernev }; 114cbe63bfdSIskren Chernev 115cbe63bfdSIskren Chernev /* 1152MHz configuration */ 116cbe63bfdSIskren Chernev static const struct alpha_pll_config gpll10_config = { 117cbe63bfdSIskren Chernev .l = 0x3c, 118cbe63bfdSIskren Chernev .vco_val = 0x1 << 20, 119cbe63bfdSIskren Chernev .vco_mask = GENMASK(21, 20), 120cbe63bfdSIskren Chernev .main_output_mask = BIT(0), 121cbe63bfdSIskren Chernev .config_ctl_val = 0x4001055b, 122cbe63bfdSIskren Chernev }; 123cbe63bfdSIskren Chernev 124cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll10 = { 125cbe63bfdSIskren Chernev .offset = 0xa000, 126cbe63bfdSIskren Chernev .vco_table = gpll10_vco, 127cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(gpll10_vco), 1289e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 129cbe63bfdSIskren Chernev .clkr = { 130cbe63bfdSIskren Chernev .enable_reg = 0x79000, 131cbe63bfdSIskren Chernev .enable_mask = BIT(10), 132cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 133cbe63bfdSIskren Chernev .name = "gpll10", 134cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 135cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 136cbe63bfdSIskren Chernev }, 137cbe63bfdSIskren Chernev .num_parents = 1, 138cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 139cbe63bfdSIskren Chernev }, 140cbe63bfdSIskren Chernev }, 141cbe63bfdSIskren Chernev }; 142cbe63bfdSIskren Chernev 143cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll10_out_main[] = { 144cbe63bfdSIskren Chernev { 0x0, 1 }, 145cbe63bfdSIskren Chernev { } 146cbe63bfdSIskren Chernev }; 147cbe63bfdSIskren Chernev 148cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll10_out_main = { 149cbe63bfdSIskren Chernev .offset = 0xa000, 150cbe63bfdSIskren Chernev .post_div_shift = 8, 151cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll10_out_main, 152cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll10_out_main), 153cbe63bfdSIskren Chernev .width = 4, 1549e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 155cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 156cbe63bfdSIskren Chernev .name = "gpll10_out_main", 157cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll10.clkr.hw }, 158cbe63bfdSIskren Chernev .num_parents = 1, 159cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 160cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ops, 161cbe63bfdSIskren Chernev }, 162cbe63bfdSIskren Chernev }; 163cbe63bfdSIskren Chernev 164cbe63bfdSIskren Chernev /* 600MHz configuration */ 165cbe63bfdSIskren Chernev static const struct alpha_pll_config gpll11_config = { 166cbe63bfdSIskren Chernev .l = 0x1F, 167cbe63bfdSIskren Chernev .alpha = 0x0, 168cbe63bfdSIskren Chernev .alpha_hi = 0x40, 169cbe63bfdSIskren Chernev .alpha_en_mask = BIT(24), 170cbe63bfdSIskren Chernev .vco_val = 0x2 << 20, 171cbe63bfdSIskren Chernev .vco_mask = GENMASK(21, 20), 172cbe63bfdSIskren Chernev .config_ctl_val = 0x4001055b, 173cbe63bfdSIskren Chernev }; 174cbe63bfdSIskren Chernev 175cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll11 = { 176cbe63bfdSIskren Chernev .offset = 0xb000, 177cbe63bfdSIskren Chernev .vco_table = default_vco, 178cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 179cbe63bfdSIskren Chernev .flags = SUPPORTS_DYNAMIC_UPDATE, 1809e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 181cbe63bfdSIskren Chernev .clkr = { 182cbe63bfdSIskren Chernev .enable_reg = 0x79000, 183cbe63bfdSIskren Chernev .enable_mask = BIT(11), 184cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 185cbe63bfdSIskren Chernev .name = "gpll11", 186cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 187cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 188cbe63bfdSIskren Chernev }, 189cbe63bfdSIskren Chernev .num_parents = 1, 190cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 191cbe63bfdSIskren Chernev }, 192cbe63bfdSIskren Chernev }, 193cbe63bfdSIskren Chernev }; 194cbe63bfdSIskren Chernev 195cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll11_out_main[] = { 196cbe63bfdSIskren Chernev { 0x0, 1 }, 197cbe63bfdSIskren Chernev { } 198cbe63bfdSIskren Chernev }; 199cbe63bfdSIskren Chernev 200cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll11_out_main = { 201cbe63bfdSIskren Chernev .offset = 0xb000, 202cbe63bfdSIskren Chernev .post_div_shift = 8, 203cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll11_out_main, 204cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll11_out_main), 205cbe63bfdSIskren Chernev .width = 4, 2069e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 207cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 208cbe63bfdSIskren Chernev .name = "gpll11_out_main", 209cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll11.clkr.hw }, 210cbe63bfdSIskren Chernev .num_parents = 1, 211cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 212cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ops, 213cbe63bfdSIskren Chernev }, 214cbe63bfdSIskren Chernev }; 215cbe63bfdSIskren Chernev 216cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll3 = { 217cbe63bfdSIskren Chernev .offset = 0x3000, 218cbe63bfdSIskren Chernev .vco_table = default_vco, 219cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 2209e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 221cbe63bfdSIskren Chernev .clkr = { 222cbe63bfdSIskren Chernev .enable_reg = 0x79000, 223cbe63bfdSIskren Chernev .enable_mask = BIT(3), 224cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 225cbe63bfdSIskren Chernev .name = "gpll3", 226cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 227cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 228cbe63bfdSIskren Chernev }, 229cbe63bfdSIskren Chernev .num_parents = 1, 230cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 231cbe63bfdSIskren Chernev }, 232cbe63bfdSIskren Chernev }, 233cbe63bfdSIskren Chernev }; 234cbe63bfdSIskren Chernev 235cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll4 = { 236cbe63bfdSIskren Chernev .offset = 0x4000, 237cbe63bfdSIskren Chernev .vco_table = default_vco, 238cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 2399e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 240cbe63bfdSIskren Chernev .clkr = { 241cbe63bfdSIskren Chernev .enable_reg = 0x79000, 242cbe63bfdSIskren Chernev .enable_mask = BIT(4), 243cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 244cbe63bfdSIskren Chernev .name = "gpll4", 245cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 246cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 247cbe63bfdSIskren Chernev }, 248cbe63bfdSIskren Chernev .num_parents = 1, 249cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 250cbe63bfdSIskren Chernev }, 251cbe63bfdSIskren Chernev }, 252cbe63bfdSIskren Chernev }; 253cbe63bfdSIskren Chernev 254cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll4_out_main[] = { 255cbe63bfdSIskren Chernev { 0x0, 1 }, 256cbe63bfdSIskren Chernev { } 257cbe63bfdSIskren Chernev }; 258cbe63bfdSIskren Chernev 259cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll4_out_main = { 260cbe63bfdSIskren Chernev .offset = 0x4000, 261cbe63bfdSIskren Chernev .post_div_shift = 8, 262cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll4_out_main, 263cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll4_out_main), 264cbe63bfdSIskren Chernev .width = 4, 2659e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 266cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 267cbe63bfdSIskren Chernev .name = "gpll4_out_main", 268cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll4.clkr.hw }, 269cbe63bfdSIskren Chernev .num_parents = 1, 270cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 271cbe63bfdSIskren Chernev }, 272cbe63bfdSIskren Chernev }; 273cbe63bfdSIskren Chernev 274cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll6 = { 275cbe63bfdSIskren Chernev .offset = 0x6000, 276cbe63bfdSIskren Chernev .vco_table = default_vco, 277cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 2789e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 279cbe63bfdSIskren Chernev .clkr = { 280cbe63bfdSIskren Chernev .enable_reg = 0x79000, 281cbe63bfdSIskren Chernev .enable_mask = BIT(6), 282cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 283cbe63bfdSIskren Chernev .name = "gpll6", 284cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 285cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 286cbe63bfdSIskren Chernev }, 287cbe63bfdSIskren Chernev .num_parents = 1, 288cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 289cbe63bfdSIskren Chernev }, 290cbe63bfdSIskren Chernev }, 291cbe63bfdSIskren Chernev }; 292cbe63bfdSIskren Chernev 293cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll6_out_main[] = { 294cbe63bfdSIskren Chernev { 0x1, 2 }, 295cbe63bfdSIskren Chernev { } 296cbe63bfdSIskren Chernev }; 297cbe63bfdSIskren Chernev 298cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll6_out_main = { 299cbe63bfdSIskren Chernev .offset = 0x6000, 300cbe63bfdSIskren Chernev .post_div_shift = 8, 301cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll6_out_main, 302cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main), 303cbe63bfdSIskren Chernev .width = 4, 3049e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 305cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 306cbe63bfdSIskren Chernev .name = "gpll6_out_main", 307cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw }, 308cbe63bfdSIskren Chernev .num_parents = 1, 309cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 310cbe63bfdSIskren Chernev }, 311cbe63bfdSIskren Chernev }; 312cbe63bfdSIskren Chernev 313cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll7 = { 314cbe63bfdSIskren Chernev .offset = 0x7000, 315cbe63bfdSIskren Chernev .vco_table = default_vco, 316cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 3179e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 318cbe63bfdSIskren Chernev .clkr = { 319cbe63bfdSIskren Chernev .enable_reg = 0x79000, 320cbe63bfdSIskren Chernev .enable_mask = BIT(7), 321cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 322cbe63bfdSIskren Chernev .name = "gpll7", 323cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 324cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 325cbe63bfdSIskren Chernev }, 326cbe63bfdSIskren Chernev .num_parents = 1, 327cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 328cbe63bfdSIskren Chernev }, 329cbe63bfdSIskren Chernev }, 330cbe63bfdSIskren Chernev }; 331cbe63bfdSIskren Chernev 332cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll7_out_main[] = { 333cbe63bfdSIskren Chernev { 0x0, 1 }, 334cbe63bfdSIskren Chernev { } 335cbe63bfdSIskren Chernev }; 336cbe63bfdSIskren Chernev 337cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll7_out_main = { 338cbe63bfdSIskren Chernev .offset = 0x7000, 339cbe63bfdSIskren Chernev .post_div_shift = 8, 340cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll7_out_main, 341cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll7_out_main), 342cbe63bfdSIskren Chernev .width = 4, 3439e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 344cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 345cbe63bfdSIskren Chernev .name = "gpll7_out_main", 346cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll7.clkr.hw }, 347cbe63bfdSIskren Chernev .num_parents = 1, 348cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 349cbe63bfdSIskren Chernev }, 350cbe63bfdSIskren Chernev }; 351cbe63bfdSIskren Chernev 352cbe63bfdSIskren Chernev /* 800MHz configuration */ 353cbe63bfdSIskren Chernev static const struct alpha_pll_config gpll8_config = { 354cbe63bfdSIskren Chernev .l = 0x29, 355cbe63bfdSIskren Chernev .alpha = 0xAAAAAAAA, 356cbe63bfdSIskren Chernev .alpha_hi = 0xAA, 357cbe63bfdSIskren Chernev .alpha_en_mask = BIT(24), 358cbe63bfdSIskren Chernev .vco_val = 0x2 << 20, 359cbe63bfdSIskren Chernev .vco_mask = GENMASK(21, 20), 360cbe63bfdSIskren Chernev .main_output_mask = BIT(0), 361cbe63bfdSIskren Chernev .early_output_mask = BIT(3), 362cbe63bfdSIskren Chernev .post_div_val = 0x1 << 8, 363cbe63bfdSIskren Chernev .post_div_mask = GENMASK(11, 8), 364cbe63bfdSIskren Chernev .config_ctl_val = 0x4001055b, 365cbe63bfdSIskren Chernev }; 366cbe63bfdSIskren Chernev 367cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll8 = { 368cbe63bfdSIskren Chernev .offset = 0x8000, 369cbe63bfdSIskren Chernev .vco_table = default_vco, 370cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(default_vco), 3719e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 372cbe63bfdSIskren Chernev .flags = SUPPORTS_DYNAMIC_UPDATE, 373cbe63bfdSIskren Chernev .clkr = { 374cbe63bfdSIskren Chernev .enable_reg = 0x79000, 375cbe63bfdSIskren Chernev .enable_mask = BIT(8), 376cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 377cbe63bfdSIskren Chernev .name = "gpll8", 378cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 379cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 380cbe63bfdSIskren Chernev }, 381cbe63bfdSIskren Chernev .num_parents = 1, 382cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 383cbe63bfdSIskren Chernev }, 384cbe63bfdSIskren Chernev }, 385cbe63bfdSIskren Chernev }; 386cbe63bfdSIskren Chernev 387cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll8_out_main[] = { 388cbe63bfdSIskren Chernev { 0x1, 2 }, 389cbe63bfdSIskren Chernev { } 390cbe63bfdSIskren Chernev }; 391cbe63bfdSIskren Chernev 392cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll8_out_main = { 393cbe63bfdSIskren Chernev .offset = 0x8000, 394cbe63bfdSIskren Chernev .post_div_shift = 8, 395cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll8_out_main, 396cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main), 397cbe63bfdSIskren Chernev .width = 4, 3989e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 399cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 400cbe63bfdSIskren Chernev .name = "gpll8_out_main", 401cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw }, 402cbe63bfdSIskren Chernev .num_parents = 1, 403cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 404cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ro_ops, 405cbe63bfdSIskren Chernev }, 406cbe63bfdSIskren Chernev }; 407cbe63bfdSIskren Chernev 408cbe63bfdSIskren Chernev /* 1152MHz configuration */ 409cbe63bfdSIskren Chernev static const struct alpha_pll_config gpll9_config = { 410cbe63bfdSIskren Chernev .l = 0x3C, 411cbe63bfdSIskren Chernev .alpha = 0x0, 412cbe63bfdSIskren Chernev .post_div_val = 0x1 << 8, 413cbe63bfdSIskren Chernev .post_div_mask = GENMASK(9, 8), 414cbe63bfdSIskren Chernev .main_output_mask = BIT(0), 415cbe63bfdSIskren Chernev .config_ctl_val = 0x00004289, 416cbe63bfdSIskren Chernev }; 417cbe63bfdSIskren Chernev 418cbe63bfdSIskren Chernev static struct clk_alpha_pll gpll9 = { 419cbe63bfdSIskren Chernev .offset = 0x9000, 420cbe63bfdSIskren Chernev .vco_table = gpll9_vco, 421cbe63bfdSIskren Chernev .num_vco = ARRAY_SIZE(gpll9_vco), 4229e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO], 423cbe63bfdSIskren Chernev .clkr = { 424cbe63bfdSIskren Chernev .enable_reg = 0x79000, 425cbe63bfdSIskren Chernev .enable_mask = BIT(9), 426cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 427cbe63bfdSIskren Chernev .name = "gpll9", 428cbe63bfdSIskren Chernev .parent_data = &(const struct clk_parent_data){ 429cbe63bfdSIskren Chernev .fw_name = "bi_tcxo", 430cbe63bfdSIskren Chernev }, 431cbe63bfdSIskren Chernev .num_parents = 1, 432cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_ops, 433cbe63bfdSIskren Chernev }, 434cbe63bfdSIskren Chernev }, 435cbe63bfdSIskren Chernev }; 436cbe63bfdSIskren Chernev 437cbe63bfdSIskren Chernev static const struct clk_div_table post_div_table_gpll9_out_main[] = { 438cbe63bfdSIskren Chernev { 0x1, 2 }, 439cbe63bfdSIskren Chernev { } 440cbe63bfdSIskren Chernev }; 441cbe63bfdSIskren Chernev 442cbe63bfdSIskren Chernev static struct clk_alpha_pll_postdiv gpll9_out_main = { 443cbe63bfdSIskren Chernev .offset = 0x9000, 444cbe63bfdSIskren Chernev .post_div_shift = 8, 445cbe63bfdSIskren Chernev .post_div_table = post_div_table_gpll9_out_main, 446cbe63bfdSIskren Chernev .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main), 447cbe63bfdSIskren Chernev .width = 2, 4489e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO], 449cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 450cbe63bfdSIskren Chernev .name = "gpll9_out_main", 451cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw }, 452cbe63bfdSIskren Chernev .num_parents = 1, 453cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 454cbe63bfdSIskren Chernev .ops = &clk_alpha_pll_postdiv_ops, 455cbe63bfdSIskren Chernev }, 456cbe63bfdSIskren Chernev }; 457cbe63bfdSIskren Chernev 458cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_0[] = { 459cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 460cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 461cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 462cbe63bfdSIskren Chernev }; 463cbe63bfdSIskren Chernev 464cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_0[] = { 465cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 466cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 467cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 468cbe63bfdSIskren Chernev }; 469cbe63bfdSIskren Chernev 470cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_1[] = { 471cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 472cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 473cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 474cbe63bfdSIskren Chernev { P_GPLL6_OUT_MAIN, 4 }, 475cbe63bfdSIskren Chernev }; 476cbe63bfdSIskren Chernev 477cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_1[] = { 478cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 479cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 480cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 481cbe63bfdSIskren Chernev { .hw = &gpll6_out_main.clkr.hw }, 482cbe63bfdSIskren Chernev }; 483cbe63bfdSIskren Chernev 484cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_2[] = { 485cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 486cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 487cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 488cbe63bfdSIskren Chernev { P_SLEEP_CLK, 5 }, 489cbe63bfdSIskren Chernev }; 490cbe63bfdSIskren Chernev 491cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_2[] = { 492cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 493cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 494cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 495cbe63bfdSIskren Chernev { .fw_name = "sleep_clk" }, 496cbe63bfdSIskren Chernev }; 497cbe63bfdSIskren Chernev 498cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_3[] = { 499cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 500cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 501cbe63bfdSIskren Chernev { P_GPLL9_OUT_EARLY, 2 }, 502cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 503cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 504cbe63bfdSIskren Chernev }; 505cbe63bfdSIskren Chernev 506cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_3[] = { 507cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 508cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 509cbe63bfdSIskren Chernev { .hw = &gpll9.clkr.hw }, 510cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 511cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 512cbe63bfdSIskren Chernev }; 513cbe63bfdSIskren Chernev 514cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_4[] = { 515cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 516cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 517cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 518cbe63bfdSIskren Chernev { P_GPLL4_OUT_MAIN, 5 }, 519cbe63bfdSIskren Chernev }; 520cbe63bfdSIskren Chernev 521cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_4[] = { 522cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 523cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 524cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 525cbe63bfdSIskren Chernev { .hw = &gpll4_out_main.clkr.hw }, 526cbe63bfdSIskren Chernev }; 527cbe63bfdSIskren Chernev 528cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_5[] = { 529cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 530cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 531cbe63bfdSIskren Chernev { P_GPLL8_OUT_EARLY, 2 }, 532cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 533cbe63bfdSIskren Chernev { P_GPLL8_OUT_MAIN, 4 }, 534cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 535cbe63bfdSIskren Chernev }; 536cbe63bfdSIskren Chernev 537cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_5[] = { 538cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 539cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 540cbe63bfdSIskren Chernev { .hw = &gpll8.clkr.hw }, 541cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 542cbe63bfdSIskren Chernev { .hw = &gpll8_out_main.clkr.hw }, 543cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 544cbe63bfdSIskren Chernev }; 545cbe63bfdSIskren Chernev 546cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_6[] = { 547cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 548cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 549cbe63bfdSIskren Chernev { P_GPLL8_OUT_EARLY, 2 }, 550cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 551cbe63bfdSIskren Chernev { P_GPLL6_OUT_MAIN, 4 }, 552cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 553cbe63bfdSIskren Chernev { P_GPLL3_OUT_EARLY, 6 }, 554cbe63bfdSIskren Chernev }; 555cbe63bfdSIskren Chernev 556cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_6[] = { 557cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 558cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 559cbe63bfdSIskren Chernev { .hw = &gpll8.clkr.hw }, 560cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 561cbe63bfdSIskren Chernev { .hw = &gpll6_out_main.clkr.hw }, 562cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 563cbe63bfdSIskren Chernev { .hw = &gpll3.clkr.hw }, 564cbe63bfdSIskren Chernev }; 565cbe63bfdSIskren Chernev 566cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_7[] = { 567cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 568cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 569cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 570cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 571cbe63bfdSIskren Chernev { P_GPLL4_OUT_MAIN, 5 }, 572cbe63bfdSIskren Chernev { P_GPLL3_OUT_EARLY, 6 }, 573cbe63bfdSIskren Chernev }; 574cbe63bfdSIskren Chernev 575cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_7[] = { 576cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 577cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 578cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 579cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 580cbe63bfdSIskren Chernev { .hw = &gpll4_out_main.clkr.hw }, 581cbe63bfdSIskren Chernev { .hw = &gpll3.clkr.hw }, 582cbe63bfdSIskren Chernev }; 583cbe63bfdSIskren Chernev 584cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_8[] = { 585cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 586cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 587cbe63bfdSIskren Chernev { P_GPLL8_OUT_EARLY, 2 }, 588cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 589cbe63bfdSIskren Chernev { P_GPLL8_OUT_MAIN, 4 }, 590cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 591cbe63bfdSIskren Chernev { P_GPLL3_OUT_EARLY, 6 }, 592cbe63bfdSIskren Chernev }; 593cbe63bfdSIskren Chernev 594cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_8[] = { 595cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 596cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 597cbe63bfdSIskren Chernev { .hw = &gpll8.clkr.hw }, 598cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 599cbe63bfdSIskren Chernev { .hw = &gpll8_out_main.clkr.hw }, 600cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 601cbe63bfdSIskren Chernev { .hw = &gpll3.clkr.hw }, 602cbe63bfdSIskren Chernev }; 603cbe63bfdSIskren Chernev 604cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_9[] = { 605cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 606cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 607cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 608cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 609cbe63bfdSIskren Chernev { P_GPLL8_OUT_MAIN, 4 }, 610cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 611cbe63bfdSIskren Chernev { P_GPLL3_OUT_EARLY, 6 }, 612cbe63bfdSIskren Chernev }; 613cbe63bfdSIskren Chernev 614cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_9[] = { 615cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 616cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 617cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 618cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 619cbe63bfdSIskren Chernev { .hw = &gpll8_out_main.clkr.hw }, 620cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 621cbe63bfdSIskren Chernev { .hw = &gpll3.clkr.hw }, 622cbe63bfdSIskren Chernev }; 623cbe63bfdSIskren Chernev 624cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_10[] = { 625cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 626cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 627cbe63bfdSIskren Chernev { P_GPLL8_OUT_EARLY, 2 }, 628cbe63bfdSIskren Chernev { P_GPLL10_OUT_MAIN, 3 }, 629cbe63bfdSIskren Chernev { P_GPLL6_OUT_EARLY, 4 }, 630cbe63bfdSIskren Chernev { P_GPLL9_OUT_MAIN, 5 }, 631cbe63bfdSIskren Chernev }; 632cbe63bfdSIskren Chernev 633cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_10[] = { 634cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 635cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 636cbe63bfdSIskren Chernev { .hw = &gpll8.clkr.hw }, 637cbe63bfdSIskren Chernev { .hw = &gpll10_out_main.clkr.hw }, 638cbe63bfdSIskren Chernev { .hw = &gpll6.clkr.hw }, 639cbe63bfdSIskren Chernev { .hw = &gpll9_out_main.clkr.hw }, 640cbe63bfdSIskren Chernev }; 641cbe63bfdSIskren Chernev 642cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_11[] = { 643cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 644cbe63bfdSIskren Chernev { P_GPLL0_OUT_EARLY, 1 }, 645cbe63bfdSIskren Chernev { P_GPLL0_OUT_AUX2, 2 }, 646cbe63bfdSIskren Chernev { P_GPLL7_OUT_MAIN, 3 }, 647cbe63bfdSIskren Chernev { P_GPLL4_OUT_MAIN, 5 }, 648cbe63bfdSIskren Chernev }; 649cbe63bfdSIskren Chernev 650cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_11[] = { 651cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 652cbe63bfdSIskren Chernev { .hw = &gpll0.clkr.hw }, 653cbe63bfdSIskren Chernev { .hw = &gpll0_out_aux2.clkr.hw }, 654cbe63bfdSIskren Chernev { .hw = &gpll7_out_main.clkr.hw }, 655cbe63bfdSIskren Chernev { .hw = &gpll4_out_main.clkr.hw }, 656cbe63bfdSIskren Chernev }; 657cbe63bfdSIskren Chernev 658cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_12[] = { 659cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 660cbe63bfdSIskren Chernev { P_SLEEP_CLK, 5 }, 661cbe63bfdSIskren Chernev }; 662cbe63bfdSIskren Chernev 663cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_12[] = { 664cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 665cbe63bfdSIskren Chernev { .fw_name = "sleep_clk" }, 666cbe63bfdSIskren Chernev }; 667cbe63bfdSIskren Chernev 668cbe63bfdSIskren Chernev static const struct parent_map gcc_parent_map_13[] = { 669cbe63bfdSIskren Chernev { P_BI_TCXO, 0 }, 670cbe63bfdSIskren Chernev { P_GPLL11_OUT_MAIN, 1 }, 671cbe63bfdSIskren Chernev }; 672cbe63bfdSIskren Chernev 673cbe63bfdSIskren Chernev static const struct clk_parent_data gcc_parents_13[] = { 674cbe63bfdSIskren Chernev { .fw_name = "bi_tcxo" }, 675cbe63bfdSIskren Chernev { .hw = &gpll11_out_main.clkr.hw }, 676cbe63bfdSIskren Chernev }; 677cbe63bfdSIskren Chernev 678cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = { 679cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 680cbe63bfdSIskren Chernev F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 681cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 682cbe63bfdSIskren Chernev F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 683cbe63bfdSIskren Chernev { } 684cbe63bfdSIskren Chernev }; 685cbe63bfdSIskren Chernev 686cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_axi_clk_src = { 687cbe63bfdSIskren Chernev .cmd_rcgr = 0x5802c, 688cbe63bfdSIskren Chernev .mnd_width = 0, 689cbe63bfdSIskren Chernev .hid_width = 5, 690cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_7, 691cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_axi_clk_src, 692cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 693cbe63bfdSIskren Chernev .name = "gcc_camss_axi_clk_src", 694cbe63bfdSIskren Chernev .parent_data = gcc_parents_7, 695cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_7), 696cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 697*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 698cbe63bfdSIskren Chernev }, 699cbe63bfdSIskren Chernev }; 700cbe63bfdSIskren Chernev 701cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = { 702cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 703cbe63bfdSIskren Chernev F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 704cbe63bfdSIskren Chernev { } 705cbe63bfdSIskren Chernev }; 706cbe63bfdSIskren Chernev 707cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_cci_clk_src = { 708cbe63bfdSIskren Chernev .cmd_rcgr = 0x56000, 709cbe63bfdSIskren Chernev .mnd_width = 0, 710cbe63bfdSIskren Chernev .hid_width = 5, 711cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_9, 712cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_cci_clk_src, 713cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 714cbe63bfdSIskren Chernev .name = "gcc_camss_cci_clk_src", 715cbe63bfdSIskren Chernev .parent_data = gcc_parents_9, 716cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_9), 717cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 718*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 719cbe63bfdSIskren Chernev }, 720cbe63bfdSIskren Chernev }; 721cbe63bfdSIskren Chernev 722cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = { 723cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 724cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 725cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 726cbe63bfdSIskren Chernev F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0), 727cbe63bfdSIskren Chernev { } 728cbe63bfdSIskren Chernev }; 729cbe63bfdSIskren Chernev 730cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { 731cbe63bfdSIskren Chernev .cmd_rcgr = 0x59000, 732cbe63bfdSIskren Chernev .mnd_width = 0, 733cbe63bfdSIskren Chernev .hid_width = 5, 734cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_4, 735cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 736cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 737cbe63bfdSIskren Chernev .name = "gcc_camss_csi0phytimer_clk_src", 738cbe63bfdSIskren Chernev .parent_data = gcc_parents_4, 739cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_4), 740cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 741*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 742cbe63bfdSIskren Chernev }, 743cbe63bfdSIskren Chernev }; 744cbe63bfdSIskren Chernev 745cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { 746cbe63bfdSIskren Chernev .cmd_rcgr = 0x5901c, 747cbe63bfdSIskren Chernev .mnd_width = 0, 748cbe63bfdSIskren Chernev .hid_width = 5, 749cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_4, 750cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 751cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 752cbe63bfdSIskren Chernev .name = "gcc_camss_csi1phytimer_clk_src", 753cbe63bfdSIskren Chernev .parent_data = gcc_parents_4, 754cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_4), 755cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 756*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 757cbe63bfdSIskren Chernev }, 758cbe63bfdSIskren Chernev }; 759cbe63bfdSIskren Chernev 760cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = { 761cbe63bfdSIskren Chernev .cmd_rcgr = 0x59038, 762cbe63bfdSIskren Chernev .mnd_width = 0, 763cbe63bfdSIskren Chernev .hid_width = 5, 764cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_4, 765cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 766cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 767cbe63bfdSIskren Chernev .name = "gcc_camss_csi2phytimer_clk_src", 768cbe63bfdSIskren Chernev .parent_data = gcc_parents_4, 769cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_4), 770cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 771*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 772cbe63bfdSIskren Chernev }, 773cbe63bfdSIskren Chernev }; 774cbe63bfdSIskren Chernev 775cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { 776cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 777cbe63bfdSIskren Chernev F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24), 778cbe63bfdSIskren Chernev F(64000000, P_GPLL9_OUT_MAIN, 1, 1, 9), 779cbe63bfdSIskren Chernev { } 780cbe63bfdSIskren Chernev }; 781cbe63bfdSIskren Chernev 782cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_mclk0_clk_src = { 783cbe63bfdSIskren Chernev .cmd_rcgr = 0x51000, 784cbe63bfdSIskren Chernev .mnd_width = 8, 785cbe63bfdSIskren Chernev .hid_width = 5, 786cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_3, 787cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 788cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 789cbe63bfdSIskren Chernev .name = "gcc_camss_mclk0_clk_src", 790cbe63bfdSIskren Chernev .parent_data = gcc_parents_3, 791cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_3), 792cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 793*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 794cbe63bfdSIskren Chernev }, 795cbe63bfdSIskren Chernev }; 796cbe63bfdSIskren Chernev 797cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_mclk1_clk_src = { 798cbe63bfdSIskren Chernev .cmd_rcgr = 0x5101c, 799cbe63bfdSIskren Chernev .mnd_width = 8, 800cbe63bfdSIskren Chernev .hid_width = 5, 801cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_3, 802cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 803cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 804cbe63bfdSIskren Chernev .name = "gcc_camss_mclk1_clk_src", 805cbe63bfdSIskren Chernev .parent_data = gcc_parents_3, 806cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_3), 807cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 808*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 809cbe63bfdSIskren Chernev }, 810cbe63bfdSIskren Chernev }; 811cbe63bfdSIskren Chernev 812cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_mclk2_clk_src = { 813cbe63bfdSIskren Chernev .cmd_rcgr = 0x51038, 814cbe63bfdSIskren Chernev .mnd_width = 8, 815cbe63bfdSIskren Chernev .hid_width = 5, 816cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_3, 817cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 818cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 819cbe63bfdSIskren Chernev .name = "gcc_camss_mclk2_clk_src", 820cbe63bfdSIskren Chernev .parent_data = gcc_parents_3, 821cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_3), 822cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 823*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 824cbe63bfdSIskren Chernev }, 825cbe63bfdSIskren Chernev }; 826cbe63bfdSIskren Chernev 827cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_mclk3_clk_src = { 828cbe63bfdSIskren Chernev .cmd_rcgr = 0x51054, 829cbe63bfdSIskren Chernev .mnd_width = 8, 830cbe63bfdSIskren Chernev .hid_width = 5, 831cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_3, 832cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 833cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 834cbe63bfdSIskren Chernev .name = "gcc_camss_mclk3_clk_src", 835cbe63bfdSIskren Chernev .parent_data = gcc_parents_3, 836cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_3), 837cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 838*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 839cbe63bfdSIskren Chernev }, 840cbe63bfdSIskren Chernev }; 841cbe63bfdSIskren Chernev 842cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = { 843cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 844cbe63bfdSIskren Chernev F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0), 845cbe63bfdSIskren Chernev F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 846cbe63bfdSIskren Chernev { } 847cbe63bfdSIskren Chernev }; 848cbe63bfdSIskren Chernev 849cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = { 850cbe63bfdSIskren Chernev .cmd_rcgr = 0x55024, 851cbe63bfdSIskren Chernev .mnd_width = 0, 852cbe63bfdSIskren Chernev .hid_width = 5, 853cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_8, 854cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src, 855cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 856cbe63bfdSIskren Chernev .name = "gcc_camss_ope_ahb_clk_src", 857cbe63bfdSIskren Chernev .parent_data = gcc_parents_8, 858cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_8), 859cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 860*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 861cbe63bfdSIskren Chernev }, 862cbe63bfdSIskren Chernev }; 863cbe63bfdSIskren Chernev 864cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = { 865cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 866cbe63bfdSIskren Chernev F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0), 867cbe63bfdSIskren Chernev F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0), 868cbe63bfdSIskren Chernev F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0), 869cbe63bfdSIskren Chernev F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0), 870cbe63bfdSIskren Chernev { } 871cbe63bfdSIskren Chernev }; 872cbe63bfdSIskren Chernev 873cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_ope_clk_src = { 874cbe63bfdSIskren Chernev .cmd_rcgr = 0x55004, 875cbe63bfdSIskren Chernev .mnd_width = 0, 876cbe63bfdSIskren Chernev .hid_width = 5, 877cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_8, 878cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_ope_clk_src, 879cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 880cbe63bfdSIskren Chernev .name = "gcc_camss_ope_clk_src", 881cbe63bfdSIskren Chernev .parent_data = gcc_parents_8, 882cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_8), 883cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 884*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 885cbe63bfdSIskren Chernev }, 886cbe63bfdSIskren Chernev }; 887cbe63bfdSIskren Chernev 888cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = { 889cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 890cbe63bfdSIskren Chernev F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0), 891cbe63bfdSIskren Chernev F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0), 892cbe63bfdSIskren Chernev F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0), 893cbe63bfdSIskren Chernev F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0), 894cbe63bfdSIskren Chernev F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0), 895cbe63bfdSIskren Chernev F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0), 896cbe63bfdSIskren Chernev F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0), 897cbe63bfdSIskren Chernev F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0), 898cbe63bfdSIskren Chernev F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0), 899cbe63bfdSIskren Chernev F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0), 900cbe63bfdSIskren Chernev F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0), 901cbe63bfdSIskren Chernev F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0), 902cbe63bfdSIskren Chernev F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0), 903cbe63bfdSIskren Chernev F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0), 904cbe63bfdSIskren Chernev F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0), 905cbe63bfdSIskren Chernev { } 906cbe63bfdSIskren Chernev }; 907cbe63bfdSIskren Chernev 908cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_0_clk_src = { 909cbe63bfdSIskren Chernev .cmd_rcgr = 0x52004, 910cbe63bfdSIskren Chernev .mnd_width = 8, 911cbe63bfdSIskren Chernev .hid_width = 5, 912cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_5, 913cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 914cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 915cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_0_clk_src", 916cbe63bfdSIskren Chernev .parent_data = gcc_parents_5, 917cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_5), 918cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 919*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 920cbe63bfdSIskren Chernev }, 921cbe63bfdSIskren Chernev }; 922cbe63bfdSIskren Chernev 923cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = { 924cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 925cbe63bfdSIskren Chernev F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0), 926cbe63bfdSIskren Chernev F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 927cbe63bfdSIskren Chernev F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 928cbe63bfdSIskren Chernev F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 929cbe63bfdSIskren Chernev F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0), 930cbe63bfdSIskren Chernev { } 931cbe63bfdSIskren Chernev }; 932cbe63bfdSIskren Chernev 933cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = { 934cbe63bfdSIskren Chernev .cmd_rcgr = 0x52094, 935cbe63bfdSIskren Chernev .mnd_width = 0, 936cbe63bfdSIskren Chernev .hid_width = 5, 937cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_6, 938cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 939cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 940cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_0_csid_clk_src", 941cbe63bfdSIskren Chernev .parent_data = gcc_parents_6, 942cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_6), 943cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 944*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 945cbe63bfdSIskren Chernev }, 946cbe63bfdSIskren Chernev }; 947cbe63bfdSIskren Chernev 948cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_1_clk_src = { 949cbe63bfdSIskren Chernev .cmd_rcgr = 0x52024, 950cbe63bfdSIskren Chernev .mnd_width = 8, 951cbe63bfdSIskren Chernev .hid_width = 5, 952cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_5, 953cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 954cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 955cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_1_clk_src", 956cbe63bfdSIskren Chernev .parent_data = gcc_parents_5, 957cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_5), 958cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 959*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 960cbe63bfdSIskren Chernev }, 961cbe63bfdSIskren Chernev }; 962cbe63bfdSIskren Chernev 963cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = { 964cbe63bfdSIskren Chernev .cmd_rcgr = 0x520b4, 965cbe63bfdSIskren Chernev .mnd_width = 0, 966cbe63bfdSIskren Chernev .hid_width = 5, 967cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_6, 968cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 969cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 970cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_1_csid_clk_src", 971cbe63bfdSIskren Chernev .parent_data = gcc_parents_6, 972cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_6), 973cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 974*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 975cbe63bfdSIskren Chernev }, 976cbe63bfdSIskren Chernev }; 977cbe63bfdSIskren Chernev 978cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_2_clk_src = { 979cbe63bfdSIskren Chernev .cmd_rcgr = 0x52044, 980cbe63bfdSIskren Chernev .mnd_width = 8, 981cbe63bfdSIskren Chernev .hid_width = 5, 982cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_5, 983cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 984cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 985cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_2_clk_src", 986cbe63bfdSIskren Chernev .parent_data = gcc_parents_5, 987cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_5), 988cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 989*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 990cbe63bfdSIskren Chernev }, 991cbe63bfdSIskren Chernev }; 992cbe63bfdSIskren Chernev 993cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_2_csid_clk_src = { 994cbe63bfdSIskren Chernev .cmd_rcgr = 0x520d4, 995cbe63bfdSIskren Chernev .mnd_width = 0, 996cbe63bfdSIskren Chernev .hid_width = 5, 997cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_6, 998cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 999cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1000cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_2_csid_clk_src", 1001cbe63bfdSIskren Chernev .parent_data = gcc_parents_6, 1002cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_6), 1003cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1004*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1005cbe63bfdSIskren Chernev }, 1006cbe63bfdSIskren Chernev }; 1007cbe63bfdSIskren Chernev 1008cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = { 1009cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1010cbe63bfdSIskren Chernev F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1011cbe63bfdSIskren Chernev F(341333333, P_GPLL6_OUT_EARLY, 1, 4, 9), 1012cbe63bfdSIskren Chernev F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0), 1013cbe63bfdSIskren Chernev { } 1014cbe63bfdSIskren Chernev }; 1015cbe63bfdSIskren Chernev 1016cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = { 1017cbe63bfdSIskren Chernev .cmd_rcgr = 0x52064, 1018cbe63bfdSIskren Chernev .mnd_width = 16, 1019cbe63bfdSIskren Chernev .hid_width = 5, 1020cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_10, 1021cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src, 1022cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1023cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_cphy_rx_clk_src", 1024cbe63bfdSIskren Chernev .parent_data = gcc_parents_10, 1025cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_10), 1026cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 1027*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1028cbe63bfdSIskren Chernev }, 1029cbe63bfdSIskren Chernev }; 1030cbe63bfdSIskren Chernev 1031cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = { 1032cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1033cbe63bfdSIskren Chernev F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0), 1034cbe63bfdSIskren Chernev F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0), 1035cbe63bfdSIskren Chernev { } 1036cbe63bfdSIskren Chernev }; 1037cbe63bfdSIskren Chernev 1038cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_camss_top_ahb_clk_src = { 1039cbe63bfdSIskren Chernev .cmd_rcgr = 0x58010, 1040cbe63bfdSIskren Chernev .mnd_width = 0, 1041cbe63bfdSIskren Chernev .hid_width = 5, 1042cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_7, 1043cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_camss_top_ahb_clk_src, 1044cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1045cbe63bfdSIskren Chernev .name = "gcc_camss_top_ahb_clk_src", 1046cbe63bfdSIskren Chernev .parent_data = gcc_parents_7, 1047cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_7), 1048cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 1049*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1050cbe63bfdSIskren Chernev }, 1051cbe63bfdSIskren Chernev }; 1052cbe63bfdSIskren Chernev 1053cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 1054cbe63bfdSIskren Chernev F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1055cbe63bfdSIskren Chernev F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1056cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1057cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 1058cbe63bfdSIskren Chernev { } 1059cbe63bfdSIskren Chernev }; 1060cbe63bfdSIskren Chernev 1061cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_gp1_clk_src = { 1062cbe63bfdSIskren Chernev .cmd_rcgr = 0x4d004, 1063cbe63bfdSIskren Chernev .mnd_width = 8, 1064cbe63bfdSIskren Chernev .hid_width = 5, 1065cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_2, 1066cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_gp1_clk_src, 1067cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1068cbe63bfdSIskren Chernev .name = "gcc_gp1_clk_src", 1069cbe63bfdSIskren Chernev .parent_data = gcc_parents_2, 1070cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_2), 1071cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1072cbe63bfdSIskren Chernev }, 1073cbe63bfdSIskren Chernev }; 1074cbe63bfdSIskren Chernev 1075cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_gp2_clk_src = { 1076cbe63bfdSIskren Chernev .cmd_rcgr = 0x4e004, 1077cbe63bfdSIskren Chernev .mnd_width = 8, 1078cbe63bfdSIskren Chernev .hid_width = 5, 1079cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_2, 1080cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_gp1_clk_src, 1081cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1082cbe63bfdSIskren Chernev .name = "gcc_gp2_clk_src", 1083cbe63bfdSIskren Chernev .parent_data = gcc_parents_2, 1084cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_2), 1085cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1086cbe63bfdSIskren Chernev }, 1087cbe63bfdSIskren Chernev }; 1088cbe63bfdSIskren Chernev 1089cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_gp3_clk_src = { 1090cbe63bfdSIskren Chernev .cmd_rcgr = 0x4f004, 1091cbe63bfdSIskren Chernev .mnd_width = 8, 1092cbe63bfdSIskren Chernev .hid_width = 5, 1093cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_2, 1094cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_gp1_clk_src, 1095cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1096cbe63bfdSIskren Chernev .name = "gcc_gp3_clk_src", 1097cbe63bfdSIskren Chernev .parent_data = gcc_parents_2, 1098cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_2), 1099cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1100cbe63bfdSIskren Chernev }, 1101cbe63bfdSIskren Chernev }; 1102cbe63bfdSIskren Chernev 1103cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 1104cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1105cbe63bfdSIskren Chernev F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0), 1106cbe63bfdSIskren Chernev { } 1107cbe63bfdSIskren Chernev }; 1108cbe63bfdSIskren Chernev 1109cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_pdm2_clk_src = { 1110cbe63bfdSIskren Chernev .cmd_rcgr = 0x20010, 1111cbe63bfdSIskren Chernev .mnd_width = 0, 1112cbe63bfdSIskren Chernev .hid_width = 5, 1113cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1114cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_pdm2_clk_src, 1115cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1116cbe63bfdSIskren Chernev .name = "gcc_pdm2_clk_src", 1117cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1118cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1119*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1120cbe63bfdSIskren Chernev }, 1121cbe63bfdSIskren Chernev }; 1122cbe63bfdSIskren Chernev 1123cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 1124cbe63bfdSIskren Chernev F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625), 1125cbe63bfdSIskren Chernev F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625), 1126cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1127cbe63bfdSIskren Chernev F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625), 1128cbe63bfdSIskren Chernev F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75), 1129cbe63bfdSIskren Chernev F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25), 1130cbe63bfdSIskren Chernev F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75), 1131cbe63bfdSIskren Chernev F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1132cbe63bfdSIskren Chernev F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15), 1133cbe63bfdSIskren Chernev F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25), 1134cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1135cbe63bfdSIskren Chernev F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375), 1136cbe63bfdSIskren Chernev F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75), 1137cbe63bfdSIskren Chernev F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625), 1138cbe63bfdSIskren Chernev F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0), 1139cbe63bfdSIskren Chernev F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0), 1140cbe63bfdSIskren Chernev { } 1141cbe63bfdSIskren Chernev }; 1142cbe63bfdSIskren Chernev 1143cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 1144cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s0_clk_src", 1145cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1146cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1147cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1148cbe63bfdSIskren Chernev }; 1149cbe63bfdSIskren Chernev 1150cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 1151cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f148, 1152cbe63bfdSIskren Chernev .mnd_width = 16, 1153cbe63bfdSIskren Chernev .hid_width = 5, 1154cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1155cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1156cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 1157cbe63bfdSIskren Chernev }; 1158cbe63bfdSIskren Chernev 1159cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 1160cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s1_clk_src", 1161cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1162cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1163cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1164cbe63bfdSIskren Chernev }; 1165cbe63bfdSIskren Chernev 1166cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 1167cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f278, 1168cbe63bfdSIskren Chernev .mnd_width = 16, 1169cbe63bfdSIskren Chernev .hid_width = 5, 1170cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1171cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1172cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 1173cbe63bfdSIskren Chernev }; 1174cbe63bfdSIskren Chernev 1175cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 1176cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s2_clk_src", 1177cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1178cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1179cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1180cbe63bfdSIskren Chernev }; 1181cbe63bfdSIskren Chernev 1182cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 1183cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f3a8, 1184cbe63bfdSIskren Chernev .mnd_width = 16, 1185cbe63bfdSIskren Chernev .hid_width = 5, 1186cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1187cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1188cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 1189cbe63bfdSIskren Chernev }; 1190cbe63bfdSIskren Chernev 1191cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 1192cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s3_clk_src", 1193cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1194cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1195cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1196cbe63bfdSIskren Chernev }; 1197cbe63bfdSIskren Chernev 1198cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 1199cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f4d8, 1200cbe63bfdSIskren Chernev .mnd_width = 16, 1201cbe63bfdSIskren Chernev .hid_width = 5, 1202cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1203cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1204cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 1205cbe63bfdSIskren Chernev }; 1206cbe63bfdSIskren Chernev 1207cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 1208cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s4_clk_src", 1209cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1210cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1211cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1212cbe63bfdSIskren Chernev }; 1213cbe63bfdSIskren Chernev 1214cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 1215cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f608, 1216cbe63bfdSIskren Chernev .mnd_width = 16, 1217cbe63bfdSIskren Chernev .hid_width = 5, 1218cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1219cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1220cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 1221cbe63bfdSIskren Chernev }; 1222cbe63bfdSIskren Chernev 1223cbe63bfdSIskren Chernev static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 1224cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s5_clk_src", 1225cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1226cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 1227cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1228cbe63bfdSIskren Chernev }; 1229cbe63bfdSIskren Chernev 1230cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 1231cbe63bfdSIskren Chernev .cmd_rcgr = 0x1f738, 1232cbe63bfdSIskren Chernev .mnd_width = 16, 1233cbe63bfdSIskren Chernev .hid_width = 5, 1234cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1235cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1236cbe63bfdSIskren Chernev .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 1237cbe63bfdSIskren Chernev }; 1238cbe63bfdSIskren Chernev 1239cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 1240cbe63bfdSIskren Chernev F(144000, P_BI_TCXO, 16, 3, 25), 1241cbe63bfdSIskren Chernev F(400000, P_BI_TCXO, 12, 1, 4), 1242cbe63bfdSIskren Chernev F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3), 1243cbe63bfdSIskren Chernev F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2), 1244cbe63bfdSIskren Chernev F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1245cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1246cbe63bfdSIskren Chernev F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 1247cbe63bfdSIskren Chernev F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 1248cbe63bfdSIskren Chernev { } 1249cbe63bfdSIskren Chernev }; 1250cbe63bfdSIskren Chernev 1251cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 1252cbe63bfdSIskren Chernev .cmd_rcgr = 0x38028, 1253cbe63bfdSIskren Chernev .mnd_width = 8, 1254cbe63bfdSIskren Chernev .hid_width = 5, 1255cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_1, 1256cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 1257cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1258cbe63bfdSIskren Chernev .name = "gcc_sdcc1_apps_clk_src", 1259cbe63bfdSIskren Chernev .parent_data = gcc_parents_1, 1260cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_1), 126185d4e6eaSKonrad Dybcio .ops = &clk_rcg2_floor_ops, 1262cbe63bfdSIskren Chernev }, 1263cbe63bfdSIskren Chernev }; 1264cbe63bfdSIskren Chernev 1265cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 1266cbe63bfdSIskren Chernev F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1267cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1268cbe63bfdSIskren Chernev F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1269cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1270cbe63bfdSIskren Chernev F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 1271cbe63bfdSIskren Chernev { } 1272cbe63bfdSIskren Chernev }; 1273cbe63bfdSIskren Chernev 1274cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 1275cbe63bfdSIskren Chernev .cmd_rcgr = 0x38010, 1276cbe63bfdSIskren Chernev .mnd_width = 0, 1277cbe63bfdSIskren Chernev .hid_width = 5, 1278cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1279cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 1280cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1281cbe63bfdSIskren Chernev .name = "gcc_sdcc1_ice_core_clk_src", 1282cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1283cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1284cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1285cbe63bfdSIskren Chernev }, 1286cbe63bfdSIskren Chernev }; 1287cbe63bfdSIskren Chernev 1288cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1289cbe63bfdSIskren Chernev F(400000, P_BI_TCXO, 12, 1, 4), 1290cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1291cbe63bfdSIskren Chernev F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1292cbe63bfdSIskren Chernev F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1293cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1294cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1295cbe63bfdSIskren Chernev { } 1296cbe63bfdSIskren Chernev }; 1297cbe63bfdSIskren Chernev 1298cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1299cbe63bfdSIskren Chernev .cmd_rcgr = 0x1e00c, 1300cbe63bfdSIskren Chernev .mnd_width = 8, 1301cbe63bfdSIskren Chernev .hid_width = 5, 1302cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_11, 1303cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1304cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1305cbe63bfdSIskren Chernev .name = "gcc_sdcc2_apps_clk_src", 1306cbe63bfdSIskren Chernev .parent_data = gcc_parents_11, 1307cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_11), 130885d4e6eaSKonrad Dybcio .ops = &clk_rcg2_floor_ops, 1309cbe63bfdSIskren Chernev .flags = CLK_OPS_PARENT_ENABLE, 1310cbe63bfdSIskren Chernev }, 1311cbe63bfdSIskren Chernev }; 1312cbe63bfdSIskren Chernev 1313cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1314cbe63bfdSIskren Chernev F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1315cbe63bfdSIskren Chernev F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1316cbe63bfdSIskren Chernev F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1317cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1318cbe63bfdSIskren Chernev F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1319cbe63bfdSIskren Chernev { } 1320cbe63bfdSIskren Chernev }; 1321cbe63bfdSIskren Chernev 1322cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1323cbe63bfdSIskren Chernev .cmd_rcgr = 0x45020, 1324cbe63bfdSIskren Chernev .mnd_width = 8, 1325cbe63bfdSIskren Chernev .hid_width = 5, 1326cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1327cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1328cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1329cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_axi_clk_src", 1330cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1331cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1332*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1333cbe63bfdSIskren Chernev }, 1334cbe63bfdSIskren Chernev }; 1335cbe63bfdSIskren Chernev 1336cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1337cbe63bfdSIskren Chernev F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 1338cbe63bfdSIskren Chernev F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1339cbe63bfdSIskren Chernev F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1340cbe63bfdSIskren Chernev F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 1341cbe63bfdSIskren Chernev { } 1342cbe63bfdSIskren Chernev }; 1343cbe63bfdSIskren Chernev 1344cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1345cbe63bfdSIskren Chernev .cmd_rcgr = 0x45048, 1346cbe63bfdSIskren Chernev .mnd_width = 0, 1347cbe63bfdSIskren Chernev .hid_width = 5, 1348cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1349cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1350cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1351cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_ice_core_clk_src", 1352cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1353cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1354*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1355cbe63bfdSIskren Chernev }, 1356cbe63bfdSIskren Chernev }; 1357cbe63bfdSIskren Chernev 1358cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1359cbe63bfdSIskren Chernev F(9600000, P_BI_TCXO, 2, 0, 0), 1360cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1361cbe63bfdSIskren Chernev { } 1362cbe63bfdSIskren Chernev }; 1363cbe63bfdSIskren Chernev 1364cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1365cbe63bfdSIskren Chernev .cmd_rcgr = 0x4507c, 1366cbe63bfdSIskren Chernev .mnd_width = 0, 1367cbe63bfdSIskren Chernev .hid_width = 5, 1368cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1369cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1370cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1371cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_phy_aux_clk_src", 1372cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1373cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1374cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1375cbe63bfdSIskren Chernev }, 1376cbe63bfdSIskren Chernev }; 1377cbe63bfdSIskren Chernev 1378cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 1379cbe63bfdSIskren Chernev F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 1380cbe63bfdSIskren Chernev F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1381cbe63bfdSIskren Chernev F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1382cbe63bfdSIskren Chernev { } 1383cbe63bfdSIskren Chernev }; 1384cbe63bfdSIskren Chernev 1385cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1386cbe63bfdSIskren Chernev .cmd_rcgr = 0x45060, 1387cbe63bfdSIskren Chernev .mnd_width = 0, 1388cbe63bfdSIskren Chernev .hid_width = 5, 1389cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1390cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 1391cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1392cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_unipro_core_clk_src", 1393cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1394cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1395*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1396cbe63bfdSIskren Chernev }, 1397cbe63bfdSIskren Chernev }; 1398cbe63bfdSIskren Chernev 1399cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1400cbe63bfdSIskren Chernev F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0), 1401cbe63bfdSIskren Chernev F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0), 1402cbe63bfdSIskren Chernev F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1403cbe63bfdSIskren Chernev F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1404cbe63bfdSIskren Chernev { } 1405cbe63bfdSIskren Chernev }; 1406cbe63bfdSIskren Chernev 1407cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1408cbe63bfdSIskren Chernev .cmd_rcgr = 0x1a01c, 1409cbe63bfdSIskren Chernev .mnd_width = 8, 1410cbe63bfdSIskren Chernev .hid_width = 5, 1411cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1412cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1413cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1414cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_master_clk_src", 1415cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1416cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1417*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1418cbe63bfdSIskren Chernev }, 1419cbe63bfdSIskren Chernev }; 1420cbe63bfdSIskren Chernev 1421cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 1422cbe63bfdSIskren Chernev F(19200000, P_BI_TCXO, 1, 0, 0), 1423cbe63bfdSIskren Chernev { } 1424cbe63bfdSIskren Chernev }; 1425cbe63bfdSIskren Chernev 1426cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1427cbe63bfdSIskren Chernev .cmd_rcgr = 0x1a034, 1428cbe63bfdSIskren Chernev .mnd_width = 0, 1429cbe63bfdSIskren Chernev .hid_width = 5, 1430cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_0, 1431cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1432cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1433cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_mock_utmi_clk_src", 1434cbe63bfdSIskren Chernev .parent_data = gcc_parents_0, 1435cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_0), 1436cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1437cbe63bfdSIskren Chernev }, 1438cbe63bfdSIskren Chernev }; 1439cbe63bfdSIskren Chernev 1440cbe63bfdSIskren Chernev static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1441cbe63bfdSIskren Chernev .reg = 0x1a04c, 1442cbe63bfdSIskren Chernev .shift = 0, 1443cbe63bfdSIskren Chernev .width = 2, 1444cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data) { 1445cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1446cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]) { 1447cbe63bfdSIskren Chernev &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw }, 1448cbe63bfdSIskren Chernev .num_parents = 1, 1449cbe63bfdSIskren Chernev .ops = &clk_regmap_div_ro_ops, 1450cbe63bfdSIskren Chernev }, 1451cbe63bfdSIskren Chernev }; 1452cbe63bfdSIskren Chernev 1453cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1454cbe63bfdSIskren Chernev .cmd_rcgr = 0x1a060, 1455cbe63bfdSIskren Chernev .mnd_width = 0, 1456cbe63bfdSIskren Chernev .hid_width = 5, 1457cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_12, 1458cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1459cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1460cbe63bfdSIskren Chernev .name = "gcc_usb3_prim_phy_aux_clk_src", 1461cbe63bfdSIskren Chernev .parent_data = gcc_parents_12, 1462cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_12), 1463cbe63bfdSIskren Chernev .ops = &clk_rcg2_ops, 1464cbe63bfdSIskren Chernev }, 1465cbe63bfdSIskren Chernev }; 1466cbe63bfdSIskren Chernev 1467cbe63bfdSIskren Chernev static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = { 1468cbe63bfdSIskren Chernev F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0), 1469cbe63bfdSIskren Chernev F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0), 1470cbe63bfdSIskren Chernev F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0), 1471cbe63bfdSIskren Chernev F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0), 1472cbe63bfdSIskren Chernev { } 1473cbe63bfdSIskren Chernev }; 1474cbe63bfdSIskren Chernev 1475cbe63bfdSIskren Chernev static struct clk_rcg2 gcc_video_venus_clk_src = { 1476cbe63bfdSIskren Chernev .cmd_rcgr = 0x58060, 1477cbe63bfdSIskren Chernev .mnd_width = 0, 1478cbe63bfdSIskren Chernev .hid_width = 5, 1479cbe63bfdSIskren Chernev .parent_map = gcc_parent_map_13, 1480cbe63bfdSIskren Chernev .freq_tbl = ftbl_gcc_video_venus_clk_src, 1481cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data){ 1482cbe63bfdSIskren Chernev .name = "gcc_video_venus_clk_src", 1483cbe63bfdSIskren Chernev .parent_data = gcc_parents_13, 1484cbe63bfdSIskren Chernev .num_parents = ARRAY_SIZE(gcc_parents_13), 1485cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1486*996c32b7SKonrad Dybcio .ops = &clk_rcg2_shared_ops, 1487cbe63bfdSIskren Chernev }, 1488cbe63bfdSIskren Chernev }; 1489cbe63bfdSIskren Chernev 1490cbe63bfdSIskren Chernev static struct clk_branch gcc_ahb2phy_csi_clk = { 1491cbe63bfdSIskren Chernev .halt_reg = 0x1d004, 1492cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1493cbe63bfdSIskren Chernev .hwcg_reg = 0x1d004, 1494cbe63bfdSIskren Chernev .hwcg_bit = 1, 1495cbe63bfdSIskren Chernev .clkr = { 1496cbe63bfdSIskren Chernev .enable_reg = 0x1d004, 1497cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1498cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1499cbe63bfdSIskren Chernev .name = "gcc_ahb2phy_csi_clk", 1500cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1501cbe63bfdSIskren Chernev }, 1502cbe63bfdSIskren Chernev }, 1503cbe63bfdSIskren Chernev }; 1504cbe63bfdSIskren Chernev 1505cbe63bfdSIskren Chernev static struct clk_branch gcc_ahb2phy_usb_clk = { 1506cbe63bfdSIskren Chernev .halt_reg = 0x1d008, 1507cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1508cbe63bfdSIskren Chernev .hwcg_reg = 0x1d008, 1509cbe63bfdSIskren Chernev .hwcg_bit = 1, 1510cbe63bfdSIskren Chernev .clkr = { 1511cbe63bfdSIskren Chernev .enable_reg = 0x1d008, 1512cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1513cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1514cbe63bfdSIskren Chernev .name = "gcc_ahb2phy_usb_clk", 1515cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1516cbe63bfdSIskren Chernev }, 1517cbe63bfdSIskren Chernev }, 1518cbe63bfdSIskren Chernev }; 1519cbe63bfdSIskren Chernev 1520cbe63bfdSIskren Chernev static struct clk_branch gcc_bimc_gpu_axi_clk = { 1521cbe63bfdSIskren Chernev .halt_reg = 0x71154, 1522cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 1523cbe63bfdSIskren Chernev .hwcg_reg = 0x71154, 1524cbe63bfdSIskren Chernev .hwcg_bit = 1, 1525cbe63bfdSIskren Chernev .clkr = { 1526cbe63bfdSIskren Chernev .enable_reg = 0x71154, 1527cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1528cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1529cbe63bfdSIskren Chernev .name = "gcc_bimc_gpu_axi_clk", 1530cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1531cbe63bfdSIskren Chernev }, 1532cbe63bfdSIskren Chernev }, 1533cbe63bfdSIskren Chernev }; 1534cbe63bfdSIskren Chernev 1535cbe63bfdSIskren Chernev static struct clk_branch gcc_boot_rom_ahb_clk = { 1536cbe63bfdSIskren Chernev .halt_reg = 0x23004, 1537cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 1538cbe63bfdSIskren Chernev .hwcg_reg = 0x23004, 1539cbe63bfdSIskren Chernev .hwcg_bit = 1, 1540cbe63bfdSIskren Chernev .clkr = { 1541cbe63bfdSIskren Chernev .enable_reg = 0x79004, 1542cbe63bfdSIskren Chernev .enable_mask = BIT(10), 1543cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1544cbe63bfdSIskren Chernev .name = "gcc_boot_rom_ahb_clk", 1545cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1546cbe63bfdSIskren Chernev }, 1547cbe63bfdSIskren Chernev }, 1548cbe63bfdSIskren Chernev }; 1549cbe63bfdSIskren Chernev 1550cbe63bfdSIskren Chernev static struct clk_branch gcc_cam_throttle_nrt_clk = { 1551cbe63bfdSIskren Chernev .halt_reg = 0x17070, 1552cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 1553cbe63bfdSIskren Chernev .hwcg_reg = 0x17070, 1554cbe63bfdSIskren Chernev .hwcg_bit = 1, 1555cbe63bfdSIskren Chernev .clkr = { 1556cbe63bfdSIskren Chernev .enable_reg = 0x79004, 1557cbe63bfdSIskren Chernev .enable_mask = BIT(27), 1558cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1559cbe63bfdSIskren Chernev .name = "gcc_cam_throttle_nrt_clk", 1560cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1561cbe63bfdSIskren Chernev }, 1562cbe63bfdSIskren Chernev }, 1563cbe63bfdSIskren Chernev }; 1564cbe63bfdSIskren Chernev 1565cbe63bfdSIskren Chernev static struct clk_branch gcc_cam_throttle_rt_clk = { 1566cbe63bfdSIskren Chernev .halt_reg = 0x1706c, 1567cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 1568cbe63bfdSIskren Chernev .hwcg_reg = 0x1706c, 1569cbe63bfdSIskren Chernev .hwcg_bit = 1, 1570cbe63bfdSIskren Chernev .clkr = { 1571cbe63bfdSIskren Chernev .enable_reg = 0x79004, 1572cbe63bfdSIskren Chernev .enable_mask = BIT(26), 1573cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1574cbe63bfdSIskren Chernev .name = "gcc_cam_throttle_rt_clk", 1575cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1576cbe63bfdSIskren Chernev }, 1577cbe63bfdSIskren Chernev }, 1578cbe63bfdSIskren Chernev }; 1579cbe63bfdSIskren Chernev 1580cbe63bfdSIskren Chernev static struct clk_branch gcc_camera_ahb_clk = { 1581cbe63bfdSIskren Chernev .halt_reg = 0x17008, 1582cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 1583cbe63bfdSIskren Chernev .hwcg_reg = 0x17008, 1584cbe63bfdSIskren Chernev .hwcg_bit = 1, 1585cbe63bfdSIskren Chernev .clkr = { 1586cbe63bfdSIskren Chernev .enable_reg = 0x17008, 1587cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1588cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1589cbe63bfdSIskren Chernev .name = "gcc_camera_ahb_clk", 1590cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 1591cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1592cbe63bfdSIskren Chernev }, 1593cbe63bfdSIskren Chernev }, 1594cbe63bfdSIskren Chernev }; 1595cbe63bfdSIskren Chernev 1596cbe63bfdSIskren Chernev static struct clk_branch gcc_camera_xo_clk = { 1597cbe63bfdSIskren Chernev .halt_reg = 0x17028, 1598cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1599cbe63bfdSIskren Chernev .clkr = { 1600cbe63bfdSIskren Chernev .enable_reg = 0x17028, 1601cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1602cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1603cbe63bfdSIskren Chernev .name = "gcc_camera_xo_clk", 1604cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 1605cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1606cbe63bfdSIskren Chernev }, 1607cbe63bfdSIskren Chernev }, 1608cbe63bfdSIskren Chernev }; 1609cbe63bfdSIskren Chernev 1610cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_axi_clk = { 1611cbe63bfdSIskren Chernev .halt_reg = 0x58044, 1612cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1613cbe63bfdSIskren Chernev .clkr = { 1614cbe63bfdSIskren Chernev .enable_reg = 0x58044, 1615cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1616cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1617cbe63bfdSIskren Chernev .name = "gcc_camss_axi_clk", 1618cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1619cbe63bfdSIskren Chernev &gcc_camss_axi_clk_src.clkr.hw, 1620cbe63bfdSIskren Chernev }, 1621cbe63bfdSIskren Chernev .num_parents = 1, 1622cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1623cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1624cbe63bfdSIskren Chernev }, 1625cbe63bfdSIskren Chernev }, 1626cbe63bfdSIskren Chernev }; 1627cbe63bfdSIskren Chernev 1628cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_camnoc_atb_clk = { 1629cbe63bfdSIskren Chernev .halt_reg = 0x5804c, 1630cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 1631cbe63bfdSIskren Chernev .hwcg_reg = 0x5804c, 1632cbe63bfdSIskren Chernev .hwcg_bit = 1, 1633cbe63bfdSIskren Chernev .clkr = { 1634cbe63bfdSIskren Chernev .enable_reg = 0x5804c, 1635cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1636cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1637cbe63bfdSIskren Chernev .name = "gcc_camss_camnoc_atb_clk", 1638cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1639cbe63bfdSIskren Chernev }, 1640cbe63bfdSIskren Chernev }, 1641cbe63bfdSIskren Chernev }; 1642cbe63bfdSIskren Chernev 1643cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_camnoc_nts_xo_clk = { 1644cbe63bfdSIskren Chernev .halt_reg = 0x58050, 1645cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 1646cbe63bfdSIskren Chernev .hwcg_reg = 0x58050, 1647cbe63bfdSIskren Chernev .hwcg_bit = 1, 1648cbe63bfdSIskren Chernev .clkr = { 1649cbe63bfdSIskren Chernev .enable_reg = 0x58050, 1650cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1651cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1652cbe63bfdSIskren Chernev .name = "gcc_camss_camnoc_nts_xo_clk", 1653cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1654cbe63bfdSIskren Chernev }, 1655cbe63bfdSIskren Chernev }, 1656cbe63bfdSIskren Chernev }; 1657cbe63bfdSIskren Chernev 1658cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_cci_0_clk = { 1659cbe63bfdSIskren Chernev .halt_reg = 0x56018, 1660cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1661cbe63bfdSIskren Chernev .clkr = { 1662cbe63bfdSIskren Chernev .enable_reg = 0x56018, 1663cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1664cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1665cbe63bfdSIskren Chernev .name = "gcc_camss_cci_0_clk", 1666cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1667cbe63bfdSIskren Chernev &gcc_camss_cci_clk_src.clkr.hw, 1668cbe63bfdSIskren Chernev }, 1669cbe63bfdSIskren Chernev .num_parents = 1, 1670cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1671cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1672cbe63bfdSIskren Chernev }, 1673cbe63bfdSIskren Chernev }, 1674cbe63bfdSIskren Chernev }; 1675cbe63bfdSIskren Chernev 1676cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_cphy_0_clk = { 1677cbe63bfdSIskren Chernev .halt_reg = 0x52088, 1678cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1679cbe63bfdSIskren Chernev .clkr = { 1680cbe63bfdSIskren Chernev .enable_reg = 0x52088, 1681cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1682cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1683cbe63bfdSIskren Chernev .name = "gcc_camss_cphy_0_clk", 1684cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1685cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1686cbe63bfdSIskren Chernev }, 1687cbe63bfdSIskren Chernev .num_parents = 1, 1688cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1689cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1690cbe63bfdSIskren Chernev }, 1691cbe63bfdSIskren Chernev }, 1692cbe63bfdSIskren Chernev }; 1693cbe63bfdSIskren Chernev 1694cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_cphy_1_clk = { 1695cbe63bfdSIskren Chernev .halt_reg = 0x5208c, 1696cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1697cbe63bfdSIskren Chernev .clkr = { 1698cbe63bfdSIskren Chernev .enable_reg = 0x5208c, 1699cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1700cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1701cbe63bfdSIskren Chernev .name = "gcc_camss_cphy_1_clk", 1702cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1703cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1704cbe63bfdSIskren Chernev }, 1705cbe63bfdSIskren Chernev .num_parents = 1, 1706cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1707cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1708cbe63bfdSIskren Chernev }, 1709cbe63bfdSIskren Chernev }, 1710cbe63bfdSIskren Chernev }; 1711cbe63bfdSIskren Chernev 1712cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_cphy_2_clk = { 1713cbe63bfdSIskren Chernev .halt_reg = 0x52090, 1714cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1715cbe63bfdSIskren Chernev .clkr = { 1716cbe63bfdSIskren Chernev .enable_reg = 0x52090, 1717cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1718cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1719cbe63bfdSIskren Chernev .name = "gcc_camss_cphy_2_clk", 1720cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1721cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1722cbe63bfdSIskren Chernev }, 1723cbe63bfdSIskren Chernev .num_parents = 1, 1724cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1725cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1726cbe63bfdSIskren Chernev }, 1727cbe63bfdSIskren Chernev }, 1728cbe63bfdSIskren Chernev }; 1729cbe63bfdSIskren Chernev 1730cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_csi0phytimer_clk = { 1731cbe63bfdSIskren Chernev .halt_reg = 0x59018, 1732cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1733cbe63bfdSIskren Chernev .clkr = { 1734cbe63bfdSIskren Chernev .enable_reg = 0x59018, 1735cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1736cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1737cbe63bfdSIskren Chernev .name = "gcc_camss_csi0phytimer_clk", 1738cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1739cbe63bfdSIskren Chernev &gcc_camss_csi0phytimer_clk_src.clkr.hw, 1740cbe63bfdSIskren Chernev }, 1741cbe63bfdSIskren Chernev .num_parents = 1, 1742cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1743cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1744cbe63bfdSIskren Chernev }, 1745cbe63bfdSIskren Chernev }, 1746cbe63bfdSIskren Chernev }; 1747cbe63bfdSIskren Chernev 1748cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_csi1phytimer_clk = { 1749cbe63bfdSIskren Chernev .halt_reg = 0x59034, 1750cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1751cbe63bfdSIskren Chernev .clkr = { 1752cbe63bfdSIskren Chernev .enable_reg = 0x59034, 1753cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1754cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1755cbe63bfdSIskren Chernev .name = "gcc_camss_csi1phytimer_clk", 1756cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1757cbe63bfdSIskren Chernev &gcc_camss_csi1phytimer_clk_src.clkr.hw, 1758cbe63bfdSIskren Chernev }, 1759cbe63bfdSIskren Chernev .num_parents = 1, 1760cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1761cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1762cbe63bfdSIskren Chernev }, 1763cbe63bfdSIskren Chernev }, 1764cbe63bfdSIskren Chernev }; 1765cbe63bfdSIskren Chernev 1766cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_csi2phytimer_clk = { 1767cbe63bfdSIskren Chernev .halt_reg = 0x59050, 1768cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1769cbe63bfdSIskren Chernev .clkr = { 1770cbe63bfdSIskren Chernev .enable_reg = 0x59050, 1771cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1772cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1773cbe63bfdSIskren Chernev .name = "gcc_camss_csi2phytimer_clk", 1774cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1775cbe63bfdSIskren Chernev &gcc_camss_csi2phytimer_clk_src.clkr.hw, 1776cbe63bfdSIskren Chernev }, 1777cbe63bfdSIskren Chernev .num_parents = 1, 1778cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1779cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1780cbe63bfdSIskren Chernev }, 1781cbe63bfdSIskren Chernev }, 1782cbe63bfdSIskren Chernev }; 1783cbe63bfdSIskren Chernev 1784cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_mclk0_clk = { 1785cbe63bfdSIskren Chernev .halt_reg = 0x51018, 1786cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1787cbe63bfdSIskren Chernev .clkr = { 1788cbe63bfdSIskren Chernev .enable_reg = 0x51018, 1789cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1790cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1791cbe63bfdSIskren Chernev .name = "gcc_camss_mclk0_clk", 1792cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1793cbe63bfdSIskren Chernev &gcc_camss_mclk0_clk_src.clkr.hw, 1794cbe63bfdSIskren Chernev }, 1795cbe63bfdSIskren Chernev .num_parents = 1, 1796cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1797cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1798cbe63bfdSIskren Chernev }, 1799cbe63bfdSIskren Chernev }, 1800cbe63bfdSIskren Chernev }; 1801cbe63bfdSIskren Chernev 1802cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_mclk1_clk = { 1803cbe63bfdSIskren Chernev .halt_reg = 0x51034, 1804cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1805cbe63bfdSIskren Chernev .clkr = { 1806cbe63bfdSIskren Chernev .enable_reg = 0x51034, 1807cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1808cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1809cbe63bfdSIskren Chernev .name = "gcc_camss_mclk1_clk", 1810cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1811cbe63bfdSIskren Chernev &gcc_camss_mclk1_clk_src.clkr.hw, 1812cbe63bfdSIskren Chernev }, 1813cbe63bfdSIskren Chernev .num_parents = 1, 1814cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1815cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1816cbe63bfdSIskren Chernev }, 1817cbe63bfdSIskren Chernev }, 1818cbe63bfdSIskren Chernev }; 1819cbe63bfdSIskren Chernev 1820cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_mclk2_clk = { 1821cbe63bfdSIskren Chernev .halt_reg = 0x51050, 1822cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1823cbe63bfdSIskren Chernev .clkr = { 1824cbe63bfdSIskren Chernev .enable_reg = 0x51050, 1825cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1826cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1827cbe63bfdSIskren Chernev .name = "gcc_camss_mclk2_clk", 1828cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1829cbe63bfdSIskren Chernev &gcc_camss_mclk2_clk_src.clkr.hw, 1830cbe63bfdSIskren Chernev }, 1831cbe63bfdSIskren Chernev .num_parents = 1, 1832cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1833cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1834cbe63bfdSIskren Chernev }, 1835cbe63bfdSIskren Chernev }, 1836cbe63bfdSIskren Chernev }; 1837cbe63bfdSIskren Chernev 1838cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_mclk3_clk = { 1839cbe63bfdSIskren Chernev .halt_reg = 0x5106c, 1840cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1841cbe63bfdSIskren Chernev .clkr = { 1842cbe63bfdSIskren Chernev .enable_reg = 0x5106c, 1843cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1844cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1845cbe63bfdSIskren Chernev .name = "gcc_camss_mclk3_clk", 1846cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1847cbe63bfdSIskren Chernev &gcc_camss_mclk3_clk_src.clkr.hw, 1848cbe63bfdSIskren Chernev }, 1849cbe63bfdSIskren Chernev .num_parents = 1, 1850cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1851cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1852cbe63bfdSIskren Chernev }, 1853cbe63bfdSIskren Chernev }, 1854cbe63bfdSIskren Chernev }; 1855cbe63bfdSIskren Chernev 1856cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_nrt_axi_clk = { 1857cbe63bfdSIskren Chernev .halt_reg = 0x58054, 1858cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1859cbe63bfdSIskren Chernev .clkr = { 1860cbe63bfdSIskren Chernev .enable_reg = 0x58054, 1861cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1862cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1863cbe63bfdSIskren Chernev .name = "gcc_camss_nrt_axi_clk", 1864cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1865cbe63bfdSIskren Chernev }, 1866cbe63bfdSIskren Chernev }, 1867cbe63bfdSIskren Chernev }; 1868cbe63bfdSIskren Chernev 1869cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_ope_ahb_clk = { 1870cbe63bfdSIskren Chernev .halt_reg = 0x5503c, 1871cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1872cbe63bfdSIskren Chernev .clkr = { 1873cbe63bfdSIskren Chernev .enable_reg = 0x5503c, 1874cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1875cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1876cbe63bfdSIskren Chernev .name = "gcc_camss_ope_ahb_clk", 1877cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1878cbe63bfdSIskren Chernev &gcc_camss_ope_ahb_clk_src.clkr.hw, 1879cbe63bfdSIskren Chernev }, 1880cbe63bfdSIskren Chernev .num_parents = 1, 1881cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1882cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1883cbe63bfdSIskren Chernev }, 1884cbe63bfdSIskren Chernev }, 1885cbe63bfdSIskren Chernev }; 1886cbe63bfdSIskren Chernev 1887cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_ope_clk = { 1888cbe63bfdSIskren Chernev .halt_reg = 0x5501c, 1889cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1890cbe63bfdSIskren Chernev .clkr = { 1891cbe63bfdSIskren Chernev .enable_reg = 0x5501c, 1892cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1893cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1894cbe63bfdSIskren Chernev .name = "gcc_camss_ope_clk", 1895cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1896cbe63bfdSIskren Chernev &gcc_camss_ope_clk_src.clkr.hw, 1897cbe63bfdSIskren Chernev }, 1898cbe63bfdSIskren Chernev .num_parents = 1, 1899cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1900cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1901cbe63bfdSIskren Chernev }, 1902cbe63bfdSIskren Chernev }, 1903cbe63bfdSIskren Chernev }; 1904cbe63bfdSIskren Chernev 1905cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_rt_axi_clk = { 1906cbe63bfdSIskren Chernev .halt_reg = 0x5805c, 1907cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1908cbe63bfdSIskren Chernev .clkr = { 1909cbe63bfdSIskren Chernev .enable_reg = 0x5805c, 1910cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1911cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1912cbe63bfdSIskren Chernev .name = "gcc_camss_rt_axi_clk", 1913cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1914cbe63bfdSIskren Chernev }, 1915cbe63bfdSIskren Chernev }, 1916cbe63bfdSIskren Chernev }; 1917cbe63bfdSIskren Chernev 1918cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_0_clk = { 1919cbe63bfdSIskren Chernev .halt_reg = 0x5201c, 1920cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1921cbe63bfdSIskren Chernev .clkr = { 1922cbe63bfdSIskren Chernev .enable_reg = 0x5201c, 1923cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1924cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1925cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_0_clk", 1926cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1927cbe63bfdSIskren Chernev &gcc_camss_tfe_0_clk_src.clkr.hw, 1928cbe63bfdSIskren Chernev }, 1929cbe63bfdSIskren Chernev .num_parents = 1, 1930cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1931cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1932cbe63bfdSIskren Chernev }, 1933cbe63bfdSIskren Chernev }, 1934cbe63bfdSIskren Chernev }; 1935cbe63bfdSIskren Chernev 1936cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = { 1937cbe63bfdSIskren Chernev .halt_reg = 0x5207c, 1938cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1939cbe63bfdSIskren Chernev .clkr = { 1940cbe63bfdSIskren Chernev .enable_reg = 0x5207c, 1941cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1942cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1943cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_0_cphy_rx_clk", 1944cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1945cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1946cbe63bfdSIskren Chernev }, 1947cbe63bfdSIskren Chernev .num_parents = 1, 1948cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1949cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1950cbe63bfdSIskren Chernev }, 1951cbe63bfdSIskren Chernev }, 1952cbe63bfdSIskren Chernev }; 1953cbe63bfdSIskren Chernev 1954cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_0_csid_clk = { 1955cbe63bfdSIskren Chernev .halt_reg = 0x520ac, 1956cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1957cbe63bfdSIskren Chernev .clkr = { 1958cbe63bfdSIskren Chernev .enable_reg = 0x520ac, 1959cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1960cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1961cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_0_csid_clk", 1962cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1963cbe63bfdSIskren Chernev &gcc_camss_tfe_0_csid_clk_src.clkr.hw, 1964cbe63bfdSIskren Chernev }, 1965cbe63bfdSIskren Chernev .num_parents = 1, 1966cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1967cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1968cbe63bfdSIskren Chernev }, 1969cbe63bfdSIskren Chernev }, 1970cbe63bfdSIskren Chernev }; 1971cbe63bfdSIskren Chernev 1972cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_1_clk = { 1973cbe63bfdSIskren Chernev .halt_reg = 0x5203c, 1974cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1975cbe63bfdSIskren Chernev .clkr = { 1976cbe63bfdSIskren Chernev .enable_reg = 0x5203c, 1977cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1978cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1979cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_1_clk", 1980cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1981cbe63bfdSIskren Chernev &gcc_camss_tfe_1_clk_src.clkr.hw, 1982cbe63bfdSIskren Chernev }, 1983cbe63bfdSIskren Chernev .num_parents = 1, 1984cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 1985cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 1986cbe63bfdSIskren Chernev }, 1987cbe63bfdSIskren Chernev }, 1988cbe63bfdSIskren Chernev }; 1989cbe63bfdSIskren Chernev 1990cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = { 1991cbe63bfdSIskren Chernev .halt_reg = 0x52080, 1992cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 1993cbe63bfdSIskren Chernev .clkr = { 1994cbe63bfdSIskren Chernev .enable_reg = 0x52080, 1995cbe63bfdSIskren Chernev .enable_mask = BIT(0), 1996cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 1997cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_1_cphy_rx_clk", 1998cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 1999cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2000cbe63bfdSIskren Chernev }, 2001cbe63bfdSIskren Chernev .num_parents = 1, 2002cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2003cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2004cbe63bfdSIskren Chernev }, 2005cbe63bfdSIskren Chernev }, 2006cbe63bfdSIskren Chernev }; 2007cbe63bfdSIskren Chernev 2008cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_1_csid_clk = { 2009cbe63bfdSIskren Chernev .halt_reg = 0x520cc, 2010cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2011cbe63bfdSIskren Chernev .clkr = { 2012cbe63bfdSIskren Chernev .enable_reg = 0x520cc, 2013cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2014cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2015cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_1_csid_clk", 2016cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2017cbe63bfdSIskren Chernev &gcc_camss_tfe_1_csid_clk_src.clkr.hw, 2018cbe63bfdSIskren Chernev }, 2019cbe63bfdSIskren Chernev .num_parents = 1, 2020cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2021cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2022cbe63bfdSIskren Chernev }, 2023cbe63bfdSIskren Chernev }, 2024cbe63bfdSIskren Chernev }; 2025cbe63bfdSIskren Chernev 2026cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_2_clk = { 2027cbe63bfdSIskren Chernev .halt_reg = 0x5205c, 2028cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2029cbe63bfdSIskren Chernev .clkr = { 2030cbe63bfdSIskren Chernev .enable_reg = 0x5205c, 2031cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2032cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2033cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_2_clk", 2034cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2035cbe63bfdSIskren Chernev &gcc_camss_tfe_2_clk_src.clkr.hw, 2036cbe63bfdSIskren Chernev }, 2037cbe63bfdSIskren Chernev .num_parents = 1, 2038cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2039cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2040cbe63bfdSIskren Chernev }, 2041cbe63bfdSIskren Chernev }, 2042cbe63bfdSIskren Chernev }; 2043cbe63bfdSIskren Chernev 2044cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_2_cphy_rx_clk = { 2045cbe63bfdSIskren Chernev .halt_reg = 0x52084, 2046cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2047cbe63bfdSIskren Chernev .clkr = { 2048cbe63bfdSIskren Chernev .enable_reg = 0x52084, 2049cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2050cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2051cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_2_cphy_rx_clk", 2052cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2053cbe63bfdSIskren Chernev &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2054cbe63bfdSIskren Chernev }, 2055cbe63bfdSIskren Chernev .num_parents = 1, 2056cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2057cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2058cbe63bfdSIskren Chernev }, 2059cbe63bfdSIskren Chernev }, 2060cbe63bfdSIskren Chernev }; 2061cbe63bfdSIskren Chernev 2062cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_tfe_2_csid_clk = { 2063cbe63bfdSIskren Chernev .halt_reg = 0x520ec, 2064cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2065cbe63bfdSIskren Chernev .clkr = { 2066cbe63bfdSIskren Chernev .enable_reg = 0x520ec, 2067cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2068cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2069cbe63bfdSIskren Chernev .name = "gcc_camss_tfe_2_csid_clk", 2070cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2071cbe63bfdSIskren Chernev &gcc_camss_tfe_2_csid_clk_src.clkr.hw, 2072cbe63bfdSIskren Chernev }, 2073cbe63bfdSIskren Chernev .num_parents = 1, 2074cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2075cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2076cbe63bfdSIskren Chernev }, 2077cbe63bfdSIskren Chernev }, 2078cbe63bfdSIskren Chernev }; 2079cbe63bfdSIskren Chernev 2080cbe63bfdSIskren Chernev static struct clk_branch gcc_camss_top_ahb_clk = { 2081cbe63bfdSIskren Chernev .halt_reg = 0x58028, 2082cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2083cbe63bfdSIskren Chernev .clkr = { 2084cbe63bfdSIskren Chernev .enable_reg = 0x58028, 2085cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2086cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2087cbe63bfdSIskren Chernev .name = "gcc_camss_top_ahb_clk", 2088cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2089cbe63bfdSIskren Chernev &gcc_camss_top_ahb_clk_src.clkr.hw, 2090cbe63bfdSIskren Chernev }, 2091cbe63bfdSIskren Chernev .num_parents = 1, 2092cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2093cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2094cbe63bfdSIskren Chernev }, 2095cbe63bfdSIskren Chernev }, 2096cbe63bfdSIskren Chernev }; 2097cbe63bfdSIskren Chernev 2098cbe63bfdSIskren Chernev static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 2099cbe63bfdSIskren Chernev .halt_reg = 0x1a084, 2100cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2101cbe63bfdSIskren Chernev .hwcg_reg = 0x1a084, 2102cbe63bfdSIskren Chernev .hwcg_bit = 1, 2103cbe63bfdSIskren Chernev .clkr = { 2104cbe63bfdSIskren Chernev .enable_reg = 0x1a084, 2105cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2106cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2107cbe63bfdSIskren Chernev .name = "gcc_cfg_noc_usb3_prim_axi_clk", 2108cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2109cbe63bfdSIskren Chernev &gcc_usb30_prim_master_clk_src.clkr.hw, 2110cbe63bfdSIskren Chernev }, 2111cbe63bfdSIskren Chernev .num_parents = 1, 2112cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2113cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2114cbe63bfdSIskren Chernev }, 2115cbe63bfdSIskren Chernev }, 2116cbe63bfdSIskren Chernev }; 2117cbe63bfdSIskren Chernev 2118cbe63bfdSIskren Chernev static struct clk_branch gcc_cpuss_gnoc_clk = { 2119cbe63bfdSIskren Chernev .halt_reg = 0x2b004, 2120cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2121cbe63bfdSIskren Chernev .hwcg_reg = 0x2b004, 2122cbe63bfdSIskren Chernev .hwcg_bit = 1, 2123cbe63bfdSIskren Chernev .clkr = { 2124cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2125cbe63bfdSIskren Chernev .enable_mask = BIT(22), 2126cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2127cbe63bfdSIskren Chernev .name = "gcc_cpuss_gnoc_clk", 2128cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 2129cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2130cbe63bfdSIskren Chernev }, 2131cbe63bfdSIskren Chernev }, 2132cbe63bfdSIskren Chernev }; 2133cbe63bfdSIskren Chernev 2134cbe63bfdSIskren Chernev static struct clk_branch gcc_disp_ahb_clk = { 2135cbe63bfdSIskren Chernev .halt_reg = 0x1700c, 2136cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2137cbe63bfdSIskren Chernev .hwcg_reg = 0x1700c, 2138cbe63bfdSIskren Chernev .hwcg_bit = 1, 2139cbe63bfdSIskren Chernev .clkr = { 2140cbe63bfdSIskren Chernev .enable_reg = 0x1700c, 2141cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2142cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2143cbe63bfdSIskren Chernev .name = "gcc_disp_ahb_clk", 2144cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 2145cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2146cbe63bfdSIskren Chernev }, 2147cbe63bfdSIskren Chernev }, 2148cbe63bfdSIskren Chernev }; 2149cbe63bfdSIskren Chernev 2150cbe63bfdSIskren Chernev static struct clk_regmap_div gcc_disp_gpll0_clk_src = { 2151cbe63bfdSIskren Chernev .reg = 0x17058, 2152cbe63bfdSIskren Chernev .shift = 0, 2153cbe63bfdSIskren Chernev .width = 2, 2154cbe63bfdSIskren Chernev .clkr.hw.init = &(struct clk_init_data) { 2155cbe63bfdSIskren Chernev .name = "gcc_disp_gpll0_clk_src", 2156cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 2157cbe63bfdSIskren Chernev .num_parents = 1, 2158cbe63bfdSIskren Chernev .ops = &clk_regmap_div_ops, 2159cbe63bfdSIskren Chernev }, 2160cbe63bfdSIskren Chernev }; 2161cbe63bfdSIskren Chernev 2162cbe63bfdSIskren Chernev static struct clk_branch gcc_disp_gpll0_div_clk_src = { 2163cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 2164cbe63bfdSIskren Chernev .clkr = { 2165cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2166cbe63bfdSIskren Chernev .enable_mask = BIT(20), 2167cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2168cbe63bfdSIskren Chernev .name = "gcc_disp_gpll0_div_clk_src", 2169cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2170cbe63bfdSIskren Chernev &gcc_disp_gpll0_clk_src.clkr.hw, 2171cbe63bfdSIskren Chernev }, 2172cbe63bfdSIskren Chernev .num_parents = 1, 2173cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2174cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2175cbe63bfdSIskren Chernev }, 2176cbe63bfdSIskren Chernev }, 2177cbe63bfdSIskren Chernev }; 2178cbe63bfdSIskren Chernev 2179cbe63bfdSIskren Chernev static struct clk_branch gcc_disp_hf_axi_clk = { 2180cbe63bfdSIskren Chernev .halt_reg = 0x17020, 2181cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2182cbe63bfdSIskren Chernev .hwcg_reg = 0x17020, 2183cbe63bfdSIskren Chernev .hwcg_bit = 1, 2184cbe63bfdSIskren Chernev .clkr = { 2185cbe63bfdSIskren Chernev .enable_reg = 0x17020, 2186cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2187cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2188cbe63bfdSIskren Chernev .name = "gcc_disp_hf_axi_clk", 2189cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2190cbe63bfdSIskren Chernev }, 2191cbe63bfdSIskren Chernev }, 2192cbe63bfdSIskren Chernev }; 2193cbe63bfdSIskren Chernev 2194cbe63bfdSIskren Chernev static struct clk_branch gcc_disp_throttle_core_clk = { 2195cbe63bfdSIskren Chernev .halt_reg = 0x17064, 2196cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2197cbe63bfdSIskren Chernev .hwcg_reg = 0x17064, 2198cbe63bfdSIskren Chernev .hwcg_bit = 1, 2199cbe63bfdSIskren Chernev .clkr = { 2200cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2201cbe63bfdSIskren Chernev .enable_mask = BIT(5), 2202cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2203cbe63bfdSIskren Chernev .name = "gcc_disp_throttle_core_clk", 2204cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2205cbe63bfdSIskren Chernev }, 2206cbe63bfdSIskren Chernev }, 2207cbe63bfdSIskren Chernev }; 2208cbe63bfdSIskren Chernev 2209cbe63bfdSIskren Chernev static struct clk_branch gcc_disp_xo_clk = { 2210cbe63bfdSIskren Chernev .halt_reg = 0x1702c, 2211cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2212cbe63bfdSIskren Chernev .clkr = { 2213cbe63bfdSIskren Chernev .enable_reg = 0x1702c, 2214cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2215cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2216cbe63bfdSIskren Chernev .name = "gcc_disp_xo_clk", 2217cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 2218cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2219cbe63bfdSIskren Chernev }, 2220cbe63bfdSIskren Chernev }, 2221cbe63bfdSIskren Chernev }; 2222cbe63bfdSIskren Chernev 2223cbe63bfdSIskren Chernev static struct clk_branch gcc_gp1_clk = { 2224cbe63bfdSIskren Chernev .halt_reg = 0x4d000, 2225cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2226cbe63bfdSIskren Chernev .clkr = { 2227cbe63bfdSIskren Chernev .enable_reg = 0x4d000, 2228cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2229cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2230cbe63bfdSIskren Chernev .name = "gcc_gp1_clk", 2231cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2232cbe63bfdSIskren Chernev &gcc_gp1_clk_src.clkr.hw, 2233cbe63bfdSIskren Chernev }, 2234cbe63bfdSIskren Chernev .num_parents = 1, 2235cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2236cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2237cbe63bfdSIskren Chernev }, 2238cbe63bfdSIskren Chernev }, 2239cbe63bfdSIskren Chernev }; 2240cbe63bfdSIskren Chernev 2241cbe63bfdSIskren Chernev static struct clk_branch gcc_gp2_clk = { 2242cbe63bfdSIskren Chernev .halt_reg = 0x4e000, 2243cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2244cbe63bfdSIskren Chernev .clkr = { 2245cbe63bfdSIskren Chernev .enable_reg = 0x4e000, 2246cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2247cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2248cbe63bfdSIskren Chernev .name = "gcc_gp2_clk", 2249cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2250cbe63bfdSIskren Chernev &gcc_gp2_clk_src.clkr.hw, 2251cbe63bfdSIskren Chernev }, 2252cbe63bfdSIskren Chernev .num_parents = 1, 2253cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2254cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2255cbe63bfdSIskren Chernev }, 2256cbe63bfdSIskren Chernev }, 2257cbe63bfdSIskren Chernev }; 2258cbe63bfdSIskren Chernev 2259cbe63bfdSIskren Chernev static struct clk_branch gcc_gp3_clk = { 2260cbe63bfdSIskren Chernev .halt_reg = 0x4f000, 2261cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2262cbe63bfdSIskren Chernev .clkr = { 2263cbe63bfdSIskren Chernev .enable_reg = 0x4f000, 2264cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2265cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2266cbe63bfdSIskren Chernev .name = "gcc_gp3_clk", 2267cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2268cbe63bfdSIskren Chernev &gcc_gp3_clk_src.clkr.hw, 2269cbe63bfdSIskren Chernev }, 2270cbe63bfdSIskren Chernev .num_parents = 1, 2271cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2272cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2273cbe63bfdSIskren Chernev }, 2274cbe63bfdSIskren Chernev }, 2275cbe63bfdSIskren Chernev }; 2276cbe63bfdSIskren Chernev 2277cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_cfg_ahb_clk = { 2278cbe63bfdSIskren Chernev .halt_reg = 0x36004, 2279cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2280cbe63bfdSIskren Chernev .hwcg_reg = 0x36004, 2281cbe63bfdSIskren Chernev .hwcg_bit = 1, 2282cbe63bfdSIskren Chernev .clkr = { 2283cbe63bfdSIskren Chernev .enable_reg = 0x36004, 2284cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2285cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2286cbe63bfdSIskren Chernev .name = "gcc_gpu_cfg_ahb_clk", 2287cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 2288cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2289cbe63bfdSIskren Chernev }, 2290cbe63bfdSIskren Chernev }, 2291cbe63bfdSIskren Chernev }; 2292cbe63bfdSIskren Chernev 2293cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_gpll0_clk_src = { 2294cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 2295cbe63bfdSIskren Chernev .clkr = { 2296cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2297cbe63bfdSIskren Chernev .enable_mask = BIT(15), 2298cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2299cbe63bfdSIskren Chernev .name = "gcc_gpu_gpll0_clk_src", 2300cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2301cbe63bfdSIskren Chernev &gpll0.clkr.hw, 2302cbe63bfdSIskren Chernev }, 2303cbe63bfdSIskren Chernev .num_parents = 1, 2304cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2305cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2306cbe63bfdSIskren Chernev }, 2307cbe63bfdSIskren Chernev }, 2308cbe63bfdSIskren Chernev }; 2309cbe63bfdSIskren Chernev 2310cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 2311cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 2312cbe63bfdSIskren Chernev .clkr = { 2313cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2314cbe63bfdSIskren Chernev .enable_mask = BIT(16), 2315cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2316cbe63bfdSIskren Chernev .name = "gcc_gpu_gpll0_div_clk_src", 2317cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2318cbe63bfdSIskren Chernev &gpll0_out_aux2.clkr.hw, 2319cbe63bfdSIskren Chernev }, 2320cbe63bfdSIskren Chernev .num_parents = 1, 2321cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2322cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2323cbe63bfdSIskren Chernev }, 2324cbe63bfdSIskren Chernev }, 2325cbe63bfdSIskren Chernev }; 2326cbe63bfdSIskren Chernev 2327cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_iref_clk = { 2328cbe63bfdSIskren Chernev .halt_reg = 0x36100, 2329cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 2330cbe63bfdSIskren Chernev .clkr = { 2331cbe63bfdSIskren Chernev .enable_reg = 0x36100, 2332cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2333cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2334cbe63bfdSIskren Chernev .name = "gcc_gpu_iref_clk", 2335cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2336cbe63bfdSIskren Chernev }, 2337cbe63bfdSIskren Chernev }, 2338cbe63bfdSIskren Chernev }; 2339cbe63bfdSIskren Chernev 2340cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 2341cbe63bfdSIskren Chernev .halt_reg = 0x3600c, 2342cbe63bfdSIskren Chernev .halt_check = BRANCH_VOTED, 2343cbe63bfdSIskren Chernev .hwcg_reg = 0x3600c, 2344cbe63bfdSIskren Chernev .hwcg_bit = 1, 2345cbe63bfdSIskren Chernev .clkr = { 2346cbe63bfdSIskren Chernev .enable_reg = 0x3600c, 2347cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2348cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2349cbe63bfdSIskren Chernev .name = "gcc_gpu_memnoc_gfx_clk", 2350cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2351cbe63bfdSIskren Chernev }, 2352cbe63bfdSIskren Chernev }, 2353cbe63bfdSIskren Chernev }; 2354cbe63bfdSIskren Chernev 2355cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2356cbe63bfdSIskren Chernev .halt_reg = 0x36018, 2357cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2358cbe63bfdSIskren Chernev .clkr = { 2359cbe63bfdSIskren Chernev .enable_reg = 0x36018, 2360cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2361cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2362cbe63bfdSIskren Chernev .name = "gcc_gpu_snoc_dvm_gfx_clk", 2363cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2364cbe63bfdSIskren Chernev }, 2365cbe63bfdSIskren Chernev }, 2366cbe63bfdSIskren Chernev }; 2367cbe63bfdSIskren Chernev 2368cbe63bfdSIskren Chernev static struct clk_branch gcc_gpu_throttle_core_clk = { 2369cbe63bfdSIskren Chernev .halt_reg = 0x36048, 2370cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2371cbe63bfdSIskren Chernev .hwcg_reg = 0x36048, 2372cbe63bfdSIskren Chernev .hwcg_bit = 1, 2373cbe63bfdSIskren Chernev .clkr = { 2374cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2375cbe63bfdSIskren Chernev .enable_mask = BIT(31), 2376cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2377cbe63bfdSIskren Chernev .name = "gcc_gpu_throttle_core_clk", 2378cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2379cbe63bfdSIskren Chernev }, 2380cbe63bfdSIskren Chernev }, 2381cbe63bfdSIskren Chernev }; 2382cbe63bfdSIskren Chernev 2383cbe63bfdSIskren Chernev static struct clk_branch gcc_pdm2_clk = { 2384cbe63bfdSIskren Chernev .halt_reg = 0x2000c, 2385cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2386cbe63bfdSIskren Chernev .clkr = { 2387cbe63bfdSIskren Chernev .enable_reg = 0x2000c, 2388cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2389cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2390cbe63bfdSIskren Chernev .name = "gcc_pdm2_clk", 2391cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2392cbe63bfdSIskren Chernev &gcc_pdm2_clk_src.clkr.hw, 2393cbe63bfdSIskren Chernev }, 2394cbe63bfdSIskren Chernev .num_parents = 1, 2395cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2396cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2397cbe63bfdSIskren Chernev }, 2398cbe63bfdSIskren Chernev }, 2399cbe63bfdSIskren Chernev }; 2400cbe63bfdSIskren Chernev 2401cbe63bfdSIskren Chernev static struct clk_branch gcc_pdm_ahb_clk = { 2402cbe63bfdSIskren Chernev .halt_reg = 0x20004, 2403cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2404cbe63bfdSIskren Chernev .hwcg_reg = 0x20004, 2405cbe63bfdSIskren Chernev .hwcg_bit = 1, 2406cbe63bfdSIskren Chernev .clkr = { 2407cbe63bfdSIskren Chernev .enable_reg = 0x20004, 2408cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2409cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2410cbe63bfdSIskren Chernev .name = "gcc_pdm_ahb_clk", 2411cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2412cbe63bfdSIskren Chernev }, 2413cbe63bfdSIskren Chernev }, 2414cbe63bfdSIskren Chernev }; 2415cbe63bfdSIskren Chernev 2416cbe63bfdSIskren Chernev static struct clk_branch gcc_pdm_xo4_clk = { 2417cbe63bfdSIskren Chernev .halt_reg = 0x20008, 2418cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2419cbe63bfdSIskren Chernev .clkr = { 2420cbe63bfdSIskren Chernev .enable_reg = 0x20008, 2421cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2422cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2423cbe63bfdSIskren Chernev .name = "gcc_pdm_xo4_clk", 2424cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2425cbe63bfdSIskren Chernev }, 2426cbe63bfdSIskren Chernev }, 2427cbe63bfdSIskren Chernev }; 2428cbe63bfdSIskren Chernev 2429cbe63bfdSIskren Chernev static struct clk_branch gcc_prng_ahb_clk = { 2430cbe63bfdSIskren Chernev .halt_reg = 0x21004, 2431cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2432cbe63bfdSIskren Chernev .hwcg_reg = 0x21004, 2433cbe63bfdSIskren Chernev .hwcg_bit = 1, 2434cbe63bfdSIskren Chernev .clkr = { 2435cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2436cbe63bfdSIskren Chernev .enable_mask = BIT(13), 2437cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2438cbe63bfdSIskren Chernev .name = "gcc_prng_ahb_clk", 2439cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2440cbe63bfdSIskren Chernev }, 2441cbe63bfdSIskren Chernev }, 2442cbe63bfdSIskren Chernev }; 2443cbe63bfdSIskren Chernev 2444cbe63bfdSIskren Chernev static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2445cbe63bfdSIskren Chernev .halt_reg = 0x17014, 2446cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2447cbe63bfdSIskren Chernev .hwcg_reg = 0x17014, 2448cbe63bfdSIskren Chernev .hwcg_bit = 1, 2449cbe63bfdSIskren Chernev .clkr = { 2450cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2451cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2452cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2453cbe63bfdSIskren Chernev .name = "gcc_qmip_camera_nrt_ahb_clk", 2454cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2455cbe63bfdSIskren Chernev }, 2456cbe63bfdSIskren Chernev }, 2457cbe63bfdSIskren Chernev }; 2458cbe63bfdSIskren Chernev 2459cbe63bfdSIskren Chernev static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2460cbe63bfdSIskren Chernev .halt_reg = 0x17060, 2461cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2462cbe63bfdSIskren Chernev .hwcg_reg = 0x17060, 2463cbe63bfdSIskren Chernev .hwcg_bit = 1, 2464cbe63bfdSIskren Chernev .clkr = { 2465cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2466cbe63bfdSIskren Chernev .enable_mask = BIT(2), 2467cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2468cbe63bfdSIskren Chernev .name = "gcc_qmip_camera_rt_ahb_clk", 2469cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2470cbe63bfdSIskren Chernev }, 2471cbe63bfdSIskren Chernev }, 2472cbe63bfdSIskren Chernev }; 2473cbe63bfdSIskren Chernev 2474cbe63bfdSIskren Chernev static struct clk_branch gcc_qmip_disp_ahb_clk = { 2475cbe63bfdSIskren Chernev .halt_reg = 0x17018, 2476cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2477cbe63bfdSIskren Chernev .hwcg_reg = 0x17018, 2478cbe63bfdSIskren Chernev .hwcg_bit = 1, 2479cbe63bfdSIskren Chernev .clkr = { 2480cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2481cbe63bfdSIskren Chernev .enable_mask = BIT(1), 2482cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2483cbe63bfdSIskren Chernev .name = "gcc_qmip_disp_ahb_clk", 2484cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2485cbe63bfdSIskren Chernev }, 2486cbe63bfdSIskren Chernev }, 2487cbe63bfdSIskren Chernev }; 2488cbe63bfdSIskren Chernev 2489cbe63bfdSIskren Chernev static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = { 2490cbe63bfdSIskren Chernev .halt_reg = 0x36040, 2491cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2492cbe63bfdSIskren Chernev .hwcg_reg = 0x36040, 2493cbe63bfdSIskren Chernev .hwcg_bit = 1, 2494cbe63bfdSIskren Chernev .clkr = { 2495cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2496cbe63bfdSIskren Chernev .enable_mask = BIT(4), 2497cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2498cbe63bfdSIskren Chernev .name = "gcc_qmip_gpu_cfg_ahb_clk", 2499cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2500cbe63bfdSIskren Chernev }, 2501cbe63bfdSIskren Chernev }, 2502cbe63bfdSIskren Chernev }; 2503cbe63bfdSIskren Chernev 2504cbe63bfdSIskren Chernev static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2505cbe63bfdSIskren Chernev .halt_reg = 0x17010, 2506cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2507cbe63bfdSIskren Chernev .hwcg_reg = 0x17010, 2508cbe63bfdSIskren Chernev .hwcg_bit = 1, 2509cbe63bfdSIskren Chernev .clkr = { 2510cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2511cbe63bfdSIskren Chernev .enable_mask = BIT(25), 2512cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2513cbe63bfdSIskren Chernev .name = "gcc_qmip_video_vcodec_ahb_clk", 2514cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2515cbe63bfdSIskren Chernev }, 2516cbe63bfdSIskren Chernev }, 2517cbe63bfdSIskren Chernev }; 2518cbe63bfdSIskren Chernev 2519cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2520cbe63bfdSIskren Chernev .halt_reg = 0x1f014, 2521cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2522cbe63bfdSIskren Chernev .clkr = { 2523cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2524cbe63bfdSIskren Chernev .enable_mask = BIT(9), 2525cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2526cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_core_2x_clk", 2527cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2528cbe63bfdSIskren Chernev }, 2529cbe63bfdSIskren Chernev }, 2530cbe63bfdSIskren Chernev }; 2531cbe63bfdSIskren Chernev 2532cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2533cbe63bfdSIskren Chernev .halt_reg = 0x1f00c, 2534cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2535cbe63bfdSIskren Chernev .clkr = { 2536cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2537cbe63bfdSIskren Chernev .enable_mask = BIT(8), 2538cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2539cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_core_clk", 2540cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2541cbe63bfdSIskren Chernev }, 2542cbe63bfdSIskren Chernev }, 2543cbe63bfdSIskren Chernev }; 2544cbe63bfdSIskren Chernev 2545cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2546cbe63bfdSIskren Chernev .halt_reg = 0x1f144, 2547cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2548cbe63bfdSIskren Chernev .clkr = { 2549cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2550cbe63bfdSIskren Chernev .enable_mask = BIT(10), 2551cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2552cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s0_clk", 2553cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2554cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 2555cbe63bfdSIskren Chernev }, 2556cbe63bfdSIskren Chernev .num_parents = 1, 2557cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2558cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2559cbe63bfdSIskren Chernev }, 2560cbe63bfdSIskren Chernev }, 2561cbe63bfdSIskren Chernev }; 2562cbe63bfdSIskren Chernev 2563cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2564cbe63bfdSIskren Chernev .halt_reg = 0x1f274, 2565cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2566cbe63bfdSIskren Chernev .clkr = { 2567cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2568cbe63bfdSIskren Chernev .enable_mask = BIT(11), 2569cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2570cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s1_clk", 2571cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2572cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 2573cbe63bfdSIskren Chernev }, 2574cbe63bfdSIskren Chernev .num_parents = 1, 2575cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2576cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2577cbe63bfdSIskren Chernev }, 2578cbe63bfdSIskren Chernev }, 2579cbe63bfdSIskren Chernev }; 2580cbe63bfdSIskren Chernev 2581cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2582cbe63bfdSIskren Chernev .halt_reg = 0x1f3a4, 2583cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2584cbe63bfdSIskren Chernev .clkr = { 2585cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2586cbe63bfdSIskren Chernev .enable_mask = BIT(12), 2587cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2588cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s2_clk", 2589cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2590cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2591cbe63bfdSIskren Chernev }, 2592cbe63bfdSIskren Chernev .num_parents = 1, 2593cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2594cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2595cbe63bfdSIskren Chernev }, 2596cbe63bfdSIskren Chernev }, 2597cbe63bfdSIskren Chernev }; 2598cbe63bfdSIskren Chernev 2599cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2600cbe63bfdSIskren Chernev .halt_reg = 0x1f4d4, 2601cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2602cbe63bfdSIskren Chernev .clkr = { 2603cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2604cbe63bfdSIskren Chernev .enable_mask = BIT(13), 2605cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2606cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s3_clk", 2607cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2608cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2609cbe63bfdSIskren Chernev }, 2610cbe63bfdSIskren Chernev .num_parents = 1, 2611cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2612cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2613cbe63bfdSIskren Chernev }, 2614cbe63bfdSIskren Chernev }, 2615cbe63bfdSIskren Chernev }; 2616cbe63bfdSIskren Chernev 2617cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2618cbe63bfdSIskren Chernev .halt_reg = 0x1f604, 2619cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2620cbe63bfdSIskren Chernev .clkr = { 2621cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2622cbe63bfdSIskren Chernev .enable_mask = BIT(14), 2623cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2624cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s4_clk", 2625cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2626cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2627cbe63bfdSIskren Chernev }, 2628cbe63bfdSIskren Chernev .num_parents = 1, 2629cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2630cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2631cbe63bfdSIskren Chernev }, 2632cbe63bfdSIskren Chernev }, 2633cbe63bfdSIskren Chernev }; 2634cbe63bfdSIskren Chernev 2635cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2636cbe63bfdSIskren Chernev .halt_reg = 0x1f734, 2637cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2638cbe63bfdSIskren Chernev .clkr = { 2639cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2640cbe63bfdSIskren Chernev .enable_mask = BIT(15), 2641cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2642cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap0_s5_clk", 2643cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2644cbe63bfdSIskren Chernev &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2645cbe63bfdSIskren Chernev }, 2646cbe63bfdSIskren Chernev .num_parents = 1, 2647cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2648cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2649cbe63bfdSIskren Chernev }, 2650cbe63bfdSIskren Chernev }, 2651cbe63bfdSIskren Chernev }; 2652cbe63bfdSIskren Chernev 2653cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2654cbe63bfdSIskren Chernev .halt_reg = 0x1f004, 2655cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2656cbe63bfdSIskren Chernev .hwcg_reg = 0x1f004, 2657cbe63bfdSIskren Chernev .hwcg_bit = 1, 2658cbe63bfdSIskren Chernev .clkr = { 2659cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2660cbe63bfdSIskren Chernev .enable_mask = BIT(6), 2661cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2662cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2663cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2664cbe63bfdSIskren Chernev }, 2665cbe63bfdSIskren Chernev }, 2666cbe63bfdSIskren Chernev }; 2667cbe63bfdSIskren Chernev 2668cbe63bfdSIskren Chernev static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2669cbe63bfdSIskren Chernev .halt_reg = 0x1f008, 2670cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2671cbe63bfdSIskren Chernev .hwcg_reg = 0x1f008, 2672cbe63bfdSIskren Chernev .hwcg_bit = 1, 2673cbe63bfdSIskren Chernev .clkr = { 2674cbe63bfdSIskren Chernev .enable_reg = 0x7900c, 2675cbe63bfdSIskren Chernev .enable_mask = BIT(7), 2676cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2677cbe63bfdSIskren Chernev .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2678cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2679cbe63bfdSIskren Chernev }, 2680cbe63bfdSIskren Chernev }, 2681cbe63bfdSIskren Chernev }; 2682cbe63bfdSIskren Chernev 2683cbe63bfdSIskren Chernev static struct clk_branch gcc_sdcc1_ahb_clk = { 2684cbe63bfdSIskren Chernev .halt_reg = 0x38008, 2685cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2686cbe63bfdSIskren Chernev .clkr = { 2687cbe63bfdSIskren Chernev .enable_reg = 0x38008, 2688cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2689cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2690cbe63bfdSIskren Chernev .name = "gcc_sdcc1_ahb_clk", 2691cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2692cbe63bfdSIskren Chernev }, 2693cbe63bfdSIskren Chernev }, 2694cbe63bfdSIskren Chernev }; 2695cbe63bfdSIskren Chernev 2696cbe63bfdSIskren Chernev static struct clk_branch gcc_sdcc1_apps_clk = { 2697cbe63bfdSIskren Chernev .halt_reg = 0x38004, 2698cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2699cbe63bfdSIskren Chernev .clkr = { 2700cbe63bfdSIskren Chernev .enable_reg = 0x38004, 2701cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2702cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2703cbe63bfdSIskren Chernev .name = "gcc_sdcc1_apps_clk", 2704cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2705cbe63bfdSIskren Chernev &gcc_sdcc1_apps_clk_src.clkr.hw, 2706cbe63bfdSIskren Chernev }, 2707cbe63bfdSIskren Chernev .num_parents = 1, 2708cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT /* | CLK_ENABLE_HAND_OFF */, 2709cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2710cbe63bfdSIskren Chernev }, 2711cbe63bfdSIskren Chernev }, 2712cbe63bfdSIskren Chernev }; 2713cbe63bfdSIskren Chernev 2714cbe63bfdSIskren Chernev static struct clk_branch gcc_sdcc1_ice_core_clk = { 2715cbe63bfdSIskren Chernev .halt_reg = 0x3800c, 2716cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2717cbe63bfdSIskren Chernev .hwcg_reg = 0x3800c, 2718cbe63bfdSIskren Chernev .hwcg_bit = 1, 2719cbe63bfdSIskren Chernev .clkr = { 2720cbe63bfdSIskren Chernev .enable_reg = 0x3800c, 2721cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2722cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2723cbe63bfdSIskren Chernev .name = "gcc_sdcc1_ice_core_clk", 2724cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2725cbe63bfdSIskren Chernev &gcc_sdcc1_ice_core_clk_src.clkr.hw, 2726cbe63bfdSIskren Chernev }, 2727cbe63bfdSIskren Chernev .num_parents = 1, 2728cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2729cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2730cbe63bfdSIskren Chernev }, 2731cbe63bfdSIskren Chernev }, 2732cbe63bfdSIskren Chernev }; 2733cbe63bfdSIskren Chernev 2734cbe63bfdSIskren Chernev static struct clk_branch gcc_sdcc2_ahb_clk = { 2735cbe63bfdSIskren Chernev .halt_reg = 0x1e008, 2736cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2737cbe63bfdSIskren Chernev .clkr = { 2738cbe63bfdSIskren Chernev .enable_reg = 0x1e008, 2739cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2740cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2741cbe63bfdSIskren Chernev .name = "gcc_sdcc2_ahb_clk", 2742cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2743cbe63bfdSIskren Chernev }, 2744cbe63bfdSIskren Chernev }, 2745cbe63bfdSIskren Chernev }; 2746cbe63bfdSIskren Chernev 2747cbe63bfdSIskren Chernev static struct clk_branch gcc_sdcc2_apps_clk = { 2748cbe63bfdSIskren Chernev .halt_reg = 0x1e004, 2749cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2750cbe63bfdSIskren Chernev .clkr = { 2751cbe63bfdSIskren Chernev .enable_reg = 0x1e004, 2752cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2753cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2754cbe63bfdSIskren Chernev .name = "gcc_sdcc2_apps_clk", 2755cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2756cbe63bfdSIskren Chernev &gcc_sdcc2_apps_clk_src.clkr.hw, 2757cbe63bfdSIskren Chernev }, 2758cbe63bfdSIskren Chernev .num_parents = 1, 2759cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2760cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2761cbe63bfdSIskren Chernev }, 2762cbe63bfdSIskren Chernev }, 2763cbe63bfdSIskren Chernev }; 2764cbe63bfdSIskren Chernev 2765cbe63bfdSIskren Chernev static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 2766cbe63bfdSIskren Chernev .halt_reg = 0x2b06c, 2767cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 2768cbe63bfdSIskren Chernev .hwcg_reg = 0x2b06c, 2769cbe63bfdSIskren Chernev .hwcg_bit = 1, 2770cbe63bfdSIskren Chernev .clkr = { 2771cbe63bfdSIskren Chernev .enable_reg = 0x79004, 2772cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2773cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2774cbe63bfdSIskren Chernev .name = "gcc_sys_noc_cpuss_ahb_clk", 2775cbe63bfdSIskren Chernev .flags = CLK_IS_CRITICAL, 2776cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2777cbe63bfdSIskren Chernev }, 2778cbe63bfdSIskren Chernev }, 2779cbe63bfdSIskren Chernev }; 2780cbe63bfdSIskren Chernev 2781cbe63bfdSIskren Chernev static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { 2782cbe63bfdSIskren Chernev .halt_reg = 0x45098, 2783cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2784cbe63bfdSIskren Chernev .clkr = { 2785cbe63bfdSIskren Chernev .enable_reg = 0x45098, 2786cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2787cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2788cbe63bfdSIskren Chernev .name = "gcc_sys_noc_ufs_phy_axi_clk", 2789cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2790cbe63bfdSIskren Chernev &gcc_ufs_phy_axi_clk_src.clkr.hw, 2791cbe63bfdSIskren Chernev }, 2792cbe63bfdSIskren Chernev .num_parents = 1, 2793cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2794cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2795cbe63bfdSIskren Chernev }, 2796cbe63bfdSIskren Chernev }, 2797cbe63bfdSIskren Chernev }; 2798cbe63bfdSIskren Chernev 2799cbe63bfdSIskren Chernev static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { 2800cbe63bfdSIskren Chernev .halt_reg = 0x1a080, 2801cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2802cbe63bfdSIskren Chernev .hwcg_reg = 0x1a080, 2803cbe63bfdSIskren Chernev .hwcg_bit = 1, 2804cbe63bfdSIskren Chernev .clkr = { 2805cbe63bfdSIskren Chernev .enable_reg = 0x1a080, 2806cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2807cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2808cbe63bfdSIskren Chernev .name = "gcc_sys_noc_usb3_prim_axi_clk", 2809cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2810cbe63bfdSIskren Chernev &gcc_usb30_prim_master_clk_src.clkr.hw, 2811cbe63bfdSIskren Chernev }, 2812cbe63bfdSIskren Chernev .num_parents = 1, 2813cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2814cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2815cbe63bfdSIskren Chernev }, 2816cbe63bfdSIskren Chernev }, 2817cbe63bfdSIskren Chernev }; 2818cbe63bfdSIskren Chernev 2819cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_clkref_clk = { 2820cbe63bfdSIskren Chernev .halt_reg = 0x8c000, 2821cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2822cbe63bfdSIskren Chernev .clkr = { 2823cbe63bfdSIskren Chernev .enable_reg = 0x8c000, 2824cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2825cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2826cbe63bfdSIskren Chernev .name = "gcc_ufs_clkref_clk", 2827cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2828cbe63bfdSIskren Chernev }, 2829cbe63bfdSIskren Chernev }, 2830cbe63bfdSIskren Chernev }; 2831cbe63bfdSIskren Chernev 2832cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_ahb_clk = { 2833cbe63bfdSIskren Chernev .halt_reg = 0x45014, 2834cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2835cbe63bfdSIskren Chernev .hwcg_reg = 0x45014, 2836cbe63bfdSIskren Chernev .hwcg_bit = 1, 2837cbe63bfdSIskren Chernev .clkr = { 2838cbe63bfdSIskren Chernev .enable_reg = 0x45014, 2839cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2840cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2841cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_ahb_clk", 2842cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2843cbe63bfdSIskren Chernev }, 2844cbe63bfdSIskren Chernev }, 2845cbe63bfdSIskren Chernev }; 2846cbe63bfdSIskren Chernev 2847cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_axi_clk = { 2848cbe63bfdSIskren Chernev .halt_reg = 0x45010, 2849cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2850cbe63bfdSIskren Chernev .hwcg_reg = 0x45010, 2851cbe63bfdSIskren Chernev .hwcg_bit = 1, 2852cbe63bfdSIskren Chernev .clkr = { 2853cbe63bfdSIskren Chernev .enable_reg = 0x45010, 2854cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2855cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2856cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_axi_clk", 2857cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2858cbe63bfdSIskren Chernev &gcc_ufs_phy_axi_clk_src.clkr.hw, 2859cbe63bfdSIskren Chernev }, 2860cbe63bfdSIskren Chernev .num_parents = 1, 2861cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2862cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2863cbe63bfdSIskren Chernev }, 2864cbe63bfdSIskren Chernev }, 2865cbe63bfdSIskren Chernev }; 2866cbe63bfdSIskren Chernev 2867cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2868cbe63bfdSIskren Chernev .halt_reg = 0x45044, 2869cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2870cbe63bfdSIskren Chernev .hwcg_reg = 0x45044, 2871cbe63bfdSIskren Chernev .hwcg_bit = 1, 2872cbe63bfdSIskren Chernev .clkr = { 2873cbe63bfdSIskren Chernev .enable_reg = 0x45044, 2874cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2875cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2876cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_ice_core_clk", 2877cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2878cbe63bfdSIskren Chernev &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2879cbe63bfdSIskren Chernev }, 2880cbe63bfdSIskren Chernev .num_parents = 1, 2881cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2882cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2883cbe63bfdSIskren Chernev }, 2884cbe63bfdSIskren Chernev }, 2885cbe63bfdSIskren Chernev }; 2886cbe63bfdSIskren Chernev 2887cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2888cbe63bfdSIskren Chernev .halt_reg = 0x45078, 2889cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2890cbe63bfdSIskren Chernev .hwcg_reg = 0x45078, 2891cbe63bfdSIskren Chernev .hwcg_bit = 1, 2892cbe63bfdSIskren Chernev .clkr = { 2893cbe63bfdSIskren Chernev .enable_reg = 0x45078, 2894cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2895cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2896cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_phy_aux_clk", 2897cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2898cbe63bfdSIskren Chernev &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2899cbe63bfdSIskren Chernev }, 2900cbe63bfdSIskren Chernev .num_parents = 1, 2901cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2902cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2903cbe63bfdSIskren Chernev }, 2904cbe63bfdSIskren Chernev }, 2905cbe63bfdSIskren Chernev }; 2906cbe63bfdSIskren Chernev 2907cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2908cbe63bfdSIskren Chernev .halt_reg = 0x4501c, 2909cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_SKIP, 2910cbe63bfdSIskren Chernev .clkr = { 2911cbe63bfdSIskren Chernev .enable_reg = 0x4501c, 2912cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2913cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2914cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_rx_symbol_0_clk", 2915cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2916cbe63bfdSIskren Chernev }, 2917cbe63bfdSIskren Chernev }, 2918cbe63bfdSIskren Chernev }; 2919cbe63bfdSIskren Chernev 2920cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2921cbe63bfdSIskren Chernev .halt_reg = 0x45018, 2922cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_SKIP, 2923cbe63bfdSIskren Chernev .clkr = { 2924cbe63bfdSIskren Chernev .enable_reg = 0x45018, 2925cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2926cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2927cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_tx_symbol_0_clk", 2928cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2929cbe63bfdSIskren Chernev }, 2930cbe63bfdSIskren Chernev }, 2931cbe63bfdSIskren Chernev }; 2932cbe63bfdSIskren Chernev 2933cbe63bfdSIskren Chernev static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2934cbe63bfdSIskren Chernev .halt_reg = 0x45040, 2935cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2936cbe63bfdSIskren Chernev .hwcg_reg = 0x45040, 2937cbe63bfdSIskren Chernev .hwcg_bit = 1, 2938cbe63bfdSIskren Chernev .clkr = { 2939cbe63bfdSIskren Chernev .enable_reg = 0x45040, 2940cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2941cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2942cbe63bfdSIskren Chernev .name = "gcc_ufs_phy_unipro_core_clk", 2943cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2944cbe63bfdSIskren Chernev &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2945cbe63bfdSIskren Chernev }, 2946cbe63bfdSIskren Chernev .num_parents = 1, 2947cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2948cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2949cbe63bfdSIskren Chernev }, 2950cbe63bfdSIskren Chernev }, 2951cbe63bfdSIskren Chernev }; 2952cbe63bfdSIskren Chernev 2953cbe63bfdSIskren Chernev static struct clk_branch gcc_usb30_prim_master_clk = { 2954cbe63bfdSIskren Chernev .halt_reg = 0x1a010, 2955cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2956cbe63bfdSIskren Chernev .clkr = { 2957cbe63bfdSIskren Chernev .enable_reg = 0x1a010, 2958cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2959cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2960cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_master_clk", 2961cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2962cbe63bfdSIskren Chernev &gcc_usb30_prim_master_clk_src.clkr.hw, 2963cbe63bfdSIskren Chernev }, 2964cbe63bfdSIskren Chernev .num_parents = 1, 2965cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2966cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2967cbe63bfdSIskren Chernev }, 2968cbe63bfdSIskren Chernev }, 2969cbe63bfdSIskren Chernev }; 2970cbe63bfdSIskren Chernev 2971cbe63bfdSIskren Chernev static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2972cbe63bfdSIskren Chernev .halt_reg = 0x1a018, 2973cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2974cbe63bfdSIskren Chernev .clkr = { 2975cbe63bfdSIskren Chernev .enable_reg = 0x1a018, 2976cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2977cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2978cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_mock_utmi_clk", 2979cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 2980cbe63bfdSIskren Chernev &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2981cbe63bfdSIskren Chernev }, 2982cbe63bfdSIskren Chernev .num_parents = 1, 2983cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 2984cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2985cbe63bfdSIskren Chernev }, 2986cbe63bfdSIskren Chernev }, 2987cbe63bfdSIskren Chernev }; 2988cbe63bfdSIskren Chernev 2989cbe63bfdSIskren Chernev static struct clk_branch gcc_usb30_prim_sleep_clk = { 2990cbe63bfdSIskren Chernev .halt_reg = 0x1a014, 2991cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 2992cbe63bfdSIskren Chernev .clkr = { 2993cbe63bfdSIskren Chernev .enable_reg = 0x1a014, 2994cbe63bfdSIskren Chernev .enable_mask = BIT(0), 2995cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 2996cbe63bfdSIskren Chernev .name = "gcc_usb30_prim_sleep_clk", 2997cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 2998cbe63bfdSIskren Chernev }, 2999cbe63bfdSIskren Chernev }, 3000cbe63bfdSIskren Chernev }; 3001cbe63bfdSIskren Chernev 3002cbe63bfdSIskren Chernev static struct clk_branch gcc_usb3_prim_clkref_clk = { 3003cbe63bfdSIskren Chernev .halt_reg = 0x9f000, 3004cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3005cbe63bfdSIskren Chernev .clkr = { 3006cbe63bfdSIskren Chernev .enable_reg = 0x9f000, 3007cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3008cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3009cbe63bfdSIskren Chernev .name = "gcc_usb3_prim_clkref_clk", 3010cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3011cbe63bfdSIskren Chernev }, 3012cbe63bfdSIskren Chernev }, 3013cbe63bfdSIskren Chernev }; 3014cbe63bfdSIskren Chernev 3015cbe63bfdSIskren Chernev static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3016cbe63bfdSIskren Chernev .halt_reg = 0x1a054, 3017cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3018cbe63bfdSIskren Chernev .clkr = { 3019cbe63bfdSIskren Chernev .enable_reg = 0x1a054, 3020cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3021cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3022cbe63bfdSIskren Chernev .name = "gcc_usb3_prim_phy_com_aux_clk", 3023cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 3024cbe63bfdSIskren Chernev &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3025cbe63bfdSIskren Chernev }, 3026cbe63bfdSIskren Chernev .num_parents = 1, 3027cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 3028cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3029cbe63bfdSIskren Chernev }, 3030cbe63bfdSIskren Chernev }, 3031cbe63bfdSIskren Chernev }; 3032cbe63bfdSIskren Chernev 3033cbe63bfdSIskren Chernev static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3034cbe63bfdSIskren Chernev .halt_reg = 0x1a058, 3035cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_SKIP, 3036cbe63bfdSIskren Chernev .hwcg_reg = 0x1a058, 3037cbe63bfdSIskren Chernev .hwcg_bit = 1, 3038cbe63bfdSIskren Chernev .clkr = { 3039cbe63bfdSIskren Chernev .enable_reg = 0x1a058, 3040cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3041cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3042cbe63bfdSIskren Chernev .name = "gcc_usb3_prim_phy_pipe_clk", 3043cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3044cbe63bfdSIskren Chernev }, 3045cbe63bfdSIskren Chernev }, 3046cbe63bfdSIskren Chernev }; 3047cbe63bfdSIskren Chernev 3048cbe63bfdSIskren Chernev static struct clk_branch gcc_vcodec0_axi_clk = { 3049cbe63bfdSIskren Chernev .halt_reg = 0x6e008, 3050cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3051cbe63bfdSIskren Chernev .clkr = { 3052cbe63bfdSIskren Chernev .enable_reg = 0x6e008, 3053cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3054cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3055cbe63bfdSIskren Chernev .name = "gcc_vcodec0_axi_clk", 3056cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3057cbe63bfdSIskren Chernev }, 3058cbe63bfdSIskren Chernev }, 3059cbe63bfdSIskren Chernev }; 3060cbe63bfdSIskren Chernev 3061cbe63bfdSIskren Chernev static struct clk_branch gcc_venus_ahb_clk = { 3062cbe63bfdSIskren Chernev .halt_reg = 0x6e010, 3063cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3064cbe63bfdSIskren Chernev .clkr = { 3065cbe63bfdSIskren Chernev .enable_reg = 0x6e010, 3066cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3067cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3068cbe63bfdSIskren Chernev .name = "gcc_venus_ahb_clk", 3069cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3070cbe63bfdSIskren Chernev }, 3071cbe63bfdSIskren Chernev }, 3072cbe63bfdSIskren Chernev }; 3073cbe63bfdSIskren Chernev 3074cbe63bfdSIskren Chernev static struct clk_branch gcc_venus_ctl_axi_clk = { 3075cbe63bfdSIskren Chernev .halt_reg = 0x6e004, 3076cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3077cbe63bfdSIskren Chernev .clkr = { 3078cbe63bfdSIskren Chernev .enable_reg = 0x6e004, 3079cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3080cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3081cbe63bfdSIskren Chernev .name = "gcc_venus_ctl_axi_clk", 3082cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3083cbe63bfdSIskren Chernev }, 3084cbe63bfdSIskren Chernev }, 3085cbe63bfdSIskren Chernev }; 3086cbe63bfdSIskren Chernev 3087cbe63bfdSIskren Chernev static struct clk_branch gcc_video_ahb_clk = { 3088cbe63bfdSIskren Chernev .halt_reg = 0x17004, 3089cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3090cbe63bfdSIskren Chernev .hwcg_reg = 0x17004, 3091cbe63bfdSIskren Chernev .hwcg_bit = 1, 3092cbe63bfdSIskren Chernev .clkr = { 3093cbe63bfdSIskren Chernev .enable_reg = 0x17004, 3094cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3095cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3096cbe63bfdSIskren Chernev .name = "gcc_video_ahb_clk", 3097cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3098cbe63bfdSIskren Chernev }, 3099cbe63bfdSIskren Chernev }, 3100cbe63bfdSIskren Chernev }; 3101cbe63bfdSIskren Chernev 3102cbe63bfdSIskren Chernev static struct clk_branch gcc_video_axi0_clk = { 3103cbe63bfdSIskren Chernev .halt_reg = 0x1701c, 3104cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3105cbe63bfdSIskren Chernev .hwcg_reg = 0x1701c, 3106cbe63bfdSIskren Chernev .hwcg_bit = 1, 3107cbe63bfdSIskren Chernev .clkr = { 3108cbe63bfdSIskren Chernev .enable_reg = 0x1701c, 3109cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3110cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3111cbe63bfdSIskren Chernev .name = "gcc_video_axi0_clk", 3112cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3113cbe63bfdSIskren Chernev }, 3114cbe63bfdSIskren Chernev }, 3115cbe63bfdSIskren Chernev }; 3116cbe63bfdSIskren Chernev 3117cbe63bfdSIskren Chernev static struct clk_branch gcc_video_throttle_core_clk = { 3118cbe63bfdSIskren Chernev .halt_reg = 0x17068, 3119cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_VOTED, 3120cbe63bfdSIskren Chernev .hwcg_reg = 0x17068, 3121cbe63bfdSIskren Chernev .hwcg_bit = 1, 3122cbe63bfdSIskren Chernev .clkr = { 3123cbe63bfdSIskren Chernev .enable_reg = 0x79004, 3124cbe63bfdSIskren Chernev .enable_mask = BIT(28), 3125cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3126cbe63bfdSIskren Chernev .name = "gcc_video_throttle_core_clk", 3127cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3128cbe63bfdSIskren Chernev }, 3129cbe63bfdSIskren Chernev }, 3130cbe63bfdSIskren Chernev }; 3131cbe63bfdSIskren Chernev 3132cbe63bfdSIskren Chernev static struct clk_branch gcc_video_vcodec0_sys_clk = { 3133cbe63bfdSIskren Chernev .halt_reg = 0x580a4, 3134cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT_DELAY, 3135cbe63bfdSIskren Chernev .hwcg_reg = 0x580a4, 3136cbe63bfdSIskren Chernev .hwcg_bit = 1, 3137cbe63bfdSIskren Chernev .clkr = { 3138cbe63bfdSIskren Chernev .enable_reg = 0x580a4, 3139cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3140cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3141cbe63bfdSIskren Chernev .name = "gcc_video_vcodec0_sys_clk", 3142cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 3143cbe63bfdSIskren Chernev &gcc_video_venus_clk_src.clkr.hw, 3144cbe63bfdSIskren Chernev }, 3145cbe63bfdSIskren Chernev .num_parents = 1, 3146cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 3147cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3148cbe63bfdSIskren Chernev }, 3149cbe63bfdSIskren Chernev }, 3150cbe63bfdSIskren Chernev }; 3151cbe63bfdSIskren Chernev 3152cbe63bfdSIskren Chernev static struct clk_branch gcc_video_venus_ctl_clk = { 3153cbe63bfdSIskren Chernev .halt_reg = 0x5808c, 3154cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3155cbe63bfdSIskren Chernev .clkr = { 3156cbe63bfdSIskren Chernev .enable_reg = 0x5808c, 3157cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3158cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3159cbe63bfdSIskren Chernev .name = "gcc_video_venus_ctl_clk", 3160cbe63bfdSIskren Chernev .parent_hws = (const struct clk_hw *[]){ 3161cbe63bfdSIskren Chernev &gcc_video_venus_clk_src.clkr.hw, 3162cbe63bfdSIskren Chernev }, 3163cbe63bfdSIskren Chernev .num_parents = 1, 3164cbe63bfdSIskren Chernev .flags = CLK_SET_RATE_PARENT, 3165cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3166cbe63bfdSIskren Chernev }, 3167cbe63bfdSIskren Chernev }, 3168cbe63bfdSIskren Chernev }; 3169cbe63bfdSIskren Chernev 3170cbe63bfdSIskren Chernev static struct clk_branch gcc_video_xo_clk = { 3171cbe63bfdSIskren Chernev .halt_reg = 0x17024, 3172cbe63bfdSIskren Chernev .halt_check = BRANCH_HALT, 3173cbe63bfdSIskren Chernev .clkr = { 3174cbe63bfdSIskren Chernev .enable_reg = 0x17024, 3175cbe63bfdSIskren Chernev .enable_mask = BIT(0), 3176cbe63bfdSIskren Chernev .hw.init = &(struct clk_init_data){ 3177cbe63bfdSIskren Chernev .name = "gcc_video_xo_clk", 3178cbe63bfdSIskren Chernev .ops = &clk_branch2_ops, 3179cbe63bfdSIskren Chernev }, 3180cbe63bfdSIskren Chernev }, 3181cbe63bfdSIskren Chernev }; 3182cbe63bfdSIskren Chernev 3183cbe63bfdSIskren Chernev static struct gdsc gcc_camss_top_gdsc = { 3184cbe63bfdSIskren Chernev .gdscr = 0x58004, 3185cbe63bfdSIskren Chernev .pd = { 3186cbe63bfdSIskren Chernev .name = "gcc_camss_top", 3187cbe63bfdSIskren Chernev }, 3188cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3189cbe63bfdSIskren Chernev }; 3190cbe63bfdSIskren Chernev 3191cbe63bfdSIskren Chernev static struct gdsc gcc_ufs_phy_gdsc = { 3192cbe63bfdSIskren Chernev .gdscr = 0x45004, 3193cbe63bfdSIskren Chernev .pd = { 3194cbe63bfdSIskren Chernev .name = "gcc_ufs_phy", 3195cbe63bfdSIskren Chernev }, 3196cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3197cbe63bfdSIskren Chernev }; 3198cbe63bfdSIskren Chernev 3199cbe63bfdSIskren Chernev static struct gdsc gcc_usb30_prim_gdsc = { 3200cbe63bfdSIskren Chernev .gdscr = 0x1a004, 3201cbe63bfdSIskren Chernev .pd = { 3202cbe63bfdSIskren Chernev .name = "gcc_usb30_prim", 3203cbe63bfdSIskren Chernev }, 3204cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3205cbe63bfdSIskren Chernev }; 3206cbe63bfdSIskren Chernev 3207cbe63bfdSIskren Chernev static struct gdsc gcc_vcodec0_gdsc = { 3208cbe63bfdSIskren Chernev .gdscr = 0x58098, 3209cbe63bfdSIskren Chernev .pd = { 3210cbe63bfdSIskren Chernev .name = "gcc_vcodec0", 3211cbe63bfdSIskren Chernev }, 3212cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3213cbe63bfdSIskren Chernev }; 3214cbe63bfdSIskren Chernev 3215cbe63bfdSIskren Chernev static struct gdsc gcc_venus_gdsc = { 3216cbe63bfdSIskren Chernev .gdscr = 0x5807c, 3217cbe63bfdSIskren Chernev .pd = { 3218cbe63bfdSIskren Chernev .name = "gcc_venus", 3219cbe63bfdSIskren Chernev }, 3220cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3221cbe63bfdSIskren Chernev }; 3222cbe63bfdSIskren Chernev 3223cbe63bfdSIskren Chernev static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = { 3224cbe63bfdSIskren Chernev .gdscr = 0x7d060, 3225cbe63bfdSIskren Chernev .pd = { 3226cbe63bfdSIskren Chernev .name = "hlos1_vote_turing_mmu_tbu1", 3227cbe63bfdSIskren Chernev }, 3228cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3229cbe63bfdSIskren Chernev .flags = VOTABLE, 3230cbe63bfdSIskren Chernev }; 3231cbe63bfdSIskren Chernev 3232cbe63bfdSIskren Chernev static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { 3233e41bdd18SShawn Guo .gdscr = 0x7d07c, 3234cbe63bfdSIskren Chernev .pd = { 3235cbe63bfdSIskren Chernev .name = "hlos1_vote_turing_mmu_tbu0", 3236cbe63bfdSIskren Chernev }, 3237cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3238cbe63bfdSIskren Chernev .flags = VOTABLE, 3239cbe63bfdSIskren Chernev }; 3240cbe63bfdSIskren Chernev 3241cbe63bfdSIskren Chernev static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = { 3242cbe63bfdSIskren Chernev .gdscr = 0x7d074, 3243cbe63bfdSIskren Chernev .pd = { 3244cbe63bfdSIskren Chernev .name = "hlos1_vote_mm_snoc_mmu_tbu_rt", 3245cbe63bfdSIskren Chernev }, 3246cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3247cbe63bfdSIskren Chernev .flags = VOTABLE, 3248cbe63bfdSIskren Chernev }; 3249cbe63bfdSIskren Chernev 3250cbe63bfdSIskren Chernev static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = { 3251cbe63bfdSIskren Chernev .gdscr = 0x7d078, 3252cbe63bfdSIskren Chernev .pd = { 3253cbe63bfdSIskren Chernev .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt", 3254cbe63bfdSIskren Chernev }, 3255cbe63bfdSIskren Chernev .pwrsts = PWRSTS_OFF_ON, 3256cbe63bfdSIskren Chernev .flags = VOTABLE, 3257cbe63bfdSIskren Chernev }; 3258cbe63bfdSIskren Chernev 3259cbe63bfdSIskren Chernev static struct clk_regmap *gcc_sm6115_clocks[] = { 3260cbe63bfdSIskren Chernev [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr, 3261cbe63bfdSIskren Chernev [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr, 3262cbe63bfdSIskren Chernev [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr, 3263cbe63bfdSIskren Chernev [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3264cbe63bfdSIskren Chernev [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, 3265cbe63bfdSIskren Chernev [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, 3266cbe63bfdSIskren Chernev [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 3267cbe63bfdSIskren Chernev [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 3268cbe63bfdSIskren Chernev [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, 3269cbe63bfdSIskren Chernev [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, 3270cbe63bfdSIskren Chernev [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr, 3271cbe63bfdSIskren Chernev [GCC_CAMSS_CAMNOC_NTS_XO_CLK] = &gcc_camss_camnoc_nts_xo_clk.clkr, 3272cbe63bfdSIskren Chernev [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr, 3273cbe63bfdSIskren Chernev [GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr, 3274cbe63bfdSIskren Chernev [GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr, 3275cbe63bfdSIskren Chernev [GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr, 3276cbe63bfdSIskren Chernev [GCC_CAMSS_CPHY_2_CLK] = &gcc_camss_cphy_2_clk.clkr, 3277cbe63bfdSIskren Chernev [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 3278cbe63bfdSIskren Chernev [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr, 3279cbe63bfdSIskren Chernev [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, 3280cbe63bfdSIskren Chernev [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr, 3281cbe63bfdSIskren Chernev [GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr, 3282cbe63bfdSIskren Chernev [GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr, 3283cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 3284cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr, 3285cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 3286cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr, 3287cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, 3288cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr, 3289cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr, 3290cbe63bfdSIskren Chernev [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr, 3291cbe63bfdSIskren Chernev [GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr, 3292cbe63bfdSIskren Chernev [GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr, 3293cbe63bfdSIskren Chernev [GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr, 3294cbe63bfdSIskren Chernev [GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr, 3295cbe63bfdSIskren Chernev [GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr, 3296cbe63bfdSIskren Chernev [GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr, 3297cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr, 3298cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr, 3299cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr, 3300cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr, 3301cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr, 3302cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr, 3303cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr, 3304cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr, 3305cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr, 3306cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr, 3307cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_2_CLK] = &gcc_camss_tfe_2_clk.clkr, 3308cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_2_CLK_SRC] = &gcc_camss_tfe_2_clk_src.clkr, 3309cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_2_CPHY_RX_CLK] = &gcc_camss_tfe_2_cphy_rx_clk.clkr, 3310cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_2_CSID_CLK] = &gcc_camss_tfe_2_csid_clk.clkr, 3311cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_2_CSID_CLK_SRC] = &gcc_camss_tfe_2_csid_clk_src.clkr, 3312cbe63bfdSIskren Chernev [GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr, 3313cbe63bfdSIskren Chernev [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 3314cbe63bfdSIskren Chernev [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, 3315cbe63bfdSIskren Chernev [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3316cbe63bfdSIskren Chernev [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, 3317cbe63bfdSIskren Chernev [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, 3318cbe63bfdSIskren Chernev [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 3319cbe63bfdSIskren Chernev [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 3320cbe63bfdSIskren Chernev [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3321cbe63bfdSIskren Chernev [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, 3322cbe63bfdSIskren Chernev [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 3323cbe63bfdSIskren Chernev [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3324cbe63bfdSIskren Chernev [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3325cbe63bfdSIskren Chernev [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3326cbe63bfdSIskren Chernev [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3327cbe63bfdSIskren Chernev [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3328cbe63bfdSIskren Chernev [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3329cbe63bfdSIskren Chernev [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 3330cbe63bfdSIskren Chernev [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3331cbe63bfdSIskren Chernev [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3332cbe63bfdSIskren Chernev [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, 3333cbe63bfdSIskren Chernev [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3334cbe63bfdSIskren Chernev [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3335cbe63bfdSIskren Chernev [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, 3336cbe63bfdSIskren Chernev [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3337cbe63bfdSIskren Chernev [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3338cbe63bfdSIskren Chernev [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3339cbe63bfdSIskren Chernev [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3340cbe63bfdSIskren Chernev [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3341cbe63bfdSIskren Chernev [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3342cbe63bfdSIskren Chernev [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3343cbe63bfdSIskren Chernev [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3344cbe63bfdSIskren Chernev [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr, 3345cbe63bfdSIskren Chernev [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3346cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 3347cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 3348cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3349cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3350cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3351cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3352cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3353cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3354cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3355cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3356cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3357cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3358cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3359cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3360cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3361cbe63bfdSIskren Chernev [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3362cbe63bfdSIskren Chernev [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3363cbe63bfdSIskren Chernev [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3364cbe63bfdSIskren Chernev [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 3365cbe63bfdSIskren Chernev [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 3366cbe63bfdSIskren Chernev [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 3367cbe63bfdSIskren Chernev [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3368cbe63bfdSIskren Chernev [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3369cbe63bfdSIskren Chernev [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3370cbe63bfdSIskren Chernev [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 3371cbe63bfdSIskren Chernev [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, 3372cbe63bfdSIskren Chernev [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, 3373cbe63bfdSIskren Chernev [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, 3374cbe63bfdSIskren Chernev [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3375cbe63bfdSIskren Chernev [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3376cbe63bfdSIskren Chernev [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3377cbe63bfdSIskren Chernev [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3378cbe63bfdSIskren Chernev [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3379cbe63bfdSIskren Chernev [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3380cbe63bfdSIskren Chernev [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3381cbe63bfdSIskren Chernev [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3382cbe63bfdSIskren Chernev [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3383cbe63bfdSIskren Chernev [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3384cbe63bfdSIskren Chernev [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 3385cbe63bfdSIskren Chernev &gcc_ufs_phy_unipro_core_clk_src.clkr, 3386cbe63bfdSIskren Chernev [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3387cbe63bfdSIskren Chernev [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3388cbe63bfdSIskren Chernev [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3389cbe63bfdSIskren Chernev [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 3390cbe63bfdSIskren Chernev &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3391cbe63bfdSIskren Chernev [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = 3392cbe63bfdSIskren Chernev &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3393cbe63bfdSIskren Chernev [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3394cbe63bfdSIskren Chernev [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 3395cbe63bfdSIskren Chernev [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3396cbe63bfdSIskren Chernev [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3397cbe63bfdSIskren Chernev [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3398cbe63bfdSIskren Chernev [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr, 3399cbe63bfdSIskren Chernev [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr, 3400cbe63bfdSIskren Chernev [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr, 3401cbe63bfdSIskren Chernev [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 3402cbe63bfdSIskren Chernev [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3403cbe63bfdSIskren Chernev [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, 3404cbe63bfdSIskren Chernev [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr, 3405cbe63bfdSIskren Chernev [GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr, 3406cbe63bfdSIskren Chernev [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr, 3407cbe63bfdSIskren Chernev [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 3408cbe63bfdSIskren Chernev [GPLL0] = &gpll0.clkr, 3409cbe63bfdSIskren Chernev [GPLL0_OUT_AUX2] = &gpll0_out_aux2.clkr, 3410cbe63bfdSIskren Chernev [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr, 3411cbe63bfdSIskren Chernev [GPLL10] = &gpll10.clkr, 3412cbe63bfdSIskren Chernev [GPLL10_OUT_MAIN] = &gpll10_out_main.clkr, 3413cbe63bfdSIskren Chernev [GPLL11] = &gpll11.clkr, 3414cbe63bfdSIskren Chernev [GPLL11_OUT_MAIN] = &gpll11_out_main.clkr, 3415cbe63bfdSIskren Chernev [GPLL3] = &gpll3.clkr, 3416cbe63bfdSIskren Chernev [GPLL4] = &gpll4.clkr, 3417cbe63bfdSIskren Chernev [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr, 3418cbe63bfdSIskren Chernev [GPLL6] = &gpll6.clkr, 3419cbe63bfdSIskren Chernev [GPLL6_OUT_MAIN] = &gpll6_out_main.clkr, 3420cbe63bfdSIskren Chernev [GPLL7] = &gpll7.clkr, 3421cbe63bfdSIskren Chernev [GPLL7_OUT_MAIN] = &gpll7_out_main.clkr, 3422cbe63bfdSIskren Chernev [GPLL8] = &gpll8.clkr, 3423cbe63bfdSIskren Chernev [GPLL8_OUT_MAIN] = &gpll8_out_main.clkr, 3424cbe63bfdSIskren Chernev [GPLL9] = &gpll9.clkr, 3425cbe63bfdSIskren Chernev [GPLL9_OUT_MAIN] = &gpll9_out_main.clkr, 3426cbe63bfdSIskren Chernev }; 3427cbe63bfdSIskren Chernev 3428cbe63bfdSIskren Chernev static const struct qcom_reset_map gcc_sm6115_resets[] = { 3429cbe63bfdSIskren Chernev [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, 3430cbe63bfdSIskren Chernev [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, 3431cbe63bfdSIskren Chernev [GCC_SDCC1_BCR] = { 0x38000 }, 3432cbe63bfdSIskren Chernev [GCC_SDCC2_BCR] = { 0x1e000 }, 3433cbe63bfdSIskren Chernev [GCC_UFS_PHY_BCR] = { 0x45000 }, 3434cbe63bfdSIskren Chernev [GCC_USB30_PRIM_BCR] = { 0x1a000 }, 3435cbe63bfdSIskren Chernev [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, 3436cbe63bfdSIskren Chernev [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, 3437cbe63bfdSIskren Chernev [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, 3438cbe63bfdSIskren Chernev [GCC_VCODEC0_BCR] = { 0x58094 }, 3439cbe63bfdSIskren Chernev [GCC_VENUS_BCR] = { 0x58078 }, 3440cbe63bfdSIskren Chernev [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 }, 3441cbe63bfdSIskren Chernev }; 3442cbe63bfdSIskren Chernev 3443cbe63bfdSIskren Chernev static struct gdsc *gcc_sm6115_gdscs[] = { 3444cbe63bfdSIskren Chernev [GCC_CAMSS_TOP_GDSC] = &gcc_camss_top_gdsc, 3445cbe63bfdSIskren Chernev [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, 3446cbe63bfdSIskren Chernev [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 3447cbe63bfdSIskren Chernev [GCC_VCODEC0_GDSC] = &gcc_vcodec0_gdsc, 3448cbe63bfdSIskren Chernev [GCC_VENUS_GDSC] = &gcc_venus_gdsc, 3449cbe63bfdSIskren Chernev [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, 3450cbe63bfdSIskren Chernev [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc, 3451cbe63bfdSIskren Chernev [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc, 3452cbe63bfdSIskren Chernev [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc, 3453cbe63bfdSIskren Chernev }; 3454cbe63bfdSIskren Chernev 3455cbe63bfdSIskren Chernev static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3456cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3457cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3458cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3459cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3460cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3461cbe63bfdSIskren Chernev DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3462cbe63bfdSIskren Chernev }; 3463cbe63bfdSIskren Chernev 3464cbe63bfdSIskren Chernev static const struct regmap_config gcc_sm6115_regmap_config = { 3465cbe63bfdSIskren Chernev .reg_bits = 32, 3466cbe63bfdSIskren Chernev .reg_stride = 4, 3467cbe63bfdSIskren Chernev .val_bits = 32, 3468cbe63bfdSIskren Chernev .max_register = 0xc7000, 3469cbe63bfdSIskren Chernev .fast_io = true, 3470cbe63bfdSIskren Chernev }; 3471cbe63bfdSIskren Chernev 3472cbe63bfdSIskren Chernev static const struct qcom_cc_desc gcc_sm6115_desc = { 3473cbe63bfdSIskren Chernev .config = &gcc_sm6115_regmap_config, 3474cbe63bfdSIskren Chernev .clks = gcc_sm6115_clocks, 3475cbe63bfdSIskren Chernev .num_clks = ARRAY_SIZE(gcc_sm6115_clocks), 3476cbe63bfdSIskren Chernev .resets = gcc_sm6115_resets, 3477cbe63bfdSIskren Chernev .num_resets = ARRAY_SIZE(gcc_sm6115_resets), 3478cbe63bfdSIskren Chernev .gdscs = gcc_sm6115_gdscs, 3479cbe63bfdSIskren Chernev .num_gdscs = ARRAY_SIZE(gcc_sm6115_gdscs), 3480cbe63bfdSIskren Chernev }; 3481cbe63bfdSIskren Chernev 3482cbe63bfdSIskren Chernev static const struct of_device_id gcc_sm6115_match_table[] = { 3483cbe63bfdSIskren Chernev { .compatible = "qcom,gcc-sm6115" }, 3484cbe63bfdSIskren Chernev { } 3485cbe63bfdSIskren Chernev }; 3486cbe63bfdSIskren Chernev MODULE_DEVICE_TABLE(of, gcc_sm6115_match_table); 3487cbe63bfdSIskren Chernev 3488cbe63bfdSIskren Chernev static int gcc_sm6115_probe(struct platform_device *pdev) 3489cbe63bfdSIskren Chernev { 3490cbe63bfdSIskren Chernev struct regmap *regmap; 3491cbe63bfdSIskren Chernev int ret; 3492cbe63bfdSIskren Chernev 3493cbe63bfdSIskren Chernev regmap = qcom_cc_map(pdev, &gcc_sm6115_desc); 3494cbe63bfdSIskren Chernev if (IS_ERR(regmap)) 3495cbe63bfdSIskren Chernev return PTR_ERR(regmap); 3496cbe63bfdSIskren Chernev 3497cbe63bfdSIskren Chernev ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3498cbe63bfdSIskren Chernev ARRAY_SIZE(gcc_dfs_clocks)); 3499cbe63bfdSIskren Chernev if (ret) 3500cbe63bfdSIskren Chernev return ret; 3501cbe63bfdSIskren Chernev 3502cbe63bfdSIskren Chernev clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config); 3503cbe63bfdSIskren Chernev clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config); 3504cbe63bfdSIskren Chernev clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config); 3505cbe63bfdSIskren Chernev clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config); 3506cbe63bfdSIskren Chernev 3507cbe63bfdSIskren Chernev return qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap); 3508cbe63bfdSIskren Chernev } 3509cbe63bfdSIskren Chernev 3510cbe63bfdSIskren Chernev static struct platform_driver gcc_sm6115_driver = { 3511cbe63bfdSIskren Chernev .probe = gcc_sm6115_probe, 3512cbe63bfdSIskren Chernev .driver = { 3513cbe63bfdSIskren Chernev .name = "gcc-sm6115", 3514cbe63bfdSIskren Chernev .of_match_table = gcc_sm6115_match_table, 3515cbe63bfdSIskren Chernev }, 3516cbe63bfdSIskren Chernev }; 3517cbe63bfdSIskren Chernev 3518cbe63bfdSIskren Chernev static int __init gcc_sm6115_init(void) 3519cbe63bfdSIskren Chernev { 3520cbe63bfdSIskren Chernev return platform_driver_register(&gcc_sm6115_driver); 3521cbe63bfdSIskren Chernev } 3522cbe63bfdSIskren Chernev subsys_initcall(gcc_sm6115_init); 3523cbe63bfdSIskren Chernev 3524cbe63bfdSIskren Chernev static void __exit gcc_sm6115_exit(void) 3525cbe63bfdSIskren Chernev { 3526cbe63bfdSIskren Chernev platform_driver_unregister(&gcc_sm6115_driver); 3527cbe63bfdSIskren Chernev } 3528cbe63bfdSIskren Chernev module_exit(gcc_sm6115_exit); 3529cbe63bfdSIskren Chernev 3530cbe63bfdSIskren Chernev MODULE_DESCRIPTION("QTI GCC SM6115 and SM4250 Driver"); 3531cbe63bfdSIskren Chernev MODULE_LICENSE("GPL v2"); 3532cbe63bfdSIskren Chernev MODULE_ALIAS("platform:gcc-sm6115"); 3533