1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/of_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,sdx75-gcc.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-rcg.h" 16 #include "clk-regmap.h" 17 #include "clk-regmap-divider.h" 18 #include "clk-regmap-mux.h" 19 #include "clk-regmap-phy-mux.h" 20 #include "gdsc.h" 21 #include "reset.h" 22 23 enum { 24 DT_BI_TCXO, 25 DT_SLEEP_CLK, 26 DT_EMAC0_SGMIIPHY_MAC_RCLK, 27 DT_EMAC0_SGMIIPHY_MAC_TCLK, 28 DT_EMAC0_SGMIIPHY_RCLK, 29 DT_EMAC0_SGMIIPHY_TCLK, 30 DT_EMAC1_SGMIIPHY_MAC_RCLK, 31 DT_EMAC1_SGMIIPHY_MAC_TCLK, 32 DT_EMAC1_SGMIIPHY_RCLK, 33 DT_EMAC1_SGMIIPHY_TCLK, 34 DT_PCIE20_PHY_AUX_CLK, 35 DT_PCIE_1_PIPE_CLK, 36 DT_PCIE_2_PIPE_CLK, 37 DT_PCIE_PIPE_CLK, 38 DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 39 }; 40 41 enum { 42 P_BI_TCXO, 43 P_EMAC0_SGMIIPHY_MAC_RCLK, 44 P_EMAC0_SGMIIPHY_MAC_TCLK, 45 P_EMAC0_SGMIIPHY_RCLK, 46 P_EMAC0_SGMIIPHY_TCLK, 47 P_EMAC1_SGMIIPHY_MAC_RCLK, 48 P_EMAC1_SGMIIPHY_MAC_TCLK, 49 P_EMAC1_SGMIIPHY_RCLK, 50 P_EMAC1_SGMIIPHY_TCLK, 51 P_GPLL0_OUT_EVEN, 52 P_GPLL0_OUT_MAIN, 53 P_GPLL4_OUT_MAIN, 54 P_GPLL5_OUT_MAIN, 55 P_GPLL6_OUT_MAIN, 56 P_GPLL8_OUT_MAIN, 57 P_PCIE20_PHY_AUX_CLK, 58 P_PCIE_1_PIPE_CLK, 59 P_PCIE_2_PIPE_CLK, 60 P_PCIE_PIPE_CLK, 61 P_SLEEP_CLK, 62 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 63 }; 64 65 static struct clk_alpha_pll gpll0 = { 66 .offset = 0x0, 67 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 68 .clkr = { 69 .enable_reg = 0x7d000, 70 .enable_mask = BIT(0), 71 .hw.init = &(const struct clk_init_data) { 72 .name = "gpll0", 73 .parent_data = &(const struct clk_parent_data) { 74 .index = DT_BI_TCXO, 75 }, 76 .num_parents = 1, 77 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 78 }, 79 }, 80 }; 81 82 static const struct clk_div_table post_div_table_gpll0_out_even[] = { 83 { 0x1, 2 }, 84 { } 85 }; 86 87 static struct clk_alpha_pll_postdiv gpll0_out_even = { 88 .offset = 0x0, 89 .post_div_shift = 10, 90 .post_div_table = post_div_table_gpll0_out_even, 91 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even), 92 .width = 4, 93 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 94 .clkr.hw.init = &(const struct clk_init_data) { 95 .name = "gpll0_out_even", 96 .parent_hws = (const struct clk_hw*[]) { 97 &gpll0.clkr.hw, 98 }, 99 .num_parents = 1, 100 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 101 }, 102 }; 103 104 static struct clk_alpha_pll gpll4 = { 105 .offset = 0x4000, 106 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 107 .clkr = { 108 .enable_reg = 0x7d000, 109 .enable_mask = BIT(4), 110 .hw.init = &(const struct clk_init_data) { 111 .name = "gpll4", 112 .parent_data = &(const struct clk_parent_data) { 113 .index = DT_BI_TCXO, 114 }, 115 .num_parents = 1, 116 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 117 }, 118 }, 119 }; 120 121 static struct clk_alpha_pll gpll5 = { 122 .offset = 0x5000, 123 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 124 .clkr = { 125 .enable_reg = 0x7d000, 126 .enable_mask = BIT(5), 127 .hw.init = &(const struct clk_init_data) { 128 .name = "gpll5", 129 .parent_data = &(const struct clk_parent_data) { 130 .index = DT_BI_TCXO, 131 }, 132 .num_parents = 1, 133 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 134 }, 135 }, 136 }; 137 138 static struct clk_alpha_pll gpll6 = { 139 .offset = 0x6000, 140 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 141 .clkr = { 142 .enable_reg = 0x7d000, 143 .enable_mask = BIT(6), 144 .hw.init = &(const struct clk_init_data) { 145 .name = "gpll6", 146 .parent_data = &(const struct clk_parent_data) { 147 .index = DT_BI_TCXO, 148 }, 149 .num_parents = 1, 150 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 151 }, 152 }, 153 }; 154 155 static struct clk_alpha_pll gpll8 = { 156 .offset = 0x8000, 157 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 158 .clkr = { 159 .enable_reg = 0x7d000, 160 .enable_mask = BIT(8), 161 .hw.init = &(const struct clk_init_data) { 162 .name = "gpll8", 163 .parent_data = &(const struct clk_parent_data) { 164 .index = DT_BI_TCXO, 165 }, 166 .num_parents = 1, 167 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 168 }, 169 }, 170 }; 171 172 static const struct parent_map gcc_parent_map_0[] = { 173 { P_BI_TCXO, 0 }, 174 { P_GPLL0_OUT_MAIN, 1 }, 175 { P_GPLL0_OUT_EVEN, 6 }, 176 }; 177 178 static const struct clk_parent_data gcc_parent_data_0[] = { 179 { .index = DT_BI_TCXO }, 180 { .hw = &gpll0.clkr.hw }, 181 { .hw = &gpll0_out_even.clkr.hw }, 182 }; 183 184 static const struct parent_map gcc_parent_map_1[] = { 185 { P_BI_TCXO, 0 }, 186 { P_GPLL0_OUT_MAIN, 1 }, 187 { P_GPLL4_OUT_MAIN, 2 }, 188 { P_GPLL5_OUT_MAIN, 5 }, 189 { P_GPLL0_OUT_EVEN, 6 }, 190 }; 191 192 static const struct clk_parent_data gcc_parent_data_1[] = { 193 { .index = DT_BI_TCXO }, 194 { .hw = &gpll0.clkr.hw }, 195 { .hw = &gpll4.clkr.hw }, 196 { .hw = &gpll5.clkr.hw }, 197 { .hw = &gpll0_out_even.clkr.hw }, 198 }; 199 200 static const struct parent_map gcc_parent_map_2[] = { 201 { P_BI_TCXO, 0 }, 202 { P_GPLL0_OUT_MAIN, 1 }, 203 { P_SLEEP_CLK, 5 }, 204 { P_GPLL0_OUT_EVEN, 6 }, 205 }; 206 207 static const struct clk_parent_data gcc_parent_data_2[] = { 208 { .index = DT_BI_TCXO }, 209 { .hw = &gpll0.clkr.hw }, 210 { .index = DT_SLEEP_CLK }, 211 { .hw = &gpll0_out_even.clkr.hw }, 212 }; 213 214 static const struct parent_map gcc_parent_map_3[] = { 215 { P_BI_TCXO, 0 }, 216 { P_SLEEP_CLK, 5 }, 217 }; 218 219 static const struct clk_parent_data gcc_parent_data_3[] = { 220 { .index = DT_BI_TCXO }, 221 { .index = DT_SLEEP_CLK }, 222 }; 223 224 static const struct parent_map gcc_parent_map_4[] = { 225 { P_BI_TCXO, 0 }, 226 { P_GPLL0_OUT_MAIN, 1 }, 227 { P_SLEEP_CLK, 5 }, 228 }; 229 230 static const struct clk_parent_data gcc_parent_data_4[] = { 231 { .index = DT_BI_TCXO }, 232 { .hw = &gpll0.clkr.hw }, 233 { .index = DT_SLEEP_CLK }, 234 }; 235 236 static const struct parent_map gcc_parent_map_5[] = { 237 { P_EMAC0_SGMIIPHY_RCLK, 0 }, 238 { P_BI_TCXO, 2 }, 239 }; 240 241 static const struct clk_parent_data gcc_parent_data_5[] = { 242 { .index = DT_EMAC0_SGMIIPHY_RCLK }, 243 { .index = DT_BI_TCXO }, 244 }; 245 246 static const struct parent_map gcc_parent_map_6[] = { 247 { P_EMAC0_SGMIIPHY_TCLK, 0 }, 248 { P_BI_TCXO, 2 }, 249 }; 250 251 static const struct clk_parent_data gcc_parent_data_6[] = { 252 { .index = DT_EMAC0_SGMIIPHY_TCLK }, 253 { .index = DT_BI_TCXO }, 254 }; 255 256 static const struct parent_map gcc_parent_map_7[] = { 257 { P_EMAC0_SGMIIPHY_MAC_RCLK, 0 }, 258 { P_BI_TCXO, 2 }, 259 }; 260 261 static const struct clk_parent_data gcc_parent_data_7[] = { 262 { .index = DT_EMAC0_SGMIIPHY_MAC_RCLK }, 263 { .index = DT_BI_TCXO }, 264 }; 265 266 static const struct parent_map gcc_parent_map_8[] = { 267 { P_EMAC0_SGMIIPHY_MAC_TCLK, 0 }, 268 { P_BI_TCXO, 2 }, 269 }; 270 271 static const struct clk_parent_data gcc_parent_data_8[] = { 272 { .index = DT_EMAC0_SGMIIPHY_MAC_TCLK }, 273 { .index = DT_BI_TCXO }, 274 }; 275 276 static const struct parent_map gcc_parent_map_9[] = { 277 { P_EMAC1_SGMIIPHY_RCLK, 0 }, 278 { P_BI_TCXO, 2 }, 279 }; 280 281 static const struct clk_parent_data gcc_parent_data_9[] = { 282 { .index = DT_EMAC1_SGMIIPHY_RCLK }, 283 { .index = DT_BI_TCXO }, 284 }; 285 286 static const struct parent_map gcc_parent_map_10[] = { 287 { P_EMAC1_SGMIIPHY_TCLK, 0 }, 288 { P_BI_TCXO, 2 }, 289 }; 290 291 static const struct clk_parent_data gcc_parent_data_10[] = { 292 { .index = DT_EMAC1_SGMIIPHY_TCLK }, 293 { .index = DT_BI_TCXO }, 294 }; 295 296 static const struct parent_map gcc_parent_map_11[] = { 297 { P_EMAC1_SGMIIPHY_MAC_RCLK, 0 }, 298 { P_BI_TCXO, 2 }, 299 }; 300 301 static const struct clk_parent_data gcc_parent_data_11[] = { 302 { .index = DT_EMAC1_SGMIIPHY_MAC_RCLK }, 303 { .index = DT_BI_TCXO }, 304 }; 305 306 static const struct parent_map gcc_parent_map_12[] = { 307 { P_EMAC1_SGMIIPHY_MAC_TCLK, 0 }, 308 { P_BI_TCXO, 2 }, 309 }; 310 311 static const struct clk_parent_data gcc_parent_data_12[] = { 312 { .index = DT_EMAC1_SGMIIPHY_MAC_TCLK }, 313 { .index = DT_BI_TCXO }, 314 }; 315 316 static const struct parent_map gcc_parent_map_15[] = { 317 { P_PCIE20_PHY_AUX_CLK, 0 }, 318 { P_BI_TCXO, 2 }, 319 }; 320 321 static const struct clk_parent_data gcc_parent_data_15[] = { 322 { .index = DT_PCIE20_PHY_AUX_CLK }, 323 { .index = DT_BI_TCXO }, 324 }; 325 326 static const struct parent_map gcc_parent_map_17[] = { 327 { P_BI_TCXO, 0 }, 328 { P_GPLL0_OUT_MAIN, 1 }, 329 { P_GPLL6_OUT_MAIN, 2 }, 330 { P_GPLL0_OUT_EVEN, 6 }, 331 }; 332 333 static const struct clk_parent_data gcc_parent_data_17[] = { 334 { .index = DT_BI_TCXO }, 335 { .hw = &gpll0.clkr.hw }, 336 { .hw = &gpll6.clkr.hw }, 337 { .hw = &gpll0_out_even.clkr.hw }, 338 }; 339 340 static const struct parent_map gcc_parent_map_18[] = { 341 { P_BI_TCXO, 0 }, 342 { P_GPLL0_OUT_MAIN, 1 }, 343 { P_GPLL8_OUT_MAIN, 2 }, 344 { P_GPLL0_OUT_EVEN, 6 }, 345 }; 346 347 static const struct clk_parent_data gcc_parent_data_18[] = { 348 { .index = DT_BI_TCXO }, 349 { .hw = &gpll0.clkr.hw }, 350 { .hw = &gpll8.clkr.hw }, 351 { .hw = &gpll0_out_even.clkr.hw }, 352 }; 353 354 static const struct parent_map gcc_parent_map_19[] = { 355 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 356 { P_BI_TCXO, 2 }, 357 }; 358 359 static const struct clk_parent_data gcc_parent_data_19[] = { 360 { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK }, 361 { .index = DT_BI_TCXO }, 362 }; 363 364 static struct clk_regmap_mux gcc_emac0_cc_sgmiiphy_rx_clk_src = { 365 .reg = 0x71060, 366 .shift = 0, 367 .width = 2, 368 .parent_map = gcc_parent_map_5, 369 .clkr = { 370 .hw.init = &(const struct clk_init_data) { 371 .name = "gcc_emac0_cc_sgmiiphy_rx_clk_src", 372 .parent_data = gcc_parent_data_5, 373 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 374 .ops = &clk_regmap_mux_closest_ops, 375 }, 376 }, 377 }; 378 379 static struct clk_regmap_mux gcc_emac0_cc_sgmiiphy_tx_clk_src = { 380 .reg = 0x71058, 381 .shift = 0, 382 .width = 2, 383 .parent_map = gcc_parent_map_6, 384 .clkr = { 385 .hw.init = &(const struct clk_init_data) { 386 .name = "gcc_emac0_cc_sgmiiphy_tx_clk_src", 387 .parent_data = gcc_parent_data_6, 388 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 389 .ops = &clk_regmap_mux_closest_ops, 390 }, 391 }, 392 }; 393 394 static struct clk_regmap_mux gcc_emac0_sgmiiphy_mac_rclk_src = { 395 .reg = 0x71098, 396 .shift = 0, 397 .width = 2, 398 .parent_map = gcc_parent_map_7, 399 .clkr = { 400 .hw.init = &(const struct clk_init_data) { 401 .name = "gcc_emac0_sgmiiphy_mac_rclk_src", 402 .parent_data = gcc_parent_data_7, 403 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 404 .ops = &clk_regmap_mux_closest_ops, 405 }, 406 }, 407 }; 408 409 static struct clk_regmap_mux gcc_emac0_sgmiiphy_mac_tclk_src = { 410 .reg = 0x71094, 411 .shift = 0, 412 .width = 2, 413 .parent_map = gcc_parent_map_8, 414 .clkr = { 415 .hw.init = &(const struct clk_init_data) { 416 .name = "gcc_emac0_sgmiiphy_mac_tclk_src", 417 .parent_data = gcc_parent_data_8, 418 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 419 .ops = &clk_regmap_mux_closest_ops, 420 }, 421 }, 422 }; 423 424 static struct clk_regmap_mux gcc_emac1_cc_sgmiiphy_rx_clk_src = { 425 .reg = 0x72060, 426 .shift = 0, 427 .width = 2, 428 .parent_map = gcc_parent_map_9, 429 .clkr = { 430 .hw.init = &(const struct clk_init_data) { 431 .name = "gcc_emac1_cc_sgmiiphy_rx_clk_src", 432 .parent_data = gcc_parent_data_9, 433 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 434 .ops = &clk_regmap_mux_closest_ops, 435 }, 436 }, 437 }; 438 439 static struct clk_regmap_mux gcc_emac1_cc_sgmiiphy_tx_clk_src = { 440 .reg = 0x72058, 441 .shift = 0, 442 .width = 2, 443 .parent_map = gcc_parent_map_10, 444 .clkr = { 445 .hw.init = &(const struct clk_init_data) { 446 .name = "gcc_emac1_cc_sgmiiphy_tx_clk_src", 447 .parent_data = gcc_parent_data_10, 448 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 449 .ops = &clk_regmap_mux_closest_ops, 450 }, 451 }, 452 }; 453 454 static struct clk_regmap_mux gcc_emac1_sgmiiphy_mac_rclk_src = { 455 .reg = 0x72098, 456 .shift = 0, 457 .width = 2, 458 .parent_map = gcc_parent_map_11, 459 .clkr = { 460 .hw.init = &(const struct clk_init_data) { 461 .name = "gcc_emac1_sgmiiphy_mac_rclk_src", 462 .parent_data = gcc_parent_data_11, 463 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 464 .ops = &clk_regmap_mux_closest_ops, 465 }, 466 }, 467 }; 468 469 static struct clk_regmap_mux gcc_emac1_sgmiiphy_mac_tclk_src = { 470 .reg = 0x72094, 471 .shift = 0, 472 .width = 2, 473 .parent_map = gcc_parent_map_12, 474 .clkr = { 475 .hw.init = &(const struct clk_init_data) { 476 .name = "gcc_emac1_sgmiiphy_mac_tclk_src", 477 .parent_data = gcc_parent_data_12, 478 .num_parents = ARRAY_SIZE(gcc_parent_data_12), 479 .ops = &clk_regmap_mux_closest_ops, 480 }, 481 }, 482 }; 483 484 static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = { 485 .reg = 0x67084, 486 .clkr = { 487 .hw.init = &(const struct clk_init_data) { 488 .name = "gcc_pcie_1_pipe_clk_src", 489 .parent_data = &(const struct clk_parent_data) { 490 .index = DT_PCIE_1_PIPE_CLK, 491 }, 492 .num_parents = 1, 493 .ops = &clk_regmap_phy_mux_ops, 494 }, 495 }, 496 }; 497 498 static struct clk_regmap_phy_mux gcc_pcie_2_pipe_clk_src = { 499 .reg = 0x68050, 500 .clkr = { 501 .hw.init = &(const struct clk_init_data) { 502 .name = "gcc_pcie_2_pipe_clk_src", 503 .parent_data = &(const struct clk_parent_data) { 504 .index = DT_PCIE_2_PIPE_CLK, 505 }, 506 .num_parents = 1, 507 .ops = &clk_regmap_phy_mux_ops, 508 }, 509 }, 510 }; 511 512 static struct clk_regmap_mux gcc_pcie_aux_clk_src = { 513 .reg = 0x53074, 514 .shift = 0, 515 .width = 2, 516 .parent_map = gcc_parent_map_15, 517 .clkr = { 518 .hw.init = &(const struct clk_init_data) { 519 .name = "gcc_pcie_aux_clk_src", 520 .parent_data = gcc_parent_data_15, 521 .num_parents = ARRAY_SIZE(gcc_parent_data_15), 522 .ops = &clk_regmap_mux_closest_ops, 523 }, 524 }, 525 }; 526 527 static struct clk_regmap_phy_mux gcc_pcie_pipe_clk_src = { 528 .reg = 0x53058, 529 .clkr = { 530 .hw.init = &(const struct clk_init_data) { 531 .name = "gcc_pcie_pipe_clk_src", 532 .parent_data = &(const struct clk_parent_data) { 533 .index = DT_PCIE_PIPE_CLK, 534 }, 535 .num_parents = 1, 536 .ops = &clk_regmap_phy_mux_ops, 537 }, 538 }, 539 }; 540 541 static struct clk_regmap_mux gcc_usb3_phy_pipe_clk_src = { 542 .reg = 0x27070, 543 .shift = 0, 544 .width = 2, 545 .parent_map = gcc_parent_map_19, 546 .clkr = { 547 .hw.init = &(const struct clk_init_data) { 548 .name = "gcc_usb3_phy_pipe_clk_src", 549 .parent_data = gcc_parent_data_19, 550 .num_parents = ARRAY_SIZE(gcc_parent_data_19), 551 .ops = &clk_regmap_mux_closest_ops, 552 }, 553 }, 554 }; 555 556 static const struct freq_tbl ftbl_gcc_eee_emac0_clk_src[] = { 557 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 558 { } 559 }; 560 561 static struct clk_rcg2 gcc_eee_emac0_clk_src = { 562 .cmd_rcgr = 0x710b0, 563 .mnd_width = 16, 564 .hid_width = 5, 565 .parent_map = gcc_parent_map_2, 566 .freq_tbl = ftbl_gcc_eee_emac0_clk_src, 567 .clkr.hw.init = &(const struct clk_init_data) { 568 .name = "gcc_eee_emac0_clk_src", 569 .parent_data = gcc_parent_data_2, 570 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 571 .ops = &clk_rcg2_shared_ops, 572 }, 573 }; 574 575 static struct clk_rcg2 gcc_eee_emac1_clk_src = { 576 .cmd_rcgr = 0x720b0, 577 .mnd_width = 16, 578 .hid_width = 5, 579 .parent_map = gcc_parent_map_2, 580 .freq_tbl = ftbl_gcc_eee_emac0_clk_src, 581 .clkr.hw.init = &(const struct clk_init_data) { 582 .name = "gcc_eee_emac1_clk_src", 583 .parent_data = gcc_parent_data_2, 584 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 585 .ops = &clk_rcg2_shared_ops, 586 }, 587 }; 588 589 static const struct freq_tbl ftbl_gcc_emac0_phy_aux_clk_src[] = { 590 F(19200000, P_BI_TCXO, 1, 0, 0), 591 { } 592 }; 593 594 static struct clk_rcg2 gcc_emac0_phy_aux_clk_src = { 595 .cmd_rcgr = 0x7102c, 596 .mnd_width = 0, 597 .hid_width = 5, 598 .parent_map = gcc_parent_map_4, 599 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 600 .clkr.hw.init = &(const struct clk_init_data) { 601 .name = "gcc_emac0_phy_aux_clk_src", 602 .parent_data = gcc_parent_data_4, 603 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 604 .ops = &clk_rcg2_shared_ops, 605 }, 606 }; 607 608 static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] = { 609 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 610 F(125000000, P_GPLL4_OUT_MAIN, 4, 0, 0), 611 F(230400000, P_GPLL5_OUT_MAIN, 3.5, 0, 0), 612 { } 613 }; 614 615 static struct clk_rcg2 gcc_emac0_ptp_clk_src = { 616 .cmd_rcgr = 0x7107c, 617 .mnd_width = 16, 618 .hid_width = 5, 619 .parent_map = gcc_parent_map_1, 620 .freq_tbl = ftbl_gcc_emac0_ptp_clk_src, 621 .clkr.hw.init = &(const struct clk_init_data) { 622 .name = "gcc_emac0_ptp_clk_src", 623 .parent_data = gcc_parent_data_1, 624 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 625 .ops = &clk_rcg2_shared_ops, 626 }, 627 }; 628 629 static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] = { 630 F(5000000, P_GPLL0_OUT_EVEN, 10, 1, 6), 631 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 632 F(125000000, P_GPLL4_OUT_MAIN, 4, 0, 0), 633 F(250000000, P_GPLL4_OUT_MAIN, 2, 0, 0), 634 { } 635 }; 636 637 static struct clk_rcg2 gcc_emac0_rgmii_clk_src = { 638 .cmd_rcgr = 0x71064, 639 .mnd_width = 16, 640 .hid_width = 5, 641 .parent_map = gcc_parent_map_1, 642 .freq_tbl = ftbl_gcc_emac0_rgmii_clk_src, 643 .clkr.hw.init = &(const struct clk_init_data) { 644 .name = "gcc_emac0_rgmii_clk_src", 645 .parent_data = gcc_parent_data_1, 646 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 647 .ops = &clk_rcg2_shared_ops, 648 }, 649 }; 650 651 static struct clk_rcg2 gcc_emac1_phy_aux_clk_src = { 652 .cmd_rcgr = 0x7202c, 653 .mnd_width = 0, 654 .hid_width = 5, 655 .parent_map = gcc_parent_map_4, 656 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 657 .clkr.hw.init = &(const struct clk_init_data) { 658 .name = "gcc_emac1_phy_aux_clk_src", 659 .parent_data = gcc_parent_data_4, 660 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 661 .ops = &clk_rcg2_shared_ops, 662 }, 663 }; 664 665 static struct clk_rcg2 gcc_emac1_ptp_clk_src = { 666 .cmd_rcgr = 0x7207c, 667 .mnd_width = 16, 668 .hid_width = 5, 669 .parent_map = gcc_parent_map_1, 670 .freq_tbl = ftbl_gcc_emac0_ptp_clk_src, 671 .clkr.hw.init = &(const struct clk_init_data) { 672 .name = "gcc_emac1_ptp_clk_src", 673 .parent_data = gcc_parent_data_1, 674 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 675 .ops = &clk_rcg2_shared_ops, 676 }, 677 }; 678 679 static struct clk_rcg2 gcc_emac1_rgmii_clk_src = { 680 .cmd_rcgr = 0x72064, 681 .mnd_width = 16, 682 .hid_width = 5, 683 .parent_map = gcc_parent_map_1, 684 .freq_tbl = ftbl_gcc_emac0_rgmii_clk_src, 685 .clkr.hw.init = &(const struct clk_init_data) { 686 .name = "gcc_emac1_rgmii_clk_src", 687 .parent_data = gcc_parent_data_1, 688 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 689 .ops = &clk_rcg2_shared_ops, 690 }, 691 }; 692 693 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 694 F(19200000, P_BI_TCXO, 1, 0, 0), 695 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 696 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 697 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 698 { } 699 }; 700 701 static struct clk_rcg2 gcc_gp1_clk_src = { 702 .cmd_rcgr = 0x47004, 703 .mnd_width = 16, 704 .hid_width = 5, 705 .parent_map = gcc_parent_map_2, 706 .freq_tbl = ftbl_gcc_gp1_clk_src, 707 .clkr.hw.init = &(const struct clk_init_data) { 708 .name = "gcc_gp1_clk_src", 709 .parent_data = gcc_parent_data_2, 710 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 711 .ops = &clk_rcg2_shared_ops, 712 }, 713 }; 714 715 static struct clk_rcg2 gcc_gp2_clk_src = { 716 .cmd_rcgr = 0x48004, 717 .mnd_width = 16, 718 .hid_width = 5, 719 .parent_map = gcc_parent_map_2, 720 .freq_tbl = ftbl_gcc_gp1_clk_src, 721 .clkr.hw.init = &(const struct clk_init_data) { 722 .name = "gcc_gp2_clk_src", 723 .parent_data = gcc_parent_data_2, 724 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 725 .ops = &clk_rcg2_shared_ops, 726 }, 727 }; 728 729 static struct clk_rcg2 gcc_gp3_clk_src = { 730 .cmd_rcgr = 0x49004, 731 .mnd_width = 16, 732 .hid_width = 5, 733 .parent_map = gcc_parent_map_2, 734 .freq_tbl = ftbl_gcc_gp1_clk_src, 735 .clkr.hw.init = &(const struct clk_init_data) { 736 .name = "gcc_gp3_clk_src", 737 .parent_data = gcc_parent_data_2, 738 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 739 .ops = &clk_rcg2_shared_ops, 740 }, 741 }; 742 743 static struct clk_rcg2 gcc_pcie_1_aux_phy_clk_src = { 744 .cmd_rcgr = 0x67044, 745 .mnd_width = 16, 746 .hid_width = 5, 747 .parent_map = gcc_parent_map_3, 748 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 749 .clkr.hw.init = &(const struct clk_init_data) { 750 .name = "gcc_pcie_1_aux_phy_clk_src", 751 .parent_data = gcc_parent_data_3, 752 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 753 .ops = &clk_rcg2_shared_ops, 754 }, 755 }; 756 757 static const struct freq_tbl ftbl_gcc_pcie_1_phy_rchng_clk_src[] = { 758 F(19200000, P_BI_TCXO, 1, 0, 0), 759 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 760 { } 761 }; 762 763 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 764 .cmd_rcgr = 0x6706c, 765 .mnd_width = 0, 766 .hid_width = 5, 767 .parent_map = gcc_parent_map_2, 768 .freq_tbl = ftbl_gcc_pcie_1_phy_rchng_clk_src, 769 .clkr.hw.init = &(const struct clk_init_data) { 770 .name = "gcc_pcie_1_phy_rchng_clk_src", 771 .parent_data = gcc_parent_data_2, 772 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 773 .ops = &clk_rcg2_shared_ops, 774 }, 775 }; 776 777 static struct clk_rcg2 gcc_pcie_2_aux_phy_clk_src = { 778 .cmd_rcgr = 0x68064, 779 .mnd_width = 16, 780 .hid_width = 5, 781 .parent_map = gcc_parent_map_3, 782 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 783 .clkr.hw.init = &(const struct clk_init_data) { 784 .name = "gcc_pcie_2_aux_phy_clk_src", 785 .parent_data = gcc_parent_data_3, 786 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 787 .ops = &clk_rcg2_shared_ops, 788 }, 789 }; 790 791 static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = { 792 .cmd_rcgr = 0x68038, 793 .mnd_width = 0, 794 .hid_width = 5, 795 .parent_map = gcc_parent_map_2, 796 .freq_tbl = ftbl_gcc_pcie_1_phy_rchng_clk_src, 797 .clkr.hw.init = &(const struct clk_init_data) { 798 .name = "gcc_pcie_2_phy_rchng_clk_src", 799 .parent_data = gcc_parent_data_2, 800 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 801 .ops = &clk_rcg2_shared_ops, 802 }, 803 }; 804 805 static struct clk_rcg2 gcc_pcie_aux_phy_clk_src = { 806 .cmd_rcgr = 0x5305c, 807 .mnd_width = 16, 808 .hid_width = 5, 809 .parent_map = gcc_parent_map_3, 810 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 811 .clkr.hw.init = &(const struct clk_init_data) { 812 .name = "gcc_pcie_aux_phy_clk_src", 813 .parent_data = gcc_parent_data_3, 814 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 815 .ops = &clk_rcg2_shared_ops, 816 }, 817 }; 818 819 static struct clk_rcg2 gcc_pcie_rchng_phy_clk_src = { 820 .cmd_rcgr = 0x53078, 821 .mnd_width = 0, 822 .hid_width = 5, 823 .parent_map = gcc_parent_map_2, 824 .freq_tbl = ftbl_gcc_pcie_1_phy_rchng_clk_src, 825 .clkr.hw.init = &(const struct clk_init_data) { 826 .name = "gcc_pcie_rchng_phy_clk_src", 827 .parent_data = gcc_parent_data_2, 828 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 829 .ops = &clk_rcg2_shared_ops, 830 }, 831 }; 832 833 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 834 F(19200000, P_BI_TCXO, 1, 0, 0), 835 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 836 { } 837 }; 838 839 static struct clk_rcg2 gcc_pdm2_clk_src = { 840 .cmd_rcgr = 0x34010, 841 .mnd_width = 0, 842 .hid_width = 5, 843 .parent_map = gcc_parent_map_0, 844 .freq_tbl = ftbl_gcc_pdm2_clk_src, 845 .clkr.hw.init = &(const struct clk_init_data) { 846 .name = "gcc_pdm2_clk_src", 847 .parent_data = gcc_parent_data_0, 848 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 849 .ops = &clk_rcg2_shared_ops, 850 }, 851 }; 852 853 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 854 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 855 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 856 F(19200000, P_BI_TCXO, 1, 0, 0), 857 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 858 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 859 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 860 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 861 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 862 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 863 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 864 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 865 { } 866 }; 867 868 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 869 .name = "gcc_qupv3_wrap0_s0_clk_src", 870 .parent_data = gcc_parent_data_0, 871 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 872 .ops = &clk_rcg2_shared_ops, 873 }; 874 875 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 876 .cmd_rcgr = 0x6c010, 877 .mnd_width = 16, 878 .hid_width = 5, 879 .parent_map = gcc_parent_map_0, 880 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 881 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 882 }; 883 884 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 885 .name = "gcc_qupv3_wrap0_s1_clk_src", 886 .parent_data = gcc_parent_data_0, 887 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 888 .ops = &clk_rcg2_shared_ops, 889 }; 890 891 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 892 .cmd_rcgr = 0x6c148, 893 .mnd_width = 16, 894 .hid_width = 5, 895 .parent_map = gcc_parent_map_0, 896 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 897 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 898 }; 899 900 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 901 .name = "gcc_qupv3_wrap0_s2_clk_src", 902 .parent_data = gcc_parent_data_0, 903 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 904 .ops = &clk_rcg2_shared_ops, 905 }; 906 907 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 908 .cmd_rcgr = 0x6c280, 909 .mnd_width = 16, 910 .hid_width = 5, 911 .parent_map = gcc_parent_map_0, 912 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 913 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 914 }; 915 916 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 917 .name = "gcc_qupv3_wrap0_s3_clk_src", 918 .parent_data = gcc_parent_data_0, 919 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 920 .ops = &clk_rcg2_shared_ops, 921 }; 922 923 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 924 .cmd_rcgr = 0x6c3b8, 925 .mnd_width = 16, 926 .hid_width = 5, 927 .parent_map = gcc_parent_map_0, 928 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 929 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 930 }; 931 932 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 933 .name = "gcc_qupv3_wrap0_s4_clk_src", 934 .parent_data = gcc_parent_data_0, 935 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 936 .ops = &clk_rcg2_shared_ops, 937 }; 938 939 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 940 .cmd_rcgr = 0x6c4f0, 941 .mnd_width = 16, 942 .hid_width = 5, 943 .parent_map = gcc_parent_map_0, 944 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 945 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 946 }; 947 948 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 949 .name = "gcc_qupv3_wrap0_s5_clk_src", 950 .parent_data = gcc_parent_data_0, 951 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 952 .ops = &clk_rcg2_shared_ops, 953 }; 954 955 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 956 .cmd_rcgr = 0x6c628, 957 .mnd_width = 16, 958 .hid_width = 5, 959 .parent_map = gcc_parent_map_0, 960 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 961 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 962 }; 963 964 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 965 .name = "gcc_qupv3_wrap0_s6_clk_src", 966 .parent_data = gcc_parent_data_0, 967 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 968 .ops = &clk_rcg2_shared_ops, 969 }; 970 971 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 972 .cmd_rcgr = 0x6c760, 973 .mnd_width = 16, 974 .hid_width = 5, 975 .parent_map = gcc_parent_map_0, 976 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 977 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 978 }; 979 980 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 981 .name = "gcc_qupv3_wrap0_s7_clk_src", 982 .parent_data = gcc_parent_data_0, 983 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 984 .ops = &clk_rcg2_shared_ops, 985 }; 986 987 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 988 .cmd_rcgr = 0x6c898, 989 .mnd_width = 16, 990 .hid_width = 5, 991 .parent_map = gcc_parent_map_0, 992 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 993 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 994 }; 995 996 static struct clk_init_data gcc_qupv3_wrap0_s8_clk_src_init = { 997 .name = "gcc_qupv3_wrap0_s8_clk_src", 998 .parent_data = gcc_parent_data_0, 999 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1000 .ops = &clk_rcg2_shared_ops, 1001 }; 1002 1003 static struct clk_rcg2 gcc_qupv3_wrap0_s8_clk_src = { 1004 .cmd_rcgr = 0x6c9d0, 1005 .mnd_width = 16, 1006 .hid_width = 5, 1007 .parent_map = gcc_parent_map_0, 1008 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1009 .clkr.hw.init = &gcc_qupv3_wrap0_s8_clk_src_init, 1010 }; 1011 1012 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 1013 F(144000, P_BI_TCXO, 16, 3, 25), 1014 F(400000, P_BI_TCXO, 12, 1, 4), 1015 F(19200000, P_BI_TCXO, 1, 0, 0), 1016 F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), 1017 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 1018 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 1019 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 1020 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 1021 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 1022 { } 1023 }; 1024 1025 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 1026 .cmd_rcgr = 0x6b014, 1027 .mnd_width = 8, 1028 .hid_width = 5, 1029 .parent_map = gcc_parent_map_17, 1030 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 1031 .clkr.hw.init = &(const struct clk_init_data) { 1032 .name = "gcc_sdcc1_apps_clk_src", 1033 .parent_data = gcc_parent_data_17, 1034 .num_parents = ARRAY_SIZE(gcc_parent_data_17), 1035 .ops = &clk_rcg2_floor_ops, 1036 }, 1037 }; 1038 1039 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1040 F(400000, P_BI_TCXO, 12, 1, 4), 1041 F(19200000, P_BI_TCXO, 1, 0, 0), 1042 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 1043 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 1044 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 1045 F(202000000, P_GPLL8_OUT_MAIN, 4, 0, 0), 1046 { } 1047 }; 1048 1049 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1050 .cmd_rcgr = 0x6a018, 1051 .mnd_width = 8, 1052 .hid_width = 5, 1053 .parent_map = gcc_parent_map_18, 1054 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1055 .clkr.hw.init = &(const struct clk_init_data) { 1056 .name = "gcc_sdcc2_apps_clk_src", 1057 .parent_data = gcc_parent_data_18, 1058 .num_parents = ARRAY_SIZE(gcc_parent_data_18), 1059 .ops = &clk_rcg2_floor_ops, 1060 }, 1061 }; 1062 1063 static const struct freq_tbl ftbl_gcc_usb30_master_clk_src[] = { 1064 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0), 1065 { } 1066 }; 1067 1068 static struct clk_rcg2 gcc_usb30_master_clk_src = { 1069 .cmd_rcgr = 0x27034, 1070 .mnd_width = 8, 1071 .hid_width = 5, 1072 .parent_map = gcc_parent_map_0, 1073 .freq_tbl = ftbl_gcc_usb30_master_clk_src, 1074 .clkr.hw.init = &(const struct clk_init_data) { 1075 .name = "gcc_usb30_master_clk_src", 1076 .parent_data = gcc_parent_data_0, 1077 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1078 .ops = &clk_rcg2_shared_ops, 1079 }, 1080 }; 1081 1082 static struct clk_rcg2 gcc_usb30_mock_utmi_clk_src = { 1083 .cmd_rcgr = 0x2704c, 1084 .mnd_width = 0, 1085 .hid_width = 5, 1086 .parent_map = gcc_parent_map_0, 1087 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 1088 .clkr.hw.init = &(const struct clk_init_data) { 1089 .name = "gcc_usb30_mock_utmi_clk_src", 1090 .parent_data = gcc_parent_data_0, 1091 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1092 .ops = &clk_rcg2_shared_ops, 1093 }, 1094 }; 1095 1096 static const struct freq_tbl ftbl_gcc_usb3_phy_aux_clk_src[] = { 1097 F(1000000, P_BI_TCXO, 1, 5, 96), 1098 F(19200000, P_BI_TCXO, 1, 0, 0), 1099 { } 1100 }; 1101 1102 static struct clk_rcg2 gcc_usb3_phy_aux_clk_src = { 1103 .cmd_rcgr = 0x27074, 1104 .mnd_width = 16, 1105 .hid_width = 5, 1106 .parent_map = gcc_parent_map_3, 1107 .freq_tbl = ftbl_gcc_usb3_phy_aux_clk_src, 1108 .clkr.hw.init = &(const struct clk_init_data) { 1109 .name = "gcc_usb3_phy_aux_clk_src", 1110 .parent_data = gcc_parent_data_3, 1111 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1112 .ops = &clk_rcg2_shared_ops, 1113 }, 1114 }; 1115 1116 static struct clk_regmap_div gcc_pcie_1_pipe_div2_clk_src = { 1117 .reg = 0x67088, 1118 .shift = 0, 1119 .width = 4, 1120 .clkr.hw.init = &(const struct clk_init_data) { 1121 .name = "gcc_pcie_1_pipe_div2_clk_src", 1122 .parent_hws = (const struct clk_hw*[]) { 1123 &gcc_pcie_1_pipe_clk_src.clkr.hw, 1124 }, 1125 .num_parents = 1, 1126 .flags = CLK_SET_RATE_PARENT, 1127 .ops = &clk_regmap_div_ro_ops, 1128 }, 1129 }; 1130 1131 static struct clk_regmap_div gcc_pcie_2_pipe_div2_clk_src = { 1132 .reg = 0x68088, 1133 .shift = 0, 1134 .width = 4, 1135 .clkr.hw.init = &(const struct clk_init_data) { 1136 .name = "gcc_pcie_2_pipe_div2_clk_src", 1137 .parent_hws = (const struct clk_hw*[]) { 1138 &gcc_pcie_2_pipe_clk_src.clkr.hw, 1139 }, 1140 .num_parents = 1, 1141 .flags = CLK_SET_RATE_PARENT, 1142 .ops = &clk_regmap_div_ro_ops, 1143 }, 1144 }; 1145 1146 static struct clk_regmap_div gcc_usb30_mock_utmi_postdiv_clk_src = { 1147 .reg = 0x27064, 1148 .shift = 0, 1149 .width = 4, 1150 .clkr.hw.init = &(const struct clk_init_data) { 1151 .name = "gcc_usb30_mock_utmi_postdiv_clk_src", 1152 .parent_hws = (const struct clk_hw*[]) { 1153 &gcc_usb30_mock_utmi_clk_src.clkr.hw, 1154 }, 1155 .num_parents = 1, 1156 .flags = CLK_SET_RATE_PARENT, 1157 .ops = &clk_regmap_div_ro_ops, 1158 }, 1159 }; 1160 1161 static struct clk_branch gcc_boot_rom_ahb_clk = { 1162 .halt_reg = 0x37004, 1163 .halt_check = BRANCH_HALT_VOTED, 1164 .hwcg_reg = 0x37004, 1165 .hwcg_bit = 1, 1166 .clkr = { 1167 .enable_reg = 0x7d008, 1168 .enable_mask = BIT(26), 1169 .hw.init = &(const struct clk_init_data) { 1170 .name = "gcc_boot_rom_ahb_clk", 1171 .ops = &clk_branch2_ops, 1172 }, 1173 }, 1174 }; 1175 1176 static struct clk_branch gcc_eee_emac0_clk = { 1177 .halt_reg = 0x710ac, 1178 .halt_check = BRANCH_HALT, 1179 .clkr = { 1180 .enable_reg = 0x710ac, 1181 .enable_mask = BIT(0), 1182 .hw.init = &(const struct clk_init_data) { 1183 .name = "gcc_eee_emac0_clk", 1184 .parent_hws = (const struct clk_hw*[]) { 1185 &gcc_eee_emac0_clk_src.clkr.hw, 1186 }, 1187 .num_parents = 1, 1188 .flags = CLK_SET_RATE_PARENT, 1189 .ops = &clk_branch2_ops, 1190 }, 1191 }, 1192 }; 1193 1194 static struct clk_branch gcc_eee_emac1_clk = { 1195 .halt_reg = 0x720ac, 1196 .halt_check = BRANCH_HALT, 1197 .clkr = { 1198 .enable_reg = 0x720ac, 1199 .enable_mask = BIT(0), 1200 .hw.init = &(const struct clk_init_data) { 1201 .name = "gcc_eee_emac1_clk", 1202 .parent_hws = (const struct clk_hw*[]) { 1203 &gcc_eee_emac1_clk_src.clkr.hw, 1204 }, 1205 .num_parents = 1, 1206 .flags = CLK_SET_RATE_PARENT, 1207 .ops = &clk_branch2_ops, 1208 }, 1209 }, 1210 }; 1211 1212 static struct clk_branch gcc_emac0_axi_clk = { 1213 .halt_reg = 0x71018, 1214 .halt_check = BRANCH_HALT_VOTED, 1215 .hwcg_reg = 0x71018, 1216 .hwcg_bit = 1, 1217 .clkr = { 1218 .enable_reg = 0x71018, 1219 .enable_mask = BIT(0), 1220 .hw.init = &(const struct clk_init_data) { 1221 .name = "gcc_emac0_axi_clk", 1222 .ops = &clk_branch2_ops, 1223 }, 1224 }, 1225 }; 1226 1227 static struct clk_branch gcc_emac0_cc_sgmiiphy_rx_clk = { 1228 .halt_reg = 0x7105c, 1229 .halt_check = BRANCH_HALT_DELAY, 1230 .clkr = { 1231 .enable_reg = 0x7105c, 1232 .enable_mask = BIT(0), 1233 .hw.init = &(const struct clk_init_data) { 1234 .name = "gcc_emac0_cc_sgmiiphy_rx_clk", 1235 .parent_hws = (const struct clk_hw*[]) { 1236 &gcc_emac0_cc_sgmiiphy_rx_clk_src.clkr.hw, 1237 }, 1238 .num_parents = 1, 1239 .flags = CLK_SET_RATE_PARENT, 1240 .ops = &clk_branch2_ops, 1241 }, 1242 }, 1243 }; 1244 1245 static struct clk_branch gcc_emac0_cc_sgmiiphy_tx_clk = { 1246 .halt_reg = 0x71054, 1247 .halt_check = BRANCH_HALT_DELAY, 1248 .clkr = { 1249 .enable_reg = 0x71054, 1250 .enable_mask = BIT(0), 1251 .hw.init = &(const struct clk_init_data) { 1252 .name = "gcc_emac0_cc_sgmiiphy_tx_clk", 1253 .parent_hws = (const struct clk_hw*[]) { 1254 &gcc_emac0_cc_sgmiiphy_tx_clk_src.clkr.hw, 1255 }, 1256 .num_parents = 1, 1257 .flags = CLK_SET_RATE_PARENT, 1258 .ops = &clk_branch2_ops, 1259 }, 1260 }, 1261 }; 1262 1263 static struct clk_branch gcc_emac0_phy_aux_clk = { 1264 .halt_reg = 0x71028, 1265 .halt_check = BRANCH_HALT, 1266 .clkr = { 1267 .enable_reg = 0x71028, 1268 .enable_mask = BIT(0), 1269 .hw.init = &(const struct clk_init_data) { 1270 .name = "gcc_emac0_phy_aux_clk", 1271 .parent_hws = (const struct clk_hw*[]) { 1272 &gcc_emac0_phy_aux_clk_src.clkr.hw, 1273 }, 1274 .num_parents = 1, 1275 .flags = CLK_SET_RATE_PARENT, 1276 .ops = &clk_branch2_ops, 1277 }, 1278 }, 1279 }; 1280 1281 static struct clk_branch gcc_emac0_ptp_clk = { 1282 .halt_reg = 0x71044, 1283 .halt_check = BRANCH_HALT, 1284 .clkr = { 1285 .enable_reg = 0x71044, 1286 .enable_mask = BIT(0), 1287 .hw.init = &(const struct clk_init_data) { 1288 .name = "gcc_emac0_ptp_clk", 1289 .parent_hws = (const struct clk_hw*[]) { 1290 &gcc_emac0_ptp_clk_src.clkr.hw, 1291 }, 1292 .num_parents = 1, 1293 .flags = CLK_SET_RATE_PARENT, 1294 .ops = &clk_branch2_ops, 1295 }, 1296 }, 1297 }; 1298 1299 static struct clk_branch gcc_emac0_rgmii_clk = { 1300 .halt_reg = 0x71050, 1301 .halt_check = BRANCH_HALT, 1302 .clkr = { 1303 .enable_reg = 0x71050, 1304 .enable_mask = BIT(0), 1305 .hw.init = &(const struct clk_init_data) { 1306 .name = "gcc_emac0_rgmii_clk", 1307 .parent_hws = (const struct clk_hw*[]) { 1308 &gcc_emac0_rgmii_clk_src.clkr.hw, 1309 }, 1310 .num_parents = 1, 1311 .flags = CLK_SET_RATE_PARENT, 1312 .ops = &clk_branch2_ops, 1313 }, 1314 }, 1315 }; 1316 1317 static struct clk_branch gcc_emac0_rpcs_rx_clk = { 1318 .halt_reg = 0x710a0, 1319 .halt_check = BRANCH_HALT_DELAY, 1320 .clkr = { 1321 .enable_reg = 0x710a0, 1322 .enable_mask = BIT(0), 1323 .hw.init = &(const struct clk_init_data) { 1324 .name = "gcc_emac0_rpcs_rx_clk", 1325 .parent_hws = (const struct clk_hw*[]) { 1326 &gcc_emac0_sgmiiphy_mac_rclk_src.clkr.hw, 1327 }, 1328 .num_parents = 1, 1329 .flags = CLK_SET_RATE_PARENT, 1330 .ops = &clk_branch2_ops, 1331 }, 1332 }, 1333 }; 1334 1335 static struct clk_branch gcc_emac0_rpcs_tx_clk = { 1336 .halt_reg = 0x7109c, 1337 .halt_check = BRANCH_HALT_DELAY, 1338 .clkr = { 1339 .enable_reg = 0x7109c, 1340 .enable_mask = BIT(0), 1341 .hw.init = &(const struct clk_init_data) { 1342 .name = "gcc_emac0_rpcs_tx_clk", 1343 .parent_hws = (const struct clk_hw*[]) { 1344 &gcc_emac0_sgmiiphy_mac_tclk_src.clkr.hw, 1345 }, 1346 .num_parents = 1, 1347 .flags = CLK_SET_RATE_PARENT, 1348 .ops = &clk_branch2_ops, 1349 }, 1350 }, 1351 }; 1352 1353 static struct clk_branch gcc_emac0_slv_ahb_clk = { 1354 .halt_reg = 0x71024, 1355 .halt_check = BRANCH_HALT_VOTED, 1356 .hwcg_reg = 0x71024, 1357 .hwcg_bit = 1, 1358 .clkr = { 1359 .enable_reg = 0x71024, 1360 .enable_mask = BIT(0), 1361 .hw.init = &(const struct clk_init_data) { 1362 .name = "gcc_emac0_slv_ahb_clk", 1363 .ops = &clk_branch2_ops, 1364 }, 1365 }, 1366 }; 1367 1368 static struct clk_branch gcc_emac0_xgxs_rx_clk = { 1369 .halt_reg = 0x710a8, 1370 .halt_check = BRANCH_HALT_DELAY, 1371 .clkr = { 1372 .enable_reg = 0x710a8, 1373 .enable_mask = BIT(0), 1374 .hw.init = &(const struct clk_init_data) { 1375 .name = "gcc_emac0_xgxs_rx_clk", 1376 .parent_hws = (const struct clk_hw*[]) { 1377 &gcc_emac0_sgmiiphy_mac_rclk_src.clkr.hw, 1378 }, 1379 .num_parents = 1, 1380 .flags = CLK_SET_RATE_PARENT, 1381 .ops = &clk_branch2_ops, 1382 }, 1383 }, 1384 }; 1385 1386 static struct clk_branch gcc_emac0_xgxs_tx_clk = { 1387 .halt_reg = 0x710a4, 1388 .halt_check = BRANCH_HALT_DELAY, 1389 .clkr = { 1390 .enable_reg = 0x710a4, 1391 .enable_mask = BIT(0), 1392 .hw.init = &(const struct clk_init_data) { 1393 .name = "gcc_emac0_xgxs_tx_clk", 1394 .parent_hws = (const struct clk_hw*[]) { 1395 &gcc_emac0_sgmiiphy_mac_tclk_src.clkr.hw, 1396 }, 1397 .num_parents = 1, 1398 .flags = CLK_SET_RATE_PARENT, 1399 .ops = &clk_branch2_ops, 1400 }, 1401 }, 1402 }; 1403 1404 static struct clk_branch gcc_emac1_axi_clk = { 1405 .halt_reg = 0x72018, 1406 .halt_check = BRANCH_HALT_VOTED, 1407 .hwcg_reg = 0x72018, 1408 .hwcg_bit = 1, 1409 .clkr = { 1410 .enable_reg = 0x72018, 1411 .enable_mask = BIT(0), 1412 .hw.init = &(const struct clk_init_data) { 1413 .name = "gcc_emac1_axi_clk", 1414 .ops = &clk_branch2_ops, 1415 }, 1416 }, 1417 }; 1418 1419 static struct clk_branch gcc_emac1_cc_sgmiiphy_rx_clk = { 1420 .halt_reg = 0x7205c, 1421 .halt_check = BRANCH_HALT_DELAY, 1422 .clkr = { 1423 .enable_reg = 0x7205c, 1424 .enable_mask = BIT(0), 1425 .hw.init = &(const struct clk_init_data) { 1426 .name = "gcc_emac1_cc_sgmiiphy_rx_clk", 1427 .parent_hws = (const struct clk_hw*[]) { 1428 &gcc_emac1_cc_sgmiiphy_rx_clk_src.clkr.hw, 1429 }, 1430 .num_parents = 1, 1431 .flags = CLK_SET_RATE_PARENT, 1432 .ops = &clk_branch2_ops, 1433 }, 1434 }, 1435 }; 1436 1437 static struct clk_branch gcc_emac1_cc_sgmiiphy_tx_clk = { 1438 .halt_reg = 0x72054, 1439 .halt_check = BRANCH_HALT_DELAY, 1440 .clkr = { 1441 .enable_reg = 0x72054, 1442 .enable_mask = BIT(0), 1443 .hw.init = &(const struct clk_init_data) { 1444 .name = "gcc_emac1_cc_sgmiiphy_tx_clk", 1445 .parent_hws = (const struct clk_hw*[]) { 1446 &gcc_emac1_cc_sgmiiphy_tx_clk_src.clkr.hw, 1447 }, 1448 .num_parents = 1, 1449 .flags = CLK_SET_RATE_PARENT, 1450 .ops = &clk_branch2_ops, 1451 }, 1452 }, 1453 }; 1454 1455 static struct clk_branch gcc_emac1_phy_aux_clk = { 1456 .halt_reg = 0x72028, 1457 .halt_check = BRANCH_HALT, 1458 .clkr = { 1459 .enable_reg = 0x72028, 1460 .enable_mask = BIT(0), 1461 .hw.init = &(const struct clk_init_data) { 1462 .name = "gcc_emac1_phy_aux_clk", 1463 .parent_hws = (const struct clk_hw*[]) { 1464 &gcc_emac1_phy_aux_clk_src.clkr.hw, 1465 }, 1466 .num_parents = 1, 1467 .flags = CLK_SET_RATE_PARENT, 1468 .ops = &clk_branch2_ops, 1469 }, 1470 }, 1471 }; 1472 1473 static struct clk_branch gcc_emac1_ptp_clk = { 1474 .halt_reg = 0x72044, 1475 .halt_check = BRANCH_HALT, 1476 .clkr = { 1477 .enable_reg = 0x72044, 1478 .enable_mask = BIT(0), 1479 .hw.init = &(const struct clk_init_data) { 1480 .name = "gcc_emac1_ptp_clk", 1481 .parent_hws = (const struct clk_hw*[]) { 1482 &gcc_emac1_ptp_clk_src.clkr.hw, 1483 }, 1484 .num_parents = 1, 1485 .flags = CLK_SET_RATE_PARENT, 1486 .ops = &clk_branch2_ops, 1487 }, 1488 }, 1489 }; 1490 1491 static struct clk_branch gcc_emac1_rgmii_clk = { 1492 .halt_reg = 0x72050, 1493 .halt_check = BRANCH_HALT, 1494 .clkr = { 1495 .enable_reg = 0x72050, 1496 .enable_mask = BIT(0), 1497 .hw.init = &(const struct clk_init_data) { 1498 .name = "gcc_emac1_rgmii_clk", 1499 .parent_hws = (const struct clk_hw*[]) { 1500 &gcc_emac1_rgmii_clk_src.clkr.hw, 1501 }, 1502 .num_parents = 1, 1503 .flags = CLK_SET_RATE_PARENT, 1504 .ops = &clk_branch2_ops, 1505 }, 1506 }, 1507 }; 1508 1509 static struct clk_branch gcc_emac1_rpcs_rx_clk = { 1510 .halt_reg = 0x720a0, 1511 .halt_check = BRANCH_HALT_DELAY, 1512 .clkr = { 1513 .enable_reg = 0x720a0, 1514 .enable_mask = BIT(0), 1515 .hw.init = &(const struct clk_init_data) { 1516 .name = "gcc_emac1_rpcs_rx_clk", 1517 .parent_hws = (const struct clk_hw*[]) { 1518 &gcc_emac1_sgmiiphy_mac_rclk_src.clkr.hw, 1519 }, 1520 .num_parents = 1, 1521 .flags = CLK_SET_RATE_PARENT, 1522 .ops = &clk_branch2_ops, 1523 }, 1524 }, 1525 }; 1526 1527 static struct clk_branch gcc_emac1_rpcs_tx_clk = { 1528 .halt_reg = 0x7209c, 1529 .halt_check = BRANCH_HALT_DELAY, 1530 .clkr = { 1531 .enable_reg = 0x7209c, 1532 .enable_mask = BIT(0), 1533 .hw.init = &(const struct clk_init_data) { 1534 .name = "gcc_emac1_rpcs_tx_clk", 1535 .parent_hws = (const struct clk_hw*[]) { 1536 &gcc_emac1_sgmiiphy_mac_tclk_src.clkr.hw, 1537 }, 1538 .num_parents = 1, 1539 .flags = CLK_SET_RATE_PARENT, 1540 .ops = &clk_branch2_ops, 1541 }, 1542 }, 1543 }; 1544 1545 static struct clk_branch gcc_emac1_slv_ahb_clk = { 1546 .halt_reg = 0x72024, 1547 .halt_check = BRANCH_HALT_VOTED, 1548 .hwcg_reg = 0x72024, 1549 .hwcg_bit = 1, 1550 .clkr = { 1551 .enable_reg = 0x72024, 1552 .enable_mask = BIT(0), 1553 .hw.init = &(const struct clk_init_data) { 1554 .name = "gcc_emac1_slv_ahb_clk", 1555 .ops = &clk_branch2_ops, 1556 }, 1557 }, 1558 }; 1559 1560 static struct clk_branch gcc_emac1_xgxs_rx_clk = { 1561 .halt_reg = 0x720a8, 1562 .halt_check = BRANCH_HALT_DELAY, 1563 .clkr = { 1564 .enable_reg = 0x720a8, 1565 .enable_mask = BIT(0), 1566 .hw.init = &(const struct clk_init_data) { 1567 .name = "gcc_emac1_xgxs_rx_clk", 1568 .parent_hws = (const struct clk_hw*[]) { 1569 &gcc_emac1_sgmiiphy_mac_rclk_src.clkr.hw, 1570 }, 1571 .num_parents = 1, 1572 .flags = CLK_SET_RATE_PARENT, 1573 .ops = &clk_branch2_ops, 1574 }, 1575 }, 1576 }; 1577 1578 static struct clk_branch gcc_emac1_xgxs_tx_clk = { 1579 .halt_reg = 0x720a4, 1580 .halt_check = BRANCH_HALT_DELAY, 1581 .clkr = { 1582 .enable_reg = 0x720a4, 1583 .enable_mask = BIT(0), 1584 .hw.init = &(const struct clk_init_data) { 1585 .name = "gcc_emac1_xgxs_tx_clk", 1586 .parent_hws = (const struct clk_hw*[]) { 1587 &gcc_emac1_sgmiiphy_mac_tclk_src.clkr.hw, 1588 }, 1589 .num_parents = 1, 1590 .flags = CLK_SET_RATE_PARENT, 1591 .ops = &clk_branch2_ops, 1592 }, 1593 }, 1594 }; 1595 1596 static struct clk_branch gcc_emac_0_clkref_en = { 1597 .halt_reg = 0x98108, 1598 .halt_check = BRANCH_HALT_ENABLE, 1599 .clkr = { 1600 .enable_reg = 0x98108, 1601 .enable_mask = BIT(0), 1602 .hw.init = &(const struct clk_init_data) { 1603 .name = "gcc_emac_0_clkref_en", 1604 .ops = &clk_branch2_ops, 1605 }, 1606 }, 1607 }; 1608 1609 static struct clk_branch gcc_emac_1_clkref_en = { 1610 .halt_reg = 0x9810c, 1611 .halt_check = BRANCH_HALT_ENABLE, 1612 .clkr = { 1613 .enable_reg = 0x9810c, 1614 .enable_mask = BIT(0), 1615 .hw.init = &(const struct clk_init_data) { 1616 .name = "gcc_emac_1_clkref_en", 1617 .ops = &clk_branch2_ops, 1618 }, 1619 }, 1620 }; 1621 1622 static struct clk_branch gcc_gp1_clk = { 1623 .halt_reg = 0x47000, 1624 .halt_check = BRANCH_HALT, 1625 .clkr = { 1626 .enable_reg = 0x47000, 1627 .enable_mask = BIT(0), 1628 .hw.init = &(const struct clk_init_data) { 1629 .name = "gcc_gp1_clk", 1630 .parent_hws = (const struct clk_hw*[]) { 1631 &gcc_gp1_clk_src.clkr.hw, 1632 }, 1633 .num_parents = 1, 1634 .flags = CLK_SET_RATE_PARENT, 1635 .ops = &clk_branch2_ops, 1636 }, 1637 }, 1638 }; 1639 1640 static struct clk_branch gcc_gp2_clk = { 1641 .halt_reg = 0x48000, 1642 .halt_check = BRANCH_HALT, 1643 .clkr = { 1644 .enable_reg = 0x48000, 1645 .enable_mask = BIT(0), 1646 .hw.init = &(const struct clk_init_data) { 1647 .name = "gcc_gp2_clk", 1648 .parent_hws = (const struct clk_hw*[]) { 1649 &gcc_gp2_clk_src.clkr.hw, 1650 }, 1651 .num_parents = 1, 1652 .flags = CLK_SET_RATE_PARENT, 1653 .ops = &clk_branch2_ops, 1654 }, 1655 }, 1656 }; 1657 1658 static struct clk_branch gcc_gp3_clk = { 1659 .halt_reg = 0x49000, 1660 .halt_check = BRANCH_HALT, 1661 .clkr = { 1662 .enable_reg = 0x49000, 1663 .enable_mask = BIT(0), 1664 .hw.init = &(const struct clk_init_data) { 1665 .name = "gcc_gp3_clk", 1666 .parent_hws = (const struct clk_hw*[]) { 1667 &gcc_gp3_clk_src.clkr.hw, 1668 }, 1669 .num_parents = 1, 1670 .flags = CLK_SET_RATE_PARENT, 1671 .ops = &clk_branch2_ops, 1672 }, 1673 }, 1674 }; 1675 1676 static struct clk_branch gcc_pcie_0_clkref_en = { 1677 .halt_reg = 0x98004, 1678 .halt_check = BRANCH_HALT_ENABLE, 1679 .clkr = { 1680 .enable_reg = 0x98004, 1681 .enable_mask = BIT(0), 1682 .hw.init = &(const struct clk_init_data) { 1683 .name = "gcc_pcie_0_clkref_en", 1684 .ops = &clk_branch2_ops, 1685 }, 1686 }, 1687 }; 1688 1689 static struct clk_branch gcc_pcie_1_aux_clk = { 1690 .halt_reg = 0x67038, 1691 .halt_check = BRANCH_HALT_DELAY, 1692 .clkr = { 1693 .enable_reg = 0x7d010, 1694 .enable_mask = BIT(22), 1695 .hw.init = &(const struct clk_init_data) { 1696 .name = "gcc_pcie_1_aux_clk", 1697 .parent_hws = (const struct clk_hw*[]) { 1698 &gcc_pcie_1_aux_phy_clk_src.clkr.hw, 1699 }, 1700 .num_parents = 1, 1701 .flags = CLK_SET_RATE_PARENT, 1702 .ops = &clk_branch2_ops, 1703 }, 1704 }, 1705 }; 1706 1707 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1708 .halt_reg = 0x67034, 1709 .halt_check = BRANCH_HALT_VOTED, 1710 .hwcg_reg = 0x67034, 1711 .hwcg_bit = 1, 1712 .clkr = { 1713 .enable_reg = 0x7d010, 1714 .enable_mask = BIT(21), 1715 .hw.init = &(const struct clk_init_data) { 1716 .name = "gcc_pcie_1_cfg_ahb_clk", 1717 .ops = &clk_branch2_ops, 1718 }, 1719 }, 1720 }; 1721 1722 static struct clk_branch gcc_pcie_1_clkref_en = { 1723 .halt_reg = 0x98114, 1724 .halt_check = BRANCH_HALT_ENABLE, 1725 .clkr = { 1726 .enable_reg = 0x98114, 1727 .enable_mask = BIT(0), 1728 .hw.init = &(const struct clk_init_data) { 1729 .name = "gcc_pcie_1_clkref_en", 1730 .ops = &clk_branch2_ops, 1731 }, 1732 }, 1733 }; 1734 1735 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1736 .halt_reg = 0x67028, 1737 .halt_check = BRANCH_HALT_VOTED, 1738 .clkr = { 1739 .enable_reg = 0x7d010, 1740 .enable_mask = BIT(20), 1741 .hw.init = &(const struct clk_init_data) { 1742 .name = "gcc_pcie_1_mstr_axi_clk", 1743 .ops = &clk_branch2_ops, 1744 }, 1745 }, 1746 }; 1747 1748 static struct clk_branch gcc_pcie_1_phy_rchng_clk = { 1749 .halt_reg = 0x67068, 1750 .halt_check = BRANCH_HALT_VOTED, 1751 .clkr = { 1752 .enable_reg = 0x7d010, 1753 .enable_mask = BIT(24), 1754 .hw.init = &(const struct clk_init_data) { 1755 .name = "gcc_pcie_1_phy_rchng_clk", 1756 .parent_hws = (const struct clk_hw*[]) { 1757 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 1758 }, 1759 .num_parents = 1, 1760 .flags = CLK_SET_RATE_PARENT, 1761 .ops = &clk_branch2_ops, 1762 }, 1763 }, 1764 }; 1765 1766 static struct clk_branch gcc_pcie_1_pipe_clk = { 1767 .halt_reg = 0x6705c, 1768 .halt_check = BRANCH_HALT_DELAY, 1769 .clkr = { 1770 .enable_reg = 0x7d010, 1771 .enable_mask = BIT(23), 1772 .hw.init = &(const struct clk_init_data) { 1773 .name = "gcc_pcie_1_pipe_clk", 1774 .parent_hws = (const struct clk_hw*[]) { 1775 &gcc_pcie_1_pipe_clk_src.clkr.hw, 1776 }, 1777 .num_parents = 1, 1778 .flags = CLK_SET_RATE_PARENT, 1779 .ops = &clk_branch2_ops, 1780 }, 1781 }, 1782 }; 1783 1784 static struct clk_branch gcc_pcie_1_pipe_div2_clk = { 1785 .halt_reg = 0x6708c, 1786 .halt_check = BRANCH_HALT_DELAY, 1787 .clkr = { 1788 .enable_reg = 0x7d020, 1789 .enable_mask = BIT(3), 1790 .hw.init = &(const struct clk_init_data) { 1791 .name = "gcc_pcie_1_pipe_div2_clk", 1792 .parent_hws = (const struct clk_hw*[]) { 1793 &gcc_pcie_1_pipe_div2_clk_src.clkr.hw, 1794 }, 1795 .num_parents = 1, 1796 .flags = CLK_SET_RATE_PARENT, 1797 .ops = &clk_branch2_ops, 1798 }, 1799 }, 1800 }; 1801 1802 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1803 .halt_reg = 0x6701c, 1804 .halt_check = BRANCH_HALT_VOTED, 1805 .clkr = { 1806 .enable_reg = 0x7d010, 1807 .enable_mask = BIT(19), 1808 .hw.init = &(const struct clk_init_data) { 1809 .name = "gcc_pcie_1_slv_axi_clk", 1810 .ops = &clk_branch2_ops, 1811 }, 1812 }, 1813 }; 1814 1815 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 1816 .halt_reg = 0x67018, 1817 .halt_check = BRANCH_HALT_VOTED, 1818 .clkr = { 1819 .enable_reg = 0x7d010, 1820 .enable_mask = BIT(18), 1821 .hw.init = &(const struct clk_init_data) { 1822 .name = "gcc_pcie_1_slv_q2a_axi_clk", 1823 .ops = &clk_branch2_ops, 1824 }, 1825 }, 1826 }; 1827 1828 static struct clk_branch gcc_pcie_2_aux_clk = { 1829 .halt_reg = 0x68058, 1830 .halt_check = BRANCH_HALT_DELAY, 1831 .clkr = { 1832 .enable_reg = 0x7d010, 1833 .enable_mask = BIT(29), 1834 .hw.init = &(const struct clk_init_data) { 1835 .name = "gcc_pcie_2_aux_clk", 1836 .parent_hws = (const struct clk_hw*[]) { 1837 &gcc_pcie_2_aux_phy_clk_src.clkr.hw, 1838 }, 1839 .num_parents = 1, 1840 .flags = CLK_SET_RATE_PARENT, 1841 .ops = &clk_branch2_ops, 1842 }, 1843 }, 1844 }; 1845 1846 static struct clk_branch gcc_pcie_2_cfg_ahb_clk = { 1847 .halt_reg = 0x68034, 1848 .halt_check = BRANCH_HALT_VOTED, 1849 .hwcg_reg = 0x68034, 1850 .hwcg_bit = 1, 1851 .clkr = { 1852 .enable_reg = 0x7d010, 1853 .enable_mask = BIT(28), 1854 .hw.init = &(const struct clk_init_data) { 1855 .name = "gcc_pcie_2_cfg_ahb_clk", 1856 .ops = &clk_branch2_ops, 1857 }, 1858 }, 1859 }; 1860 1861 static struct clk_branch gcc_pcie_2_clkref_en = { 1862 .halt_reg = 0x98110, 1863 .halt_check = BRANCH_HALT_ENABLE, 1864 .clkr = { 1865 .enable_reg = 0x98110, 1866 .enable_mask = BIT(0), 1867 .hw.init = &(const struct clk_init_data) { 1868 .name = "gcc_pcie_2_clkref_en", 1869 .ops = &clk_branch2_ops, 1870 }, 1871 }, 1872 }; 1873 1874 static struct clk_branch gcc_pcie_2_mstr_axi_clk = { 1875 .halt_reg = 0x68028, 1876 .halt_check = BRANCH_HALT_VOTED, 1877 .clkr = { 1878 .enable_reg = 0x7d008, 1879 .enable_mask = BIT(8), 1880 .hw.init = &(const struct clk_init_data) { 1881 .name = "gcc_pcie_2_mstr_axi_clk", 1882 .ops = &clk_branch2_ops, 1883 }, 1884 }, 1885 }; 1886 1887 static struct clk_branch gcc_pcie_2_phy_rchng_clk = { 1888 .halt_reg = 0x68098, 1889 .halt_check = BRANCH_HALT_VOTED, 1890 .clkr = { 1891 .enable_reg = 0x7d010, 1892 .enable_mask = BIT(31), 1893 .hw.init = &(const struct clk_init_data) { 1894 .name = "gcc_pcie_2_phy_rchng_clk", 1895 .parent_hws = (const struct clk_hw*[]) { 1896 &gcc_pcie_2_phy_rchng_clk_src.clkr.hw, 1897 }, 1898 .num_parents = 1, 1899 .flags = CLK_SET_RATE_PARENT, 1900 .ops = &clk_branch2_ops, 1901 }, 1902 }, 1903 }; 1904 1905 static struct clk_branch gcc_pcie_2_pipe_clk = { 1906 .halt_reg = 0x6807c, 1907 .halt_check = BRANCH_HALT_DELAY, 1908 .clkr = { 1909 .enable_reg = 0x7d010, 1910 .enable_mask = BIT(30), 1911 .hw.init = &(const struct clk_init_data) { 1912 .name = "gcc_pcie_2_pipe_clk", 1913 .parent_hws = (const struct clk_hw*[]) { 1914 &gcc_pcie_2_pipe_clk_src.clkr.hw, 1915 }, 1916 .num_parents = 1, 1917 .flags = CLK_SET_RATE_PARENT, 1918 .ops = &clk_branch2_ops, 1919 }, 1920 }, 1921 }; 1922 1923 static struct clk_branch gcc_pcie_2_pipe_div2_clk = { 1924 .halt_reg = 0x6808c, 1925 .halt_check = BRANCH_HALT_DELAY, 1926 .clkr = { 1927 .enable_reg = 0x7d020, 1928 .enable_mask = BIT(4), 1929 .hw.init = &(const struct clk_init_data) { 1930 .name = "gcc_pcie_2_pipe_div2_clk", 1931 .parent_hws = (const struct clk_hw*[]) { 1932 &gcc_pcie_2_pipe_div2_clk_src.clkr.hw, 1933 }, 1934 .num_parents = 1, 1935 .flags = CLK_SET_RATE_PARENT, 1936 .ops = &clk_branch2_ops, 1937 }, 1938 }, 1939 }; 1940 1941 static struct clk_branch gcc_pcie_2_slv_axi_clk = { 1942 .halt_reg = 0x6801c, 1943 .halt_check = BRANCH_HALT_VOTED, 1944 .clkr = { 1945 .enable_reg = 0x7d010, 1946 .enable_mask = BIT(26), 1947 .hw.init = &(const struct clk_init_data) { 1948 .name = "gcc_pcie_2_slv_axi_clk", 1949 .ops = &clk_branch2_ops, 1950 }, 1951 }, 1952 }; 1953 1954 static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = { 1955 .halt_reg = 0x68018, 1956 .halt_check = BRANCH_HALT_VOTED, 1957 .clkr = { 1958 .enable_reg = 0x7d010, 1959 .enable_mask = BIT(25), 1960 .hw.init = &(const struct clk_init_data) { 1961 .name = "gcc_pcie_2_slv_q2a_axi_clk", 1962 .ops = &clk_branch2_ops, 1963 }, 1964 }, 1965 }; 1966 1967 static struct clk_branch gcc_pcie_aux_clk = { 1968 .halt_reg = 0x5303c, 1969 .halt_check = BRANCH_HALT_DELAY, 1970 .hwcg_reg = 0x5303c, 1971 .hwcg_bit = 1, 1972 .clkr = { 1973 .enable_reg = 0x7d010, 1974 .enable_mask = BIT(15), 1975 .hw.init = &(const struct clk_init_data) { 1976 .name = "gcc_pcie_aux_clk", 1977 .parent_hws = (const struct clk_hw*[]) { 1978 &gcc_pcie_aux_clk_src.clkr.hw, 1979 }, 1980 .num_parents = 1, 1981 .flags = CLK_SET_RATE_PARENT, 1982 .ops = &clk_branch2_ops, 1983 }, 1984 }, 1985 }; 1986 1987 static struct clk_branch gcc_pcie_cfg_ahb_clk = { 1988 .halt_reg = 0x53034, 1989 .halt_check = BRANCH_HALT_VOTED, 1990 .hwcg_reg = 0x53034, 1991 .hwcg_bit = 1, 1992 .clkr = { 1993 .enable_reg = 0x7d010, 1994 .enable_mask = BIT(13), 1995 .hw.init = &(const struct clk_init_data) { 1996 .name = "gcc_pcie_cfg_ahb_clk", 1997 .ops = &clk_branch2_ops, 1998 }, 1999 }, 2000 }; 2001 2002 static struct clk_branch gcc_pcie_mstr_axi_clk = { 2003 .halt_reg = 0x53028, 2004 .halt_check = BRANCH_HALT_VOTED, 2005 .hwcg_reg = 0x53028, 2006 .hwcg_bit = 1, 2007 .clkr = { 2008 .enable_reg = 0x7d010, 2009 .enable_mask = BIT(12), 2010 .hw.init = &(const struct clk_init_data) { 2011 .name = "gcc_pcie_mstr_axi_clk", 2012 .ops = &clk_branch2_ops, 2013 }, 2014 }, 2015 }; 2016 2017 static struct clk_branch gcc_pcie_pipe_clk = { 2018 .halt_reg = 0x5304c, 2019 .halt_check = BRANCH_HALT_DELAY, 2020 .hwcg_reg = 0x5304c, 2021 .hwcg_bit = 1, 2022 .clkr = { 2023 .enable_reg = 0x7d010, 2024 .enable_mask = BIT(17), 2025 .hw.init = &(const struct clk_init_data) { 2026 .name = "gcc_pcie_pipe_clk", 2027 .parent_hws = (const struct clk_hw*[]) { 2028 &gcc_pcie_pipe_clk_src.clkr.hw, 2029 }, 2030 .num_parents = 1, 2031 .flags = CLK_SET_RATE_PARENT, 2032 .ops = &clk_branch2_ops, 2033 }, 2034 }, 2035 }; 2036 2037 static struct clk_branch gcc_pcie_rchng_phy_clk = { 2038 .halt_reg = 0x53038, 2039 .halt_check = BRANCH_HALT_VOTED, 2040 .hwcg_reg = 0x53038, 2041 .hwcg_bit = 1, 2042 .clkr = { 2043 .enable_reg = 0x7d010, 2044 .enable_mask = BIT(14), 2045 .hw.init = &(const struct clk_init_data) { 2046 .name = "gcc_pcie_rchng_phy_clk", 2047 .parent_hws = (const struct clk_hw*[]) { 2048 &gcc_pcie_rchng_phy_clk_src.clkr.hw, 2049 }, 2050 .num_parents = 1, 2051 .flags = CLK_SET_RATE_PARENT, 2052 .ops = &clk_branch2_ops, 2053 }, 2054 }, 2055 }; 2056 2057 static struct clk_branch gcc_pcie_sleep_clk = { 2058 .halt_reg = 0x53048, 2059 .halt_check = BRANCH_HALT_VOTED, 2060 .hwcg_reg = 0x53048, 2061 .hwcg_bit = 1, 2062 .clkr = { 2063 .enable_reg = 0x7d010, 2064 .enable_mask = BIT(16), 2065 .hw.init = &(const struct clk_init_data) { 2066 .name = "gcc_pcie_sleep_clk", 2067 .parent_hws = (const struct clk_hw*[]) { 2068 &gcc_pcie_aux_phy_clk_src.clkr.hw, 2069 }, 2070 .num_parents = 1, 2071 .flags = CLK_SET_RATE_PARENT, 2072 .ops = &clk_branch2_ops, 2073 }, 2074 }, 2075 }; 2076 2077 static struct clk_branch gcc_pcie_slv_axi_clk = { 2078 .halt_reg = 0x5301c, 2079 .halt_check = BRANCH_HALT_VOTED, 2080 .clkr = { 2081 .enable_reg = 0x7d010, 2082 .enable_mask = BIT(11), 2083 .hw.init = &(const struct clk_init_data) { 2084 .name = "gcc_pcie_slv_axi_clk", 2085 .ops = &clk_branch2_ops, 2086 }, 2087 }, 2088 }; 2089 2090 static struct clk_branch gcc_pcie_slv_q2a_axi_clk = { 2091 .halt_reg = 0x53018, 2092 .halt_check = BRANCH_HALT_VOTED, 2093 .hwcg_reg = 0x53018, 2094 .hwcg_bit = 1, 2095 .clkr = { 2096 .enable_reg = 0x7d010, 2097 .enable_mask = BIT(10), 2098 .hw.init = &(const struct clk_init_data) { 2099 .name = "gcc_pcie_slv_q2a_axi_clk", 2100 .ops = &clk_branch2_ops, 2101 }, 2102 }, 2103 }; 2104 2105 static struct clk_branch gcc_pdm2_clk = { 2106 .halt_reg = 0x3400c, 2107 .halt_check = BRANCH_HALT, 2108 .clkr = { 2109 .enable_reg = 0x3400c, 2110 .enable_mask = BIT(0), 2111 .hw.init = &(const struct clk_init_data) { 2112 .name = "gcc_pdm2_clk", 2113 .parent_hws = (const struct clk_hw*[]) { 2114 &gcc_pdm2_clk_src.clkr.hw, 2115 }, 2116 .num_parents = 1, 2117 .flags = CLK_SET_RATE_PARENT, 2118 .ops = &clk_branch2_ops, 2119 }, 2120 }, 2121 }; 2122 2123 static struct clk_branch gcc_pdm_ahb_clk = { 2124 .halt_reg = 0x34004, 2125 .halt_check = BRANCH_HALT, 2126 .clkr = { 2127 .enable_reg = 0x34004, 2128 .enable_mask = BIT(0), 2129 .hw.init = &(const struct clk_init_data) { 2130 .name = "gcc_pdm_ahb_clk", 2131 .ops = &clk_branch2_ops, 2132 }, 2133 }, 2134 }; 2135 2136 static struct clk_branch gcc_pdm_xo4_clk = { 2137 .halt_reg = 0x34008, 2138 .halt_check = BRANCH_HALT, 2139 .clkr = { 2140 .enable_reg = 0x34008, 2141 .enable_mask = BIT(0), 2142 .hw.init = &(const struct clk_init_data) { 2143 .name = "gcc_pdm_xo4_clk", 2144 .ops = &clk_branch2_ops, 2145 }, 2146 }, 2147 }; 2148 2149 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2150 .halt_reg = 0x2d018, 2151 .halt_check = BRANCH_HALT_VOTED, 2152 .clkr = { 2153 .enable_reg = 0x7d008, 2154 .enable_mask = BIT(15), 2155 .hw.init = &(const struct clk_init_data) { 2156 .name = "gcc_qupv3_wrap0_core_2x_clk", 2157 .ops = &clk_branch2_ops, 2158 }, 2159 }, 2160 }; 2161 2162 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2163 .halt_reg = 0x2d008, 2164 .halt_check = BRANCH_HALT_VOTED, 2165 .clkr = { 2166 .enable_reg = 0x7d008, 2167 .enable_mask = BIT(14), 2168 .hw.init = &(const struct clk_init_data) { 2169 .name = "gcc_qupv3_wrap0_core_clk", 2170 .ops = &clk_branch2_ops, 2171 }, 2172 }, 2173 }; 2174 2175 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2176 .halt_reg = 0x6c004, 2177 .halt_check = BRANCH_HALT_VOTED, 2178 .clkr = { 2179 .enable_reg = 0x7d008, 2180 .enable_mask = BIT(16), 2181 .hw.init = &(const struct clk_init_data) { 2182 .name = "gcc_qupv3_wrap0_s0_clk", 2183 .parent_hws = (const struct clk_hw*[]) { 2184 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 2185 }, 2186 .num_parents = 1, 2187 .flags = CLK_SET_RATE_PARENT, 2188 .ops = &clk_branch2_ops, 2189 }, 2190 }, 2191 }; 2192 2193 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2194 .halt_reg = 0x6c13c, 2195 .halt_check = BRANCH_HALT_VOTED, 2196 .clkr = { 2197 .enable_reg = 0x7d008, 2198 .enable_mask = BIT(17), 2199 .hw.init = &(const struct clk_init_data) { 2200 .name = "gcc_qupv3_wrap0_s1_clk", 2201 .parent_hws = (const struct clk_hw*[]) { 2202 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 2203 }, 2204 .num_parents = 1, 2205 .flags = CLK_SET_RATE_PARENT, 2206 .ops = &clk_branch2_ops, 2207 }, 2208 }, 2209 }; 2210 2211 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2212 .halt_reg = 0x6c274, 2213 .halt_check = BRANCH_HALT_VOTED, 2214 .clkr = { 2215 .enable_reg = 0x7d008, 2216 .enable_mask = BIT(18), 2217 .hw.init = &(const struct clk_init_data) { 2218 .name = "gcc_qupv3_wrap0_s2_clk", 2219 .parent_hws = (const struct clk_hw*[]) { 2220 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2221 }, 2222 .num_parents = 1, 2223 .flags = CLK_SET_RATE_PARENT, 2224 .ops = &clk_branch2_ops, 2225 }, 2226 }, 2227 }; 2228 2229 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2230 .halt_reg = 0x6c3ac, 2231 .halt_check = BRANCH_HALT_VOTED, 2232 .clkr = { 2233 .enable_reg = 0x7d008, 2234 .enable_mask = BIT(19), 2235 .hw.init = &(const struct clk_init_data) { 2236 .name = "gcc_qupv3_wrap0_s3_clk", 2237 .parent_hws = (const struct clk_hw*[]) { 2238 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2239 }, 2240 .num_parents = 1, 2241 .flags = CLK_SET_RATE_PARENT, 2242 .ops = &clk_branch2_ops, 2243 }, 2244 }, 2245 }; 2246 2247 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2248 .halt_reg = 0x6c4e4, 2249 .halt_check = BRANCH_HALT_VOTED, 2250 .clkr = { 2251 .enable_reg = 0x7d008, 2252 .enable_mask = BIT(20), 2253 .hw.init = &(const struct clk_init_data) { 2254 .name = "gcc_qupv3_wrap0_s4_clk", 2255 .parent_hws = (const struct clk_hw*[]) { 2256 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2257 }, 2258 .num_parents = 1, 2259 .flags = CLK_SET_RATE_PARENT, 2260 .ops = &clk_branch2_ops, 2261 }, 2262 }, 2263 }; 2264 2265 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2266 .halt_reg = 0x6c61c, 2267 .halt_check = BRANCH_HALT_VOTED, 2268 .clkr = { 2269 .enable_reg = 0x7d008, 2270 .enable_mask = BIT(21), 2271 .hw.init = &(const struct clk_init_data) { 2272 .name = "gcc_qupv3_wrap0_s5_clk", 2273 .parent_hws = (const struct clk_hw*[]) { 2274 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2275 }, 2276 .num_parents = 1, 2277 .flags = CLK_SET_RATE_PARENT, 2278 .ops = &clk_branch2_ops, 2279 }, 2280 }, 2281 }; 2282 2283 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 2284 .halt_reg = 0x6c754, 2285 .halt_check = BRANCH_HALT_VOTED, 2286 .clkr = { 2287 .enable_reg = 0x7d008, 2288 .enable_mask = BIT(22), 2289 .hw.init = &(const struct clk_init_data) { 2290 .name = "gcc_qupv3_wrap0_s6_clk", 2291 .parent_hws = (const struct clk_hw*[]) { 2292 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 2293 }, 2294 .num_parents = 1, 2295 .flags = CLK_SET_RATE_PARENT, 2296 .ops = &clk_branch2_ops, 2297 }, 2298 }, 2299 }; 2300 2301 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 2302 .halt_reg = 0x6c88c, 2303 .halt_check = BRANCH_HALT_VOTED, 2304 .clkr = { 2305 .enable_reg = 0x7d008, 2306 .enable_mask = BIT(23), 2307 .hw.init = &(const struct clk_init_data) { 2308 .name = "gcc_qupv3_wrap0_s7_clk", 2309 .parent_hws = (const struct clk_hw*[]) { 2310 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 2311 }, 2312 .num_parents = 1, 2313 .flags = CLK_SET_RATE_PARENT, 2314 .ops = &clk_branch2_ops, 2315 }, 2316 }, 2317 }; 2318 2319 static struct clk_branch gcc_qupv3_wrap0_s8_clk = { 2320 .halt_reg = 0x6c9c4, 2321 .halt_check = BRANCH_HALT_VOTED, 2322 .clkr = { 2323 .enable_reg = 0x7d020, 2324 .enable_mask = BIT(7), 2325 .hw.init = &(const struct clk_init_data) { 2326 .name = "gcc_qupv3_wrap0_s8_clk", 2327 .parent_hws = (const struct clk_hw*[]) { 2328 &gcc_qupv3_wrap0_s8_clk_src.clkr.hw, 2329 }, 2330 .num_parents = 1, 2331 .flags = CLK_SET_RATE_PARENT, 2332 .ops = &clk_branch2_ops, 2333 }, 2334 }, 2335 }; 2336 2337 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2338 .halt_reg = 0x2d000, 2339 .halt_check = BRANCH_HALT_VOTED, 2340 .hwcg_reg = 0x2d000, 2341 .hwcg_bit = 1, 2342 .clkr = { 2343 .enable_reg = 0x7d008, 2344 .enable_mask = BIT(12), 2345 .hw.init = &(const struct clk_init_data) { 2346 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2347 .ops = &clk_branch2_ops, 2348 }, 2349 }, 2350 }; 2351 2352 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2353 .halt_reg = 0x2d004, 2354 .halt_check = BRANCH_HALT_VOTED, 2355 .hwcg_reg = 0x2d004, 2356 .hwcg_bit = 1, 2357 .clkr = { 2358 .enable_reg = 0x7d008, 2359 .enable_mask = BIT(13), 2360 .hw.init = &(const struct clk_init_data) { 2361 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2362 .ops = &clk_branch2_ops, 2363 }, 2364 }, 2365 }; 2366 2367 static struct clk_branch gcc_sdcc1_ahb_clk = { 2368 .halt_reg = 0x6b004, 2369 .halt_check = BRANCH_HALT, 2370 .clkr = { 2371 .enable_reg = 0x6b004, 2372 .enable_mask = BIT(0), 2373 .hw.init = &(const struct clk_init_data) { 2374 .name = "gcc_sdcc1_ahb_clk", 2375 .ops = &clk_branch2_ops, 2376 }, 2377 }, 2378 }; 2379 2380 static struct clk_branch gcc_sdcc1_apps_clk = { 2381 .halt_reg = 0x6b008, 2382 .halt_check = BRANCH_HALT, 2383 .clkr = { 2384 .enable_reg = 0x6b008, 2385 .enable_mask = BIT(0), 2386 .hw.init = &(const struct clk_init_data) { 2387 .name = "gcc_sdcc1_apps_clk", 2388 .parent_hws = (const struct clk_hw*[]) { 2389 &gcc_sdcc1_apps_clk_src.clkr.hw, 2390 }, 2391 .num_parents = 1, 2392 .flags = CLK_SET_RATE_PARENT, 2393 .ops = &clk_branch2_ops, 2394 }, 2395 }, 2396 }; 2397 2398 static struct clk_branch gcc_sdcc2_ahb_clk = { 2399 .halt_reg = 0x6a010, 2400 .halt_check = BRANCH_HALT, 2401 .clkr = { 2402 .enable_reg = 0x6a010, 2403 .enable_mask = BIT(0), 2404 .hw.init = &(const struct clk_init_data) { 2405 .name = "gcc_sdcc2_ahb_clk", 2406 .ops = &clk_branch2_ops, 2407 }, 2408 }, 2409 }; 2410 2411 static struct clk_branch gcc_sdcc2_apps_clk = { 2412 .halt_reg = 0x6a004, 2413 .halt_check = BRANCH_HALT, 2414 .clkr = { 2415 .enable_reg = 0x6a004, 2416 .enable_mask = BIT(0), 2417 .hw.init = &(const struct clk_init_data) { 2418 .name = "gcc_sdcc2_apps_clk", 2419 .parent_hws = (const struct clk_hw*[]) { 2420 &gcc_sdcc2_apps_clk_src.clkr.hw, 2421 }, 2422 .num_parents = 1, 2423 .flags = CLK_SET_RATE_PARENT, 2424 .ops = &clk_branch2_ops, 2425 }, 2426 }, 2427 }; 2428 2429 static struct clk_branch gcc_usb2_clkref_en = { 2430 .halt_reg = 0x98008, 2431 .halt_check = BRANCH_HALT_ENABLE, 2432 .clkr = { 2433 .enable_reg = 0x98008, 2434 .enable_mask = BIT(0), 2435 .hw.init = &(const struct clk_init_data) { 2436 .name = "gcc_usb2_clkref_en", 2437 .ops = &clk_branch2_ops, 2438 }, 2439 }, 2440 }; 2441 2442 static struct clk_branch gcc_usb30_master_clk = { 2443 .halt_reg = 0x27018, 2444 .halt_check = BRANCH_HALT, 2445 .clkr = { 2446 .enable_reg = 0x27018, 2447 .enable_mask = BIT(0), 2448 .hw.init = &(const struct clk_init_data) { 2449 .name = "gcc_usb30_master_clk", 2450 .parent_hws = (const struct clk_hw*[]) { 2451 &gcc_usb30_master_clk_src.clkr.hw, 2452 }, 2453 .num_parents = 1, 2454 .flags = CLK_SET_RATE_PARENT, 2455 .ops = &clk_branch2_ops, 2456 }, 2457 }, 2458 }; 2459 2460 static struct clk_branch gcc_usb30_mock_utmi_clk = { 2461 .halt_reg = 0x27030, 2462 .halt_check = BRANCH_HALT, 2463 .clkr = { 2464 .enable_reg = 0x27030, 2465 .enable_mask = BIT(0), 2466 .hw.init = &(const struct clk_init_data) { 2467 .name = "gcc_usb30_mock_utmi_clk", 2468 .parent_hws = (const struct clk_hw*[]) { 2469 &gcc_usb30_mock_utmi_postdiv_clk_src.clkr.hw, 2470 }, 2471 .num_parents = 1, 2472 .flags = CLK_SET_RATE_PARENT, 2473 .ops = &clk_branch2_ops, 2474 }, 2475 }, 2476 }; 2477 2478 static struct clk_branch gcc_usb30_mstr_axi_clk = { 2479 .halt_reg = 0x27024, 2480 .halt_check = BRANCH_HALT, 2481 .clkr = { 2482 .enable_reg = 0x27024, 2483 .enable_mask = BIT(0), 2484 .hw.init = &(const struct clk_init_data) { 2485 .name = "gcc_usb30_mstr_axi_clk", 2486 .ops = &clk_branch2_ops, 2487 }, 2488 }, 2489 }; 2490 2491 static struct clk_branch gcc_usb30_sleep_clk = { 2492 .halt_reg = 0x2702c, 2493 .halt_check = BRANCH_HALT, 2494 .clkr = { 2495 .enable_reg = 0x2702c, 2496 .enable_mask = BIT(0), 2497 .hw.init = &(const struct clk_init_data) { 2498 .name = "gcc_usb30_sleep_clk", 2499 .ops = &clk_branch2_ops, 2500 }, 2501 }, 2502 }; 2503 2504 static struct clk_branch gcc_usb30_slv_ahb_clk = { 2505 .halt_reg = 0x27028, 2506 .halt_check = BRANCH_HALT, 2507 .clkr = { 2508 .enable_reg = 0x27028, 2509 .enable_mask = BIT(0), 2510 .hw.init = &(const struct clk_init_data) { 2511 .name = "gcc_usb30_slv_ahb_clk", 2512 .ops = &clk_branch2_ops, 2513 }, 2514 }, 2515 }; 2516 2517 static struct clk_branch gcc_usb3_phy_aux_clk = { 2518 .halt_reg = 0x27068, 2519 .halt_check = BRANCH_HALT, 2520 .clkr = { 2521 .enable_reg = 0x27068, 2522 .enable_mask = BIT(0), 2523 .hw.init = &(const struct clk_init_data) { 2524 .name = "gcc_usb3_phy_aux_clk", 2525 .parent_hws = (const struct clk_hw*[]) { 2526 &gcc_usb3_phy_aux_clk_src.clkr.hw, 2527 }, 2528 .num_parents = 1, 2529 .flags = CLK_SET_RATE_PARENT, 2530 .ops = &clk_branch2_ops, 2531 }, 2532 }, 2533 }; 2534 2535 static struct clk_branch gcc_usb3_phy_pipe_clk = { 2536 .halt_reg = 0x2706c, 2537 .halt_check = BRANCH_HALT_DELAY, 2538 .hwcg_reg = 0x2706c, 2539 .hwcg_bit = 1, 2540 .clkr = { 2541 .enable_reg = 0x2706c, 2542 .enable_mask = BIT(0), 2543 .hw.init = &(const struct clk_init_data) { 2544 .name = "gcc_usb3_phy_pipe_clk", 2545 .parent_hws = (const struct clk_hw*[]) { 2546 &gcc_usb3_phy_pipe_clk_src.clkr.hw, 2547 }, 2548 .num_parents = 1, 2549 .flags = CLK_SET_RATE_PARENT, 2550 .ops = &clk_branch2_ops, 2551 }, 2552 }, 2553 }; 2554 2555 static struct clk_branch gcc_usb3_prim_clkref_en = { 2556 .halt_reg = 0x98000, 2557 .halt_check = BRANCH_HALT_ENABLE, 2558 .clkr = { 2559 .enable_reg = 0x98000, 2560 .enable_mask = BIT(0), 2561 .hw.init = &(const struct clk_init_data) { 2562 .name = "gcc_usb3_prim_clkref_en", 2563 .ops = &clk_branch2_ops, 2564 }, 2565 }, 2566 }; 2567 2568 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 2569 .halt_reg = 0x29004, 2570 .halt_check = BRANCH_HALT, 2571 .hwcg_reg = 0x29004, 2572 .hwcg_bit = 1, 2573 .clkr = { 2574 .enable_reg = 0x29004, 2575 .enable_mask = BIT(0), 2576 .hw.init = &(const struct clk_init_data) { 2577 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2578 .ops = &clk_branch2_aon_ops, 2579 }, 2580 }, 2581 }; 2582 2583 static struct gdsc gcc_emac0_gdsc = { 2584 .gdscr = 0x71004, 2585 .en_rest_wait_val = 0x2, 2586 .en_few_wait_val = 0x2, 2587 .clk_dis_wait_val = 0xf, 2588 .pd = { 2589 .name = "gcc_emac0_gdsc", 2590 }, 2591 .pwrsts = PWRSTS_OFF_ON, 2592 .flags = RETAIN_FF_ENABLE, 2593 }; 2594 2595 static struct gdsc gcc_emac1_gdsc = { 2596 .gdscr = 0x72004, 2597 .en_rest_wait_val = 0x2, 2598 .en_few_wait_val = 0x2, 2599 .clk_dis_wait_val = 0xf, 2600 .pd = { 2601 .name = "gcc_emac1_gdsc", 2602 }, 2603 .pwrsts = PWRSTS_OFF_ON, 2604 .flags = RETAIN_FF_ENABLE, 2605 }; 2606 2607 static struct gdsc gcc_pcie_1_gdsc = { 2608 .gdscr = 0x67004, 2609 .en_rest_wait_val = 0x2, 2610 .en_few_wait_val = 0x2, 2611 .clk_dis_wait_val = 0xf, 2612 .pd = { 2613 .name = "gcc_pcie_1_gdsc", 2614 }, 2615 .pwrsts = PWRSTS_OFF_ON, 2616 .flags = RETAIN_FF_ENABLE, 2617 }; 2618 2619 static struct gdsc gcc_pcie_1_phy_gdsc = { 2620 .gdscr = 0x56004, 2621 .en_rest_wait_val = 0x2, 2622 .en_few_wait_val = 0x2, 2623 .clk_dis_wait_val = 0x2, 2624 .pd = { 2625 .name = "gcc_pcie_1_phy_gdsc", 2626 }, 2627 .pwrsts = PWRSTS_OFF_ON, 2628 .flags = RETAIN_FF_ENABLE, 2629 }; 2630 2631 static struct gdsc gcc_pcie_2_gdsc = { 2632 .gdscr = 0x68004, 2633 .en_rest_wait_val = 0x2, 2634 .en_few_wait_val = 0x2, 2635 .clk_dis_wait_val = 0xf, 2636 .pd = { 2637 .name = "gcc_pcie_2_gdsc", 2638 }, 2639 .pwrsts = PWRSTS_OFF_ON, 2640 .flags = RETAIN_FF_ENABLE, 2641 }; 2642 2643 static struct gdsc gcc_pcie_2_phy_gdsc = { 2644 .gdscr = 0x6e004, 2645 .en_rest_wait_val = 0x2, 2646 .en_few_wait_val = 0x2, 2647 .clk_dis_wait_val = 0x2, 2648 .pd = { 2649 .name = "gcc_pcie_2_phy_gdsc", 2650 }, 2651 .pwrsts = PWRSTS_OFF_ON, 2652 .flags = RETAIN_FF_ENABLE, 2653 }; 2654 2655 static struct gdsc gcc_pcie_gdsc = { 2656 .gdscr = 0x53004, 2657 .en_rest_wait_val = 0x2, 2658 .en_few_wait_val = 0x2, 2659 .clk_dis_wait_val = 0xf, 2660 .pd = { 2661 .name = "gcc_pcie_gdsc", 2662 }, 2663 .pwrsts = PWRSTS_OFF_ON, 2664 .flags = RETAIN_FF_ENABLE, 2665 }; 2666 2667 static struct gdsc gcc_pcie_phy_gdsc = { 2668 .gdscr = 0x54004, 2669 .en_rest_wait_val = 0x2, 2670 .en_few_wait_val = 0x2, 2671 .clk_dis_wait_val = 0x2, 2672 .pd = { 2673 .name = "gcc_pcie_phy_gdsc", 2674 }, 2675 .pwrsts = PWRSTS_OFF_ON, 2676 .flags = RETAIN_FF_ENABLE, 2677 }; 2678 2679 static struct gdsc gcc_usb30_gdsc = { 2680 .gdscr = 0x27004, 2681 .en_rest_wait_val = 0x2, 2682 .en_few_wait_val = 0x2, 2683 .clk_dis_wait_val = 0xf, 2684 .pd = { 2685 .name = "gcc_usb30_gdsc", 2686 }, 2687 .pwrsts = PWRSTS_OFF_ON, 2688 .flags = RETAIN_FF_ENABLE, 2689 }; 2690 2691 static struct gdsc gcc_usb3_phy_gdsc = { 2692 .gdscr = 0x28008, 2693 .en_rest_wait_val = 0x2, 2694 .en_few_wait_val = 0x2, 2695 .clk_dis_wait_val = 0x2, 2696 .pd = { 2697 .name = "gcc_usb3_phy_gdsc", 2698 }, 2699 .pwrsts = PWRSTS_OFF_ON, 2700 .flags = RETAIN_FF_ENABLE, 2701 }; 2702 2703 static struct clk_regmap *gcc_sdx75_clocks[] = { 2704 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2705 [GCC_EEE_EMAC0_CLK] = &gcc_eee_emac0_clk.clkr, 2706 [GCC_EEE_EMAC0_CLK_SRC] = &gcc_eee_emac0_clk_src.clkr, 2707 [GCC_EEE_EMAC1_CLK] = &gcc_eee_emac1_clk.clkr, 2708 [GCC_EEE_EMAC1_CLK_SRC] = &gcc_eee_emac1_clk_src.clkr, 2709 [GCC_EMAC0_AXI_CLK] = &gcc_emac0_axi_clk.clkr, 2710 [GCC_EMAC0_CC_SGMIIPHY_RX_CLK] = &gcc_emac0_cc_sgmiiphy_rx_clk.clkr, 2711 [GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC] = &gcc_emac0_cc_sgmiiphy_rx_clk_src.clkr, 2712 [GCC_EMAC0_CC_SGMIIPHY_TX_CLK] = &gcc_emac0_cc_sgmiiphy_tx_clk.clkr, 2713 [GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC] = &gcc_emac0_cc_sgmiiphy_tx_clk_src.clkr, 2714 [GCC_EMAC0_PHY_AUX_CLK] = &gcc_emac0_phy_aux_clk.clkr, 2715 [GCC_EMAC0_PHY_AUX_CLK_SRC] = &gcc_emac0_phy_aux_clk_src.clkr, 2716 [GCC_EMAC0_PTP_CLK] = &gcc_emac0_ptp_clk.clkr, 2717 [GCC_EMAC0_PTP_CLK_SRC] = &gcc_emac0_ptp_clk_src.clkr, 2718 [GCC_EMAC0_RGMII_CLK] = &gcc_emac0_rgmii_clk.clkr, 2719 [GCC_EMAC0_RGMII_CLK_SRC] = &gcc_emac0_rgmii_clk_src.clkr, 2720 [GCC_EMAC0_RPCS_RX_CLK] = &gcc_emac0_rpcs_rx_clk.clkr, 2721 [GCC_EMAC0_RPCS_TX_CLK] = &gcc_emac0_rpcs_tx_clk.clkr, 2722 [GCC_EMAC0_SGMIIPHY_MAC_RCLK_SRC] = &gcc_emac0_sgmiiphy_mac_rclk_src.clkr, 2723 [GCC_EMAC0_SGMIIPHY_MAC_TCLK_SRC] = &gcc_emac0_sgmiiphy_mac_tclk_src.clkr, 2724 [GCC_EMAC0_SLV_AHB_CLK] = &gcc_emac0_slv_ahb_clk.clkr, 2725 [GCC_EMAC0_XGXS_RX_CLK] = &gcc_emac0_xgxs_rx_clk.clkr, 2726 [GCC_EMAC0_XGXS_TX_CLK] = &gcc_emac0_xgxs_tx_clk.clkr, 2727 [GCC_EMAC1_AXI_CLK] = &gcc_emac1_axi_clk.clkr, 2728 [GCC_EMAC1_CC_SGMIIPHY_RX_CLK] = &gcc_emac1_cc_sgmiiphy_rx_clk.clkr, 2729 [GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC] = &gcc_emac1_cc_sgmiiphy_rx_clk_src.clkr, 2730 [GCC_EMAC1_CC_SGMIIPHY_TX_CLK] = &gcc_emac1_cc_sgmiiphy_tx_clk.clkr, 2731 [GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC] = &gcc_emac1_cc_sgmiiphy_tx_clk_src.clkr, 2732 [GCC_EMAC1_PHY_AUX_CLK] = &gcc_emac1_phy_aux_clk.clkr, 2733 [GCC_EMAC1_PHY_AUX_CLK_SRC] = &gcc_emac1_phy_aux_clk_src.clkr, 2734 [GCC_EMAC1_PTP_CLK] = &gcc_emac1_ptp_clk.clkr, 2735 [GCC_EMAC1_PTP_CLK_SRC] = &gcc_emac1_ptp_clk_src.clkr, 2736 [GCC_EMAC1_RGMII_CLK] = &gcc_emac1_rgmii_clk.clkr, 2737 [GCC_EMAC1_RGMII_CLK_SRC] = &gcc_emac1_rgmii_clk_src.clkr, 2738 [GCC_EMAC1_RPCS_RX_CLK] = &gcc_emac1_rpcs_rx_clk.clkr, 2739 [GCC_EMAC1_RPCS_TX_CLK] = &gcc_emac1_rpcs_tx_clk.clkr, 2740 [GCC_EMAC1_SGMIIPHY_MAC_RCLK_SRC] = &gcc_emac1_sgmiiphy_mac_rclk_src.clkr, 2741 [GCC_EMAC1_SGMIIPHY_MAC_TCLK_SRC] = &gcc_emac1_sgmiiphy_mac_tclk_src.clkr, 2742 [GCC_EMAC1_SLV_AHB_CLK] = &gcc_emac1_slv_ahb_clk.clkr, 2743 [GCC_EMAC1_XGXS_RX_CLK] = &gcc_emac1_xgxs_rx_clk.clkr, 2744 [GCC_EMAC1_XGXS_TX_CLK] = &gcc_emac1_xgxs_tx_clk.clkr, 2745 [GCC_EMAC_0_CLKREF_EN] = &gcc_emac_0_clkref_en.clkr, 2746 [GCC_EMAC_1_CLKREF_EN] = &gcc_emac_1_clkref_en.clkr, 2747 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2748 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2749 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2750 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2751 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2752 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2753 [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr, 2754 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 2755 [GCC_PCIE_1_AUX_PHY_CLK_SRC] = &gcc_pcie_1_aux_phy_clk_src.clkr, 2756 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 2757 [GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr, 2758 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 2759 [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr, 2760 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 2761 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 2762 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr, 2763 [GCC_PCIE_1_PIPE_DIV2_CLK] = &gcc_pcie_1_pipe_div2_clk.clkr, 2764 [GCC_PCIE_1_PIPE_DIV2_CLK_SRC] = &gcc_pcie_1_pipe_div2_clk_src.clkr, 2765 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 2766 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 2767 [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr, 2768 [GCC_PCIE_2_AUX_PHY_CLK_SRC] = &gcc_pcie_2_aux_phy_clk_src.clkr, 2769 [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr, 2770 [GCC_PCIE_2_CLKREF_EN] = &gcc_pcie_2_clkref_en.clkr, 2771 [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr, 2772 [GCC_PCIE_2_PHY_RCHNG_CLK] = &gcc_pcie_2_phy_rchng_clk.clkr, 2773 [GCC_PCIE_2_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2_phy_rchng_clk_src.clkr, 2774 [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr, 2775 [GCC_PCIE_2_PIPE_CLK_SRC] = &gcc_pcie_2_pipe_clk_src.clkr, 2776 [GCC_PCIE_2_PIPE_DIV2_CLK] = &gcc_pcie_2_pipe_div2_clk.clkr, 2777 [GCC_PCIE_2_PIPE_DIV2_CLK_SRC] = &gcc_pcie_2_pipe_div2_clk_src.clkr, 2778 [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr, 2779 [GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr, 2780 [GCC_PCIE_AUX_CLK] = &gcc_pcie_aux_clk.clkr, 2781 [GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr, 2782 [GCC_PCIE_AUX_PHY_CLK_SRC] = &gcc_pcie_aux_phy_clk_src.clkr, 2783 [GCC_PCIE_CFG_AHB_CLK] = &gcc_pcie_cfg_ahb_clk.clkr, 2784 [GCC_PCIE_MSTR_AXI_CLK] = &gcc_pcie_mstr_axi_clk.clkr, 2785 [GCC_PCIE_PIPE_CLK] = &gcc_pcie_pipe_clk.clkr, 2786 [GCC_PCIE_PIPE_CLK_SRC] = &gcc_pcie_pipe_clk_src.clkr, 2787 [GCC_PCIE_RCHNG_PHY_CLK] = &gcc_pcie_rchng_phy_clk.clkr, 2788 [GCC_PCIE_RCHNG_PHY_CLK_SRC] = &gcc_pcie_rchng_phy_clk_src.clkr, 2789 [GCC_PCIE_SLEEP_CLK] = &gcc_pcie_sleep_clk.clkr, 2790 [GCC_PCIE_SLV_AXI_CLK] = &gcc_pcie_slv_axi_clk.clkr, 2791 [GCC_PCIE_SLV_Q2A_AXI_CLK] = &gcc_pcie_slv_q2a_axi_clk.clkr, 2792 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2793 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 2794 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2795 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2796 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 2797 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 2798 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 2799 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 2800 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 2801 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 2802 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 2803 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 2804 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 2805 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 2806 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 2807 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 2808 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 2809 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 2810 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 2811 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 2812 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 2813 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 2814 [GCC_QUPV3_WRAP0_S8_CLK] = &gcc_qupv3_wrap0_s8_clk.clkr, 2815 [GCC_QUPV3_WRAP0_S8_CLK_SRC] = &gcc_qupv3_wrap0_s8_clk_src.clkr, 2816 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 2817 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 2818 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2819 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2820 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 2821 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2822 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2823 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 2824 [GCC_USB2_CLKREF_EN] = &gcc_usb2_clkref_en.clkr, 2825 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, 2826 [GCC_USB30_MASTER_CLK_SRC] = &gcc_usb30_master_clk_src.clkr, 2827 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 2828 [GCC_USB30_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mock_utmi_clk_src.clkr, 2829 [GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mock_utmi_postdiv_clk_src.clkr, 2830 [GCC_USB30_MSTR_AXI_CLK] = &gcc_usb30_mstr_axi_clk.clkr, 2831 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 2832 [GCC_USB30_SLV_AHB_CLK] = &gcc_usb30_slv_ahb_clk.clkr, 2833 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, 2834 [GCC_USB3_PHY_AUX_CLK_SRC] = &gcc_usb3_phy_aux_clk_src.clkr, 2835 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, 2836 [GCC_USB3_PHY_PIPE_CLK_SRC] = &gcc_usb3_phy_pipe_clk_src.clkr, 2837 [GCC_USB3_PRIM_CLKREF_EN] = &gcc_usb3_prim_clkref_en.clkr, 2838 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 2839 [GPLL0] = &gpll0.clkr, 2840 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 2841 [GPLL4] = &gpll4.clkr, 2842 [GPLL5] = &gpll5.clkr, 2843 [GPLL6] = &gpll6.clkr, 2844 [GPLL8] = &gpll8.clkr, 2845 }; 2846 2847 static struct gdsc *gcc_sdx75_gdscs[] = { 2848 [GCC_EMAC0_GDSC] = &gcc_emac0_gdsc, 2849 [GCC_EMAC1_GDSC] = &gcc_emac1_gdsc, 2850 [GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc, 2851 [GCC_PCIE_1_PHY_GDSC] = &gcc_pcie_1_phy_gdsc, 2852 [GCC_PCIE_2_GDSC] = &gcc_pcie_2_gdsc, 2853 [GCC_PCIE_2_PHY_GDSC] = &gcc_pcie_2_phy_gdsc, 2854 [GCC_PCIE_GDSC] = &gcc_pcie_gdsc, 2855 [GCC_PCIE_PHY_GDSC] = &gcc_pcie_phy_gdsc, 2856 [GCC_USB30_GDSC] = &gcc_usb30_gdsc, 2857 [GCC_USB3_PHY_GDSC] = &gcc_usb3_phy_gdsc, 2858 }; 2859 2860 static const struct qcom_reset_map gcc_sdx75_resets[] = { 2861 [GCC_EMAC0_BCR] = { 0x71000 }, 2862 [GCC_EMAC0_RGMII_CLK_ARES] = { 0x71050, 2 }, 2863 [GCC_EMAC1_BCR] = { 0x72000 }, 2864 [GCC_EMMC_BCR] = { 0x6b000 }, 2865 [GCC_PCIE_1_BCR] = { 0x67000 }, 2866 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x9e700 }, 2867 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x56120 }, 2868 [GCC_PCIE_1_PHY_BCR] = { 0x56000 }, 2869 [GCC_PCIE_2_BCR] = { 0x68000 }, 2870 [GCC_PCIE_2_LINK_DOWN_BCR] = { 0x9f700 }, 2871 [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x6e130 }, 2872 [GCC_PCIE_2_PHY_BCR] = { 0x6e000 }, 2873 [GCC_PCIE_BCR] = { 0x53000 }, 2874 [GCC_PCIE_LINK_DOWN_BCR] = { 0x87000 }, 2875 [GCC_PCIE_NOCSR_COM_PHY_BCR] = { 0x88008 }, 2876 [GCC_PCIE_PHY_BCR] = { 0x54000 }, 2877 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x88000 }, 2878 [GCC_PCIE_PHY_COM_BCR] = { 0x88004 }, 2879 [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x8800c }, 2880 [GCC_QUSB2PHY_BCR] = { 0x2a000 }, 2881 [GCC_TCSR_PCIE_BCR] = { 0x84000 }, 2882 [GCC_USB30_BCR] = { 0x27000 }, 2883 [GCC_USB3_PHY_BCR] = { 0x28000 }, 2884 [GCC_USB3PHY_PHY_BCR] = { 0x28004 }, 2885 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x29000 }, 2886 }; 2887 2888 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 2889 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 2890 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 2891 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 2892 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 2893 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 2894 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 2895 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 2896 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 2897 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s8_clk_src), 2898 }; 2899 2900 static const struct regmap_config gcc_sdx75_regmap_config = { 2901 .reg_bits = 32, 2902 .reg_stride = 4, 2903 .val_bits = 32, 2904 .max_register = 0x1f41f0, 2905 .fast_io = true, 2906 }; 2907 2908 static const struct qcom_cc_desc gcc_sdx75_desc = { 2909 .config = &gcc_sdx75_regmap_config, 2910 .clks = gcc_sdx75_clocks, 2911 .num_clks = ARRAY_SIZE(gcc_sdx75_clocks), 2912 .resets = gcc_sdx75_resets, 2913 .num_resets = ARRAY_SIZE(gcc_sdx75_resets), 2914 .gdscs = gcc_sdx75_gdscs, 2915 .num_gdscs = ARRAY_SIZE(gcc_sdx75_gdscs), 2916 }; 2917 2918 static const struct of_device_id gcc_sdx75_match_table[] = { 2919 { .compatible = "qcom,sdx75-gcc" }, 2920 { } 2921 }; 2922 MODULE_DEVICE_TABLE(of, gcc_sdx75_match_table); 2923 2924 static int gcc_sdx75_probe(struct platform_device *pdev) 2925 { 2926 struct regmap *regmap; 2927 int ret; 2928 2929 regmap = qcom_cc_map(pdev, &gcc_sdx75_desc); 2930 if (IS_ERR(regmap)) 2931 return PTR_ERR(regmap); 2932 2933 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 2934 ARRAY_SIZE(gcc_dfs_clocks)); 2935 if (ret) 2936 return ret; 2937 2938 /* 2939 * Keep clocks always enabled: 2940 * gcc_ahb_pcie_link_clk 2941 * gcc_xo_pcie_link_clk 2942 */ 2943 regmap_update_bits(regmap, 0x3e004, BIT(0), BIT(0)); 2944 regmap_update_bits(regmap, 0x3e008, BIT(0), BIT(0)); 2945 2946 return qcom_cc_really_probe(pdev, &gcc_sdx75_desc, regmap); 2947 } 2948 2949 static struct platform_driver gcc_sdx75_driver = { 2950 .probe = gcc_sdx75_probe, 2951 .driver = { 2952 .name = "gcc-sdx75", 2953 .of_match_table = gcc_sdx75_match_table, 2954 }, 2955 }; 2956 2957 static int __init gcc_sdx75_init(void) 2958 { 2959 return platform_driver_register(&gcc_sdx75_driver); 2960 } 2961 subsys_initcall(gcc_sdx75_init); 2962 2963 static void __exit gcc_sdx75_exit(void) 2964 { 2965 platform_driver_unregister(&gcc_sdx75_driver); 2966 } 2967 module_exit(gcc_sdx75_exit); 2968 2969 MODULE_DESCRIPTION("QTI GCC SDX75 Driver"); 2970 MODULE_LICENSE("GPL"); 2971