1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020, Linaro Ltd. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,gcc-sdx55.h> 13 14 #include "common.h" 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-pll.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "gdsc.h" 21 #include "reset.h" 22 23 enum { 24 P_BI_TCXO, 25 P_CORE_BI_PLL_TEST_SE, 26 P_GPLL0_OUT_EVEN, 27 P_GPLL0_OUT_MAIN, 28 P_GPLL4_OUT_EVEN, 29 P_GPLL5_OUT_MAIN, 30 P_SLEEP_CLK, 31 }; 32 33 static const struct pll_vco lucid_vco[] = { 34 { 249600000, 2000000000, 0 }, 35 }; 36 37 static struct clk_alpha_pll gpll0 = { 38 .offset = 0x0, 39 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 40 .vco_table = lucid_vco, 41 .num_vco = ARRAY_SIZE(lucid_vco), 42 .clkr = { 43 .enable_reg = 0x6d000, 44 .enable_mask = BIT(0), 45 .hw.init = &(struct clk_init_data){ 46 .name = "gpll0", 47 .parent_data = &(const struct clk_parent_data){ 48 .fw_name = "bi_tcxo", 49 }, 50 .num_parents = 1, 51 .ops = &clk_alpha_pll_fixed_lucid_ops, 52 }, 53 }, 54 }; 55 56 static const struct clk_div_table post_div_table_lucid_even[] = { 57 { 0x0, 1 }, 58 { 0x1, 2 }, 59 { 0x3, 4 }, 60 { 0x7, 8 }, 61 { } 62 }; 63 64 static struct clk_alpha_pll_postdiv gpll0_out_even = { 65 .offset = 0x0, 66 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 67 .post_div_shift = 8, 68 .post_div_table = post_div_table_lucid_even, 69 .num_post_div = ARRAY_SIZE(post_div_table_lucid_even), 70 .width = 4, 71 .clkr.hw.init = &(struct clk_init_data){ 72 .name = "gpll0_out_even", 73 .parent_hws = (const struct clk_hw*[]){ 74 &gpll0.clkr.hw, 75 }, 76 .num_parents = 1, 77 .ops = &clk_alpha_pll_postdiv_lucid_ops, 78 }, 79 }; 80 81 static struct clk_alpha_pll gpll4 = { 82 .offset = 0x76000, 83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 84 .vco_table = lucid_vco, 85 .num_vco = ARRAY_SIZE(lucid_vco), 86 .clkr = { 87 .enable_reg = 0x6d000, 88 .enable_mask = BIT(4), 89 .hw.init = &(struct clk_init_data){ 90 .name = "gpll4", 91 .parent_data = &(const struct clk_parent_data){ 92 .fw_name = "bi_tcxo", 93 }, 94 .num_parents = 1, 95 .ops = &clk_alpha_pll_fixed_lucid_ops, 96 }, 97 }, 98 }; 99 100 static struct clk_alpha_pll_postdiv gpll4_out_even = { 101 .offset = 0x76000, 102 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 103 .post_div_shift = 8, 104 .post_div_table = post_div_table_lucid_even, 105 .num_post_div = ARRAY_SIZE(post_div_table_lucid_even), 106 .width = 4, 107 .clkr.hw.init = &(struct clk_init_data){ 108 .name = "gpll4_out_even", 109 .parent_hws = (const struct clk_hw*[]){ 110 &gpll4.clkr.hw, 111 }, 112 .num_parents = 1, 113 .ops = &clk_alpha_pll_postdiv_lucid_ops, 114 }, 115 }; 116 117 static struct clk_alpha_pll gpll5 = { 118 .offset = 0x74000, 119 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 120 .vco_table = lucid_vco, 121 .num_vco = ARRAY_SIZE(lucid_vco), 122 .clkr = { 123 .enable_reg = 0x6d000, 124 .enable_mask = BIT(5), 125 .hw.init = &(struct clk_init_data){ 126 .name = "gpll5", 127 .parent_data = &(const struct clk_parent_data){ 128 .fw_name = "bi_tcxo", 129 }, 130 .num_parents = 1, 131 .ops = &clk_alpha_pll_fixed_lucid_ops, 132 }, 133 }, 134 }; 135 136 static const struct parent_map gcc_parent_map_0[] = { 137 { P_BI_TCXO, 0 }, 138 { P_GPLL0_OUT_MAIN, 1 }, 139 { P_GPLL0_OUT_EVEN, 6 }, 140 { P_CORE_BI_PLL_TEST_SE, 7 }, 141 }; 142 143 static const struct clk_parent_data gcc_parents_0[] = { 144 { .fw_name = "bi_tcxo" }, 145 { .hw = &gpll0.clkr.hw }, 146 { .hw = &gpll0_out_even.clkr.hw }, 147 { .fw_name = "core_bi_pll_test_se" }, 148 }; 149 150 static const struct clk_parent_data gcc_parents_0_ao[] = { 151 { .fw_name = "bi_tcxo_ao" }, 152 { .hw = &gpll0.clkr.hw }, 153 { .hw = &gpll0_out_even.clkr.hw }, 154 { .fw_name = "core_bi_pll_test_se" }, 155 }; 156 157 static const struct parent_map gcc_parent_map_2[] = { 158 { P_BI_TCXO, 0 }, 159 { P_GPLL0_OUT_MAIN, 1 }, 160 { P_GPLL4_OUT_EVEN, 2 }, 161 { P_GPLL5_OUT_MAIN, 5 }, 162 { P_GPLL0_OUT_EVEN, 6 }, 163 { P_CORE_BI_PLL_TEST_SE, 7 }, 164 }; 165 166 static const struct clk_parent_data gcc_parents_2[] = { 167 { .fw_name = "bi_tcxo" }, 168 { .hw = &gpll0.clkr.hw }, 169 { .hw = &gpll4_out_even.clkr.hw }, 170 { .hw = &gpll5.clkr.hw }, 171 { .hw = &gpll0_out_even.clkr.hw }, 172 { .fw_name = "core_bi_pll_test_se" }, 173 }; 174 175 static const struct parent_map gcc_parent_map_3[] = { 176 { P_BI_TCXO, 0 }, 177 { P_GPLL0_OUT_MAIN, 1 }, 178 { P_SLEEP_CLK, 5 }, 179 { P_GPLL0_OUT_EVEN, 6 }, 180 { P_CORE_BI_PLL_TEST_SE, 7 }, 181 }; 182 183 static const struct clk_parent_data gcc_parents_3[] = { 184 { .fw_name = "bi_tcxo" }, 185 { .hw = &gpll0.clkr.hw }, 186 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 187 { .hw = &gpll0_out_even.clkr.hw }, 188 { .fw_name = "core_bi_pll_test_se" }, 189 }; 190 191 static const struct parent_map gcc_parent_map_4[] = { 192 { P_BI_TCXO, 0 }, 193 { P_SLEEP_CLK, 5 }, 194 { P_CORE_BI_PLL_TEST_SE, 7 }, 195 }; 196 197 static const struct clk_parent_data gcc_parents_4[] = { 198 { .fw_name = "bi_tcxo" }, 199 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 200 { .fw_name = "core_bi_pll_test_se" }, 201 }; 202 203 static const struct parent_map gcc_parent_map_5[] = { 204 { P_BI_TCXO, 0 }, 205 { P_GPLL0_OUT_MAIN, 1 }, 206 { P_GPLL4_OUT_EVEN, 2 }, 207 { P_GPLL0_OUT_EVEN, 6 }, 208 { P_CORE_BI_PLL_TEST_SE, 7 }, 209 }; 210 211 static const struct clk_parent_data gcc_parents_5[] = { 212 { .fw_name = "bi_tcxo" }, 213 { .hw = &gpll0.clkr.hw }, 214 { .hw = &gpll4_out_even.clkr.hw }, 215 { .hw = &gpll0_out_even.clkr.hw }, 216 { .fw_name = "core_bi_pll_test_se" }, 217 }; 218 219 static const struct freq_tbl ftbl_gcc_blsp1_qup1_i2c_apps_clk_src[] = { 220 F(9600000, P_BI_TCXO, 2, 0, 0), 221 F(19200000, P_BI_TCXO, 1, 0, 0), 222 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 223 { } 224 }; 225 226 static struct clk_rcg2 gcc_blsp1_qup1_i2c_apps_clk_src = { 227 .cmd_rcgr = 0x11024, 228 .mnd_width = 8, 229 .hid_width = 5, 230 .parent_map = gcc_parent_map_0, 231 .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src, 232 .clkr.hw.init = &(struct clk_init_data){ 233 .name = "gcc_blsp1_qup1_i2c_apps_clk_src", 234 .parent_data = gcc_parents_0, 235 .num_parents = 4, 236 .ops = &clk_rcg2_ops, 237 }, 238 }; 239 240 static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = { 241 F(960000, P_BI_TCXO, 10, 1, 2), 242 F(4800000, P_BI_TCXO, 4, 0, 0), 243 F(9600000, P_BI_TCXO, 2, 0, 0), 244 F(15000000, P_GPLL0_OUT_EVEN, 5, 1, 4), 245 F(19200000, P_BI_TCXO, 1, 0, 0), 246 F(24000000, P_GPLL0_OUT_MAIN, 12.5, 1, 2), 247 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 248 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 249 { } 250 }; 251 252 static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = { 253 .cmd_rcgr = 0x1100c, 254 .mnd_width = 8, 255 .hid_width = 5, 256 .parent_map = gcc_parent_map_0, 257 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src, 258 .clkr.hw.init = &(struct clk_init_data){ 259 .name = "gcc_blsp1_qup1_spi_apps_clk_src", 260 .parent_data = gcc_parents_0, 261 .num_parents = 4, 262 .ops = &clk_rcg2_ops, 263 }, 264 }; 265 266 static struct clk_rcg2 gcc_blsp1_qup2_i2c_apps_clk_src = { 267 .cmd_rcgr = 0x13024, 268 .mnd_width = 8, 269 .hid_width = 5, 270 .parent_map = gcc_parent_map_0, 271 .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src, 272 .clkr.hw.init = &(struct clk_init_data){ 273 .name = "gcc_blsp1_qup2_i2c_apps_clk_src", 274 .parent_data = gcc_parents_0, 275 .num_parents = 4, 276 .ops = &clk_rcg2_ops, 277 }, 278 }; 279 280 static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = { 281 .cmd_rcgr = 0x1300c, 282 .mnd_width = 8, 283 .hid_width = 5, 284 .parent_map = gcc_parent_map_0, 285 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src, 286 .clkr.hw.init = &(struct clk_init_data){ 287 .name = "gcc_blsp1_qup2_spi_apps_clk_src", 288 .parent_data = gcc_parents_0, 289 .num_parents = 4, 290 .ops = &clk_rcg2_ops, 291 }, 292 }; 293 294 static struct clk_rcg2 gcc_blsp1_qup3_i2c_apps_clk_src = { 295 .cmd_rcgr = 0x15024, 296 .mnd_width = 8, 297 .hid_width = 5, 298 .parent_map = gcc_parent_map_0, 299 .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src, 300 .clkr.hw.init = &(struct clk_init_data){ 301 .name = "gcc_blsp1_qup3_i2c_apps_clk_src", 302 .parent_data = gcc_parents_0, 303 .num_parents = 4, 304 .ops = &clk_rcg2_ops, 305 }, 306 }; 307 308 static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = { 309 .cmd_rcgr = 0x1500c, 310 .mnd_width = 8, 311 .hid_width = 5, 312 .parent_map = gcc_parent_map_0, 313 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src, 314 .clkr.hw.init = &(struct clk_init_data){ 315 .name = "gcc_blsp1_qup3_spi_apps_clk_src", 316 .parent_data = gcc_parents_0, 317 .num_parents = 4, 318 .ops = &clk_rcg2_ops, 319 }, 320 }; 321 322 static struct clk_rcg2 gcc_blsp1_qup4_i2c_apps_clk_src = { 323 .cmd_rcgr = 0x17024, 324 .mnd_width = 8, 325 .hid_width = 5, 326 .parent_map = gcc_parent_map_0, 327 .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src, 328 .clkr.hw.init = &(struct clk_init_data){ 329 .name = "gcc_blsp1_qup4_i2c_apps_clk_src", 330 .parent_data = gcc_parents_0, 331 .num_parents = 4, 332 .ops = &clk_rcg2_ops, 333 }, 334 }; 335 336 static struct clk_rcg2 gcc_blsp1_qup4_spi_apps_clk_src = { 337 .cmd_rcgr = 0x1700c, 338 .mnd_width = 8, 339 .hid_width = 5, 340 .parent_map = gcc_parent_map_0, 341 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src, 342 .clkr.hw.init = &(struct clk_init_data){ 343 .name = "gcc_blsp1_qup4_spi_apps_clk_src", 344 .parent_data = gcc_parents_0, 345 .num_parents = 4, 346 .ops = &clk_rcg2_ops, 347 }, 348 }; 349 350 static const struct freq_tbl ftbl_gcc_blsp1_uart1_apps_clk_src[] = { 351 F(3686400, P_GPLL0_OUT_EVEN, 1, 192, 15625), 352 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 353 F(9600000, P_BI_TCXO, 2, 0, 0), 354 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 355 F(16000000, P_GPLL0_OUT_EVEN, 1, 4, 75), 356 F(19200000, P_BI_TCXO, 1, 0, 0), 357 F(19354839, P_GPLL0_OUT_MAIN, 15.5, 1, 2), 358 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2), 359 F(20689655, P_GPLL0_OUT_MAIN, 14.5, 1, 2), 360 F(21428571, P_GPLL0_OUT_MAIN, 14, 1, 2), 361 F(22222222, P_GPLL0_OUT_MAIN, 13.5, 1, 2), 362 F(23076923, P_GPLL0_OUT_MAIN, 13, 1, 2), 363 F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5), 364 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 365 F(26086957, P_GPLL0_OUT_MAIN, 11.5, 1, 2), 366 F(27272727, P_GPLL0_OUT_MAIN, 11, 1, 2), 367 F(28571429, P_GPLL0_OUT_MAIN, 10.5, 1, 2), 368 F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75), 369 F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0), 370 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375), 371 F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), 372 F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375), 373 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75), 374 F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625), 375 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 376 F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0), 377 { } 378 }; 379 380 static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = { 381 .cmd_rcgr = 0x1200c, 382 .mnd_width = 16, 383 .hid_width = 5, 384 .parent_map = gcc_parent_map_0, 385 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src, 386 .clkr.hw.init = &(struct clk_init_data){ 387 .name = "gcc_blsp1_uart1_apps_clk_src", 388 .parent_data = gcc_parents_0, 389 .num_parents = 4, 390 .ops = &clk_rcg2_ops, 391 }, 392 }; 393 394 static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = { 395 .cmd_rcgr = 0x1400c, 396 .mnd_width = 16, 397 .hid_width = 5, 398 .parent_map = gcc_parent_map_0, 399 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src, 400 .clkr.hw.init = &(struct clk_init_data){ 401 .name = "gcc_blsp1_uart2_apps_clk_src", 402 .parent_data = gcc_parents_0, 403 .num_parents = 4, 404 .ops = &clk_rcg2_ops, 405 }, 406 }; 407 408 static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = { 409 .cmd_rcgr = 0x1600c, 410 .mnd_width = 16, 411 .hid_width = 5, 412 .parent_map = gcc_parent_map_0, 413 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src, 414 .clkr.hw.init = &(struct clk_init_data){ 415 .name = "gcc_blsp1_uart3_apps_clk_src", 416 .parent_data = gcc_parents_0, 417 .num_parents = 4, 418 .ops = &clk_rcg2_ops, 419 }, 420 }; 421 422 static struct clk_rcg2 gcc_blsp1_uart4_apps_clk_src = { 423 .cmd_rcgr = 0x1800c, 424 .mnd_width = 16, 425 .hid_width = 5, 426 .parent_map = gcc_parent_map_0, 427 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src, 428 .clkr.hw.init = &(struct clk_init_data){ 429 .name = "gcc_blsp1_uart4_apps_clk_src", 430 .parent_data = gcc_parents_0, 431 .num_parents = 4, 432 .ops = &clk_rcg2_ops, 433 }, 434 }; 435 436 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { 437 F(19200000, P_BI_TCXO, 1, 0, 0), 438 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 439 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 440 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 441 { } 442 }; 443 444 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 445 .cmd_rcgr = 0x24010, 446 .mnd_width = 0, 447 .hid_width = 5, 448 .parent_map = gcc_parent_map_0, 449 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, 450 .clkr.hw.init = &(struct clk_init_data){ 451 .name = "gcc_cpuss_ahb_clk_src", 452 .parent_data = gcc_parents_0_ao, 453 .num_parents = 4, 454 .ops = &clk_rcg2_ops, 455 }, 456 }; 457 458 static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = { 459 F(19200000, P_BI_TCXO, 1, 0, 0), 460 { } 461 }; 462 463 static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = { 464 .cmd_rcgr = 0x2402c, 465 .mnd_width = 0, 466 .hid_width = 5, 467 .parent_map = gcc_parent_map_0, 468 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, 469 .clkr.hw.init = &(struct clk_init_data){ 470 .name = "gcc_cpuss_rbcpr_clk_src", 471 .parent_data = gcc_parents_0_ao, 472 .num_parents = 4, 473 .ops = &clk_rcg2_ops, 474 }, 475 }; 476 477 static const struct freq_tbl ftbl_gcc_emac_clk_src[] = { 478 F(2500000, P_BI_TCXO, 1, 25, 192), 479 F(5000000, P_BI_TCXO, 1, 25, 96), 480 F(19200000, P_BI_TCXO, 1, 0, 0), 481 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 482 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 483 F(250000000, P_GPLL4_OUT_EVEN, 2, 0, 0), 484 { } 485 }; 486 487 static struct clk_rcg2 gcc_emac_clk_src = { 488 .cmd_rcgr = 0x47020, 489 .mnd_width = 8, 490 .hid_width = 5, 491 .parent_map = gcc_parent_map_5, 492 .freq_tbl = ftbl_gcc_emac_clk_src, 493 .clkr.hw.init = &(struct clk_init_data){ 494 .name = "gcc_emac_clk_src", 495 .parent_data = gcc_parents_5, 496 .num_parents = 5, 497 .ops = &clk_rcg2_ops, 498 }, 499 }; 500 501 static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = { 502 F(19200000, P_BI_TCXO, 1, 0, 0), 503 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 504 F(230400000, P_GPLL5_OUT_MAIN, 3.5, 0, 0), 505 { } 506 }; 507 508 static struct clk_rcg2 gcc_emac_ptp_clk_src = { 509 .cmd_rcgr = 0x47038, 510 .mnd_width = 0, 511 .hid_width = 5, 512 .parent_map = gcc_parent_map_2, 513 .freq_tbl = ftbl_gcc_emac_ptp_clk_src, 514 .clkr.hw.init = &(struct clk_init_data){ 515 .name = "gcc_emac_ptp_clk_src", 516 .parent_data = gcc_parents_2, 517 .num_parents = 6, 518 .ops = &clk_rcg2_ops, 519 }, 520 }; 521 522 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 523 F(19200000, P_BI_TCXO, 1, 0, 0), 524 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 525 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 526 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 527 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 528 { } 529 }; 530 531 static struct clk_rcg2 gcc_gp1_clk_src = { 532 .cmd_rcgr = 0x2b004, 533 .mnd_width = 8, 534 .hid_width = 5, 535 .parent_map = gcc_parent_map_3, 536 .freq_tbl = ftbl_gcc_gp1_clk_src, 537 .clkr.hw.init = &(struct clk_init_data){ 538 .name = "gcc_gp1_clk_src", 539 .parent_data = gcc_parents_3, 540 .num_parents = 5, 541 .ops = &clk_rcg2_ops, 542 }, 543 }; 544 545 static struct clk_rcg2 gcc_gp2_clk_src = { 546 .cmd_rcgr = 0x2c004, 547 .mnd_width = 8, 548 .hid_width = 5, 549 .parent_map = gcc_parent_map_3, 550 .freq_tbl = ftbl_gcc_gp1_clk_src, 551 .clkr.hw.init = &(struct clk_init_data){ 552 .name = "gcc_gp2_clk_src", 553 .parent_data = gcc_parents_3, 554 .num_parents = 5, 555 .ops = &clk_rcg2_ops, 556 }, 557 }; 558 559 static struct clk_rcg2 gcc_gp3_clk_src = { 560 .cmd_rcgr = 0x2d004, 561 .mnd_width = 8, 562 .hid_width = 5, 563 .parent_map = gcc_parent_map_3, 564 .freq_tbl = ftbl_gcc_gp1_clk_src, 565 .clkr.hw.init = &(struct clk_init_data){ 566 .name = "gcc_gp3_clk_src", 567 .parent_data = gcc_parents_3, 568 .num_parents = 5, 569 .ops = &clk_rcg2_ops, 570 }, 571 }; 572 573 static struct clk_rcg2 gcc_pcie_aux_phy_clk_src = { 574 .cmd_rcgr = 0x37034, 575 .mnd_width = 16, 576 .hid_width = 5, 577 .parent_map = gcc_parent_map_4, 578 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, 579 .clkr.hw.init = &(struct clk_init_data){ 580 .name = "gcc_pcie_aux_phy_clk_src", 581 .parent_data = gcc_parents_4, 582 .num_parents = 3, 583 .ops = &clk_rcg2_ops, 584 }, 585 }; 586 587 static const struct freq_tbl ftbl_gcc_pcie_rchng_phy_clk_src[] = { 588 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 589 { } 590 }; 591 592 static struct clk_rcg2 gcc_pcie_rchng_phy_clk_src = { 593 .cmd_rcgr = 0x37050, 594 .mnd_width = 0, 595 .hid_width = 5, 596 .parent_map = gcc_parent_map_3, 597 .freq_tbl = ftbl_gcc_pcie_rchng_phy_clk_src, 598 .clkr.hw.init = &(struct clk_init_data){ 599 .name = "gcc_pcie_rchng_phy_clk_src", 600 .parent_data = gcc_parents_3, 601 .num_parents = 5, 602 .ops = &clk_rcg2_ops, 603 }, 604 }; 605 606 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 607 F(9600000, P_BI_TCXO, 2, 0, 0), 608 F(19200000, P_BI_TCXO, 1, 0, 0), 609 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 610 { } 611 }; 612 613 static struct clk_rcg2 gcc_pdm2_clk_src = { 614 .cmd_rcgr = 0x19010, 615 .mnd_width = 0, 616 .hid_width = 5, 617 .parent_map = gcc_parent_map_0, 618 .freq_tbl = ftbl_gcc_pdm2_clk_src, 619 .clkr.hw.init = &(struct clk_init_data){ 620 .name = "gcc_pdm2_clk_src", 621 .parent_data = gcc_parents_0, 622 .num_parents = 4, 623 .ops = &clk_rcg2_ops, 624 }, 625 }; 626 627 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 628 .cmd_rcgr = 0xf00c, 629 .mnd_width = 8, 630 .hid_width = 5, 631 .parent_map = gcc_parent_map_0, 632 .freq_tbl = ftbl_gcc_gp1_clk_src, 633 .clkr.hw.init = &(struct clk_init_data){ 634 .name = "gcc_sdcc1_apps_clk_src", 635 .parent_data = gcc_parents_0, 636 .num_parents = 4, 637 .ops = &clk_rcg2_ops, 638 }, 639 }; 640 641 static const struct freq_tbl ftbl_gcc_usb30_master_clk_src[] = { 642 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0), 643 { } 644 }; 645 646 static struct clk_rcg2 gcc_usb30_master_clk_src = { 647 .cmd_rcgr = 0xb024, 648 .mnd_width = 8, 649 .hid_width = 5, 650 .parent_map = gcc_parent_map_0, 651 .freq_tbl = ftbl_gcc_usb30_master_clk_src, 652 .clkr.hw.init = &(struct clk_init_data){ 653 .name = "gcc_usb30_master_clk_src", 654 .parent_data = gcc_parents_0, 655 .num_parents = 4, 656 .ops = &clk_rcg2_ops, 657 }, 658 }; 659 660 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = { 661 F(19200000, P_BI_TCXO, 1, 0, 0), 662 { } 663 }; 664 665 static struct clk_rcg2 gcc_usb30_mock_utmi_clk_src = { 666 .cmd_rcgr = 0xb03c, 667 .mnd_width = 0, 668 .hid_width = 5, 669 .parent_map = gcc_parent_map_0, 670 .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src, 671 .clkr.hw.init = &(struct clk_init_data){ 672 .name = "gcc_usb30_mock_utmi_clk_src", 673 .parent_data = gcc_parents_0, 674 .num_parents = 4, 675 .ops = &clk_rcg2_ops, 676 }, 677 }; 678 679 static const struct freq_tbl ftbl_gcc_usb3_phy_aux_clk_src[] = { 680 F(1000000, P_BI_TCXO, 1, 5, 96), 681 F(19200000, P_BI_TCXO, 1, 0, 0), 682 { } 683 }; 684 685 static struct clk_rcg2 gcc_usb3_phy_aux_clk_src = { 686 .cmd_rcgr = 0xb064, 687 .mnd_width = 16, 688 .hid_width = 5, 689 .parent_map = gcc_parent_map_4, 690 .freq_tbl = ftbl_gcc_usb3_phy_aux_clk_src, 691 .clkr.hw.init = &(struct clk_init_data){ 692 .name = "gcc_usb3_phy_aux_clk_src", 693 .parent_data = gcc_parents_4, 694 .num_parents = 3, 695 .ops = &clk_rcg2_ops, 696 }, 697 }; 698 699 static struct clk_branch gcc_ahb_pcie_link_clk = { 700 .halt_reg = 0x22004, 701 .halt_check = BRANCH_HALT, 702 .clkr = { 703 .enable_reg = 0x22004, 704 .enable_mask = BIT(0), 705 .hw.init = &(struct clk_init_data){ 706 .name = "gcc_ahb_pcie_link_clk", 707 .ops = &clk_branch2_ops, 708 }, 709 }, 710 }; 711 712 static struct clk_branch gcc_blsp1_ahb_clk = { 713 .halt_reg = 0x10004, 714 .halt_check = BRANCH_HALT_VOTED, 715 .clkr = { 716 .enable_reg = 0x6d008, 717 .enable_mask = BIT(14), 718 .hw.init = &(struct clk_init_data){ 719 .name = "gcc_blsp1_ahb_clk", 720 .ops = &clk_branch2_ops, 721 }, 722 }, 723 }; 724 725 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 726 .halt_reg = 0x11008, 727 .halt_check = BRANCH_HALT, 728 .clkr = { 729 .enable_reg = 0x11008, 730 .enable_mask = BIT(0), 731 .hw.init = &(struct clk_init_data){ 732 .name = "gcc_blsp1_qup1_i2c_apps_clk", 733 .parent_hws = (const struct clk_hw *[]){ 734 &gcc_blsp1_qup1_i2c_apps_clk_src.clkr.hw }, 735 .num_parents = 1, 736 .flags = CLK_SET_RATE_PARENT, 737 .ops = &clk_branch2_ops, 738 }, 739 }, 740 }; 741 742 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 743 .halt_reg = 0x11004, 744 .halt_check = BRANCH_HALT, 745 .clkr = { 746 .enable_reg = 0x11004, 747 .enable_mask = BIT(0), 748 .hw.init = &(struct clk_init_data){ 749 .name = "gcc_blsp1_qup1_spi_apps_clk", 750 .parent_hws = (const struct clk_hw *[]){ 751 &gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw }, 752 .num_parents = 1, 753 .flags = CLK_SET_RATE_PARENT, 754 .ops = &clk_branch2_ops, 755 }, 756 }, 757 }; 758 759 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 760 .halt_reg = 0x13008, 761 .halt_check = BRANCH_HALT, 762 .clkr = { 763 .enable_reg = 0x13008, 764 .enable_mask = BIT(0), 765 .hw.init = &(struct clk_init_data){ 766 .name = "gcc_blsp1_qup2_i2c_apps_clk", 767 .parent_hws = (const struct clk_hw *[]){ 768 &gcc_blsp1_qup2_i2c_apps_clk_src.clkr.hw }, 769 .num_parents = 1, 770 .flags = CLK_SET_RATE_PARENT, 771 .ops = &clk_branch2_ops, 772 }, 773 }, 774 }; 775 776 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 777 .halt_reg = 0x13004, 778 .halt_check = BRANCH_HALT, 779 .clkr = { 780 .enable_reg = 0x13004, 781 .enable_mask = BIT(0), 782 .hw.init = &(struct clk_init_data){ 783 .name = "gcc_blsp1_qup2_spi_apps_clk", 784 .parent_hws = (const struct clk_hw *[]){ 785 &gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw }, 786 .num_parents = 1, 787 .flags = CLK_SET_RATE_PARENT, 788 .ops = &clk_branch2_ops, 789 }, 790 }, 791 }; 792 793 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 794 .halt_reg = 0x15008, 795 .halt_check = BRANCH_HALT, 796 .clkr = { 797 .enable_reg = 0x15008, 798 .enable_mask = BIT(0), 799 .hw.init = &(struct clk_init_data){ 800 .name = "gcc_blsp1_qup3_i2c_apps_clk", 801 .parent_hws = (const struct clk_hw *[]){ 802 &gcc_blsp1_qup3_i2c_apps_clk_src.clkr.hw }, 803 .num_parents = 1, 804 .flags = CLK_SET_RATE_PARENT, 805 .ops = &clk_branch2_ops, 806 }, 807 }, 808 }; 809 810 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 811 .halt_reg = 0x15004, 812 .halt_check = BRANCH_HALT, 813 .clkr = { 814 .enable_reg = 0x15004, 815 .enable_mask = BIT(0), 816 .hw.init = &(struct clk_init_data){ 817 .name = "gcc_blsp1_qup3_spi_apps_clk", 818 .parent_hws = (const struct clk_hw *[]){ 819 &gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw }, 820 .num_parents = 1, 821 .flags = CLK_SET_RATE_PARENT, 822 .ops = &clk_branch2_ops, 823 }, 824 }, 825 }; 826 827 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 828 .halt_reg = 0x17008, 829 .halt_check = BRANCH_HALT, 830 .clkr = { 831 .enable_reg = 0x17008, 832 .enable_mask = BIT(0), 833 .hw.init = &(struct clk_init_data){ 834 .name = "gcc_blsp1_qup4_i2c_apps_clk", 835 .parent_hws = (const struct clk_hw *[]){ 836 &gcc_blsp1_qup4_i2c_apps_clk_src.clkr.hw }, 837 .num_parents = 1, 838 .flags = CLK_SET_RATE_PARENT, 839 .ops = &clk_branch2_ops, 840 }, 841 }, 842 }; 843 844 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 845 .halt_reg = 0x17004, 846 .halt_check = BRANCH_HALT, 847 .clkr = { 848 .enable_reg = 0x17004, 849 .enable_mask = BIT(0), 850 .hw.init = &(struct clk_init_data){ 851 .name = "gcc_blsp1_qup4_spi_apps_clk", 852 .parent_hws = (const struct clk_hw *[]){ 853 &gcc_blsp1_qup4_spi_apps_clk_src.clkr.hw }, 854 .num_parents = 1, 855 .flags = CLK_SET_RATE_PARENT, 856 .ops = &clk_branch2_ops, 857 }, 858 }, 859 }; 860 861 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 862 .halt_reg = 0x12004, 863 .halt_check = BRANCH_HALT, 864 .clkr = { 865 .enable_reg = 0x12004, 866 .enable_mask = BIT(0), 867 .hw.init = &(struct clk_init_data){ 868 .name = "gcc_blsp1_uart1_apps_clk", 869 .parent_hws = (const struct clk_hw *[]){ 870 &gcc_blsp1_uart1_apps_clk_src.clkr.hw }, 871 .num_parents = 1, 872 .flags = CLK_SET_RATE_PARENT, 873 .ops = &clk_branch2_ops, 874 }, 875 }, 876 }; 877 878 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 879 .halt_reg = 0x14004, 880 .halt_check = BRANCH_HALT, 881 .clkr = { 882 .enable_reg = 0x14004, 883 .enable_mask = BIT(0), 884 .hw.init = &(struct clk_init_data){ 885 .name = "gcc_blsp1_uart2_apps_clk", 886 .parent_hws = (const struct clk_hw *[]){ 887 &gcc_blsp1_uart2_apps_clk_src.clkr.hw }, 888 .num_parents = 1, 889 .flags = CLK_SET_RATE_PARENT, 890 .ops = &clk_branch2_ops, 891 }, 892 }, 893 }; 894 895 static struct clk_branch gcc_blsp1_uart3_apps_clk = { 896 .halt_reg = 0x16004, 897 .halt_check = BRANCH_HALT, 898 .clkr = { 899 .enable_reg = 0x16004, 900 .enable_mask = BIT(0), 901 .hw.init = &(struct clk_init_data){ 902 .name = "gcc_blsp1_uart3_apps_clk", 903 .parent_hws = (const struct clk_hw *[]){ 904 &gcc_blsp1_uart3_apps_clk_src.clkr.hw }, 905 .num_parents = 1, 906 .flags = CLK_SET_RATE_PARENT, 907 .ops = &clk_branch2_ops, 908 }, 909 }, 910 }; 911 912 static struct clk_branch gcc_blsp1_uart4_apps_clk = { 913 .halt_reg = 0x18004, 914 .halt_check = BRANCH_HALT, 915 .clkr = { 916 .enable_reg = 0x18004, 917 .enable_mask = BIT(0), 918 .hw.init = &(struct clk_init_data){ 919 .name = "gcc_blsp1_uart4_apps_clk", 920 .parent_hws = (const struct clk_hw *[]){ 921 &gcc_blsp1_uart4_apps_clk_src.clkr.hw }, 922 .num_parents = 1, 923 .flags = CLK_SET_RATE_PARENT, 924 .ops = &clk_branch2_ops, 925 }, 926 }, 927 }; 928 929 static struct clk_branch gcc_boot_rom_ahb_clk = { 930 .halt_reg = 0x1c004, 931 .halt_check = BRANCH_HALT_VOTED, 932 .hwcg_reg = 0x1c004, 933 .hwcg_bit = 1, 934 .clkr = { 935 .enable_reg = 0x6d008, 936 .enable_mask = BIT(10), 937 .hw.init = &(struct clk_init_data){ 938 .name = "gcc_boot_rom_ahb_clk", 939 .ops = &clk_branch2_ops, 940 }, 941 }, 942 }; 943 944 static struct clk_branch gcc_ce1_ahb_clk = { 945 .halt_reg = 0x2100c, 946 .halt_check = BRANCH_HALT_VOTED, 947 .hwcg_reg = 0x2100c, 948 .hwcg_bit = 1, 949 .clkr = { 950 .enable_reg = 0x6d008, 951 .enable_mask = BIT(3), 952 .hw.init = &(struct clk_init_data){ 953 .name = "gcc_ce1_ahb_clk", 954 .ops = &clk_branch2_ops, 955 }, 956 }, 957 }; 958 959 static struct clk_branch gcc_ce1_axi_clk = { 960 .halt_reg = 0x21008, 961 .halt_check = BRANCH_HALT_VOTED, 962 .clkr = { 963 .enable_reg = 0x6d008, 964 .enable_mask = BIT(4), 965 .hw.init = &(struct clk_init_data){ 966 .name = "gcc_ce1_axi_clk", 967 .ops = &clk_branch2_ops, 968 }, 969 }, 970 }; 971 972 static struct clk_branch gcc_ce1_clk = { 973 .halt_reg = 0x21004, 974 .halt_check = BRANCH_HALT_VOTED, 975 .clkr = { 976 .enable_reg = 0x6d008, 977 .enable_mask = BIT(5), 978 .hw.init = &(struct clk_init_data){ 979 .name = "gcc_ce1_clk", 980 .ops = &clk_branch2_ops, 981 }, 982 }, 983 }; 984 985 static struct clk_branch gcc_cpuss_rbcpr_clk = { 986 .halt_reg = 0x24008, 987 .halt_check = BRANCH_HALT, 988 .clkr = { 989 .enable_reg = 0x24008, 990 .enable_mask = BIT(0), 991 .hw.init = &(struct clk_init_data){ 992 .name = "gcc_cpuss_rbcpr_clk", 993 .parent_hws = (const struct clk_hw *[]){ 994 &gcc_cpuss_rbcpr_clk_src.clkr.hw }, 995 .num_parents = 1, 996 .flags = CLK_SET_RATE_PARENT, 997 .ops = &clk_branch2_ops, 998 }, 999 }, 1000 }; 1001 1002 static struct clk_branch gcc_eth_axi_clk = { 1003 .halt_reg = 0x4701c, 1004 .halt_check = BRANCH_HALT, 1005 .clkr = { 1006 .enable_reg = 0x4701c, 1007 .enable_mask = BIT(0), 1008 .hw.init = &(struct clk_init_data){ 1009 .name = "gcc_eth_axi_clk", 1010 .ops = &clk_branch2_ops, 1011 }, 1012 }, 1013 }; 1014 1015 static struct clk_branch gcc_eth_ptp_clk = { 1016 .halt_reg = 0x47018, 1017 .halt_check = BRANCH_HALT, 1018 .clkr = { 1019 .enable_reg = 0x47018, 1020 .enable_mask = BIT(0), 1021 .hw.init = &(struct clk_init_data){ 1022 .name = "gcc_eth_ptp_clk", 1023 .parent_hws = (const struct clk_hw *[]){ 1024 &gcc_emac_ptp_clk_src.clkr.hw }, 1025 .num_parents = 1, 1026 .flags = CLK_SET_RATE_PARENT, 1027 .ops = &clk_branch2_ops, 1028 }, 1029 }, 1030 }; 1031 1032 static struct clk_branch gcc_eth_rgmii_clk = { 1033 .halt_reg = 0x47010, 1034 .halt_check = BRANCH_HALT, 1035 .clkr = { 1036 .enable_reg = 0x47010, 1037 .enable_mask = BIT(0), 1038 .hw.init = &(struct clk_init_data){ 1039 .name = "gcc_eth_rgmii_clk", 1040 .parent_hws = (const struct clk_hw *[]){ 1041 &gcc_emac_clk_src.clkr.hw }, 1042 .num_parents = 1, 1043 .flags = CLK_SET_RATE_PARENT, 1044 .ops = &clk_branch2_ops, 1045 }, 1046 }, 1047 }; 1048 1049 static struct clk_branch gcc_eth_slave_ahb_clk = { 1050 .halt_reg = 0x47014, 1051 .halt_check = BRANCH_HALT, 1052 .clkr = { 1053 .enable_reg = 0x47014, 1054 .enable_mask = BIT(0), 1055 .hw.init = &(struct clk_init_data){ 1056 .name = "gcc_eth_slave_ahb_clk", 1057 .ops = &clk_branch2_ops, 1058 }, 1059 }, 1060 }; 1061 1062 static struct clk_branch gcc_gp1_clk = { 1063 .halt_reg = 0x2b000, 1064 .halt_check = BRANCH_HALT, 1065 .clkr = { 1066 .enable_reg = 0x2b000, 1067 .enable_mask = BIT(0), 1068 .hw.init = &(struct clk_init_data){ 1069 .name = "gcc_gp1_clk", 1070 .parent_hws = (const struct clk_hw *[]){ 1071 &gcc_gp1_clk_src.clkr.hw }, 1072 .num_parents = 1, 1073 .flags = CLK_SET_RATE_PARENT, 1074 .ops = &clk_branch2_ops, 1075 }, 1076 }, 1077 }; 1078 1079 static struct clk_branch gcc_gp2_clk = { 1080 .halt_reg = 0x2c000, 1081 .halt_check = BRANCH_HALT, 1082 .clkr = { 1083 .enable_reg = 0x2c000, 1084 .enable_mask = BIT(0), 1085 .hw.init = &(struct clk_init_data){ 1086 .name = "gcc_gp2_clk", 1087 .parent_hws = (const struct clk_hw *[]){ 1088 &gcc_gp2_clk_src.clkr.hw }, 1089 .num_parents = 1, 1090 .flags = CLK_SET_RATE_PARENT, 1091 .ops = &clk_branch2_ops, 1092 }, 1093 }, 1094 }; 1095 1096 static struct clk_branch gcc_gp3_clk = { 1097 .halt_reg = 0x2d000, 1098 .halt_check = BRANCH_HALT, 1099 .clkr = { 1100 .enable_reg = 0x2d000, 1101 .enable_mask = BIT(0), 1102 .hw.init = &(struct clk_init_data){ 1103 .name = "gcc_gp3_clk", 1104 .parent_hws = (const struct clk_hw *[]){ 1105 &gcc_gp3_clk_src.clkr.hw }, 1106 .num_parents = 1, 1107 .flags = CLK_SET_RATE_PARENT, 1108 .ops = &clk_branch2_ops, 1109 }, 1110 }, 1111 }; 1112 1113 static struct clk_branch gcc_pcie_0_clkref_clk = { 1114 .halt_reg = 0x88004, 1115 .halt_check = BRANCH_HALT_DELAY, 1116 .clkr = { 1117 .enable_reg = 0x88004, 1118 .enable_mask = BIT(0), 1119 .hw.init = &(struct clk_init_data){ 1120 .name = "gcc_pcie_0_clkref_clk", 1121 .ops = &clk_branch2_ops, 1122 }, 1123 }, 1124 }; 1125 1126 static struct clk_branch gcc_pcie_aux_clk = { 1127 .halt_reg = 0x37024, 1128 .halt_check = BRANCH_HALT_DELAY, 1129 .clkr = { 1130 .enable_reg = 0x6d010, 1131 .enable_mask = BIT(3), 1132 .hw.init = &(struct clk_init_data){ 1133 .name = "gcc_pcie_aux_clk", 1134 .ops = &clk_branch2_ops, 1135 }, 1136 }, 1137 }; 1138 1139 static struct clk_branch gcc_pcie_cfg_ahb_clk = { 1140 .halt_reg = 0x3701c, 1141 .halt_check = BRANCH_HALT_VOTED, 1142 .clkr = { 1143 .enable_reg = 0x6d010, 1144 .enable_mask = BIT(2), 1145 .hw.init = &(struct clk_init_data){ 1146 .name = "gcc_pcie_cfg_ahb_clk", 1147 .ops = &clk_branch2_ops, 1148 }, 1149 }, 1150 }; 1151 1152 static struct clk_branch gcc_pcie_mstr_axi_clk = { 1153 .halt_reg = 0x37018, 1154 .halt_check = BRANCH_HALT_VOTED, 1155 .clkr = { 1156 .enable_reg = 0x6d010, 1157 .enable_mask = BIT(1), 1158 .hw.init = &(struct clk_init_data){ 1159 .name = "gcc_pcie_mstr_axi_clk", 1160 .ops = &clk_branch2_ops, 1161 }, 1162 }, 1163 }; 1164 1165 static struct clk_branch gcc_pcie_pipe_clk = { 1166 .halt_reg = 0x3702c, 1167 .halt_check = BRANCH_HALT_DELAY, 1168 .clkr = { 1169 .enable_reg = 0x6d010, 1170 .enable_mask = BIT(4), 1171 .hw.init = &(struct clk_init_data){ 1172 .name = "gcc_pcie_pipe_clk", 1173 .ops = &clk_branch2_ops, 1174 }, 1175 }, 1176 }; 1177 1178 static struct clk_branch gcc_pcie_rchng_phy_clk = { 1179 .halt_reg = 0x37020, 1180 .halt_check = BRANCH_HALT_VOTED, 1181 .clkr = { 1182 .enable_reg = 0x6d010, 1183 .enable_mask = BIT(7), 1184 .hw.init = &(struct clk_init_data){ 1185 .name = "gcc_pcie_rchng_phy_clk", 1186 .parent_hws = (const struct clk_hw *[]){ 1187 &gcc_pcie_rchng_phy_clk_src.clkr.hw }, 1188 .num_parents = 1, 1189 .flags = CLK_SET_RATE_PARENT, 1190 .ops = &clk_branch2_ops, 1191 }, 1192 }, 1193 }; 1194 1195 static struct clk_branch gcc_pcie_sleep_clk = { 1196 .halt_reg = 0x37028, 1197 .halt_check = BRANCH_HALT_VOTED, 1198 .clkr = { 1199 .enable_reg = 0x6d010, 1200 .enable_mask = BIT(6), 1201 .hw.init = &(struct clk_init_data){ 1202 .name = "gcc_pcie_sleep_clk", 1203 .parent_hws = (const struct clk_hw *[]){ 1204 &gcc_pcie_aux_phy_clk_src.clkr.hw }, 1205 .num_parents = 1, 1206 .flags = CLK_SET_RATE_PARENT, 1207 .ops = &clk_branch2_ops, 1208 }, 1209 }, 1210 }; 1211 1212 static struct clk_branch gcc_pcie_slv_axi_clk = { 1213 .halt_reg = 0x37014, 1214 .halt_check = BRANCH_HALT_VOTED, 1215 .hwcg_reg = 0x37014, 1216 .hwcg_bit = 1, 1217 .clkr = { 1218 .enable_reg = 0x6d010, 1219 .enable_mask = BIT(0), 1220 .hw.init = &(struct clk_init_data){ 1221 .name = "gcc_pcie_slv_axi_clk", 1222 .ops = &clk_branch2_ops, 1223 }, 1224 }, 1225 }; 1226 1227 static struct clk_branch gcc_pcie_slv_q2a_axi_clk = { 1228 .halt_reg = 0x37010, 1229 .halt_check = BRANCH_HALT_VOTED, 1230 .clkr = { 1231 .enable_reg = 0x6d010, 1232 .enable_mask = BIT(5), 1233 .hw.init = &(struct clk_init_data){ 1234 .name = "gcc_pcie_slv_q2a_axi_clk", 1235 .ops = &clk_branch2_ops, 1236 }, 1237 }, 1238 }; 1239 1240 static struct clk_branch gcc_pdm2_clk = { 1241 .halt_reg = 0x1900c, 1242 .halt_check = BRANCH_HALT, 1243 .clkr = { 1244 .enable_reg = 0x1900c, 1245 .enable_mask = BIT(0), 1246 .hw.init = &(struct clk_init_data){ 1247 .name = "gcc_pdm2_clk", 1248 .parent_hws = (const struct clk_hw *[]){ 1249 &gcc_pdm2_clk_src.clkr.hw }, 1250 .num_parents = 1, 1251 .flags = CLK_SET_RATE_PARENT, 1252 .ops = &clk_branch2_ops, 1253 }, 1254 }, 1255 }; 1256 1257 static struct clk_branch gcc_pdm_ahb_clk = { 1258 .halt_reg = 0x19004, 1259 .halt_check = BRANCH_HALT, 1260 .hwcg_reg = 0x19004, 1261 .hwcg_bit = 1, 1262 .clkr = { 1263 .enable_reg = 0x19004, 1264 .enable_mask = BIT(0), 1265 .hw.init = &(struct clk_init_data){ 1266 .name = "gcc_pdm_ahb_clk", 1267 .ops = &clk_branch2_ops, 1268 }, 1269 }, 1270 }; 1271 1272 static struct clk_branch gcc_pdm_xo4_clk = { 1273 .halt_reg = 0x19008, 1274 .halt_check = BRANCH_HALT, 1275 .clkr = { 1276 .enable_reg = 0x19008, 1277 .enable_mask = BIT(0), 1278 .hw.init = &(struct clk_init_data){ 1279 .name = "gcc_pdm_xo4_clk", 1280 .ops = &clk_branch2_ops, 1281 }, 1282 }, 1283 }; 1284 1285 static struct clk_branch gcc_sdcc1_ahb_clk = { 1286 .halt_reg = 0xf008, 1287 .halt_check = BRANCH_HALT, 1288 .clkr = { 1289 .enable_reg = 0xf008, 1290 .enable_mask = BIT(0), 1291 .hw.init = &(struct clk_init_data){ 1292 .name = "gcc_sdcc1_ahb_clk", 1293 .ops = &clk_branch2_ops, 1294 }, 1295 }, 1296 }; 1297 1298 static struct clk_branch gcc_sdcc1_apps_clk = { 1299 .halt_reg = 0xf004, 1300 .halt_check = BRANCH_HALT, 1301 .clkr = { 1302 .enable_reg = 0xf004, 1303 .enable_mask = BIT(0), 1304 .hw.init = &(struct clk_init_data){ 1305 .name = "gcc_sdcc1_apps_clk", 1306 .parent_hws = (const struct clk_hw *[]){ 1307 &gcc_sdcc1_apps_clk_src.clkr.hw }, 1308 .num_parents = 1, 1309 .flags = CLK_SET_RATE_PARENT, 1310 .ops = &clk_branch2_ops, 1311 }, 1312 }, 1313 }; 1314 1315 static struct clk_branch gcc_usb30_master_clk = { 1316 .halt_reg = 0xb010, 1317 .halt_check = BRANCH_HALT, 1318 .clkr = { 1319 .enable_reg = 0xb010, 1320 .enable_mask = BIT(0), 1321 .hw.init = &(struct clk_init_data){ 1322 .name = "gcc_usb30_master_clk", 1323 .parent_hws = (const struct clk_hw *[]){ 1324 &gcc_usb30_master_clk_src.clkr.hw }, 1325 .num_parents = 1, 1326 .flags = CLK_SET_RATE_PARENT, 1327 .ops = &clk_branch2_ops, 1328 }, 1329 }, 1330 }; 1331 1332 static struct clk_branch gcc_usb30_mock_utmi_clk = { 1333 .halt_reg = 0xb020, 1334 .halt_check = BRANCH_HALT, 1335 .clkr = { 1336 .enable_reg = 0xb020, 1337 .enable_mask = BIT(0), 1338 .hw.init = &(struct clk_init_data){ 1339 .name = "gcc_usb30_mock_utmi_clk", 1340 .parent_hws = (const struct clk_hw *[]){ 1341 &gcc_usb30_mock_utmi_clk_src.clkr.hw }, 1342 .num_parents = 1, 1343 .flags = CLK_SET_RATE_PARENT, 1344 .ops = &clk_branch2_ops, 1345 }, 1346 }, 1347 }; 1348 1349 static struct clk_branch gcc_usb30_mstr_axi_clk = { 1350 .halt_reg = 0xb014, 1351 .halt_check = BRANCH_HALT, 1352 .clkr = { 1353 .enable_reg = 0xb014, 1354 .enable_mask = BIT(0), 1355 .hw.init = &(struct clk_init_data){ 1356 .name = "gcc_usb30_mstr_axi_clk", 1357 .ops = &clk_branch2_ops, 1358 }, 1359 }, 1360 }; 1361 1362 static struct clk_branch gcc_usb30_sleep_clk = { 1363 .halt_reg = 0xb01c, 1364 .halt_check = BRANCH_HALT, 1365 .clkr = { 1366 .enable_reg = 0xb01c, 1367 .enable_mask = BIT(0), 1368 .hw.init = &(struct clk_init_data){ 1369 .name = "gcc_usb30_sleep_clk", 1370 .ops = &clk_branch2_ops, 1371 }, 1372 }, 1373 }; 1374 1375 static struct clk_branch gcc_usb30_slv_ahb_clk = { 1376 .halt_reg = 0xb018, 1377 .halt_check = BRANCH_HALT, 1378 .clkr = { 1379 .enable_reg = 0xb018, 1380 .enable_mask = BIT(0), 1381 .hw.init = &(struct clk_init_data){ 1382 .name = "gcc_usb30_slv_ahb_clk", 1383 .ops = &clk_branch2_ops, 1384 }, 1385 }, 1386 }; 1387 1388 static struct clk_branch gcc_usb3_phy_aux_clk = { 1389 .halt_reg = 0xb058, 1390 .halt_check = BRANCH_HALT, 1391 .clkr = { 1392 .enable_reg = 0xb058, 1393 .enable_mask = BIT(0), 1394 .hw.init = &(struct clk_init_data){ 1395 .name = "gcc_usb3_phy_aux_clk", 1396 .parent_hws = (const struct clk_hw *[]){ 1397 &gcc_usb3_phy_aux_clk_src.clkr.hw }, 1398 .num_parents = 1, 1399 .flags = CLK_SET_RATE_PARENT, 1400 .ops = &clk_branch2_ops, 1401 }, 1402 }, 1403 }; 1404 1405 static struct clk_branch gcc_usb3_phy_pipe_clk = { 1406 .halt_reg = 0xb05c, 1407 .halt_check = BRANCH_HALT_DELAY, 1408 .clkr = { 1409 .enable_reg = 0xb05c, 1410 .enable_mask = BIT(0), 1411 .hw.init = &(struct clk_init_data){ 1412 .name = "gcc_usb3_phy_pipe_clk", 1413 .ops = &clk_branch2_ops, 1414 }, 1415 }, 1416 }; 1417 1418 static struct clk_branch gcc_usb3_prim_clkref_clk = { 1419 .halt_reg = 0x88000, 1420 .halt_check = BRANCH_HALT_DELAY, 1421 .clkr = { 1422 .enable_reg = 0x88000, 1423 .enable_mask = BIT(0), 1424 .hw.init = &(struct clk_init_data){ 1425 .name = "gcc_usb3_prim_clkref_clk", 1426 .ops = &clk_branch2_ops, 1427 }, 1428 }, 1429 }; 1430 1431 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 1432 .halt_reg = 0xe004, 1433 .halt_check = BRANCH_HALT, 1434 .hwcg_reg = 0xe004, 1435 .hwcg_bit = 1, 1436 .clkr = { 1437 .enable_reg = 0xe004, 1438 .enable_mask = BIT(0), 1439 .hw.init = &(struct clk_init_data){ 1440 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 1441 .ops = &clk_branch2_ops, 1442 }, 1443 }, 1444 }; 1445 1446 static struct clk_branch gcc_xo_pcie_link_clk = { 1447 .halt_reg = 0x22008, 1448 .halt_check = BRANCH_HALT, 1449 .clkr = { 1450 .enable_reg = 0x22008, 1451 .enable_mask = BIT(0), 1452 .hw.init = &(struct clk_init_data){ 1453 .name = "gcc_xo_pcie_link_clk", 1454 .ops = &clk_branch2_ops, 1455 }, 1456 }, 1457 }; 1458 1459 static struct gdsc usb30_gdsc = { 1460 .gdscr = 0x0b004, 1461 .pd = { 1462 .name = "usb30_gdsc", 1463 }, 1464 .pwrsts = PWRSTS_OFF_ON, 1465 }; 1466 1467 static struct gdsc pcie_gdsc = { 1468 .gdscr = 0x37004, 1469 .pd = { 1470 .name = "pcie_gdsc", 1471 }, 1472 .pwrsts = PWRSTS_OFF_ON, 1473 }; 1474 1475 static struct gdsc emac_gdsc = { 1476 .gdscr = 0x47004, 1477 .pd = { 1478 .name = "emac_gdsc", 1479 }, 1480 .pwrsts = PWRSTS_OFF_ON, 1481 }; 1482 1483 static struct clk_regmap *gcc_sdx55_clocks[] = { 1484 [GCC_AHB_PCIE_LINK_CLK] = &gcc_ahb_pcie_link_clk.clkr, 1485 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 1486 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 1487 [GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] = 1488 &gcc_blsp1_qup1_i2c_apps_clk_src.clkr, 1489 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 1490 [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = 1491 &gcc_blsp1_qup1_spi_apps_clk_src.clkr, 1492 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 1493 [GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] = 1494 &gcc_blsp1_qup2_i2c_apps_clk_src.clkr, 1495 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 1496 [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = 1497 &gcc_blsp1_qup2_spi_apps_clk_src.clkr, 1498 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 1499 [GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] = 1500 &gcc_blsp1_qup3_i2c_apps_clk_src.clkr, 1501 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 1502 [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = 1503 &gcc_blsp1_qup3_spi_apps_clk_src.clkr, 1504 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 1505 [GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] = 1506 &gcc_blsp1_qup4_i2c_apps_clk_src.clkr, 1507 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 1508 [GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] = 1509 &gcc_blsp1_qup4_spi_apps_clk_src.clkr, 1510 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 1511 [GCC_BLSP1_UART1_APPS_CLK_SRC] = &gcc_blsp1_uart1_apps_clk_src.clkr, 1512 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 1513 [GCC_BLSP1_UART2_APPS_CLK_SRC] = &gcc_blsp1_uart2_apps_clk_src.clkr, 1514 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 1515 [GCC_BLSP1_UART3_APPS_CLK_SRC] = &gcc_blsp1_uart3_apps_clk_src.clkr, 1516 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, 1517 [GCC_BLSP1_UART4_APPS_CLK_SRC] = &gcc_blsp1_uart4_apps_clk_src.clkr, 1518 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 1519 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, 1520 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, 1521 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, 1522 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, 1523 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, 1524 [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr, 1525 [GCC_EMAC_CLK_SRC] = &gcc_emac_clk_src.clkr, 1526 [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr, 1527 [GCC_ETH_AXI_CLK] = &gcc_eth_axi_clk.clkr, 1528 [GCC_ETH_PTP_CLK] = &gcc_eth_ptp_clk.clkr, 1529 [GCC_ETH_RGMII_CLK] = &gcc_eth_rgmii_clk.clkr, 1530 [GCC_ETH_SLAVE_AHB_CLK] = &gcc_eth_slave_ahb_clk.clkr, 1531 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 1532 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 1533 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 1534 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 1535 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 1536 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 1537 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr, 1538 [GCC_PCIE_AUX_CLK] = &gcc_pcie_aux_clk.clkr, 1539 [GCC_PCIE_AUX_PHY_CLK_SRC] = &gcc_pcie_aux_phy_clk_src.clkr, 1540 [GCC_PCIE_CFG_AHB_CLK] = &gcc_pcie_cfg_ahb_clk.clkr, 1541 [GCC_PCIE_MSTR_AXI_CLK] = &gcc_pcie_mstr_axi_clk.clkr, 1542 [GCC_PCIE_PIPE_CLK] = &gcc_pcie_pipe_clk.clkr, 1543 [GCC_PCIE_RCHNG_PHY_CLK] = &gcc_pcie_rchng_phy_clk.clkr, 1544 [GCC_PCIE_RCHNG_PHY_CLK_SRC] = &gcc_pcie_rchng_phy_clk_src.clkr, 1545 [GCC_PCIE_SLEEP_CLK] = &gcc_pcie_sleep_clk.clkr, 1546 [GCC_PCIE_SLV_AXI_CLK] = &gcc_pcie_slv_axi_clk.clkr, 1547 [GCC_PCIE_SLV_Q2A_AXI_CLK] = &gcc_pcie_slv_q2a_axi_clk.clkr, 1548 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 1549 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 1550 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 1551 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 1552 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 1553 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 1554 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 1555 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, 1556 [GCC_USB30_MASTER_CLK_SRC] = &gcc_usb30_master_clk_src.clkr, 1557 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 1558 [GCC_USB30_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mock_utmi_clk_src.clkr, 1559 [GCC_USB30_MSTR_AXI_CLK] = &gcc_usb30_mstr_axi_clk.clkr, 1560 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 1561 [GCC_USB30_SLV_AHB_CLK] = &gcc_usb30_slv_ahb_clk.clkr, 1562 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, 1563 [GCC_USB3_PHY_AUX_CLK_SRC] = &gcc_usb3_phy_aux_clk_src.clkr, 1564 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, 1565 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 1566 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 1567 [GCC_XO_PCIE_LINK_CLK] = &gcc_xo_pcie_link_clk.clkr, 1568 [GPLL0] = &gpll0.clkr, 1569 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 1570 [GPLL4] = &gpll4.clkr, 1571 [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr, 1572 [GPLL5] = &gpll5.clkr, 1573 }; 1574 1575 static const struct qcom_reset_map gcc_sdx55_resets[] = { 1576 [GCC_EMAC_BCR] = { 0x47000 }, 1577 [GCC_PCIE_BCR] = { 0x37000 }, 1578 [GCC_PCIE_LINK_DOWN_BCR] = { 0x77000 }, 1579 [GCC_PCIE_PHY_BCR] = { 0x39000 }, 1580 [GCC_PCIE_PHY_COM_BCR] = { 0x78004 }, 1581 [GCC_QUSB2PHY_BCR] = { 0xd000 }, 1582 [GCC_USB30_BCR] = { 0xb000 }, 1583 [GCC_USB3_PHY_BCR] = { 0xc000 }, 1584 [GCC_USB3PHY_PHY_BCR] = { 0xc004 }, 1585 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0xe000 }, 1586 }; 1587 1588 static struct gdsc *gcc_sdx55_gdscs[] = { 1589 [USB30_GDSC] = &usb30_gdsc, 1590 [PCIE_GDSC] = &pcie_gdsc, 1591 [EMAC_GDSC] = &emac_gdsc, 1592 }; 1593 1594 static const struct regmap_config gcc_sdx55_regmap_config = { 1595 .reg_bits = 32, 1596 .reg_stride = 4, 1597 .val_bits = 32, 1598 .max_register = 0x9b040, 1599 .fast_io = true, 1600 }; 1601 1602 static const struct qcom_cc_desc gcc_sdx55_desc = { 1603 .config = &gcc_sdx55_regmap_config, 1604 .clks = gcc_sdx55_clocks, 1605 .num_clks = ARRAY_SIZE(gcc_sdx55_clocks), 1606 .resets = gcc_sdx55_resets, 1607 .num_resets = ARRAY_SIZE(gcc_sdx55_resets), 1608 .gdscs = gcc_sdx55_gdscs, 1609 .num_gdscs = ARRAY_SIZE(gcc_sdx55_gdscs), 1610 }; 1611 1612 static const struct of_device_id gcc_sdx55_match_table[] = { 1613 { .compatible = "qcom,gcc-sdx55" }, 1614 { } 1615 }; 1616 MODULE_DEVICE_TABLE(of, gcc_sdx55_match_table); 1617 1618 static int gcc_sdx55_probe(struct platform_device *pdev) 1619 { 1620 struct regmap *regmap; 1621 1622 regmap = qcom_cc_map(pdev, &gcc_sdx55_desc); 1623 if (IS_ERR(regmap)) 1624 return PTR_ERR(regmap); 1625 1626 /* 1627 * Keep the clocks always-ON as they are critical to the functioning 1628 * of the system: 1629 * GCC_SYS_NOC_CPUSS_AHB_CLK, GCC_CPUSS_AHB_CLK, GCC_CPUSS_GNOC_CLK 1630 */ 1631 regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0)); 1632 regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); 1633 regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); 1634 1635 return qcom_cc_really_probe(pdev, &gcc_sdx55_desc, regmap); 1636 } 1637 1638 static struct platform_driver gcc_sdx55_driver = { 1639 .probe = gcc_sdx55_probe, 1640 .driver = { 1641 .name = "gcc-sdx55", 1642 .of_match_table = gcc_sdx55_match_table, 1643 }, 1644 }; 1645 1646 static int __init gcc_sdx55_init(void) 1647 { 1648 return platform_driver_register(&gcc_sdx55_driver); 1649 } 1650 subsys_initcall(gcc_sdx55_init); 1651 1652 static void __exit gcc_sdx55_exit(void) 1653 { 1654 platform_driver_unregister(&gcc_sdx55_driver); 1655 } 1656 module_exit(gcc_sdx55_exit); 1657 1658 MODULE_DESCRIPTION("QTI GCC SDX55 Driver"); 1659 MODULE_LICENSE("GPL v2"); 1660