1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/bitops.h> 8 #include <linux/err.h> 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/clk-provider.h> 14 #include <linux/regmap.h> 15 #include <linux/reset-controller.h> 16 17 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 18 19 #include "common.h" 20 #include "clk-regmap.h" 21 #include "clk-pll.h" 22 #include "clk-rcg.h" 23 #include "clk-branch.h" 24 #include "clk-alpha-pll.h" 25 #include "gdsc.h" 26 #include "reset.h" 27 28 enum { 29 P_BI_TCXO, 30 P_AUD_REF_CLK, 31 P_CORE_BI_PLL_TEST_SE, 32 P_GPLL0_OUT_EVEN, 33 P_GPLL0_OUT_MAIN, 34 P_GPLL4_OUT_MAIN, 35 P_SLEEP_CLK, 36 }; 37 38 static const struct parent_map gcc_parent_map_0[] = { 39 { P_BI_TCXO, 0 }, 40 { P_GPLL0_OUT_MAIN, 1 }, 41 { P_GPLL0_OUT_EVEN, 6 }, 42 { P_CORE_BI_PLL_TEST_SE, 7 }, 43 }; 44 45 static const char * const gcc_parent_names_0[] = { 46 "bi_tcxo", 47 "gpll0", 48 "gpll0_out_even", 49 "core_bi_pll_test_se", 50 }; 51 52 static const struct parent_map gcc_parent_map_1[] = { 53 { P_BI_TCXO, 0 }, 54 { P_GPLL0_OUT_MAIN, 1 }, 55 { P_SLEEP_CLK, 5 }, 56 { P_GPLL0_OUT_EVEN, 6 }, 57 { P_CORE_BI_PLL_TEST_SE, 7 }, 58 }; 59 60 static const char * const gcc_parent_names_1[] = { 61 "bi_tcxo", 62 "gpll0", 63 "core_pi_sleep_clk", 64 "gpll0_out_even", 65 "core_bi_pll_test_se", 66 }; 67 68 static const struct parent_map gcc_parent_map_2[] = { 69 { P_BI_TCXO, 0 }, 70 { P_SLEEP_CLK, 5 }, 71 { P_CORE_BI_PLL_TEST_SE, 7 }, 72 }; 73 74 static const char * const gcc_parent_names_2[] = { 75 "bi_tcxo", 76 "core_pi_sleep_clk", 77 "core_bi_pll_test_se", 78 }; 79 80 static const struct parent_map gcc_parent_map_3[] = { 81 { P_BI_TCXO, 0 }, 82 { P_GPLL0_OUT_MAIN, 1 }, 83 { P_CORE_BI_PLL_TEST_SE, 7 }, 84 }; 85 86 static const char * const gcc_parent_names_3[] = { 87 "bi_tcxo", 88 "gpll0", 89 "core_bi_pll_test_se", 90 }; 91 92 static const struct parent_map gcc_parent_map_4[] = { 93 { P_BI_TCXO, 0 }, 94 { P_CORE_BI_PLL_TEST_SE, 7 }, 95 }; 96 97 static const char * const gcc_parent_names_4[] = { 98 "bi_tcxo", 99 "core_bi_pll_test_se", 100 }; 101 102 static const struct parent_map gcc_parent_map_6[] = { 103 { P_BI_TCXO, 0 }, 104 { P_GPLL0_OUT_MAIN, 1 }, 105 { P_AUD_REF_CLK, 2 }, 106 { P_GPLL0_OUT_EVEN, 6 }, 107 { P_CORE_BI_PLL_TEST_SE, 7 }, 108 }; 109 110 static const char * const gcc_parent_names_6[] = { 111 "bi_tcxo", 112 "gpll0", 113 "aud_ref_clk", 114 "gpll0_out_even", 115 "core_bi_pll_test_se", 116 }; 117 118 static const char * const gcc_parent_names_7_ao[] = { 119 "bi_tcxo_ao", 120 "gpll0", 121 "gpll0_out_even", 122 "core_bi_pll_test_se", 123 }; 124 125 static const char * const gcc_parent_names_8[] = { 126 "bi_tcxo", 127 "gpll0", 128 "core_bi_pll_test_se", 129 }; 130 131 static const char * const gcc_parent_names_8_ao[] = { 132 "bi_tcxo_ao", 133 "gpll0", 134 "core_bi_pll_test_se", 135 }; 136 137 static const struct parent_map gcc_parent_map_10[] = { 138 { P_BI_TCXO, 0 }, 139 { P_GPLL0_OUT_MAIN, 1 }, 140 { P_GPLL4_OUT_MAIN, 5 }, 141 { P_GPLL0_OUT_EVEN, 6 }, 142 { P_CORE_BI_PLL_TEST_SE, 7 }, 143 }; 144 145 static const char * const gcc_parent_names_10[] = { 146 "bi_tcxo", 147 "gpll0", 148 "gpll4", 149 "gpll0_out_even", 150 "core_bi_pll_test_se", 151 }; 152 153 static struct clk_alpha_pll gpll0 = { 154 .offset = 0x0, 155 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 156 .clkr = { 157 .enable_reg = 0x52000, 158 .enable_mask = BIT(0), 159 .hw.init = &(struct clk_init_data){ 160 .name = "gpll0", 161 .parent_names = (const char *[]){ "bi_tcxo" }, 162 .num_parents = 1, 163 .ops = &clk_alpha_pll_fixed_fabia_ops, 164 }, 165 }, 166 }; 167 168 static struct clk_alpha_pll gpll4 = { 169 .offset = 0x76000, 170 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 171 .clkr = { 172 .enable_reg = 0x52000, 173 .enable_mask = BIT(4), 174 .hw.init = &(struct clk_init_data){ 175 .name = "gpll4", 176 .parent_names = (const char *[]){ "bi_tcxo" }, 177 .num_parents = 1, 178 .ops = &clk_alpha_pll_fixed_fabia_ops, 179 }, 180 }, 181 }; 182 183 static const struct clk_div_table post_div_table_fabia_even[] = { 184 { 0x0, 1 }, 185 { 0x1, 2 }, 186 { 0x3, 4 }, 187 { 0x7, 8 }, 188 { } 189 }; 190 191 static struct clk_alpha_pll_postdiv gpll0_out_even = { 192 .offset = 0x0, 193 .post_div_shift = 8, 194 .post_div_table = post_div_table_fabia_even, 195 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 196 .width = 4, 197 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 198 .clkr.hw.init = &(struct clk_init_data){ 199 .name = "gpll0_out_even", 200 .parent_names = (const char *[]){ "gpll0" }, 201 .num_parents = 1, 202 .ops = &clk_alpha_pll_postdiv_fabia_ops, 203 }, 204 }; 205 206 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { 207 F(19200000, P_BI_TCXO, 1, 0, 0), 208 { } 209 }; 210 211 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 212 .cmd_rcgr = 0x48014, 213 .mnd_width = 0, 214 .hid_width = 5, 215 .parent_map = gcc_parent_map_0, 216 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, 217 .clkr.hw.init = &(struct clk_init_data){ 218 .name = "gcc_cpuss_ahb_clk_src", 219 .parent_names = gcc_parent_names_7_ao, 220 .num_parents = 4, 221 .ops = &clk_rcg2_ops, 222 }, 223 }; 224 225 static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = { 226 F(19200000, P_BI_TCXO, 1, 0, 0), 227 { } 228 }; 229 230 static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = { 231 .cmd_rcgr = 0x4815c, 232 .mnd_width = 0, 233 .hid_width = 5, 234 .parent_map = gcc_parent_map_3, 235 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, 236 .clkr.hw.init = &(struct clk_init_data){ 237 .name = "gcc_cpuss_rbcpr_clk_src", 238 .parent_names = gcc_parent_names_8_ao, 239 .num_parents = 3, 240 .ops = &clk_rcg2_ops, 241 }, 242 }; 243 244 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 245 F(19200000, P_BI_TCXO, 1, 0, 0), 246 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 247 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 248 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 249 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 250 { } 251 }; 252 253 static struct clk_rcg2 gcc_gp1_clk_src = { 254 .cmd_rcgr = 0x64004, 255 .mnd_width = 8, 256 .hid_width = 5, 257 .parent_map = gcc_parent_map_1, 258 .freq_tbl = ftbl_gcc_gp1_clk_src, 259 .clkr.hw.init = &(struct clk_init_data){ 260 .name = "gcc_gp1_clk_src", 261 .parent_names = gcc_parent_names_1, 262 .num_parents = 5, 263 .ops = &clk_rcg2_ops, 264 }, 265 }; 266 267 static struct clk_rcg2 gcc_gp2_clk_src = { 268 .cmd_rcgr = 0x65004, 269 .mnd_width = 8, 270 .hid_width = 5, 271 .parent_map = gcc_parent_map_1, 272 .freq_tbl = ftbl_gcc_gp1_clk_src, 273 .clkr.hw.init = &(struct clk_init_data){ 274 .name = "gcc_gp2_clk_src", 275 .parent_names = gcc_parent_names_1, 276 .num_parents = 5, 277 .ops = &clk_rcg2_ops, 278 }, 279 }; 280 281 static struct clk_rcg2 gcc_gp3_clk_src = { 282 .cmd_rcgr = 0x66004, 283 .mnd_width = 8, 284 .hid_width = 5, 285 .parent_map = gcc_parent_map_1, 286 .freq_tbl = ftbl_gcc_gp1_clk_src, 287 .clkr.hw.init = &(struct clk_init_data){ 288 .name = "gcc_gp3_clk_src", 289 .parent_names = gcc_parent_names_1, 290 .num_parents = 5, 291 .ops = &clk_rcg2_ops, 292 }, 293 }; 294 295 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 296 F(9600000, P_BI_TCXO, 2, 0, 0), 297 F(19200000, P_BI_TCXO, 1, 0, 0), 298 { } 299 }; 300 301 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 302 .cmd_rcgr = 0x6b028, 303 .mnd_width = 16, 304 .hid_width = 5, 305 .parent_map = gcc_parent_map_2, 306 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 307 .clkr.hw.init = &(struct clk_init_data){ 308 .name = "gcc_pcie_0_aux_clk_src", 309 .parent_names = gcc_parent_names_2, 310 .num_parents = 3, 311 .ops = &clk_rcg2_ops, 312 }, 313 }; 314 315 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 316 .cmd_rcgr = 0x8d028, 317 .mnd_width = 16, 318 .hid_width = 5, 319 .parent_map = gcc_parent_map_2, 320 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 321 .clkr.hw.init = &(struct clk_init_data){ 322 .name = "gcc_pcie_1_aux_clk_src", 323 .parent_names = gcc_parent_names_2, 324 .num_parents = 3, 325 .ops = &clk_rcg2_ops, 326 }, 327 }; 328 329 static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { 330 F(19200000, P_BI_TCXO, 1, 0, 0), 331 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 332 { } 333 }; 334 335 static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { 336 .cmd_rcgr = 0x6f014, 337 .mnd_width = 0, 338 .hid_width = 5, 339 .parent_map = gcc_parent_map_0, 340 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, 341 .clkr.hw.init = &(struct clk_init_data){ 342 .name = "gcc_pcie_phy_refgen_clk_src", 343 .parent_names = gcc_parent_names_0, 344 .num_parents = 4, 345 .ops = &clk_rcg2_ops, 346 }, 347 }; 348 349 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { 350 F(19200000, P_BI_TCXO, 1, 0, 0), 351 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 352 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 353 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 354 { } 355 }; 356 357 static struct clk_rcg2 gcc_qspi_core_clk_src = { 358 .cmd_rcgr = 0x4b008, 359 .mnd_width = 0, 360 .hid_width = 5, 361 .parent_map = gcc_parent_map_0, 362 .freq_tbl = ftbl_gcc_qspi_core_clk_src, 363 .clkr.hw.init = &(struct clk_init_data){ 364 .name = "gcc_qspi_core_clk_src", 365 .parent_names = gcc_parent_names_0, 366 .num_parents = 4, 367 .ops = &clk_rcg2_floor_ops, 368 }, 369 }; 370 371 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 372 F(9600000, P_BI_TCXO, 2, 0, 0), 373 F(19200000, P_BI_TCXO, 1, 0, 0), 374 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 375 { } 376 }; 377 378 static struct clk_rcg2 gcc_pdm2_clk_src = { 379 .cmd_rcgr = 0x33010, 380 .mnd_width = 0, 381 .hid_width = 5, 382 .parent_map = gcc_parent_map_0, 383 .freq_tbl = ftbl_gcc_pdm2_clk_src, 384 .clkr.hw.init = &(struct clk_init_data){ 385 .name = "gcc_pdm2_clk_src", 386 .parent_names = gcc_parent_names_0, 387 .num_parents = 4, 388 .ops = &clk_rcg2_ops, 389 }, 390 }; 391 392 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 393 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 394 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 395 F(19200000, P_BI_TCXO, 1, 0, 0), 396 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 397 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 398 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 399 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 400 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 401 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 402 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 403 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), 404 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), 405 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), 406 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), 407 F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75), 408 { } 409 }; 410 411 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_init = { 412 .name = "gcc_qupv3_wrap0_s0_clk_src", 413 .parent_names = gcc_parent_names_0, 414 .num_parents = 4, 415 .ops = &clk_rcg2_shared_ops, 416 }; 417 418 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 419 .cmd_rcgr = 0x17034, 420 .mnd_width = 16, 421 .hid_width = 5, 422 .parent_map = gcc_parent_map_0, 423 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 424 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_init, 425 }; 426 427 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_init = { 428 .name = "gcc_qupv3_wrap0_s1_clk_src", 429 .parent_names = gcc_parent_names_0, 430 .num_parents = 4, 431 .ops = &clk_rcg2_shared_ops, 432 }; 433 434 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 435 .cmd_rcgr = 0x17164, 436 .mnd_width = 16, 437 .hid_width = 5, 438 .parent_map = gcc_parent_map_0, 439 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 440 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_init, 441 }; 442 443 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_init = { 444 .name = "gcc_qupv3_wrap0_s2_clk_src", 445 .parent_names = gcc_parent_names_0, 446 .num_parents = 4, 447 .ops = &clk_rcg2_shared_ops, 448 }; 449 450 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 451 .cmd_rcgr = 0x17294, 452 .mnd_width = 16, 453 .hid_width = 5, 454 .parent_map = gcc_parent_map_0, 455 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 456 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_init, 457 }; 458 459 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_init = { 460 .name = "gcc_qupv3_wrap0_s3_clk_src", 461 .parent_names = gcc_parent_names_0, 462 .num_parents = 4, 463 .ops = &clk_rcg2_shared_ops, 464 }; 465 466 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 467 .cmd_rcgr = 0x173c4, 468 .mnd_width = 16, 469 .hid_width = 5, 470 .parent_map = gcc_parent_map_0, 471 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 472 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_init, 473 }; 474 475 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_init = { 476 .name = "gcc_qupv3_wrap0_s4_clk_src", 477 .parent_names = gcc_parent_names_0, 478 .num_parents = 4, 479 .ops = &clk_rcg2_shared_ops, 480 }; 481 482 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 483 .cmd_rcgr = 0x174f4, 484 .mnd_width = 16, 485 .hid_width = 5, 486 .parent_map = gcc_parent_map_0, 487 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 488 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_init, 489 }; 490 491 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_init = { 492 .name = "gcc_qupv3_wrap0_s5_clk_src", 493 .parent_names = gcc_parent_names_0, 494 .num_parents = 4, 495 .ops = &clk_rcg2_shared_ops, 496 }; 497 498 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 499 .cmd_rcgr = 0x17624, 500 .mnd_width = 16, 501 .hid_width = 5, 502 .parent_map = gcc_parent_map_0, 503 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 504 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_init, 505 }; 506 507 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_init = { 508 .name = "gcc_qupv3_wrap0_s6_clk_src", 509 .parent_names = gcc_parent_names_0, 510 .num_parents = 4, 511 .ops = &clk_rcg2_shared_ops, 512 }; 513 514 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 515 .cmd_rcgr = 0x17754, 516 .mnd_width = 16, 517 .hid_width = 5, 518 .parent_map = gcc_parent_map_0, 519 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 520 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_init, 521 }; 522 523 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_init = { 524 .name = "gcc_qupv3_wrap0_s7_clk_src", 525 .parent_names = gcc_parent_names_0, 526 .num_parents = 4, 527 .ops = &clk_rcg2_shared_ops, 528 }; 529 530 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 531 .cmd_rcgr = 0x17884, 532 .mnd_width = 16, 533 .hid_width = 5, 534 .parent_map = gcc_parent_map_0, 535 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 536 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_init, 537 }; 538 539 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_init = { 540 .name = "gcc_qupv3_wrap1_s0_clk_src", 541 .parent_names = gcc_parent_names_0, 542 .num_parents = 4, 543 .ops = &clk_rcg2_shared_ops, 544 }; 545 546 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 547 .cmd_rcgr = 0x18018, 548 .mnd_width = 16, 549 .hid_width = 5, 550 .parent_map = gcc_parent_map_0, 551 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 552 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_init, 553 }; 554 555 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_init = { 556 .name = "gcc_qupv3_wrap1_s1_clk_src", 557 .parent_names = gcc_parent_names_0, 558 .num_parents = 4, 559 .ops = &clk_rcg2_shared_ops, 560 }; 561 562 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 563 .cmd_rcgr = 0x18148, 564 .mnd_width = 16, 565 .hid_width = 5, 566 .parent_map = gcc_parent_map_0, 567 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 568 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_init, 569 }; 570 571 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_init = { 572 .name = "gcc_qupv3_wrap1_s2_clk_src", 573 .parent_names = gcc_parent_names_0, 574 .num_parents = 4, 575 .ops = &clk_rcg2_shared_ops, 576 }; 577 578 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 579 .cmd_rcgr = 0x18278, 580 .mnd_width = 16, 581 .hid_width = 5, 582 .parent_map = gcc_parent_map_0, 583 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 584 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_init, 585 }; 586 587 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_init = { 588 .name = "gcc_qupv3_wrap1_s3_clk_src", 589 .parent_names = gcc_parent_names_0, 590 .num_parents = 4, 591 .ops = &clk_rcg2_shared_ops, 592 }; 593 594 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 595 .cmd_rcgr = 0x183a8, 596 .mnd_width = 16, 597 .hid_width = 5, 598 .parent_map = gcc_parent_map_0, 599 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 600 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_init, 601 }; 602 603 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_init = { 604 .name = "gcc_qupv3_wrap1_s4_clk_src", 605 .parent_names = gcc_parent_names_0, 606 .num_parents = 4, 607 .ops = &clk_rcg2_shared_ops, 608 }; 609 610 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 611 .cmd_rcgr = 0x184d8, 612 .mnd_width = 16, 613 .hid_width = 5, 614 .parent_map = gcc_parent_map_0, 615 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 616 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_init, 617 }; 618 619 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_init = { 620 .name = "gcc_qupv3_wrap1_s5_clk_src", 621 .parent_names = gcc_parent_names_0, 622 .num_parents = 4, 623 .ops = &clk_rcg2_shared_ops, 624 }; 625 626 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 627 .cmd_rcgr = 0x18608, 628 .mnd_width = 16, 629 .hid_width = 5, 630 .parent_map = gcc_parent_map_0, 631 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 632 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_init, 633 }; 634 635 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_init = { 636 .name = "gcc_qupv3_wrap1_s6_clk_src", 637 .parent_names = gcc_parent_names_0, 638 .num_parents = 4, 639 .ops = &clk_rcg2_shared_ops, 640 }; 641 642 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 643 .cmd_rcgr = 0x18738, 644 .mnd_width = 16, 645 .hid_width = 5, 646 .parent_map = gcc_parent_map_0, 647 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 648 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_init, 649 }; 650 651 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_init = { 652 .name = "gcc_qupv3_wrap1_s7_clk_src", 653 .parent_names = gcc_parent_names_0, 654 .num_parents = 4, 655 .ops = &clk_rcg2_shared_ops, 656 }; 657 658 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 659 .cmd_rcgr = 0x18868, 660 .mnd_width = 16, 661 .hid_width = 5, 662 .parent_map = gcc_parent_map_0, 663 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 664 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_init, 665 }; 666 667 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 668 F(400000, P_BI_TCXO, 12, 1, 4), 669 F(9600000, P_BI_TCXO, 2, 0, 0), 670 F(19200000, P_BI_TCXO, 1, 0, 0), 671 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 672 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 673 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 674 F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0), 675 { } 676 }; 677 678 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 679 .cmd_rcgr = 0x1400c, 680 .mnd_width = 8, 681 .hid_width = 5, 682 .parent_map = gcc_parent_map_10, 683 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 684 .clkr.hw.init = &(struct clk_init_data){ 685 .name = "gcc_sdcc2_apps_clk_src", 686 .parent_names = gcc_parent_names_10, 687 .num_parents = 5, 688 .ops = &clk_rcg2_ops, 689 }, 690 }; 691 692 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 693 F(400000, P_BI_TCXO, 12, 1, 4), 694 F(9600000, P_BI_TCXO, 2, 0, 0), 695 F(19200000, P_BI_TCXO, 1, 0, 0), 696 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 697 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 698 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 699 { } 700 }; 701 702 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 703 .cmd_rcgr = 0x1600c, 704 .mnd_width = 8, 705 .hid_width = 5, 706 .parent_map = gcc_parent_map_0, 707 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 708 .clkr.hw.init = &(struct clk_init_data){ 709 .name = "gcc_sdcc4_apps_clk_src", 710 .parent_names = gcc_parent_names_0, 711 .num_parents = 4, 712 .ops = &clk_rcg2_ops, 713 }, 714 }; 715 716 static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { 717 F(105495, P_BI_TCXO, 2, 1, 91), 718 { } 719 }; 720 721 static struct clk_rcg2 gcc_tsif_ref_clk_src = { 722 .cmd_rcgr = 0x36010, 723 .mnd_width = 8, 724 .hid_width = 5, 725 .parent_map = gcc_parent_map_6, 726 .freq_tbl = ftbl_gcc_tsif_ref_clk_src, 727 .clkr.hw.init = &(struct clk_init_data){ 728 .name = "gcc_tsif_ref_clk_src", 729 .parent_names = gcc_parent_names_6, 730 .num_parents = 5, 731 .ops = &clk_rcg2_ops, 732 }, 733 }; 734 735 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { 736 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 737 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 738 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 739 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 740 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 741 { } 742 }; 743 744 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { 745 .cmd_rcgr = 0x7501c, 746 .mnd_width = 8, 747 .hid_width = 5, 748 .parent_map = gcc_parent_map_0, 749 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, 750 .clkr.hw.init = &(struct clk_init_data){ 751 .name = "gcc_ufs_card_axi_clk_src", 752 .parent_names = gcc_parent_names_0, 753 .num_parents = 4, 754 .ops = &clk_rcg2_shared_ops, 755 }, 756 }; 757 758 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { 759 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 760 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 761 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 762 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 763 { } 764 }; 765 766 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { 767 .cmd_rcgr = 0x7505c, 768 .mnd_width = 0, 769 .hid_width = 5, 770 .parent_map = gcc_parent_map_0, 771 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 772 .clkr.hw.init = &(struct clk_init_data){ 773 .name = "gcc_ufs_card_ice_core_clk_src", 774 .parent_names = gcc_parent_names_0, 775 .num_parents = 4, 776 .ops = &clk_rcg2_shared_ops, 777 }, 778 }; 779 780 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { 781 .cmd_rcgr = 0x75090, 782 .mnd_width = 0, 783 .hid_width = 5, 784 .parent_map = gcc_parent_map_4, 785 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, 786 .clkr.hw.init = &(struct clk_init_data){ 787 .name = "gcc_ufs_card_phy_aux_clk_src", 788 .parent_names = gcc_parent_names_4, 789 .num_parents = 2, 790 .ops = &clk_rcg2_ops, 791 }, 792 }; 793 794 static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { 795 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 796 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 797 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 798 { } 799 }; 800 801 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { 802 .cmd_rcgr = 0x75074, 803 .mnd_width = 0, 804 .hid_width = 5, 805 .parent_map = gcc_parent_map_0, 806 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, 807 .clkr.hw.init = &(struct clk_init_data){ 808 .name = "gcc_ufs_card_unipro_core_clk_src", 809 .parent_names = gcc_parent_names_0, 810 .num_parents = 4, 811 .ops = &clk_rcg2_shared_ops, 812 }, 813 }; 814 815 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 816 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 817 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 818 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 819 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 820 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 821 { } 822 }; 823 824 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 825 .cmd_rcgr = 0x7701c, 826 .mnd_width = 8, 827 .hid_width = 5, 828 .parent_map = gcc_parent_map_0, 829 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 830 .clkr.hw.init = &(struct clk_init_data){ 831 .name = "gcc_ufs_phy_axi_clk_src", 832 .parent_names = gcc_parent_names_0, 833 .num_parents = 4, 834 .ops = &clk_rcg2_shared_ops, 835 }, 836 }; 837 838 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 839 .cmd_rcgr = 0x7705c, 840 .mnd_width = 0, 841 .hid_width = 5, 842 .parent_map = gcc_parent_map_0, 843 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 844 .clkr.hw.init = &(struct clk_init_data){ 845 .name = "gcc_ufs_phy_ice_core_clk_src", 846 .parent_names = gcc_parent_names_0, 847 .num_parents = 4, 848 .ops = &clk_rcg2_shared_ops, 849 }, 850 }; 851 852 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 853 .cmd_rcgr = 0x77090, 854 .mnd_width = 0, 855 .hid_width = 5, 856 .parent_map = gcc_parent_map_4, 857 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 858 .clkr.hw.init = &(struct clk_init_data){ 859 .name = "gcc_ufs_phy_phy_aux_clk_src", 860 .parent_names = gcc_parent_names_4, 861 .num_parents = 2, 862 .ops = &clk_rcg2_shared_ops, 863 }, 864 }; 865 866 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 867 .cmd_rcgr = 0x77074, 868 .mnd_width = 0, 869 .hid_width = 5, 870 .parent_map = gcc_parent_map_0, 871 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, 872 .clkr.hw.init = &(struct clk_init_data){ 873 .name = "gcc_ufs_phy_unipro_core_clk_src", 874 .parent_names = gcc_parent_names_0, 875 .num_parents = 4, 876 .ops = &clk_rcg2_shared_ops, 877 }, 878 }; 879 880 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 881 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), 882 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), 883 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 884 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 885 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 886 { } 887 }; 888 889 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 890 .cmd_rcgr = 0xf018, 891 .mnd_width = 8, 892 .hid_width = 5, 893 .parent_map = gcc_parent_map_0, 894 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 895 .clkr.hw.init = &(struct clk_init_data){ 896 .name = "gcc_usb30_prim_master_clk_src", 897 .parent_names = gcc_parent_names_0, 898 .num_parents = 4, 899 .ops = &clk_rcg2_shared_ops, 900 }, 901 }; 902 903 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 904 F(19200000, P_BI_TCXO, 1, 0, 0), 905 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), 906 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0), 907 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 908 { } 909 }; 910 911 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 912 .cmd_rcgr = 0xf030, 913 .mnd_width = 0, 914 .hid_width = 5, 915 .parent_map = gcc_parent_map_0, 916 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 917 .clkr.hw.init = &(struct clk_init_data){ 918 .name = "gcc_usb30_prim_mock_utmi_clk_src", 919 .parent_names = gcc_parent_names_0, 920 .num_parents = 4, 921 .ops = &clk_rcg2_shared_ops, 922 }, 923 }; 924 925 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { 926 .cmd_rcgr = 0x10018, 927 .mnd_width = 8, 928 .hid_width = 5, 929 .parent_map = gcc_parent_map_0, 930 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 931 .clkr.hw.init = &(struct clk_init_data){ 932 .name = "gcc_usb30_sec_master_clk_src", 933 .parent_names = gcc_parent_names_0, 934 .num_parents = 4, 935 .ops = &clk_rcg2_ops, 936 }, 937 }; 938 939 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { 940 .cmd_rcgr = 0x10030, 941 .mnd_width = 0, 942 .hid_width = 5, 943 .parent_map = gcc_parent_map_0, 944 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 945 .clkr.hw.init = &(struct clk_init_data){ 946 .name = "gcc_usb30_sec_mock_utmi_clk_src", 947 .parent_names = gcc_parent_names_0, 948 .num_parents = 4, 949 .ops = &clk_rcg2_ops, 950 }, 951 }; 952 953 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 954 .cmd_rcgr = 0xf05c, 955 .mnd_width = 0, 956 .hid_width = 5, 957 .parent_map = gcc_parent_map_2, 958 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, 959 .clkr.hw.init = &(struct clk_init_data){ 960 .name = "gcc_usb3_prim_phy_aux_clk_src", 961 .parent_names = gcc_parent_names_2, 962 .num_parents = 3, 963 .ops = &clk_rcg2_ops, 964 }, 965 }; 966 967 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { 968 .cmd_rcgr = 0x1005c, 969 .mnd_width = 0, 970 .hid_width = 5, 971 .parent_map = gcc_parent_map_2, 972 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, 973 .clkr.hw.init = &(struct clk_init_data){ 974 .name = "gcc_usb3_sec_phy_aux_clk_src", 975 .parent_names = gcc_parent_names_2, 976 .num_parents = 3, 977 .ops = &clk_rcg2_shared_ops, 978 }, 979 }; 980 981 static struct clk_rcg2 gcc_vs_ctrl_clk_src = { 982 .cmd_rcgr = 0x7a030, 983 .mnd_width = 0, 984 .hid_width = 5, 985 .parent_map = gcc_parent_map_3, 986 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, 987 .clkr.hw.init = &(struct clk_init_data){ 988 .name = "gcc_vs_ctrl_clk_src", 989 .parent_names = gcc_parent_names_3, 990 .num_parents = 3, 991 .ops = &clk_rcg2_ops, 992 }, 993 }; 994 995 static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = { 996 F(19200000, P_BI_TCXO, 1, 0, 0), 997 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 998 F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0), 999 { } 1000 }; 1001 1002 static struct clk_rcg2 gcc_vsensor_clk_src = { 1003 .cmd_rcgr = 0x7a018, 1004 .mnd_width = 0, 1005 .hid_width = 5, 1006 .parent_map = gcc_parent_map_3, 1007 .freq_tbl = ftbl_gcc_vsensor_clk_src, 1008 .clkr.hw.init = &(struct clk_init_data){ 1009 .name = "gcc_vsensor_clk_src", 1010 .parent_names = gcc_parent_names_8, 1011 .num_parents = 3, 1012 .ops = &clk_rcg2_ops, 1013 }, 1014 }; 1015 1016 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { 1017 .halt_reg = 0x90014, 1018 .halt_check = BRANCH_HALT, 1019 .clkr = { 1020 .enable_reg = 0x90014, 1021 .enable_mask = BIT(0), 1022 .hw.init = &(struct clk_init_data){ 1023 .name = "gcc_aggre_noc_pcie_tbu_clk", 1024 .ops = &clk_branch2_ops, 1025 }, 1026 }, 1027 }; 1028 1029 static struct clk_branch gcc_aggre_ufs_card_axi_clk = { 1030 .halt_reg = 0x82028, 1031 .halt_check = BRANCH_HALT, 1032 .hwcg_reg = 0x82028, 1033 .hwcg_bit = 1, 1034 .clkr = { 1035 .enable_reg = 0x82028, 1036 .enable_mask = BIT(0), 1037 .hw.init = &(struct clk_init_data){ 1038 .name = "gcc_aggre_ufs_card_axi_clk", 1039 .parent_names = (const char *[]){ 1040 "gcc_ufs_card_axi_clk_src", 1041 }, 1042 .num_parents = 1, 1043 .flags = CLK_SET_RATE_PARENT, 1044 .ops = &clk_branch2_ops, 1045 }, 1046 }, 1047 }; 1048 1049 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1050 .halt_reg = 0x82024, 1051 .halt_check = BRANCH_HALT, 1052 .hwcg_reg = 0x82024, 1053 .hwcg_bit = 1, 1054 .clkr = { 1055 .enable_reg = 0x82024, 1056 .enable_mask = BIT(0), 1057 .hw.init = &(struct clk_init_data){ 1058 .name = "gcc_aggre_ufs_phy_axi_clk", 1059 .parent_names = (const char *[]){ 1060 "gcc_ufs_phy_axi_clk_src", 1061 }, 1062 .num_parents = 1, 1063 .flags = CLK_SET_RATE_PARENT, 1064 .ops = &clk_branch2_ops, 1065 }, 1066 }, 1067 }; 1068 1069 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1070 .halt_reg = 0x8201c, 1071 .halt_check = BRANCH_HALT, 1072 .clkr = { 1073 .enable_reg = 0x8201c, 1074 .enable_mask = BIT(0), 1075 .hw.init = &(struct clk_init_data){ 1076 .name = "gcc_aggre_usb3_prim_axi_clk", 1077 .parent_names = (const char *[]){ 1078 "gcc_usb30_prim_master_clk_src", 1079 }, 1080 .num_parents = 1, 1081 .flags = CLK_SET_RATE_PARENT, 1082 .ops = &clk_branch2_ops, 1083 }, 1084 }, 1085 }; 1086 1087 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { 1088 .halt_reg = 0x82020, 1089 .halt_check = BRANCH_HALT, 1090 .clkr = { 1091 .enable_reg = 0x82020, 1092 .enable_mask = BIT(0), 1093 .hw.init = &(struct clk_init_data){ 1094 .name = "gcc_aggre_usb3_sec_axi_clk", 1095 .parent_names = (const char *[]){ 1096 "gcc_usb30_sec_master_clk_src", 1097 }, 1098 .num_parents = 1, 1099 .flags = CLK_SET_RATE_PARENT, 1100 .ops = &clk_branch2_ops, 1101 }, 1102 }, 1103 }; 1104 1105 static struct clk_branch gcc_apc_vs_clk = { 1106 .halt_reg = 0x7a050, 1107 .halt_check = BRANCH_HALT, 1108 .clkr = { 1109 .enable_reg = 0x7a050, 1110 .enable_mask = BIT(0), 1111 .hw.init = &(struct clk_init_data){ 1112 .name = "gcc_apc_vs_clk", 1113 .parent_names = (const char *[]){ 1114 "gcc_vsensor_clk_src", 1115 }, 1116 .num_parents = 1, 1117 .flags = CLK_SET_RATE_PARENT, 1118 .ops = &clk_branch2_ops, 1119 }, 1120 }, 1121 }; 1122 1123 static struct clk_branch gcc_boot_rom_ahb_clk = { 1124 .halt_reg = 0x38004, 1125 .halt_check = BRANCH_HALT_VOTED, 1126 .hwcg_reg = 0x38004, 1127 .hwcg_bit = 1, 1128 .clkr = { 1129 .enable_reg = 0x52004, 1130 .enable_mask = BIT(10), 1131 .hw.init = &(struct clk_init_data){ 1132 .name = "gcc_boot_rom_ahb_clk", 1133 .ops = &clk_branch2_ops, 1134 }, 1135 }, 1136 }; 1137 1138 static struct clk_branch gcc_camera_ahb_clk = { 1139 .halt_reg = 0xb008, 1140 .halt_check = BRANCH_HALT, 1141 .hwcg_reg = 0xb008, 1142 .hwcg_bit = 1, 1143 .clkr = { 1144 .enable_reg = 0xb008, 1145 .enable_mask = BIT(0), 1146 .hw.init = &(struct clk_init_data){ 1147 .name = "gcc_camera_ahb_clk", 1148 .flags = CLK_IS_CRITICAL, 1149 .ops = &clk_branch2_ops, 1150 }, 1151 }, 1152 }; 1153 1154 static struct clk_branch gcc_camera_axi_clk = { 1155 .halt_reg = 0xb020, 1156 .halt_check = BRANCH_VOTED, 1157 .clkr = { 1158 .enable_reg = 0xb020, 1159 .enable_mask = BIT(0), 1160 .hw.init = &(struct clk_init_data){ 1161 .name = "gcc_camera_axi_clk", 1162 .ops = &clk_branch2_ops, 1163 }, 1164 }, 1165 }; 1166 1167 static struct clk_branch gcc_camera_xo_clk = { 1168 .halt_reg = 0xb02c, 1169 .halt_check = BRANCH_HALT, 1170 .clkr = { 1171 .enable_reg = 0xb02c, 1172 .enable_mask = BIT(0), 1173 .hw.init = &(struct clk_init_data){ 1174 .name = "gcc_camera_xo_clk", 1175 .flags = CLK_IS_CRITICAL, 1176 .ops = &clk_branch2_ops, 1177 }, 1178 }, 1179 }; 1180 1181 static struct clk_branch gcc_ce1_ahb_clk = { 1182 .halt_reg = 0x4100c, 1183 .halt_check = BRANCH_HALT_VOTED, 1184 .hwcg_reg = 0x4100c, 1185 .hwcg_bit = 1, 1186 .clkr = { 1187 .enable_reg = 0x52004, 1188 .enable_mask = BIT(3), 1189 .hw.init = &(struct clk_init_data){ 1190 .name = "gcc_ce1_ahb_clk", 1191 .ops = &clk_branch2_ops, 1192 }, 1193 }, 1194 }; 1195 1196 static struct clk_branch gcc_ce1_axi_clk = { 1197 .halt_reg = 0x41008, 1198 .halt_check = BRANCH_HALT_VOTED, 1199 .clkr = { 1200 .enable_reg = 0x52004, 1201 .enable_mask = BIT(4), 1202 .hw.init = &(struct clk_init_data){ 1203 .name = "gcc_ce1_axi_clk", 1204 .ops = &clk_branch2_ops, 1205 }, 1206 }, 1207 }; 1208 1209 static struct clk_branch gcc_ce1_clk = { 1210 .halt_reg = 0x41004, 1211 .halt_check = BRANCH_HALT_VOTED, 1212 .clkr = { 1213 .enable_reg = 0x52004, 1214 .enable_mask = BIT(5), 1215 .hw.init = &(struct clk_init_data){ 1216 .name = "gcc_ce1_clk", 1217 .ops = &clk_branch2_ops, 1218 }, 1219 }, 1220 }; 1221 1222 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1223 .halt_reg = 0x502c, 1224 .halt_check = BRANCH_HALT, 1225 .clkr = { 1226 .enable_reg = 0x502c, 1227 .enable_mask = BIT(0), 1228 .hw.init = &(struct clk_init_data){ 1229 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1230 .parent_names = (const char *[]){ 1231 "gcc_usb30_prim_master_clk_src", 1232 }, 1233 .num_parents = 1, 1234 .flags = CLK_SET_RATE_PARENT, 1235 .ops = &clk_branch2_ops, 1236 }, 1237 }, 1238 }; 1239 1240 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { 1241 .halt_reg = 0x5030, 1242 .halt_check = BRANCH_HALT, 1243 .clkr = { 1244 .enable_reg = 0x5030, 1245 .enable_mask = BIT(0), 1246 .hw.init = &(struct clk_init_data){ 1247 .name = "gcc_cfg_noc_usb3_sec_axi_clk", 1248 .parent_names = (const char *[]){ 1249 "gcc_usb30_sec_master_clk_src", 1250 }, 1251 .num_parents = 1, 1252 .flags = CLK_SET_RATE_PARENT, 1253 .ops = &clk_branch2_ops, 1254 }, 1255 }, 1256 }; 1257 1258 static struct clk_branch gcc_cpuss_ahb_clk = { 1259 .halt_reg = 0x48000, 1260 .halt_check = BRANCH_HALT_VOTED, 1261 .clkr = { 1262 .enable_reg = 0x52004, 1263 .enable_mask = BIT(21), 1264 .hw.init = &(struct clk_init_data){ 1265 .name = "gcc_cpuss_ahb_clk", 1266 .parent_names = (const char *[]){ 1267 "gcc_cpuss_ahb_clk_src", 1268 }, 1269 .num_parents = 1, 1270 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1271 .ops = &clk_branch2_ops, 1272 }, 1273 }, 1274 }; 1275 1276 static struct clk_branch gcc_cpuss_rbcpr_clk = { 1277 .halt_reg = 0x48008, 1278 .halt_check = BRANCH_HALT, 1279 .clkr = { 1280 .enable_reg = 0x48008, 1281 .enable_mask = BIT(0), 1282 .hw.init = &(struct clk_init_data){ 1283 .name = "gcc_cpuss_rbcpr_clk", 1284 .parent_names = (const char *[]){ 1285 "gcc_cpuss_rbcpr_clk_src", 1286 }, 1287 .num_parents = 1, 1288 .flags = CLK_SET_RATE_PARENT, 1289 .ops = &clk_branch2_ops, 1290 }, 1291 }, 1292 }; 1293 1294 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1295 .halt_reg = 0x44038, 1296 .halt_check = BRANCH_VOTED, 1297 .clkr = { 1298 .enable_reg = 0x44038, 1299 .enable_mask = BIT(0), 1300 .hw.init = &(struct clk_init_data){ 1301 .name = "gcc_ddrss_gpu_axi_clk", 1302 .ops = &clk_branch2_ops, 1303 }, 1304 }, 1305 }; 1306 1307 static struct clk_branch gcc_disp_ahb_clk = { 1308 .halt_reg = 0xb00c, 1309 .halt_check = BRANCH_HALT, 1310 .hwcg_reg = 0xb00c, 1311 .hwcg_bit = 1, 1312 .clkr = { 1313 .enable_reg = 0xb00c, 1314 .enable_mask = BIT(0), 1315 .hw.init = &(struct clk_init_data){ 1316 .name = "gcc_disp_ahb_clk", 1317 .flags = CLK_IS_CRITICAL, 1318 .ops = &clk_branch2_ops, 1319 }, 1320 }, 1321 }; 1322 1323 static struct clk_branch gcc_disp_axi_clk = { 1324 .halt_reg = 0xb024, 1325 .halt_check = BRANCH_VOTED, 1326 .clkr = { 1327 .enable_reg = 0xb024, 1328 .enable_mask = BIT(0), 1329 .hw.init = &(struct clk_init_data){ 1330 .name = "gcc_disp_axi_clk", 1331 .ops = &clk_branch2_ops, 1332 }, 1333 }, 1334 }; 1335 1336 static struct clk_branch gcc_disp_gpll0_clk_src = { 1337 .halt_check = BRANCH_HALT_DELAY, 1338 .clkr = { 1339 .enable_reg = 0x52004, 1340 .enable_mask = BIT(18), 1341 .hw.init = &(struct clk_init_data){ 1342 .name = "gcc_disp_gpll0_clk_src", 1343 .parent_names = (const char *[]){ 1344 "gpll0", 1345 }, 1346 .num_parents = 1, 1347 .ops = &clk_branch2_ops, 1348 }, 1349 }, 1350 }; 1351 1352 static struct clk_branch gcc_disp_gpll0_div_clk_src = { 1353 .halt_check = BRANCH_HALT_DELAY, 1354 .clkr = { 1355 .enable_reg = 0x52004, 1356 .enable_mask = BIT(19), 1357 .hw.init = &(struct clk_init_data){ 1358 .name = "gcc_disp_gpll0_div_clk_src", 1359 .parent_names = (const char *[]){ 1360 "gpll0_out_even", 1361 }, 1362 .num_parents = 1, 1363 .ops = &clk_branch2_ops, 1364 }, 1365 }, 1366 }; 1367 1368 static struct clk_branch gcc_disp_xo_clk = { 1369 .halt_reg = 0xb030, 1370 .halt_check = BRANCH_HALT, 1371 .clkr = { 1372 .enable_reg = 0xb030, 1373 .enable_mask = BIT(0), 1374 .hw.init = &(struct clk_init_data){ 1375 .name = "gcc_disp_xo_clk", 1376 .flags = CLK_IS_CRITICAL, 1377 .ops = &clk_branch2_ops, 1378 }, 1379 }, 1380 }; 1381 1382 static struct clk_branch gcc_gp1_clk = { 1383 .halt_reg = 0x64000, 1384 .halt_check = BRANCH_HALT, 1385 .clkr = { 1386 .enable_reg = 0x64000, 1387 .enable_mask = BIT(0), 1388 .hw.init = &(struct clk_init_data){ 1389 .name = "gcc_gp1_clk", 1390 .parent_names = (const char *[]){ 1391 "gcc_gp1_clk_src", 1392 }, 1393 .num_parents = 1, 1394 .flags = CLK_SET_RATE_PARENT, 1395 .ops = &clk_branch2_ops, 1396 }, 1397 }, 1398 }; 1399 1400 static struct clk_branch gcc_gp2_clk = { 1401 .halt_reg = 0x65000, 1402 .halt_check = BRANCH_HALT, 1403 .clkr = { 1404 .enable_reg = 0x65000, 1405 .enable_mask = BIT(0), 1406 .hw.init = &(struct clk_init_data){ 1407 .name = "gcc_gp2_clk", 1408 .parent_names = (const char *[]){ 1409 "gcc_gp2_clk_src", 1410 }, 1411 .num_parents = 1, 1412 .flags = CLK_SET_RATE_PARENT, 1413 .ops = &clk_branch2_ops, 1414 }, 1415 }, 1416 }; 1417 1418 static struct clk_branch gcc_gp3_clk = { 1419 .halt_reg = 0x66000, 1420 .halt_check = BRANCH_HALT, 1421 .clkr = { 1422 .enable_reg = 0x66000, 1423 .enable_mask = BIT(0), 1424 .hw.init = &(struct clk_init_data){ 1425 .name = "gcc_gp3_clk", 1426 .parent_names = (const char *[]){ 1427 "gcc_gp3_clk_src", 1428 }, 1429 .num_parents = 1, 1430 .flags = CLK_SET_RATE_PARENT, 1431 .ops = &clk_branch2_ops, 1432 }, 1433 }, 1434 }; 1435 1436 static struct clk_branch gcc_gpu_cfg_ahb_clk = { 1437 .halt_reg = 0x71004, 1438 .halt_check = BRANCH_HALT, 1439 .hwcg_reg = 0x71004, 1440 .hwcg_bit = 1, 1441 .clkr = { 1442 .enable_reg = 0x71004, 1443 .enable_mask = BIT(0), 1444 .hw.init = &(struct clk_init_data){ 1445 .name = "gcc_gpu_cfg_ahb_clk", 1446 .flags = CLK_IS_CRITICAL, 1447 .ops = &clk_branch2_ops, 1448 }, 1449 }, 1450 }; 1451 1452 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1453 .halt_check = BRANCH_HALT_DELAY, 1454 .clkr = { 1455 .enable_reg = 0x52004, 1456 .enable_mask = BIT(15), 1457 .hw.init = &(struct clk_init_data){ 1458 .name = "gcc_gpu_gpll0_clk_src", 1459 .parent_names = (const char *[]){ 1460 "gpll0", 1461 }, 1462 .num_parents = 1, 1463 .ops = &clk_branch2_ops, 1464 }, 1465 }, 1466 }; 1467 1468 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1469 .halt_check = BRANCH_HALT_DELAY, 1470 .clkr = { 1471 .enable_reg = 0x52004, 1472 .enable_mask = BIT(16), 1473 .hw.init = &(struct clk_init_data){ 1474 .name = "gcc_gpu_gpll0_div_clk_src", 1475 .parent_names = (const char *[]){ 1476 "gpll0_out_even", 1477 }, 1478 .num_parents = 1, 1479 .ops = &clk_branch2_ops, 1480 }, 1481 }, 1482 }; 1483 1484 static struct clk_branch gcc_gpu_iref_clk = { 1485 .halt_reg = 0x8c010, 1486 .halt_check = BRANCH_HALT, 1487 .clkr = { 1488 .enable_reg = 0x8c010, 1489 .enable_mask = BIT(0), 1490 .hw.init = &(struct clk_init_data){ 1491 .name = "gcc_gpu_iref_clk", 1492 .ops = &clk_branch2_ops, 1493 }, 1494 }, 1495 }; 1496 1497 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1498 .halt_reg = 0x7100c, 1499 .halt_check = BRANCH_VOTED, 1500 .clkr = { 1501 .enable_reg = 0x7100c, 1502 .enable_mask = BIT(0), 1503 .hw.init = &(struct clk_init_data){ 1504 .name = "gcc_gpu_memnoc_gfx_clk", 1505 .ops = &clk_branch2_ops, 1506 }, 1507 }, 1508 }; 1509 1510 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1511 .halt_reg = 0x71018, 1512 .halt_check = BRANCH_HALT, 1513 .clkr = { 1514 .enable_reg = 0x71018, 1515 .enable_mask = BIT(0), 1516 .hw.init = &(struct clk_init_data){ 1517 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1518 .ops = &clk_branch2_ops, 1519 }, 1520 }, 1521 }; 1522 1523 static struct clk_branch gcc_gpu_vs_clk = { 1524 .halt_reg = 0x7a04c, 1525 .halt_check = BRANCH_HALT, 1526 .clkr = { 1527 .enable_reg = 0x7a04c, 1528 .enable_mask = BIT(0), 1529 .hw.init = &(struct clk_init_data){ 1530 .name = "gcc_gpu_vs_clk", 1531 .parent_names = (const char *[]){ 1532 "gcc_vsensor_clk_src", 1533 }, 1534 .num_parents = 1, 1535 .flags = CLK_SET_RATE_PARENT, 1536 .ops = &clk_branch2_ops, 1537 }, 1538 }, 1539 }; 1540 1541 static struct clk_branch gcc_mss_axis2_clk = { 1542 .halt_reg = 0x8a008, 1543 .halt_check = BRANCH_HALT, 1544 .clkr = { 1545 .enable_reg = 0x8a008, 1546 .enable_mask = BIT(0), 1547 .hw.init = &(struct clk_init_data){ 1548 .name = "gcc_mss_axis2_clk", 1549 .ops = &clk_branch2_ops, 1550 }, 1551 }, 1552 }; 1553 1554 static struct clk_branch gcc_mss_cfg_ahb_clk = { 1555 .halt_reg = 0x8a000, 1556 .halt_check = BRANCH_HALT, 1557 .hwcg_reg = 0x8a000, 1558 .hwcg_bit = 1, 1559 .clkr = { 1560 .enable_reg = 0x8a000, 1561 .enable_mask = BIT(0), 1562 .hw.init = &(struct clk_init_data){ 1563 .name = "gcc_mss_cfg_ahb_clk", 1564 .ops = &clk_branch2_ops, 1565 }, 1566 }, 1567 }; 1568 1569 static struct clk_branch gcc_mss_gpll0_div_clk_src = { 1570 .halt_check = BRANCH_HALT_DELAY, 1571 .clkr = { 1572 .enable_reg = 0x52004, 1573 .enable_mask = BIT(17), 1574 .hw.init = &(struct clk_init_data){ 1575 .name = "gcc_mss_gpll0_div_clk_src", 1576 .ops = &clk_branch2_ops, 1577 }, 1578 }, 1579 }; 1580 1581 static struct clk_branch gcc_mss_mfab_axis_clk = { 1582 .halt_reg = 0x8a004, 1583 .halt_check = BRANCH_VOTED, 1584 .hwcg_reg = 0x8a004, 1585 .hwcg_bit = 1, 1586 .clkr = { 1587 .enable_reg = 0x8a004, 1588 .enable_mask = BIT(0), 1589 .hw.init = &(struct clk_init_data){ 1590 .name = "gcc_mss_mfab_axis_clk", 1591 .ops = &clk_branch2_ops, 1592 }, 1593 }, 1594 }; 1595 1596 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = { 1597 .halt_reg = 0x8a154, 1598 .halt_check = BRANCH_VOTED, 1599 .clkr = { 1600 .enable_reg = 0x8a154, 1601 .enable_mask = BIT(0), 1602 .hw.init = &(struct clk_init_data){ 1603 .name = "gcc_mss_q6_memnoc_axi_clk", 1604 .ops = &clk_branch2_ops, 1605 }, 1606 }, 1607 }; 1608 1609 static struct clk_branch gcc_mss_snoc_axi_clk = { 1610 .halt_reg = 0x8a150, 1611 .halt_check = BRANCH_HALT, 1612 .clkr = { 1613 .enable_reg = 0x8a150, 1614 .enable_mask = BIT(0), 1615 .hw.init = &(struct clk_init_data){ 1616 .name = "gcc_mss_snoc_axi_clk", 1617 .ops = &clk_branch2_ops, 1618 }, 1619 }, 1620 }; 1621 1622 static struct clk_branch gcc_mss_vs_clk = { 1623 .halt_reg = 0x7a048, 1624 .halt_check = BRANCH_HALT, 1625 .clkr = { 1626 .enable_reg = 0x7a048, 1627 .enable_mask = BIT(0), 1628 .hw.init = &(struct clk_init_data){ 1629 .name = "gcc_mss_vs_clk", 1630 .parent_names = (const char *[]){ 1631 "gcc_vsensor_clk_src", 1632 }, 1633 .num_parents = 1, 1634 .flags = CLK_SET_RATE_PARENT, 1635 .ops = &clk_branch2_ops, 1636 }, 1637 }, 1638 }; 1639 1640 static struct clk_branch gcc_pcie_0_aux_clk = { 1641 .halt_reg = 0x6b01c, 1642 .halt_check = BRANCH_HALT_VOTED, 1643 .clkr = { 1644 .enable_reg = 0x5200c, 1645 .enable_mask = BIT(3), 1646 .hw.init = &(struct clk_init_data){ 1647 .name = "gcc_pcie_0_aux_clk", 1648 .parent_names = (const char *[]){ 1649 "gcc_pcie_0_aux_clk_src", 1650 }, 1651 .num_parents = 1, 1652 .flags = CLK_SET_RATE_PARENT, 1653 .ops = &clk_branch2_ops, 1654 }, 1655 }, 1656 }; 1657 1658 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1659 .halt_reg = 0x6b018, 1660 .halt_check = BRANCH_HALT_VOTED, 1661 .hwcg_reg = 0x6b018, 1662 .hwcg_bit = 1, 1663 .clkr = { 1664 .enable_reg = 0x5200c, 1665 .enable_mask = BIT(2), 1666 .hw.init = &(struct clk_init_data){ 1667 .name = "gcc_pcie_0_cfg_ahb_clk", 1668 .ops = &clk_branch2_ops, 1669 }, 1670 }, 1671 }; 1672 1673 static struct clk_branch gcc_pcie_0_clkref_clk = { 1674 .halt_reg = 0x8c00c, 1675 .halt_check = BRANCH_HALT, 1676 .clkr = { 1677 .enable_reg = 0x8c00c, 1678 .enable_mask = BIT(0), 1679 .hw.init = &(struct clk_init_data){ 1680 .name = "gcc_pcie_0_clkref_clk", 1681 .ops = &clk_branch2_ops, 1682 }, 1683 }, 1684 }; 1685 1686 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1687 .halt_reg = 0x6b014, 1688 .halt_check = BRANCH_HALT_VOTED, 1689 .clkr = { 1690 .enable_reg = 0x5200c, 1691 .enable_mask = BIT(1), 1692 .hw.init = &(struct clk_init_data){ 1693 .name = "gcc_pcie_0_mstr_axi_clk", 1694 .ops = &clk_branch2_ops, 1695 }, 1696 }, 1697 }; 1698 1699 static struct clk_branch gcc_pcie_0_pipe_clk = { 1700 .halt_check = BRANCH_HALT_SKIP, 1701 .clkr = { 1702 .enable_reg = 0x5200c, 1703 .enable_mask = BIT(4), 1704 .hw.init = &(struct clk_init_data){ 1705 .name = "gcc_pcie_0_pipe_clk", 1706 .ops = &clk_branch2_ops, 1707 }, 1708 }, 1709 }; 1710 1711 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1712 .halt_reg = 0x6b010, 1713 .halt_check = BRANCH_HALT_VOTED, 1714 .hwcg_reg = 0x6b010, 1715 .hwcg_bit = 1, 1716 .clkr = { 1717 .enable_reg = 0x5200c, 1718 .enable_mask = BIT(0), 1719 .hw.init = &(struct clk_init_data){ 1720 .name = "gcc_pcie_0_slv_axi_clk", 1721 .ops = &clk_branch2_ops, 1722 }, 1723 }, 1724 }; 1725 1726 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1727 .halt_reg = 0x6b00c, 1728 .halt_check = BRANCH_HALT_VOTED, 1729 .clkr = { 1730 .enable_reg = 0x5200c, 1731 .enable_mask = BIT(5), 1732 .hw.init = &(struct clk_init_data){ 1733 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1734 .ops = &clk_branch2_ops, 1735 }, 1736 }, 1737 }; 1738 1739 static struct clk_branch gcc_pcie_1_aux_clk = { 1740 .halt_reg = 0x8d01c, 1741 .halt_check = BRANCH_HALT_VOTED, 1742 .clkr = { 1743 .enable_reg = 0x52004, 1744 .enable_mask = BIT(29), 1745 .hw.init = &(struct clk_init_data){ 1746 .name = "gcc_pcie_1_aux_clk", 1747 .parent_names = (const char *[]){ 1748 "gcc_pcie_1_aux_clk_src", 1749 }, 1750 .num_parents = 1, 1751 .flags = CLK_SET_RATE_PARENT, 1752 .ops = &clk_branch2_ops, 1753 }, 1754 }, 1755 }; 1756 1757 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1758 .halt_reg = 0x8d018, 1759 .halt_check = BRANCH_HALT_VOTED, 1760 .hwcg_reg = 0x8d018, 1761 .hwcg_bit = 1, 1762 .clkr = { 1763 .enable_reg = 0x52004, 1764 .enable_mask = BIT(28), 1765 .hw.init = &(struct clk_init_data){ 1766 .name = "gcc_pcie_1_cfg_ahb_clk", 1767 .ops = &clk_branch2_ops, 1768 }, 1769 }, 1770 }; 1771 1772 static struct clk_branch gcc_pcie_1_clkref_clk = { 1773 .halt_reg = 0x8c02c, 1774 .halt_check = BRANCH_HALT, 1775 .clkr = { 1776 .enable_reg = 0x8c02c, 1777 .enable_mask = BIT(0), 1778 .hw.init = &(struct clk_init_data){ 1779 .name = "gcc_pcie_1_clkref_clk", 1780 .ops = &clk_branch2_ops, 1781 }, 1782 }, 1783 }; 1784 1785 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1786 .halt_reg = 0x8d014, 1787 .halt_check = BRANCH_HALT_VOTED, 1788 .clkr = { 1789 .enable_reg = 0x52004, 1790 .enable_mask = BIT(27), 1791 .hw.init = &(struct clk_init_data){ 1792 .name = "gcc_pcie_1_mstr_axi_clk", 1793 .ops = &clk_branch2_ops, 1794 }, 1795 }, 1796 }; 1797 1798 static struct clk_branch gcc_pcie_1_pipe_clk = { 1799 .halt_check = BRANCH_HALT_SKIP, 1800 .clkr = { 1801 .enable_reg = 0x52004, 1802 .enable_mask = BIT(30), 1803 .hw.init = &(struct clk_init_data){ 1804 .name = "gcc_pcie_1_pipe_clk", 1805 .ops = &clk_branch2_ops, 1806 }, 1807 }, 1808 }; 1809 1810 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1811 .halt_reg = 0x8d010, 1812 .halt_check = BRANCH_HALT_VOTED, 1813 .hwcg_reg = 0x8d010, 1814 .hwcg_bit = 1, 1815 .clkr = { 1816 .enable_reg = 0x52004, 1817 .enable_mask = BIT(26), 1818 .hw.init = &(struct clk_init_data){ 1819 .name = "gcc_pcie_1_slv_axi_clk", 1820 .ops = &clk_branch2_ops, 1821 }, 1822 }, 1823 }; 1824 1825 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 1826 .halt_reg = 0x8d00c, 1827 .halt_check = BRANCH_HALT_VOTED, 1828 .clkr = { 1829 .enable_reg = 0x52004, 1830 .enable_mask = BIT(25), 1831 .hw.init = &(struct clk_init_data){ 1832 .name = "gcc_pcie_1_slv_q2a_axi_clk", 1833 .ops = &clk_branch2_ops, 1834 }, 1835 }, 1836 }; 1837 1838 static struct clk_branch gcc_pcie_phy_aux_clk = { 1839 .halt_reg = 0x6f004, 1840 .halt_check = BRANCH_HALT, 1841 .clkr = { 1842 .enable_reg = 0x6f004, 1843 .enable_mask = BIT(0), 1844 .hw.init = &(struct clk_init_data){ 1845 .name = "gcc_pcie_phy_aux_clk", 1846 .parent_names = (const char *[]){ 1847 "gcc_pcie_0_aux_clk_src", 1848 }, 1849 .num_parents = 1, 1850 .flags = CLK_SET_RATE_PARENT, 1851 .ops = &clk_branch2_ops, 1852 }, 1853 }, 1854 }; 1855 1856 static struct clk_branch gcc_pcie_phy_refgen_clk = { 1857 .halt_reg = 0x6f02c, 1858 .halt_check = BRANCH_HALT, 1859 .clkr = { 1860 .enable_reg = 0x6f02c, 1861 .enable_mask = BIT(0), 1862 .hw.init = &(struct clk_init_data){ 1863 .name = "gcc_pcie_phy_refgen_clk", 1864 .parent_names = (const char *[]){ 1865 "gcc_pcie_phy_refgen_clk_src", 1866 }, 1867 .num_parents = 1, 1868 .flags = CLK_SET_RATE_PARENT, 1869 .ops = &clk_branch2_ops, 1870 }, 1871 }, 1872 }; 1873 1874 static struct clk_branch gcc_pdm2_clk = { 1875 .halt_reg = 0x3300c, 1876 .halt_check = BRANCH_HALT, 1877 .clkr = { 1878 .enable_reg = 0x3300c, 1879 .enable_mask = BIT(0), 1880 .hw.init = &(struct clk_init_data){ 1881 .name = "gcc_pdm2_clk", 1882 .parent_names = (const char *[]){ 1883 "gcc_pdm2_clk_src", 1884 }, 1885 .num_parents = 1, 1886 .flags = CLK_SET_RATE_PARENT, 1887 .ops = &clk_branch2_ops, 1888 }, 1889 }, 1890 }; 1891 1892 static struct clk_branch gcc_pdm_ahb_clk = { 1893 .halt_reg = 0x33004, 1894 .halt_check = BRANCH_HALT, 1895 .hwcg_reg = 0x33004, 1896 .hwcg_bit = 1, 1897 .clkr = { 1898 .enable_reg = 0x33004, 1899 .enable_mask = BIT(0), 1900 .hw.init = &(struct clk_init_data){ 1901 .name = "gcc_pdm_ahb_clk", 1902 .ops = &clk_branch2_ops, 1903 }, 1904 }, 1905 }; 1906 1907 static struct clk_branch gcc_pdm_xo4_clk = { 1908 .halt_reg = 0x33008, 1909 .halt_check = BRANCH_HALT, 1910 .clkr = { 1911 .enable_reg = 0x33008, 1912 .enable_mask = BIT(0), 1913 .hw.init = &(struct clk_init_data){ 1914 .name = "gcc_pdm_xo4_clk", 1915 .ops = &clk_branch2_ops, 1916 }, 1917 }, 1918 }; 1919 1920 static struct clk_branch gcc_prng_ahb_clk = { 1921 .halt_reg = 0x34004, 1922 .halt_check = BRANCH_HALT_VOTED, 1923 .hwcg_reg = 0x34004, 1924 .hwcg_bit = 1, 1925 .clkr = { 1926 .enable_reg = 0x52004, 1927 .enable_mask = BIT(13), 1928 .hw.init = &(struct clk_init_data){ 1929 .name = "gcc_prng_ahb_clk", 1930 .ops = &clk_branch2_ops, 1931 }, 1932 }, 1933 }; 1934 1935 static struct clk_branch gcc_qmip_camera_ahb_clk = { 1936 .halt_reg = 0xb014, 1937 .halt_check = BRANCH_HALT, 1938 .hwcg_reg = 0xb014, 1939 .hwcg_bit = 1, 1940 .clkr = { 1941 .enable_reg = 0xb014, 1942 .enable_mask = BIT(0), 1943 .hw.init = &(struct clk_init_data){ 1944 .name = "gcc_qmip_camera_ahb_clk", 1945 .ops = &clk_branch2_ops, 1946 }, 1947 }, 1948 }; 1949 1950 static struct clk_branch gcc_qmip_disp_ahb_clk = { 1951 .halt_reg = 0xb018, 1952 .halt_check = BRANCH_HALT, 1953 .hwcg_reg = 0xb018, 1954 .hwcg_bit = 1, 1955 .clkr = { 1956 .enable_reg = 0xb018, 1957 .enable_mask = BIT(0), 1958 .hw.init = &(struct clk_init_data){ 1959 .name = "gcc_qmip_disp_ahb_clk", 1960 .ops = &clk_branch2_ops, 1961 }, 1962 }, 1963 }; 1964 1965 static struct clk_branch gcc_qmip_video_ahb_clk = { 1966 .halt_reg = 0xb010, 1967 .halt_check = BRANCH_HALT, 1968 .hwcg_reg = 0xb010, 1969 .hwcg_bit = 1, 1970 .clkr = { 1971 .enable_reg = 0xb010, 1972 .enable_mask = BIT(0), 1973 .hw.init = &(struct clk_init_data){ 1974 .name = "gcc_qmip_video_ahb_clk", 1975 .ops = &clk_branch2_ops, 1976 }, 1977 }, 1978 }; 1979 1980 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { 1981 .halt_reg = 0x4b000, 1982 .halt_check = BRANCH_HALT, 1983 .clkr = { 1984 .enable_reg = 0x4b000, 1985 .enable_mask = BIT(0), 1986 .hw.init = &(struct clk_init_data){ 1987 .name = "gcc_qspi_cnoc_periph_ahb_clk", 1988 .ops = &clk_branch2_ops, 1989 }, 1990 }, 1991 }; 1992 1993 static struct clk_branch gcc_qspi_core_clk = { 1994 .halt_reg = 0x4b004, 1995 .halt_check = BRANCH_HALT, 1996 .clkr = { 1997 .enable_reg = 0x4b004, 1998 .enable_mask = BIT(0), 1999 .hw.init = &(struct clk_init_data){ 2000 .name = "gcc_qspi_core_clk", 2001 .parent_names = (const char *[]){ 2002 "gcc_qspi_core_clk_src", 2003 }, 2004 .num_parents = 1, 2005 .flags = CLK_SET_RATE_PARENT, 2006 .ops = &clk_branch2_ops, 2007 }, 2008 }, 2009 }; 2010 2011 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2012 .halt_reg = 0x17030, 2013 .halt_check = BRANCH_HALT_VOTED, 2014 .clkr = { 2015 .enable_reg = 0x5200c, 2016 .enable_mask = BIT(10), 2017 .hw.init = &(struct clk_init_data){ 2018 .name = "gcc_qupv3_wrap0_s0_clk", 2019 .parent_names = (const char *[]){ 2020 "gcc_qupv3_wrap0_s0_clk_src", 2021 }, 2022 .num_parents = 1, 2023 .flags = CLK_SET_RATE_PARENT, 2024 .ops = &clk_branch2_ops, 2025 }, 2026 }, 2027 }; 2028 2029 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2030 .halt_reg = 0x17160, 2031 .halt_check = BRANCH_HALT_VOTED, 2032 .clkr = { 2033 .enable_reg = 0x5200c, 2034 .enable_mask = BIT(11), 2035 .hw.init = &(struct clk_init_data){ 2036 .name = "gcc_qupv3_wrap0_s1_clk", 2037 .parent_names = (const char *[]){ 2038 "gcc_qupv3_wrap0_s1_clk_src", 2039 }, 2040 .num_parents = 1, 2041 .flags = CLK_SET_RATE_PARENT, 2042 .ops = &clk_branch2_ops, 2043 }, 2044 }, 2045 }; 2046 2047 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2048 .halt_reg = 0x17290, 2049 .halt_check = BRANCH_HALT_VOTED, 2050 .clkr = { 2051 .enable_reg = 0x5200c, 2052 .enable_mask = BIT(12), 2053 .hw.init = &(struct clk_init_data){ 2054 .name = "gcc_qupv3_wrap0_s2_clk", 2055 .parent_names = (const char *[]){ 2056 "gcc_qupv3_wrap0_s2_clk_src", 2057 }, 2058 .num_parents = 1, 2059 .flags = CLK_SET_RATE_PARENT, 2060 .ops = &clk_branch2_ops, 2061 }, 2062 }, 2063 }; 2064 2065 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2066 .halt_reg = 0x173c0, 2067 .halt_check = BRANCH_HALT_VOTED, 2068 .clkr = { 2069 .enable_reg = 0x5200c, 2070 .enable_mask = BIT(13), 2071 .hw.init = &(struct clk_init_data){ 2072 .name = "gcc_qupv3_wrap0_s3_clk", 2073 .parent_names = (const char *[]){ 2074 "gcc_qupv3_wrap0_s3_clk_src", 2075 }, 2076 .num_parents = 1, 2077 .flags = CLK_SET_RATE_PARENT, 2078 .ops = &clk_branch2_ops, 2079 }, 2080 }, 2081 }; 2082 2083 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2084 .halt_reg = 0x174f0, 2085 .halt_check = BRANCH_HALT_VOTED, 2086 .clkr = { 2087 .enable_reg = 0x5200c, 2088 .enable_mask = BIT(14), 2089 .hw.init = &(struct clk_init_data){ 2090 .name = "gcc_qupv3_wrap0_s4_clk", 2091 .parent_names = (const char *[]){ 2092 "gcc_qupv3_wrap0_s4_clk_src", 2093 }, 2094 .num_parents = 1, 2095 .flags = CLK_SET_RATE_PARENT, 2096 .ops = &clk_branch2_ops, 2097 }, 2098 }, 2099 }; 2100 2101 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2102 .halt_reg = 0x17620, 2103 .halt_check = BRANCH_HALT_VOTED, 2104 .clkr = { 2105 .enable_reg = 0x5200c, 2106 .enable_mask = BIT(15), 2107 .hw.init = &(struct clk_init_data){ 2108 .name = "gcc_qupv3_wrap0_s5_clk", 2109 .parent_names = (const char *[]){ 2110 "gcc_qupv3_wrap0_s5_clk_src", 2111 }, 2112 .num_parents = 1, 2113 .flags = CLK_SET_RATE_PARENT, 2114 .ops = &clk_branch2_ops, 2115 }, 2116 }, 2117 }; 2118 2119 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 2120 .halt_reg = 0x17750, 2121 .halt_check = BRANCH_HALT_VOTED, 2122 .clkr = { 2123 .enable_reg = 0x5200c, 2124 .enable_mask = BIT(16), 2125 .hw.init = &(struct clk_init_data){ 2126 .name = "gcc_qupv3_wrap0_s6_clk", 2127 .parent_names = (const char *[]){ 2128 "gcc_qupv3_wrap0_s6_clk_src", 2129 }, 2130 .num_parents = 1, 2131 .flags = CLK_SET_RATE_PARENT, 2132 .ops = &clk_branch2_ops, 2133 }, 2134 }, 2135 }; 2136 2137 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 2138 .halt_reg = 0x17880, 2139 .halt_check = BRANCH_HALT_VOTED, 2140 .clkr = { 2141 .enable_reg = 0x5200c, 2142 .enable_mask = BIT(17), 2143 .hw.init = &(struct clk_init_data){ 2144 .name = "gcc_qupv3_wrap0_s7_clk", 2145 .parent_names = (const char *[]){ 2146 "gcc_qupv3_wrap0_s7_clk_src", 2147 }, 2148 .num_parents = 1, 2149 .flags = CLK_SET_RATE_PARENT, 2150 .ops = &clk_branch2_ops, 2151 }, 2152 }, 2153 }; 2154 2155 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2156 .halt_reg = 0x18014, 2157 .halt_check = BRANCH_HALT_VOTED, 2158 .clkr = { 2159 .enable_reg = 0x5200c, 2160 .enable_mask = BIT(22), 2161 .hw.init = &(struct clk_init_data){ 2162 .name = "gcc_qupv3_wrap1_s0_clk", 2163 .parent_names = (const char *[]){ 2164 "gcc_qupv3_wrap1_s0_clk_src", 2165 }, 2166 .num_parents = 1, 2167 .flags = CLK_SET_RATE_PARENT, 2168 .ops = &clk_branch2_ops, 2169 }, 2170 }, 2171 }; 2172 2173 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2174 .halt_reg = 0x18144, 2175 .halt_check = BRANCH_HALT_VOTED, 2176 .clkr = { 2177 .enable_reg = 0x5200c, 2178 .enable_mask = BIT(23), 2179 .hw.init = &(struct clk_init_data){ 2180 .name = "gcc_qupv3_wrap1_s1_clk", 2181 .parent_names = (const char *[]){ 2182 "gcc_qupv3_wrap1_s1_clk_src", 2183 }, 2184 .num_parents = 1, 2185 .flags = CLK_SET_RATE_PARENT, 2186 .ops = &clk_branch2_ops, 2187 }, 2188 }, 2189 }; 2190 2191 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2192 .halt_reg = 0x18274, 2193 .halt_check = BRANCH_HALT_VOTED, 2194 .clkr = { 2195 .enable_reg = 0x5200c, 2196 .enable_mask = BIT(24), 2197 .hw.init = &(struct clk_init_data){ 2198 .name = "gcc_qupv3_wrap1_s2_clk", 2199 .parent_names = (const char *[]){ 2200 "gcc_qupv3_wrap1_s2_clk_src", 2201 }, 2202 .num_parents = 1, 2203 .flags = CLK_SET_RATE_PARENT, 2204 .ops = &clk_branch2_ops, 2205 }, 2206 }, 2207 }; 2208 2209 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2210 .halt_reg = 0x183a4, 2211 .halt_check = BRANCH_HALT_VOTED, 2212 .clkr = { 2213 .enable_reg = 0x5200c, 2214 .enable_mask = BIT(25), 2215 .hw.init = &(struct clk_init_data){ 2216 .name = "gcc_qupv3_wrap1_s3_clk", 2217 .parent_names = (const char *[]){ 2218 "gcc_qupv3_wrap1_s3_clk_src", 2219 }, 2220 .num_parents = 1, 2221 .flags = CLK_SET_RATE_PARENT, 2222 .ops = &clk_branch2_ops, 2223 }, 2224 }, 2225 }; 2226 2227 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2228 .halt_reg = 0x184d4, 2229 .halt_check = BRANCH_HALT_VOTED, 2230 .clkr = { 2231 .enable_reg = 0x5200c, 2232 .enable_mask = BIT(26), 2233 .hw.init = &(struct clk_init_data){ 2234 .name = "gcc_qupv3_wrap1_s4_clk", 2235 .parent_names = (const char *[]){ 2236 "gcc_qupv3_wrap1_s4_clk_src", 2237 }, 2238 .num_parents = 1, 2239 .flags = CLK_SET_RATE_PARENT, 2240 .ops = &clk_branch2_ops, 2241 }, 2242 }, 2243 }; 2244 2245 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2246 .halt_reg = 0x18604, 2247 .halt_check = BRANCH_HALT_VOTED, 2248 .clkr = { 2249 .enable_reg = 0x5200c, 2250 .enable_mask = BIT(27), 2251 .hw.init = &(struct clk_init_data){ 2252 .name = "gcc_qupv3_wrap1_s5_clk", 2253 .parent_names = (const char *[]){ 2254 "gcc_qupv3_wrap1_s5_clk_src", 2255 }, 2256 .num_parents = 1, 2257 .flags = CLK_SET_RATE_PARENT, 2258 .ops = &clk_branch2_ops, 2259 }, 2260 }, 2261 }; 2262 2263 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 2264 .halt_reg = 0x18734, 2265 .halt_check = BRANCH_HALT_VOTED, 2266 .clkr = { 2267 .enable_reg = 0x5200c, 2268 .enable_mask = BIT(28), 2269 .hw.init = &(struct clk_init_data){ 2270 .name = "gcc_qupv3_wrap1_s6_clk", 2271 .parent_names = (const char *[]){ 2272 "gcc_qupv3_wrap1_s6_clk_src", 2273 }, 2274 .num_parents = 1, 2275 .flags = CLK_SET_RATE_PARENT, 2276 .ops = &clk_branch2_ops, 2277 }, 2278 }, 2279 }; 2280 2281 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 2282 .halt_reg = 0x18864, 2283 .halt_check = BRANCH_HALT_VOTED, 2284 .clkr = { 2285 .enable_reg = 0x5200c, 2286 .enable_mask = BIT(29), 2287 .hw.init = &(struct clk_init_data){ 2288 .name = "gcc_qupv3_wrap1_s7_clk", 2289 .parent_names = (const char *[]){ 2290 "gcc_qupv3_wrap1_s7_clk_src", 2291 }, 2292 .num_parents = 1, 2293 .flags = CLK_SET_RATE_PARENT, 2294 .ops = &clk_branch2_ops, 2295 }, 2296 }, 2297 }; 2298 2299 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2300 .halt_reg = 0x17004, 2301 .halt_check = BRANCH_HALT_VOTED, 2302 .clkr = { 2303 .enable_reg = 0x5200c, 2304 .enable_mask = BIT(6), 2305 .hw.init = &(struct clk_init_data){ 2306 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2307 .ops = &clk_branch2_ops, 2308 }, 2309 }, 2310 }; 2311 2312 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2313 .halt_reg = 0x17008, 2314 .halt_check = BRANCH_HALT_VOTED, 2315 .hwcg_reg = 0x17008, 2316 .hwcg_bit = 1, 2317 .clkr = { 2318 .enable_reg = 0x5200c, 2319 .enable_mask = BIT(7), 2320 .hw.init = &(struct clk_init_data){ 2321 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2322 .ops = &clk_branch2_ops, 2323 }, 2324 }, 2325 }; 2326 2327 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2328 .halt_reg = 0x1800c, 2329 .halt_check = BRANCH_HALT_VOTED, 2330 .clkr = { 2331 .enable_reg = 0x5200c, 2332 .enable_mask = BIT(20), 2333 .hw.init = &(struct clk_init_data){ 2334 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2335 .ops = &clk_branch2_ops, 2336 }, 2337 }, 2338 }; 2339 2340 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2341 .halt_reg = 0x18010, 2342 .halt_check = BRANCH_HALT_VOTED, 2343 .hwcg_reg = 0x18010, 2344 .hwcg_bit = 1, 2345 .clkr = { 2346 .enable_reg = 0x5200c, 2347 .enable_mask = BIT(21), 2348 .hw.init = &(struct clk_init_data){ 2349 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2350 .ops = &clk_branch2_ops, 2351 }, 2352 }, 2353 }; 2354 2355 static struct clk_branch gcc_sdcc2_ahb_clk = { 2356 .halt_reg = 0x14008, 2357 .halt_check = BRANCH_HALT, 2358 .clkr = { 2359 .enable_reg = 0x14008, 2360 .enable_mask = BIT(0), 2361 .hw.init = &(struct clk_init_data){ 2362 .name = "gcc_sdcc2_ahb_clk", 2363 .ops = &clk_branch2_ops, 2364 }, 2365 }, 2366 }; 2367 2368 static struct clk_branch gcc_sdcc2_apps_clk = { 2369 .halt_reg = 0x14004, 2370 .halt_check = BRANCH_HALT, 2371 .clkr = { 2372 .enable_reg = 0x14004, 2373 .enable_mask = BIT(0), 2374 .hw.init = &(struct clk_init_data){ 2375 .name = "gcc_sdcc2_apps_clk", 2376 .parent_names = (const char *[]){ 2377 "gcc_sdcc2_apps_clk_src", 2378 }, 2379 .num_parents = 1, 2380 .flags = CLK_SET_RATE_PARENT, 2381 .ops = &clk_branch2_ops, 2382 }, 2383 }, 2384 }; 2385 2386 static struct clk_branch gcc_sdcc4_ahb_clk = { 2387 .halt_reg = 0x16008, 2388 .halt_check = BRANCH_HALT, 2389 .clkr = { 2390 .enable_reg = 0x16008, 2391 .enable_mask = BIT(0), 2392 .hw.init = &(struct clk_init_data){ 2393 .name = "gcc_sdcc4_ahb_clk", 2394 .ops = &clk_branch2_ops, 2395 }, 2396 }, 2397 }; 2398 2399 static struct clk_branch gcc_sdcc4_apps_clk = { 2400 .halt_reg = 0x16004, 2401 .halt_check = BRANCH_HALT, 2402 .clkr = { 2403 .enable_reg = 0x16004, 2404 .enable_mask = BIT(0), 2405 .hw.init = &(struct clk_init_data){ 2406 .name = "gcc_sdcc4_apps_clk", 2407 .parent_names = (const char *[]){ 2408 "gcc_sdcc4_apps_clk_src", 2409 }, 2410 .num_parents = 1, 2411 .flags = CLK_SET_RATE_PARENT, 2412 .ops = &clk_branch2_ops, 2413 }, 2414 }, 2415 }; 2416 2417 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 2418 .halt_reg = 0x414c, 2419 .halt_check = BRANCH_HALT_VOTED, 2420 .clkr = { 2421 .enable_reg = 0x52004, 2422 .enable_mask = BIT(0), 2423 .hw.init = &(struct clk_init_data){ 2424 .name = "gcc_sys_noc_cpuss_ahb_clk", 2425 .parent_names = (const char *[]){ 2426 "gcc_cpuss_ahb_clk_src", 2427 }, 2428 .num_parents = 1, 2429 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 2430 .ops = &clk_branch2_ops, 2431 }, 2432 }, 2433 }; 2434 2435 static struct clk_branch gcc_tsif_ahb_clk = { 2436 .halt_reg = 0x36004, 2437 .halt_check = BRANCH_HALT, 2438 .clkr = { 2439 .enable_reg = 0x36004, 2440 .enable_mask = BIT(0), 2441 .hw.init = &(struct clk_init_data){ 2442 .name = "gcc_tsif_ahb_clk", 2443 .ops = &clk_branch2_ops, 2444 }, 2445 }, 2446 }; 2447 2448 static struct clk_branch gcc_tsif_inactivity_timers_clk = { 2449 .halt_reg = 0x3600c, 2450 .halt_check = BRANCH_HALT, 2451 .clkr = { 2452 .enable_reg = 0x3600c, 2453 .enable_mask = BIT(0), 2454 .hw.init = &(struct clk_init_data){ 2455 .name = "gcc_tsif_inactivity_timers_clk", 2456 .ops = &clk_branch2_ops, 2457 }, 2458 }, 2459 }; 2460 2461 static struct clk_branch gcc_tsif_ref_clk = { 2462 .halt_reg = 0x36008, 2463 .halt_check = BRANCH_HALT, 2464 .clkr = { 2465 .enable_reg = 0x36008, 2466 .enable_mask = BIT(0), 2467 .hw.init = &(struct clk_init_data){ 2468 .name = "gcc_tsif_ref_clk", 2469 .parent_names = (const char *[]){ 2470 "gcc_tsif_ref_clk_src", 2471 }, 2472 .num_parents = 1, 2473 .flags = CLK_SET_RATE_PARENT, 2474 .ops = &clk_branch2_ops, 2475 }, 2476 }, 2477 }; 2478 2479 static struct clk_branch gcc_ufs_card_ahb_clk = { 2480 .halt_reg = 0x75010, 2481 .halt_check = BRANCH_HALT, 2482 .hwcg_reg = 0x75010, 2483 .hwcg_bit = 1, 2484 .clkr = { 2485 .enable_reg = 0x75010, 2486 .enable_mask = BIT(0), 2487 .hw.init = &(struct clk_init_data){ 2488 .name = "gcc_ufs_card_ahb_clk", 2489 .ops = &clk_branch2_ops, 2490 }, 2491 }, 2492 }; 2493 2494 static struct clk_branch gcc_ufs_card_axi_clk = { 2495 .halt_reg = 0x7500c, 2496 .halt_check = BRANCH_HALT, 2497 .hwcg_reg = 0x7500c, 2498 .hwcg_bit = 1, 2499 .clkr = { 2500 .enable_reg = 0x7500c, 2501 .enable_mask = BIT(0), 2502 .hw.init = &(struct clk_init_data){ 2503 .name = "gcc_ufs_card_axi_clk", 2504 .parent_names = (const char *[]){ 2505 "gcc_ufs_card_axi_clk_src", 2506 }, 2507 .num_parents = 1, 2508 .flags = CLK_SET_RATE_PARENT, 2509 .ops = &clk_branch2_ops, 2510 }, 2511 }, 2512 }; 2513 2514 static struct clk_branch gcc_ufs_card_clkref_clk = { 2515 .halt_reg = 0x8c004, 2516 .halt_check = BRANCH_HALT, 2517 .clkr = { 2518 .enable_reg = 0x8c004, 2519 .enable_mask = BIT(0), 2520 .hw.init = &(struct clk_init_data){ 2521 .name = "gcc_ufs_card_clkref_clk", 2522 .ops = &clk_branch2_ops, 2523 }, 2524 }, 2525 }; 2526 2527 static struct clk_branch gcc_ufs_card_ice_core_clk = { 2528 .halt_reg = 0x75058, 2529 .halt_check = BRANCH_HALT, 2530 .hwcg_reg = 0x75058, 2531 .hwcg_bit = 1, 2532 .clkr = { 2533 .enable_reg = 0x75058, 2534 .enable_mask = BIT(0), 2535 .hw.init = &(struct clk_init_data){ 2536 .name = "gcc_ufs_card_ice_core_clk", 2537 .parent_names = (const char *[]){ 2538 "gcc_ufs_card_ice_core_clk_src", 2539 }, 2540 .num_parents = 1, 2541 .flags = CLK_SET_RATE_PARENT, 2542 .ops = &clk_branch2_ops, 2543 }, 2544 }, 2545 }; 2546 2547 static struct clk_branch gcc_ufs_card_phy_aux_clk = { 2548 .halt_reg = 0x7508c, 2549 .halt_check = BRANCH_HALT, 2550 .hwcg_reg = 0x7508c, 2551 .hwcg_bit = 1, 2552 .clkr = { 2553 .enable_reg = 0x7508c, 2554 .enable_mask = BIT(0), 2555 .hw.init = &(struct clk_init_data){ 2556 .name = "gcc_ufs_card_phy_aux_clk", 2557 .parent_names = (const char *[]){ 2558 "gcc_ufs_card_phy_aux_clk_src", 2559 }, 2560 .num_parents = 1, 2561 .flags = CLK_SET_RATE_PARENT, 2562 .ops = &clk_branch2_ops, 2563 }, 2564 }, 2565 }; 2566 2567 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { 2568 .halt_check = BRANCH_HALT_SKIP, 2569 .clkr = { 2570 .enable_reg = 0x75018, 2571 .enable_mask = BIT(0), 2572 .hw.init = &(struct clk_init_data){ 2573 .name = "gcc_ufs_card_rx_symbol_0_clk", 2574 .ops = &clk_branch2_ops, 2575 }, 2576 }, 2577 }; 2578 2579 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { 2580 .halt_check = BRANCH_HALT_SKIP, 2581 .clkr = { 2582 .enable_reg = 0x750a8, 2583 .enable_mask = BIT(0), 2584 .hw.init = &(struct clk_init_data){ 2585 .name = "gcc_ufs_card_rx_symbol_1_clk", 2586 .ops = &clk_branch2_ops, 2587 }, 2588 }, 2589 }; 2590 2591 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { 2592 .halt_check = BRANCH_HALT_SKIP, 2593 .clkr = { 2594 .enable_reg = 0x75014, 2595 .enable_mask = BIT(0), 2596 .hw.init = &(struct clk_init_data){ 2597 .name = "gcc_ufs_card_tx_symbol_0_clk", 2598 .ops = &clk_branch2_ops, 2599 }, 2600 }, 2601 }; 2602 2603 static struct clk_branch gcc_ufs_card_unipro_core_clk = { 2604 .halt_reg = 0x75054, 2605 .halt_check = BRANCH_HALT, 2606 .hwcg_reg = 0x75054, 2607 .hwcg_bit = 1, 2608 .clkr = { 2609 .enable_reg = 0x75054, 2610 .enable_mask = BIT(0), 2611 .hw.init = &(struct clk_init_data){ 2612 .name = "gcc_ufs_card_unipro_core_clk", 2613 .parent_names = (const char *[]){ 2614 "gcc_ufs_card_unipro_core_clk_src", 2615 }, 2616 .num_parents = 1, 2617 .flags = CLK_SET_RATE_PARENT, 2618 .ops = &clk_branch2_ops, 2619 }, 2620 }, 2621 }; 2622 2623 static struct clk_branch gcc_ufs_mem_clkref_clk = { 2624 .halt_reg = 0x8c000, 2625 .halt_check = BRANCH_HALT, 2626 .clkr = { 2627 .enable_reg = 0x8c000, 2628 .enable_mask = BIT(0), 2629 .hw.init = &(struct clk_init_data){ 2630 .name = "gcc_ufs_mem_clkref_clk", 2631 .ops = &clk_branch2_ops, 2632 }, 2633 }, 2634 }; 2635 2636 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2637 .halt_reg = 0x77010, 2638 .halt_check = BRANCH_HALT, 2639 .hwcg_reg = 0x77010, 2640 .hwcg_bit = 1, 2641 .clkr = { 2642 .enable_reg = 0x77010, 2643 .enable_mask = BIT(0), 2644 .hw.init = &(struct clk_init_data){ 2645 .name = "gcc_ufs_phy_ahb_clk", 2646 .ops = &clk_branch2_ops, 2647 }, 2648 }, 2649 }; 2650 2651 static struct clk_branch gcc_ufs_phy_axi_clk = { 2652 .halt_reg = 0x7700c, 2653 .halt_check = BRANCH_HALT, 2654 .hwcg_reg = 0x7700c, 2655 .hwcg_bit = 1, 2656 .clkr = { 2657 .enable_reg = 0x7700c, 2658 .enable_mask = BIT(0), 2659 .hw.init = &(struct clk_init_data){ 2660 .name = "gcc_ufs_phy_axi_clk", 2661 .parent_names = (const char *[]){ 2662 "gcc_ufs_phy_axi_clk_src", 2663 }, 2664 .num_parents = 1, 2665 .flags = CLK_SET_RATE_PARENT, 2666 .ops = &clk_branch2_ops, 2667 }, 2668 }, 2669 }; 2670 2671 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2672 .halt_reg = 0x77058, 2673 .halt_check = BRANCH_HALT, 2674 .hwcg_reg = 0x77058, 2675 .hwcg_bit = 1, 2676 .clkr = { 2677 .enable_reg = 0x77058, 2678 .enable_mask = BIT(0), 2679 .hw.init = &(struct clk_init_data){ 2680 .name = "gcc_ufs_phy_ice_core_clk", 2681 .parent_names = (const char *[]){ 2682 "gcc_ufs_phy_ice_core_clk_src", 2683 }, 2684 .num_parents = 1, 2685 .flags = CLK_SET_RATE_PARENT, 2686 .ops = &clk_branch2_ops, 2687 }, 2688 }, 2689 }; 2690 2691 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2692 .halt_reg = 0x7708c, 2693 .halt_check = BRANCH_HALT, 2694 .hwcg_reg = 0x7708c, 2695 .hwcg_bit = 1, 2696 .clkr = { 2697 .enable_reg = 0x7708c, 2698 .enable_mask = BIT(0), 2699 .hw.init = &(struct clk_init_data){ 2700 .name = "gcc_ufs_phy_phy_aux_clk", 2701 .parent_names = (const char *[]){ 2702 "gcc_ufs_phy_phy_aux_clk_src", 2703 }, 2704 .num_parents = 1, 2705 .flags = CLK_SET_RATE_PARENT, 2706 .ops = &clk_branch2_ops, 2707 }, 2708 }, 2709 }; 2710 2711 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2712 .halt_check = BRANCH_HALT_SKIP, 2713 .clkr = { 2714 .enable_reg = 0x77018, 2715 .enable_mask = BIT(0), 2716 .hw.init = &(struct clk_init_data){ 2717 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2718 .ops = &clk_branch2_ops, 2719 }, 2720 }, 2721 }; 2722 2723 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2724 .halt_check = BRANCH_HALT_SKIP, 2725 .clkr = { 2726 .enable_reg = 0x770a8, 2727 .enable_mask = BIT(0), 2728 .hw.init = &(struct clk_init_data){ 2729 .name = "gcc_ufs_phy_rx_symbol_1_clk", 2730 .ops = &clk_branch2_ops, 2731 }, 2732 }, 2733 }; 2734 2735 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2736 .halt_check = BRANCH_HALT_SKIP, 2737 .clkr = { 2738 .enable_reg = 0x77014, 2739 .enable_mask = BIT(0), 2740 .hw.init = &(struct clk_init_data){ 2741 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2742 .ops = &clk_branch2_ops, 2743 }, 2744 }, 2745 }; 2746 2747 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2748 .halt_reg = 0x77054, 2749 .halt_check = BRANCH_HALT, 2750 .hwcg_reg = 0x77054, 2751 .hwcg_bit = 1, 2752 .clkr = { 2753 .enable_reg = 0x77054, 2754 .enable_mask = BIT(0), 2755 .hw.init = &(struct clk_init_data){ 2756 .name = "gcc_ufs_phy_unipro_core_clk", 2757 .parent_names = (const char *[]){ 2758 "gcc_ufs_phy_unipro_core_clk_src", 2759 }, 2760 .num_parents = 1, 2761 .flags = CLK_SET_RATE_PARENT, 2762 .ops = &clk_branch2_ops, 2763 }, 2764 }, 2765 }; 2766 2767 static struct clk_branch gcc_usb30_prim_master_clk = { 2768 .halt_reg = 0xf00c, 2769 .halt_check = BRANCH_HALT, 2770 .clkr = { 2771 .enable_reg = 0xf00c, 2772 .enable_mask = BIT(0), 2773 .hw.init = &(struct clk_init_data){ 2774 .name = "gcc_usb30_prim_master_clk", 2775 .parent_names = (const char *[]){ 2776 "gcc_usb30_prim_master_clk_src", 2777 }, 2778 .num_parents = 1, 2779 .flags = CLK_SET_RATE_PARENT, 2780 .ops = &clk_branch2_ops, 2781 }, 2782 }, 2783 }; 2784 2785 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2786 .halt_reg = 0xf014, 2787 .halt_check = BRANCH_HALT, 2788 .clkr = { 2789 .enable_reg = 0xf014, 2790 .enable_mask = BIT(0), 2791 .hw.init = &(struct clk_init_data){ 2792 .name = "gcc_usb30_prim_mock_utmi_clk", 2793 .parent_names = (const char *[]){ 2794 "gcc_usb30_prim_mock_utmi_clk_src", 2795 }, 2796 .num_parents = 1, 2797 .flags = CLK_SET_RATE_PARENT, 2798 .ops = &clk_branch2_ops, 2799 }, 2800 }, 2801 }; 2802 2803 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2804 .halt_reg = 0xf010, 2805 .halt_check = BRANCH_HALT, 2806 .clkr = { 2807 .enable_reg = 0xf010, 2808 .enable_mask = BIT(0), 2809 .hw.init = &(struct clk_init_data){ 2810 .name = "gcc_usb30_prim_sleep_clk", 2811 .ops = &clk_branch2_ops, 2812 }, 2813 }, 2814 }; 2815 2816 static struct clk_branch gcc_usb30_sec_master_clk = { 2817 .halt_reg = 0x1000c, 2818 .halt_check = BRANCH_HALT, 2819 .clkr = { 2820 .enable_reg = 0x1000c, 2821 .enable_mask = BIT(0), 2822 .hw.init = &(struct clk_init_data){ 2823 .name = "gcc_usb30_sec_master_clk", 2824 .parent_names = (const char *[]){ 2825 "gcc_usb30_sec_master_clk_src", 2826 }, 2827 .num_parents = 1, 2828 .flags = CLK_SET_RATE_PARENT, 2829 .ops = &clk_branch2_ops, 2830 }, 2831 }, 2832 }; 2833 2834 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { 2835 .halt_reg = 0x10014, 2836 .halt_check = BRANCH_HALT, 2837 .clkr = { 2838 .enable_reg = 0x10014, 2839 .enable_mask = BIT(0), 2840 .hw.init = &(struct clk_init_data){ 2841 .name = "gcc_usb30_sec_mock_utmi_clk", 2842 .parent_names = (const char *[]){ 2843 "gcc_usb30_sec_mock_utmi_clk_src", 2844 }, 2845 .num_parents = 1, 2846 .flags = CLK_SET_RATE_PARENT, 2847 .ops = &clk_branch2_ops, 2848 }, 2849 }, 2850 }; 2851 2852 static struct clk_branch gcc_usb30_sec_sleep_clk = { 2853 .halt_reg = 0x10010, 2854 .halt_check = BRANCH_HALT, 2855 .clkr = { 2856 .enable_reg = 0x10010, 2857 .enable_mask = BIT(0), 2858 .hw.init = &(struct clk_init_data){ 2859 .name = "gcc_usb30_sec_sleep_clk", 2860 .ops = &clk_branch2_ops, 2861 }, 2862 }, 2863 }; 2864 2865 static struct clk_branch gcc_usb3_prim_clkref_clk = { 2866 .halt_reg = 0x8c008, 2867 .halt_check = BRANCH_HALT, 2868 .clkr = { 2869 .enable_reg = 0x8c008, 2870 .enable_mask = BIT(0), 2871 .hw.init = &(struct clk_init_data){ 2872 .name = "gcc_usb3_prim_clkref_clk", 2873 .ops = &clk_branch2_ops, 2874 }, 2875 }, 2876 }; 2877 2878 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2879 .halt_reg = 0xf04c, 2880 .halt_check = BRANCH_HALT, 2881 .clkr = { 2882 .enable_reg = 0xf04c, 2883 .enable_mask = BIT(0), 2884 .hw.init = &(struct clk_init_data){ 2885 .name = "gcc_usb3_prim_phy_aux_clk", 2886 .parent_names = (const char *[]){ 2887 "gcc_usb3_prim_phy_aux_clk_src", 2888 }, 2889 .num_parents = 1, 2890 .flags = CLK_SET_RATE_PARENT, 2891 .ops = &clk_branch2_ops, 2892 }, 2893 }, 2894 }; 2895 2896 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2897 .halt_reg = 0xf050, 2898 .halt_check = BRANCH_HALT, 2899 .clkr = { 2900 .enable_reg = 0xf050, 2901 .enable_mask = BIT(0), 2902 .hw.init = &(struct clk_init_data){ 2903 .name = "gcc_usb3_prim_phy_com_aux_clk", 2904 .parent_names = (const char *[]){ 2905 "gcc_usb3_prim_phy_aux_clk_src", 2906 }, 2907 .num_parents = 1, 2908 .flags = CLK_SET_RATE_PARENT, 2909 .ops = &clk_branch2_ops, 2910 }, 2911 }, 2912 }; 2913 2914 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2915 .halt_check = BRANCH_HALT_SKIP, 2916 .clkr = { 2917 .enable_reg = 0xf054, 2918 .enable_mask = BIT(0), 2919 .hw.init = &(struct clk_init_data){ 2920 .name = "gcc_usb3_prim_phy_pipe_clk", 2921 .ops = &clk_branch2_ops, 2922 }, 2923 }, 2924 }; 2925 2926 static struct clk_branch gcc_usb3_sec_clkref_clk = { 2927 .halt_reg = 0x8c028, 2928 .halt_check = BRANCH_HALT, 2929 .clkr = { 2930 .enable_reg = 0x8c028, 2931 .enable_mask = BIT(0), 2932 .hw.init = &(struct clk_init_data){ 2933 .name = "gcc_usb3_sec_clkref_clk", 2934 .ops = &clk_branch2_ops, 2935 }, 2936 }, 2937 }; 2938 2939 static struct clk_branch gcc_usb3_sec_phy_aux_clk = { 2940 .halt_reg = 0x1004c, 2941 .halt_check = BRANCH_HALT, 2942 .clkr = { 2943 .enable_reg = 0x1004c, 2944 .enable_mask = BIT(0), 2945 .hw.init = &(struct clk_init_data){ 2946 .name = "gcc_usb3_sec_phy_aux_clk", 2947 .parent_names = (const char *[]){ 2948 "gcc_usb3_sec_phy_aux_clk_src", 2949 }, 2950 .num_parents = 1, 2951 .flags = CLK_SET_RATE_PARENT, 2952 .ops = &clk_branch2_ops, 2953 }, 2954 }, 2955 }; 2956 2957 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { 2958 .halt_reg = 0x10050, 2959 .halt_check = BRANCH_HALT, 2960 .clkr = { 2961 .enable_reg = 0x10050, 2962 .enable_mask = BIT(0), 2963 .hw.init = &(struct clk_init_data){ 2964 .name = "gcc_usb3_sec_phy_com_aux_clk", 2965 .parent_names = (const char *[]){ 2966 "gcc_usb3_sec_phy_aux_clk_src", 2967 }, 2968 .num_parents = 1, 2969 .flags = CLK_SET_RATE_PARENT, 2970 .ops = &clk_branch2_ops, 2971 }, 2972 }, 2973 }; 2974 2975 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { 2976 .halt_check = BRANCH_HALT_SKIP, 2977 .clkr = { 2978 .enable_reg = 0x10054, 2979 .enable_mask = BIT(0), 2980 .hw.init = &(struct clk_init_data){ 2981 .name = "gcc_usb3_sec_phy_pipe_clk", 2982 .ops = &clk_branch2_ops, 2983 }, 2984 }, 2985 }; 2986 2987 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 2988 .halt_reg = 0x6a004, 2989 .halt_check = BRANCH_HALT, 2990 .hwcg_reg = 0x6a004, 2991 .hwcg_bit = 1, 2992 .clkr = { 2993 .enable_reg = 0x6a004, 2994 .enable_mask = BIT(0), 2995 .hw.init = &(struct clk_init_data){ 2996 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2997 .ops = &clk_branch2_ops, 2998 }, 2999 }, 3000 }; 3001 3002 static struct clk_branch gcc_vdda_vs_clk = { 3003 .halt_reg = 0x7a00c, 3004 .halt_check = BRANCH_HALT, 3005 .clkr = { 3006 .enable_reg = 0x7a00c, 3007 .enable_mask = BIT(0), 3008 .hw.init = &(struct clk_init_data){ 3009 .name = "gcc_vdda_vs_clk", 3010 .parent_names = (const char *[]){ 3011 "gcc_vsensor_clk_src", 3012 }, 3013 .num_parents = 1, 3014 .flags = CLK_SET_RATE_PARENT, 3015 .ops = &clk_branch2_ops, 3016 }, 3017 }, 3018 }; 3019 3020 static struct clk_branch gcc_vddcx_vs_clk = { 3021 .halt_reg = 0x7a004, 3022 .halt_check = BRANCH_HALT, 3023 .clkr = { 3024 .enable_reg = 0x7a004, 3025 .enable_mask = BIT(0), 3026 .hw.init = &(struct clk_init_data){ 3027 .name = "gcc_vddcx_vs_clk", 3028 .parent_names = (const char *[]){ 3029 "gcc_vsensor_clk_src", 3030 }, 3031 .num_parents = 1, 3032 .flags = CLK_SET_RATE_PARENT, 3033 .ops = &clk_branch2_ops, 3034 }, 3035 }, 3036 }; 3037 3038 static struct clk_branch gcc_vddmx_vs_clk = { 3039 .halt_reg = 0x7a008, 3040 .halt_check = BRANCH_HALT, 3041 .clkr = { 3042 .enable_reg = 0x7a008, 3043 .enable_mask = BIT(0), 3044 .hw.init = &(struct clk_init_data){ 3045 .name = "gcc_vddmx_vs_clk", 3046 .parent_names = (const char *[]){ 3047 "gcc_vsensor_clk_src", 3048 }, 3049 .num_parents = 1, 3050 .flags = CLK_SET_RATE_PARENT, 3051 .ops = &clk_branch2_ops, 3052 }, 3053 }, 3054 }; 3055 3056 static struct clk_branch gcc_video_ahb_clk = { 3057 .halt_reg = 0xb004, 3058 .halt_check = BRANCH_HALT, 3059 .hwcg_reg = 0xb004, 3060 .hwcg_bit = 1, 3061 .clkr = { 3062 .enable_reg = 0xb004, 3063 .enable_mask = BIT(0), 3064 .hw.init = &(struct clk_init_data){ 3065 .name = "gcc_video_ahb_clk", 3066 .flags = CLK_IS_CRITICAL, 3067 .ops = &clk_branch2_ops, 3068 }, 3069 }, 3070 }; 3071 3072 static struct clk_branch gcc_video_axi_clk = { 3073 .halt_reg = 0xb01c, 3074 .halt_check = BRANCH_VOTED, 3075 .clkr = { 3076 .enable_reg = 0xb01c, 3077 .enable_mask = BIT(0), 3078 .hw.init = &(struct clk_init_data){ 3079 .name = "gcc_video_axi_clk", 3080 .ops = &clk_branch2_ops, 3081 }, 3082 }, 3083 }; 3084 3085 static struct clk_branch gcc_video_xo_clk = { 3086 .halt_reg = 0xb028, 3087 .halt_check = BRANCH_HALT, 3088 .clkr = { 3089 .enable_reg = 0xb028, 3090 .enable_mask = BIT(0), 3091 .hw.init = &(struct clk_init_data){ 3092 .name = "gcc_video_xo_clk", 3093 .flags = CLK_IS_CRITICAL, 3094 .ops = &clk_branch2_ops, 3095 }, 3096 }, 3097 }; 3098 3099 static struct clk_branch gcc_vs_ctrl_ahb_clk = { 3100 .halt_reg = 0x7a014, 3101 .halt_check = BRANCH_HALT, 3102 .hwcg_reg = 0x7a014, 3103 .hwcg_bit = 1, 3104 .clkr = { 3105 .enable_reg = 0x7a014, 3106 .enable_mask = BIT(0), 3107 .hw.init = &(struct clk_init_data){ 3108 .name = "gcc_vs_ctrl_ahb_clk", 3109 .ops = &clk_branch2_ops, 3110 }, 3111 }, 3112 }; 3113 3114 static struct clk_branch gcc_vs_ctrl_clk = { 3115 .halt_reg = 0x7a010, 3116 .halt_check = BRANCH_HALT, 3117 .clkr = { 3118 .enable_reg = 0x7a010, 3119 .enable_mask = BIT(0), 3120 .hw.init = &(struct clk_init_data){ 3121 .name = "gcc_vs_ctrl_clk", 3122 .parent_names = (const char *[]){ 3123 "gcc_vs_ctrl_clk_src", 3124 }, 3125 .num_parents = 1, 3126 .flags = CLK_SET_RATE_PARENT, 3127 .ops = &clk_branch2_ops, 3128 }, 3129 }, 3130 }; 3131 3132 static struct clk_branch gcc_cpuss_dvm_bus_clk = { 3133 .halt_reg = 0x48190, 3134 .halt_check = BRANCH_HALT, 3135 .clkr = { 3136 .enable_reg = 0x48190, 3137 .enable_mask = BIT(0), 3138 .hw.init = &(struct clk_init_data){ 3139 .name = "gcc_cpuss_dvm_bus_clk", 3140 .flags = CLK_IS_CRITICAL, 3141 .ops = &clk_branch2_ops, 3142 }, 3143 }, 3144 }; 3145 3146 static struct clk_branch gcc_cpuss_gnoc_clk = { 3147 .halt_reg = 0x48004, 3148 .halt_check = BRANCH_HALT_VOTED, 3149 .hwcg_reg = 0x48004, 3150 .hwcg_bit = 1, 3151 .clkr = { 3152 .enable_reg = 0x52004, 3153 .enable_mask = BIT(22), 3154 .hw.init = &(struct clk_init_data){ 3155 .name = "gcc_cpuss_gnoc_clk", 3156 .flags = CLK_IS_CRITICAL, 3157 .ops = &clk_branch2_ops, 3158 }, 3159 }, 3160 }; 3161 3162 /* TODO: Remove after DTS updated to protect these */ 3163 #ifdef CONFIG_SDM_LPASSCC_845 3164 static struct clk_branch gcc_lpass_q6_axi_clk = { 3165 .halt_reg = 0x47000, 3166 .halt_check = BRANCH_HALT, 3167 .clkr = { 3168 .enable_reg = 0x47000, 3169 .enable_mask = BIT(0), 3170 .hw.init = &(struct clk_init_data){ 3171 .name = "gcc_lpass_q6_axi_clk", 3172 .flags = CLK_IS_CRITICAL, 3173 .ops = &clk_branch2_ops, 3174 }, 3175 }, 3176 }; 3177 3178 static struct clk_branch gcc_lpass_sway_clk = { 3179 .halt_reg = 0x47008, 3180 .halt_check = BRANCH_HALT, 3181 .clkr = { 3182 .enable_reg = 0x47008, 3183 .enable_mask = BIT(0), 3184 .hw.init = &(struct clk_init_data){ 3185 .name = "gcc_lpass_sway_clk", 3186 .flags = CLK_IS_CRITICAL, 3187 .ops = &clk_branch2_ops, 3188 }, 3189 }, 3190 }; 3191 #endif 3192 3193 static struct gdsc pcie_0_gdsc = { 3194 .gdscr = 0x6b004, 3195 .pd = { 3196 .name = "pcie_0_gdsc", 3197 }, 3198 .pwrsts = PWRSTS_OFF_ON, 3199 .flags = POLL_CFG_GDSCR, 3200 }; 3201 3202 static struct gdsc pcie_1_gdsc = { 3203 .gdscr = 0x8d004, 3204 .pd = { 3205 .name = "pcie_1_gdsc", 3206 }, 3207 .pwrsts = PWRSTS_OFF_ON, 3208 .flags = POLL_CFG_GDSCR, 3209 }; 3210 3211 static struct gdsc ufs_card_gdsc = { 3212 .gdscr = 0x75004, 3213 .pd = { 3214 .name = "ufs_card_gdsc", 3215 }, 3216 .pwrsts = PWRSTS_OFF_ON, 3217 .flags = POLL_CFG_GDSCR, 3218 }; 3219 3220 static struct gdsc ufs_phy_gdsc = { 3221 .gdscr = 0x77004, 3222 .pd = { 3223 .name = "ufs_phy_gdsc", 3224 }, 3225 .pwrsts = PWRSTS_OFF_ON, 3226 .flags = POLL_CFG_GDSCR, 3227 }; 3228 3229 static struct gdsc usb30_prim_gdsc = { 3230 .gdscr = 0xf004, 3231 .pd = { 3232 .name = "usb30_prim_gdsc", 3233 }, 3234 .pwrsts = PWRSTS_OFF_ON, 3235 .flags = POLL_CFG_GDSCR, 3236 }; 3237 3238 static struct gdsc usb30_sec_gdsc = { 3239 .gdscr = 0x10004, 3240 .pd = { 3241 .name = "usb30_sec_gdsc", 3242 }, 3243 .pwrsts = PWRSTS_OFF_ON, 3244 .flags = POLL_CFG_GDSCR, 3245 }; 3246 3247 static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = { 3248 .gdscr = 0x7d030, 3249 .pd = { 3250 .name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc", 3251 }, 3252 .pwrsts = PWRSTS_OFF_ON, 3253 }; 3254 3255 static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = { 3256 .gdscr = 0x7d03c, 3257 .pd = { 3258 .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc", 3259 }, 3260 .pwrsts = PWRSTS_OFF_ON, 3261 }; 3262 3263 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = { 3264 .gdscr = 0x7d034, 3265 .pd = { 3266 .name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc", 3267 }, 3268 .pwrsts = PWRSTS_OFF_ON, 3269 }; 3270 3271 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = { 3272 .gdscr = 0x7d038, 3273 .pd = { 3274 .name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc", 3275 }, 3276 .pwrsts = PWRSTS_OFF_ON, 3277 }; 3278 3279 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { 3280 .gdscr = 0x7d040, 3281 .pd = { 3282 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", 3283 }, 3284 .pwrsts = PWRSTS_OFF_ON, 3285 }; 3286 3287 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = { 3288 .gdscr = 0x7d048, 3289 .pd = { 3290 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", 3291 }, 3292 .pwrsts = PWRSTS_OFF_ON, 3293 }; 3294 3295 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = { 3296 .gdscr = 0x7d044, 3297 .pd = { 3298 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc", 3299 }, 3300 .pwrsts = PWRSTS_OFF_ON, 3301 }; 3302 3303 static struct clk_regmap *gcc_sdm845_clocks[] = { 3304 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, 3305 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, 3306 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 3307 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 3308 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, 3309 [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr, 3310 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3311 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 3312 [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr, 3313 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 3314 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, 3315 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, 3316 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, 3317 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3318 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, 3319 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, 3320 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, 3321 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, 3322 [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr, 3323 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 3324 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, 3325 [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr, 3326 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 3327 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 3328 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 3329 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3330 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3331 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3332 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3333 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3334 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3335 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 3336 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3337 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3338 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, 3339 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3340 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3341 [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr, 3342 [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr, 3343 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 3344 [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr, 3345 [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr, 3346 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr, 3347 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, 3348 [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr, 3349 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3350 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 3351 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3352 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr, 3353 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3354 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3355 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3356 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 3357 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 3358 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 3359 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 3360 [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr, 3361 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 3362 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 3363 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 3364 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 3365 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, 3366 [GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr, 3367 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, 3368 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3369 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3370 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3371 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3372 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3373 [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr, 3374 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3375 [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr, 3376 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3377 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3378 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3379 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3380 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3381 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3382 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3383 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3384 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3385 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3386 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3387 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3388 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 3389 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 3390 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 3391 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 3392 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3393 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3394 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3395 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3396 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3397 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3398 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3399 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3400 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3401 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3402 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3403 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3404 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 3405 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 3406 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 3407 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 3408 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3409 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3410 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3411 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3412 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3413 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3414 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3415 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3416 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3417 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 3418 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 3419 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 3420 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = 3421 &gcc_tsif_inactivity_timers_clk.clkr, 3422 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 3423 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, 3424 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, 3425 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, 3426 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, 3427 [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr, 3428 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, 3429 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, 3430 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, 3431 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, 3432 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, 3433 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, 3434 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, 3435 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, 3436 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = 3437 &gcc_ufs_card_unipro_core_clk_src.clkr, 3438 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, 3439 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3440 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3441 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3442 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3443 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3444 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3445 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3446 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3447 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3448 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3449 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3450 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 3451 &gcc_ufs_phy_unipro_core_clk_src.clkr, 3452 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3453 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3454 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3455 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 3456 &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3457 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3458 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, 3459 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, 3460 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, 3461 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = 3462 &gcc_usb30_sec_mock_utmi_clk_src.clkr, 3463 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, 3464 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 3465 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3466 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3467 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3468 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3469 [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr, 3470 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, 3471 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, 3472 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, 3473 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, 3474 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 3475 [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr, 3476 [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr, 3477 [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr, 3478 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 3479 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr, 3480 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 3481 [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr, 3482 [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr, 3483 [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr, 3484 [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr, 3485 [GPLL0] = &gpll0.clkr, 3486 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 3487 [GPLL4] = &gpll4.clkr, 3488 [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr, 3489 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, 3490 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, 3491 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, 3492 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, 3493 #ifdef CONFIG_SDM_LPASSCC_845 3494 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, 3495 [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr, 3496 #endif 3497 }; 3498 3499 static const struct qcom_reset_map gcc_sdm845_resets[] = { 3500 [GCC_MMSS_BCR] = { 0xb000 }, 3501 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3502 [GCC_PCIE_1_BCR] = { 0x8d000 }, 3503 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 3504 [GCC_PDM_BCR] = { 0x33000 }, 3505 [GCC_PRNG_BCR] = { 0x34000 }, 3506 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, 3507 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 3508 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3509 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3510 [GCC_SDCC2_BCR] = { 0x14000 }, 3511 [GCC_SDCC4_BCR] = { 0x16000 }, 3512 [GCC_TSIF_BCR] = { 0x36000 }, 3513 [GCC_UFS_CARD_BCR] = { 0x75000 }, 3514 [GCC_UFS_PHY_BCR] = { 0x77000 }, 3515 [GCC_USB30_PRIM_BCR] = { 0xf000 }, 3516 [GCC_USB30_SEC_BCR] = { 0x10000 }, 3517 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 3518 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3519 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 3520 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 3521 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3522 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 3523 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 3524 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3525 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 3526 }; 3527 3528 static struct gdsc *gcc_sdm845_gdscs[] = { 3529 [PCIE_0_GDSC] = &pcie_0_gdsc, 3530 [PCIE_1_GDSC] = &pcie_1_gdsc, 3531 [UFS_CARD_GDSC] = &ufs_card_gdsc, 3532 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3533 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3534 [USB30_SEC_GDSC] = &usb30_sec_gdsc, 3535 [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = 3536 &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc, 3537 [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = 3538 &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc, 3539 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = 3540 &hlos1_vote_aggre_noc_mmu_tbu1_gdsc, 3541 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = 3542 &hlos1_vote_aggre_noc_mmu_tbu2_gdsc, 3543 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = 3544 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, 3545 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = 3546 &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, 3547 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc, 3548 }; 3549 3550 static const struct regmap_config gcc_sdm845_regmap_config = { 3551 .reg_bits = 32, 3552 .reg_stride = 4, 3553 .val_bits = 32, 3554 .max_register = 0x182090, 3555 .fast_io = true, 3556 }; 3557 3558 static const struct qcom_cc_desc gcc_sdm845_desc = { 3559 .config = &gcc_sdm845_regmap_config, 3560 .clks = gcc_sdm845_clocks, 3561 .num_clks = ARRAY_SIZE(gcc_sdm845_clocks), 3562 .resets = gcc_sdm845_resets, 3563 .num_resets = ARRAY_SIZE(gcc_sdm845_resets), 3564 .gdscs = gcc_sdm845_gdscs, 3565 .num_gdscs = ARRAY_SIZE(gcc_sdm845_gdscs), 3566 }; 3567 3568 static const struct of_device_id gcc_sdm845_match_table[] = { 3569 { .compatible = "qcom,gcc-sdm845" }, 3570 { } 3571 }; 3572 MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table); 3573 3574 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3575 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk), 3576 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk), 3577 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk), 3578 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk), 3579 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk), 3580 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk), 3581 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk), 3582 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk), 3583 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk), 3584 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk), 3585 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk), 3586 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk), 3587 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk), 3588 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk), 3589 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk), 3590 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk), 3591 }; 3592 3593 static int gcc_sdm845_probe(struct platform_device *pdev) 3594 { 3595 struct regmap *regmap; 3596 int ret; 3597 3598 regmap = qcom_cc_map(pdev, &gcc_sdm845_desc); 3599 if (IS_ERR(regmap)) 3600 return PTR_ERR(regmap); 3601 3602 /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */ 3603 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); 3604 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 3605 3606 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3607 ARRAY_SIZE(gcc_dfs_clocks)); 3608 if (ret) 3609 return ret; 3610 3611 return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap); 3612 } 3613 3614 static struct platform_driver gcc_sdm845_driver = { 3615 .probe = gcc_sdm845_probe, 3616 .driver = { 3617 .name = "gcc-sdm845", 3618 .of_match_table = gcc_sdm845_match_table, 3619 }, 3620 }; 3621 3622 static int __init gcc_sdm845_init(void) 3623 { 3624 return platform_driver_register(&gcc_sdm845_driver); 3625 } 3626 subsys_initcall(gcc_sdm845_init); 3627 3628 static void __exit gcc_sdm845_exit(void) 3629 { 3630 platform_driver_unregister(&gcc_sdm845_driver); 3631 } 3632 module_exit(gcc_sdm845_exit); 3633 3634 MODULE_DESCRIPTION("QTI GCC SDM845 Driver"); 3635 MODULE_LICENSE("GPL v2"); 3636 MODULE_ALIAS("platform:gcc-sdm845"); 3637