1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/bitops.h> 8 #include <linux/err.h> 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/clk-provider.h> 14 #include <linux/regmap.h> 15 #include <linux/reset-controller.h> 16 17 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 18 19 #include "common.h" 20 #include "clk-regmap.h" 21 #include "clk-pll.h" 22 #include "clk-rcg.h" 23 #include "clk-branch.h" 24 #include "clk-alpha-pll.h" 25 #include "gdsc.h" 26 #include "reset.h" 27 28 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } 29 30 enum { 31 P_BI_TCXO, 32 P_AUD_REF_CLK, 33 P_CORE_BI_PLL_TEST_SE, 34 P_GPLL0_OUT_EVEN, 35 P_GPLL0_OUT_MAIN, 36 P_GPLL4_OUT_MAIN, 37 P_SLEEP_CLK, 38 }; 39 40 static const struct parent_map gcc_parent_map_0[] = { 41 { P_BI_TCXO, 0 }, 42 { P_GPLL0_OUT_MAIN, 1 }, 43 { P_GPLL0_OUT_EVEN, 6 }, 44 { P_CORE_BI_PLL_TEST_SE, 7 }, 45 }; 46 47 static const char * const gcc_parent_names_0[] = { 48 "bi_tcxo", 49 "gpll0", 50 "gpll0_out_even", 51 "core_bi_pll_test_se", 52 }; 53 54 static const struct parent_map gcc_parent_map_1[] = { 55 { P_BI_TCXO, 0 }, 56 { P_GPLL0_OUT_MAIN, 1 }, 57 { P_SLEEP_CLK, 5 }, 58 { P_GPLL0_OUT_EVEN, 6 }, 59 { P_CORE_BI_PLL_TEST_SE, 7 }, 60 }; 61 62 static const char * const gcc_parent_names_1[] = { 63 "bi_tcxo", 64 "gpll0", 65 "core_pi_sleep_clk", 66 "gpll0_out_even", 67 "core_bi_pll_test_se", 68 }; 69 70 static const struct parent_map gcc_parent_map_2[] = { 71 { P_BI_TCXO, 0 }, 72 { P_SLEEP_CLK, 5 }, 73 { P_CORE_BI_PLL_TEST_SE, 7 }, 74 }; 75 76 static const char * const gcc_parent_names_2[] = { 77 "bi_tcxo", 78 "core_pi_sleep_clk", 79 "core_bi_pll_test_se", 80 }; 81 82 static const struct parent_map gcc_parent_map_3[] = { 83 { P_BI_TCXO, 0 }, 84 { P_GPLL0_OUT_MAIN, 1 }, 85 { P_CORE_BI_PLL_TEST_SE, 7 }, 86 }; 87 88 static const char * const gcc_parent_names_3[] = { 89 "bi_tcxo", 90 "gpll0", 91 "core_bi_pll_test_se", 92 }; 93 94 static const struct parent_map gcc_parent_map_4[] = { 95 { P_BI_TCXO, 0 }, 96 { P_CORE_BI_PLL_TEST_SE, 7 }, 97 }; 98 99 static const char * const gcc_parent_names_4[] = { 100 "bi_tcxo", 101 "core_bi_pll_test_se", 102 }; 103 104 static const struct parent_map gcc_parent_map_5[] = { 105 { P_BI_TCXO, 0 }, 106 { P_GPLL0_OUT_MAIN, 1 }, 107 { P_GPLL4_OUT_MAIN, 5 }, 108 { P_GPLL0_OUT_EVEN, 6 }, 109 { P_CORE_BI_PLL_TEST_SE, 7 }, 110 }; 111 112 static const char * const gcc_parent_names_5[] = { 113 "bi_tcxo", 114 "gpll0", 115 "gpll4", 116 "gpll0_out_even", 117 "core_bi_pll_test_se", 118 }; 119 120 static const struct parent_map gcc_parent_map_6[] = { 121 { P_BI_TCXO, 0 }, 122 { P_GPLL0_OUT_MAIN, 1 }, 123 { P_AUD_REF_CLK, 2 }, 124 { P_GPLL0_OUT_EVEN, 6 }, 125 { P_CORE_BI_PLL_TEST_SE, 7 }, 126 }; 127 128 static const char * const gcc_parent_names_6[] = { 129 "bi_tcxo", 130 "gpll0", 131 "aud_ref_clk", 132 "gpll0_out_even", 133 "core_bi_pll_test_se", 134 }; 135 136 static const char * const gcc_parent_names_7[] = { 137 "bi_tcxo", 138 "gpll0", 139 "gpll0_out_even", 140 "core_bi_pll_test_se", 141 }; 142 143 static const char * const gcc_parent_names_8[] = { 144 "bi_tcxo", 145 "gpll0", 146 "core_bi_pll_test_se", 147 }; 148 149 static const struct parent_map gcc_parent_map_10[] = { 150 { P_BI_TCXO, 0 }, 151 { P_GPLL0_OUT_MAIN, 1 }, 152 { P_GPLL4_OUT_MAIN, 5 }, 153 { P_GPLL0_OUT_EVEN, 6 }, 154 { P_CORE_BI_PLL_TEST_SE, 7 }, 155 }; 156 157 static const char * const gcc_parent_names_10[] = { 158 "bi_tcxo", 159 "gpll0", 160 "gpll4", 161 "gpll0_out_even", 162 "core_bi_pll_test_se", 163 }; 164 165 static struct clk_alpha_pll gpll0 = { 166 .offset = 0x0, 167 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 168 .clkr = { 169 .enable_reg = 0x52000, 170 .enable_mask = BIT(0), 171 .hw.init = &(struct clk_init_data){ 172 .name = "gpll0", 173 .parent_names = (const char *[]){ "bi_tcxo" }, 174 .num_parents = 1, 175 .ops = &clk_alpha_pll_fixed_fabia_ops, 176 }, 177 }, 178 }; 179 180 static struct clk_alpha_pll gpll4 = { 181 .offset = 0x76000, 182 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 183 .clkr = { 184 .enable_reg = 0x52000, 185 .enable_mask = BIT(4), 186 .hw.init = &(struct clk_init_data){ 187 .name = "gpll4", 188 .parent_names = (const char *[]){ "bi_tcxo" }, 189 .num_parents = 1, 190 .ops = &clk_alpha_pll_fixed_fabia_ops, 191 }, 192 }, 193 }; 194 195 static const struct clk_div_table post_div_table_fabia_even[] = { 196 { 0x0, 1 }, 197 { 0x1, 2 }, 198 { 0x3, 4 }, 199 { 0x7, 8 }, 200 { } 201 }; 202 203 static struct clk_alpha_pll_postdiv gpll0_out_even = { 204 .offset = 0x0, 205 .post_div_shift = 8, 206 .post_div_table = post_div_table_fabia_even, 207 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 208 .width = 4, 209 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 210 .clkr.hw.init = &(struct clk_init_data){ 211 .name = "gpll0_out_even", 212 .parent_names = (const char *[]){ "gpll0" }, 213 .num_parents = 1, 214 .ops = &clk_alpha_pll_postdiv_fabia_ops, 215 }, 216 }; 217 218 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { 219 F(19200000, P_BI_TCXO, 1, 0, 0), 220 { } 221 }; 222 223 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 224 .cmd_rcgr = 0x48014, 225 .mnd_width = 0, 226 .hid_width = 5, 227 .parent_map = gcc_parent_map_0, 228 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, 229 .clkr.hw.init = &(struct clk_init_data){ 230 .name = "gcc_cpuss_ahb_clk_src", 231 .parent_names = gcc_parent_names_7, 232 .num_parents = 4, 233 .ops = &clk_rcg2_ops, 234 }, 235 }; 236 237 static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = { 238 F(19200000, P_BI_TCXO, 1, 0, 0), 239 { } 240 }; 241 242 static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = { 243 .cmd_rcgr = 0x4815c, 244 .mnd_width = 0, 245 .hid_width = 5, 246 .parent_map = gcc_parent_map_3, 247 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, 248 .clkr.hw.init = &(struct clk_init_data){ 249 .name = "gcc_cpuss_rbcpr_clk_src", 250 .parent_names = gcc_parent_names_8, 251 .num_parents = 3, 252 .ops = &clk_rcg2_ops, 253 }, 254 }; 255 256 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 257 F(19200000, P_BI_TCXO, 1, 0, 0), 258 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 259 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 260 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 261 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 262 { } 263 }; 264 265 static struct clk_rcg2 gcc_gp1_clk_src = { 266 .cmd_rcgr = 0x64004, 267 .mnd_width = 8, 268 .hid_width = 5, 269 .parent_map = gcc_parent_map_1, 270 .freq_tbl = ftbl_gcc_gp1_clk_src, 271 .clkr.hw.init = &(struct clk_init_data){ 272 .name = "gcc_gp1_clk_src", 273 .parent_names = gcc_parent_names_1, 274 .num_parents = 5, 275 .ops = &clk_rcg2_ops, 276 }, 277 }; 278 279 static struct clk_rcg2 gcc_gp2_clk_src = { 280 .cmd_rcgr = 0x65004, 281 .mnd_width = 8, 282 .hid_width = 5, 283 .parent_map = gcc_parent_map_1, 284 .freq_tbl = ftbl_gcc_gp1_clk_src, 285 .clkr.hw.init = &(struct clk_init_data){ 286 .name = "gcc_gp2_clk_src", 287 .parent_names = gcc_parent_names_1, 288 .num_parents = 5, 289 .ops = &clk_rcg2_ops, 290 }, 291 }; 292 293 static struct clk_rcg2 gcc_gp3_clk_src = { 294 .cmd_rcgr = 0x66004, 295 .mnd_width = 8, 296 .hid_width = 5, 297 .parent_map = gcc_parent_map_1, 298 .freq_tbl = ftbl_gcc_gp1_clk_src, 299 .clkr.hw.init = &(struct clk_init_data){ 300 .name = "gcc_gp3_clk_src", 301 .parent_names = gcc_parent_names_1, 302 .num_parents = 5, 303 .ops = &clk_rcg2_ops, 304 }, 305 }; 306 307 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 308 F(9600000, P_BI_TCXO, 2, 0, 0), 309 F(19200000, P_BI_TCXO, 1, 0, 0), 310 { } 311 }; 312 313 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 314 .cmd_rcgr = 0x6b028, 315 .mnd_width = 16, 316 .hid_width = 5, 317 .parent_map = gcc_parent_map_2, 318 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 319 .clkr.hw.init = &(struct clk_init_data){ 320 .name = "gcc_pcie_0_aux_clk_src", 321 .parent_names = gcc_parent_names_2, 322 .num_parents = 3, 323 .ops = &clk_rcg2_ops, 324 }, 325 }; 326 327 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 328 .cmd_rcgr = 0x8d028, 329 .mnd_width = 16, 330 .hid_width = 5, 331 .parent_map = gcc_parent_map_2, 332 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 333 .clkr.hw.init = &(struct clk_init_data){ 334 .name = "gcc_pcie_1_aux_clk_src", 335 .parent_names = gcc_parent_names_2, 336 .num_parents = 3, 337 .ops = &clk_rcg2_ops, 338 }, 339 }; 340 341 static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { 342 F(19200000, P_BI_TCXO, 1, 0, 0), 343 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 344 { } 345 }; 346 347 static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { 348 .cmd_rcgr = 0x6f014, 349 .mnd_width = 0, 350 .hid_width = 5, 351 .parent_map = gcc_parent_map_0, 352 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, 353 .clkr.hw.init = &(struct clk_init_data){ 354 .name = "gcc_pcie_phy_refgen_clk_src", 355 .parent_names = gcc_parent_names_0, 356 .num_parents = 4, 357 .ops = &clk_rcg2_ops, 358 }, 359 }; 360 361 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 362 F(9600000, P_BI_TCXO, 2, 0, 0), 363 F(19200000, P_BI_TCXO, 1, 0, 0), 364 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 365 { } 366 }; 367 368 static struct clk_rcg2 gcc_pdm2_clk_src = { 369 .cmd_rcgr = 0x33010, 370 .mnd_width = 0, 371 .hid_width = 5, 372 .parent_map = gcc_parent_map_0, 373 .freq_tbl = ftbl_gcc_pdm2_clk_src, 374 .clkr.hw.init = &(struct clk_init_data){ 375 .name = "gcc_pdm2_clk_src", 376 .parent_names = gcc_parent_names_0, 377 .num_parents = 4, 378 .ops = &clk_rcg2_ops, 379 }, 380 }; 381 382 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 383 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 384 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 385 F(19200000, P_BI_TCXO, 1, 0, 0), 386 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 387 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 388 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 389 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 390 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 391 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 392 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 393 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), 394 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), 395 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), 396 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), 397 F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75), 398 { } 399 }; 400 401 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 402 .cmd_rcgr = 0x17034, 403 .mnd_width = 16, 404 .hid_width = 5, 405 .parent_map = gcc_parent_map_0, 406 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 407 .clkr.hw.init = &(struct clk_init_data){ 408 .name = "gcc_qupv3_wrap0_s0_clk_src", 409 .parent_names = gcc_parent_names_0, 410 .num_parents = 4, 411 .ops = &clk_rcg2_shared_ops, 412 }, 413 }; 414 415 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 416 .cmd_rcgr = 0x17164, 417 .mnd_width = 16, 418 .hid_width = 5, 419 .parent_map = gcc_parent_map_0, 420 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 421 .clkr.hw.init = &(struct clk_init_data){ 422 .name = "gcc_qupv3_wrap0_s1_clk_src", 423 .parent_names = gcc_parent_names_0, 424 .num_parents = 4, 425 .ops = &clk_rcg2_shared_ops, 426 }, 427 }; 428 429 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 430 .cmd_rcgr = 0x17294, 431 .mnd_width = 16, 432 .hid_width = 5, 433 .parent_map = gcc_parent_map_0, 434 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 435 .clkr.hw.init = &(struct clk_init_data){ 436 .name = "gcc_qupv3_wrap0_s2_clk_src", 437 .parent_names = gcc_parent_names_0, 438 .num_parents = 4, 439 .ops = &clk_rcg2_shared_ops, 440 }, 441 }; 442 443 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 444 .cmd_rcgr = 0x173c4, 445 .mnd_width = 16, 446 .hid_width = 5, 447 .parent_map = gcc_parent_map_0, 448 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 449 .clkr.hw.init = &(struct clk_init_data){ 450 .name = "gcc_qupv3_wrap0_s3_clk_src", 451 .parent_names = gcc_parent_names_0, 452 .num_parents = 4, 453 .ops = &clk_rcg2_shared_ops, 454 }, 455 }; 456 457 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 458 .cmd_rcgr = 0x174f4, 459 .mnd_width = 16, 460 .hid_width = 5, 461 .parent_map = gcc_parent_map_0, 462 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 463 .clkr.hw.init = &(struct clk_init_data){ 464 .name = "gcc_qupv3_wrap0_s4_clk_src", 465 .parent_names = gcc_parent_names_0, 466 .num_parents = 4, 467 .ops = &clk_rcg2_shared_ops, 468 }, 469 }; 470 471 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 472 .cmd_rcgr = 0x17624, 473 .mnd_width = 16, 474 .hid_width = 5, 475 .parent_map = gcc_parent_map_0, 476 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 477 .clkr.hw.init = &(struct clk_init_data){ 478 .name = "gcc_qupv3_wrap0_s5_clk_src", 479 .parent_names = gcc_parent_names_0, 480 .num_parents = 4, 481 .ops = &clk_rcg2_shared_ops, 482 }, 483 }; 484 485 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 486 .cmd_rcgr = 0x17754, 487 .mnd_width = 16, 488 .hid_width = 5, 489 .parent_map = gcc_parent_map_0, 490 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 491 .clkr.hw.init = &(struct clk_init_data){ 492 .name = "gcc_qupv3_wrap0_s6_clk_src", 493 .parent_names = gcc_parent_names_0, 494 .num_parents = 4, 495 .ops = &clk_rcg2_shared_ops, 496 }, 497 }; 498 499 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 500 .cmd_rcgr = 0x17884, 501 .mnd_width = 16, 502 .hid_width = 5, 503 .parent_map = gcc_parent_map_0, 504 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 505 .clkr.hw.init = &(struct clk_init_data){ 506 .name = "gcc_qupv3_wrap0_s7_clk_src", 507 .parent_names = gcc_parent_names_0, 508 .num_parents = 4, 509 .ops = &clk_rcg2_shared_ops, 510 }, 511 }; 512 513 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 514 .cmd_rcgr = 0x18018, 515 .mnd_width = 16, 516 .hid_width = 5, 517 .parent_map = gcc_parent_map_0, 518 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 519 .clkr.hw.init = &(struct clk_init_data){ 520 .name = "gcc_qupv3_wrap1_s0_clk_src", 521 .parent_names = gcc_parent_names_0, 522 .num_parents = 4, 523 .ops = &clk_rcg2_shared_ops, 524 }, 525 }; 526 527 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 528 .cmd_rcgr = 0x18148, 529 .mnd_width = 16, 530 .hid_width = 5, 531 .parent_map = gcc_parent_map_0, 532 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 533 .clkr.hw.init = &(struct clk_init_data){ 534 .name = "gcc_qupv3_wrap1_s1_clk_src", 535 .parent_names = gcc_parent_names_0, 536 .num_parents = 4, 537 .ops = &clk_rcg2_shared_ops, 538 }, 539 }; 540 541 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 542 .cmd_rcgr = 0x18278, 543 .mnd_width = 16, 544 .hid_width = 5, 545 .parent_map = gcc_parent_map_0, 546 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 547 .clkr.hw.init = &(struct clk_init_data){ 548 .name = "gcc_qupv3_wrap1_s2_clk_src", 549 .parent_names = gcc_parent_names_0, 550 .num_parents = 4, 551 .ops = &clk_rcg2_shared_ops, 552 }, 553 }; 554 555 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 556 .cmd_rcgr = 0x183a8, 557 .mnd_width = 16, 558 .hid_width = 5, 559 .parent_map = gcc_parent_map_0, 560 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 561 .clkr.hw.init = &(struct clk_init_data){ 562 .name = "gcc_qupv3_wrap1_s3_clk_src", 563 .parent_names = gcc_parent_names_0, 564 .num_parents = 4, 565 .ops = &clk_rcg2_shared_ops, 566 }, 567 }; 568 569 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 570 .cmd_rcgr = 0x184d8, 571 .mnd_width = 16, 572 .hid_width = 5, 573 .parent_map = gcc_parent_map_0, 574 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 575 .clkr.hw.init = &(struct clk_init_data){ 576 .name = "gcc_qupv3_wrap1_s4_clk_src", 577 .parent_names = gcc_parent_names_0, 578 .num_parents = 4, 579 .ops = &clk_rcg2_shared_ops, 580 }, 581 }; 582 583 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 584 .cmd_rcgr = 0x18608, 585 .mnd_width = 16, 586 .hid_width = 5, 587 .parent_map = gcc_parent_map_0, 588 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 589 .clkr.hw.init = &(struct clk_init_data){ 590 .name = "gcc_qupv3_wrap1_s5_clk_src", 591 .parent_names = gcc_parent_names_0, 592 .num_parents = 4, 593 .ops = &clk_rcg2_shared_ops, 594 }, 595 }; 596 597 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 598 .cmd_rcgr = 0x18738, 599 .mnd_width = 16, 600 .hid_width = 5, 601 .parent_map = gcc_parent_map_0, 602 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 603 .clkr.hw.init = &(struct clk_init_data){ 604 .name = "gcc_qupv3_wrap1_s6_clk_src", 605 .parent_names = gcc_parent_names_0, 606 .num_parents = 4, 607 .ops = &clk_rcg2_shared_ops, 608 }, 609 }; 610 611 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 612 .cmd_rcgr = 0x18868, 613 .mnd_width = 16, 614 .hid_width = 5, 615 .parent_map = gcc_parent_map_0, 616 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 617 .clkr.hw.init = &(struct clk_init_data){ 618 .name = "gcc_qupv3_wrap1_s7_clk_src", 619 .parent_names = gcc_parent_names_0, 620 .num_parents = 4, 621 .ops = &clk_rcg2_shared_ops, 622 }, 623 }; 624 625 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 626 F(400000, P_BI_TCXO, 12, 1, 4), 627 F(9600000, P_BI_TCXO, 2, 0, 0), 628 F(19200000, P_BI_TCXO, 1, 0, 0), 629 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 630 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 631 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 632 F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0), 633 { } 634 }; 635 636 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 637 .cmd_rcgr = 0x1400c, 638 .mnd_width = 8, 639 .hid_width = 5, 640 .parent_map = gcc_parent_map_10, 641 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 642 .clkr.hw.init = &(struct clk_init_data){ 643 .name = "gcc_sdcc2_apps_clk_src", 644 .parent_names = gcc_parent_names_10, 645 .num_parents = 5, 646 .ops = &clk_rcg2_ops, 647 }, 648 }; 649 650 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 651 F(400000, P_BI_TCXO, 12, 1, 4), 652 F(9600000, P_BI_TCXO, 2, 0, 0), 653 F(19200000, P_BI_TCXO, 1, 0, 0), 654 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 655 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 656 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 657 { } 658 }; 659 660 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 661 .cmd_rcgr = 0x1600c, 662 .mnd_width = 8, 663 .hid_width = 5, 664 .parent_map = gcc_parent_map_0, 665 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 666 .clkr.hw.init = &(struct clk_init_data){ 667 .name = "gcc_sdcc4_apps_clk_src", 668 .parent_names = gcc_parent_names_0, 669 .num_parents = 4, 670 .ops = &clk_rcg2_ops, 671 }, 672 }; 673 674 static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { 675 F(105495, P_BI_TCXO, 2, 1, 91), 676 { } 677 }; 678 679 static struct clk_rcg2 gcc_tsif_ref_clk_src = { 680 .cmd_rcgr = 0x36010, 681 .mnd_width = 8, 682 .hid_width = 5, 683 .parent_map = gcc_parent_map_6, 684 .freq_tbl = ftbl_gcc_tsif_ref_clk_src, 685 .clkr.hw.init = &(struct clk_init_data){ 686 .name = "gcc_tsif_ref_clk_src", 687 .parent_names = gcc_parent_names_6, 688 .num_parents = 5, 689 .ops = &clk_rcg2_ops, 690 }, 691 }; 692 693 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { 694 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 695 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 696 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 697 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 698 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 699 { } 700 }; 701 702 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { 703 .cmd_rcgr = 0x7501c, 704 .mnd_width = 8, 705 .hid_width = 5, 706 .parent_map = gcc_parent_map_0, 707 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, 708 .clkr.hw.init = &(struct clk_init_data){ 709 .name = "gcc_ufs_card_axi_clk_src", 710 .parent_names = gcc_parent_names_0, 711 .num_parents = 4, 712 .ops = &clk_rcg2_shared_ops, 713 }, 714 }; 715 716 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { 717 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 718 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 719 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 720 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 721 { } 722 }; 723 724 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { 725 .cmd_rcgr = 0x7505c, 726 .mnd_width = 0, 727 .hid_width = 5, 728 .parent_map = gcc_parent_map_0, 729 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 730 .clkr.hw.init = &(struct clk_init_data){ 731 .name = "gcc_ufs_card_ice_core_clk_src", 732 .parent_names = gcc_parent_names_0, 733 .num_parents = 4, 734 .ops = &clk_rcg2_shared_ops, 735 }, 736 }; 737 738 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { 739 .cmd_rcgr = 0x75090, 740 .mnd_width = 0, 741 .hid_width = 5, 742 .parent_map = gcc_parent_map_4, 743 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, 744 .clkr.hw.init = &(struct clk_init_data){ 745 .name = "gcc_ufs_card_phy_aux_clk_src", 746 .parent_names = gcc_parent_names_4, 747 .num_parents = 2, 748 .ops = &clk_rcg2_ops, 749 }, 750 }; 751 752 static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { 753 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 754 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 755 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 756 { } 757 }; 758 759 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { 760 .cmd_rcgr = 0x75074, 761 .mnd_width = 0, 762 .hid_width = 5, 763 .parent_map = gcc_parent_map_0, 764 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, 765 .clkr.hw.init = &(struct clk_init_data){ 766 .name = "gcc_ufs_card_unipro_core_clk_src", 767 .parent_names = gcc_parent_names_0, 768 .num_parents = 4, 769 .ops = &clk_rcg2_shared_ops, 770 }, 771 }; 772 773 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 774 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 775 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 776 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 777 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 778 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 779 { } 780 }; 781 782 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 783 .cmd_rcgr = 0x7701c, 784 .mnd_width = 8, 785 .hid_width = 5, 786 .parent_map = gcc_parent_map_0, 787 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 788 .clkr.hw.init = &(struct clk_init_data){ 789 .name = "gcc_ufs_phy_axi_clk_src", 790 .parent_names = gcc_parent_names_0, 791 .num_parents = 4, 792 .ops = &clk_rcg2_shared_ops, 793 }, 794 }; 795 796 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 797 .cmd_rcgr = 0x7705c, 798 .mnd_width = 0, 799 .hid_width = 5, 800 .parent_map = gcc_parent_map_0, 801 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 802 .clkr.hw.init = &(struct clk_init_data){ 803 .name = "gcc_ufs_phy_ice_core_clk_src", 804 .parent_names = gcc_parent_names_0, 805 .num_parents = 4, 806 .ops = &clk_rcg2_shared_ops, 807 }, 808 }; 809 810 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 811 .cmd_rcgr = 0x77090, 812 .mnd_width = 0, 813 .hid_width = 5, 814 .parent_map = gcc_parent_map_4, 815 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 816 .clkr.hw.init = &(struct clk_init_data){ 817 .name = "gcc_ufs_phy_phy_aux_clk_src", 818 .parent_names = gcc_parent_names_4, 819 .num_parents = 2, 820 .ops = &clk_rcg2_shared_ops, 821 }, 822 }; 823 824 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 825 .cmd_rcgr = 0x77074, 826 .mnd_width = 0, 827 .hid_width = 5, 828 .parent_map = gcc_parent_map_0, 829 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, 830 .clkr.hw.init = &(struct clk_init_data){ 831 .name = "gcc_ufs_phy_unipro_core_clk_src", 832 .parent_names = gcc_parent_names_0, 833 .num_parents = 4, 834 .ops = &clk_rcg2_shared_ops, 835 }, 836 }; 837 838 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 839 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), 840 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), 841 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 842 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 843 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 844 { } 845 }; 846 847 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 848 .cmd_rcgr = 0xf018, 849 .mnd_width = 8, 850 .hid_width = 5, 851 .parent_map = gcc_parent_map_0, 852 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 853 .clkr.hw.init = &(struct clk_init_data){ 854 .name = "gcc_usb30_prim_master_clk_src", 855 .parent_names = gcc_parent_names_0, 856 .num_parents = 4, 857 .ops = &clk_rcg2_shared_ops, 858 }, 859 }; 860 861 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 862 F(19200000, P_BI_TCXO, 1, 0, 0), 863 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), 864 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0), 865 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 866 { } 867 }; 868 869 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 870 .cmd_rcgr = 0xf030, 871 .mnd_width = 0, 872 .hid_width = 5, 873 .parent_map = gcc_parent_map_0, 874 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 875 .clkr.hw.init = &(struct clk_init_data){ 876 .name = "gcc_usb30_prim_mock_utmi_clk_src", 877 .parent_names = gcc_parent_names_0, 878 .num_parents = 4, 879 .ops = &clk_rcg2_shared_ops, 880 }, 881 }; 882 883 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { 884 .cmd_rcgr = 0x10018, 885 .mnd_width = 8, 886 .hid_width = 5, 887 .parent_map = gcc_parent_map_0, 888 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 889 .clkr.hw.init = &(struct clk_init_data){ 890 .name = "gcc_usb30_sec_master_clk_src", 891 .parent_names = gcc_parent_names_0, 892 .num_parents = 4, 893 .ops = &clk_rcg2_ops, 894 }, 895 }; 896 897 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { 898 .cmd_rcgr = 0x10030, 899 .mnd_width = 0, 900 .hid_width = 5, 901 .parent_map = gcc_parent_map_0, 902 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 903 .clkr.hw.init = &(struct clk_init_data){ 904 .name = "gcc_usb30_sec_mock_utmi_clk_src", 905 .parent_names = gcc_parent_names_0, 906 .num_parents = 4, 907 .ops = &clk_rcg2_ops, 908 }, 909 }; 910 911 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 912 .cmd_rcgr = 0xf05c, 913 .mnd_width = 0, 914 .hid_width = 5, 915 .parent_map = gcc_parent_map_2, 916 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, 917 .clkr.hw.init = &(struct clk_init_data){ 918 .name = "gcc_usb3_prim_phy_aux_clk_src", 919 .parent_names = gcc_parent_names_2, 920 .num_parents = 3, 921 .ops = &clk_rcg2_ops, 922 }, 923 }; 924 925 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { 926 .cmd_rcgr = 0x1005c, 927 .mnd_width = 0, 928 .hid_width = 5, 929 .parent_map = gcc_parent_map_2, 930 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, 931 .clkr.hw.init = &(struct clk_init_data){ 932 .name = "gcc_usb3_sec_phy_aux_clk_src", 933 .parent_names = gcc_parent_names_2, 934 .num_parents = 3, 935 .ops = &clk_rcg2_shared_ops, 936 }, 937 }; 938 939 static struct clk_rcg2 gcc_vs_ctrl_clk_src = { 940 .cmd_rcgr = 0x7a030, 941 .mnd_width = 0, 942 .hid_width = 5, 943 .parent_map = gcc_parent_map_3, 944 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, 945 .clkr.hw.init = &(struct clk_init_data){ 946 .name = "gcc_vs_ctrl_clk_src", 947 .parent_names = gcc_parent_names_3, 948 .num_parents = 3, 949 .ops = &clk_rcg2_ops, 950 }, 951 }; 952 953 static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = { 954 F(19200000, P_BI_TCXO, 1, 0, 0), 955 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 956 F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0), 957 { } 958 }; 959 960 static struct clk_rcg2 gcc_vsensor_clk_src = { 961 .cmd_rcgr = 0x7a018, 962 .mnd_width = 0, 963 .hid_width = 5, 964 .parent_map = gcc_parent_map_3, 965 .freq_tbl = ftbl_gcc_vsensor_clk_src, 966 .clkr.hw.init = &(struct clk_init_data){ 967 .name = "gcc_vsensor_clk_src", 968 .parent_names = gcc_parent_names_8, 969 .num_parents = 3, 970 .ops = &clk_rcg2_ops, 971 }, 972 }; 973 974 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { 975 .halt_reg = 0x90014, 976 .halt_check = BRANCH_HALT, 977 .clkr = { 978 .enable_reg = 0x90014, 979 .enable_mask = BIT(0), 980 .hw.init = &(struct clk_init_data){ 981 .name = "gcc_aggre_noc_pcie_tbu_clk", 982 .ops = &clk_branch2_ops, 983 }, 984 }, 985 }; 986 987 static struct clk_branch gcc_aggre_ufs_card_axi_clk = { 988 .halt_reg = 0x82028, 989 .halt_check = BRANCH_HALT, 990 .hwcg_reg = 0x82028, 991 .hwcg_bit = 1, 992 .clkr = { 993 .enable_reg = 0x82028, 994 .enable_mask = BIT(0), 995 .hw.init = &(struct clk_init_data){ 996 .name = "gcc_aggre_ufs_card_axi_clk", 997 .parent_names = (const char *[]){ 998 "gcc_ufs_card_axi_clk_src", 999 }, 1000 .num_parents = 1, 1001 .flags = CLK_SET_RATE_PARENT, 1002 .ops = &clk_branch2_ops, 1003 }, 1004 }, 1005 }; 1006 1007 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1008 .halt_reg = 0x82024, 1009 .halt_check = BRANCH_HALT, 1010 .hwcg_reg = 0x82024, 1011 .hwcg_bit = 1, 1012 .clkr = { 1013 .enable_reg = 0x82024, 1014 .enable_mask = BIT(0), 1015 .hw.init = &(struct clk_init_data){ 1016 .name = "gcc_aggre_ufs_phy_axi_clk", 1017 .parent_names = (const char *[]){ 1018 "gcc_ufs_phy_axi_clk_src", 1019 }, 1020 .num_parents = 1, 1021 .flags = CLK_SET_RATE_PARENT, 1022 .ops = &clk_branch2_ops, 1023 }, 1024 }, 1025 }; 1026 1027 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1028 .halt_reg = 0x8201c, 1029 .halt_check = BRANCH_HALT, 1030 .clkr = { 1031 .enable_reg = 0x8201c, 1032 .enable_mask = BIT(0), 1033 .hw.init = &(struct clk_init_data){ 1034 .name = "gcc_aggre_usb3_prim_axi_clk", 1035 .parent_names = (const char *[]){ 1036 "gcc_usb30_prim_master_clk_src", 1037 }, 1038 .num_parents = 1, 1039 .flags = CLK_SET_RATE_PARENT, 1040 .ops = &clk_branch2_ops, 1041 }, 1042 }, 1043 }; 1044 1045 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { 1046 .halt_reg = 0x82020, 1047 .halt_check = BRANCH_HALT, 1048 .clkr = { 1049 .enable_reg = 0x82020, 1050 .enable_mask = BIT(0), 1051 .hw.init = &(struct clk_init_data){ 1052 .name = "gcc_aggre_usb3_sec_axi_clk", 1053 .parent_names = (const char *[]){ 1054 "gcc_usb30_sec_master_clk_src", 1055 }, 1056 .num_parents = 1, 1057 .flags = CLK_SET_RATE_PARENT, 1058 .ops = &clk_branch2_ops, 1059 }, 1060 }, 1061 }; 1062 1063 static struct clk_branch gcc_apc_vs_clk = { 1064 .halt_reg = 0x7a050, 1065 .halt_check = BRANCH_HALT, 1066 .clkr = { 1067 .enable_reg = 0x7a050, 1068 .enable_mask = BIT(0), 1069 .hw.init = &(struct clk_init_data){ 1070 .name = "gcc_apc_vs_clk", 1071 .parent_names = (const char *[]){ 1072 "gcc_vsensor_clk_src", 1073 }, 1074 .num_parents = 1, 1075 .flags = CLK_SET_RATE_PARENT, 1076 .ops = &clk_branch2_ops, 1077 }, 1078 }, 1079 }; 1080 1081 static struct clk_branch gcc_boot_rom_ahb_clk = { 1082 .halt_reg = 0x38004, 1083 .halt_check = BRANCH_HALT_VOTED, 1084 .hwcg_reg = 0x38004, 1085 .hwcg_bit = 1, 1086 .clkr = { 1087 .enable_reg = 0x52004, 1088 .enable_mask = BIT(10), 1089 .hw.init = &(struct clk_init_data){ 1090 .name = "gcc_boot_rom_ahb_clk", 1091 .ops = &clk_branch2_ops, 1092 }, 1093 }, 1094 }; 1095 1096 static struct clk_branch gcc_camera_ahb_clk = { 1097 .halt_reg = 0xb008, 1098 .halt_check = BRANCH_HALT, 1099 .hwcg_reg = 0xb008, 1100 .hwcg_bit = 1, 1101 .clkr = { 1102 .enable_reg = 0xb008, 1103 .enable_mask = BIT(0), 1104 .hw.init = &(struct clk_init_data){ 1105 .name = "gcc_camera_ahb_clk", 1106 .ops = &clk_branch2_ops, 1107 }, 1108 }, 1109 }; 1110 1111 static struct clk_branch gcc_camera_axi_clk = { 1112 .halt_reg = 0xb020, 1113 .halt_check = BRANCH_VOTED, 1114 .clkr = { 1115 .enable_reg = 0xb020, 1116 .enable_mask = BIT(0), 1117 .hw.init = &(struct clk_init_data){ 1118 .name = "gcc_camera_axi_clk", 1119 .ops = &clk_branch2_ops, 1120 }, 1121 }, 1122 }; 1123 1124 static struct clk_branch gcc_camera_xo_clk = { 1125 .halt_reg = 0xb02c, 1126 .halt_check = BRANCH_HALT, 1127 .clkr = { 1128 .enable_reg = 0xb02c, 1129 .enable_mask = BIT(0), 1130 .hw.init = &(struct clk_init_data){ 1131 .name = "gcc_camera_xo_clk", 1132 .ops = &clk_branch2_ops, 1133 }, 1134 }, 1135 }; 1136 1137 static struct clk_branch gcc_ce1_ahb_clk = { 1138 .halt_reg = 0x4100c, 1139 .halt_check = BRANCH_HALT_VOTED, 1140 .hwcg_reg = 0x4100c, 1141 .hwcg_bit = 1, 1142 .clkr = { 1143 .enable_reg = 0x52004, 1144 .enable_mask = BIT(3), 1145 .hw.init = &(struct clk_init_data){ 1146 .name = "gcc_ce1_ahb_clk", 1147 .ops = &clk_branch2_ops, 1148 }, 1149 }, 1150 }; 1151 1152 static struct clk_branch gcc_ce1_axi_clk = { 1153 .halt_reg = 0x41008, 1154 .halt_check = BRANCH_HALT_VOTED, 1155 .clkr = { 1156 .enable_reg = 0x52004, 1157 .enable_mask = BIT(4), 1158 .hw.init = &(struct clk_init_data){ 1159 .name = "gcc_ce1_axi_clk", 1160 .ops = &clk_branch2_ops, 1161 }, 1162 }, 1163 }; 1164 1165 static struct clk_branch gcc_ce1_clk = { 1166 .halt_reg = 0x41004, 1167 .halt_check = BRANCH_HALT_VOTED, 1168 .clkr = { 1169 .enable_reg = 0x52004, 1170 .enable_mask = BIT(5), 1171 .hw.init = &(struct clk_init_data){ 1172 .name = "gcc_ce1_clk", 1173 .ops = &clk_branch2_ops, 1174 }, 1175 }, 1176 }; 1177 1178 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1179 .halt_reg = 0x502c, 1180 .halt_check = BRANCH_HALT, 1181 .clkr = { 1182 .enable_reg = 0x502c, 1183 .enable_mask = BIT(0), 1184 .hw.init = &(struct clk_init_data){ 1185 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1186 .parent_names = (const char *[]){ 1187 "gcc_usb30_prim_master_clk_src", 1188 }, 1189 .num_parents = 1, 1190 .flags = CLK_SET_RATE_PARENT, 1191 .ops = &clk_branch2_ops, 1192 }, 1193 }, 1194 }; 1195 1196 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { 1197 .halt_reg = 0x5030, 1198 .halt_check = BRANCH_HALT, 1199 .clkr = { 1200 .enable_reg = 0x5030, 1201 .enable_mask = BIT(0), 1202 .hw.init = &(struct clk_init_data){ 1203 .name = "gcc_cfg_noc_usb3_sec_axi_clk", 1204 .parent_names = (const char *[]){ 1205 "gcc_usb30_sec_master_clk_src", 1206 }, 1207 .num_parents = 1, 1208 .flags = CLK_SET_RATE_PARENT, 1209 .ops = &clk_branch2_ops, 1210 }, 1211 }, 1212 }; 1213 1214 static struct clk_branch gcc_cpuss_ahb_clk = { 1215 .halt_reg = 0x48000, 1216 .halt_check = BRANCH_HALT_VOTED, 1217 .clkr = { 1218 .enable_reg = 0x52004, 1219 .enable_mask = BIT(21), 1220 .hw.init = &(struct clk_init_data){ 1221 .name = "gcc_cpuss_ahb_clk", 1222 .parent_names = (const char *[]){ 1223 "gcc_cpuss_ahb_clk_src", 1224 }, 1225 .num_parents = 1, 1226 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1227 .ops = &clk_branch2_ops, 1228 }, 1229 }, 1230 }; 1231 1232 static struct clk_branch gcc_cpuss_rbcpr_clk = { 1233 .halt_reg = 0x48008, 1234 .halt_check = BRANCH_HALT, 1235 .clkr = { 1236 .enable_reg = 0x48008, 1237 .enable_mask = BIT(0), 1238 .hw.init = &(struct clk_init_data){ 1239 .name = "gcc_cpuss_rbcpr_clk", 1240 .parent_names = (const char *[]){ 1241 "gcc_cpuss_rbcpr_clk_src", 1242 }, 1243 .num_parents = 1, 1244 .flags = CLK_SET_RATE_PARENT, 1245 .ops = &clk_branch2_ops, 1246 }, 1247 }, 1248 }; 1249 1250 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1251 .halt_reg = 0x44038, 1252 .halt_check = BRANCH_VOTED, 1253 .clkr = { 1254 .enable_reg = 0x44038, 1255 .enable_mask = BIT(0), 1256 .hw.init = &(struct clk_init_data){ 1257 .name = "gcc_ddrss_gpu_axi_clk", 1258 .ops = &clk_branch2_ops, 1259 }, 1260 }, 1261 }; 1262 1263 static struct clk_branch gcc_disp_ahb_clk = { 1264 .halt_reg = 0xb00c, 1265 .halt_check = BRANCH_HALT, 1266 .hwcg_reg = 0xb00c, 1267 .hwcg_bit = 1, 1268 .clkr = { 1269 .enable_reg = 0xb00c, 1270 .enable_mask = BIT(0), 1271 .hw.init = &(struct clk_init_data){ 1272 .name = "gcc_disp_ahb_clk", 1273 .ops = &clk_branch2_ops, 1274 }, 1275 }, 1276 }; 1277 1278 static struct clk_branch gcc_disp_axi_clk = { 1279 .halt_reg = 0xb024, 1280 .halt_check = BRANCH_VOTED, 1281 .clkr = { 1282 .enable_reg = 0xb024, 1283 .enable_mask = BIT(0), 1284 .hw.init = &(struct clk_init_data){ 1285 .name = "gcc_disp_axi_clk", 1286 .ops = &clk_branch2_ops, 1287 }, 1288 }, 1289 }; 1290 1291 static struct clk_branch gcc_disp_gpll0_clk_src = { 1292 .halt_check = BRANCH_HALT_DELAY, 1293 .clkr = { 1294 .enable_reg = 0x52004, 1295 .enable_mask = BIT(18), 1296 .hw.init = &(struct clk_init_data){ 1297 .name = "gcc_disp_gpll0_clk_src", 1298 .parent_names = (const char *[]){ 1299 "gpll0", 1300 }, 1301 .num_parents = 1, 1302 .ops = &clk_branch2_ops, 1303 }, 1304 }, 1305 }; 1306 1307 static struct clk_branch gcc_disp_gpll0_div_clk_src = { 1308 .halt_check = BRANCH_HALT_DELAY, 1309 .clkr = { 1310 .enable_reg = 0x52004, 1311 .enable_mask = BIT(19), 1312 .hw.init = &(struct clk_init_data){ 1313 .name = "gcc_disp_gpll0_div_clk_src", 1314 .parent_names = (const char *[]){ 1315 "gpll0_out_even", 1316 }, 1317 .num_parents = 1, 1318 .ops = &clk_branch2_ops, 1319 }, 1320 }, 1321 }; 1322 1323 static struct clk_branch gcc_disp_xo_clk = { 1324 .halt_reg = 0xb030, 1325 .halt_check = BRANCH_HALT, 1326 .clkr = { 1327 .enable_reg = 0xb030, 1328 .enable_mask = BIT(0), 1329 .hw.init = &(struct clk_init_data){ 1330 .name = "gcc_disp_xo_clk", 1331 .ops = &clk_branch2_ops, 1332 }, 1333 }, 1334 }; 1335 1336 static struct clk_branch gcc_gp1_clk = { 1337 .halt_reg = 0x64000, 1338 .halt_check = BRANCH_HALT, 1339 .clkr = { 1340 .enable_reg = 0x64000, 1341 .enable_mask = BIT(0), 1342 .hw.init = &(struct clk_init_data){ 1343 .name = "gcc_gp1_clk", 1344 .parent_names = (const char *[]){ 1345 "gcc_gp1_clk_src", 1346 }, 1347 .num_parents = 1, 1348 .flags = CLK_SET_RATE_PARENT, 1349 .ops = &clk_branch2_ops, 1350 }, 1351 }, 1352 }; 1353 1354 static struct clk_branch gcc_gp2_clk = { 1355 .halt_reg = 0x65000, 1356 .halt_check = BRANCH_HALT, 1357 .clkr = { 1358 .enable_reg = 0x65000, 1359 .enable_mask = BIT(0), 1360 .hw.init = &(struct clk_init_data){ 1361 .name = "gcc_gp2_clk", 1362 .parent_names = (const char *[]){ 1363 "gcc_gp2_clk_src", 1364 }, 1365 .num_parents = 1, 1366 .flags = CLK_SET_RATE_PARENT, 1367 .ops = &clk_branch2_ops, 1368 }, 1369 }, 1370 }; 1371 1372 static struct clk_branch gcc_gp3_clk = { 1373 .halt_reg = 0x66000, 1374 .halt_check = BRANCH_HALT, 1375 .clkr = { 1376 .enable_reg = 0x66000, 1377 .enable_mask = BIT(0), 1378 .hw.init = &(struct clk_init_data){ 1379 .name = "gcc_gp3_clk", 1380 .parent_names = (const char *[]){ 1381 "gcc_gp3_clk_src", 1382 }, 1383 .num_parents = 1, 1384 .flags = CLK_SET_RATE_PARENT, 1385 .ops = &clk_branch2_ops, 1386 }, 1387 }, 1388 }; 1389 1390 static struct clk_branch gcc_gpu_cfg_ahb_clk = { 1391 .halt_reg = 0x71004, 1392 .halt_check = BRANCH_HALT, 1393 .hwcg_reg = 0x71004, 1394 .hwcg_bit = 1, 1395 .clkr = { 1396 .enable_reg = 0x71004, 1397 .enable_mask = BIT(0), 1398 .hw.init = &(struct clk_init_data){ 1399 .name = "gcc_gpu_cfg_ahb_clk", 1400 .ops = &clk_branch2_ops, 1401 }, 1402 }, 1403 }; 1404 1405 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1406 .halt_check = BRANCH_HALT_DELAY, 1407 .clkr = { 1408 .enable_reg = 0x52004, 1409 .enable_mask = BIT(15), 1410 .hw.init = &(struct clk_init_data){ 1411 .name = "gcc_gpu_gpll0_clk_src", 1412 .parent_names = (const char *[]){ 1413 "gpll0", 1414 }, 1415 .num_parents = 1, 1416 .ops = &clk_branch2_ops, 1417 }, 1418 }, 1419 }; 1420 1421 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1422 .halt_check = BRANCH_HALT_DELAY, 1423 .clkr = { 1424 .enable_reg = 0x52004, 1425 .enable_mask = BIT(16), 1426 .hw.init = &(struct clk_init_data){ 1427 .name = "gcc_gpu_gpll0_div_clk_src", 1428 .parent_names = (const char *[]){ 1429 "gpll0_out_even", 1430 }, 1431 .num_parents = 1, 1432 .ops = &clk_branch2_ops, 1433 }, 1434 }, 1435 }; 1436 1437 static struct clk_branch gcc_gpu_iref_clk = { 1438 .halt_reg = 0x8c010, 1439 .halt_check = BRANCH_HALT, 1440 .clkr = { 1441 .enable_reg = 0x8c010, 1442 .enable_mask = BIT(0), 1443 .hw.init = &(struct clk_init_data){ 1444 .name = "gcc_gpu_iref_clk", 1445 .ops = &clk_branch2_ops, 1446 }, 1447 }, 1448 }; 1449 1450 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1451 .halt_reg = 0x7100c, 1452 .halt_check = BRANCH_VOTED, 1453 .clkr = { 1454 .enable_reg = 0x7100c, 1455 .enable_mask = BIT(0), 1456 .hw.init = &(struct clk_init_data){ 1457 .name = "gcc_gpu_memnoc_gfx_clk", 1458 .ops = &clk_branch2_ops, 1459 }, 1460 }, 1461 }; 1462 1463 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1464 .halt_reg = 0x71018, 1465 .halt_check = BRANCH_HALT, 1466 .clkr = { 1467 .enable_reg = 0x71018, 1468 .enable_mask = BIT(0), 1469 .hw.init = &(struct clk_init_data){ 1470 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1471 .ops = &clk_branch2_ops, 1472 }, 1473 }, 1474 }; 1475 1476 static struct clk_branch gcc_gpu_vs_clk = { 1477 .halt_reg = 0x7a04c, 1478 .halt_check = BRANCH_HALT, 1479 .clkr = { 1480 .enable_reg = 0x7a04c, 1481 .enable_mask = BIT(0), 1482 .hw.init = &(struct clk_init_data){ 1483 .name = "gcc_gpu_vs_clk", 1484 .parent_names = (const char *[]){ 1485 "gcc_vsensor_clk_src", 1486 }, 1487 .num_parents = 1, 1488 .flags = CLK_SET_RATE_PARENT, 1489 .ops = &clk_branch2_ops, 1490 }, 1491 }, 1492 }; 1493 1494 static struct clk_branch gcc_mss_axis2_clk = { 1495 .halt_reg = 0x8a008, 1496 .halt_check = BRANCH_HALT, 1497 .clkr = { 1498 .enable_reg = 0x8a008, 1499 .enable_mask = BIT(0), 1500 .hw.init = &(struct clk_init_data){ 1501 .name = "gcc_mss_axis2_clk", 1502 .ops = &clk_branch2_ops, 1503 }, 1504 }, 1505 }; 1506 1507 static struct clk_branch gcc_mss_cfg_ahb_clk = { 1508 .halt_reg = 0x8a000, 1509 .halt_check = BRANCH_HALT, 1510 .hwcg_reg = 0x8a000, 1511 .hwcg_bit = 1, 1512 .clkr = { 1513 .enable_reg = 0x8a000, 1514 .enable_mask = BIT(0), 1515 .hw.init = &(struct clk_init_data){ 1516 .name = "gcc_mss_cfg_ahb_clk", 1517 .ops = &clk_branch2_ops, 1518 }, 1519 }, 1520 }; 1521 1522 static struct clk_branch gcc_mss_gpll0_div_clk_src = { 1523 .halt_check = BRANCH_HALT_DELAY, 1524 .clkr = { 1525 .enable_reg = 0x52004, 1526 .enable_mask = BIT(17), 1527 .hw.init = &(struct clk_init_data){ 1528 .name = "gcc_mss_gpll0_div_clk_src", 1529 .ops = &clk_branch2_ops, 1530 }, 1531 }, 1532 }; 1533 1534 static struct clk_branch gcc_mss_mfab_axis_clk = { 1535 .halt_reg = 0x8a004, 1536 .halt_check = BRANCH_VOTED, 1537 .hwcg_reg = 0x8a004, 1538 .hwcg_bit = 1, 1539 .clkr = { 1540 .enable_reg = 0x8a004, 1541 .enable_mask = BIT(0), 1542 .hw.init = &(struct clk_init_data){ 1543 .name = "gcc_mss_mfab_axis_clk", 1544 .ops = &clk_branch2_ops, 1545 }, 1546 }, 1547 }; 1548 1549 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = { 1550 .halt_reg = 0x8a154, 1551 .halt_check = BRANCH_VOTED, 1552 .clkr = { 1553 .enable_reg = 0x8a154, 1554 .enable_mask = BIT(0), 1555 .hw.init = &(struct clk_init_data){ 1556 .name = "gcc_mss_q6_memnoc_axi_clk", 1557 .ops = &clk_branch2_ops, 1558 }, 1559 }, 1560 }; 1561 1562 static struct clk_branch gcc_mss_snoc_axi_clk = { 1563 .halt_reg = 0x8a150, 1564 .halt_check = BRANCH_HALT, 1565 .clkr = { 1566 .enable_reg = 0x8a150, 1567 .enable_mask = BIT(0), 1568 .hw.init = &(struct clk_init_data){ 1569 .name = "gcc_mss_snoc_axi_clk", 1570 .ops = &clk_branch2_ops, 1571 }, 1572 }, 1573 }; 1574 1575 static struct clk_branch gcc_mss_vs_clk = { 1576 .halt_reg = 0x7a048, 1577 .halt_check = BRANCH_HALT, 1578 .clkr = { 1579 .enable_reg = 0x7a048, 1580 .enable_mask = BIT(0), 1581 .hw.init = &(struct clk_init_data){ 1582 .name = "gcc_mss_vs_clk", 1583 .parent_names = (const char *[]){ 1584 "gcc_vsensor_clk_src", 1585 }, 1586 .num_parents = 1, 1587 .flags = CLK_SET_RATE_PARENT, 1588 .ops = &clk_branch2_ops, 1589 }, 1590 }, 1591 }; 1592 1593 static struct clk_branch gcc_pcie_0_aux_clk = { 1594 .halt_reg = 0x6b01c, 1595 .halt_check = BRANCH_HALT_VOTED, 1596 .clkr = { 1597 .enable_reg = 0x5200c, 1598 .enable_mask = BIT(3), 1599 .hw.init = &(struct clk_init_data){ 1600 .name = "gcc_pcie_0_aux_clk", 1601 .parent_names = (const char *[]){ 1602 "gcc_pcie_0_aux_clk_src", 1603 }, 1604 .num_parents = 1, 1605 .flags = CLK_SET_RATE_PARENT, 1606 .ops = &clk_branch2_ops, 1607 }, 1608 }, 1609 }; 1610 1611 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1612 .halt_reg = 0x6b018, 1613 .halt_check = BRANCH_HALT_VOTED, 1614 .hwcg_reg = 0x6b018, 1615 .hwcg_bit = 1, 1616 .clkr = { 1617 .enable_reg = 0x5200c, 1618 .enable_mask = BIT(2), 1619 .hw.init = &(struct clk_init_data){ 1620 .name = "gcc_pcie_0_cfg_ahb_clk", 1621 .ops = &clk_branch2_ops, 1622 }, 1623 }, 1624 }; 1625 1626 static struct clk_branch gcc_pcie_0_clkref_clk = { 1627 .halt_reg = 0x8c00c, 1628 .halt_check = BRANCH_HALT, 1629 .clkr = { 1630 .enable_reg = 0x8c00c, 1631 .enable_mask = BIT(0), 1632 .hw.init = &(struct clk_init_data){ 1633 .name = "gcc_pcie_0_clkref_clk", 1634 .ops = &clk_branch2_ops, 1635 }, 1636 }, 1637 }; 1638 1639 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1640 .halt_reg = 0x6b014, 1641 .halt_check = BRANCH_HALT_VOTED, 1642 .clkr = { 1643 .enable_reg = 0x5200c, 1644 .enable_mask = BIT(1), 1645 .hw.init = &(struct clk_init_data){ 1646 .name = "gcc_pcie_0_mstr_axi_clk", 1647 .ops = &clk_branch2_ops, 1648 }, 1649 }, 1650 }; 1651 1652 static struct clk_branch gcc_pcie_0_pipe_clk = { 1653 .halt_check = BRANCH_HALT_SKIP, 1654 .clkr = { 1655 .enable_reg = 0x5200c, 1656 .enable_mask = BIT(4), 1657 .hw.init = &(struct clk_init_data){ 1658 .name = "gcc_pcie_0_pipe_clk", 1659 .ops = &clk_branch2_ops, 1660 }, 1661 }, 1662 }; 1663 1664 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1665 .halt_reg = 0x6b010, 1666 .halt_check = BRANCH_HALT_VOTED, 1667 .hwcg_reg = 0x6b010, 1668 .hwcg_bit = 1, 1669 .clkr = { 1670 .enable_reg = 0x5200c, 1671 .enable_mask = BIT(0), 1672 .hw.init = &(struct clk_init_data){ 1673 .name = "gcc_pcie_0_slv_axi_clk", 1674 .ops = &clk_branch2_ops, 1675 }, 1676 }, 1677 }; 1678 1679 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1680 .halt_reg = 0x6b00c, 1681 .halt_check = BRANCH_HALT_VOTED, 1682 .clkr = { 1683 .enable_reg = 0x5200c, 1684 .enable_mask = BIT(5), 1685 .hw.init = &(struct clk_init_data){ 1686 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1687 .ops = &clk_branch2_ops, 1688 }, 1689 }, 1690 }; 1691 1692 static struct clk_branch gcc_pcie_1_aux_clk = { 1693 .halt_reg = 0x8d01c, 1694 .halt_check = BRANCH_HALT_VOTED, 1695 .clkr = { 1696 .enable_reg = 0x52004, 1697 .enable_mask = BIT(29), 1698 .hw.init = &(struct clk_init_data){ 1699 .name = "gcc_pcie_1_aux_clk", 1700 .parent_names = (const char *[]){ 1701 "gcc_pcie_1_aux_clk_src", 1702 }, 1703 .num_parents = 1, 1704 .flags = CLK_SET_RATE_PARENT, 1705 .ops = &clk_branch2_ops, 1706 }, 1707 }, 1708 }; 1709 1710 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1711 .halt_reg = 0x8d018, 1712 .halt_check = BRANCH_HALT_VOTED, 1713 .hwcg_reg = 0x8d018, 1714 .hwcg_bit = 1, 1715 .clkr = { 1716 .enable_reg = 0x52004, 1717 .enable_mask = BIT(28), 1718 .hw.init = &(struct clk_init_data){ 1719 .name = "gcc_pcie_1_cfg_ahb_clk", 1720 .ops = &clk_branch2_ops, 1721 }, 1722 }, 1723 }; 1724 1725 static struct clk_branch gcc_pcie_1_clkref_clk = { 1726 .halt_reg = 0x8c02c, 1727 .halt_check = BRANCH_HALT, 1728 .clkr = { 1729 .enable_reg = 0x8c02c, 1730 .enable_mask = BIT(0), 1731 .hw.init = &(struct clk_init_data){ 1732 .name = "gcc_pcie_1_clkref_clk", 1733 .ops = &clk_branch2_ops, 1734 }, 1735 }, 1736 }; 1737 1738 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1739 .halt_reg = 0x8d014, 1740 .halt_check = BRANCH_HALT_VOTED, 1741 .clkr = { 1742 .enable_reg = 0x52004, 1743 .enable_mask = BIT(27), 1744 .hw.init = &(struct clk_init_data){ 1745 .name = "gcc_pcie_1_mstr_axi_clk", 1746 .ops = &clk_branch2_ops, 1747 }, 1748 }, 1749 }; 1750 1751 static struct clk_branch gcc_pcie_1_pipe_clk = { 1752 .halt_check = BRANCH_HALT_SKIP, 1753 .clkr = { 1754 .enable_reg = 0x52004, 1755 .enable_mask = BIT(30), 1756 .hw.init = &(struct clk_init_data){ 1757 .name = "gcc_pcie_1_pipe_clk", 1758 .ops = &clk_branch2_ops, 1759 }, 1760 }, 1761 }; 1762 1763 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1764 .halt_reg = 0x8d010, 1765 .halt_check = BRANCH_HALT_VOTED, 1766 .hwcg_reg = 0x8d010, 1767 .hwcg_bit = 1, 1768 .clkr = { 1769 .enable_reg = 0x52004, 1770 .enable_mask = BIT(26), 1771 .hw.init = &(struct clk_init_data){ 1772 .name = "gcc_pcie_1_slv_axi_clk", 1773 .ops = &clk_branch2_ops, 1774 }, 1775 }, 1776 }; 1777 1778 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 1779 .halt_reg = 0x8d00c, 1780 .halt_check = BRANCH_HALT_VOTED, 1781 .clkr = { 1782 .enable_reg = 0x52004, 1783 .enable_mask = BIT(25), 1784 .hw.init = &(struct clk_init_data){ 1785 .name = "gcc_pcie_1_slv_q2a_axi_clk", 1786 .ops = &clk_branch2_ops, 1787 }, 1788 }, 1789 }; 1790 1791 static struct clk_branch gcc_pcie_phy_aux_clk = { 1792 .halt_reg = 0x6f004, 1793 .halt_check = BRANCH_HALT, 1794 .clkr = { 1795 .enable_reg = 0x6f004, 1796 .enable_mask = BIT(0), 1797 .hw.init = &(struct clk_init_data){ 1798 .name = "gcc_pcie_phy_aux_clk", 1799 .parent_names = (const char *[]){ 1800 "gcc_pcie_0_aux_clk_src", 1801 }, 1802 .num_parents = 1, 1803 .flags = CLK_SET_RATE_PARENT, 1804 .ops = &clk_branch2_ops, 1805 }, 1806 }, 1807 }; 1808 1809 static struct clk_branch gcc_pcie_phy_refgen_clk = { 1810 .halt_reg = 0x6f02c, 1811 .halt_check = BRANCH_HALT, 1812 .clkr = { 1813 .enable_reg = 0x6f02c, 1814 .enable_mask = BIT(0), 1815 .hw.init = &(struct clk_init_data){ 1816 .name = "gcc_pcie_phy_refgen_clk", 1817 .parent_names = (const char *[]){ 1818 "gcc_pcie_phy_refgen_clk_src", 1819 }, 1820 .num_parents = 1, 1821 .flags = CLK_SET_RATE_PARENT, 1822 .ops = &clk_branch2_ops, 1823 }, 1824 }, 1825 }; 1826 1827 static struct clk_branch gcc_pdm2_clk = { 1828 .halt_reg = 0x3300c, 1829 .halt_check = BRANCH_HALT, 1830 .clkr = { 1831 .enable_reg = 0x3300c, 1832 .enable_mask = BIT(0), 1833 .hw.init = &(struct clk_init_data){ 1834 .name = "gcc_pdm2_clk", 1835 .parent_names = (const char *[]){ 1836 "gcc_pdm2_clk_src", 1837 }, 1838 .num_parents = 1, 1839 .flags = CLK_SET_RATE_PARENT, 1840 .ops = &clk_branch2_ops, 1841 }, 1842 }, 1843 }; 1844 1845 static struct clk_branch gcc_pdm_ahb_clk = { 1846 .halt_reg = 0x33004, 1847 .halt_check = BRANCH_HALT, 1848 .hwcg_reg = 0x33004, 1849 .hwcg_bit = 1, 1850 .clkr = { 1851 .enable_reg = 0x33004, 1852 .enable_mask = BIT(0), 1853 .hw.init = &(struct clk_init_data){ 1854 .name = "gcc_pdm_ahb_clk", 1855 .ops = &clk_branch2_ops, 1856 }, 1857 }, 1858 }; 1859 1860 static struct clk_branch gcc_pdm_xo4_clk = { 1861 .halt_reg = 0x33008, 1862 .halt_check = BRANCH_HALT, 1863 .clkr = { 1864 .enable_reg = 0x33008, 1865 .enable_mask = BIT(0), 1866 .hw.init = &(struct clk_init_data){ 1867 .name = "gcc_pdm_xo4_clk", 1868 .ops = &clk_branch2_ops, 1869 }, 1870 }, 1871 }; 1872 1873 static struct clk_branch gcc_prng_ahb_clk = { 1874 .halt_reg = 0x34004, 1875 .halt_check = BRANCH_HALT_VOTED, 1876 .hwcg_reg = 0x34004, 1877 .hwcg_bit = 1, 1878 .clkr = { 1879 .enable_reg = 0x52004, 1880 .enable_mask = BIT(13), 1881 .hw.init = &(struct clk_init_data){ 1882 .name = "gcc_prng_ahb_clk", 1883 .ops = &clk_branch2_ops, 1884 }, 1885 }, 1886 }; 1887 1888 static struct clk_branch gcc_qmip_camera_ahb_clk = { 1889 .halt_reg = 0xb014, 1890 .halt_check = BRANCH_HALT, 1891 .hwcg_reg = 0xb014, 1892 .hwcg_bit = 1, 1893 .clkr = { 1894 .enable_reg = 0xb014, 1895 .enable_mask = BIT(0), 1896 .hw.init = &(struct clk_init_data){ 1897 .name = "gcc_qmip_camera_ahb_clk", 1898 .ops = &clk_branch2_ops, 1899 }, 1900 }, 1901 }; 1902 1903 static struct clk_branch gcc_qmip_disp_ahb_clk = { 1904 .halt_reg = 0xb018, 1905 .halt_check = BRANCH_HALT, 1906 .hwcg_reg = 0xb018, 1907 .hwcg_bit = 1, 1908 .clkr = { 1909 .enable_reg = 0xb018, 1910 .enable_mask = BIT(0), 1911 .hw.init = &(struct clk_init_data){ 1912 .name = "gcc_qmip_disp_ahb_clk", 1913 .ops = &clk_branch2_ops, 1914 }, 1915 }, 1916 }; 1917 1918 static struct clk_branch gcc_qmip_video_ahb_clk = { 1919 .halt_reg = 0xb010, 1920 .halt_check = BRANCH_HALT, 1921 .hwcg_reg = 0xb010, 1922 .hwcg_bit = 1, 1923 .clkr = { 1924 .enable_reg = 0xb010, 1925 .enable_mask = BIT(0), 1926 .hw.init = &(struct clk_init_data){ 1927 .name = "gcc_qmip_video_ahb_clk", 1928 .ops = &clk_branch2_ops, 1929 }, 1930 }, 1931 }; 1932 1933 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 1934 .halt_reg = 0x17030, 1935 .halt_check = BRANCH_HALT_VOTED, 1936 .clkr = { 1937 .enable_reg = 0x5200c, 1938 .enable_mask = BIT(10), 1939 .hw.init = &(struct clk_init_data){ 1940 .name = "gcc_qupv3_wrap0_s0_clk", 1941 .parent_names = (const char *[]){ 1942 "gcc_qupv3_wrap0_s0_clk_src", 1943 }, 1944 .num_parents = 1, 1945 .flags = CLK_SET_RATE_PARENT, 1946 .ops = &clk_branch2_ops, 1947 }, 1948 }, 1949 }; 1950 1951 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 1952 .halt_reg = 0x17160, 1953 .halt_check = BRANCH_HALT_VOTED, 1954 .clkr = { 1955 .enable_reg = 0x5200c, 1956 .enable_mask = BIT(11), 1957 .hw.init = &(struct clk_init_data){ 1958 .name = "gcc_qupv3_wrap0_s1_clk", 1959 .parent_names = (const char *[]){ 1960 "gcc_qupv3_wrap0_s1_clk_src", 1961 }, 1962 .num_parents = 1, 1963 .flags = CLK_SET_RATE_PARENT, 1964 .ops = &clk_branch2_ops, 1965 }, 1966 }, 1967 }; 1968 1969 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 1970 .halt_reg = 0x17290, 1971 .halt_check = BRANCH_HALT_VOTED, 1972 .clkr = { 1973 .enable_reg = 0x5200c, 1974 .enable_mask = BIT(12), 1975 .hw.init = &(struct clk_init_data){ 1976 .name = "gcc_qupv3_wrap0_s2_clk", 1977 .parent_names = (const char *[]){ 1978 "gcc_qupv3_wrap0_s2_clk_src", 1979 }, 1980 .num_parents = 1, 1981 .flags = CLK_SET_RATE_PARENT, 1982 .ops = &clk_branch2_ops, 1983 }, 1984 }, 1985 }; 1986 1987 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 1988 .halt_reg = 0x173c0, 1989 .halt_check = BRANCH_HALT_VOTED, 1990 .clkr = { 1991 .enable_reg = 0x5200c, 1992 .enable_mask = BIT(13), 1993 .hw.init = &(struct clk_init_data){ 1994 .name = "gcc_qupv3_wrap0_s3_clk", 1995 .parent_names = (const char *[]){ 1996 "gcc_qupv3_wrap0_s3_clk_src", 1997 }, 1998 .num_parents = 1, 1999 .flags = CLK_SET_RATE_PARENT, 2000 .ops = &clk_branch2_ops, 2001 }, 2002 }, 2003 }; 2004 2005 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2006 .halt_reg = 0x174f0, 2007 .halt_check = BRANCH_HALT_VOTED, 2008 .clkr = { 2009 .enable_reg = 0x5200c, 2010 .enable_mask = BIT(14), 2011 .hw.init = &(struct clk_init_data){ 2012 .name = "gcc_qupv3_wrap0_s4_clk", 2013 .parent_names = (const char *[]){ 2014 "gcc_qupv3_wrap0_s4_clk_src", 2015 }, 2016 .num_parents = 1, 2017 .flags = CLK_SET_RATE_PARENT, 2018 .ops = &clk_branch2_ops, 2019 }, 2020 }, 2021 }; 2022 2023 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2024 .halt_reg = 0x17620, 2025 .halt_check = BRANCH_HALT_VOTED, 2026 .clkr = { 2027 .enable_reg = 0x5200c, 2028 .enable_mask = BIT(15), 2029 .hw.init = &(struct clk_init_data){ 2030 .name = "gcc_qupv3_wrap0_s5_clk", 2031 .parent_names = (const char *[]){ 2032 "gcc_qupv3_wrap0_s5_clk_src", 2033 }, 2034 .num_parents = 1, 2035 .flags = CLK_SET_RATE_PARENT, 2036 .ops = &clk_branch2_ops, 2037 }, 2038 }, 2039 }; 2040 2041 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 2042 .halt_reg = 0x17750, 2043 .halt_check = BRANCH_HALT_VOTED, 2044 .clkr = { 2045 .enable_reg = 0x5200c, 2046 .enable_mask = BIT(16), 2047 .hw.init = &(struct clk_init_data){ 2048 .name = "gcc_qupv3_wrap0_s6_clk", 2049 .parent_names = (const char *[]){ 2050 "gcc_qupv3_wrap0_s6_clk_src", 2051 }, 2052 .num_parents = 1, 2053 .flags = CLK_SET_RATE_PARENT, 2054 .ops = &clk_branch2_ops, 2055 }, 2056 }, 2057 }; 2058 2059 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 2060 .halt_reg = 0x17880, 2061 .halt_check = BRANCH_HALT_VOTED, 2062 .clkr = { 2063 .enable_reg = 0x5200c, 2064 .enable_mask = BIT(17), 2065 .hw.init = &(struct clk_init_data){ 2066 .name = "gcc_qupv3_wrap0_s7_clk", 2067 .parent_names = (const char *[]){ 2068 "gcc_qupv3_wrap0_s7_clk_src", 2069 }, 2070 .num_parents = 1, 2071 .flags = CLK_SET_RATE_PARENT, 2072 .ops = &clk_branch2_ops, 2073 }, 2074 }, 2075 }; 2076 2077 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2078 .halt_reg = 0x18014, 2079 .halt_check = BRANCH_HALT_VOTED, 2080 .clkr = { 2081 .enable_reg = 0x5200c, 2082 .enable_mask = BIT(22), 2083 .hw.init = &(struct clk_init_data){ 2084 .name = "gcc_qupv3_wrap1_s0_clk", 2085 .parent_names = (const char *[]){ 2086 "gcc_qupv3_wrap1_s0_clk_src", 2087 }, 2088 .num_parents = 1, 2089 .flags = CLK_SET_RATE_PARENT, 2090 .ops = &clk_branch2_ops, 2091 }, 2092 }, 2093 }; 2094 2095 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2096 .halt_reg = 0x18144, 2097 .halt_check = BRANCH_HALT_VOTED, 2098 .clkr = { 2099 .enable_reg = 0x5200c, 2100 .enable_mask = BIT(23), 2101 .hw.init = &(struct clk_init_data){ 2102 .name = "gcc_qupv3_wrap1_s1_clk", 2103 .parent_names = (const char *[]){ 2104 "gcc_qupv3_wrap1_s1_clk_src", 2105 }, 2106 .num_parents = 1, 2107 .flags = CLK_SET_RATE_PARENT, 2108 .ops = &clk_branch2_ops, 2109 }, 2110 }, 2111 }; 2112 2113 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2114 .halt_reg = 0x18274, 2115 .halt_check = BRANCH_HALT_VOTED, 2116 .clkr = { 2117 .enable_reg = 0x5200c, 2118 .enable_mask = BIT(24), 2119 .hw.init = &(struct clk_init_data){ 2120 .name = "gcc_qupv3_wrap1_s2_clk", 2121 .parent_names = (const char *[]){ 2122 "gcc_qupv3_wrap1_s2_clk_src", 2123 }, 2124 .num_parents = 1, 2125 .flags = CLK_SET_RATE_PARENT, 2126 .ops = &clk_branch2_ops, 2127 }, 2128 }, 2129 }; 2130 2131 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2132 .halt_reg = 0x183a4, 2133 .halt_check = BRANCH_HALT_VOTED, 2134 .clkr = { 2135 .enable_reg = 0x5200c, 2136 .enable_mask = BIT(25), 2137 .hw.init = &(struct clk_init_data){ 2138 .name = "gcc_qupv3_wrap1_s3_clk", 2139 .parent_names = (const char *[]){ 2140 "gcc_qupv3_wrap1_s3_clk_src", 2141 }, 2142 .num_parents = 1, 2143 .flags = CLK_SET_RATE_PARENT, 2144 .ops = &clk_branch2_ops, 2145 }, 2146 }, 2147 }; 2148 2149 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2150 .halt_reg = 0x184d4, 2151 .halt_check = BRANCH_HALT_VOTED, 2152 .clkr = { 2153 .enable_reg = 0x5200c, 2154 .enable_mask = BIT(26), 2155 .hw.init = &(struct clk_init_data){ 2156 .name = "gcc_qupv3_wrap1_s4_clk", 2157 .parent_names = (const char *[]){ 2158 "gcc_qupv3_wrap1_s4_clk_src", 2159 }, 2160 .num_parents = 1, 2161 .flags = CLK_SET_RATE_PARENT, 2162 .ops = &clk_branch2_ops, 2163 }, 2164 }, 2165 }; 2166 2167 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2168 .halt_reg = 0x18604, 2169 .halt_check = BRANCH_HALT_VOTED, 2170 .clkr = { 2171 .enable_reg = 0x5200c, 2172 .enable_mask = BIT(27), 2173 .hw.init = &(struct clk_init_data){ 2174 .name = "gcc_qupv3_wrap1_s5_clk", 2175 .parent_names = (const char *[]){ 2176 "gcc_qupv3_wrap1_s5_clk_src", 2177 }, 2178 .num_parents = 1, 2179 .flags = CLK_SET_RATE_PARENT, 2180 .ops = &clk_branch2_ops, 2181 }, 2182 }, 2183 }; 2184 2185 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 2186 .halt_reg = 0x18734, 2187 .halt_check = BRANCH_HALT_VOTED, 2188 .clkr = { 2189 .enable_reg = 0x5200c, 2190 .enable_mask = BIT(28), 2191 .hw.init = &(struct clk_init_data){ 2192 .name = "gcc_qupv3_wrap1_s6_clk", 2193 .parent_names = (const char *[]){ 2194 "gcc_qupv3_wrap1_s6_clk_src", 2195 }, 2196 .num_parents = 1, 2197 .flags = CLK_SET_RATE_PARENT, 2198 .ops = &clk_branch2_ops, 2199 }, 2200 }, 2201 }; 2202 2203 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 2204 .halt_reg = 0x18864, 2205 .halt_check = BRANCH_HALT_VOTED, 2206 .clkr = { 2207 .enable_reg = 0x5200c, 2208 .enable_mask = BIT(29), 2209 .hw.init = &(struct clk_init_data){ 2210 .name = "gcc_qupv3_wrap1_s7_clk", 2211 .parent_names = (const char *[]){ 2212 "gcc_qupv3_wrap1_s7_clk_src", 2213 }, 2214 .num_parents = 1, 2215 .flags = CLK_SET_RATE_PARENT, 2216 .ops = &clk_branch2_ops, 2217 }, 2218 }, 2219 }; 2220 2221 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2222 .halt_reg = 0x17004, 2223 .halt_check = BRANCH_HALT_VOTED, 2224 .clkr = { 2225 .enable_reg = 0x5200c, 2226 .enable_mask = BIT(6), 2227 .hw.init = &(struct clk_init_data){ 2228 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2229 .ops = &clk_branch2_ops, 2230 }, 2231 }, 2232 }; 2233 2234 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2235 .halt_reg = 0x17008, 2236 .halt_check = BRANCH_HALT_VOTED, 2237 .hwcg_reg = 0x17008, 2238 .hwcg_bit = 1, 2239 .clkr = { 2240 .enable_reg = 0x5200c, 2241 .enable_mask = BIT(7), 2242 .hw.init = &(struct clk_init_data){ 2243 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2244 .ops = &clk_branch2_ops, 2245 }, 2246 }, 2247 }; 2248 2249 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2250 .halt_reg = 0x1800c, 2251 .halt_check = BRANCH_HALT_VOTED, 2252 .clkr = { 2253 .enable_reg = 0x5200c, 2254 .enable_mask = BIT(20), 2255 .hw.init = &(struct clk_init_data){ 2256 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2257 .ops = &clk_branch2_ops, 2258 }, 2259 }, 2260 }; 2261 2262 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2263 .halt_reg = 0x18010, 2264 .halt_check = BRANCH_HALT_VOTED, 2265 .hwcg_reg = 0x18010, 2266 .hwcg_bit = 1, 2267 .clkr = { 2268 .enable_reg = 0x5200c, 2269 .enable_mask = BIT(21), 2270 .hw.init = &(struct clk_init_data){ 2271 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2272 .ops = &clk_branch2_ops, 2273 }, 2274 }, 2275 }; 2276 2277 static struct clk_branch gcc_sdcc2_ahb_clk = { 2278 .halt_reg = 0x14008, 2279 .halt_check = BRANCH_HALT, 2280 .clkr = { 2281 .enable_reg = 0x14008, 2282 .enable_mask = BIT(0), 2283 .hw.init = &(struct clk_init_data){ 2284 .name = "gcc_sdcc2_ahb_clk", 2285 .ops = &clk_branch2_ops, 2286 }, 2287 }, 2288 }; 2289 2290 static struct clk_branch gcc_sdcc2_apps_clk = { 2291 .halt_reg = 0x14004, 2292 .halt_check = BRANCH_HALT, 2293 .clkr = { 2294 .enable_reg = 0x14004, 2295 .enable_mask = BIT(0), 2296 .hw.init = &(struct clk_init_data){ 2297 .name = "gcc_sdcc2_apps_clk", 2298 .parent_names = (const char *[]){ 2299 "gcc_sdcc2_apps_clk_src", 2300 }, 2301 .num_parents = 1, 2302 .flags = CLK_SET_RATE_PARENT, 2303 .ops = &clk_branch2_ops, 2304 }, 2305 }, 2306 }; 2307 2308 static struct clk_branch gcc_sdcc4_ahb_clk = { 2309 .halt_reg = 0x16008, 2310 .halt_check = BRANCH_HALT, 2311 .clkr = { 2312 .enable_reg = 0x16008, 2313 .enable_mask = BIT(0), 2314 .hw.init = &(struct clk_init_data){ 2315 .name = "gcc_sdcc4_ahb_clk", 2316 .ops = &clk_branch2_ops, 2317 }, 2318 }, 2319 }; 2320 2321 static struct clk_branch gcc_sdcc4_apps_clk = { 2322 .halt_reg = 0x16004, 2323 .halt_check = BRANCH_HALT, 2324 .clkr = { 2325 .enable_reg = 0x16004, 2326 .enable_mask = BIT(0), 2327 .hw.init = &(struct clk_init_data){ 2328 .name = "gcc_sdcc4_apps_clk", 2329 .parent_names = (const char *[]){ 2330 "gcc_sdcc4_apps_clk_src", 2331 }, 2332 .num_parents = 1, 2333 .flags = CLK_SET_RATE_PARENT, 2334 .ops = &clk_branch2_ops, 2335 }, 2336 }, 2337 }; 2338 2339 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 2340 .halt_reg = 0x414c, 2341 .halt_check = BRANCH_HALT_VOTED, 2342 .clkr = { 2343 .enable_reg = 0x52004, 2344 .enable_mask = BIT(0), 2345 .hw.init = &(struct clk_init_data){ 2346 .name = "gcc_sys_noc_cpuss_ahb_clk", 2347 .parent_names = (const char *[]){ 2348 "gcc_cpuss_ahb_clk_src", 2349 }, 2350 .num_parents = 1, 2351 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 2352 .ops = &clk_branch2_ops, 2353 }, 2354 }, 2355 }; 2356 2357 static struct clk_branch gcc_tsif_ahb_clk = { 2358 .halt_reg = 0x36004, 2359 .halt_check = BRANCH_HALT, 2360 .clkr = { 2361 .enable_reg = 0x36004, 2362 .enable_mask = BIT(0), 2363 .hw.init = &(struct clk_init_data){ 2364 .name = "gcc_tsif_ahb_clk", 2365 .ops = &clk_branch2_ops, 2366 }, 2367 }, 2368 }; 2369 2370 static struct clk_branch gcc_tsif_inactivity_timers_clk = { 2371 .halt_reg = 0x3600c, 2372 .halt_check = BRANCH_HALT, 2373 .clkr = { 2374 .enable_reg = 0x3600c, 2375 .enable_mask = BIT(0), 2376 .hw.init = &(struct clk_init_data){ 2377 .name = "gcc_tsif_inactivity_timers_clk", 2378 .ops = &clk_branch2_ops, 2379 }, 2380 }, 2381 }; 2382 2383 static struct clk_branch gcc_tsif_ref_clk = { 2384 .halt_reg = 0x36008, 2385 .halt_check = BRANCH_HALT, 2386 .clkr = { 2387 .enable_reg = 0x36008, 2388 .enable_mask = BIT(0), 2389 .hw.init = &(struct clk_init_data){ 2390 .name = "gcc_tsif_ref_clk", 2391 .parent_names = (const char *[]){ 2392 "gcc_tsif_ref_clk_src", 2393 }, 2394 .num_parents = 1, 2395 .flags = CLK_SET_RATE_PARENT, 2396 .ops = &clk_branch2_ops, 2397 }, 2398 }, 2399 }; 2400 2401 static struct clk_branch gcc_ufs_card_ahb_clk = { 2402 .halt_reg = 0x75010, 2403 .halt_check = BRANCH_HALT, 2404 .hwcg_reg = 0x75010, 2405 .hwcg_bit = 1, 2406 .clkr = { 2407 .enable_reg = 0x75010, 2408 .enable_mask = BIT(0), 2409 .hw.init = &(struct clk_init_data){ 2410 .name = "gcc_ufs_card_ahb_clk", 2411 .ops = &clk_branch2_ops, 2412 }, 2413 }, 2414 }; 2415 2416 static struct clk_branch gcc_ufs_card_axi_clk = { 2417 .halt_reg = 0x7500c, 2418 .halt_check = BRANCH_HALT, 2419 .hwcg_reg = 0x7500c, 2420 .hwcg_bit = 1, 2421 .clkr = { 2422 .enable_reg = 0x7500c, 2423 .enable_mask = BIT(0), 2424 .hw.init = &(struct clk_init_data){ 2425 .name = "gcc_ufs_card_axi_clk", 2426 .parent_names = (const char *[]){ 2427 "gcc_ufs_card_axi_clk_src", 2428 }, 2429 .num_parents = 1, 2430 .flags = CLK_SET_RATE_PARENT, 2431 .ops = &clk_branch2_ops, 2432 }, 2433 }, 2434 }; 2435 2436 static struct clk_branch gcc_ufs_card_clkref_clk = { 2437 .halt_reg = 0x8c004, 2438 .halt_check = BRANCH_HALT, 2439 .clkr = { 2440 .enable_reg = 0x8c004, 2441 .enable_mask = BIT(0), 2442 .hw.init = &(struct clk_init_data){ 2443 .name = "gcc_ufs_card_clkref_clk", 2444 .ops = &clk_branch2_ops, 2445 }, 2446 }, 2447 }; 2448 2449 static struct clk_branch gcc_ufs_card_ice_core_clk = { 2450 .halt_reg = 0x75058, 2451 .halt_check = BRANCH_HALT, 2452 .hwcg_reg = 0x75058, 2453 .hwcg_bit = 1, 2454 .clkr = { 2455 .enable_reg = 0x75058, 2456 .enable_mask = BIT(0), 2457 .hw.init = &(struct clk_init_data){ 2458 .name = "gcc_ufs_card_ice_core_clk", 2459 .parent_names = (const char *[]){ 2460 "gcc_ufs_card_ice_core_clk_src", 2461 }, 2462 .num_parents = 1, 2463 .flags = CLK_SET_RATE_PARENT, 2464 .ops = &clk_branch2_ops, 2465 }, 2466 }, 2467 }; 2468 2469 static struct clk_branch gcc_ufs_card_phy_aux_clk = { 2470 .halt_reg = 0x7508c, 2471 .halt_check = BRANCH_HALT, 2472 .hwcg_reg = 0x7508c, 2473 .hwcg_bit = 1, 2474 .clkr = { 2475 .enable_reg = 0x7508c, 2476 .enable_mask = BIT(0), 2477 .hw.init = &(struct clk_init_data){ 2478 .name = "gcc_ufs_card_phy_aux_clk", 2479 .parent_names = (const char *[]){ 2480 "gcc_ufs_card_phy_aux_clk_src", 2481 }, 2482 .num_parents = 1, 2483 .flags = CLK_SET_RATE_PARENT, 2484 .ops = &clk_branch2_ops, 2485 }, 2486 }, 2487 }; 2488 2489 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { 2490 .halt_check = BRANCH_HALT_SKIP, 2491 .clkr = { 2492 .enable_reg = 0x75018, 2493 .enable_mask = BIT(0), 2494 .hw.init = &(struct clk_init_data){ 2495 .name = "gcc_ufs_card_rx_symbol_0_clk", 2496 .ops = &clk_branch2_ops, 2497 }, 2498 }, 2499 }; 2500 2501 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { 2502 .halt_check = BRANCH_HALT_SKIP, 2503 .clkr = { 2504 .enable_reg = 0x750a8, 2505 .enable_mask = BIT(0), 2506 .hw.init = &(struct clk_init_data){ 2507 .name = "gcc_ufs_card_rx_symbol_1_clk", 2508 .ops = &clk_branch2_ops, 2509 }, 2510 }, 2511 }; 2512 2513 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { 2514 .halt_check = BRANCH_HALT_SKIP, 2515 .clkr = { 2516 .enable_reg = 0x75014, 2517 .enable_mask = BIT(0), 2518 .hw.init = &(struct clk_init_data){ 2519 .name = "gcc_ufs_card_tx_symbol_0_clk", 2520 .ops = &clk_branch2_ops, 2521 }, 2522 }, 2523 }; 2524 2525 static struct clk_branch gcc_ufs_card_unipro_core_clk = { 2526 .halt_reg = 0x75054, 2527 .halt_check = BRANCH_HALT, 2528 .hwcg_reg = 0x75054, 2529 .hwcg_bit = 1, 2530 .clkr = { 2531 .enable_reg = 0x75054, 2532 .enable_mask = BIT(0), 2533 .hw.init = &(struct clk_init_data){ 2534 .name = "gcc_ufs_card_unipro_core_clk", 2535 .parent_names = (const char *[]){ 2536 "gcc_ufs_card_unipro_core_clk_src", 2537 }, 2538 .num_parents = 1, 2539 .flags = CLK_SET_RATE_PARENT, 2540 .ops = &clk_branch2_ops, 2541 }, 2542 }, 2543 }; 2544 2545 static struct clk_branch gcc_ufs_mem_clkref_clk = { 2546 .halt_reg = 0x8c000, 2547 .halt_check = BRANCH_HALT, 2548 .clkr = { 2549 .enable_reg = 0x8c000, 2550 .enable_mask = BIT(0), 2551 .hw.init = &(struct clk_init_data){ 2552 .name = "gcc_ufs_mem_clkref_clk", 2553 .ops = &clk_branch2_ops, 2554 }, 2555 }, 2556 }; 2557 2558 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2559 .halt_reg = 0x77010, 2560 .halt_check = BRANCH_HALT, 2561 .hwcg_reg = 0x77010, 2562 .hwcg_bit = 1, 2563 .clkr = { 2564 .enable_reg = 0x77010, 2565 .enable_mask = BIT(0), 2566 .hw.init = &(struct clk_init_data){ 2567 .name = "gcc_ufs_phy_ahb_clk", 2568 .ops = &clk_branch2_ops, 2569 }, 2570 }, 2571 }; 2572 2573 static struct clk_branch gcc_ufs_phy_axi_clk = { 2574 .halt_reg = 0x7700c, 2575 .halt_check = BRANCH_HALT, 2576 .hwcg_reg = 0x7700c, 2577 .hwcg_bit = 1, 2578 .clkr = { 2579 .enable_reg = 0x7700c, 2580 .enable_mask = BIT(0), 2581 .hw.init = &(struct clk_init_data){ 2582 .name = "gcc_ufs_phy_axi_clk", 2583 .parent_names = (const char *[]){ 2584 "gcc_ufs_phy_axi_clk_src", 2585 }, 2586 .num_parents = 1, 2587 .flags = CLK_SET_RATE_PARENT, 2588 .ops = &clk_branch2_ops, 2589 }, 2590 }, 2591 }; 2592 2593 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2594 .halt_reg = 0x77058, 2595 .halt_check = BRANCH_HALT, 2596 .hwcg_reg = 0x77058, 2597 .hwcg_bit = 1, 2598 .clkr = { 2599 .enable_reg = 0x77058, 2600 .enable_mask = BIT(0), 2601 .hw.init = &(struct clk_init_data){ 2602 .name = "gcc_ufs_phy_ice_core_clk", 2603 .parent_names = (const char *[]){ 2604 "gcc_ufs_phy_ice_core_clk_src", 2605 }, 2606 .num_parents = 1, 2607 .flags = CLK_SET_RATE_PARENT, 2608 .ops = &clk_branch2_ops, 2609 }, 2610 }, 2611 }; 2612 2613 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2614 .halt_reg = 0x7708c, 2615 .halt_check = BRANCH_HALT, 2616 .hwcg_reg = 0x7708c, 2617 .hwcg_bit = 1, 2618 .clkr = { 2619 .enable_reg = 0x7708c, 2620 .enable_mask = BIT(0), 2621 .hw.init = &(struct clk_init_data){ 2622 .name = "gcc_ufs_phy_phy_aux_clk", 2623 .parent_names = (const char *[]){ 2624 "gcc_ufs_phy_phy_aux_clk_src", 2625 }, 2626 .num_parents = 1, 2627 .flags = CLK_SET_RATE_PARENT, 2628 .ops = &clk_branch2_ops, 2629 }, 2630 }, 2631 }; 2632 2633 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2634 .halt_check = BRANCH_HALT_SKIP, 2635 .clkr = { 2636 .enable_reg = 0x77018, 2637 .enable_mask = BIT(0), 2638 .hw.init = &(struct clk_init_data){ 2639 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2640 .ops = &clk_branch2_ops, 2641 }, 2642 }, 2643 }; 2644 2645 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2646 .halt_check = BRANCH_HALT_SKIP, 2647 .clkr = { 2648 .enable_reg = 0x770a8, 2649 .enable_mask = BIT(0), 2650 .hw.init = &(struct clk_init_data){ 2651 .name = "gcc_ufs_phy_rx_symbol_1_clk", 2652 .ops = &clk_branch2_ops, 2653 }, 2654 }, 2655 }; 2656 2657 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2658 .halt_check = BRANCH_HALT_SKIP, 2659 .clkr = { 2660 .enable_reg = 0x77014, 2661 .enable_mask = BIT(0), 2662 .hw.init = &(struct clk_init_data){ 2663 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2664 .ops = &clk_branch2_ops, 2665 }, 2666 }, 2667 }; 2668 2669 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2670 .halt_reg = 0x77054, 2671 .halt_check = BRANCH_HALT, 2672 .hwcg_reg = 0x77054, 2673 .hwcg_bit = 1, 2674 .clkr = { 2675 .enable_reg = 0x77054, 2676 .enable_mask = BIT(0), 2677 .hw.init = &(struct clk_init_data){ 2678 .name = "gcc_ufs_phy_unipro_core_clk", 2679 .parent_names = (const char *[]){ 2680 "gcc_ufs_phy_unipro_core_clk_src", 2681 }, 2682 .num_parents = 1, 2683 .flags = CLK_SET_RATE_PARENT, 2684 .ops = &clk_branch2_ops, 2685 }, 2686 }, 2687 }; 2688 2689 static struct clk_branch gcc_usb30_prim_master_clk = { 2690 .halt_reg = 0xf00c, 2691 .halt_check = BRANCH_HALT, 2692 .clkr = { 2693 .enable_reg = 0xf00c, 2694 .enable_mask = BIT(0), 2695 .hw.init = &(struct clk_init_data){ 2696 .name = "gcc_usb30_prim_master_clk", 2697 .parent_names = (const char *[]){ 2698 "gcc_usb30_prim_master_clk_src", 2699 }, 2700 .num_parents = 1, 2701 .flags = CLK_SET_RATE_PARENT, 2702 .ops = &clk_branch2_ops, 2703 }, 2704 }, 2705 }; 2706 2707 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2708 .halt_reg = 0xf014, 2709 .halt_check = BRANCH_HALT, 2710 .clkr = { 2711 .enable_reg = 0xf014, 2712 .enable_mask = BIT(0), 2713 .hw.init = &(struct clk_init_data){ 2714 .name = "gcc_usb30_prim_mock_utmi_clk", 2715 .parent_names = (const char *[]){ 2716 "gcc_usb30_prim_mock_utmi_clk_src", 2717 }, 2718 .num_parents = 1, 2719 .flags = CLK_SET_RATE_PARENT, 2720 .ops = &clk_branch2_ops, 2721 }, 2722 }, 2723 }; 2724 2725 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2726 .halt_reg = 0xf010, 2727 .halt_check = BRANCH_HALT, 2728 .clkr = { 2729 .enable_reg = 0xf010, 2730 .enable_mask = BIT(0), 2731 .hw.init = &(struct clk_init_data){ 2732 .name = "gcc_usb30_prim_sleep_clk", 2733 .ops = &clk_branch2_ops, 2734 }, 2735 }, 2736 }; 2737 2738 static struct clk_branch gcc_usb30_sec_master_clk = { 2739 .halt_reg = 0x1000c, 2740 .halt_check = BRANCH_HALT, 2741 .clkr = { 2742 .enable_reg = 0x1000c, 2743 .enable_mask = BIT(0), 2744 .hw.init = &(struct clk_init_data){ 2745 .name = "gcc_usb30_sec_master_clk", 2746 .parent_names = (const char *[]){ 2747 "gcc_usb30_sec_master_clk_src", 2748 }, 2749 .num_parents = 1, 2750 .flags = CLK_SET_RATE_PARENT, 2751 .ops = &clk_branch2_ops, 2752 }, 2753 }, 2754 }; 2755 2756 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { 2757 .halt_reg = 0x10014, 2758 .halt_check = BRANCH_HALT, 2759 .clkr = { 2760 .enable_reg = 0x10014, 2761 .enable_mask = BIT(0), 2762 .hw.init = &(struct clk_init_data){ 2763 .name = "gcc_usb30_sec_mock_utmi_clk", 2764 .parent_names = (const char *[]){ 2765 "gcc_usb30_sec_mock_utmi_clk_src", 2766 }, 2767 .num_parents = 1, 2768 .flags = CLK_SET_RATE_PARENT, 2769 .ops = &clk_branch2_ops, 2770 }, 2771 }, 2772 }; 2773 2774 static struct clk_branch gcc_usb30_sec_sleep_clk = { 2775 .halt_reg = 0x10010, 2776 .halt_check = BRANCH_HALT, 2777 .clkr = { 2778 .enable_reg = 0x10010, 2779 .enable_mask = BIT(0), 2780 .hw.init = &(struct clk_init_data){ 2781 .name = "gcc_usb30_sec_sleep_clk", 2782 .ops = &clk_branch2_ops, 2783 }, 2784 }, 2785 }; 2786 2787 static struct clk_branch gcc_usb3_prim_clkref_clk = { 2788 .halt_reg = 0x8c008, 2789 .halt_check = BRANCH_HALT, 2790 .clkr = { 2791 .enable_reg = 0x8c008, 2792 .enable_mask = BIT(0), 2793 .hw.init = &(struct clk_init_data){ 2794 .name = "gcc_usb3_prim_clkref_clk", 2795 .ops = &clk_branch2_ops, 2796 }, 2797 }, 2798 }; 2799 2800 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2801 .halt_reg = 0xf04c, 2802 .halt_check = BRANCH_HALT, 2803 .clkr = { 2804 .enable_reg = 0xf04c, 2805 .enable_mask = BIT(0), 2806 .hw.init = &(struct clk_init_data){ 2807 .name = "gcc_usb3_prim_phy_aux_clk", 2808 .parent_names = (const char *[]){ 2809 "gcc_usb3_prim_phy_aux_clk_src", 2810 }, 2811 .num_parents = 1, 2812 .flags = CLK_SET_RATE_PARENT, 2813 .ops = &clk_branch2_ops, 2814 }, 2815 }, 2816 }; 2817 2818 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2819 .halt_reg = 0xf050, 2820 .halt_check = BRANCH_HALT, 2821 .clkr = { 2822 .enable_reg = 0xf050, 2823 .enable_mask = BIT(0), 2824 .hw.init = &(struct clk_init_data){ 2825 .name = "gcc_usb3_prim_phy_com_aux_clk", 2826 .parent_names = (const char *[]){ 2827 "gcc_usb3_prim_phy_aux_clk_src", 2828 }, 2829 .num_parents = 1, 2830 .flags = CLK_SET_RATE_PARENT, 2831 .ops = &clk_branch2_ops, 2832 }, 2833 }, 2834 }; 2835 2836 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2837 .halt_check = BRANCH_HALT_SKIP, 2838 .clkr = { 2839 .enable_reg = 0xf054, 2840 .enable_mask = BIT(0), 2841 .hw.init = &(struct clk_init_data){ 2842 .name = "gcc_usb3_prim_phy_pipe_clk", 2843 .ops = &clk_branch2_ops, 2844 }, 2845 }, 2846 }; 2847 2848 static struct clk_branch gcc_usb3_sec_clkref_clk = { 2849 .halt_reg = 0x8c028, 2850 .halt_check = BRANCH_HALT, 2851 .clkr = { 2852 .enable_reg = 0x8c028, 2853 .enable_mask = BIT(0), 2854 .hw.init = &(struct clk_init_data){ 2855 .name = "gcc_usb3_sec_clkref_clk", 2856 .ops = &clk_branch2_ops, 2857 }, 2858 }, 2859 }; 2860 2861 static struct clk_branch gcc_usb3_sec_phy_aux_clk = { 2862 .halt_reg = 0x1004c, 2863 .halt_check = BRANCH_HALT, 2864 .clkr = { 2865 .enable_reg = 0x1004c, 2866 .enable_mask = BIT(0), 2867 .hw.init = &(struct clk_init_data){ 2868 .name = "gcc_usb3_sec_phy_aux_clk", 2869 .parent_names = (const char *[]){ 2870 "gcc_usb3_sec_phy_aux_clk_src", 2871 }, 2872 .num_parents = 1, 2873 .flags = CLK_SET_RATE_PARENT, 2874 .ops = &clk_branch2_ops, 2875 }, 2876 }, 2877 }; 2878 2879 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { 2880 .halt_reg = 0x10050, 2881 .halt_check = BRANCH_HALT, 2882 .clkr = { 2883 .enable_reg = 0x10050, 2884 .enable_mask = BIT(0), 2885 .hw.init = &(struct clk_init_data){ 2886 .name = "gcc_usb3_sec_phy_com_aux_clk", 2887 .parent_names = (const char *[]){ 2888 "gcc_usb3_sec_phy_aux_clk_src", 2889 }, 2890 .num_parents = 1, 2891 .flags = CLK_SET_RATE_PARENT, 2892 .ops = &clk_branch2_ops, 2893 }, 2894 }, 2895 }; 2896 2897 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { 2898 .halt_check = BRANCH_HALT_SKIP, 2899 .clkr = { 2900 .enable_reg = 0x10054, 2901 .enable_mask = BIT(0), 2902 .hw.init = &(struct clk_init_data){ 2903 .name = "gcc_usb3_sec_phy_pipe_clk", 2904 .ops = &clk_branch2_ops, 2905 }, 2906 }, 2907 }; 2908 2909 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 2910 .halt_reg = 0x6a004, 2911 .halt_check = BRANCH_HALT, 2912 .hwcg_reg = 0x6a004, 2913 .hwcg_bit = 1, 2914 .clkr = { 2915 .enable_reg = 0x6a004, 2916 .enable_mask = BIT(0), 2917 .hw.init = &(struct clk_init_data){ 2918 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2919 .ops = &clk_branch2_ops, 2920 }, 2921 }, 2922 }; 2923 2924 static struct clk_branch gcc_vdda_vs_clk = { 2925 .halt_reg = 0x7a00c, 2926 .halt_check = BRANCH_HALT, 2927 .clkr = { 2928 .enable_reg = 0x7a00c, 2929 .enable_mask = BIT(0), 2930 .hw.init = &(struct clk_init_data){ 2931 .name = "gcc_vdda_vs_clk", 2932 .parent_names = (const char *[]){ 2933 "gcc_vsensor_clk_src", 2934 }, 2935 .num_parents = 1, 2936 .flags = CLK_SET_RATE_PARENT, 2937 .ops = &clk_branch2_ops, 2938 }, 2939 }, 2940 }; 2941 2942 static struct clk_branch gcc_vddcx_vs_clk = { 2943 .halt_reg = 0x7a004, 2944 .halt_check = BRANCH_HALT, 2945 .clkr = { 2946 .enable_reg = 0x7a004, 2947 .enable_mask = BIT(0), 2948 .hw.init = &(struct clk_init_data){ 2949 .name = "gcc_vddcx_vs_clk", 2950 .parent_names = (const char *[]){ 2951 "gcc_vsensor_clk_src", 2952 }, 2953 .num_parents = 1, 2954 .flags = CLK_SET_RATE_PARENT, 2955 .ops = &clk_branch2_ops, 2956 }, 2957 }, 2958 }; 2959 2960 static struct clk_branch gcc_vddmx_vs_clk = { 2961 .halt_reg = 0x7a008, 2962 .halt_check = BRANCH_HALT, 2963 .clkr = { 2964 .enable_reg = 0x7a008, 2965 .enable_mask = BIT(0), 2966 .hw.init = &(struct clk_init_data){ 2967 .name = "gcc_vddmx_vs_clk", 2968 .parent_names = (const char *[]){ 2969 "gcc_vsensor_clk_src", 2970 }, 2971 .num_parents = 1, 2972 .flags = CLK_SET_RATE_PARENT, 2973 .ops = &clk_branch2_ops, 2974 }, 2975 }, 2976 }; 2977 2978 static struct clk_branch gcc_video_ahb_clk = { 2979 .halt_reg = 0xb004, 2980 .halt_check = BRANCH_HALT, 2981 .hwcg_reg = 0xb004, 2982 .hwcg_bit = 1, 2983 .clkr = { 2984 .enable_reg = 0xb004, 2985 .enable_mask = BIT(0), 2986 .hw.init = &(struct clk_init_data){ 2987 .name = "gcc_video_ahb_clk", 2988 .ops = &clk_branch2_ops, 2989 }, 2990 }, 2991 }; 2992 2993 static struct clk_branch gcc_video_axi_clk = { 2994 .halt_reg = 0xb01c, 2995 .halt_check = BRANCH_VOTED, 2996 .clkr = { 2997 .enable_reg = 0xb01c, 2998 .enable_mask = BIT(0), 2999 .hw.init = &(struct clk_init_data){ 3000 .name = "gcc_video_axi_clk", 3001 .ops = &clk_branch2_ops, 3002 }, 3003 }, 3004 }; 3005 3006 static struct clk_branch gcc_video_xo_clk = { 3007 .halt_reg = 0xb028, 3008 .halt_check = BRANCH_HALT, 3009 .clkr = { 3010 .enable_reg = 0xb028, 3011 .enable_mask = BIT(0), 3012 .hw.init = &(struct clk_init_data){ 3013 .name = "gcc_video_xo_clk", 3014 .ops = &clk_branch2_ops, 3015 }, 3016 }, 3017 }; 3018 3019 static struct clk_branch gcc_vs_ctrl_ahb_clk = { 3020 .halt_reg = 0x7a014, 3021 .halt_check = BRANCH_HALT, 3022 .hwcg_reg = 0x7a014, 3023 .hwcg_bit = 1, 3024 .clkr = { 3025 .enable_reg = 0x7a014, 3026 .enable_mask = BIT(0), 3027 .hw.init = &(struct clk_init_data){ 3028 .name = "gcc_vs_ctrl_ahb_clk", 3029 .ops = &clk_branch2_ops, 3030 }, 3031 }, 3032 }; 3033 3034 static struct clk_branch gcc_vs_ctrl_clk = { 3035 .halt_reg = 0x7a010, 3036 .halt_check = BRANCH_HALT, 3037 .clkr = { 3038 .enable_reg = 0x7a010, 3039 .enable_mask = BIT(0), 3040 .hw.init = &(struct clk_init_data){ 3041 .name = "gcc_vs_ctrl_clk", 3042 .parent_names = (const char *[]){ 3043 "gcc_vs_ctrl_clk_src", 3044 }, 3045 .num_parents = 1, 3046 .flags = CLK_SET_RATE_PARENT, 3047 .ops = &clk_branch2_ops, 3048 }, 3049 }, 3050 }; 3051 3052 static struct gdsc pcie_0_gdsc = { 3053 .gdscr = 0x6b004, 3054 .pd = { 3055 .name = "pcie_0_gdsc", 3056 }, 3057 .pwrsts = PWRSTS_OFF_ON, 3058 .flags = POLL_CFG_GDSCR, 3059 }; 3060 3061 static struct gdsc pcie_1_gdsc = { 3062 .gdscr = 0x8d004, 3063 .pd = { 3064 .name = "pcie_1_gdsc", 3065 }, 3066 .pwrsts = PWRSTS_OFF_ON, 3067 .flags = POLL_CFG_GDSCR, 3068 }; 3069 3070 static struct gdsc ufs_card_gdsc = { 3071 .gdscr = 0x75004, 3072 .pd = { 3073 .name = "ufs_card_gdsc", 3074 }, 3075 .pwrsts = PWRSTS_OFF_ON, 3076 .flags = POLL_CFG_GDSCR, 3077 }; 3078 3079 static struct gdsc ufs_phy_gdsc = { 3080 .gdscr = 0x77004, 3081 .pd = { 3082 .name = "ufs_phy_gdsc", 3083 }, 3084 .pwrsts = PWRSTS_OFF_ON, 3085 .flags = POLL_CFG_GDSCR, 3086 }; 3087 3088 static struct gdsc usb30_prim_gdsc = { 3089 .gdscr = 0xf004, 3090 .pd = { 3091 .name = "usb30_prim_gdsc", 3092 }, 3093 .pwrsts = PWRSTS_OFF_ON, 3094 .flags = POLL_CFG_GDSCR, 3095 }; 3096 3097 static struct gdsc usb30_sec_gdsc = { 3098 .gdscr = 0x10004, 3099 .pd = { 3100 .name = "usb30_sec_gdsc", 3101 }, 3102 .pwrsts = PWRSTS_OFF_ON, 3103 .flags = POLL_CFG_GDSCR, 3104 }; 3105 3106 static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = { 3107 .gdscr = 0x7d030, 3108 .pd = { 3109 .name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc", 3110 }, 3111 .pwrsts = PWRSTS_OFF_ON, 3112 }; 3113 3114 static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = { 3115 .gdscr = 0x7d03c, 3116 .pd = { 3117 .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc", 3118 }, 3119 .pwrsts = PWRSTS_OFF_ON, 3120 }; 3121 3122 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = { 3123 .gdscr = 0x7d034, 3124 .pd = { 3125 .name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc", 3126 }, 3127 .pwrsts = PWRSTS_OFF_ON, 3128 }; 3129 3130 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = { 3131 .gdscr = 0x7d038, 3132 .pd = { 3133 .name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc", 3134 }, 3135 .pwrsts = PWRSTS_OFF_ON, 3136 }; 3137 3138 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { 3139 .gdscr = 0x7d040, 3140 .pd = { 3141 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", 3142 }, 3143 .pwrsts = PWRSTS_OFF_ON, 3144 }; 3145 3146 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = { 3147 .gdscr = 0x7d048, 3148 .pd = { 3149 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", 3150 }, 3151 .pwrsts = PWRSTS_OFF_ON, 3152 }; 3153 3154 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = { 3155 .gdscr = 0x7d044, 3156 .pd = { 3157 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc", 3158 }, 3159 .pwrsts = PWRSTS_OFF_ON, 3160 }; 3161 3162 static struct clk_regmap *gcc_sdm845_clocks[] = { 3163 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, 3164 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, 3165 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 3166 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 3167 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, 3168 [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr, 3169 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3170 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 3171 [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr, 3172 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 3173 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, 3174 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, 3175 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, 3176 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3177 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, 3178 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, 3179 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, 3180 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, 3181 [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr, 3182 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 3183 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, 3184 [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr, 3185 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 3186 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 3187 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 3188 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3189 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3190 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3191 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3192 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3193 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3194 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 3195 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3196 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3197 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, 3198 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3199 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3200 [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr, 3201 [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr, 3202 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 3203 [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr, 3204 [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr, 3205 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr, 3206 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, 3207 [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr, 3208 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3209 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 3210 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3211 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr, 3212 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3213 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3214 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3215 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 3216 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 3217 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 3218 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 3219 [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr, 3220 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 3221 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 3222 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 3223 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 3224 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, 3225 [GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr, 3226 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, 3227 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3228 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3229 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3230 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3231 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3232 [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr, 3233 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3234 [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr, 3235 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3236 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3237 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3238 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3239 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3240 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3241 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3242 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3243 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3244 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3245 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3246 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3247 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 3248 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 3249 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 3250 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 3251 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3252 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3253 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3254 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3255 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3256 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3257 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3258 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3259 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3260 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3261 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3262 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3263 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 3264 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 3265 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 3266 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 3267 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3268 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3269 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3270 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3271 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3272 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3273 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3274 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3275 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3276 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 3277 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 3278 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 3279 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = 3280 &gcc_tsif_inactivity_timers_clk.clkr, 3281 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 3282 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, 3283 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, 3284 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, 3285 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, 3286 [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr, 3287 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, 3288 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, 3289 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, 3290 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, 3291 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, 3292 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, 3293 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, 3294 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, 3295 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = 3296 &gcc_ufs_card_unipro_core_clk_src.clkr, 3297 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, 3298 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3299 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3300 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3301 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3302 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3303 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3304 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3305 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3306 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3307 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3308 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3309 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 3310 &gcc_ufs_phy_unipro_core_clk_src.clkr, 3311 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3312 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3313 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3314 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 3315 &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3316 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3317 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, 3318 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, 3319 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, 3320 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = 3321 &gcc_usb30_sec_mock_utmi_clk_src.clkr, 3322 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, 3323 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 3324 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3325 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3326 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3327 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3328 [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr, 3329 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, 3330 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, 3331 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, 3332 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, 3333 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 3334 [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr, 3335 [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr, 3336 [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr, 3337 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 3338 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr, 3339 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 3340 [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr, 3341 [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr, 3342 [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr, 3343 [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr, 3344 [GPLL0] = &gpll0.clkr, 3345 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 3346 [GPLL4] = &gpll4.clkr, 3347 }; 3348 3349 static const struct qcom_reset_map gcc_sdm845_resets[] = { 3350 [GCC_MMSS_BCR] = { 0xb000 }, 3351 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3352 [GCC_PCIE_1_BCR] = { 0x8d000 }, 3353 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 3354 [GCC_PDM_BCR] = { 0x33000 }, 3355 [GCC_PRNG_BCR] = { 0x34000 }, 3356 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, 3357 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 3358 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3359 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3360 [GCC_SDCC2_BCR] = { 0x14000 }, 3361 [GCC_SDCC4_BCR] = { 0x16000 }, 3362 [GCC_TSIF_BCR] = { 0x36000 }, 3363 [GCC_UFS_CARD_BCR] = { 0x75000 }, 3364 [GCC_UFS_PHY_BCR] = { 0x77000 }, 3365 [GCC_USB30_PRIM_BCR] = { 0xf000 }, 3366 [GCC_USB30_SEC_BCR] = { 0x10000 }, 3367 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 3368 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3369 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 3370 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 3371 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3372 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 3373 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 3374 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3375 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 3376 }; 3377 3378 static struct gdsc *gcc_sdm845_gdscs[] = { 3379 [PCIE_0_GDSC] = &pcie_0_gdsc, 3380 [PCIE_1_GDSC] = &pcie_1_gdsc, 3381 [UFS_CARD_GDSC] = &ufs_card_gdsc, 3382 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3383 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3384 [USB30_SEC_GDSC] = &usb30_sec_gdsc, 3385 [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = 3386 &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc, 3387 [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = 3388 &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc, 3389 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = 3390 &hlos1_vote_aggre_noc_mmu_tbu1_gdsc, 3391 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = 3392 &hlos1_vote_aggre_noc_mmu_tbu2_gdsc, 3393 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = 3394 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, 3395 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = 3396 &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, 3397 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc, 3398 }; 3399 3400 static const struct regmap_config gcc_sdm845_regmap_config = { 3401 .reg_bits = 32, 3402 .reg_stride = 4, 3403 .val_bits = 32, 3404 .max_register = 0x182090, 3405 .fast_io = true, 3406 }; 3407 3408 static const struct qcom_cc_desc gcc_sdm845_desc = { 3409 .config = &gcc_sdm845_regmap_config, 3410 .clks = gcc_sdm845_clocks, 3411 .num_clks = ARRAY_SIZE(gcc_sdm845_clocks), 3412 .resets = gcc_sdm845_resets, 3413 .num_resets = ARRAY_SIZE(gcc_sdm845_resets), 3414 .gdscs = gcc_sdm845_gdscs, 3415 .num_gdscs = ARRAY_SIZE(gcc_sdm845_gdscs), 3416 }; 3417 3418 static const struct of_device_id gcc_sdm845_match_table[] = { 3419 { .compatible = "qcom,gcc-sdm845" }, 3420 { } 3421 }; 3422 MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table); 3423 3424 static int gcc_sdm845_probe(struct platform_device *pdev) 3425 { 3426 struct regmap *regmap; 3427 3428 regmap = qcom_cc_map(pdev, &gcc_sdm845_desc); 3429 if (IS_ERR(regmap)) 3430 return PTR_ERR(regmap); 3431 3432 /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */ 3433 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); 3434 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 3435 3436 /* Enable CPUSS clocks */ 3437 regmap_update_bits(regmap, 0x48190, BIT(0), 0x1); 3438 regmap_update_bits(regmap, 0x52004, BIT(22), 0x1); 3439 3440 return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap); 3441 } 3442 3443 static struct platform_driver gcc_sdm845_driver = { 3444 .probe = gcc_sdm845_probe, 3445 .driver = { 3446 .name = "gcc-sdm845", 3447 .of_match_table = gcc_sdm845_match_table, 3448 }, 3449 }; 3450 3451 static int __init gcc_sdm845_init(void) 3452 { 3453 return platform_driver_register(&gcc_sdm845_driver); 3454 } 3455 subsys_initcall(gcc_sdm845_init); 3456 3457 static void __exit gcc_sdm845_exit(void) 3458 { 3459 platform_driver_unregister(&gcc_sdm845_driver); 3460 } 3461 module_exit(gcc_sdm845_exit); 3462 3463 MODULE_DESCRIPTION("QTI GCC SDM845 Driver"); 3464 MODULE_LICENSE("GPL v2"); 3465 MODULE_ALIAS("platform:gcc-sdm845"); 3466