1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2018, Craig Tatlor. 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/bitops.h> 9 #include <linux/err.h> 10 #include <linux/platform_device.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_device.h> 14 #include <linux/clk-provider.h> 15 #include <linux/regmap.h> 16 #include <linux/reset-controller.h> 17 18 #include <dt-bindings/clock/qcom,gcc-sdm660.h> 19 20 #include "common.h" 21 #include "clk-regmap.h" 22 #include "clk-alpha-pll.h" 23 #include "clk-rcg.h" 24 #include "clk-branch.h" 25 #include "reset.h" 26 #include "gdsc.h" 27 28 enum { 29 P_XO, 30 P_SLEEP_CLK, 31 P_GPLL0, 32 P_GPLL1, 33 P_GPLL4, 34 P_GPLL0_EARLY_DIV, 35 P_GPLL1_EARLY_DIV, 36 }; 37 38 static struct clk_fixed_factor xo = { 39 .mult = 1, 40 .div = 1, 41 .hw.init = &(struct clk_init_data){ 42 .name = "xo", 43 .parent_data = &(const struct clk_parent_data) { 44 .fw_name = "xo" 45 }, 46 .num_parents = 1, 47 .ops = &clk_fixed_factor_ops, 48 }, 49 }; 50 51 static struct clk_alpha_pll gpll0_early = { 52 .offset = 0x0, 53 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 54 .clkr = { 55 .enable_reg = 0x52000, 56 .enable_mask = BIT(0), 57 .hw.init = &(struct clk_init_data){ 58 .name = "gpll0_early", 59 .parent_data = &(const struct clk_parent_data){ 60 .fw_name = "xo", 61 }, 62 .num_parents = 1, 63 .ops = &clk_alpha_pll_ops, 64 }, 65 }, 66 }; 67 68 static struct clk_fixed_factor gpll0_early_div = { 69 .mult = 1, 70 .div = 2, 71 .hw.init = &(struct clk_init_data){ 72 .name = "gpll0_early_div", 73 .parent_hws = (const struct clk_hw*[]){ 74 &gpll0_early.clkr.hw, 75 }, 76 .num_parents = 1, 77 .ops = &clk_fixed_factor_ops, 78 }, 79 }; 80 81 static struct clk_alpha_pll_postdiv gpll0 = { 82 .offset = 0x00000, 83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 84 .clkr.hw.init = &(struct clk_init_data){ 85 .name = "gpll0", 86 .parent_hws = (const struct clk_hw*[]){ 87 &gpll0_early.clkr.hw, 88 }, 89 .num_parents = 1, 90 .ops = &clk_alpha_pll_postdiv_ops, 91 }, 92 }; 93 94 static struct clk_alpha_pll gpll1_early = { 95 .offset = 0x1000, 96 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 97 .clkr = { 98 .enable_reg = 0x52000, 99 .enable_mask = BIT(1), 100 .hw.init = &(struct clk_init_data){ 101 .name = "gpll1_early", 102 .parent_data = &(const struct clk_parent_data){ 103 .fw_name = "xo", 104 }, 105 .num_parents = 1, 106 .ops = &clk_alpha_pll_ops, 107 }, 108 }, 109 }; 110 111 static struct clk_fixed_factor gpll1_early_div = { 112 .mult = 1, 113 .div = 2, 114 .hw.init = &(struct clk_init_data){ 115 .name = "gpll1_early_div", 116 .parent_hws = (const struct clk_hw*[]){ 117 &gpll1_early.clkr.hw, 118 }, 119 .num_parents = 1, 120 .ops = &clk_fixed_factor_ops, 121 }, 122 }; 123 124 static struct clk_alpha_pll_postdiv gpll1 = { 125 .offset = 0x1000, 126 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 127 .clkr.hw.init = &(struct clk_init_data){ 128 .name = "gpll1", 129 .parent_hws = (const struct clk_hw*[]){ 130 &gpll1_early.clkr.hw, 131 }, 132 .num_parents = 1, 133 .ops = &clk_alpha_pll_postdiv_ops, 134 }, 135 }; 136 137 static struct clk_alpha_pll gpll4_early = { 138 .offset = 0x77000, 139 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 140 .clkr = { 141 .enable_reg = 0x52000, 142 .enable_mask = BIT(4), 143 .hw.init = &(struct clk_init_data){ 144 .name = "gpll4_early", 145 .parent_data = &(const struct clk_parent_data){ 146 .fw_name = "xo", 147 }, 148 .num_parents = 1, 149 .ops = &clk_alpha_pll_ops, 150 }, 151 }, 152 }; 153 154 static struct clk_alpha_pll_postdiv gpll4 = { 155 .offset = 0x77000, 156 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 157 .clkr.hw.init = &(struct clk_init_data) 158 { 159 .name = "gpll4", 160 .parent_hws = (const struct clk_hw*[]){ 161 &gpll4_early.clkr.hw, 162 }, 163 .num_parents = 1, 164 .ops = &clk_alpha_pll_postdiv_ops, 165 }, 166 }; 167 168 static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div[] = { 169 { P_XO, 0 }, 170 { P_GPLL0, 1 }, 171 { P_GPLL0_EARLY_DIV, 6 }, 172 }; 173 174 static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div[] = { 175 { .fw_name = "xo" }, 176 { .hw = &gpll0.clkr.hw }, 177 { .hw = &gpll0_early_div.hw }, 178 }; 179 180 static const struct parent_map gcc_parent_map_xo_gpll0[] = { 181 { P_XO, 0 }, 182 { P_GPLL0, 1 }, 183 }; 184 185 static const struct clk_parent_data gcc_parent_data_xo_gpll0[] = { 186 { .fw_name = "xo" }, 187 { .hw = &gpll0.clkr.hw }, 188 }; 189 190 static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = { 191 { P_XO, 0 }, 192 { P_GPLL0, 1 }, 193 { P_SLEEP_CLK, 5 }, 194 { P_GPLL0_EARLY_DIV, 6 }, 195 }; 196 197 static const struct clk_parent_data gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div[] = { 198 { .fw_name = "xo" }, 199 { .hw = &gpll0.clkr.hw }, 200 { .fw_name = "sleep_clk" }, 201 { .hw = &gpll0_early_div.hw }, 202 }; 203 204 static const struct parent_map gcc_parent_map_xo_sleep_clk[] = { 205 { P_XO, 0 }, 206 { P_SLEEP_CLK, 5 }, 207 }; 208 209 static const struct clk_parent_data gcc_parent_data_xo_sleep_clk[] = { 210 { .fw_name = "xo" }, 211 { .fw_name = "sleep_clk" }, 212 }; 213 214 static const struct parent_map gcc_parent_map_xo_gpll4[] = { 215 { P_XO, 0 }, 216 { P_GPLL4, 5 }, 217 }; 218 219 static const struct clk_parent_data gcc_parent_data_xo_gpll4[] = { 220 { .fw_name = "xo" }, 221 { .hw = &gpll4.clkr.hw }, 222 }; 223 224 static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = { 225 { P_XO, 0 }, 226 { P_GPLL0, 1 }, 227 { P_GPLL0_EARLY_DIV, 3 }, 228 { P_GPLL1, 4 }, 229 { P_GPLL4, 5 }, 230 { P_GPLL1_EARLY_DIV, 6 }, 231 }; 232 233 static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = { 234 { .fw_name = "xo" }, 235 { .hw = &gpll0.clkr.hw }, 236 { .hw = &gpll0_early_div.hw }, 237 { .hw = &gpll1.clkr.hw }, 238 { .hw = &gpll4.clkr.hw }, 239 { .hw = &gpll1_early_div.hw }, 240 }; 241 242 static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = { 243 { P_XO, 0 }, 244 { P_GPLL0, 1 }, 245 { P_GPLL4, 5 }, 246 { P_GPLL0_EARLY_DIV, 6 }, 247 }; 248 249 static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div[] = { 250 { .fw_name = "xo" }, 251 { .hw = &gpll0.clkr.hw }, 252 { .hw = &gpll4.clkr.hw }, 253 { .hw = &gpll0_early_div.hw }, 254 }; 255 256 static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = { 257 { P_XO, 0 }, 258 { P_GPLL0, 1 }, 259 { P_GPLL0_EARLY_DIV, 2 }, 260 { P_GPLL4, 5 }, 261 }; 262 263 static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4[] = { 264 { .fw_name = "xo" }, 265 { .hw = &gpll0.clkr.hw }, 266 { .hw = &gpll0_early_div.hw }, 267 { .hw = &gpll4.clkr.hw }, 268 }; 269 270 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = { 271 F(19200000, P_XO, 1, 0, 0), 272 F(50000000, P_GPLL0, 12, 0, 0), 273 { } 274 }; 275 276 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 277 .cmd_rcgr = 0x19020, 278 .mnd_width = 0, 279 .hid_width = 5, 280 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 281 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 282 .clkr.hw.init = &(struct clk_init_data){ 283 .name = "blsp1_qup1_i2c_apps_clk_src", 284 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 285 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 286 .ops = &clk_rcg2_ops, 287 }, 288 }; 289 290 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { 291 F(960000, P_XO, 10, 1, 2), 292 F(4800000, P_XO, 4, 0, 0), 293 F(9600000, P_XO, 2, 0, 0), 294 F(15000000, P_GPLL0, 10, 1, 4), 295 F(19200000, P_XO, 1, 0, 0), 296 F(25000000, P_GPLL0, 12, 1, 2), 297 F(50000000, P_GPLL0, 12, 0, 0), 298 { } 299 }; 300 301 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 302 .cmd_rcgr = 0x1900c, 303 .mnd_width = 8, 304 .hid_width = 5, 305 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 306 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 307 .clkr.hw.init = &(struct clk_init_data){ 308 .name = "blsp1_qup1_spi_apps_clk_src", 309 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 310 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 311 .ops = &clk_rcg2_ops, 312 }, 313 }; 314 315 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 316 .cmd_rcgr = 0x1b020, 317 .mnd_width = 0, 318 .hid_width = 5, 319 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 320 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 321 .clkr.hw.init = &(struct clk_init_data){ 322 .name = "blsp1_qup2_i2c_apps_clk_src", 323 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 324 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 325 .ops = &clk_rcg2_ops, 326 }, 327 }; 328 329 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 330 .cmd_rcgr = 0x1b00c, 331 .mnd_width = 8, 332 .hid_width = 5, 333 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 334 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 335 .clkr.hw.init = &(struct clk_init_data){ 336 .name = "blsp1_qup2_spi_apps_clk_src", 337 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 338 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 339 .ops = &clk_rcg2_ops, 340 }, 341 }; 342 343 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 344 .cmd_rcgr = 0x1d020, 345 .mnd_width = 0, 346 .hid_width = 5, 347 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 348 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 349 .clkr.hw.init = &(struct clk_init_data){ 350 .name = "blsp1_qup3_i2c_apps_clk_src", 351 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 352 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 353 .ops = &clk_rcg2_ops, 354 }, 355 }; 356 357 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 358 .cmd_rcgr = 0x1d00c, 359 .mnd_width = 8, 360 .hid_width = 5, 361 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 362 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 363 .clkr.hw.init = &(struct clk_init_data){ 364 .name = "blsp1_qup3_spi_apps_clk_src", 365 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 366 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 367 .ops = &clk_rcg2_ops, 368 }, 369 }; 370 371 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 372 .cmd_rcgr = 0x1f020, 373 .mnd_width = 0, 374 .hid_width = 5, 375 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 376 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 377 .clkr.hw.init = &(struct clk_init_data){ 378 .name = "blsp1_qup4_i2c_apps_clk_src", 379 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 380 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 381 .ops = &clk_rcg2_ops, 382 }, 383 }; 384 385 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 386 .cmd_rcgr = 0x1f00c, 387 .mnd_width = 8, 388 .hid_width = 5, 389 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 390 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 391 .clkr.hw.init = &(struct clk_init_data){ 392 .name = "blsp1_qup4_spi_apps_clk_src", 393 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 394 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 395 .ops = &clk_rcg2_ops, 396 }, 397 }; 398 399 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = { 400 F(3686400, P_GPLL0, 1, 96, 15625), 401 F(7372800, P_GPLL0, 1, 192, 15625), 402 F(14745600, P_GPLL0, 1, 384, 15625), 403 F(16000000, P_GPLL0, 5, 2, 15), 404 F(19200000, P_XO, 1, 0, 0), 405 F(24000000, P_GPLL0, 5, 1, 5), 406 F(32000000, P_GPLL0, 1, 4, 75), 407 F(40000000, P_GPLL0, 15, 0, 0), 408 F(46400000, P_GPLL0, 1, 29, 375), 409 F(48000000, P_GPLL0, 12.5, 0, 0), 410 F(51200000, P_GPLL0, 1, 32, 375), 411 F(56000000, P_GPLL0, 1, 7, 75), 412 F(58982400, P_GPLL0, 1, 1536, 15625), 413 F(60000000, P_GPLL0, 10, 0, 0), 414 F(63157895, P_GPLL0, 9.5, 0, 0), 415 { } 416 }; 417 418 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 419 .cmd_rcgr = 0x1a00c, 420 .mnd_width = 16, 421 .hid_width = 5, 422 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 423 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 424 .clkr.hw.init = &(struct clk_init_data){ 425 .name = "blsp1_uart1_apps_clk_src", 426 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 427 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 428 .ops = &clk_rcg2_ops, 429 }, 430 }; 431 432 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 433 .cmd_rcgr = 0x1c00c, 434 .mnd_width = 16, 435 .hid_width = 5, 436 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 437 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 438 .clkr.hw.init = &(struct clk_init_data){ 439 .name = "blsp1_uart2_apps_clk_src", 440 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 441 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 442 .ops = &clk_rcg2_ops, 443 }, 444 }; 445 446 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { 447 .cmd_rcgr = 0x26020, 448 .mnd_width = 0, 449 .hid_width = 5, 450 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 451 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 452 .clkr.hw.init = &(struct clk_init_data){ 453 .name = "blsp2_qup1_i2c_apps_clk_src", 454 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 455 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 456 .ops = &clk_rcg2_ops, 457 }, 458 }; 459 460 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { 461 .cmd_rcgr = 0x2600c, 462 .mnd_width = 8, 463 .hid_width = 5, 464 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 465 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 466 .clkr.hw.init = &(struct clk_init_data){ 467 .name = "blsp2_qup1_spi_apps_clk_src", 468 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 469 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 470 .ops = &clk_rcg2_ops, 471 }, 472 }; 473 474 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { 475 .cmd_rcgr = 0x28020, 476 .mnd_width = 0, 477 .hid_width = 5, 478 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 479 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 480 .clkr.hw.init = &(struct clk_init_data){ 481 .name = "blsp2_qup2_i2c_apps_clk_src", 482 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 483 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 484 .ops = &clk_rcg2_ops, 485 }, 486 }; 487 488 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { 489 .cmd_rcgr = 0x2800c, 490 .mnd_width = 8, 491 .hid_width = 5, 492 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 493 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 494 .clkr.hw.init = &(struct clk_init_data){ 495 .name = "blsp2_qup2_spi_apps_clk_src", 496 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 497 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 498 .ops = &clk_rcg2_ops, 499 }, 500 }; 501 502 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { 503 .cmd_rcgr = 0x2a020, 504 .mnd_width = 0, 505 .hid_width = 5, 506 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 507 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 508 .clkr.hw.init = &(struct clk_init_data){ 509 .name = "blsp2_qup3_i2c_apps_clk_src", 510 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 511 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 512 .ops = &clk_rcg2_ops, 513 }, 514 }; 515 516 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { 517 .cmd_rcgr = 0x2a00c, 518 .mnd_width = 8, 519 .hid_width = 5, 520 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 521 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 522 .clkr.hw.init = &(struct clk_init_data){ 523 .name = "blsp2_qup3_spi_apps_clk_src", 524 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 525 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 526 .ops = &clk_rcg2_ops, 527 }, 528 }; 529 530 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { 531 .cmd_rcgr = 0x2c020, 532 .mnd_width = 0, 533 .hid_width = 5, 534 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 535 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 536 .clkr.hw.init = &(struct clk_init_data){ 537 .name = "blsp2_qup4_i2c_apps_clk_src", 538 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 539 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 540 .ops = &clk_rcg2_ops, 541 }, 542 }; 543 544 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { 545 .cmd_rcgr = 0x2c00c, 546 .mnd_width = 8, 547 .hid_width = 5, 548 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 549 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 550 .clkr.hw.init = &(struct clk_init_data){ 551 .name = "blsp2_qup4_spi_apps_clk_src", 552 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 553 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 554 .ops = &clk_rcg2_ops, 555 }, 556 }; 557 558 static struct clk_rcg2 blsp2_uart1_apps_clk_src = { 559 .cmd_rcgr = 0x2700c, 560 .mnd_width = 16, 561 .hid_width = 5, 562 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 563 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 564 .clkr.hw.init = &(struct clk_init_data){ 565 .name = "blsp2_uart1_apps_clk_src", 566 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 567 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 568 .ops = &clk_rcg2_ops, 569 }, 570 }; 571 572 static struct clk_rcg2 blsp2_uart2_apps_clk_src = { 573 .cmd_rcgr = 0x2900c, 574 .mnd_width = 16, 575 .hid_width = 5, 576 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 577 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 578 .clkr.hw.init = &(struct clk_init_data){ 579 .name = "blsp2_uart2_apps_clk_src", 580 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 581 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 582 .ops = &clk_rcg2_ops, 583 }, 584 }; 585 586 static const struct freq_tbl ftbl_gp1_clk_src[] = { 587 F(19200000, P_XO, 1, 0, 0), 588 F(100000000, P_GPLL0, 6, 0, 0), 589 F(200000000, P_GPLL0, 3, 0, 0), 590 { } 591 }; 592 593 static struct clk_rcg2 gp1_clk_src = { 594 .cmd_rcgr = 0x64004, 595 .mnd_width = 8, 596 .hid_width = 5, 597 .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div, 598 .freq_tbl = ftbl_gp1_clk_src, 599 .clkr.hw.init = &(struct clk_init_data){ 600 .name = "gp1_clk_src", 601 .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, 602 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div), 603 .ops = &clk_rcg2_ops, 604 }, 605 }; 606 607 static struct clk_rcg2 gp2_clk_src = { 608 .cmd_rcgr = 0x65004, 609 .mnd_width = 8, 610 .hid_width = 5, 611 .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div, 612 .freq_tbl = ftbl_gp1_clk_src, 613 .clkr.hw.init = &(struct clk_init_data){ 614 .name = "gp2_clk_src", 615 .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, 616 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div), 617 .ops = &clk_rcg2_ops, 618 }, 619 }; 620 621 static struct clk_rcg2 gp3_clk_src = { 622 .cmd_rcgr = 0x66004, 623 .mnd_width = 8, 624 .hid_width = 5, 625 .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div, 626 .freq_tbl = ftbl_gp1_clk_src, 627 .clkr.hw.init = &(struct clk_init_data){ 628 .name = "gp3_clk_src", 629 .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, 630 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div), 631 .ops = &clk_rcg2_ops, 632 }, 633 }; 634 635 static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = { 636 F(300000000, P_GPLL0, 2, 0, 0), 637 F(600000000, P_GPLL0, 1, 0, 0), 638 { } 639 }; 640 641 static struct clk_rcg2 hmss_gpll0_clk_src = { 642 .cmd_rcgr = 0x4805c, 643 .mnd_width = 0, 644 .hid_width = 5, 645 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 646 .freq_tbl = ftbl_hmss_gpll0_clk_src, 647 .clkr.hw.init = &(struct clk_init_data){ 648 .name = "hmss_gpll0_clk_src", 649 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 650 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 651 .ops = &clk_rcg2_ops, 652 }, 653 }; 654 655 static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = { 656 F(384000000, P_GPLL4, 4, 0, 0), 657 F(768000000, P_GPLL4, 2, 0, 0), 658 F(1536000000, P_GPLL4, 1, 0, 0), 659 { } 660 }; 661 662 static struct clk_rcg2 hmss_gpll4_clk_src = { 663 .cmd_rcgr = 0x48074, 664 .mnd_width = 0, 665 .hid_width = 5, 666 .parent_map = gcc_parent_map_xo_gpll4, 667 .freq_tbl = ftbl_hmss_gpll4_clk_src, 668 .clkr.hw.init = &(struct clk_init_data){ 669 .name = "hmss_gpll4_clk_src", 670 .parent_data = gcc_parent_data_xo_gpll4, 671 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll4), 672 .ops = &clk_rcg2_ops, 673 }, 674 }; 675 676 static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { 677 F(19200000, P_XO, 1, 0, 0), 678 { } 679 }; 680 681 static struct clk_rcg2 hmss_rbcpr_clk_src = { 682 .cmd_rcgr = 0x48044, 683 .mnd_width = 0, 684 .hid_width = 5, 685 .parent_map = gcc_parent_map_xo_gpll0, 686 .freq_tbl = ftbl_hmss_rbcpr_clk_src, 687 .clkr.hw.init = &(struct clk_init_data){ 688 .name = "hmss_rbcpr_clk_src", 689 .parent_data = gcc_parent_data_xo_gpll0, 690 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0), 691 .ops = &clk_rcg2_ops, 692 }, 693 }; 694 695 static const struct freq_tbl ftbl_pdm2_clk_src[] = { 696 F(60000000, P_GPLL0, 10, 0, 0), 697 { } 698 }; 699 700 static struct clk_rcg2 pdm2_clk_src = { 701 .cmd_rcgr = 0x33010, 702 .mnd_width = 0, 703 .hid_width = 5, 704 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 705 .freq_tbl = ftbl_pdm2_clk_src, 706 .clkr.hw.init = &(struct clk_init_data){ 707 .name = "pdm2_clk_src", 708 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 709 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 710 .ops = &clk_rcg2_ops, 711 }, 712 }; 713 714 static const struct freq_tbl ftbl_qspi_ser_clk_src[] = { 715 F(19200000, P_XO, 1, 0, 0), 716 F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0), 717 F(160400000, P_GPLL1, 5, 0, 0), 718 F(267333333, P_GPLL1, 3, 0, 0), 719 { } 720 }; 721 722 static struct clk_rcg2 qspi_ser_clk_src = { 723 .cmd_rcgr = 0x4d00c, 724 .mnd_width = 0, 725 .hid_width = 5, 726 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div, 727 .freq_tbl = ftbl_qspi_ser_clk_src, 728 .clkr.hw.init = &(struct clk_init_data){ 729 .name = "qspi_ser_clk_src", 730 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div, 731 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div), 732 .ops = &clk_rcg2_ops, 733 }, 734 }; 735 736 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { 737 F(144000, P_XO, 16, 3, 25), 738 F(400000, P_XO, 12, 1, 4), 739 F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3), 740 F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2), 741 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0), 742 F(100000000, P_GPLL0, 6, 0, 0), 743 F(192000000, P_GPLL4, 8, 0, 0), 744 F(384000000, P_GPLL4, 4, 0, 0), 745 { } 746 }; 747 748 static struct clk_rcg2 sdcc1_apps_clk_src = { 749 .cmd_rcgr = 0x1602c, 750 .mnd_width = 8, 751 .hid_width = 5, 752 .parent_map = gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div, 753 .freq_tbl = ftbl_sdcc1_apps_clk_src, 754 .clkr.hw.init = &(struct clk_init_data){ 755 .name = "sdcc1_apps_clk_src", 756 .parent_data = gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div, 757 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div), 758 .ops = &clk_rcg2_floor_ops, 759 }, 760 }; 761 762 static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = { 763 F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0), 764 F(150000000, P_GPLL0, 4, 0, 0), 765 F(200000000, P_GPLL0, 3, 0, 0), 766 F(300000000, P_GPLL0, 2, 0, 0), 767 { } 768 }; 769 770 static struct clk_rcg2 sdcc1_ice_core_clk_src = { 771 .cmd_rcgr = 0x16010, 772 .mnd_width = 0, 773 .hid_width = 5, 774 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 775 .freq_tbl = ftbl_sdcc1_ice_core_clk_src, 776 .clkr.hw.init = &(struct clk_init_data){ 777 .name = "sdcc1_ice_core_clk_src", 778 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 779 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 780 .ops = &clk_rcg2_ops, 781 }, 782 }; 783 784 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = { 785 F(144000, P_XO, 16, 3, 25), 786 F(400000, P_XO, 12, 1, 4), 787 F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3), 788 F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2), 789 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0), 790 F(100000000, P_GPLL0, 6, 0, 0), 791 F(192000000, P_GPLL4, 8, 0, 0), 792 F(200000000, P_GPLL0, 3, 0, 0), 793 { } 794 }; 795 796 static struct clk_rcg2 sdcc2_apps_clk_src = { 797 .cmd_rcgr = 0x14010, 798 .mnd_width = 8, 799 .hid_width = 5, 800 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4, 801 .freq_tbl = ftbl_sdcc2_apps_clk_src, 802 .clkr.hw.init = &(struct clk_init_data){ 803 .name = "sdcc2_apps_clk_src", 804 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4, 805 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4), 806 .ops = &clk_rcg2_floor_ops, 807 }, 808 }; 809 810 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = { 811 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0), 812 F(100000000, P_GPLL0, 6, 0, 0), 813 F(150000000, P_GPLL0, 4, 0, 0), 814 F(200000000, P_GPLL0, 3, 0, 0), 815 F(240000000, P_GPLL0, 2.5, 0, 0), 816 { } 817 }; 818 819 static struct clk_rcg2 ufs_axi_clk_src = { 820 .cmd_rcgr = 0x75018, 821 .mnd_width = 8, 822 .hid_width = 5, 823 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 824 .freq_tbl = ftbl_ufs_axi_clk_src, 825 .clkr.hw.init = &(struct clk_init_data){ 826 .name = "ufs_axi_clk_src", 827 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 828 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 829 .ops = &clk_rcg2_ops, 830 }, 831 }; 832 833 static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = { 834 F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0), 835 F(150000000, P_GPLL0, 4, 0, 0), 836 F(300000000, P_GPLL0, 2, 0, 0), 837 { } 838 }; 839 840 static struct clk_rcg2 ufs_ice_core_clk_src = { 841 .cmd_rcgr = 0x76010, 842 .mnd_width = 0, 843 .hid_width = 5, 844 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 845 .freq_tbl = ftbl_ufs_ice_core_clk_src, 846 .clkr.hw.init = &(struct clk_init_data){ 847 .name = "ufs_ice_core_clk_src", 848 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 849 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 850 .ops = &clk_rcg2_ops, 851 }, 852 }; 853 854 static struct clk_rcg2 ufs_phy_aux_clk_src = { 855 .cmd_rcgr = 0x76044, 856 .mnd_width = 0, 857 .hid_width = 5, 858 .parent_map = gcc_parent_map_xo_sleep_clk, 859 .freq_tbl = ftbl_hmss_rbcpr_clk_src, 860 .clkr.hw.init = &(struct clk_init_data){ 861 .name = "ufs_phy_aux_clk_src", 862 .parent_data = gcc_parent_data_xo_sleep_clk, 863 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_sleep_clk), 864 .ops = &clk_rcg2_ops, 865 }, 866 }; 867 868 static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = { 869 F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0), 870 F(75000000, P_GPLL0, 8, 0, 0), 871 F(150000000, P_GPLL0, 4, 0, 0), 872 { } 873 }; 874 875 static struct clk_rcg2 ufs_unipro_core_clk_src = { 876 .cmd_rcgr = 0x76028, 877 .mnd_width = 0, 878 .hid_width = 5, 879 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 880 .freq_tbl = ftbl_ufs_unipro_core_clk_src, 881 .clkr.hw.init = &(struct clk_init_data){ 882 .name = "ufs_unipro_core_clk_src", 883 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 884 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 885 .ops = &clk_rcg2_ops, 886 }, 887 }; 888 889 static const struct freq_tbl ftbl_usb20_master_clk_src[] = { 890 F(19200000, P_XO, 1, 0, 0), 891 F(60000000, P_GPLL0, 10, 0, 0), 892 F(120000000, P_GPLL0, 5, 0, 0), 893 { } 894 }; 895 896 static struct clk_rcg2 usb20_master_clk_src = { 897 .cmd_rcgr = 0x2f010, 898 .mnd_width = 8, 899 .hid_width = 5, 900 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 901 .freq_tbl = ftbl_usb20_master_clk_src, 902 .clkr.hw.init = &(struct clk_init_data){ 903 .name = "usb20_master_clk_src", 904 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 905 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 906 .ops = &clk_rcg2_ops, 907 }, 908 }; 909 910 static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] = { 911 F(19200000, P_XO, 1, 0, 0), 912 F(60000000, P_GPLL0, 10, 0, 0), 913 { } 914 }; 915 916 static struct clk_rcg2 usb20_mock_utmi_clk_src = { 917 .cmd_rcgr = 0x2f024, 918 .mnd_width = 0, 919 .hid_width = 5, 920 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 921 .freq_tbl = ftbl_usb20_mock_utmi_clk_src, 922 .clkr.hw.init = &(struct clk_init_data){ 923 .name = "usb20_mock_utmi_clk_src", 924 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 925 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 926 .ops = &clk_rcg2_ops, 927 }, 928 }; 929 930 static const struct freq_tbl ftbl_usb30_master_clk_src[] = { 931 F(19200000, P_XO, 1, 0, 0), 932 F(66666667, P_GPLL0_EARLY_DIV, 4.5, 0, 0), 933 F(120000000, P_GPLL0, 5, 0, 0), 934 F(133333333, P_GPLL0, 4.5, 0, 0), 935 F(150000000, P_GPLL0, 4, 0, 0), 936 F(200000000, P_GPLL0, 3, 0, 0), 937 F(240000000, P_GPLL0, 2.5, 0, 0), 938 { } 939 }; 940 941 static struct clk_rcg2 usb30_master_clk_src = { 942 .cmd_rcgr = 0xf014, 943 .mnd_width = 8, 944 .hid_width = 5, 945 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 946 .freq_tbl = ftbl_usb30_master_clk_src, 947 .clkr.hw.init = &(struct clk_init_data){ 948 .name = "usb30_master_clk_src", 949 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 950 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 951 .ops = &clk_rcg2_ops, 952 }, 953 }; 954 955 static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = { 956 F(19200000, P_XO, 1, 0, 0), 957 F(40000000, P_GPLL0_EARLY_DIV, 7.5, 0, 0), 958 F(60000000, P_GPLL0, 10, 0, 0), 959 { } 960 }; 961 962 static struct clk_rcg2 usb30_mock_utmi_clk_src = { 963 .cmd_rcgr = 0xf028, 964 .mnd_width = 0, 965 .hid_width = 5, 966 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, 967 .freq_tbl = ftbl_usb30_mock_utmi_clk_src, 968 .clkr.hw.init = &(struct clk_init_data){ 969 .name = "usb30_mock_utmi_clk_src", 970 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, 971 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), 972 .ops = &clk_rcg2_ops, 973 }, 974 }; 975 976 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { 977 F(1200000, P_XO, 16, 0, 0), 978 F(19200000, P_XO, 1, 0, 0), 979 { } 980 }; 981 982 static struct clk_rcg2 usb3_phy_aux_clk_src = { 983 .cmd_rcgr = 0x5000c, 984 .mnd_width = 0, 985 .hid_width = 5, 986 .parent_map = gcc_parent_map_xo_sleep_clk, 987 .freq_tbl = ftbl_usb3_phy_aux_clk_src, 988 .clkr.hw.init = &(struct clk_init_data){ 989 .name = "usb3_phy_aux_clk_src", 990 .parent_data = gcc_parent_data_xo_sleep_clk, 991 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_sleep_clk), 992 .ops = &clk_rcg2_ops, 993 }, 994 }; 995 996 static struct clk_branch gcc_aggre2_ufs_axi_clk = { 997 .halt_reg = 0x75034, 998 .halt_check = BRANCH_HALT, 999 .clkr = { 1000 .enable_reg = 0x75034, 1001 .enable_mask = BIT(0), 1002 .hw.init = &(struct clk_init_data){ 1003 .name = "gcc_aggre2_ufs_axi_clk", 1004 .parent_hws = (const struct clk_hw*[]) { 1005 &ufs_axi_clk_src.clkr.hw, 1006 }, 1007 .num_parents = 1, 1008 .ops = &clk_branch2_ops, 1009 }, 1010 }, 1011 }; 1012 1013 static struct clk_branch gcc_aggre2_usb3_axi_clk = { 1014 .halt_reg = 0xf03c, 1015 .halt_check = BRANCH_HALT, 1016 .clkr = { 1017 .enable_reg = 0xf03c, 1018 .enable_mask = BIT(0), 1019 .hw.init = &(struct clk_init_data){ 1020 .name = "gcc_aggre2_usb3_axi_clk", 1021 .parent_hws = (const struct clk_hw*[]) { 1022 &usb30_master_clk_src.clkr.hw, 1023 }, 1024 .num_parents = 1, 1025 .ops = &clk_branch2_ops, 1026 }, 1027 }, 1028 }; 1029 1030 static struct clk_branch gcc_bimc_gfx_clk = { 1031 .halt_reg = 0x7106c, 1032 .halt_check = BRANCH_VOTED, 1033 .clkr = { 1034 .enable_reg = 0x7106c, 1035 .enable_mask = BIT(0), 1036 .hw.init = &(struct clk_init_data){ 1037 .name = "gcc_bimc_gfx_clk", 1038 .ops = &clk_branch2_ops, 1039 }, 1040 }, 1041 }; 1042 1043 static struct clk_branch gcc_bimc_hmss_axi_clk = { 1044 .halt_reg = 0x48004, 1045 .halt_check = BRANCH_HALT_VOTED, 1046 .clkr = { 1047 .enable_reg = 0x52004, 1048 .enable_mask = BIT(22), 1049 .hw.init = &(struct clk_init_data){ 1050 .name = "gcc_bimc_hmss_axi_clk", 1051 .ops = &clk_branch2_ops, 1052 }, 1053 }, 1054 }; 1055 1056 static struct clk_branch gcc_bimc_mss_q6_axi_clk = { 1057 .halt_reg = 0x4401c, 1058 .halt_check = BRANCH_HALT, 1059 .clkr = { 1060 .enable_reg = 0x4401c, 1061 .enable_mask = BIT(0), 1062 .hw.init = &(struct clk_init_data){ 1063 .name = "gcc_bimc_mss_q6_axi_clk", 1064 .ops = &clk_branch2_ops, 1065 }, 1066 }, 1067 }; 1068 1069 static struct clk_branch gcc_blsp1_ahb_clk = { 1070 .halt_reg = 0x17004, 1071 .halt_check = BRANCH_HALT_VOTED, 1072 .clkr = { 1073 .enable_reg = 0x52004, 1074 .enable_mask = BIT(17), 1075 .hw.init = &(struct clk_init_data){ 1076 .name = "gcc_blsp1_ahb_clk", 1077 .ops = &clk_branch2_ops, 1078 }, 1079 }, 1080 }; 1081 1082 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1083 .halt_reg = 0x19008, 1084 .halt_check = BRANCH_HALT, 1085 .clkr = { 1086 .enable_reg = 0x19008, 1087 .enable_mask = BIT(0), 1088 .hw.init = &(struct clk_init_data){ 1089 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1090 .parent_hws = (const struct clk_hw*[]) { 1091 &blsp1_qup1_i2c_apps_clk_src.clkr.hw, 1092 }, 1093 .num_parents = 1, 1094 .flags = CLK_SET_RATE_PARENT, 1095 .ops = &clk_branch2_ops, 1096 }, 1097 }, 1098 }; 1099 1100 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1101 .halt_reg = 0x19004, 1102 .halt_check = BRANCH_HALT, 1103 .clkr = { 1104 .enable_reg = 0x19004, 1105 .enable_mask = BIT(0), 1106 .hw.init = &(struct clk_init_data){ 1107 .name = "gcc_blsp1_qup1_spi_apps_clk", 1108 .parent_hws = (const struct clk_hw*[]) { 1109 &blsp1_qup1_spi_apps_clk_src.clkr.hw, 1110 }, 1111 .num_parents = 1, 1112 .flags = CLK_SET_RATE_PARENT, 1113 .ops = &clk_branch2_ops, 1114 }, 1115 }, 1116 }; 1117 1118 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1119 .halt_reg = 0x1b008, 1120 .halt_check = BRANCH_HALT, 1121 .clkr = { 1122 .enable_reg = 0x1b008, 1123 .enable_mask = BIT(0), 1124 .hw.init = &(struct clk_init_data){ 1125 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1126 .parent_hws = (const struct clk_hw*[]) { 1127 &blsp1_qup2_i2c_apps_clk_src.clkr.hw, 1128 }, 1129 .num_parents = 1, 1130 .flags = CLK_SET_RATE_PARENT, 1131 .ops = &clk_branch2_ops, 1132 }, 1133 }, 1134 }; 1135 1136 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1137 .halt_reg = 0x1b004, 1138 .halt_check = BRANCH_HALT, 1139 .clkr = { 1140 .enable_reg = 0x1b004, 1141 .enable_mask = BIT(0), 1142 .hw.init = &(struct clk_init_data){ 1143 .name = "gcc_blsp1_qup2_spi_apps_clk", 1144 .parent_hws = (const struct clk_hw*[]) { 1145 &blsp1_qup2_spi_apps_clk_src.clkr.hw, 1146 }, 1147 .num_parents = 1, 1148 .flags = CLK_SET_RATE_PARENT, 1149 .ops = &clk_branch2_ops, 1150 }, 1151 }, 1152 }; 1153 1154 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1155 .halt_reg = 0x1d008, 1156 .halt_check = BRANCH_HALT, 1157 .clkr = { 1158 .enable_reg = 0x1d008, 1159 .enable_mask = BIT(0), 1160 .hw.init = &(struct clk_init_data){ 1161 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1162 .parent_hws = (const struct clk_hw*[]) { 1163 &blsp1_qup3_i2c_apps_clk_src.clkr.hw, 1164 }, 1165 .num_parents = 1, 1166 .flags = CLK_SET_RATE_PARENT, 1167 .ops = &clk_branch2_ops, 1168 }, 1169 }, 1170 }; 1171 1172 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1173 .halt_reg = 0x1d004, 1174 .halt_check = BRANCH_HALT, 1175 .clkr = { 1176 .enable_reg = 0x1d004, 1177 .enable_mask = BIT(0), 1178 .hw.init = &(struct clk_init_data){ 1179 .name = "gcc_blsp1_qup3_spi_apps_clk", 1180 .parent_hws = (const struct clk_hw*[]) { 1181 &blsp1_qup3_spi_apps_clk_src.clkr.hw, 1182 }, 1183 .num_parents = 1, 1184 .flags = CLK_SET_RATE_PARENT, 1185 .ops = &clk_branch2_ops, 1186 }, 1187 }, 1188 }; 1189 1190 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1191 .halt_reg = 0x1f008, 1192 .halt_check = BRANCH_HALT, 1193 .clkr = { 1194 .enable_reg = 0x1f008, 1195 .enable_mask = BIT(0), 1196 .hw.init = &(struct clk_init_data){ 1197 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1198 .parent_hws = (const struct clk_hw*[]) { 1199 &blsp1_qup4_i2c_apps_clk_src.clkr.hw, 1200 }, 1201 .num_parents = 1, 1202 .flags = CLK_SET_RATE_PARENT, 1203 .ops = &clk_branch2_ops, 1204 }, 1205 }, 1206 }; 1207 1208 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1209 .halt_reg = 0x1f004, 1210 .halt_check = BRANCH_HALT, 1211 .clkr = { 1212 .enable_reg = 0x1f004, 1213 .enable_mask = BIT(0), 1214 .hw.init = &(struct clk_init_data){ 1215 .name = "gcc_blsp1_qup4_spi_apps_clk", 1216 .parent_hws = (const struct clk_hw*[]) { 1217 &blsp1_qup4_spi_apps_clk_src.clkr.hw, 1218 }, 1219 .num_parents = 1, 1220 .flags = CLK_SET_RATE_PARENT, 1221 .ops = &clk_branch2_ops, 1222 }, 1223 }, 1224 }; 1225 1226 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1227 .halt_reg = 0x1a004, 1228 .halt_check = BRANCH_HALT, 1229 .clkr = { 1230 .enable_reg = 0x1a004, 1231 .enable_mask = BIT(0), 1232 .hw.init = &(struct clk_init_data){ 1233 .name = "gcc_blsp1_uart1_apps_clk", 1234 .parent_hws = (const struct clk_hw*[]) { 1235 &blsp1_uart1_apps_clk_src.clkr.hw, 1236 }, 1237 .num_parents = 1, 1238 .flags = CLK_SET_RATE_PARENT, 1239 .ops = &clk_branch2_ops, 1240 }, 1241 }, 1242 }; 1243 1244 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1245 .halt_reg = 0x1c004, 1246 .halt_check = BRANCH_HALT, 1247 .clkr = { 1248 .enable_reg = 0x1c004, 1249 .enable_mask = BIT(0), 1250 .hw.init = &(struct clk_init_data){ 1251 .name = "gcc_blsp1_uart2_apps_clk", 1252 .parent_hws = (const struct clk_hw*[]) { 1253 &blsp1_uart2_apps_clk_src.clkr.hw, 1254 }, 1255 .num_parents = 1, 1256 .flags = CLK_SET_RATE_PARENT, 1257 .ops = &clk_branch2_ops, 1258 }, 1259 }, 1260 }; 1261 1262 static struct clk_branch gcc_blsp2_ahb_clk = { 1263 .halt_reg = 0x25004, 1264 .halt_check = BRANCH_HALT_VOTED, 1265 .clkr = { 1266 .enable_reg = 0x52004, 1267 .enable_mask = BIT(15), 1268 .hw.init = &(struct clk_init_data){ 1269 .name = "gcc_blsp2_ahb_clk", 1270 .ops = &clk_branch2_ops, 1271 }, 1272 }, 1273 }; 1274 1275 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { 1276 .halt_reg = 0x26008, 1277 .halt_check = BRANCH_HALT, 1278 .clkr = { 1279 .enable_reg = 0x26008, 1280 .enable_mask = BIT(0), 1281 .hw.init = &(struct clk_init_data){ 1282 .name = "gcc_blsp2_qup1_i2c_apps_clk", 1283 .parent_hws = (const struct clk_hw*[]) { 1284 &blsp2_qup1_i2c_apps_clk_src.clkr.hw, 1285 }, 1286 .num_parents = 1, 1287 .flags = CLK_SET_RATE_PARENT, 1288 .ops = &clk_branch2_ops, 1289 }, 1290 }, 1291 }; 1292 1293 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { 1294 .halt_reg = 0x26004, 1295 .halt_check = BRANCH_HALT, 1296 .clkr = { 1297 .enable_reg = 0x26004, 1298 .enable_mask = BIT(0), 1299 .hw.init = &(struct clk_init_data){ 1300 .name = "gcc_blsp2_qup1_spi_apps_clk", 1301 .parent_hws = (const struct clk_hw*[]) { 1302 &blsp2_qup1_spi_apps_clk_src.clkr.hw, 1303 }, 1304 .num_parents = 1, 1305 .flags = CLK_SET_RATE_PARENT, 1306 .ops = &clk_branch2_ops, 1307 }, 1308 }, 1309 }; 1310 1311 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { 1312 .halt_reg = 0x28008, 1313 .halt_check = BRANCH_HALT, 1314 .clkr = { 1315 .enable_reg = 0x28008, 1316 .enable_mask = BIT(0), 1317 .hw.init = &(struct clk_init_data){ 1318 .name = "gcc_blsp2_qup2_i2c_apps_clk", 1319 .parent_hws = (const struct clk_hw*[]) { 1320 &blsp2_qup2_i2c_apps_clk_src.clkr.hw, 1321 }, 1322 .num_parents = 1, 1323 .flags = CLK_SET_RATE_PARENT, 1324 .ops = &clk_branch2_ops, 1325 }, 1326 }, 1327 }; 1328 1329 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { 1330 .halt_reg = 0x28004, 1331 .halt_check = BRANCH_HALT, 1332 .clkr = { 1333 .enable_reg = 0x28004, 1334 .enable_mask = BIT(0), 1335 .hw.init = &(struct clk_init_data){ 1336 .name = "gcc_blsp2_qup2_spi_apps_clk", 1337 .parent_hws = (const struct clk_hw*[]) { 1338 &blsp2_qup2_spi_apps_clk_src.clkr.hw, 1339 }, 1340 .num_parents = 1, 1341 .flags = CLK_SET_RATE_PARENT, 1342 .ops = &clk_branch2_ops, 1343 }, 1344 }, 1345 }; 1346 1347 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { 1348 .halt_reg = 0x2a008, 1349 .halt_check = BRANCH_HALT, 1350 .clkr = { 1351 .enable_reg = 0x2a008, 1352 .enable_mask = BIT(0), 1353 .hw.init = &(struct clk_init_data){ 1354 .name = "gcc_blsp2_qup3_i2c_apps_clk", 1355 .parent_hws = (const struct clk_hw*[]) { 1356 &blsp2_qup3_i2c_apps_clk_src.clkr.hw, 1357 }, 1358 .num_parents = 1, 1359 .flags = CLK_SET_RATE_PARENT, 1360 .ops = &clk_branch2_ops, 1361 }, 1362 }, 1363 }; 1364 1365 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { 1366 .halt_reg = 0x2a004, 1367 .halt_check = BRANCH_HALT, 1368 .clkr = { 1369 .enable_reg = 0x2a004, 1370 .enable_mask = BIT(0), 1371 .hw.init = &(struct clk_init_data){ 1372 .name = "gcc_blsp2_qup3_spi_apps_clk", 1373 .parent_hws = (const struct clk_hw*[]) { 1374 &blsp2_qup3_spi_apps_clk_src.clkr.hw, 1375 }, 1376 .num_parents = 1, 1377 .flags = CLK_SET_RATE_PARENT, 1378 .ops = &clk_branch2_ops, 1379 }, 1380 }, 1381 }; 1382 1383 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { 1384 .halt_reg = 0x2c008, 1385 .halt_check = BRANCH_HALT, 1386 .clkr = { 1387 .enable_reg = 0x2c008, 1388 .enable_mask = BIT(0), 1389 .hw.init = &(struct clk_init_data){ 1390 .name = "gcc_blsp2_qup4_i2c_apps_clk", 1391 .parent_hws = (const struct clk_hw*[]) { 1392 &blsp2_qup4_i2c_apps_clk_src.clkr.hw, 1393 }, 1394 .num_parents = 1, 1395 .flags = CLK_SET_RATE_PARENT, 1396 .ops = &clk_branch2_ops, 1397 }, 1398 }, 1399 }; 1400 1401 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { 1402 .halt_reg = 0x2c004, 1403 .halt_check = BRANCH_HALT, 1404 .clkr = { 1405 .enable_reg = 0x2c004, 1406 .enable_mask = BIT(0), 1407 .hw.init = &(struct clk_init_data){ 1408 .name = "gcc_blsp2_qup4_spi_apps_clk", 1409 .parent_hws = (const struct clk_hw*[]) { 1410 &blsp2_qup4_spi_apps_clk_src.clkr.hw, 1411 }, 1412 .num_parents = 1, 1413 .flags = CLK_SET_RATE_PARENT, 1414 .ops = &clk_branch2_ops, 1415 }, 1416 }, 1417 }; 1418 1419 static struct clk_branch gcc_blsp2_uart1_apps_clk = { 1420 .halt_reg = 0x27004, 1421 .halt_check = BRANCH_HALT, 1422 .clkr = { 1423 .enable_reg = 0x27004, 1424 .enable_mask = BIT(0), 1425 .hw.init = &(struct clk_init_data){ 1426 .name = "gcc_blsp2_uart1_apps_clk", 1427 .parent_hws = (const struct clk_hw*[]) { 1428 &blsp2_uart1_apps_clk_src.clkr.hw, 1429 }, 1430 .num_parents = 1, 1431 .flags = CLK_SET_RATE_PARENT, 1432 .ops = &clk_branch2_ops, 1433 }, 1434 }, 1435 }; 1436 1437 static struct clk_branch gcc_blsp2_uart2_apps_clk = { 1438 .halt_reg = 0x29004, 1439 .halt_check = BRANCH_HALT, 1440 .clkr = { 1441 .enable_reg = 0x29004, 1442 .enable_mask = BIT(0), 1443 .hw.init = &(struct clk_init_data){ 1444 .name = "gcc_blsp2_uart2_apps_clk", 1445 .parent_hws = (const struct clk_hw*[]) { 1446 &blsp2_uart2_apps_clk_src.clkr.hw, 1447 }, 1448 .num_parents = 1, 1449 .flags = CLK_SET_RATE_PARENT, 1450 .ops = &clk_branch2_ops, 1451 }, 1452 }, 1453 }; 1454 1455 static struct clk_branch gcc_boot_rom_ahb_clk = { 1456 .halt_reg = 0x38004, 1457 .halt_check = BRANCH_HALT_VOTED, 1458 .clkr = { 1459 .enable_reg = 0x52004, 1460 .enable_mask = BIT(10), 1461 .hw.init = &(struct clk_init_data){ 1462 .name = "gcc_boot_rom_ahb_clk", 1463 .ops = &clk_branch2_ops, 1464 }, 1465 }, 1466 }; 1467 1468 static struct clk_branch gcc_cfg_noc_usb2_axi_clk = { 1469 .halt_reg = 0x5058, 1470 .halt_check = BRANCH_HALT, 1471 .clkr = { 1472 .enable_reg = 0x5058, 1473 .enable_mask = BIT(0), 1474 .hw.init = &(struct clk_init_data){ 1475 .name = "gcc_cfg_noc_usb2_axi_clk", 1476 .parent_hws = (const struct clk_hw*[]) { 1477 &usb20_master_clk_src.clkr.hw, 1478 }, 1479 .num_parents = 1, 1480 .ops = &clk_branch2_ops, 1481 }, 1482 }, 1483 }; 1484 1485 static struct clk_branch gcc_cfg_noc_usb3_axi_clk = { 1486 .halt_reg = 0x5018, 1487 .halt_check = BRANCH_HALT, 1488 .clkr = { 1489 .enable_reg = 0x5018, 1490 .enable_mask = BIT(0), 1491 .hw.init = &(struct clk_init_data){ 1492 .name = "gcc_cfg_noc_usb3_axi_clk", 1493 .parent_hws = (const struct clk_hw*[]) { 1494 &usb30_master_clk_src.clkr.hw, 1495 }, 1496 .num_parents = 1, 1497 .ops = &clk_branch2_ops, 1498 }, 1499 }, 1500 }; 1501 1502 static struct clk_branch gcc_dcc_ahb_clk = { 1503 .halt_reg = 0x84004, 1504 .clkr = { 1505 .enable_reg = 0x84004, 1506 .enable_mask = BIT(0), 1507 .hw.init = &(struct clk_init_data){ 1508 .name = "gcc_dcc_ahb_clk", 1509 .ops = &clk_branch2_ops, 1510 }, 1511 }, 1512 }; 1513 1514 static struct clk_branch gcc_gp1_clk = { 1515 .halt_reg = 0x64000, 1516 .halt_check = BRANCH_HALT, 1517 .clkr = { 1518 .enable_reg = 0x64000, 1519 .enable_mask = BIT(0), 1520 .hw.init = &(struct clk_init_data){ 1521 .name = "gcc_gp1_clk", 1522 .parent_hws = (const struct clk_hw*[]) { 1523 &gp1_clk_src.clkr.hw, 1524 }, 1525 .num_parents = 1, 1526 .flags = CLK_SET_RATE_PARENT, 1527 .ops = &clk_branch2_ops, 1528 }, 1529 }, 1530 }; 1531 1532 static struct clk_branch gcc_gp2_clk = { 1533 .halt_reg = 0x65000, 1534 .halt_check = BRANCH_HALT, 1535 .clkr = { 1536 .enable_reg = 0x65000, 1537 .enable_mask = BIT(0), 1538 .hw.init = &(struct clk_init_data){ 1539 .name = "gcc_gp2_clk", 1540 .parent_hws = (const struct clk_hw*[]) { 1541 &gp2_clk_src.clkr.hw, 1542 }, 1543 .num_parents = 1, 1544 .flags = CLK_SET_RATE_PARENT, 1545 .ops = &clk_branch2_ops, 1546 }, 1547 }, 1548 }; 1549 1550 static struct clk_branch gcc_gp3_clk = { 1551 .halt_reg = 0x66000, 1552 .halt_check = BRANCH_HALT, 1553 .clkr = { 1554 .enable_reg = 0x66000, 1555 .enable_mask = BIT(0), 1556 .hw.init = &(struct clk_init_data){ 1557 .name = "gcc_gp3_clk", 1558 .parent_hws = (const struct clk_hw*[]) { 1559 &gp3_clk_src.clkr.hw, 1560 }, 1561 .num_parents = 1, 1562 .flags = CLK_SET_RATE_PARENT, 1563 .ops = &clk_branch2_ops, 1564 }, 1565 }, 1566 }; 1567 1568 static struct clk_branch gcc_gpu_bimc_gfx_clk = { 1569 .halt_reg = 0x71010, 1570 .halt_check = BRANCH_VOTED, 1571 .clkr = { 1572 .enable_reg = 0x71010, 1573 .enable_mask = BIT(0), 1574 .hw.init = &(struct clk_init_data){ 1575 .name = "gcc_gpu_bimc_gfx_clk", 1576 .ops = &clk_branch2_ops, 1577 }, 1578 }, 1579 }; 1580 1581 static struct clk_branch gcc_gpu_cfg_ahb_clk = { 1582 .halt_reg = 0x71004, 1583 .halt_check = BRANCH_VOTED, 1584 .clkr = { 1585 .enable_reg = 0x71004, 1586 .enable_mask = BIT(0), 1587 .hw.init = &(struct clk_init_data){ 1588 .name = "gcc_gpu_cfg_ahb_clk", 1589 .ops = &clk_branch2_ops, 1590 .flags = CLK_IS_CRITICAL, 1591 }, 1592 }, 1593 }; 1594 1595 static struct clk_branch gcc_gpu_gpll0_clk = { 1596 .halt_reg = 0x5200c, 1597 .halt_check = BRANCH_HALT_DELAY, 1598 .clkr = { 1599 .enable_reg = 0x5200c, 1600 .enable_mask = BIT(4), 1601 .hw.init = &(struct clk_init_data){ 1602 .name = "gcc_gpu_gpll0_clk", 1603 .parent_hws = (const struct clk_hw*[]) { 1604 &gpll0.clkr.hw, 1605 }, 1606 .num_parents = 1, 1607 .ops = &clk_branch2_ops, 1608 }, 1609 }, 1610 }; 1611 1612 static struct clk_branch gcc_gpu_gpll0_div_clk = { 1613 .halt_reg = 0x5200c, 1614 .halt_check = BRANCH_HALT_DELAY, 1615 .clkr = { 1616 .enable_reg = 0x5200c, 1617 .enable_mask = BIT(3), 1618 .hw.init = &(struct clk_init_data){ 1619 .name = "gcc_gpu_gpll0_div_clk", 1620 .parent_hws = (const struct clk_hw*[]) { 1621 &gpll0_early_div.hw, 1622 }, 1623 .num_parents = 1, 1624 .ops = &clk_branch2_ops, 1625 }, 1626 }, 1627 }; 1628 1629 static struct clk_branch gcc_hmss_dvm_bus_clk = { 1630 .halt_reg = 0x4808c, 1631 .halt_check = BRANCH_HALT, 1632 .clkr = { 1633 .enable_reg = 0x4808c, 1634 .enable_mask = BIT(0), 1635 .hw.init = &(struct clk_init_data){ 1636 .name = "gcc_hmss_dvm_bus_clk", 1637 .ops = &clk_branch2_ops, 1638 .flags = CLK_IGNORE_UNUSED, 1639 }, 1640 }, 1641 }; 1642 1643 static struct clk_branch gcc_hmss_rbcpr_clk = { 1644 .halt_reg = 0x48008, 1645 .halt_check = BRANCH_HALT, 1646 .clkr = { 1647 .enable_reg = 0x48008, 1648 .enable_mask = BIT(0), 1649 .hw.init = &(struct clk_init_data){ 1650 .name = "gcc_hmss_rbcpr_clk", 1651 .parent_hws = (const struct clk_hw*[]) { 1652 &hmss_rbcpr_clk_src.clkr.hw, 1653 }, 1654 .num_parents = 1, 1655 .flags = CLK_SET_RATE_PARENT, 1656 .ops = &clk_branch2_ops, 1657 }, 1658 }, 1659 }; 1660 1661 static struct clk_branch gcc_mmss_gpll0_clk = { 1662 .halt_reg = 0x5200c, 1663 .halt_check = BRANCH_HALT_DELAY, 1664 .clkr = { 1665 .enable_reg = 0x5200c, 1666 .enable_mask = BIT(1), 1667 .hw.init = &(struct clk_init_data){ 1668 .name = "gcc_mmss_gpll0_clk", 1669 .parent_hws = (const struct clk_hw*[]) { 1670 &gpll0.clkr.hw, 1671 }, 1672 .num_parents = 1, 1673 .ops = &clk_branch2_ops, 1674 }, 1675 }, 1676 }; 1677 1678 static struct clk_branch gcc_mmss_gpll0_div_clk = { 1679 .halt_reg = 0x5200c, 1680 .halt_check = BRANCH_HALT_DELAY, 1681 .clkr = { 1682 .enable_reg = 0x5200c, 1683 .enable_mask = BIT(0), 1684 .hw.init = &(struct clk_init_data){ 1685 .name = "gcc_mmss_gpll0_div_clk", 1686 .parent_hws = (const struct clk_hw*[]) { 1687 &gpll0_early_div.hw, 1688 }, 1689 .num_parents = 1, 1690 .ops = &clk_branch2_ops, 1691 }, 1692 }, 1693 }; 1694 1695 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { 1696 .halt_reg = 0x9004, 1697 .halt_check = BRANCH_HALT, 1698 .clkr = { 1699 .enable_reg = 0x9004, 1700 .enable_mask = BIT(0), 1701 .hw.init = &(struct clk_init_data){ 1702 .name = "gcc_mmss_noc_cfg_ahb_clk", 1703 .ops = &clk_branch2_ops, 1704 /* 1705 * Any access to mmss depends on this clock. 1706 * Gating this clock has been shown to crash the system 1707 * when mmssnoc_axi_rpm_clk is inited in rpmcc. 1708 */ 1709 .flags = CLK_IS_CRITICAL, 1710 }, 1711 }, 1712 }; 1713 1714 static struct clk_branch gcc_mmss_sys_noc_axi_clk = { 1715 .halt_reg = 0x9000, 1716 .halt_check = BRANCH_HALT, 1717 .clkr = { 1718 .enable_reg = 0x9000, 1719 .enable_mask = BIT(0), 1720 .hw.init = &(struct clk_init_data){ 1721 .name = "gcc_mmss_sys_noc_axi_clk", 1722 .ops = &clk_branch2_ops, 1723 }, 1724 }, 1725 }; 1726 1727 static struct clk_branch gcc_mss_cfg_ahb_clk = { 1728 .halt_reg = 0x8a000, 1729 .clkr = { 1730 .enable_reg = 0x8a000, 1731 .enable_mask = BIT(0), 1732 .hw.init = &(struct clk_init_data){ 1733 .name = "gcc_mss_cfg_ahb_clk", 1734 .ops = &clk_branch2_ops, 1735 }, 1736 }, 1737 }; 1738 1739 static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = { 1740 .halt_reg = 0x8a004, 1741 .halt_check = BRANCH_HALT, 1742 .hwcg_reg = 0x8a004, 1743 .hwcg_bit = 1, 1744 .clkr = { 1745 .enable_reg = 0x8a004, 1746 .enable_mask = BIT(0), 1747 .hw.init = &(struct clk_init_data){ 1748 .name = "gcc_mss_mnoc_bimc_axi_clk", 1749 .ops = &clk_branch2_ops, 1750 }, 1751 }, 1752 }; 1753 1754 static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 1755 .halt_reg = 0x8a040, 1756 .clkr = { 1757 .enable_reg = 0x8a040, 1758 .enable_mask = BIT(0), 1759 .hw.init = &(struct clk_init_data){ 1760 .name = "gcc_mss_q6_bimc_axi_clk", 1761 .ops = &clk_branch2_ops, 1762 }, 1763 }, 1764 }; 1765 1766 static struct clk_branch gcc_mss_snoc_axi_clk = { 1767 .halt_reg = 0x8a03c, 1768 .clkr = { 1769 .enable_reg = 0x8a03c, 1770 .enable_mask = BIT(0), 1771 .hw.init = &(struct clk_init_data){ 1772 .name = "gcc_mss_snoc_axi_clk", 1773 .ops = &clk_branch2_ops, 1774 }, 1775 }, 1776 }; 1777 1778 static struct clk_branch gcc_pdm2_clk = { 1779 .halt_reg = 0x3300c, 1780 .halt_check = BRANCH_HALT, 1781 .clkr = { 1782 .enable_reg = 0x3300c, 1783 .enable_mask = BIT(0), 1784 .hw.init = &(struct clk_init_data){ 1785 .name = "gcc_pdm2_clk", 1786 .parent_hws = (const struct clk_hw*[]) { 1787 &pdm2_clk_src.clkr.hw, 1788 }, 1789 .num_parents = 1, 1790 .flags = CLK_SET_RATE_PARENT, 1791 .ops = &clk_branch2_ops, 1792 }, 1793 }, 1794 }; 1795 1796 static struct clk_branch gcc_pdm_ahb_clk = { 1797 .halt_reg = 0x33004, 1798 .halt_check = BRANCH_HALT, 1799 .clkr = { 1800 .enable_reg = 0x33004, 1801 .enable_mask = BIT(0), 1802 .hw.init = &(struct clk_init_data){ 1803 .name = "gcc_pdm_ahb_clk", 1804 .ops = &clk_branch2_ops, 1805 }, 1806 }, 1807 }; 1808 1809 static struct clk_branch gcc_prng_ahb_clk = { 1810 .halt_reg = 0x34004, 1811 .halt_check = BRANCH_HALT_VOTED, 1812 .clkr = { 1813 .enable_reg = 0x52004, 1814 .enable_mask = BIT(13), 1815 .hw.init = &(struct clk_init_data){ 1816 .name = "gcc_prng_ahb_clk", 1817 .ops = &clk_branch2_ops, 1818 }, 1819 }, 1820 }; 1821 1822 static struct clk_branch gcc_qspi_ahb_clk = { 1823 .halt_reg = 0x4d004, 1824 .halt_check = BRANCH_HALT, 1825 .clkr = { 1826 .enable_reg = 0x4d004, 1827 .enable_mask = BIT(0), 1828 .hw.init = &(struct clk_init_data){ 1829 .name = "gcc_qspi_ahb_clk", 1830 .ops = &clk_branch2_ops, 1831 }, 1832 }, 1833 }; 1834 1835 static struct clk_branch gcc_qspi_ser_clk = { 1836 .halt_reg = 0x4d008, 1837 .halt_check = BRANCH_HALT, 1838 .clkr = { 1839 .enable_reg = 0x4d008, 1840 .enable_mask = BIT(0), 1841 .hw.init = &(struct clk_init_data){ 1842 .name = "gcc_qspi_ser_clk", 1843 .parent_hws = (const struct clk_hw*[]) { 1844 &qspi_ser_clk_src.clkr.hw, 1845 }, 1846 .num_parents = 1, 1847 .flags = CLK_SET_RATE_PARENT, 1848 .ops = &clk_branch2_ops, 1849 }, 1850 }, 1851 }; 1852 1853 static struct clk_branch gcc_rx0_usb2_clkref_clk = { 1854 .halt_reg = 0x88018, 1855 .halt_check = BRANCH_HALT_VOTED, 1856 .clkr = { 1857 .enable_reg = 0x88018, 1858 .enable_mask = BIT(0), 1859 .hw.init = &(struct clk_init_data){ 1860 .name = "gcc_rx0_usb2_clkref_clk", 1861 .ops = &clk_branch2_ops, 1862 }, 1863 }, 1864 }; 1865 1866 static struct clk_branch gcc_rx1_usb2_clkref_clk = { 1867 .halt_reg = 0x88014, 1868 .halt_check = BRANCH_HALT_VOTED, 1869 .clkr = { 1870 .enable_reg = 0x88014, 1871 .enable_mask = BIT(0), 1872 .hw.init = &(struct clk_init_data){ 1873 .name = "gcc_rx1_usb2_clkref_clk", 1874 .ops = &clk_branch2_ops, 1875 }, 1876 }, 1877 }; 1878 1879 static struct clk_branch gcc_sdcc1_ahb_clk = { 1880 .halt_reg = 0x16008, 1881 .halt_check = BRANCH_HALT, 1882 .clkr = { 1883 .enable_reg = 0x16008, 1884 .enable_mask = BIT(0), 1885 .hw.init = &(struct clk_init_data){ 1886 .name = "gcc_sdcc1_ahb_clk", 1887 .ops = &clk_branch2_ops, 1888 }, 1889 }, 1890 }; 1891 1892 static struct clk_branch gcc_sdcc1_apps_clk = { 1893 .halt_reg = 0x16004, 1894 .halt_check = BRANCH_HALT, 1895 .clkr = { 1896 .enable_reg = 0x16004, 1897 .enable_mask = BIT(0), 1898 .hw.init = &(struct clk_init_data){ 1899 .name = "gcc_sdcc1_apps_clk", 1900 .parent_hws = (const struct clk_hw*[]) { 1901 &sdcc1_apps_clk_src.clkr.hw, 1902 }, 1903 .num_parents = 1, 1904 .flags = CLK_SET_RATE_PARENT, 1905 .ops = &clk_branch2_ops, 1906 }, 1907 }, 1908 }; 1909 1910 static struct clk_branch gcc_sdcc1_ice_core_clk = { 1911 .halt_reg = 0x1600c, 1912 .halt_check = BRANCH_HALT, 1913 .clkr = { 1914 .enable_reg = 0x1600c, 1915 .enable_mask = BIT(0), 1916 .hw.init = &(struct clk_init_data){ 1917 .name = "gcc_sdcc1_ice_core_clk", 1918 .parent_hws = (const struct clk_hw*[]) { 1919 &sdcc1_ice_core_clk_src.clkr.hw, 1920 }, 1921 .num_parents = 1, 1922 .flags = CLK_SET_RATE_PARENT, 1923 .ops = &clk_branch2_ops, 1924 }, 1925 }, 1926 }; 1927 1928 static struct clk_branch gcc_sdcc2_ahb_clk = { 1929 .halt_reg = 0x14008, 1930 .halt_check = BRANCH_HALT, 1931 .clkr = { 1932 .enable_reg = 0x14008, 1933 .enable_mask = BIT(0), 1934 .hw.init = &(struct clk_init_data){ 1935 .name = "gcc_sdcc2_ahb_clk", 1936 .ops = &clk_branch2_ops, 1937 }, 1938 }, 1939 }; 1940 1941 static struct clk_branch gcc_sdcc2_apps_clk = { 1942 .halt_reg = 0x14004, 1943 .halt_check = BRANCH_HALT, 1944 .clkr = { 1945 .enable_reg = 0x14004, 1946 .enable_mask = BIT(0), 1947 .hw.init = &(struct clk_init_data){ 1948 .name = "gcc_sdcc2_apps_clk", 1949 .parent_hws = (const struct clk_hw*[]) { 1950 &sdcc2_apps_clk_src.clkr.hw, 1951 }, 1952 .num_parents = 1, 1953 .flags = CLK_SET_RATE_PARENT, 1954 .ops = &clk_branch2_ops, 1955 }, 1956 }, 1957 }; 1958 1959 static struct clk_branch gcc_ufs_ahb_clk = { 1960 .halt_reg = 0x7500c, 1961 .halt_check = BRANCH_HALT, 1962 .clkr = { 1963 .enable_reg = 0x7500c, 1964 .enable_mask = BIT(0), 1965 .hw.init = &(struct clk_init_data){ 1966 .name = "gcc_ufs_ahb_clk", 1967 .ops = &clk_branch2_ops, 1968 }, 1969 }, 1970 }; 1971 1972 static struct clk_branch gcc_ufs_axi_clk = { 1973 .halt_reg = 0x75008, 1974 .halt_check = BRANCH_HALT, 1975 .clkr = { 1976 .enable_reg = 0x75008, 1977 .enable_mask = BIT(0), 1978 .hw.init = &(struct clk_init_data){ 1979 .name = "gcc_ufs_axi_clk", 1980 .parent_hws = (const struct clk_hw*[]) { 1981 &ufs_axi_clk_src.clkr.hw, 1982 }, 1983 .num_parents = 1, 1984 .flags = CLK_SET_RATE_PARENT, 1985 .ops = &clk_branch2_ops, 1986 }, 1987 }, 1988 }; 1989 1990 static struct clk_branch gcc_ufs_clkref_clk = { 1991 .halt_reg = 0x88008, 1992 .halt_check = BRANCH_HALT, 1993 .clkr = { 1994 .enable_reg = 0x88008, 1995 .enable_mask = BIT(0), 1996 .hw.init = &(struct clk_init_data){ 1997 .name = "gcc_ufs_clkref_clk", 1998 .ops = &clk_branch2_ops, 1999 }, 2000 }, 2001 }; 2002 2003 static struct clk_branch gcc_ufs_ice_core_clk = { 2004 .halt_reg = 0x7600c, 2005 .halt_check = BRANCH_HALT, 2006 .clkr = { 2007 .enable_reg = 0x7600c, 2008 .enable_mask = BIT(0), 2009 .hw.init = &(struct clk_init_data){ 2010 .name = "gcc_ufs_ice_core_clk", 2011 .parent_hws = (const struct clk_hw*[]) { 2012 &ufs_ice_core_clk_src.clkr.hw, 2013 }, 2014 .num_parents = 1, 2015 .flags = CLK_SET_RATE_PARENT, 2016 .ops = &clk_branch2_ops, 2017 }, 2018 }, 2019 }; 2020 2021 static struct clk_branch gcc_ufs_phy_aux_clk = { 2022 .halt_reg = 0x76040, 2023 .halt_check = BRANCH_HALT, 2024 .clkr = { 2025 .enable_reg = 0x76040, 2026 .enable_mask = BIT(0), 2027 .hw.init = &(struct clk_init_data){ 2028 .name = "gcc_ufs_phy_aux_clk", 2029 .parent_hws = (const struct clk_hw*[]) { 2030 &ufs_phy_aux_clk_src.clkr.hw, 2031 }, 2032 .num_parents = 1, 2033 .flags = CLK_SET_RATE_PARENT, 2034 .ops = &clk_branch2_ops, 2035 }, 2036 }, 2037 }; 2038 2039 static struct clk_branch gcc_ufs_rx_symbol_0_clk = { 2040 .halt_reg = 0x75014, 2041 .halt_check = BRANCH_HALT_SKIP, 2042 .clkr = { 2043 .enable_reg = 0x75014, 2044 .enable_mask = BIT(0), 2045 .hw.init = &(struct clk_init_data){ 2046 .name = "gcc_ufs_rx_symbol_0_clk", 2047 .ops = &clk_branch2_ops, 2048 }, 2049 }, 2050 }; 2051 2052 static struct clk_branch gcc_ufs_rx_symbol_1_clk = { 2053 .halt_reg = 0x7605c, 2054 .halt_check = BRANCH_HALT_SKIP, 2055 .clkr = { 2056 .enable_reg = 0x7605c, 2057 .enable_mask = BIT(0), 2058 .hw.init = &(struct clk_init_data){ 2059 .name = "gcc_ufs_rx_symbol_1_clk", 2060 .ops = &clk_branch2_ops, 2061 }, 2062 }, 2063 }; 2064 2065 static struct clk_branch gcc_ufs_tx_symbol_0_clk = { 2066 .halt_reg = 0x75010, 2067 .halt_check = BRANCH_HALT_SKIP, 2068 .clkr = { 2069 .enable_reg = 0x75010, 2070 .enable_mask = BIT(0), 2071 .hw.init = &(struct clk_init_data){ 2072 .name = "gcc_ufs_tx_symbol_0_clk", 2073 .ops = &clk_branch2_ops, 2074 }, 2075 }, 2076 }; 2077 2078 static struct clk_branch gcc_ufs_unipro_core_clk = { 2079 .halt_reg = 0x76008, 2080 .halt_check = BRANCH_HALT, 2081 .clkr = { 2082 .enable_reg = 0x76008, 2083 .enable_mask = BIT(0), 2084 .hw.init = &(struct clk_init_data){ 2085 .name = "gcc_ufs_unipro_core_clk", 2086 .parent_hws = (const struct clk_hw*[]) { 2087 &ufs_unipro_core_clk_src.clkr.hw, 2088 }, 2089 .flags = CLK_SET_RATE_PARENT, 2090 .num_parents = 1, 2091 .ops = &clk_branch2_ops, 2092 }, 2093 }, 2094 }; 2095 2096 static struct clk_branch gcc_usb20_master_clk = { 2097 .halt_reg = 0x2f004, 2098 .halt_check = BRANCH_HALT, 2099 .clkr = { 2100 .enable_reg = 0x2f004, 2101 .enable_mask = BIT(0), 2102 .hw.init = &(struct clk_init_data){ 2103 .name = "gcc_usb20_master_clk", 2104 .parent_hws = (const struct clk_hw*[]) { 2105 &usb20_master_clk_src.clkr.hw, 2106 }, 2107 .flags = CLK_SET_RATE_PARENT, 2108 .num_parents = 1, 2109 .ops = &clk_branch2_ops, 2110 }, 2111 }, 2112 }; 2113 2114 static struct clk_branch gcc_usb20_mock_utmi_clk = { 2115 .halt_reg = 0x2f00c, 2116 .halt_check = BRANCH_HALT, 2117 .clkr = { 2118 .enable_reg = 0x2f00c, 2119 .enable_mask = BIT(0), 2120 .hw.init = &(struct clk_init_data){ 2121 .name = "gcc_usb20_mock_utmi_clk", 2122 .parent_hws = (const struct clk_hw*[]) { 2123 &usb20_mock_utmi_clk_src.clkr.hw, 2124 }, 2125 .num_parents = 1, 2126 .flags = CLK_SET_RATE_PARENT, 2127 .ops = &clk_branch2_ops, 2128 }, 2129 }, 2130 }; 2131 2132 static struct clk_branch gcc_usb20_sleep_clk = { 2133 .halt_reg = 0x2f008, 2134 .halt_check = BRANCH_HALT, 2135 .clkr = { 2136 .enable_reg = 0x2f008, 2137 .enable_mask = BIT(0), 2138 .hw.init = &(struct clk_init_data){ 2139 .name = "gcc_usb20_sleep_clk", 2140 .ops = &clk_branch2_ops, 2141 }, 2142 }, 2143 }; 2144 2145 static struct clk_branch gcc_usb30_master_clk = { 2146 .halt_reg = 0xf008, 2147 .halt_check = BRANCH_HALT, 2148 .clkr = { 2149 .enable_reg = 0xf008, 2150 .enable_mask = BIT(0), 2151 .hw.init = &(struct clk_init_data){ 2152 .name = "gcc_usb30_master_clk", 2153 .parent_hws = (const struct clk_hw*[]) { 2154 &usb30_master_clk_src.clkr.hw, 2155 }, 2156 .num_parents = 1, 2157 .flags = CLK_SET_RATE_PARENT, 2158 .ops = &clk_branch2_ops, 2159 }, 2160 }, 2161 }; 2162 2163 static struct clk_branch gcc_usb30_mock_utmi_clk = { 2164 .halt_reg = 0xf010, 2165 .halt_check = BRANCH_HALT, 2166 .clkr = { 2167 .enable_reg = 0xf010, 2168 .enable_mask = BIT(0), 2169 .hw.init = &(struct clk_init_data){ 2170 .name = "gcc_usb30_mock_utmi_clk", 2171 .parent_hws = (const struct clk_hw*[]) { 2172 &usb30_mock_utmi_clk_src.clkr.hw, 2173 }, 2174 .num_parents = 1, 2175 .flags = CLK_SET_RATE_PARENT, 2176 .ops = &clk_branch2_ops, 2177 }, 2178 }, 2179 }; 2180 2181 static struct clk_branch gcc_usb30_sleep_clk = { 2182 .halt_reg = 0xf00c, 2183 .halt_check = BRANCH_HALT, 2184 .clkr = { 2185 .enable_reg = 0xf00c, 2186 .enable_mask = BIT(0), 2187 .hw.init = &(struct clk_init_data){ 2188 .name = "gcc_usb30_sleep_clk", 2189 .ops = &clk_branch2_ops, 2190 }, 2191 }, 2192 }; 2193 2194 static struct clk_branch gcc_usb3_clkref_clk = { 2195 .halt_reg = 0x8800c, 2196 .halt_check = BRANCH_HALT, 2197 .clkr = { 2198 .enable_reg = 0x8800c, 2199 .enable_mask = BIT(0), 2200 .hw.init = &(struct clk_init_data){ 2201 .name = "gcc_usb3_clkref_clk", 2202 .ops = &clk_branch2_ops, 2203 }, 2204 }, 2205 }; 2206 2207 static struct clk_branch gcc_usb3_phy_aux_clk = { 2208 .halt_reg = 0x50000, 2209 .halt_check = BRANCH_HALT, 2210 .clkr = { 2211 .enable_reg = 0x50000, 2212 .enable_mask = BIT(0), 2213 .hw.init = &(struct clk_init_data){ 2214 .name = "gcc_usb3_phy_aux_clk", 2215 .parent_hws = (const struct clk_hw*[]) { 2216 &usb3_phy_aux_clk_src.clkr.hw, 2217 }, 2218 .num_parents = 1, 2219 .flags = CLK_SET_RATE_PARENT, 2220 .ops = &clk_branch2_ops, 2221 }, 2222 }, 2223 }; 2224 2225 static struct clk_branch gcc_usb3_phy_pipe_clk = { 2226 .halt_reg = 0x50004, 2227 .halt_check = BRANCH_HALT_DELAY, 2228 .clkr = { 2229 .enable_reg = 0x50004, 2230 .enable_mask = BIT(0), 2231 .hw.init = &(struct clk_init_data){ 2232 .name = "gcc_usb3_phy_pipe_clk", 2233 .ops = &clk_branch2_ops, 2234 }, 2235 }, 2236 }; 2237 2238 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 2239 .halt_reg = 0x6a004, 2240 .halt_check = BRANCH_HALT, 2241 .clkr = { 2242 .enable_reg = 0x6a004, 2243 .enable_mask = BIT(0), 2244 .hw.init = &(struct clk_init_data){ 2245 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2246 .ops = &clk_branch2_ops, 2247 }, 2248 }, 2249 }; 2250 2251 static struct gdsc ufs_gdsc = { 2252 .gdscr = 0x75004, 2253 .gds_hw_ctrl = 0x0, 2254 .pd = { 2255 .name = "ufs_gdsc", 2256 }, 2257 .pwrsts = PWRSTS_OFF_ON, 2258 .flags = VOTABLE, 2259 }; 2260 2261 static struct gdsc usb_30_gdsc = { 2262 .gdscr = 0xf004, 2263 .gds_hw_ctrl = 0x0, 2264 .pd = { 2265 .name = "usb_30_gdsc", 2266 }, 2267 .pwrsts = PWRSTS_OFF_ON, 2268 .flags = VOTABLE, 2269 }; 2270 2271 static struct gdsc pcie_0_gdsc = { 2272 .gdscr = 0x6b004, 2273 .gds_hw_ctrl = 0x0, 2274 .pd = { 2275 .name = "pcie_0_gdsc", 2276 }, 2277 .pwrsts = PWRSTS_OFF_ON, 2278 .flags = VOTABLE, 2279 }; 2280 2281 static struct clk_hw *gcc_sdm660_hws[] = { 2282 &xo.hw, 2283 &gpll0_early_div.hw, 2284 &gpll1_early_div.hw, 2285 }; 2286 2287 static struct clk_regmap *gcc_sdm660_clocks[] = { 2288 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2289 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2290 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2291 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2292 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2293 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2294 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2295 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2296 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2297 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2298 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, 2299 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, 2300 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, 2301 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, 2302 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, 2303 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, 2304 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, 2305 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, 2306 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, 2307 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, 2308 [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr, 2309 [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr, 2310 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, 2311 [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr, 2312 [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr, 2313 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2314 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2315 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2316 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2317 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2318 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2319 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2320 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 2321 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 2322 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2323 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2324 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, 2325 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, 2326 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, 2327 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, 2328 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, 2329 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, 2330 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, 2331 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, 2332 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, 2333 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, 2334 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, 2335 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2336 [GCC_CFG_NOC_USB2_AXI_CLK] = &gcc_cfg_noc_usb2_axi_clk.clkr, 2337 [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr, 2338 [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr, 2339 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2340 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2341 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2342 [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr, 2343 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 2344 [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr, 2345 [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr, 2346 [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr, 2347 [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr, 2348 [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr, 2349 [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr, 2350 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr, 2351 [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr, 2352 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 2353 [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr, 2354 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 2355 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, 2356 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2357 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2358 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2359 [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr, 2360 [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr, 2361 [GCC_RX0_USB2_CLKREF_CLK] = &gcc_rx0_usb2_clkref_clk.clkr, 2362 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr, 2363 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2364 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2365 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 2366 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2367 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2368 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, 2369 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, 2370 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, 2371 [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr, 2372 [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr, 2373 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, 2374 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, 2375 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, 2376 [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr, 2377 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr, 2378 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr, 2379 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr, 2380 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, 2381 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 2382 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 2383 [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr, 2384 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, 2385 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, 2386 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 2387 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 2388 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 2389 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 2390 [GPLL0] = &gpll0.clkr, 2391 [GPLL0_EARLY] = &gpll0_early.clkr, 2392 [GPLL1] = &gpll1.clkr, 2393 [GPLL1_EARLY] = &gpll1_early.clkr, 2394 [GPLL4] = &gpll4.clkr, 2395 [GPLL4_EARLY] = &gpll4_early.clkr, 2396 [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr, 2397 [HMSS_GPLL4_CLK_SRC] = &hmss_gpll4_clk_src.clkr, 2398 [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr, 2399 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 2400 [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr, 2401 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 2402 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr, 2403 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 2404 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, 2405 [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr, 2406 [UFS_PHY_AUX_CLK_SRC] = &ufs_phy_aux_clk_src.clkr, 2407 [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr, 2408 [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr, 2409 [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr, 2410 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, 2411 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 2412 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, 2413 }; 2414 2415 static struct gdsc *gcc_sdm660_gdscs[] = { 2416 [UFS_GDSC] = &ufs_gdsc, 2417 [USB_30_GDSC] = &usb_30_gdsc, 2418 [PCIE_0_GDSC] = &pcie_0_gdsc, 2419 }; 2420 2421 static const struct qcom_reset_map gcc_sdm660_resets[] = { 2422 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 2423 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 2424 [GCC_UFS_BCR] = { 0x75000 }, 2425 [GCC_USB3_DP_PHY_BCR] = { 0x50028 }, 2426 [GCC_USB3_PHY_BCR] = { 0x50020 }, 2427 [GCC_USB3PHY_PHY_BCR] = { 0x50024 }, 2428 [GCC_USB_20_BCR] = { 0x2f000 }, 2429 [GCC_USB_30_BCR] = { 0xf000 }, 2430 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 2431 [GCC_MSS_RESTART] = { 0x79000 }, 2432 }; 2433 2434 static const struct regmap_config gcc_sdm660_regmap_config = { 2435 .reg_bits = 32, 2436 .reg_stride = 4, 2437 .val_bits = 32, 2438 .max_register = 0x94000, 2439 .fast_io = true, 2440 }; 2441 2442 static const struct qcom_cc_desc gcc_sdm660_desc = { 2443 .config = &gcc_sdm660_regmap_config, 2444 .clks = gcc_sdm660_clocks, 2445 .num_clks = ARRAY_SIZE(gcc_sdm660_clocks), 2446 .resets = gcc_sdm660_resets, 2447 .num_resets = ARRAY_SIZE(gcc_sdm660_resets), 2448 .gdscs = gcc_sdm660_gdscs, 2449 .num_gdscs = ARRAY_SIZE(gcc_sdm660_gdscs), 2450 .clk_hws = gcc_sdm660_hws, 2451 .num_clk_hws = ARRAY_SIZE(gcc_sdm660_hws), 2452 }; 2453 2454 static const struct of_device_id gcc_sdm660_match_table[] = { 2455 { .compatible = "qcom,gcc-sdm630" }, 2456 { .compatible = "qcom,gcc-sdm660" }, 2457 { } 2458 }; 2459 MODULE_DEVICE_TABLE(of, gcc_sdm660_match_table); 2460 2461 static int gcc_sdm660_probe(struct platform_device *pdev) 2462 { 2463 int ret; 2464 struct regmap *regmap; 2465 2466 regmap = qcom_cc_map(pdev, &gcc_sdm660_desc); 2467 if (IS_ERR(regmap)) 2468 return PTR_ERR(regmap); 2469 2470 /* 2471 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be 2472 * turned off by hardware during certain apps low power modes. 2473 */ 2474 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); 2475 if (ret) 2476 return ret; 2477 2478 return qcom_cc_really_probe(pdev, &gcc_sdm660_desc, regmap); 2479 } 2480 2481 static struct platform_driver gcc_sdm660_driver = { 2482 .probe = gcc_sdm660_probe, 2483 .driver = { 2484 .name = "gcc-sdm660", 2485 .of_match_table = gcc_sdm660_match_table, 2486 }, 2487 }; 2488 2489 static int __init gcc_sdm660_init(void) 2490 { 2491 return platform_driver_register(&gcc_sdm660_driver); 2492 } 2493 core_initcall_sync(gcc_sdm660_init); 2494 2495 static void __exit gcc_sdm660_exit(void) 2496 { 2497 platform_driver_unregister(&gcc_sdm660_driver); 2498 } 2499 module_exit(gcc_sdm660_exit); 2500 2501 MODULE_LICENSE("GPL v2"); 2502 MODULE_DESCRIPTION("QCOM GCC sdm660 Driver"); 2503