1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Ltd. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/err.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of_device.h> 12 #include <linux/of.h> 13 #include <linux/regmap.h> 14 15 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 16 17 #include "clk-alpha-pll.h" 18 #include "clk-branch.h" 19 #include "clk-rcg.h" 20 #include "clk-regmap.h" 21 #include "clk-regmap-divider.h" 22 #include "clk-regmap-mux.h" 23 #include "common.h" 24 #include "gdsc.h" 25 #include "reset.h" 26 27 /* Need to match the order of clocks in DT binding */ 28 enum { 29 DT_BI_TCXO, 30 DT_SLEEP_CLK, 31 DT_UFS_PHY_RX_SYMBOL_0_CLK, 32 DT_UFS_PHY_RX_SYMBOL_1_CLK, 33 DT_UFS_PHY_TX_SYMBOL_0_CLK, 34 DT_UFS_CARD_RX_SYMBOL_0_CLK, 35 DT_UFS_CARD_RX_SYMBOL_1_CLK, 36 DT_UFS_CARD_TX_SYMBOL_0_CLK, 37 DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 38 DT_GCC_USB4_PHY_PIPEGMUX_CLK_SRC, 39 DT_GCC_USB4_PHY_DP_GMUX_CLK_SRC, 40 DT_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC, 41 DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK, 42 DT_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 43 DT_QUSB4PHY_GCC_USB4_RX0_CLK, 44 DT_QUSB4PHY_GCC_USB4_RX1_CLK, 45 DT_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK, 46 DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 47 DT_GCC_USB4_1_PHY_DP_GMUX_CLK_SRC, 48 DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 49 DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 50 DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 51 DT_QUSB4PHY_1_GCC_USB4_RX0_CLK, 52 DT_QUSB4PHY_1_GCC_USB4_RX1_CLK, 53 DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK, 54 DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK, 55 DT_PCIE_2A_PIPE_CLK, 56 DT_PCIE_2B_PIPE_CLK, 57 DT_PCIE_3A_PIPE_CLK, 58 DT_PCIE_3B_PIPE_CLK, 59 DT_PCIE_4_PIPE_CLK, 60 DT_RXC0_REF_CLK, 61 DT_RXC1_REF_CLK, 62 }; 63 64 enum { 65 P_BI_TCXO, 66 P_GCC_GPLL0_OUT_EVEN, 67 P_GCC_GPLL0_OUT_MAIN, 68 P_GCC_GPLL2_OUT_MAIN, 69 P_GCC_GPLL4_OUT_MAIN, 70 P_GCC_GPLL7_OUT_MAIN, 71 P_GCC_GPLL8_OUT_MAIN, 72 P_GCC_GPLL9_OUT_MAIN, 73 P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 74 P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 75 P_GCC_USB4_1_PHY_DP_GMUX_CLK_SRC, 76 P_GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC, 77 P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, 78 P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 79 P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 80 P_GCC_USB4_PHY_DP_GMUX_CLK_SRC, 81 P_GCC_USB4_PHY_PCIE_PIPE_CLK_SRC, 82 P_GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC, 83 P_GCC_USB4_PHY_PIPEGMUX_CLK_SRC, 84 P_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC, 85 P_PCIE_2A_PIPE_CLK, 86 P_PCIE_2B_PIPE_CLK, 87 P_PCIE_3A_PIPE_CLK, 88 P_PCIE_3B_PIPE_CLK, 89 P_PCIE_4_PIPE_CLK, 90 P_QUSB4PHY_1_GCC_USB4_RX0_CLK, 91 P_QUSB4PHY_1_GCC_USB4_RX1_CLK, 92 P_QUSB4PHY_GCC_USB4_RX0_CLK, 93 P_QUSB4PHY_GCC_USB4_RX1_CLK, 94 P_RXC0_REF_CLK, 95 P_RXC1_REF_CLK, 96 P_SLEEP_CLK, 97 P_UFS_CARD_RX_SYMBOL_0_CLK, 98 P_UFS_CARD_RX_SYMBOL_1_CLK, 99 P_UFS_CARD_TX_SYMBOL_0_CLK, 100 P_UFS_PHY_RX_SYMBOL_0_CLK, 101 P_UFS_PHY_RX_SYMBOL_1_CLK, 102 P_UFS_PHY_TX_SYMBOL_0_CLK, 103 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 104 P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK, 105 P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK, 106 P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK, 107 P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 108 P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 109 P_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK, 110 P_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 111 }; 112 113 static const struct clk_parent_data gcc_parent_data_tcxo = { .index = DT_BI_TCXO }; 114 115 static struct clk_alpha_pll gcc_gpll0 = { 116 .offset = 0x0, 117 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 118 .clkr = { 119 .enable_reg = 0x52028, 120 .enable_mask = BIT(0), 121 .hw.init = &(const struct clk_init_data) { 122 .name = "gcc_gpll0", 123 .parent_data = &gcc_parent_data_tcxo, 124 .num_parents = 1, 125 .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops, 126 }, 127 }, 128 }; 129 130 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 131 { 0x1, 2 }, 132 { } 133 }; 134 135 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 136 .offset = 0x0, 137 .post_div_shift = 8, 138 .post_div_table = post_div_table_gcc_gpll0_out_even, 139 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 140 .width = 4, 141 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 142 .clkr.hw.init = &(const struct clk_init_data) { 143 .name = "gcc_gpll0_out_even", 144 .parent_hws = (const struct clk_hw*[]){ 145 &gcc_gpll0.clkr.hw, 146 }, 147 .num_parents = 1, 148 .ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops, 149 }, 150 }; 151 152 static struct clk_alpha_pll gcc_gpll2 = { 153 .offset = 0x2000, 154 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 155 .clkr = { 156 .enable_reg = 0x52028, 157 .enable_mask = BIT(2), 158 .hw.init = &(const struct clk_init_data) { 159 .name = "gcc_gpll2", 160 .parent_data = &gcc_parent_data_tcxo, 161 .num_parents = 1, 162 .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops, 163 }, 164 }, 165 }; 166 167 static struct clk_alpha_pll gcc_gpll4 = { 168 .offset = 0x76000, 169 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 170 .clkr = { 171 .enable_reg = 0x52028, 172 .enable_mask = BIT(4), 173 .hw.init = &(const struct clk_init_data) { 174 .name = "gcc_gpll4", 175 .parent_data = &gcc_parent_data_tcxo, 176 .num_parents = 1, 177 .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops, 178 }, 179 }, 180 }; 181 182 static struct clk_alpha_pll gcc_gpll7 = { 183 .offset = 0x1a000, 184 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 185 .clkr = { 186 .enable_reg = 0x52028, 187 .enable_mask = BIT(7), 188 .hw.init = &(const struct clk_init_data) { 189 .name = "gcc_gpll7", 190 .parent_data = &gcc_parent_data_tcxo, 191 .num_parents = 1, 192 .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops, 193 }, 194 }, 195 }; 196 197 static struct clk_alpha_pll gcc_gpll8 = { 198 .offset = 0x1b000, 199 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 200 .clkr = { 201 .enable_reg = 0x52028, 202 .enable_mask = BIT(8), 203 .hw.init = &(const struct clk_init_data) { 204 .name = "gcc_gpll8", 205 .parent_data = &gcc_parent_data_tcxo, 206 .num_parents = 1, 207 .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops, 208 }, 209 }, 210 }; 211 212 static struct clk_alpha_pll gcc_gpll9 = { 213 .offset = 0x1c000, 214 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 215 .clkr = { 216 .enable_reg = 0x52028, 217 .enable_mask = BIT(9), 218 .hw.init = &(const struct clk_init_data) { 219 .name = "gcc_gpll9", 220 .parent_data = &gcc_parent_data_tcxo, 221 .num_parents = 1, 222 .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops, 223 }, 224 }, 225 }; 226 227 static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src; 228 static struct clk_rcg2 gcc_usb4_phy_pcie_pipe_clk_src; 229 230 static const struct parent_map gcc_parent_map_0[] = { 231 { P_BI_TCXO, 0 }, 232 { P_GCC_GPLL0_OUT_MAIN, 1 }, 233 { P_GCC_GPLL0_OUT_EVEN, 6 }, 234 }; 235 236 static const struct clk_parent_data gcc_parent_data_0[] = { 237 { .index = DT_BI_TCXO }, 238 { .hw = &gcc_gpll0.clkr.hw }, 239 { .hw = &gcc_gpll0_out_even.clkr.hw }, 240 }; 241 242 static const struct parent_map gcc_parent_map_1[] = { 243 { P_BI_TCXO, 0 }, 244 { P_SLEEP_CLK, 5 }, 245 }; 246 247 static const struct clk_parent_data gcc_parent_data_1[] = { 248 { .index = DT_BI_TCXO }, 249 { .index = DT_SLEEP_CLK }, 250 }; 251 252 static const struct parent_map gcc_parent_map_2[] = { 253 { P_BI_TCXO, 0 }, 254 { P_GCC_GPLL0_OUT_MAIN, 1 }, 255 { P_SLEEP_CLK, 5 }, 256 { P_GCC_GPLL0_OUT_EVEN, 6 }, 257 }; 258 259 static const struct clk_parent_data gcc_parent_data_2[] = { 260 { .index = DT_BI_TCXO }, 261 { .hw = &gcc_gpll0.clkr.hw }, 262 { .index = DT_SLEEP_CLK }, 263 { .hw = &gcc_gpll0_out_even.clkr.hw }, 264 }; 265 266 static const struct parent_map gcc_parent_map_3[] = { 267 { P_BI_TCXO, 0 }, 268 }; 269 270 static const struct clk_parent_data gcc_parent_data_3[] = { 271 { .index = DT_BI_TCXO }, 272 }; 273 274 static const struct parent_map gcc_parent_map_4[] = { 275 { P_BI_TCXO, 0 }, 276 { P_GCC_GPLL7_OUT_MAIN, 2 }, 277 { P_GCC_GPLL4_OUT_MAIN, 5 }, 278 { P_GCC_GPLL0_OUT_EVEN, 6 }, 279 }; 280 281 static const struct clk_parent_data gcc_parent_data_4[] = { 282 { .index = DT_BI_TCXO }, 283 { .hw = &gcc_gpll7.clkr.hw }, 284 { .hw = &gcc_gpll4.clkr.hw }, 285 { .hw = &gcc_gpll0_out_even.clkr.hw }, 286 }; 287 288 static const struct parent_map gcc_parent_map_5[] = { 289 { P_BI_TCXO, 0 }, 290 { P_GCC_GPLL0_OUT_MAIN, 1 }, 291 { P_GCC_GPLL8_OUT_MAIN, 2 }, 292 { P_GCC_GPLL0_OUT_EVEN, 6 }, 293 }; 294 295 static const struct clk_parent_data gcc_parent_data_5[] = { 296 { .index = DT_BI_TCXO }, 297 { .hw = &gcc_gpll0.clkr.hw }, 298 { .hw = &gcc_gpll8.clkr.hw }, 299 { .hw = &gcc_gpll0_out_even.clkr.hw }, 300 }; 301 302 static const struct parent_map gcc_parent_map_6[] = { 303 { P_BI_TCXO, 0 }, 304 { P_GCC_GPLL0_OUT_MAIN, 1 }, 305 { P_GCC_GPLL7_OUT_MAIN, 2 }, 306 }; 307 308 static const struct clk_parent_data gcc_parent_data_6[] = { 309 { .index = DT_BI_TCXO }, 310 { .hw = &gcc_gpll0.clkr.hw }, 311 { .hw = &gcc_gpll7.clkr.hw }, 312 }; 313 314 static const struct parent_map gcc_parent_map_7[] = { 315 { P_BI_TCXO, 0 }, 316 { P_GCC_GPLL0_OUT_MAIN, 1 }, 317 { P_GCC_GPLL2_OUT_MAIN, 2 }, 318 }; 319 320 static const struct clk_parent_data gcc_parent_data_7[] = { 321 { .index = DT_BI_TCXO }, 322 { .hw = &gcc_gpll0.clkr.hw }, 323 { .hw = &gcc_gpll2.clkr.hw }, 324 }; 325 326 static const struct parent_map gcc_parent_map_8[] = { 327 { P_BI_TCXO, 0 }, 328 { P_GCC_GPLL7_OUT_MAIN, 2 }, 329 { P_RXC0_REF_CLK, 3 }, 330 { P_GCC_GPLL0_OUT_EVEN, 6 }, 331 }; 332 333 static const struct clk_parent_data gcc_parent_data_8[] = { 334 { .index = DT_BI_TCXO }, 335 { .hw = &gcc_gpll7.clkr.hw }, 336 { .index = DT_RXC0_REF_CLK }, 337 { .hw = &gcc_gpll0_out_even.clkr.hw }, 338 }; 339 340 static const struct parent_map gcc_parent_map_9[] = { 341 { P_BI_TCXO, 0 }, 342 { P_GCC_GPLL7_OUT_MAIN, 2 }, 343 { P_RXC1_REF_CLK, 3 }, 344 { P_GCC_GPLL0_OUT_EVEN, 6 }, 345 }; 346 347 static const struct clk_parent_data gcc_parent_data_9[] = { 348 { .index = DT_BI_TCXO }, 349 { .hw = &gcc_gpll7.clkr.hw }, 350 { .index = DT_RXC1_REF_CLK }, 351 { .hw = &gcc_gpll0_out_even.clkr.hw }, 352 }; 353 354 static const struct parent_map gcc_parent_map_10[] = { 355 { P_PCIE_2A_PIPE_CLK, 0 }, 356 { P_BI_TCXO, 2 }, 357 }; 358 359 static const struct clk_parent_data gcc_parent_data_10[] = { 360 { .index = DT_PCIE_2A_PIPE_CLK }, 361 { .index = DT_BI_TCXO }, 362 }; 363 364 static const struct parent_map gcc_parent_map_11[] = { 365 { P_PCIE_2B_PIPE_CLK, 0 }, 366 { P_BI_TCXO, 2 }, 367 }; 368 369 static const struct clk_parent_data gcc_parent_data_11[] = { 370 { .index = DT_PCIE_2B_PIPE_CLK }, 371 { .index = DT_BI_TCXO }, 372 }; 373 374 static const struct parent_map gcc_parent_map_12[] = { 375 { P_PCIE_3A_PIPE_CLK, 0 }, 376 { P_BI_TCXO, 2 }, 377 }; 378 379 static const struct clk_parent_data gcc_parent_data_12[] = { 380 { .index = DT_PCIE_3A_PIPE_CLK }, 381 { .index = DT_BI_TCXO }, 382 }; 383 384 static const struct parent_map gcc_parent_map_13[] = { 385 { P_PCIE_3B_PIPE_CLK, 0 }, 386 { P_BI_TCXO, 2 }, 387 }; 388 389 static const struct clk_parent_data gcc_parent_data_13[] = { 390 { .index = DT_PCIE_3B_PIPE_CLK }, 391 { .index = DT_BI_TCXO }, 392 }; 393 394 static const struct parent_map gcc_parent_map_14[] = { 395 { P_PCIE_4_PIPE_CLK, 0 }, 396 { P_BI_TCXO, 2 }, 397 }; 398 399 static const struct clk_parent_data gcc_parent_data_14[] = { 400 { .index = DT_PCIE_4_PIPE_CLK }, 401 { .index = DT_BI_TCXO }, 402 }; 403 404 static const struct parent_map gcc_parent_map_15[] = { 405 { P_BI_TCXO, 0 }, 406 { P_GCC_GPLL0_OUT_MAIN, 1 }, 407 { P_GCC_GPLL9_OUT_MAIN, 2 }, 408 { P_GCC_GPLL4_OUT_MAIN, 5 }, 409 { P_GCC_GPLL0_OUT_EVEN, 6 }, 410 }; 411 412 static const struct clk_parent_data gcc_parent_data_15[] = { 413 { .index = DT_BI_TCXO }, 414 { .hw = &gcc_gpll0.clkr.hw }, 415 { .hw = &gcc_gpll9.clkr.hw }, 416 { .hw = &gcc_gpll4.clkr.hw }, 417 { .hw = &gcc_gpll0_out_even.clkr.hw }, 418 }; 419 420 static const struct parent_map gcc_parent_map_16[] = { 421 { P_UFS_CARD_RX_SYMBOL_0_CLK, 0 }, 422 { P_BI_TCXO, 2 }, 423 }; 424 425 static const struct clk_parent_data gcc_parent_data_16[] = { 426 { .index = DT_UFS_CARD_RX_SYMBOL_0_CLK }, 427 { .index = DT_BI_TCXO }, 428 }; 429 430 static const struct parent_map gcc_parent_map_17[] = { 431 { P_UFS_CARD_RX_SYMBOL_1_CLK, 0 }, 432 { P_BI_TCXO, 2 }, 433 }; 434 435 static const struct clk_parent_data gcc_parent_data_17[] = { 436 { .index = DT_UFS_CARD_RX_SYMBOL_1_CLK }, 437 { .index = DT_BI_TCXO }, 438 }; 439 440 static const struct parent_map gcc_parent_map_18[] = { 441 { P_UFS_CARD_TX_SYMBOL_0_CLK, 0 }, 442 { P_BI_TCXO, 2 }, 443 }; 444 445 static const struct clk_parent_data gcc_parent_data_18[] = { 446 { .index = DT_UFS_CARD_TX_SYMBOL_0_CLK }, 447 { .index = DT_BI_TCXO }, 448 }; 449 450 static const struct parent_map gcc_parent_map_19[] = { 451 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, 452 { P_BI_TCXO, 2 }, 453 }; 454 455 static const struct clk_parent_data gcc_parent_data_19[] = { 456 { .index = DT_UFS_PHY_RX_SYMBOL_0_CLK }, 457 { .index = DT_BI_TCXO }, 458 }; 459 460 static const struct parent_map gcc_parent_map_20[] = { 461 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, 462 { P_BI_TCXO, 2 }, 463 }; 464 465 static const struct clk_parent_data gcc_parent_data_20[] = { 466 { .index = DT_UFS_PHY_RX_SYMBOL_1_CLK }, 467 { .index = DT_BI_TCXO }, 468 }; 469 470 static const struct parent_map gcc_parent_map_21[] = { 471 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, 472 { P_BI_TCXO, 2 }, 473 }; 474 475 static const struct clk_parent_data gcc_parent_data_21[] = { 476 { .index = DT_UFS_PHY_TX_SYMBOL_0_CLK }, 477 { .index = DT_BI_TCXO }, 478 }; 479 480 static const struct parent_map gcc_parent_map_22[] = { 481 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 482 { P_BI_TCXO, 2 }, 483 }; 484 485 static const struct clk_parent_data gcc_parent_data_22[] = { 486 { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK }, 487 { .index = DT_BI_TCXO }, 488 }; 489 490 static const struct parent_map gcc_parent_map_23[] = { 491 { P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK, 0 }, 492 { P_BI_TCXO, 2 }, 493 }; 494 495 static const struct clk_parent_data gcc_parent_data_23[] = { 496 { .index = DT_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK }, 497 { .index = DT_BI_TCXO }, 498 }; 499 500 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 501 .reg = 0xf060, 502 .shift = 0, 503 .width = 2, 504 .parent_map = gcc_parent_map_22, 505 .clkr = { 506 .hw.init = &(const struct clk_init_data) { 507 .name = "gcc_usb3_prim_phy_pipe_clk_src", 508 .parent_data = gcc_parent_data_22, 509 .num_parents = ARRAY_SIZE(gcc_parent_data_22), 510 .ops = &clk_regmap_mux_closest_ops, 511 }, 512 }, 513 }; 514 515 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = { 516 .reg = 0x10060, 517 .shift = 0, 518 .width = 2, 519 .parent_map = gcc_parent_map_23, 520 .clkr = { 521 .hw.init = &(const struct clk_init_data) { 522 .name = "gcc_usb3_sec_phy_pipe_clk_src", 523 .parent_data = gcc_parent_data_23, 524 .num_parents = ARRAY_SIZE(gcc_parent_data_23), 525 .ops = &clk_regmap_mux_closest_ops, 526 }, 527 }, 528 }; 529 530 static const struct parent_map gcc_parent_map_24[] = { 531 { P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK, 0 }, 532 { P_BI_TCXO, 2 }, 533 }; 534 535 static const struct clk_parent_data gcc_parent_data_24[] = { 536 { .index = DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK }, 537 { .index = DT_BI_TCXO }, 538 }; 539 540 static const struct parent_map gcc_parent_map_25[] = { 541 { P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK, 0 }, 542 { P_BI_TCXO, 2 }, 543 }; 544 545 static const struct clk_parent_data gcc_parent_data_25[] = { 546 { .index = DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK }, 547 { .index = DT_BI_TCXO }, 548 }; 549 550 static const struct parent_map gcc_parent_map_26[] = { 551 { P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 }, 552 { P_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 }, 553 { P_GCC_USB4_PHY_PIPEGMUX_CLK_SRC, 3 }, 554 }; 555 556 static const struct clk_parent_data gcc_parent_data_26[] = { 557 { .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw }, 558 { .index = DT_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 559 { .index = DT_GCC_USB4_PHY_PIPEGMUX_CLK_SRC }, 560 }; 561 562 static const struct parent_map gcc_parent_map_27[] = { 563 { P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 0 }, 564 { P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 }, 565 { P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 3 }, 566 }; 567 568 static const struct clk_parent_data gcc_parent_data_27[] = { 569 { .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw }, 570 { .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 571 { .index = DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC }, 572 }; 573 574 static const struct parent_map gcc_parent_map_28[] = { 575 { P_GCC_USB4_1_PHY_DP_GMUX_CLK_SRC, 0 }, 576 { P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 }, 577 }; 578 579 static const struct clk_parent_data gcc_parent_data_28[] = { 580 { .index = DT_GCC_USB4_1_PHY_DP_GMUX_CLK_SRC }, 581 { .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 582 }; 583 584 static const struct parent_map gcc_parent_map_29[] = { 585 { P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 }, 586 { P_BI_TCXO, 2 }, 587 }; 588 589 static const struct clk_parent_data gcc_parent_data_29[] = { 590 { .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK }, 591 { .index = DT_BI_TCXO }, 592 }; 593 594 static const struct parent_map gcc_parent_map_30[] = { 595 { P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 0 }, 596 { P_GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC, 1 }, 597 }; 598 599 static const struct clk_parent_data gcc_parent_data_30[] = { 600 { .index = DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC }, 601 { .hw = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr.hw }, 602 }; 603 604 static struct clk_regmap_mux gcc_usb4_1_phy_pcie_pipegmux_clk_src = { 605 .reg = 0xb80dc, 606 .shift = 0, 607 .width = 1, 608 .parent_map = gcc_parent_map_30, 609 .clkr = { 610 .hw.init = &(const struct clk_init_data) { 611 .name = "gcc_usb4_1_phy_pcie_pipegmux_clk_src", 612 .parent_data = gcc_parent_data_30, 613 .num_parents = ARRAY_SIZE(gcc_parent_data_30), 614 .ops = &clk_regmap_mux_closest_ops, 615 }, 616 }, 617 }; 618 619 static const struct parent_map gcc_parent_map_31[] = { 620 { P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 }, 621 { P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 }, 622 }; 623 624 static const struct clk_parent_data gcc_parent_data_31[] = { 625 { .hw = &gcc_usb4_1_phy_pcie_pipegmux_clk_src.clkr.hw }, 626 { .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK }, 627 }; 628 629 static const struct parent_map gcc_parent_map_32[] = { 630 { P_QUSB4PHY_1_GCC_USB4_RX0_CLK, 0 }, 631 { P_BI_TCXO, 2 }, 632 }; 633 634 static const struct clk_parent_data gcc_parent_data_32[] = { 635 { .index = DT_QUSB4PHY_1_GCC_USB4_RX0_CLK }, 636 { .index = DT_BI_TCXO }, 637 }; 638 639 static const struct parent_map gcc_parent_map_33[] = { 640 { P_QUSB4PHY_1_GCC_USB4_RX1_CLK, 0 }, 641 { P_BI_TCXO, 2 }, 642 }; 643 644 static const struct clk_parent_data gcc_parent_data_33[] = { 645 { .index = DT_QUSB4PHY_1_GCC_USB4_RX1_CLK }, 646 { .index = DT_BI_TCXO }, 647 }; 648 649 static const struct parent_map gcc_parent_map_34[] = { 650 { P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 0 }, 651 { P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 }, 652 }; 653 654 static const struct clk_parent_data gcc_parent_data_34[] = { 655 { .index = DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC }, 656 { .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK }, 657 }; 658 659 static const struct parent_map gcc_parent_map_35[] = { 660 { P_GCC_USB4_PHY_DP_GMUX_CLK_SRC, 0 }, 661 { P_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 }, 662 }; 663 664 static const struct clk_parent_data gcc_parent_data_35[] = { 665 { .index = DT_GCC_USB4_PHY_DP_GMUX_CLK_SRC }, 666 { .index = DT_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 667 }; 668 669 static const struct parent_map gcc_parent_map_36[] = { 670 { P_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 }, 671 { P_BI_TCXO, 2 }, 672 }; 673 674 static const struct clk_parent_data gcc_parent_data_36[] = { 675 { .index = DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK }, 676 { .index = DT_BI_TCXO }, 677 }; 678 679 static const struct parent_map gcc_parent_map_37[] = { 680 { P_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC, 0 }, 681 { P_GCC_USB4_PHY_PCIE_PIPE_CLK_SRC, 1 }, 682 }; 683 684 static const struct clk_parent_data gcc_parent_data_37[] = { 685 { .index = DT_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC }, 686 { .hw = &gcc_usb4_phy_pcie_pipe_clk_src.clkr.hw }, 687 }; 688 689 static struct clk_regmap_mux gcc_usb4_phy_pcie_pipegmux_clk_src = { 690 .reg = 0x2a0dc, 691 .shift = 0, 692 .width = 1, 693 .parent_map = gcc_parent_map_37, 694 .clkr = { 695 .hw.init = &(const struct clk_init_data) { 696 .name = "gcc_usb4_phy_pcie_pipegmux_clk_src", 697 .parent_data = gcc_parent_data_37, 698 .num_parents = ARRAY_SIZE(gcc_parent_data_37), 699 .ops = &clk_regmap_mux_closest_ops, 700 }, 701 }, 702 }; 703 704 static const struct parent_map gcc_parent_map_38[] = { 705 { P_GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 }, 706 { P_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 }, 707 }; 708 709 static const struct clk_parent_data gcc_parent_data_38[] = { 710 { .hw = &gcc_usb4_phy_pcie_pipegmux_clk_src.clkr.hw }, 711 { .index = DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK }, 712 }; 713 714 static const struct parent_map gcc_parent_map_39[] = { 715 { P_QUSB4PHY_GCC_USB4_RX0_CLK, 0 }, 716 { P_BI_TCXO, 2 }, 717 }; 718 719 static const struct clk_parent_data gcc_parent_data_39[] = { 720 { .index = DT_QUSB4PHY_GCC_USB4_RX0_CLK }, 721 { .index = DT_BI_TCXO }, 722 }; 723 724 static const struct parent_map gcc_parent_map_40[] = { 725 { P_QUSB4PHY_GCC_USB4_RX1_CLK, 0 }, 726 { P_BI_TCXO, 2 }, 727 }; 728 729 static const struct clk_parent_data gcc_parent_data_40[] = { 730 { .index = DT_QUSB4PHY_GCC_USB4_RX1_CLK }, 731 { .index = DT_BI_TCXO }, 732 }; 733 734 static const struct parent_map gcc_parent_map_41[] = { 735 { P_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC, 0 }, 736 { P_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 }, 737 }; 738 739 static const struct clk_parent_data gcc_parent_data_41[] = { 740 { .index = DT_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC }, 741 { .index = DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK }, 742 }; 743 744 static struct clk_regmap_mux gcc_pcie_2a_pipe_clk_src = { 745 .reg = 0x9d05c, 746 .shift = 0, 747 .width = 2, 748 .parent_map = gcc_parent_map_10, 749 .clkr = { 750 .hw.init = &(const struct clk_init_data) { 751 .name = "gcc_pcie_2a_pipe_clk_src", 752 .parent_data = gcc_parent_data_10, 753 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 754 .ops = &clk_regmap_mux_closest_ops, 755 }, 756 }, 757 }; 758 759 static struct clk_regmap_mux gcc_pcie_2b_pipe_clk_src = { 760 .reg = 0x9e05c, 761 .shift = 0, 762 .width = 2, 763 .parent_map = gcc_parent_map_11, 764 .clkr = { 765 .hw.init = &(const struct clk_init_data) { 766 .name = "gcc_pcie_2b_pipe_clk_src", 767 .parent_data = gcc_parent_data_11, 768 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 769 .ops = &clk_regmap_mux_closest_ops, 770 }, 771 }, 772 }; 773 774 static struct clk_regmap_mux gcc_pcie_3a_pipe_clk_src = { 775 .reg = 0xa005c, 776 .shift = 0, 777 .width = 2, 778 .parent_map = gcc_parent_map_12, 779 .clkr = { 780 .hw.init = &(const struct clk_init_data) { 781 .name = "gcc_pcie_3a_pipe_clk_src", 782 .parent_data = gcc_parent_data_12, 783 .num_parents = ARRAY_SIZE(gcc_parent_data_12), 784 .ops = &clk_regmap_mux_closest_ops, 785 }, 786 }, 787 }; 788 789 static struct clk_regmap_mux gcc_pcie_3b_pipe_clk_src = { 790 .reg = 0xa205c, 791 .shift = 0, 792 .width = 2, 793 .parent_map = gcc_parent_map_13, 794 .clkr = { 795 .hw.init = &(const struct clk_init_data) { 796 .name = "gcc_pcie_3b_pipe_clk_src", 797 .parent_data = gcc_parent_data_13, 798 .num_parents = ARRAY_SIZE(gcc_parent_data_13), 799 .ops = &clk_regmap_mux_closest_ops, 800 }, 801 }, 802 }; 803 804 static struct clk_regmap_mux gcc_pcie_4_pipe_clk_src = { 805 .reg = 0x6b05c, 806 .shift = 0, 807 .width = 2, 808 .parent_map = gcc_parent_map_14, 809 .clkr = { 810 .hw.init = &(const struct clk_init_data) { 811 .name = "gcc_pcie_4_pipe_clk_src", 812 .parent_data = gcc_parent_data_14, 813 .num_parents = ARRAY_SIZE(gcc_parent_data_14), 814 .ops = &clk_regmap_mux_closest_ops, 815 }, 816 }, 817 }; 818 819 static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src = { 820 .reg = 0x75058, 821 .shift = 0, 822 .width = 2, 823 .parent_map = gcc_parent_map_16, 824 .clkr = { 825 .hw.init = &(const struct clk_init_data) { 826 .name = "gcc_ufs_card_rx_symbol_0_clk_src", 827 .parent_data = gcc_parent_data_16, 828 .num_parents = ARRAY_SIZE(gcc_parent_data_16), 829 .ops = &clk_regmap_mux_closest_ops, 830 }, 831 }, 832 }; 833 834 static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src = { 835 .reg = 0x750c8, 836 .shift = 0, 837 .width = 2, 838 .parent_map = gcc_parent_map_17, 839 .clkr = { 840 .hw.init = &(const struct clk_init_data) { 841 .name = "gcc_ufs_card_rx_symbol_1_clk_src", 842 .parent_data = gcc_parent_data_17, 843 .num_parents = ARRAY_SIZE(gcc_parent_data_17), 844 .ops = &clk_regmap_mux_closest_ops, 845 }, 846 }, 847 }; 848 849 static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src = { 850 .reg = 0x75048, 851 .shift = 0, 852 .width = 2, 853 .parent_map = gcc_parent_map_18, 854 .clkr = { 855 .hw.init = &(const struct clk_init_data) { 856 .name = "gcc_ufs_card_tx_symbol_0_clk_src", 857 .parent_data = gcc_parent_data_18, 858 .num_parents = ARRAY_SIZE(gcc_parent_data_18), 859 .ops = &clk_regmap_mux_closest_ops, 860 }, 861 }, 862 }; 863 864 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 865 .reg = 0x77058, 866 .shift = 0, 867 .width = 2, 868 .parent_map = gcc_parent_map_19, 869 .clkr = { 870 .hw.init = &(const struct clk_init_data) { 871 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 872 .parent_data = gcc_parent_data_19, 873 .num_parents = ARRAY_SIZE(gcc_parent_data_19), 874 .ops = &clk_regmap_mux_closest_ops, 875 }, 876 }, 877 }; 878 879 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 880 .reg = 0x770c8, 881 .shift = 0, 882 .width = 2, 883 .parent_map = gcc_parent_map_20, 884 .clkr = { 885 .hw.init = &(const struct clk_init_data) { 886 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 887 .parent_data = gcc_parent_data_20, 888 .num_parents = ARRAY_SIZE(gcc_parent_data_20), 889 .ops = &clk_regmap_mux_closest_ops, 890 }, 891 }, 892 }; 893 894 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 895 .reg = 0x77048, 896 .shift = 0, 897 .width = 2, 898 .parent_map = gcc_parent_map_21, 899 .clkr = { 900 .hw.init = &(const struct clk_init_data) { 901 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 902 .parent_data = gcc_parent_data_21, 903 .num_parents = ARRAY_SIZE(gcc_parent_data_21), 904 .ops = &clk_regmap_mux_closest_ops, 905 }, 906 }, 907 }; 908 909 static struct clk_regmap_mux gcc_usb34_prim_phy_pipe_clk_src = { 910 .reg = 0xf064, 911 .shift = 0, 912 .width = 2, 913 .parent_map = gcc_parent_map_26, 914 .clkr = { 915 .hw.init = &(const struct clk_init_data) { 916 .name = "gcc_usb34_prim_phy_pipe_clk_src", 917 .parent_data = gcc_parent_data_26, 918 .num_parents = ARRAY_SIZE(gcc_parent_data_26), 919 .ops = &clk_regmap_mux_closest_ops, 920 }, 921 }, 922 }; 923 924 static struct clk_regmap_mux gcc_usb34_sec_phy_pipe_clk_src = { 925 .reg = 0x10064, 926 .shift = 0, 927 .width = 2, 928 .parent_map = gcc_parent_map_27, 929 .clkr = { 930 .hw.init = &(const struct clk_init_data) { 931 .name = "gcc_usb34_sec_phy_pipe_clk_src", 932 .parent_data = gcc_parent_data_27, 933 .num_parents = ARRAY_SIZE(gcc_parent_data_27), 934 .ops = &clk_regmap_mux_closest_ops, 935 }, 936 }, 937 }; 938 939 static struct clk_regmap_mux gcc_usb3_mp_phy_pipe_0_clk_src = { 940 .reg = 0xab060, 941 .shift = 0, 942 .width = 2, 943 .parent_map = gcc_parent_map_24, 944 .clkr = { 945 .hw.init = &(const struct clk_init_data) { 946 .name = "gcc_usb3_mp_phy_pipe_0_clk_src", 947 .parent_data = gcc_parent_data_24, 948 .num_parents = ARRAY_SIZE(gcc_parent_data_24), 949 .ops = &clk_regmap_mux_closest_ops, 950 }, 951 }, 952 }; 953 954 static struct clk_regmap_mux gcc_usb3_mp_phy_pipe_1_clk_src = { 955 .reg = 0xab068, 956 .shift = 0, 957 .width = 2, 958 .parent_map = gcc_parent_map_25, 959 .clkr = { 960 .hw.init = &(const struct clk_init_data) { 961 .name = "gcc_usb3_mp_phy_pipe_1_clk_src", 962 .parent_data = gcc_parent_data_25, 963 .num_parents = ARRAY_SIZE(gcc_parent_data_25), 964 .ops = &clk_regmap_mux_closest_ops, 965 }, 966 }, 967 }; 968 969 static struct clk_regmap_mux gcc_usb4_1_phy_dp_clk_src = { 970 .reg = 0xb8050, 971 .shift = 0, 972 .width = 2, 973 .parent_map = gcc_parent_map_28, 974 .clkr = { 975 .hw.init = &(const struct clk_init_data) { 976 .name = "gcc_usb4_1_phy_dp_clk_src", 977 .parent_data = gcc_parent_data_28, 978 .num_parents = ARRAY_SIZE(gcc_parent_data_28), 979 .ops = &clk_regmap_mux_closest_ops, 980 }, 981 }, 982 }; 983 984 static struct clk_regmap_mux gcc_usb4_1_phy_p2rr2p_pipe_clk_src = { 985 .reg = 0xb80b0, 986 .shift = 0, 987 .width = 2, 988 .parent_map = gcc_parent_map_29, 989 .clkr = { 990 .hw.init = &(const struct clk_init_data) { 991 .name = "gcc_usb4_1_phy_p2rr2p_pipe_clk_src", 992 .parent_data = gcc_parent_data_29, 993 .num_parents = ARRAY_SIZE(gcc_parent_data_29), 994 .ops = &clk_regmap_mux_closest_ops, 995 }, 996 }, 997 }; 998 999 static struct clk_regmap_mux gcc_usb4_1_phy_pcie_pipe_mux_clk_src = { 1000 .reg = 0xb80e0, 1001 .shift = 0, 1002 .width = 2, 1003 .parent_map = gcc_parent_map_31, 1004 .clkr = { 1005 .hw.init = &(const struct clk_init_data) { 1006 .name = "gcc_usb4_1_phy_pcie_pipe_mux_clk_src", 1007 .parent_data = gcc_parent_data_31, 1008 .num_parents = ARRAY_SIZE(gcc_parent_data_31), 1009 .ops = &clk_regmap_mux_closest_ops, 1010 }, 1011 }, 1012 }; 1013 1014 static struct clk_regmap_mux gcc_usb4_1_phy_rx0_clk_src = { 1015 .reg = 0xb8090, 1016 .shift = 0, 1017 .width = 2, 1018 .parent_map = gcc_parent_map_32, 1019 .clkr = { 1020 .hw.init = &(const struct clk_init_data) { 1021 .name = "gcc_usb4_1_phy_rx0_clk_src", 1022 .parent_data = gcc_parent_data_32, 1023 .num_parents = ARRAY_SIZE(gcc_parent_data_32), 1024 .ops = &clk_regmap_mux_closest_ops, 1025 }, 1026 }, 1027 }; 1028 1029 static struct clk_regmap_mux gcc_usb4_1_phy_rx1_clk_src = { 1030 .reg = 0xb809c, 1031 .shift = 0, 1032 .width = 2, 1033 .parent_map = gcc_parent_map_33, 1034 .clkr = { 1035 .hw.init = &(const struct clk_init_data) { 1036 .name = "gcc_usb4_1_phy_rx1_clk_src", 1037 .parent_data = gcc_parent_data_33, 1038 .num_parents = ARRAY_SIZE(gcc_parent_data_33), 1039 .ops = &clk_regmap_mux_closest_ops, 1040 }, 1041 }, 1042 }; 1043 1044 static struct clk_regmap_mux gcc_usb4_1_phy_sys_clk_src = { 1045 .reg = 0xb80c0, 1046 .shift = 0, 1047 .width = 2, 1048 .parent_map = gcc_parent_map_34, 1049 .clkr = { 1050 .hw.init = &(const struct clk_init_data) { 1051 .name = "gcc_usb4_1_phy_sys_clk_src", 1052 .parent_data = gcc_parent_data_34, 1053 .num_parents = ARRAY_SIZE(gcc_parent_data_34), 1054 .ops = &clk_regmap_mux_closest_ops, 1055 }, 1056 }, 1057 }; 1058 1059 static struct clk_regmap_mux gcc_usb4_phy_dp_clk_src = { 1060 .reg = 0x2a050, 1061 .shift = 0, 1062 .width = 2, 1063 .parent_map = gcc_parent_map_35, 1064 .clkr = { 1065 .hw.init = &(const struct clk_init_data) { 1066 .name = "gcc_usb4_phy_dp_clk_src", 1067 .parent_data = gcc_parent_data_35, 1068 .num_parents = ARRAY_SIZE(gcc_parent_data_35), 1069 .ops = &clk_regmap_mux_closest_ops, 1070 }, 1071 }, 1072 }; 1073 1074 static struct clk_regmap_mux gcc_usb4_phy_p2rr2p_pipe_clk_src = { 1075 .reg = 0x2a0b0, 1076 .shift = 0, 1077 .width = 2, 1078 .parent_map = gcc_parent_map_36, 1079 .clkr = { 1080 .hw.init = &(const struct clk_init_data) { 1081 .name = "gcc_usb4_phy_p2rr2p_pipe_clk_src", 1082 .parent_data = gcc_parent_data_36, 1083 .num_parents = ARRAY_SIZE(gcc_parent_data_36), 1084 .ops = &clk_regmap_mux_closest_ops, 1085 }, 1086 }, 1087 }; 1088 1089 static struct clk_regmap_mux gcc_usb4_phy_pcie_pipe_mux_clk_src = { 1090 .reg = 0x2a0e0, 1091 .shift = 0, 1092 .width = 2, 1093 .parent_map = gcc_parent_map_38, 1094 .clkr = { 1095 .hw.init = &(const struct clk_init_data) { 1096 .name = "gcc_usb4_phy_pcie_pipe_mux_clk_src", 1097 .parent_data = gcc_parent_data_38, 1098 .num_parents = ARRAY_SIZE(gcc_parent_data_38), 1099 .ops = &clk_regmap_mux_closest_ops, 1100 }, 1101 }, 1102 }; 1103 1104 static struct clk_regmap_mux gcc_usb4_phy_rx0_clk_src = { 1105 .reg = 0x2a090, 1106 .shift = 0, 1107 .width = 2, 1108 .parent_map = gcc_parent_map_39, 1109 .clkr = { 1110 .hw.init = &(const struct clk_init_data) { 1111 .name = "gcc_usb4_phy_rx0_clk_src", 1112 .parent_data = gcc_parent_data_39, 1113 .num_parents = ARRAY_SIZE(gcc_parent_data_39), 1114 .ops = &clk_regmap_mux_closest_ops, 1115 }, 1116 }, 1117 }; 1118 1119 static struct clk_regmap_mux gcc_usb4_phy_rx1_clk_src = { 1120 .reg = 0x2a09c, 1121 .shift = 0, 1122 .width = 2, 1123 .parent_map = gcc_parent_map_40, 1124 .clkr = { 1125 .hw.init = &(const struct clk_init_data) { 1126 .name = "gcc_usb4_phy_rx1_clk_src", 1127 .parent_data = gcc_parent_data_40, 1128 .num_parents = ARRAY_SIZE(gcc_parent_data_40), 1129 .ops = &clk_regmap_mux_closest_ops, 1130 }, 1131 }, 1132 }; 1133 1134 static struct clk_regmap_mux gcc_usb4_phy_sys_clk_src = { 1135 .reg = 0x2a0c0, 1136 .shift = 0, 1137 .width = 2, 1138 .parent_map = gcc_parent_map_41, 1139 .clkr = { 1140 .hw.init = &(const struct clk_init_data) { 1141 .name = "gcc_usb4_phy_sys_clk_src", 1142 .parent_data = gcc_parent_data_41, 1143 .num_parents = ARRAY_SIZE(gcc_parent_data_41), 1144 .ops = &clk_regmap_mux_closest_ops, 1145 }, 1146 }, 1147 }; 1148 1149 static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] = { 1150 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1151 F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0), 1152 F(230400000, P_GCC_GPLL4_OUT_MAIN, 3.5, 0, 0), 1153 { } 1154 }; 1155 1156 static struct clk_rcg2 gcc_emac0_ptp_clk_src = { 1157 .cmd_rcgr = 0xaa020, 1158 .mnd_width = 0, 1159 .hid_width = 5, 1160 .parent_map = gcc_parent_map_4, 1161 .freq_tbl = ftbl_gcc_emac0_ptp_clk_src, 1162 .clkr.hw.init = &(const struct clk_init_data) { 1163 .name = "gcc_emac0_ptp_clk_src", 1164 .parent_data = gcc_parent_data_4, 1165 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1166 .ops = &clk_rcg2_shared_ops, 1167 }, 1168 }; 1169 1170 static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] = { 1171 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 1172 F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0), 1173 F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0), 1174 { } 1175 }; 1176 1177 static struct clk_rcg2 gcc_emac0_rgmii_clk_src = { 1178 .cmd_rcgr = 0xaa040, 1179 .mnd_width = 8, 1180 .hid_width = 5, 1181 .parent_map = gcc_parent_map_8, 1182 .freq_tbl = ftbl_gcc_emac0_rgmii_clk_src, 1183 .clkr.hw.init = &(const struct clk_init_data) { 1184 .name = "gcc_emac0_rgmii_clk_src", 1185 .parent_data = gcc_parent_data_8, 1186 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 1187 .ops = &clk_rcg2_shared_ops, 1188 }, 1189 }; 1190 1191 static struct clk_rcg2 gcc_emac1_ptp_clk_src = { 1192 .cmd_rcgr = 0xba020, 1193 .mnd_width = 0, 1194 .hid_width = 5, 1195 .parent_map = gcc_parent_map_4, 1196 .freq_tbl = ftbl_gcc_emac0_ptp_clk_src, 1197 .clkr.hw.init = &(const struct clk_init_data) { 1198 .name = "gcc_emac1_ptp_clk_src", 1199 .parent_data = gcc_parent_data_4, 1200 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1201 .ops = &clk_rcg2_shared_ops, 1202 }, 1203 }; 1204 1205 static struct clk_rcg2 gcc_emac1_rgmii_clk_src = { 1206 .cmd_rcgr = 0xba040, 1207 .mnd_width = 8, 1208 .hid_width = 5, 1209 .parent_map = gcc_parent_map_9, 1210 .freq_tbl = ftbl_gcc_emac0_rgmii_clk_src, 1211 .clkr.hw.init = &(const struct clk_init_data) { 1212 .name = "gcc_emac1_rgmii_clk_src", 1213 .parent_data = gcc_parent_data_9, 1214 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 1215 .ops = &clk_rcg2_shared_ops, 1216 }, 1217 }; 1218 1219 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 1220 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 1221 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 1222 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1223 { } 1224 }; 1225 1226 static struct clk_rcg2 gcc_gp1_clk_src = { 1227 .cmd_rcgr = 0x64004, 1228 .mnd_width = 16, 1229 .hid_width = 5, 1230 .parent_map = gcc_parent_map_2, 1231 .freq_tbl = ftbl_gcc_gp1_clk_src, 1232 .clkr.hw.init = &(const struct clk_init_data) { 1233 .name = "gcc_gp1_clk_src", 1234 .parent_data = gcc_parent_data_2, 1235 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1236 .ops = &clk_rcg2_shared_ops, 1237 }, 1238 }; 1239 1240 static struct clk_rcg2 gcc_gp2_clk_src = { 1241 .cmd_rcgr = 0x65004, 1242 .mnd_width = 16, 1243 .hid_width = 5, 1244 .parent_map = gcc_parent_map_2, 1245 .freq_tbl = ftbl_gcc_gp1_clk_src, 1246 .clkr.hw.init = &(const struct clk_init_data) { 1247 .name = "gcc_gp2_clk_src", 1248 .parent_data = gcc_parent_data_2, 1249 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1250 .ops = &clk_rcg2_shared_ops, 1251 }, 1252 }; 1253 1254 static struct clk_rcg2 gcc_gp3_clk_src = { 1255 .cmd_rcgr = 0x66004, 1256 .mnd_width = 16, 1257 .hid_width = 5, 1258 .parent_map = gcc_parent_map_2, 1259 .freq_tbl = ftbl_gcc_gp1_clk_src, 1260 .clkr.hw.init = &(const struct clk_init_data) { 1261 .name = "gcc_gp3_clk_src", 1262 .parent_data = gcc_parent_data_2, 1263 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1264 .ops = &clk_rcg2_shared_ops, 1265 }, 1266 }; 1267 1268 static struct clk_rcg2 gcc_gp4_clk_src = { 1269 .cmd_rcgr = 0xc2004, 1270 .mnd_width = 16, 1271 .hid_width = 5, 1272 .parent_map = gcc_parent_map_2, 1273 .freq_tbl = ftbl_gcc_gp1_clk_src, 1274 .clkr.hw.init = &(const struct clk_init_data) { 1275 .name = "gcc_gp4_clk_src", 1276 .parent_data = gcc_parent_data_2, 1277 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1278 .ops = &clk_rcg2_shared_ops, 1279 }, 1280 }; 1281 1282 static struct clk_rcg2 gcc_gp5_clk_src = { 1283 .cmd_rcgr = 0xc3004, 1284 .mnd_width = 16, 1285 .hid_width = 5, 1286 .parent_map = gcc_parent_map_2, 1287 .freq_tbl = ftbl_gcc_gp1_clk_src, 1288 .clkr.hw.init = &(const struct clk_init_data) { 1289 .name = "gcc_gp5_clk_src", 1290 .parent_data = gcc_parent_data_2, 1291 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1292 .ops = &clk_rcg2_shared_ops, 1293 }, 1294 }; 1295 1296 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 1297 F(9600000, P_BI_TCXO, 2, 0, 0), 1298 F(19200000, P_BI_TCXO, 1, 0, 0), 1299 { } 1300 }; 1301 1302 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 1303 .cmd_rcgr = 0xa4054, 1304 .mnd_width = 16, 1305 .hid_width = 5, 1306 .parent_map = gcc_parent_map_1, 1307 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1308 .clkr.hw.init = &(const struct clk_init_data) { 1309 .name = "gcc_pcie_0_aux_clk_src", 1310 .parent_data = gcc_parent_data_1, 1311 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1312 .ops = &clk_rcg2_shared_ops, 1313 }, 1314 }; 1315 1316 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 1317 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1318 { } 1319 }; 1320 1321 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 1322 .cmd_rcgr = 0xa403c, 1323 .mnd_width = 0, 1324 .hid_width = 5, 1325 .parent_map = gcc_parent_map_0, 1326 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1327 .clkr.hw.init = &(const struct clk_init_data) { 1328 .name = "gcc_pcie_0_phy_rchng_clk_src", 1329 .parent_data = gcc_parent_data_0, 1330 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1331 .ops = &clk_rcg2_shared_ops, 1332 }, 1333 }; 1334 1335 static const struct freq_tbl ftbl_gcc_pcie_1_aux_clk_src[] = { 1336 F(19200000, P_BI_TCXO, 1, 0, 0), 1337 { } 1338 }; 1339 1340 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 1341 .cmd_rcgr = 0x8d054, 1342 .mnd_width = 16, 1343 .hid_width = 5, 1344 .parent_map = gcc_parent_map_1, 1345 .freq_tbl = ftbl_gcc_pcie_1_aux_clk_src, 1346 .clkr.hw.init = &(const struct clk_init_data) { 1347 .name = "gcc_pcie_1_aux_clk_src", 1348 .parent_data = gcc_parent_data_1, 1349 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1350 .ops = &clk_rcg2_shared_ops, 1351 }, 1352 }; 1353 1354 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 1355 .cmd_rcgr = 0x8d03c, 1356 .mnd_width = 0, 1357 .hid_width = 5, 1358 .parent_map = gcc_parent_map_0, 1359 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1360 .clkr.hw.init = &(const struct clk_init_data) { 1361 .name = "gcc_pcie_1_phy_rchng_clk_src", 1362 .parent_data = gcc_parent_data_0, 1363 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1364 .ops = &clk_rcg2_shared_ops, 1365 }, 1366 }; 1367 1368 static struct clk_rcg2 gcc_pcie_2a_aux_clk_src = { 1369 .cmd_rcgr = 0x9d064, 1370 .mnd_width = 16, 1371 .hid_width = 5, 1372 .parent_map = gcc_parent_map_1, 1373 .freq_tbl = ftbl_gcc_pcie_1_aux_clk_src, 1374 .clkr.hw.init = &(const struct clk_init_data) { 1375 .name = "gcc_pcie_2a_aux_clk_src", 1376 .parent_data = gcc_parent_data_1, 1377 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1378 .ops = &clk_rcg2_shared_ops, 1379 }, 1380 }; 1381 1382 static struct clk_rcg2 gcc_pcie_2a_phy_rchng_clk_src = { 1383 .cmd_rcgr = 0x9d044, 1384 .mnd_width = 0, 1385 .hid_width = 5, 1386 .parent_map = gcc_parent_map_0, 1387 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1388 .clkr.hw.init = &(const struct clk_init_data) { 1389 .name = "gcc_pcie_2a_phy_rchng_clk_src", 1390 .parent_data = gcc_parent_data_0, 1391 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1392 .ops = &clk_rcg2_shared_ops, 1393 }, 1394 }; 1395 1396 static struct clk_rcg2 gcc_pcie_2b_aux_clk_src = { 1397 .cmd_rcgr = 0x9e064, 1398 .mnd_width = 16, 1399 .hid_width = 5, 1400 .parent_map = gcc_parent_map_1, 1401 .freq_tbl = ftbl_gcc_pcie_1_aux_clk_src, 1402 .clkr.hw.init = &(const struct clk_init_data) { 1403 .name = "gcc_pcie_2b_aux_clk_src", 1404 .parent_data = gcc_parent_data_1, 1405 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1406 .ops = &clk_rcg2_shared_ops, 1407 }, 1408 }; 1409 1410 static struct clk_rcg2 gcc_pcie_2b_phy_rchng_clk_src = { 1411 .cmd_rcgr = 0x9e044, 1412 .mnd_width = 0, 1413 .hid_width = 5, 1414 .parent_map = gcc_parent_map_0, 1415 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1416 .clkr.hw.init = &(const struct clk_init_data) { 1417 .name = "gcc_pcie_2b_phy_rchng_clk_src", 1418 .parent_data = gcc_parent_data_0, 1419 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1420 .ops = &clk_rcg2_shared_ops, 1421 }, 1422 }; 1423 1424 static struct clk_rcg2 gcc_pcie_3a_aux_clk_src = { 1425 .cmd_rcgr = 0xa0064, 1426 .mnd_width = 16, 1427 .hid_width = 5, 1428 .parent_map = gcc_parent_map_1, 1429 .freq_tbl = ftbl_gcc_pcie_1_aux_clk_src, 1430 .clkr.hw.init = &(const struct clk_init_data) { 1431 .name = "gcc_pcie_3a_aux_clk_src", 1432 .parent_data = gcc_parent_data_1, 1433 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1434 .ops = &clk_rcg2_shared_ops, 1435 }, 1436 }; 1437 1438 static struct clk_rcg2 gcc_pcie_3a_phy_rchng_clk_src = { 1439 .cmd_rcgr = 0xa0044, 1440 .mnd_width = 0, 1441 .hid_width = 5, 1442 .parent_map = gcc_parent_map_0, 1443 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1444 .clkr.hw.init = &(const struct clk_init_data) { 1445 .name = "gcc_pcie_3a_phy_rchng_clk_src", 1446 .parent_data = gcc_parent_data_0, 1447 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1448 .ops = &clk_rcg2_shared_ops, 1449 }, 1450 }; 1451 1452 static struct clk_rcg2 gcc_pcie_3b_aux_clk_src = { 1453 .cmd_rcgr = 0xa2064, 1454 .mnd_width = 16, 1455 .hid_width = 5, 1456 .parent_map = gcc_parent_map_1, 1457 .freq_tbl = ftbl_gcc_pcie_1_aux_clk_src, 1458 .clkr.hw.init = &(const struct clk_init_data) { 1459 .name = "gcc_pcie_3b_aux_clk_src", 1460 .parent_data = gcc_parent_data_1, 1461 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1462 .ops = &clk_rcg2_shared_ops, 1463 }, 1464 }; 1465 1466 static struct clk_rcg2 gcc_pcie_3b_phy_rchng_clk_src = { 1467 .cmd_rcgr = 0xa2044, 1468 .mnd_width = 0, 1469 .hid_width = 5, 1470 .parent_map = gcc_parent_map_0, 1471 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1472 .clkr.hw.init = &(const struct clk_init_data) { 1473 .name = "gcc_pcie_3b_phy_rchng_clk_src", 1474 .parent_data = gcc_parent_data_0, 1475 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1476 .ops = &clk_rcg2_shared_ops, 1477 }, 1478 }; 1479 1480 static struct clk_rcg2 gcc_pcie_4_aux_clk_src = { 1481 .cmd_rcgr = 0x6b064, 1482 .mnd_width = 16, 1483 .hid_width = 5, 1484 .parent_map = gcc_parent_map_1, 1485 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1486 .clkr.hw.init = &(const struct clk_init_data) { 1487 .name = "gcc_pcie_4_aux_clk_src", 1488 .parent_data = gcc_parent_data_1, 1489 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1490 .ops = &clk_rcg2_shared_ops, 1491 }, 1492 }; 1493 1494 static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src = { 1495 .cmd_rcgr = 0x6b044, 1496 .mnd_width = 0, 1497 .hid_width = 5, 1498 .parent_map = gcc_parent_map_0, 1499 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1500 .clkr.hw.init = &(const struct clk_init_data) { 1501 .name = "gcc_pcie_4_phy_rchng_clk_src", 1502 .parent_data = gcc_parent_data_0, 1503 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1504 .ops = &clk_rcg2_shared_ops, 1505 }, 1506 }; 1507 1508 static struct clk_rcg2 gcc_pcie_rscc_xo_clk_src = { 1509 .cmd_rcgr = 0xae00c, 1510 .mnd_width = 0, 1511 .hid_width = 5, 1512 .parent_map = gcc_parent_map_3, 1513 .freq_tbl = ftbl_gcc_pcie_1_aux_clk_src, 1514 .clkr.hw.init = &(const struct clk_init_data) { 1515 .name = "gcc_pcie_rscc_xo_clk_src", 1516 .parent_data = gcc_parent_data_3, 1517 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1518 .ops = &clk_rcg2_shared_ops, 1519 }, 1520 }; 1521 1522 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 1523 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0), 1524 { } 1525 }; 1526 1527 static struct clk_rcg2 gcc_pdm2_clk_src = { 1528 .cmd_rcgr = 0x33010, 1529 .mnd_width = 0, 1530 .hid_width = 5, 1531 .parent_map = gcc_parent_map_0, 1532 .freq_tbl = ftbl_gcc_pdm2_clk_src, 1533 .clkr.hw.init = &(const struct clk_init_data) { 1534 .name = "gcc_pdm2_clk_src", 1535 .parent_data = gcc_parent_data_0, 1536 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1537 .ops = &clk_rcg2_shared_ops, 1538 }, 1539 }; 1540 1541 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 1542 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 1543 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 1544 F(19200000, P_BI_TCXO, 1, 0, 0), 1545 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 1546 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 1547 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 1548 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 1549 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1550 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 1551 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 1552 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 1553 { } 1554 }; 1555 1556 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 1557 .name = "gcc_qupv3_wrap0_s0_clk_src", 1558 .parent_data = gcc_parent_data_0, 1559 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1560 .flags = CLK_SET_RATE_PARENT, 1561 .ops = &clk_rcg2_shared_ops, 1562 }; 1563 1564 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 1565 .cmd_rcgr = 0x17148, 1566 .mnd_width = 16, 1567 .hid_width = 5, 1568 .parent_map = gcc_parent_map_0, 1569 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1570 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 1571 }; 1572 1573 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 1574 .name = "gcc_qupv3_wrap0_s1_clk_src", 1575 .parent_data = gcc_parent_data_0, 1576 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1577 .flags = CLK_SET_RATE_PARENT, 1578 .ops = &clk_rcg2_shared_ops, 1579 }; 1580 1581 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 1582 .cmd_rcgr = 0x17278, 1583 .mnd_width = 16, 1584 .hid_width = 5, 1585 .parent_map = gcc_parent_map_0, 1586 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1587 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 1588 }; 1589 1590 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 1591 .name = "gcc_qupv3_wrap0_s2_clk_src", 1592 .parent_data = gcc_parent_data_0, 1593 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1594 .flags = CLK_SET_RATE_PARENT, 1595 .ops = &clk_rcg2_shared_ops, 1596 }; 1597 1598 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 1599 .cmd_rcgr = 0x173a8, 1600 .mnd_width = 16, 1601 .hid_width = 5, 1602 .parent_map = gcc_parent_map_0, 1603 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1604 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 1605 }; 1606 1607 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 1608 .name = "gcc_qupv3_wrap0_s3_clk_src", 1609 .parent_data = gcc_parent_data_0, 1610 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1611 .flags = CLK_SET_RATE_PARENT, 1612 .ops = &clk_rcg2_shared_ops, 1613 }; 1614 1615 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 1616 .cmd_rcgr = 0x174d8, 1617 .mnd_width = 16, 1618 .hid_width = 5, 1619 .parent_map = gcc_parent_map_0, 1620 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1621 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 1622 }; 1623 1624 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 1625 .name = "gcc_qupv3_wrap0_s4_clk_src", 1626 .parent_data = gcc_parent_data_0, 1627 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1628 .flags = CLK_SET_RATE_PARENT, 1629 .ops = &clk_rcg2_shared_ops, 1630 }; 1631 1632 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 1633 .cmd_rcgr = 0x17608, 1634 .mnd_width = 16, 1635 .hid_width = 5, 1636 .parent_map = gcc_parent_map_0, 1637 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1638 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 1639 }; 1640 1641 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 1642 .name = "gcc_qupv3_wrap0_s5_clk_src", 1643 .parent_data = gcc_parent_data_0, 1644 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1645 .flags = CLK_SET_RATE_PARENT, 1646 .ops = &clk_rcg2_shared_ops, 1647 }; 1648 1649 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 1650 .cmd_rcgr = 0x17738, 1651 .mnd_width = 16, 1652 .hid_width = 5, 1653 .parent_map = gcc_parent_map_0, 1654 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1655 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 1656 }; 1657 1658 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s6_clk_src[] = { 1659 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 1660 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 1661 F(19200000, P_BI_TCXO, 1, 0, 0), 1662 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 1663 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 1664 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 1665 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 1666 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1667 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 1668 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 1669 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 1670 { } 1671 }; 1672 1673 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 1674 .name = "gcc_qupv3_wrap0_s6_clk_src", 1675 .parent_data = gcc_parent_data_0, 1676 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1677 .flags = CLK_SET_RATE_PARENT, 1678 .ops = &clk_rcg2_shared_ops, 1679 }; 1680 1681 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 1682 .cmd_rcgr = 0x17868, 1683 .mnd_width = 16, 1684 .hid_width = 5, 1685 .parent_map = gcc_parent_map_0, 1686 .freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src, 1687 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 1688 }; 1689 1690 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 1691 .name = "gcc_qupv3_wrap0_s7_clk_src", 1692 .parent_data = gcc_parent_data_0, 1693 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1694 .flags = CLK_SET_RATE_PARENT, 1695 .ops = &clk_rcg2_shared_ops, 1696 }; 1697 1698 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 1699 .cmd_rcgr = 0x17998, 1700 .mnd_width = 16, 1701 .hid_width = 5, 1702 .parent_map = gcc_parent_map_0, 1703 .freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src, 1704 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 1705 }; 1706 1707 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 1708 .name = "gcc_qupv3_wrap1_s0_clk_src", 1709 .parent_data = gcc_parent_data_0, 1710 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1711 .flags = CLK_SET_RATE_PARENT, 1712 .ops = &clk_rcg2_shared_ops, 1713 }; 1714 1715 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 1716 .cmd_rcgr = 0x18148, 1717 .mnd_width = 16, 1718 .hid_width = 5, 1719 .parent_map = gcc_parent_map_0, 1720 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1721 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 1722 }; 1723 1724 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 1725 .name = "gcc_qupv3_wrap1_s1_clk_src", 1726 .parent_data = gcc_parent_data_0, 1727 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1728 .flags = CLK_SET_RATE_PARENT, 1729 .ops = &clk_rcg2_shared_ops, 1730 }; 1731 1732 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 1733 .cmd_rcgr = 0x18278, 1734 .mnd_width = 16, 1735 .hid_width = 5, 1736 .parent_map = gcc_parent_map_0, 1737 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1738 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 1739 }; 1740 1741 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 1742 .name = "gcc_qupv3_wrap1_s2_clk_src", 1743 .parent_data = gcc_parent_data_0, 1744 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1745 .flags = CLK_SET_RATE_PARENT, 1746 .ops = &clk_rcg2_shared_ops, 1747 }; 1748 1749 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 1750 .cmd_rcgr = 0x183a8, 1751 .mnd_width = 16, 1752 .hid_width = 5, 1753 .parent_map = gcc_parent_map_0, 1754 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1755 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 1756 }; 1757 1758 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 1759 .name = "gcc_qupv3_wrap1_s3_clk_src", 1760 .parent_data = gcc_parent_data_0, 1761 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1762 .flags = CLK_SET_RATE_PARENT, 1763 .ops = &clk_rcg2_shared_ops, 1764 }; 1765 1766 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 1767 .cmd_rcgr = 0x184d8, 1768 .mnd_width = 16, 1769 .hid_width = 5, 1770 .parent_map = gcc_parent_map_0, 1771 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1772 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 1773 }; 1774 1775 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 1776 .name = "gcc_qupv3_wrap1_s4_clk_src", 1777 .parent_data = gcc_parent_data_0, 1778 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1779 .flags = CLK_SET_RATE_PARENT, 1780 .ops = &clk_rcg2_shared_ops, 1781 }; 1782 1783 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 1784 .cmd_rcgr = 0x18608, 1785 .mnd_width = 16, 1786 .hid_width = 5, 1787 .parent_map = gcc_parent_map_0, 1788 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1789 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 1790 }; 1791 1792 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 1793 .name = "gcc_qupv3_wrap1_s5_clk_src", 1794 .parent_data = gcc_parent_data_0, 1795 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1796 .flags = CLK_SET_RATE_PARENT, 1797 .ops = &clk_rcg2_shared_ops, 1798 }; 1799 1800 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 1801 .cmd_rcgr = 0x18738, 1802 .mnd_width = 16, 1803 .hid_width = 5, 1804 .parent_map = gcc_parent_map_0, 1805 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1806 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 1807 }; 1808 1809 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 1810 .name = "gcc_qupv3_wrap1_s6_clk_src", 1811 .parent_data = gcc_parent_data_0, 1812 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1813 .flags = CLK_SET_RATE_PARENT, 1814 .ops = &clk_rcg2_shared_ops, 1815 }; 1816 1817 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 1818 .cmd_rcgr = 0x18868, 1819 .mnd_width = 16, 1820 .hid_width = 5, 1821 .parent_map = gcc_parent_map_0, 1822 .freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src, 1823 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 1824 }; 1825 1826 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 1827 .name = "gcc_qupv3_wrap1_s7_clk_src", 1828 .parent_data = gcc_parent_data_0, 1829 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1830 .flags = CLK_SET_RATE_PARENT, 1831 .ops = &clk_rcg2_shared_ops, 1832 }; 1833 1834 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 1835 .cmd_rcgr = 0x18998, 1836 .mnd_width = 16, 1837 .hid_width = 5, 1838 .parent_map = gcc_parent_map_0, 1839 .freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src, 1840 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 1841 }; 1842 1843 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 1844 .name = "gcc_qupv3_wrap2_s0_clk_src", 1845 .parent_data = gcc_parent_data_0, 1846 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1847 .flags = CLK_SET_RATE_PARENT, 1848 .ops = &clk_rcg2_shared_ops, 1849 }; 1850 1851 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 1852 .cmd_rcgr = 0x1e148, 1853 .mnd_width = 16, 1854 .hid_width = 5, 1855 .parent_map = gcc_parent_map_0, 1856 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1857 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 1858 }; 1859 1860 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 1861 .name = "gcc_qupv3_wrap2_s1_clk_src", 1862 .parent_data = gcc_parent_data_0, 1863 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1864 .flags = CLK_SET_RATE_PARENT, 1865 .ops = &clk_rcg2_shared_ops, 1866 }; 1867 1868 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 1869 .cmd_rcgr = 0x1e278, 1870 .mnd_width = 16, 1871 .hid_width = 5, 1872 .parent_map = gcc_parent_map_0, 1873 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1874 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 1875 }; 1876 1877 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 1878 .name = "gcc_qupv3_wrap2_s2_clk_src", 1879 .parent_data = gcc_parent_data_0, 1880 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1881 .flags = CLK_SET_RATE_PARENT, 1882 .ops = &clk_rcg2_shared_ops, 1883 }; 1884 1885 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 1886 .cmd_rcgr = 0x1e3a8, 1887 .mnd_width = 16, 1888 .hid_width = 5, 1889 .parent_map = gcc_parent_map_0, 1890 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1891 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 1892 }; 1893 1894 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 1895 .name = "gcc_qupv3_wrap2_s3_clk_src", 1896 .parent_data = gcc_parent_data_0, 1897 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1898 .flags = CLK_SET_RATE_PARENT, 1899 .ops = &clk_rcg2_shared_ops, 1900 }; 1901 1902 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 1903 .cmd_rcgr = 0x1e4d8, 1904 .mnd_width = 16, 1905 .hid_width = 5, 1906 .parent_map = gcc_parent_map_0, 1907 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1908 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 1909 }; 1910 1911 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 1912 .name = "gcc_qupv3_wrap2_s4_clk_src", 1913 .parent_data = gcc_parent_data_0, 1914 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1915 .flags = CLK_SET_RATE_PARENT, 1916 .ops = &clk_rcg2_shared_ops, 1917 }; 1918 1919 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 1920 .cmd_rcgr = 0x1e608, 1921 .mnd_width = 16, 1922 .hid_width = 5, 1923 .parent_map = gcc_parent_map_0, 1924 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1925 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 1926 }; 1927 1928 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 1929 .name = "gcc_qupv3_wrap2_s5_clk_src", 1930 .parent_data = gcc_parent_data_0, 1931 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1932 .flags = CLK_SET_RATE_PARENT, 1933 .ops = &clk_rcg2_shared_ops, 1934 }; 1935 1936 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 1937 .cmd_rcgr = 0x1e738, 1938 .mnd_width = 16, 1939 .hid_width = 5, 1940 .parent_map = gcc_parent_map_0, 1941 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1942 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 1943 }; 1944 1945 static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { 1946 .name = "gcc_qupv3_wrap2_s6_clk_src", 1947 .parent_data = gcc_parent_data_0, 1948 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1949 .flags = CLK_SET_RATE_PARENT, 1950 .ops = &clk_rcg2_shared_ops, 1951 }; 1952 1953 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { 1954 .cmd_rcgr = 0x1e868, 1955 .mnd_width = 16, 1956 .hid_width = 5, 1957 .parent_map = gcc_parent_map_0, 1958 .freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src, 1959 .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init, 1960 }; 1961 1962 static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = { 1963 .name = "gcc_qupv3_wrap2_s7_clk_src", 1964 .parent_data = gcc_parent_data_0, 1965 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1966 .flags = CLK_SET_RATE_PARENT, 1967 .ops = &clk_rcg2_shared_ops, 1968 }; 1969 1970 static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = { 1971 .cmd_rcgr = 0x1e998, 1972 .mnd_width = 16, 1973 .hid_width = 5, 1974 .parent_map = gcc_parent_map_0, 1975 .freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src, 1976 .clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init, 1977 }; 1978 1979 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1980 F(400000, P_BI_TCXO, 12, 1, 4), 1981 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1982 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 1983 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1984 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 1985 { } 1986 }; 1987 1988 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1989 .cmd_rcgr = 0x1400c, 1990 .mnd_width = 8, 1991 .hid_width = 5, 1992 .parent_map = gcc_parent_map_15, 1993 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1994 .clkr.hw.init = &(const struct clk_init_data) { 1995 .name = "gcc_sdcc2_apps_clk_src", 1996 .parent_data = gcc_parent_data_15, 1997 .num_parents = ARRAY_SIZE(gcc_parent_data_15), 1998 .ops = &clk_rcg2_shared_ops, 1999 }, 2000 }; 2001 2002 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 2003 F(400000, P_BI_TCXO, 12, 1, 4), 2004 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 2005 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 2006 { } 2007 }; 2008 2009 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 2010 .cmd_rcgr = 0x1600c, 2011 .mnd_width = 8, 2012 .hid_width = 5, 2013 .parent_map = gcc_parent_map_0, 2014 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 2015 .clkr.hw.init = &(const struct clk_init_data) { 2016 .name = "gcc_sdcc4_apps_clk_src", 2017 .parent_data = gcc_parent_data_0, 2018 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2019 .ops = &clk_rcg2_shared_ops, 2020 }, 2021 }; 2022 2023 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { 2024 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 2025 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 2026 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 2027 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 2028 { } 2029 }; 2030 2031 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { 2032 .cmd_rcgr = 0x75024, 2033 .mnd_width = 8, 2034 .hid_width = 5, 2035 .parent_map = gcc_parent_map_0, 2036 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, 2037 .clkr.hw.init = &(const struct clk_init_data) { 2038 .name = "gcc_ufs_card_axi_clk_src", 2039 .parent_data = gcc_parent_data_0, 2040 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2041 .ops = &clk_rcg2_shared_ops, 2042 }, 2043 }; 2044 2045 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { 2046 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 2047 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 2048 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 2049 { } 2050 }; 2051 2052 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { 2053 .cmd_rcgr = 0x7506c, 2054 .mnd_width = 0, 2055 .hid_width = 5, 2056 .parent_map = gcc_parent_map_0, 2057 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 2058 .clkr.hw.init = &(const struct clk_init_data) { 2059 .name = "gcc_ufs_card_ice_core_clk_src", 2060 .parent_data = gcc_parent_data_0, 2061 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2062 .ops = &clk_rcg2_shared_ops, 2063 }, 2064 }; 2065 2066 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { 2067 .cmd_rcgr = 0x750a0, 2068 .mnd_width = 0, 2069 .hid_width = 5, 2070 .parent_map = gcc_parent_map_3, 2071 .freq_tbl = ftbl_gcc_pcie_1_aux_clk_src, 2072 .clkr.hw.init = &(const struct clk_init_data) { 2073 .name = "gcc_ufs_card_phy_aux_clk_src", 2074 .parent_data = gcc_parent_data_3, 2075 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 2076 .ops = &clk_rcg2_shared_ops, 2077 }, 2078 }; 2079 2080 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { 2081 .cmd_rcgr = 0x75084, 2082 .mnd_width = 0, 2083 .hid_width = 5, 2084 .parent_map = gcc_parent_map_0, 2085 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 2086 .clkr.hw.init = &(const struct clk_init_data) { 2087 .name = "gcc_ufs_card_unipro_core_clk_src", 2088 .parent_data = gcc_parent_data_0, 2089 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2090 .ops = &clk_rcg2_shared_ops, 2091 }, 2092 }; 2093 2094 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 2095 .cmd_rcgr = 0x77024, 2096 .mnd_width = 8, 2097 .hid_width = 5, 2098 .parent_map = gcc_parent_map_0, 2099 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, 2100 .clkr.hw.init = &(const struct clk_init_data) { 2101 .name = "gcc_ufs_phy_axi_clk_src", 2102 .parent_data = gcc_parent_data_0, 2103 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2104 .ops = &clk_rcg2_shared_ops, 2105 }, 2106 }; 2107 2108 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 2109 .cmd_rcgr = 0x7706c, 2110 .mnd_width = 0, 2111 .hid_width = 5, 2112 .parent_map = gcc_parent_map_0, 2113 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 2114 .clkr.hw.init = &(const struct clk_init_data) { 2115 .name = "gcc_ufs_phy_ice_core_clk_src", 2116 .parent_data = gcc_parent_data_0, 2117 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2118 .ops = &clk_rcg2_shared_ops, 2119 }, 2120 }; 2121 2122 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 2123 .cmd_rcgr = 0x770a0, 2124 .mnd_width = 0, 2125 .hid_width = 5, 2126 .parent_map = gcc_parent_map_3, 2127 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2128 .clkr.hw.init = &(const struct clk_init_data) { 2129 .name = "gcc_ufs_phy_phy_aux_clk_src", 2130 .parent_data = gcc_parent_data_3, 2131 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 2132 .ops = &clk_rcg2_shared_ops, 2133 }, 2134 }; 2135 2136 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 2137 .cmd_rcgr = 0x77084, 2138 .mnd_width = 0, 2139 .hid_width = 5, 2140 .parent_map = gcc_parent_map_0, 2141 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 2142 .clkr.hw.init = &(const struct clk_init_data) { 2143 .name = "gcc_ufs_phy_unipro_core_clk_src", 2144 .parent_data = gcc_parent_data_0, 2145 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2146 .ops = &clk_rcg2_shared_ops, 2147 }, 2148 }; 2149 2150 static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = { 2151 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 2152 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 2153 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 2154 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 2155 { } 2156 }; 2157 2158 static struct clk_rcg2 gcc_usb30_mp_master_clk_src = { 2159 .cmd_rcgr = 0xab020, 2160 .mnd_width = 8, 2161 .hid_width = 5, 2162 .parent_map = gcc_parent_map_0, 2163 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 2164 .clkr.hw.init = &(const struct clk_init_data) { 2165 .name = "gcc_usb30_mp_master_clk_src", 2166 .parent_data = gcc_parent_data_0, 2167 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2168 .ops = &clk_rcg2_shared_ops, 2169 }, 2170 }; 2171 2172 static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = { 2173 .cmd_rcgr = 0xab038, 2174 .mnd_width = 0, 2175 .hid_width = 5, 2176 .parent_map = gcc_parent_map_0, 2177 .freq_tbl = ftbl_gcc_pcie_1_aux_clk_src, 2178 .clkr.hw.init = &(const struct clk_init_data) { 2179 .name = "gcc_usb30_mp_mock_utmi_clk_src", 2180 .parent_data = gcc_parent_data_0, 2181 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2182 .ops = &clk_rcg2_shared_ops, 2183 }, 2184 }; 2185 2186 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 2187 .cmd_rcgr = 0xf020, 2188 .mnd_width = 8, 2189 .hid_width = 5, 2190 .parent_map = gcc_parent_map_0, 2191 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 2192 .clkr.hw.init = &(const struct clk_init_data) { 2193 .name = "gcc_usb30_prim_master_clk_src", 2194 .parent_data = gcc_parent_data_0, 2195 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2196 .ops = &clk_rcg2_shared_ops, 2197 }, 2198 }; 2199 2200 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 2201 .cmd_rcgr = 0xf038, 2202 .mnd_width = 0, 2203 .hid_width = 5, 2204 .parent_map = gcc_parent_map_0, 2205 .freq_tbl = ftbl_gcc_pcie_1_aux_clk_src, 2206 .clkr.hw.init = &(const struct clk_init_data) { 2207 .name = "gcc_usb30_prim_mock_utmi_clk_src", 2208 .parent_data = gcc_parent_data_0, 2209 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2210 .ops = &clk_rcg2_shared_ops, 2211 }, 2212 }; 2213 2214 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { 2215 .cmd_rcgr = 0x10020, 2216 .mnd_width = 8, 2217 .hid_width = 5, 2218 .parent_map = gcc_parent_map_0, 2219 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 2220 .clkr.hw.init = &(const struct clk_init_data) { 2221 .name = "gcc_usb30_sec_master_clk_src", 2222 .parent_data = gcc_parent_data_0, 2223 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2224 .ops = &clk_rcg2_shared_ops, 2225 }, 2226 }; 2227 2228 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { 2229 .cmd_rcgr = 0x10038, 2230 .mnd_width = 0, 2231 .hid_width = 5, 2232 .parent_map = gcc_parent_map_0, 2233 .freq_tbl = ftbl_gcc_pcie_1_aux_clk_src, 2234 .clkr.hw.init = &(const struct clk_init_data) { 2235 .name = "gcc_usb30_sec_mock_utmi_clk_src", 2236 .parent_data = gcc_parent_data_0, 2237 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2238 .ops = &clk_rcg2_shared_ops, 2239 }, 2240 }; 2241 2242 static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = { 2243 .cmd_rcgr = 0xab06c, 2244 .mnd_width = 0, 2245 .hid_width = 5, 2246 .parent_map = gcc_parent_map_1, 2247 .freq_tbl = ftbl_gcc_pcie_1_aux_clk_src, 2248 .clkr.hw.init = &(const struct clk_init_data) { 2249 .name = "gcc_usb3_mp_phy_aux_clk_src", 2250 .parent_data = gcc_parent_data_1, 2251 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2252 .ops = &clk_rcg2_shared_ops, 2253 }, 2254 }; 2255 2256 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 2257 .cmd_rcgr = 0xf068, 2258 .mnd_width = 0, 2259 .hid_width = 5, 2260 .parent_map = gcc_parent_map_1, 2261 .freq_tbl = ftbl_gcc_pcie_1_aux_clk_src, 2262 .clkr.hw.init = &(const struct clk_init_data) { 2263 .name = "gcc_usb3_prim_phy_aux_clk_src", 2264 .parent_data = gcc_parent_data_1, 2265 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2266 .ops = &clk_rcg2_shared_ops, 2267 }, 2268 }; 2269 2270 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { 2271 .cmd_rcgr = 0x10068, 2272 .mnd_width = 0, 2273 .hid_width = 5, 2274 .parent_map = gcc_parent_map_1, 2275 .freq_tbl = ftbl_gcc_pcie_1_aux_clk_src, 2276 .clkr.hw.init = &(const struct clk_init_data) { 2277 .name = "gcc_usb3_sec_phy_aux_clk_src", 2278 .parent_data = gcc_parent_data_1, 2279 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2280 .ops = &clk_rcg2_shared_ops, 2281 }, 2282 }; 2283 2284 static const struct freq_tbl ftbl_gcc_usb4_1_master_clk_src[] = { 2285 F(85714286, P_GCC_GPLL0_OUT_EVEN, 3.5, 0, 0), 2286 F(175000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0), 2287 F(350000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0), 2288 { } 2289 }; 2290 2291 static struct clk_rcg2 gcc_usb4_1_master_clk_src = { 2292 .cmd_rcgr = 0xb8018, 2293 .mnd_width = 8, 2294 .hid_width = 5, 2295 .parent_map = gcc_parent_map_5, 2296 .freq_tbl = ftbl_gcc_usb4_1_master_clk_src, 2297 .clkr.hw.init = &(const struct clk_init_data) { 2298 .name = "gcc_usb4_1_master_clk_src", 2299 .parent_data = gcc_parent_data_5, 2300 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 2301 .ops = &clk_rcg2_shared_ops, 2302 }, 2303 }; 2304 2305 static const struct freq_tbl ftbl_gcc_usb4_1_phy_pcie_pipe_clk_src[] = { 2306 F(19200000, P_BI_TCXO, 1, 0, 0), 2307 F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0), 2308 F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0), 2309 { } 2310 }; 2311 2312 static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src = { 2313 .cmd_rcgr = 0xb80c4, 2314 .mnd_width = 0, 2315 .hid_width = 5, 2316 .parent_map = gcc_parent_map_6, 2317 .freq_tbl = ftbl_gcc_usb4_1_phy_pcie_pipe_clk_src, 2318 .clkr.hw.init = &(const struct clk_init_data) { 2319 .name = "gcc_usb4_1_phy_pcie_pipe_clk_src", 2320 .parent_data = gcc_parent_data_6, 2321 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 2322 .ops = &clk_rcg2_shared_ops, 2323 }, 2324 }; 2325 2326 static struct clk_rcg2 gcc_usb4_1_sb_if_clk_src = { 2327 .cmd_rcgr = 0xb8070, 2328 .mnd_width = 0, 2329 .hid_width = 5, 2330 .parent_map = gcc_parent_map_1, 2331 .freq_tbl = ftbl_gcc_pcie_1_aux_clk_src, 2332 .clkr.hw.init = &(const struct clk_init_data) { 2333 .name = "gcc_usb4_1_sb_if_clk_src", 2334 .parent_data = gcc_parent_data_1, 2335 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2336 .ops = &clk_rcg2_shared_ops, 2337 }, 2338 }; 2339 2340 static const struct freq_tbl ftbl_gcc_usb4_1_tmu_clk_src[] = { 2341 F(19200000, P_BI_TCXO, 1, 0, 0), 2342 F(250000000, P_GCC_GPLL2_OUT_MAIN, 4, 0, 0), 2343 { } 2344 }; 2345 2346 static struct clk_rcg2 gcc_usb4_1_tmu_clk_src = { 2347 .cmd_rcgr = 0xb8054, 2348 .mnd_width = 0, 2349 .hid_width = 5, 2350 .parent_map = gcc_parent_map_7, 2351 .freq_tbl = ftbl_gcc_usb4_1_tmu_clk_src, 2352 .clkr.hw.init = &(const struct clk_init_data) { 2353 .name = "gcc_usb4_1_tmu_clk_src", 2354 .parent_data = gcc_parent_data_7, 2355 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 2356 .ops = &clk_rcg2_shared_ops, 2357 }, 2358 }; 2359 2360 static struct clk_rcg2 gcc_usb4_master_clk_src = { 2361 .cmd_rcgr = 0x2a018, 2362 .mnd_width = 8, 2363 .hid_width = 5, 2364 .parent_map = gcc_parent_map_5, 2365 .freq_tbl = ftbl_gcc_usb4_1_master_clk_src, 2366 .clkr.hw.init = &(const struct clk_init_data) { 2367 .name = "gcc_usb4_master_clk_src", 2368 .parent_data = gcc_parent_data_5, 2369 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 2370 .ops = &clk_rcg2_shared_ops, 2371 }, 2372 }; 2373 2374 static struct clk_rcg2 gcc_usb4_phy_pcie_pipe_clk_src = { 2375 .cmd_rcgr = 0x2a0c4, 2376 .mnd_width = 0, 2377 .hid_width = 5, 2378 .parent_map = gcc_parent_map_6, 2379 .freq_tbl = ftbl_gcc_usb4_1_phy_pcie_pipe_clk_src, 2380 .clkr.hw.init = &(const struct clk_init_data) { 2381 .name = "gcc_usb4_phy_pcie_pipe_clk_src", 2382 .parent_data = gcc_parent_data_6, 2383 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 2384 .ops = &clk_rcg2_shared_ops, 2385 }, 2386 }; 2387 2388 static struct clk_rcg2 gcc_usb4_sb_if_clk_src = { 2389 .cmd_rcgr = 0x2a070, 2390 .mnd_width = 0, 2391 .hid_width = 5, 2392 .parent_map = gcc_parent_map_1, 2393 .freq_tbl = ftbl_gcc_pcie_1_aux_clk_src, 2394 .clkr.hw.init = &(const struct clk_init_data) { 2395 .name = "gcc_usb4_sb_if_clk_src", 2396 .parent_data = gcc_parent_data_1, 2397 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2398 .ops = &clk_rcg2_shared_ops, 2399 }, 2400 }; 2401 2402 static struct clk_rcg2 gcc_usb4_tmu_clk_src = { 2403 .cmd_rcgr = 0x2a054, 2404 .mnd_width = 0, 2405 .hid_width = 5, 2406 .parent_map = gcc_parent_map_7, 2407 .freq_tbl = ftbl_gcc_usb4_1_tmu_clk_src, 2408 .clkr.hw.init = &(const struct clk_init_data) { 2409 .name = "gcc_usb4_tmu_clk_src", 2410 .parent_data = gcc_parent_data_7, 2411 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 2412 .ops = &clk_rcg2_shared_ops, 2413 }, 2414 }; 2415 2416 static struct clk_regmap_div gcc_pcie_2a_pipe_div_clk_src = { 2417 .reg = 0x9d060, 2418 .shift = 0, 2419 .width = 4, 2420 .clkr.hw.init = &(const struct clk_init_data) { 2421 .name = "gcc_pcie_2a_pipe_div_clk_src", 2422 .parent_hws = (const struct clk_hw*[]){ 2423 &gcc_pcie_2a_pipe_clk_src.clkr.hw, 2424 }, 2425 .num_parents = 1, 2426 .flags = CLK_SET_RATE_PARENT, 2427 .ops = &clk_regmap_div_ro_ops, 2428 }, 2429 }; 2430 2431 static struct clk_regmap_div gcc_pcie_2b_pipe_div_clk_src = { 2432 .reg = 0x9e060, 2433 .shift = 0, 2434 .width = 4, 2435 .clkr.hw.init = &(const struct clk_init_data) { 2436 .name = "gcc_pcie_2b_pipe_div_clk_src", 2437 .parent_hws = (const struct clk_hw*[]){ 2438 &gcc_pcie_2b_pipe_clk_src.clkr.hw, 2439 }, 2440 .num_parents = 1, 2441 .flags = CLK_SET_RATE_PARENT, 2442 .ops = &clk_regmap_div_ro_ops, 2443 }, 2444 }; 2445 2446 static struct clk_regmap_div gcc_pcie_3a_pipe_div_clk_src = { 2447 .reg = 0xa0060, 2448 .shift = 0, 2449 .width = 4, 2450 .clkr.hw.init = &(const struct clk_init_data) { 2451 .name = "gcc_pcie_3a_pipe_div_clk_src", 2452 .parent_hws = (const struct clk_hw*[]){ 2453 &gcc_pcie_3a_pipe_clk_src.clkr.hw, 2454 }, 2455 .num_parents = 1, 2456 .flags = CLK_SET_RATE_PARENT, 2457 .ops = &clk_regmap_div_ro_ops, 2458 }, 2459 }; 2460 2461 static struct clk_regmap_div gcc_pcie_3b_pipe_div_clk_src = { 2462 .reg = 0xa2060, 2463 .shift = 0, 2464 .width = 4, 2465 .clkr.hw.init = &(const struct clk_init_data) { 2466 .name = "gcc_pcie_3b_pipe_div_clk_src", 2467 .parent_hws = (const struct clk_hw*[]){ 2468 &gcc_pcie_3b_pipe_clk_src.clkr.hw, 2469 }, 2470 .num_parents = 1, 2471 .flags = CLK_SET_RATE_PARENT, 2472 .ops = &clk_regmap_div_ro_ops, 2473 }, 2474 }; 2475 2476 static struct clk_regmap_div gcc_pcie_4_pipe_div_clk_src = { 2477 .reg = 0x6b060, 2478 .shift = 0, 2479 .width = 4, 2480 .clkr.hw.init = &(const struct clk_init_data) { 2481 .name = "gcc_pcie_4_pipe_div_clk_src", 2482 .parent_hws = (const struct clk_hw*[]){ 2483 &gcc_pcie_4_pipe_clk_src.clkr.hw, 2484 }, 2485 .num_parents = 1, 2486 .flags = CLK_SET_RATE_PARENT, 2487 .ops = &clk_regmap_div_ro_ops, 2488 }, 2489 }; 2490 2491 static struct clk_regmap_div gcc_qupv3_wrap0_s4_div_clk_src = { 2492 .reg = 0x17ac8, 2493 .shift = 0, 2494 .width = 4, 2495 .clkr.hw.init = &(const struct clk_init_data) { 2496 .name = "gcc_qupv3_wrap0_s4_div_clk_src", 2497 .parent_hws = (const struct clk_hw*[]){ 2498 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2499 }, 2500 .num_parents = 1, 2501 .flags = CLK_SET_RATE_PARENT, 2502 .ops = &clk_regmap_div_ro_ops, 2503 }, 2504 }; 2505 2506 static struct clk_regmap_div gcc_qupv3_wrap1_s4_div_clk_src = { 2507 .reg = 0x18ac8, 2508 .shift = 0, 2509 .width = 4, 2510 .clkr.hw.init = &(const struct clk_init_data) { 2511 .name = "gcc_qupv3_wrap1_s4_div_clk_src", 2512 .parent_hws = (const struct clk_hw*[]){ 2513 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2514 }, 2515 .num_parents = 1, 2516 .flags = CLK_SET_RATE_PARENT, 2517 .ops = &clk_regmap_div_ro_ops, 2518 }, 2519 }; 2520 2521 static struct clk_regmap_div gcc_qupv3_wrap2_s4_div_clk_src = { 2522 .reg = 0x1eac8, 2523 .shift = 0, 2524 .width = 4, 2525 .clkr.hw.init = &(const struct clk_init_data) { 2526 .name = "gcc_qupv3_wrap2_s4_div_clk_src", 2527 .parent_hws = (const struct clk_hw*[]){ 2528 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 2529 }, 2530 .num_parents = 1, 2531 .flags = CLK_SET_RATE_PARENT, 2532 .ops = &clk_regmap_div_ro_ops, 2533 }, 2534 }; 2535 2536 static struct clk_regmap_div gcc_usb30_mp_mock_utmi_postdiv_clk_src = { 2537 .reg = 0xab050, 2538 .shift = 0, 2539 .width = 4, 2540 .clkr.hw.init = &(const struct clk_init_data) { 2541 .name = "gcc_usb30_mp_mock_utmi_postdiv_clk_src", 2542 .parent_hws = (const struct clk_hw*[]){ 2543 &gcc_usb30_mp_mock_utmi_clk_src.clkr.hw, 2544 }, 2545 .num_parents = 1, 2546 .flags = CLK_SET_RATE_PARENT, 2547 .ops = &clk_regmap_div_ro_ops, 2548 }, 2549 }; 2550 2551 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 2552 .reg = 0xf050, 2553 .shift = 0, 2554 .width = 4, 2555 .clkr.hw.init = &(const struct clk_init_data) { 2556 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 2557 .parent_hws = (const struct clk_hw*[]){ 2558 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 2559 }, 2560 .num_parents = 1, 2561 .flags = CLK_SET_RATE_PARENT, 2562 .ops = &clk_regmap_div_ro_ops, 2563 }, 2564 }; 2565 2566 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = { 2567 .reg = 0x10050, 2568 .shift = 0, 2569 .width = 4, 2570 .clkr.hw.init = &(const struct clk_init_data) { 2571 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src", 2572 .parent_hws = (const struct clk_hw*[]){ 2573 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, 2574 }, 2575 .num_parents = 1, 2576 .flags = CLK_SET_RATE_PARENT, 2577 .ops = &clk_regmap_div_ro_ops, 2578 }, 2579 }; 2580 2581 static struct clk_branch gcc_aggre_noc_pcie0_tunnel_axi_clk = { 2582 .halt_reg = 0xa41a8, 2583 .halt_check = BRANCH_HALT_SKIP, 2584 .hwcg_reg = 0xa41a8, 2585 .hwcg_bit = 1, 2586 .clkr = { 2587 .enable_reg = 0x52018, 2588 .enable_mask = BIT(14), 2589 .hw.init = &(const struct clk_init_data) { 2590 .name = "gcc_aggre_noc_pcie0_tunnel_axi_clk", 2591 .ops = &clk_branch2_ops, 2592 }, 2593 }, 2594 }; 2595 2596 static struct clk_branch gcc_aggre_noc_pcie1_tunnel_axi_clk = { 2597 .halt_reg = 0x8d07c, 2598 .halt_check = BRANCH_HALT_SKIP, 2599 .hwcg_reg = 0x8d07c, 2600 .hwcg_bit = 1, 2601 .clkr = { 2602 .enable_reg = 0x52018, 2603 .enable_mask = BIT(21), 2604 .hw.init = &(const struct clk_init_data) { 2605 .name = "gcc_aggre_noc_pcie1_tunnel_axi_clk", 2606 .ops = &clk_branch2_ops, 2607 }, 2608 }, 2609 }; 2610 2611 static struct clk_branch gcc_aggre_noc_pcie_4_axi_clk = { 2612 .halt_reg = 0x6b1b8, 2613 .halt_check = BRANCH_HALT_SKIP, 2614 .hwcg_reg = 0x6b1b8, 2615 .hwcg_bit = 1, 2616 .clkr = { 2617 .enable_reg = 0x52000, 2618 .enable_mask = BIT(12), 2619 .hw.init = &(const struct clk_init_data) { 2620 .name = "gcc_aggre_noc_pcie_4_axi_clk", 2621 .ops = &clk_branch2_ops, 2622 }, 2623 }, 2624 }; 2625 2626 static struct clk_branch gcc_aggre_noc_pcie_south_sf_axi_clk = { 2627 .halt_reg = 0xbf13c, 2628 .halt_check = BRANCH_HALT_SKIP, 2629 .hwcg_reg = 0xbf13c, 2630 .hwcg_bit = 1, 2631 .clkr = { 2632 .enable_reg = 0x52018, 2633 .enable_mask = BIT(13), 2634 .hw.init = &(const struct clk_init_data) { 2635 .name = "gcc_aggre_noc_pcie_south_sf_axi_clk", 2636 .ops = &clk_branch2_ops, 2637 }, 2638 }, 2639 }; 2640 2641 static struct clk_branch gcc_aggre_ufs_card_axi_clk = { 2642 .halt_reg = 0x750cc, 2643 .halt_check = BRANCH_HALT_VOTED, 2644 .hwcg_reg = 0x750cc, 2645 .hwcg_bit = 1, 2646 .clkr = { 2647 .enable_reg = 0x750cc, 2648 .enable_mask = BIT(0), 2649 .hw.init = &(const struct clk_init_data) { 2650 .name = "gcc_aggre_ufs_card_axi_clk", 2651 .parent_hws = (const struct clk_hw*[]){ 2652 &gcc_ufs_card_axi_clk_src.clkr.hw, 2653 }, 2654 .num_parents = 1, 2655 .flags = CLK_SET_RATE_PARENT, 2656 .ops = &clk_branch2_ops, 2657 }, 2658 }, 2659 }; 2660 2661 static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = { 2662 .halt_reg = 0x750cc, 2663 .halt_check = BRANCH_HALT_VOTED, 2664 .hwcg_reg = 0x750cc, 2665 .hwcg_bit = 1, 2666 .clkr = { 2667 .enable_reg = 0x750cc, 2668 .enable_mask = BIT(1), 2669 .hw.init = &(const struct clk_init_data) { 2670 .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk", 2671 .parent_hws = (const struct clk_hw*[]){ 2672 &gcc_ufs_card_axi_clk_src.clkr.hw, 2673 }, 2674 .num_parents = 1, 2675 .flags = CLK_SET_RATE_PARENT, 2676 .ops = &clk_branch2_ops, 2677 }, 2678 }, 2679 }; 2680 2681 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 2682 .halt_reg = 0x770cc, 2683 .halt_check = BRANCH_HALT_VOTED, 2684 .hwcg_reg = 0x770cc, 2685 .hwcg_bit = 1, 2686 .clkr = { 2687 .enable_reg = 0x770cc, 2688 .enable_mask = BIT(0), 2689 .hw.init = &(const struct clk_init_data) { 2690 .name = "gcc_aggre_ufs_phy_axi_clk", 2691 .parent_hws = (const struct clk_hw*[]){ 2692 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2693 }, 2694 .num_parents = 1, 2695 .flags = CLK_SET_RATE_PARENT, 2696 .ops = &clk_branch2_ops, 2697 }, 2698 }, 2699 }; 2700 2701 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { 2702 .halt_reg = 0x770cc, 2703 .halt_check = BRANCH_HALT_VOTED, 2704 .hwcg_reg = 0x770cc, 2705 .hwcg_bit = 1, 2706 .clkr = { 2707 .enable_reg = 0x770cc, 2708 .enable_mask = BIT(1), 2709 .hw.init = &(const struct clk_init_data) { 2710 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", 2711 .parent_hws = (const struct clk_hw*[]){ 2712 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2713 }, 2714 .num_parents = 1, 2715 .flags = CLK_SET_RATE_PARENT, 2716 .ops = &clk_branch2_ops, 2717 }, 2718 }, 2719 }; 2720 2721 static struct clk_branch gcc_aggre_usb3_mp_axi_clk = { 2722 .halt_reg = 0xab084, 2723 .halt_check = BRANCH_HALT_VOTED, 2724 .hwcg_reg = 0xab084, 2725 .hwcg_bit = 1, 2726 .clkr = { 2727 .enable_reg = 0xab084, 2728 .enable_mask = BIT(0), 2729 .hw.init = &(const struct clk_init_data) { 2730 .name = "gcc_aggre_usb3_mp_axi_clk", 2731 .parent_hws = (const struct clk_hw*[]){ 2732 &gcc_usb30_mp_master_clk_src.clkr.hw, 2733 }, 2734 .num_parents = 1, 2735 .flags = CLK_SET_RATE_PARENT, 2736 .ops = &clk_branch2_ops, 2737 }, 2738 }, 2739 }; 2740 2741 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 2742 .halt_reg = 0xf080, 2743 .halt_check = BRANCH_HALT_VOTED, 2744 .hwcg_reg = 0xf080, 2745 .hwcg_bit = 1, 2746 .clkr = { 2747 .enable_reg = 0xf080, 2748 .enable_mask = BIT(0), 2749 .hw.init = &(const struct clk_init_data) { 2750 .name = "gcc_aggre_usb3_prim_axi_clk", 2751 .parent_hws = (const struct clk_hw*[]){ 2752 &gcc_usb30_prim_master_clk_src.clkr.hw, 2753 }, 2754 .num_parents = 1, 2755 .flags = CLK_SET_RATE_PARENT, 2756 .ops = &clk_branch2_ops, 2757 }, 2758 }, 2759 }; 2760 2761 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { 2762 .halt_reg = 0x10080, 2763 .halt_check = BRANCH_HALT_VOTED, 2764 .hwcg_reg = 0x10080, 2765 .hwcg_bit = 1, 2766 .clkr = { 2767 .enable_reg = 0x10080, 2768 .enable_mask = BIT(0), 2769 .hw.init = &(const struct clk_init_data) { 2770 .name = "gcc_aggre_usb3_sec_axi_clk", 2771 .parent_hws = (const struct clk_hw*[]){ 2772 &gcc_usb30_sec_master_clk_src.clkr.hw, 2773 }, 2774 .num_parents = 1, 2775 .flags = CLK_SET_RATE_PARENT, 2776 .ops = &clk_branch2_ops, 2777 }, 2778 }, 2779 }; 2780 2781 static struct clk_branch gcc_aggre_usb4_1_axi_clk = { 2782 .halt_reg = 0xb80e4, 2783 .halt_check = BRANCH_HALT_VOTED, 2784 .hwcg_reg = 0xb80e4, 2785 .hwcg_bit = 1, 2786 .clkr = { 2787 .enable_reg = 0xb80e4, 2788 .enable_mask = BIT(0), 2789 .hw.init = &(const struct clk_init_data) { 2790 .name = "gcc_aggre_usb4_1_axi_clk", 2791 .parent_hws = (const struct clk_hw*[]){ 2792 &gcc_usb4_1_master_clk_src.clkr.hw, 2793 }, 2794 .num_parents = 1, 2795 .flags = CLK_SET_RATE_PARENT, 2796 .ops = &clk_branch2_ops, 2797 }, 2798 }, 2799 }; 2800 2801 static struct clk_branch gcc_aggre_usb4_axi_clk = { 2802 .halt_reg = 0x2a0e4, 2803 .halt_check = BRANCH_HALT_VOTED, 2804 .hwcg_reg = 0x2a0e4, 2805 .hwcg_bit = 1, 2806 .clkr = { 2807 .enable_reg = 0x2a0e4, 2808 .enable_mask = BIT(0), 2809 .hw.init = &(const struct clk_init_data) { 2810 .name = "gcc_aggre_usb4_axi_clk", 2811 .parent_hws = (const struct clk_hw*[]){ 2812 &gcc_usb4_master_clk_src.clkr.hw, 2813 }, 2814 .num_parents = 1, 2815 .flags = CLK_SET_RATE_PARENT, 2816 .ops = &clk_branch2_ops, 2817 }, 2818 }, 2819 }; 2820 2821 static struct clk_branch gcc_aggre_usb_noc_axi_clk = { 2822 .halt_reg = 0x5d024, 2823 .halt_check = BRANCH_HALT_VOTED, 2824 .hwcg_reg = 0x5d024, 2825 .hwcg_bit = 1, 2826 .clkr = { 2827 .enable_reg = 0x5d024, 2828 .enable_mask = BIT(0), 2829 .hw.init = &(const struct clk_init_data) { 2830 .name = "gcc_aggre_usb_noc_axi_clk", 2831 .ops = &clk_branch2_ops, 2832 }, 2833 }, 2834 }; 2835 2836 static struct clk_branch gcc_aggre_usb_noc_north_axi_clk = { 2837 .halt_reg = 0x5d020, 2838 .halt_check = BRANCH_HALT_VOTED, 2839 .hwcg_reg = 0x5d020, 2840 .hwcg_bit = 1, 2841 .clkr = { 2842 .enable_reg = 0x5d020, 2843 .enable_mask = BIT(0), 2844 .hw.init = &(const struct clk_init_data) { 2845 .name = "gcc_aggre_usb_noc_north_axi_clk", 2846 .ops = &clk_branch2_ops, 2847 }, 2848 }, 2849 }; 2850 2851 static struct clk_branch gcc_aggre_usb_noc_south_axi_clk = { 2852 .halt_reg = 0x5d01c, 2853 .halt_check = BRANCH_HALT_VOTED, 2854 .hwcg_reg = 0x5d01c, 2855 .hwcg_bit = 1, 2856 .clkr = { 2857 .enable_reg = 0x5d01c, 2858 .enable_mask = BIT(0), 2859 .hw.init = &(const struct clk_init_data) { 2860 .name = "gcc_aggre_usb_noc_south_axi_clk", 2861 .ops = &clk_branch2_ops, 2862 }, 2863 }, 2864 }; 2865 2866 static struct clk_branch gcc_ahb2phy0_clk = { 2867 .halt_reg = 0x6a004, 2868 .halt_check = BRANCH_HALT_VOTED, 2869 .hwcg_reg = 0x6a004, 2870 .hwcg_bit = 1, 2871 .clkr = { 2872 .enable_reg = 0x6a004, 2873 .enable_mask = BIT(0), 2874 .hw.init = &(const struct clk_init_data) { 2875 .name = "gcc_ahb2phy0_clk", 2876 .ops = &clk_branch2_ops, 2877 }, 2878 }, 2879 }; 2880 2881 static struct clk_branch gcc_ahb2phy2_clk = { 2882 .halt_reg = 0x6a008, 2883 .halt_check = BRANCH_HALT_VOTED, 2884 .hwcg_reg = 0x6a008, 2885 .hwcg_bit = 1, 2886 .clkr = { 2887 .enable_reg = 0x6a008, 2888 .enable_mask = BIT(0), 2889 .hw.init = &(const struct clk_init_data) { 2890 .name = "gcc_ahb2phy2_clk", 2891 .ops = &clk_branch2_ops, 2892 }, 2893 }, 2894 }; 2895 2896 static struct clk_branch gcc_boot_rom_ahb_clk = { 2897 .halt_reg = 0x38004, 2898 .halt_check = BRANCH_HALT_VOTED, 2899 .hwcg_reg = 0x38004, 2900 .hwcg_bit = 1, 2901 .clkr = { 2902 .enable_reg = 0x52000, 2903 .enable_mask = BIT(10), 2904 .hw.init = &(const struct clk_init_data) { 2905 .name = "gcc_boot_rom_ahb_clk", 2906 .ops = &clk_branch2_ops, 2907 }, 2908 }, 2909 }; 2910 2911 static struct clk_branch gcc_camera_hf_axi_clk = { 2912 .halt_reg = 0x26010, 2913 .halt_check = BRANCH_HALT_SKIP, 2914 .hwcg_reg = 0x26010, 2915 .hwcg_bit = 1, 2916 .clkr = { 2917 .enable_reg = 0x26010, 2918 .enable_mask = BIT(0), 2919 .hw.init = &(const struct clk_init_data) { 2920 .name = "gcc_camera_hf_axi_clk", 2921 .ops = &clk_branch2_ops, 2922 }, 2923 }, 2924 }; 2925 2926 static struct clk_branch gcc_camera_sf_axi_clk = { 2927 .halt_reg = 0x26014, 2928 .halt_check = BRANCH_HALT_SKIP, 2929 .hwcg_reg = 0x26014, 2930 .hwcg_bit = 1, 2931 .clkr = { 2932 .enable_reg = 0x26014, 2933 .enable_mask = BIT(0), 2934 .hw.init = &(const struct clk_init_data) { 2935 .name = "gcc_camera_sf_axi_clk", 2936 .ops = &clk_branch2_ops, 2937 }, 2938 }, 2939 }; 2940 2941 static struct clk_branch gcc_camera_throttle_nrt_axi_clk = { 2942 .halt_reg = 0x2601c, 2943 .halt_check = BRANCH_HALT_SKIP, 2944 .hwcg_reg = 0x2601c, 2945 .hwcg_bit = 1, 2946 .clkr = { 2947 .enable_reg = 0x2601c, 2948 .enable_mask = BIT(0), 2949 .hw.init = &(const struct clk_init_data) { 2950 .name = "gcc_camera_throttle_nrt_axi_clk", 2951 .ops = &clk_branch2_ops, 2952 }, 2953 }, 2954 }; 2955 2956 static struct clk_branch gcc_camera_throttle_rt_axi_clk = { 2957 .halt_reg = 0x26018, 2958 .halt_check = BRANCH_HALT_SKIP, 2959 .hwcg_reg = 0x26018, 2960 .hwcg_bit = 1, 2961 .clkr = { 2962 .enable_reg = 0x26018, 2963 .enable_mask = BIT(0), 2964 .hw.init = &(const struct clk_init_data) { 2965 .name = "gcc_camera_throttle_rt_axi_clk", 2966 .ops = &clk_branch2_ops, 2967 }, 2968 }, 2969 }; 2970 2971 static struct clk_branch gcc_camera_throttle_xo_clk = { 2972 .halt_reg = 0x26024, 2973 .halt_check = BRANCH_HALT, 2974 .clkr = { 2975 .enable_reg = 0x26024, 2976 .enable_mask = BIT(0), 2977 .hw.init = &(const struct clk_init_data) { 2978 .name = "gcc_camera_throttle_xo_clk", 2979 .ops = &clk_branch2_ops, 2980 }, 2981 }, 2982 }; 2983 2984 static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = { 2985 .halt_reg = 0xab088, 2986 .halt_check = BRANCH_HALT_VOTED, 2987 .hwcg_reg = 0xab088, 2988 .hwcg_bit = 1, 2989 .clkr = { 2990 .enable_reg = 0xab088, 2991 .enable_mask = BIT(0), 2992 .hw.init = &(const struct clk_init_data) { 2993 .name = "gcc_cfg_noc_usb3_mp_axi_clk", 2994 .parent_hws = (const struct clk_hw*[]){ 2995 &gcc_usb30_mp_master_clk_src.clkr.hw, 2996 }, 2997 .num_parents = 1, 2998 .flags = CLK_SET_RATE_PARENT, 2999 .ops = &clk_branch2_ops, 3000 }, 3001 }, 3002 }; 3003 3004 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 3005 .halt_reg = 0xf084, 3006 .halt_check = BRANCH_HALT_VOTED, 3007 .hwcg_reg = 0xf084, 3008 .hwcg_bit = 1, 3009 .clkr = { 3010 .enable_reg = 0xf084, 3011 .enable_mask = BIT(0), 3012 .hw.init = &(const struct clk_init_data) { 3013 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 3014 .parent_hws = (const struct clk_hw*[]){ 3015 &gcc_usb30_prim_master_clk_src.clkr.hw, 3016 }, 3017 .num_parents = 1, 3018 .flags = CLK_SET_RATE_PARENT, 3019 .ops = &clk_branch2_ops, 3020 }, 3021 }, 3022 }; 3023 3024 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { 3025 .halt_reg = 0x10084, 3026 .halt_check = BRANCH_HALT_VOTED, 3027 .hwcg_reg = 0x10084, 3028 .hwcg_bit = 1, 3029 .clkr = { 3030 .enable_reg = 0x10084, 3031 .enable_mask = BIT(0), 3032 .hw.init = &(const struct clk_init_data) { 3033 .name = "gcc_cfg_noc_usb3_sec_axi_clk", 3034 .parent_hws = (const struct clk_hw*[]){ 3035 &gcc_usb30_sec_master_clk_src.clkr.hw, 3036 }, 3037 .num_parents = 1, 3038 .flags = CLK_SET_RATE_PARENT, 3039 .ops = &clk_branch2_ops, 3040 }, 3041 }, 3042 }; 3043 3044 static struct clk_branch gcc_cnoc_pcie0_tunnel_clk = { 3045 .halt_reg = 0xa4074, 3046 .halt_check = BRANCH_HALT_VOTED, 3047 .clkr = { 3048 .enable_reg = 0x52020, 3049 .enable_mask = BIT(8), 3050 .hw.init = &(const struct clk_init_data) { 3051 .name = "gcc_cnoc_pcie0_tunnel_clk", 3052 .ops = &clk_branch2_ops, 3053 }, 3054 }, 3055 }; 3056 3057 static struct clk_branch gcc_cnoc_pcie1_tunnel_clk = { 3058 .halt_reg = 0x8d074, 3059 .halt_check = BRANCH_HALT_VOTED, 3060 .clkr = { 3061 .enable_reg = 0x52020, 3062 .enable_mask = BIT(9), 3063 .hw.init = &(const struct clk_init_data) { 3064 .name = "gcc_cnoc_pcie1_tunnel_clk", 3065 .ops = &clk_branch2_ops, 3066 }, 3067 }, 3068 }; 3069 3070 static struct clk_branch gcc_cnoc_pcie4_qx_clk = { 3071 .halt_reg = 0x6b084, 3072 .halt_check = BRANCH_HALT_VOTED, 3073 .hwcg_reg = 0x6b084, 3074 .hwcg_bit = 1, 3075 .clkr = { 3076 .enable_reg = 0x52020, 3077 .enable_mask = BIT(10), 3078 .hw.init = &(const struct clk_init_data) { 3079 .name = "gcc_cnoc_pcie4_qx_clk", 3080 .ops = &clk_branch2_ops, 3081 }, 3082 }, 3083 }; 3084 3085 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 3086 .halt_reg = 0x7115c, 3087 .halt_check = BRANCH_HALT_SKIP, 3088 .hwcg_reg = 0x7115c, 3089 .hwcg_bit = 1, 3090 .clkr = { 3091 .enable_reg = 0x7115c, 3092 .enable_mask = BIT(0), 3093 .hw.init = &(const struct clk_init_data) { 3094 .name = "gcc_ddrss_gpu_axi_clk", 3095 .ops = &clk_branch2_aon_ops, 3096 }, 3097 }, 3098 }; 3099 3100 static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = { 3101 .halt_reg = 0xa602c, 3102 .halt_check = BRANCH_HALT_SKIP, 3103 .hwcg_reg = 0xa602c, 3104 .hwcg_bit = 1, 3105 .clkr = { 3106 .enable_reg = 0x52000, 3107 .enable_mask = BIT(19), 3108 .hw.init = &(const struct clk_init_data) { 3109 .name = "gcc_ddrss_pcie_sf_tbu_clk", 3110 .ops = &clk_branch2_ops, 3111 }, 3112 }, 3113 }; 3114 3115 static struct clk_branch gcc_disp1_hf_axi_clk = { 3116 .halt_reg = 0xbb010, 3117 .halt_check = BRANCH_HALT_SKIP, 3118 .hwcg_reg = 0xbb010, 3119 .hwcg_bit = 1, 3120 .clkr = { 3121 .enable_reg = 0xbb010, 3122 .enable_mask = BIT(0), 3123 .hw.init = &(const struct clk_init_data) { 3124 .name = "gcc_disp1_hf_axi_clk", 3125 .ops = &clk_branch2_ops, 3126 }, 3127 }, 3128 }; 3129 3130 static struct clk_branch gcc_disp1_sf_axi_clk = { 3131 .halt_reg = 0xbb018, 3132 .halt_check = BRANCH_HALT_SKIP, 3133 .hwcg_reg = 0xbb018, 3134 .hwcg_bit = 1, 3135 .clkr = { 3136 .enable_reg = 0xbb018, 3137 .enable_mask = BIT(0), 3138 .hw.init = &(const struct clk_init_data) { 3139 .name = "gcc_disp1_sf_axi_clk", 3140 .ops = &clk_branch2_ops, 3141 }, 3142 }, 3143 }; 3144 3145 static struct clk_branch gcc_disp1_throttle_nrt_axi_clk = { 3146 .halt_reg = 0xbb024, 3147 .halt_check = BRANCH_HALT_SKIP, 3148 .hwcg_reg = 0xbb024, 3149 .hwcg_bit = 1, 3150 .clkr = { 3151 .enable_reg = 0xbb024, 3152 .enable_mask = BIT(0), 3153 .hw.init = &(const struct clk_init_data) { 3154 .name = "gcc_disp1_throttle_nrt_axi_clk", 3155 .ops = &clk_branch2_ops, 3156 }, 3157 }, 3158 }; 3159 3160 static struct clk_branch gcc_disp1_throttle_rt_axi_clk = { 3161 .halt_reg = 0xbb020, 3162 .halt_check = BRANCH_HALT_SKIP, 3163 .hwcg_reg = 0xbb020, 3164 .hwcg_bit = 1, 3165 .clkr = { 3166 .enable_reg = 0xbb020, 3167 .enable_mask = BIT(0), 3168 .hw.init = &(const struct clk_init_data) { 3169 .name = "gcc_disp1_throttle_rt_axi_clk", 3170 .ops = &clk_branch2_ops, 3171 }, 3172 }, 3173 }; 3174 3175 static struct clk_branch gcc_disp_hf_axi_clk = { 3176 .halt_reg = 0x27010, 3177 .halt_check = BRANCH_HALT_SKIP, 3178 .hwcg_reg = 0x27010, 3179 .hwcg_bit = 1, 3180 .clkr = { 3181 .enable_reg = 0x27010, 3182 .enable_mask = BIT(0), 3183 .hw.init = &(const struct clk_init_data) { 3184 .name = "gcc_disp_hf_axi_clk", 3185 .ops = &clk_branch2_ops, 3186 }, 3187 }, 3188 }; 3189 3190 static struct clk_branch gcc_disp_sf_axi_clk = { 3191 .halt_reg = 0x27018, 3192 .halt_check = BRANCH_HALT_SKIP, 3193 .hwcg_reg = 0x27018, 3194 .hwcg_bit = 1, 3195 .clkr = { 3196 .enable_reg = 0x27018, 3197 .enable_mask = BIT(0), 3198 .hw.init = &(const struct clk_init_data) { 3199 .name = "gcc_disp_sf_axi_clk", 3200 .ops = &clk_branch2_ops, 3201 }, 3202 }, 3203 }; 3204 3205 static struct clk_branch gcc_disp_throttle_nrt_axi_clk = { 3206 .halt_reg = 0x27024, 3207 .halt_check = BRANCH_HALT_SKIP, 3208 .hwcg_reg = 0x27024, 3209 .hwcg_bit = 1, 3210 .clkr = { 3211 .enable_reg = 0x27024, 3212 .enable_mask = BIT(0), 3213 .hw.init = &(const struct clk_init_data) { 3214 .name = "gcc_disp_throttle_nrt_axi_clk", 3215 .ops = &clk_branch2_ops, 3216 }, 3217 }, 3218 }; 3219 3220 static struct clk_branch gcc_disp_throttle_rt_axi_clk = { 3221 .halt_reg = 0x27020, 3222 .halt_check = BRANCH_HALT_SKIP, 3223 .hwcg_reg = 0x27020, 3224 .hwcg_bit = 1, 3225 .clkr = { 3226 .enable_reg = 0x27020, 3227 .enable_mask = BIT(0), 3228 .hw.init = &(const struct clk_init_data) { 3229 .name = "gcc_disp_throttle_rt_axi_clk", 3230 .ops = &clk_branch2_ops, 3231 }, 3232 }, 3233 }; 3234 3235 static struct clk_branch gcc_emac0_axi_clk = { 3236 .halt_reg = 0xaa010, 3237 .halt_check = BRANCH_HALT_VOTED, 3238 .hwcg_reg = 0xaa010, 3239 .hwcg_bit = 1, 3240 .clkr = { 3241 .enable_reg = 0xaa010, 3242 .enable_mask = BIT(0), 3243 .hw.init = &(const struct clk_init_data) { 3244 .name = "gcc_emac0_axi_clk", 3245 .ops = &clk_branch2_ops, 3246 }, 3247 }, 3248 }; 3249 3250 static struct clk_branch gcc_emac0_ptp_clk = { 3251 .halt_reg = 0xaa01c, 3252 .halt_check = BRANCH_HALT, 3253 .clkr = { 3254 .enable_reg = 0xaa01c, 3255 .enable_mask = BIT(0), 3256 .hw.init = &(const struct clk_init_data) { 3257 .name = "gcc_emac0_ptp_clk", 3258 .parent_hws = (const struct clk_hw*[]){ 3259 &gcc_emac0_ptp_clk_src.clkr.hw, 3260 }, 3261 .num_parents = 1, 3262 .flags = CLK_SET_RATE_PARENT, 3263 .ops = &clk_branch2_ops, 3264 }, 3265 }, 3266 }; 3267 3268 static struct clk_branch gcc_emac0_rgmii_clk = { 3269 .halt_reg = 0xaa038, 3270 .halt_check = BRANCH_HALT, 3271 .clkr = { 3272 .enable_reg = 0xaa038, 3273 .enable_mask = BIT(0), 3274 .hw.init = &(const struct clk_init_data) { 3275 .name = "gcc_emac0_rgmii_clk", 3276 .parent_hws = (const struct clk_hw*[]){ 3277 &gcc_emac0_rgmii_clk_src.clkr.hw, 3278 }, 3279 .num_parents = 1, 3280 .flags = CLK_SET_RATE_PARENT, 3281 .ops = &clk_branch2_ops, 3282 }, 3283 }, 3284 }; 3285 3286 static struct clk_branch gcc_emac0_slv_ahb_clk = { 3287 .halt_reg = 0xaa018, 3288 .halt_check = BRANCH_HALT_VOTED, 3289 .hwcg_reg = 0xaa018, 3290 .hwcg_bit = 1, 3291 .clkr = { 3292 .enable_reg = 0xaa018, 3293 .enable_mask = BIT(0), 3294 .hw.init = &(const struct clk_init_data) { 3295 .name = "gcc_emac0_slv_ahb_clk", 3296 .ops = &clk_branch2_ops, 3297 }, 3298 }, 3299 }; 3300 3301 static struct clk_branch gcc_emac1_axi_clk = { 3302 .halt_reg = 0xba010, 3303 .halt_check = BRANCH_HALT_VOTED, 3304 .hwcg_reg = 0xba010, 3305 .hwcg_bit = 1, 3306 .clkr = { 3307 .enable_reg = 0xba010, 3308 .enable_mask = BIT(0), 3309 .hw.init = &(const struct clk_init_data) { 3310 .name = "gcc_emac1_axi_clk", 3311 .ops = &clk_branch2_ops, 3312 }, 3313 }, 3314 }; 3315 3316 static struct clk_branch gcc_emac1_ptp_clk = { 3317 .halt_reg = 0xba01c, 3318 .halt_check = BRANCH_HALT, 3319 .clkr = { 3320 .enable_reg = 0xba01c, 3321 .enable_mask = BIT(0), 3322 .hw.init = &(const struct clk_init_data) { 3323 .name = "gcc_emac1_ptp_clk", 3324 .parent_hws = (const struct clk_hw*[]){ 3325 &gcc_emac1_ptp_clk_src.clkr.hw, 3326 }, 3327 .num_parents = 1, 3328 .flags = CLK_SET_RATE_PARENT, 3329 .ops = &clk_branch2_ops, 3330 }, 3331 }, 3332 }; 3333 3334 static struct clk_branch gcc_emac1_rgmii_clk = { 3335 .halt_reg = 0xba038, 3336 .halt_check = BRANCH_HALT, 3337 .clkr = { 3338 .enable_reg = 0xba038, 3339 .enable_mask = BIT(0), 3340 .hw.init = &(const struct clk_init_data) { 3341 .name = "gcc_emac1_rgmii_clk", 3342 .parent_hws = (const struct clk_hw*[]){ 3343 &gcc_emac1_rgmii_clk_src.clkr.hw, 3344 }, 3345 .num_parents = 1, 3346 .flags = CLK_SET_RATE_PARENT, 3347 .ops = &clk_branch2_ops, 3348 }, 3349 }, 3350 }; 3351 3352 static struct clk_branch gcc_emac1_slv_ahb_clk = { 3353 .halt_reg = 0xba018, 3354 .halt_check = BRANCH_HALT_VOTED, 3355 .hwcg_reg = 0xba018, 3356 .hwcg_bit = 1, 3357 .clkr = { 3358 .enable_reg = 0xba018, 3359 .enable_mask = BIT(0), 3360 .hw.init = &(const struct clk_init_data) { 3361 .name = "gcc_emac1_slv_ahb_clk", 3362 .ops = &clk_branch2_ops, 3363 }, 3364 }, 3365 }; 3366 3367 static struct clk_branch gcc_gp1_clk = { 3368 .halt_reg = 0x64000, 3369 .halt_check = BRANCH_HALT, 3370 .clkr = { 3371 .enable_reg = 0x64000, 3372 .enable_mask = BIT(0), 3373 .hw.init = &(const struct clk_init_data) { 3374 .name = "gcc_gp1_clk", 3375 .parent_hws = (const struct clk_hw*[]){ 3376 &gcc_gp1_clk_src.clkr.hw, 3377 }, 3378 .num_parents = 1, 3379 .flags = CLK_SET_RATE_PARENT, 3380 .ops = &clk_branch2_ops, 3381 }, 3382 }, 3383 }; 3384 3385 static struct clk_branch gcc_gp2_clk = { 3386 .halt_reg = 0x65000, 3387 .halt_check = BRANCH_HALT, 3388 .clkr = { 3389 .enable_reg = 0x65000, 3390 .enable_mask = BIT(0), 3391 .hw.init = &(const struct clk_init_data) { 3392 .name = "gcc_gp2_clk", 3393 .parent_hws = (const struct clk_hw*[]){ 3394 &gcc_gp2_clk_src.clkr.hw, 3395 }, 3396 .num_parents = 1, 3397 .flags = CLK_SET_RATE_PARENT, 3398 .ops = &clk_branch2_ops, 3399 }, 3400 }, 3401 }; 3402 3403 static struct clk_branch gcc_gp3_clk = { 3404 .halt_reg = 0x66000, 3405 .halt_check = BRANCH_HALT, 3406 .clkr = { 3407 .enable_reg = 0x66000, 3408 .enable_mask = BIT(0), 3409 .hw.init = &(const struct clk_init_data) { 3410 .name = "gcc_gp3_clk", 3411 .parent_hws = (const struct clk_hw*[]){ 3412 &gcc_gp3_clk_src.clkr.hw, 3413 }, 3414 .num_parents = 1, 3415 .flags = CLK_SET_RATE_PARENT, 3416 .ops = &clk_branch2_ops, 3417 }, 3418 }, 3419 }; 3420 3421 static struct clk_branch gcc_gp4_clk = { 3422 .halt_reg = 0xc2000, 3423 .halt_check = BRANCH_HALT, 3424 .clkr = { 3425 .enable_reg = 0xc2000, 3426 .enable_mask = BIT(0), 3427 .hw.init = &(const struct clk_init_data) { 3428 .name = "gcc_gp4_clk", 3429 .parent_hws = (const struct clk_hw*[]){ 3430 &gcc_gp4_clk_src.clkr.hw, 3431 }, 3432 .num_parents = 1, 3433 .flags = CLK_SET_RATE_PARENT, 3434 .ops = &clk_branch2_ops, 3435 }, 3436 }, 3437 }; 3438 3439 static struct clk_branch gcc_gp5_clk = { 3440 .halt_reg = 0xc3000, 3441 .halt_check = BRANCH_HALT, 3442 .clkr = { 3443 .enable_reg = 0xc3000, 3444 .enable_mask = BIT(0), 3445 .hw.init = &(const struct clk_init_data) { 3446 .name = "gcc_gp5_clk", 3447 .parent_hws = (const struct clk_hw*[]){ 3448 &gcc_gp5_clk_src.clkr.hw, 3449 }, 3450 .num_parents = 1, 3451 .flags = CLK_SET_RATE_PARENT, 3452 .ops = &clk_branch2_ops, 3453 }, 3454 }, 3455 }; 3456 3457 static struct clk_branch gcc_gpu_gpll0_clk_src = { 3458 .halt_check = BRANCH_HALT_DELAY, 3459 .clkr = { 3460 .enable_reg = 0x52000, 3461 .enable_mask = BIT(15), 3462 .hw.init = &(const struct clk_init_data) { 3463 .name = "gcc_gpu_gpll0_clk_src", 3464 .parent_hws = (const struct clk_hw*[]){ 3465 &gcc_gpll0.clkr.hw, 3466 }, 3467 .num_parents = 1, 3468 .flags = CLK_SET_RATE_PARENT, 3469 .ops = &clk_branch2_ops, 3470 }, 3471 }, 3472 }; 3473 3474 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 3475 .halt_check = BRANCH_HALT_DELAY, 3476 .clkr = { 3477 .enable_reg = 0x52000, 3478 .enable_mask = BIT(16), 3479 .hw.init = &(const struct clk_init_data) { 3480 .name = "gcc_gpu_gpll0_div_clk_src", 3481 .parent_hws = (const struct clk_hw*[]){ 3482 &gcc_gpll0_out_even.clkr.hw, 3483 }, 3484 .num_parents = 1, 3485 .flags = CLK_SET_RATE_PARENT, 3486 .ops = &clk_branch2_ops, 3487 }, 3488 }, 3489 }; 3490 3491 static struct clk_branch gcc_gpu_iref_en = { 3492 .halt_reg = 0x8c014, 3493 .halt_check = BRANCH_HALT, 3494 .clkr = { 3495 .enable_reg = 0x8c014, 3496 .enable_mask = BIT(0), 3497 .hw.init = &(const struct clk_init_data) { 3498 .name = "gcc_gpu_iref_en", 3499 .ops = &clk_branch2_ops, 3500 }, 3501 }, 3502 }; 3503 3504 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 3505 .halt_reg = 0x71010, 3506 .halt_check = BRANCH_HALT_VOTED, 3507 .hwcg_reg = 0x71010, 3508 .hwcg_bit = 1, 3509 .clkr = { 3510 .enable_reg = 0x71010, 3511 .enable_mask = BIT(0), 3512 .hw.init = &(const struct clk_init_data) { 3513 .name = "gcc_gpu_memnoc_gfx_clk", 3514 .ops = &clk_branch2_aon_ops, 3515 }, 3516 }, 3517 }; 3518 3519 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 3520 .halt_reg = 0x71020, 3521 .halt_check = BRANCH_HALT, 3522 .clkr = { 3523 .enable_reg = 0x71020, 3524 .enable_mask = BIT(0), 3525 .hw.init = &(const struct clk_init_data) { 3526 .name = "gcc_gpu_snoc_dvm_gfx_clk", 3527 .ops = &clk_branch2_aon_ops, 3528 }, 3529 }, 3530 }; 3531 3532 static struct clk_branch gcc_gpu_tcu_throttle_ahb_clk = { 3533 .halt_reg = 0x71008, 3534 .halt_check = BRANCH_HALT_VOTED, 3535 .hwcg_reg = 0x71008, 3536 .hwcg_bit = 1, 3537 .clkr = { 3538 .enable_reg = 0x71008, 3539 .enable_mask = BIT(0), 3540 .hw.init = &(const struct clk_init_data) { 3541 .name = "gcc_gpu_tcu_throttle_ahb_clk", 3542 .ops = &clk_branch2_ops, 3543 }, 3544 }, 3545 }; 3546 3547 static struct clk_branch gcc_gpu_tcu_throttle_clk = { 3548 .halt_reg = 0x71018, 3549 .halt_check = BRANCH_HALT_VOTED, 3550 .hwcg_reg = 0x71018, 3551 .hwcg_bit = 1, 3552 .clkr = { 3553 .enable_reg = 0x71018, 3554 .enable_mask = BIT(0), 3555 .hw.init = &(const struct clk_init_data) { 3556 .name = "gcc_gpu_tcu_throttle_clk", 3557 .ops = &clk_branch2_ops, 3558 }, 3559 }, 3560 }; 3561 3562 static struct clk_branch gcc_pcie0_phy_rchng_clk = { 3563 .halt_reg = 0xa4038, 3564 .halt_check = BRANCH_HALT_VOTED, 3565 .clkr = { 3566 .enable_reg = 0x52018, 3567 .enable_mask = BIT(11), 3568 .hw.init = &(const struct clk_init_data) { 3569 .name = "gcc_pcie0_phy_rchng_clk", 3570 .parent_hws = (const struct clk_hw*[]){ 3571 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 3572 }, 3573 .num_parents = 1, 3574 .flags = CLK_SET_RATE_PARENT, 3575 .ops = &clk_branch2_ops, 3576 }, 3577 }, 3578 }; 3579 3580 static struct clk_branch gcc_pcie1_phy_rchng_clk = { 3581 .halt_reg = 0x8d038, 3582 .halt_check = BRANCH_HALT_VOTED, 3583 .clkr = { 3584 .enable_reg = 0x52000, 3585 .enable_mask = BIT(23), 3586 .hw.init = &(const struct clk_init_data) { 3587 .name = "gcc_pcie1_phy_rchng_clk", 3588 .parent_hws = (const struct clk_hw*[]){ 3589 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 3590 }, 3591 .num_parents = 1, 3592 .flags = CLK_SET_RATE_PARENT, 3593 .ops = &clk_branch2_ops, 3594 }, 3595 }, 3596 }; 3597 3598 static struct clk_branch gcc_pcie2a_phy_rchng_clk = { 3599 .halt_reg = 0x9d040, 3600 .halt_check = BRANCH_HALT_VOTED, 3601 .clkr = { 3602 .enable_reg = 0x52010, 3603 .enable_mask = BIT(15), 3604 .hw.init = &(const struct clk_init_data) { 3605 .name = "gcc_pcie2a_phy_rchng_clk", 3606 .parent_hws = (const struct clk_hw*[]){ 3607 &gcc_pcie_2a_phy_rchng_clk_src.clkr.hw, 3608 }, 3609 .num_parents = 1, 3610 .flags = CLK_SET_RATE_PARENT, 3611 .ops = &clk_branch2_ops, 3612 }, 3613 }, 3614 }; 3615 3616 static struct clk_branch gcc_pcie2b_phy_rchng_clk = { 3617 .halt_reg = 0x9e040, 3618 .halt_check = BRANCH_HALT_VOTED, 3619 .clkr = { 3620 .enable_reg = 0x52010, 3621 .enable_mask = BIT(22), 3622 .hw.init = &(const struct clk_init_data) { 3623 .name = "gcc_pcie2b_phy_rchng_clk", 3624 .parent_hws = (const struct clk_hw*[]){ 3625 &gcc_pcie_2b_phy_rchng_clk_src.clkr.hw, 3626 }, 3627 .num_parents = 1, 3628 .flags = CLK_SET_RATE_PARENT, 3629 .ops = &clk_branch2_ops, 3630 }, 3631 }, 3632 }; 3633 3634 static struct clk_branch gcc_pcie3a_phy_rchng_clk = { 3635 .halt_reg = 0xa0040, 3636 .halt_check = BRANCH_HALT_VOTED, 3637 .clkr = { 3638 .enable_reg = 0x52010, 3639 .enable_mask = BIT(29), 3640 .hw.init = &(const struct clk_init_data) { 3641 .name = "gcc_pcie3a_phy_rchng_clk", 3642 .parent_hws = (const struct clk_hw*[]){ 3643 &gcc_pcie_3a_phy_rchng_clk_src.clkr.hw, 3644 }, 3645 .num_parents = 1, 3646 .flags = CLK_SET_RATE_PARENT, 3647 .ops = &clk_branch2_ops, 3648 }, 3649 }, 3650 }; 3651 3652 static struct clk_branch gcc_pcie3b_phy_rchng_clk = { 3653 .halt_reg = 0xa2040, 3654 .halt_check = BRANCH_HALT_VOTED, 3655 .clkr = { 3656 .enable_reg = 0x52018, 3657 .enable_mask = BIT(4), 3658 .hw.init = &(const struct clk_init_data) { 3659 .name = "gcc_pcie3b_phy_rchng_clk", 3660 .parent_hws = (const struct clk_hw*[]){ 3661 &gcc_pcie_3b_phy_rchng_clk_src.clkr.hw, 3662 }, 3663 .num_parents = 1, 3664 .flags = CLK_SET_RATE_PARENT, 3665 .ops = &clk_branch2_ops, 3666 }, 3667 }, 3668 }; 3669 3670 static struct clk_branch gcc_pcie4_phy_rchng_clk = { 3671 .halt_reg = 0x6b040, 3672 .halt_check = BRANCH_HALT_VOTED, 3673 .clkr = { 3674 .enable_reg = 0x52000, 3675 .enable_mask = BIT(22), 3676 .hw.init = &(const struct clk_init_data) { 3677 .name = "gcc_pcie4_phy_rchng_clk", 3678 .parent_hws = (const struct clk_hw*[]){ 3679 &gcc_pcie_4_phy_rchng_clk_src.clkr.hw, 3680 }, 3681 .num_parents = 1, 3682 .flags = CLK_SET_RATE_PARENT, 3683 .ops = &clk_branch2_ops, 3684 }, 3685 }, 3686 }; 3687 3688 static struct clk_branch gcc_pcie_0_aux_clk = { 3689 .halt_reg = 0xa4028, 3690 .halt_check = BRANCH_HALT_VOTED, 3691 .clkr = { 3692 .enable_reg = 0x52018, 3693 .enable_mask = BIT(9), 3694 .hw.init = &(const struct clk_init_data) { 3695 .name = "gcc_pcie_0_aux_clk", 3696 .parent_hws = (const struct clk_hw*[]){ 3697 &gcc_pcie_0_aux_clk_src.clkr.hw, 3698 }, 3699 .num_parents = 1, 3700 .flags = CLK_SET_RATE_PARENT, 3701 .ops = &clk_branch2_ops, 3702 }, 3703 }, 3704 }; 3705 3706 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 3707 .halt_reg = 0xa4024, 3708 .halt_check = BRANCH_HALT_VOTED, 3709 .hwcg_reg = 0xa4024, 3710 .hwcg_bit = 1, 3711 .clkr = { 3712 .enable_reg = 0x52018, 3713 .enable_mask = BIT(8), 3714 .hw.init = &(const struct clk_init_data) { 3715 .name = "gcc_pcie_0_cfg_ahb_clk", 3716 .ops = &clk_branch2_ops, 3717 }, 3718 }, 3719 }; 3720 3721 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 3722 .halt_reg = 0xa401c, 3723 .halt_check = BRANCH_HALT_SKIP, 3724 .hwcg_reg = 0xa401c, 3725 .hwcg_bit = 1, 3726 .clkr = { 3727 .enable_reg = 0x52018, 3728 .enable_mask = BIT(7), 3729 .hw.init = &(const struct clk_init_data) { 3730 .name = "gcc_pcie_0_mstr_axi_clk", 3731 .ops = &clk_branch2_ops, 3732 }, 3733 }, 3734 }; 3735 3736 static struct clk_branch gcc_pcie_0_pipe_clk = { 3737 .halt_reg = 0xa4030, 3738 .halt_check = BRANCH_HALT_SKIP, 3739 .clkr = { 3740 .enable_reg = 0x52018, 3741 .enable_mask = BIT(10), 3742 .hw.init = &(const struct clk_init_data) { 3743 .name = "gcc_pcie_0_pipe_clk", 3744 .parent_hws = (const struct clk_hw*[]){ 3745 &gcc_usb4_phy_pcie_pipe_mux_clk_src.clkr.hw, 3746 }, 3747 .num_parents = 1, 3748 .flags = CLK_SET_RATE_PARENT, 3749 .ops = &clk_branch2_ops, 3750 }, 3751 }, 3752 }; 3753 3754 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 3755 .halt_reg = 0xa4014, 3756 .halt_check = BRANCH_HALT_VOTED, 3757 .hwcg_reg = 0xa4014, 3758 .hwcg_bit = 1, 3759 .clkr = { 3760 .enable_reg = 0x52018, 3761 .enable_mask = BIT(6), 3762 .hw.init = &(const struct clk_init_data) { 3763 .name = "gcc_pcie_0_slv_axi_clk", 3764 .ops = &clk_branch2_ops, 3765 }, 3766 }, 3767 }; 3768 3769 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 3770 .halt_reg = 0xa4010, 3771 .halt_check = BRANCH_HALT_VOTED, 3772 .clkr = { 3773 .enable_reg = 0x52018, 3774 .enable_mask = BIT(5), 3775 .hw.init = &(const struct clk_init_data) { 3776 .name = "gcc_pcie_0_slv_q2a_axi_clk", 3777 .ops = &clk_branch2_ops, 3778 }, 3779 }, 3780 }; 3781 3782 static struct clk_branch gcc_pcie_1_aux_clk = { 3783 .halt_reg = 0x8d028, 3784 .halt_check = BRANCH_HALT_VOTED, 3785 .clkr = { 3786 .enable_reg = 0x52000, 3787 .enable_mask = BIT(29), 3788 .hw.init = &(const struct clk_init_data) { 3789 .name = "gcc_pcie_1_aux_clk", 3790 .parent_hws = (const struct clk_hw*[]){ 3791 &gcc_pcie_1_aux_clk_src.clkr.hw, 3792 }, 3793 .num_parents = 1, 3794 .flags = CLK_SET_RATE_PARENT, 3795 .ops = &clk_branch2_ops, 3796 }, 3797 }, 3798 }; 3799 3800 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 3801 .halt_reg = 0x8d024, 3802 .halt_check = BRANCH_HALT_VOTED, 3803 .hwcg_reg = 0x8d024, 3804 .hwcg_bit = 1, 3805 .clkr = { 3806 .enable_reg = 0x52000, 3807 .enable_mask = BIT(28), 3808 .hw.init = &(const struct clk_init_data) { 3809 .name = "gcc_pcie_1_cfg_ahb_clk", 3810 .ops = &clk_branch2_ops, 3811 }, 3812 }, 3813 }; 3814 3815 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 3816 .halt_reg = 0x8d01c, 3817 .halt_check = BRANCH_HALT_SKIP, 3818 .hwcg_reg = 0x8d01c, 3819 .hwcg_bit = 1, 3820 .clkr = { 3821 .enable_reg = 0x52000, 3822 .enable_mask = BIT(27), 3823 .hw.init = &(const struct clk_init_data) { 3824 .name = "gcc_pcie_1_mstr_axi_clk", 3825 .ops = &clk_branch2_ops, 3826 }, 3827 }, 3828 }; 3829 3830 static struct clk_branch gcc_pcie_1_pipe_clk = { 3831 .halt_reg = 0x8d030, 3832 .halt_check = BRANCH_HALT_SKIP, 3833 .clkr = { 3834 .enable_reg = 0x52000, 3835 .enable_mask = BIT(30), 3836 .hw.init = &(const struct clk_init_data) { 3837 .name = "gcc_pcie_1_pipe_clk", 3838 .parent_hws = (const struct clk_hw*[]){ 3839 &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw, 3840 }, 3841 .num_parents = 1, 3842 .flags = CLK_SET_RATE_PARENT, 3843 .ops = &clk_branch2_ops, 3844 }, 3845 }, 3846 }; 3847 3848 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 3849 .halt_reg = 0x8d014, 3850 .halt_check = BRANCH_HALT_VOTED, 3851 .hwcg_reg = 0x8d014, 3852 .hwcg_bit = 1, 3853 .clkr = { 3854 .enable_reg = 0x52000, 3855 .enable_mask = BIT(26), 3856 .hw.init = &(const struct clk_init_data) { 3857 .name = "gcc_pcie_1_slv_axi_clk", 3858 .ops = &clk_branch2_ops, 3859 }, 3860 }, 3861 }; 3862 3863 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 3864 .halt_reg = 0x8d010, 3865 .halt_check = BRANCH_HALT_VOTED, 3866 .clkr = { 3867 .enable_reg = 0x52000, 3868 .enable_mask = BIT(25), 3869 .hw.init = &(const struct clk_init_data) { 3870 .name = "gcc_pcie_1_slv_q2a_axi_clk", 3871 .ops = &clk_branch2_ops, 3872 }, 3873 }, 3874 }; 3875 3876 static struct clk_branch gcc_pcie_2a2b_clkref_clk = { 3877 .halt_reg = 0x8c034, 3878 .halt_check = BRANCH_HALT, 3879 .clkr = { 3880 .enable_reg = 0x8c034, 3881 .enable_mask = BIT(0), 3882 .hw.init = &(const struct clk_init_data) { 3883 .name = "gcc_pcie_2a2b_clkref_clk", 3884 .ops = &clk_branch2_ops, 3885 }, 3886 }, 3887 }; 3888 3889 static struct clk_branch gcc_pcie_2a_aux_clk = { 3890 .halt_reg = 0x9d028, 3891 .halt_check = BRANCH_HALT_VOTED, 3892 .clkr = { 3893 .enable_reg = 0x52010, 3894 .enable_mask = BIT(13), 3895 .hw.init = &(const struct clk_init_data) { 3896 .name = "gcc_pcie_2a_aux_clk", 3897 .parent_hws = (const struct clk_hw*[]){ 3898 &gcc_pcie_2a_aux_clk_src.clkr.hw, 3899 }, 3900 .num_parents = 1, 3901 .flags = CLK_SET_RATE_PARENT, 3902 .ops = &clk_branch2_ops, 3903 }, 3904 }, 3905 }; 3906 3907 static struct clk_branch gcc_pcie_2a_cfg_ahb_clk = { 3908 .halt_reg = 0x9d024, 3909 .halt_check = BRANCH_HALT_VOTED, 3910 .hwcg_reg = 0x9d024, 3911 .hwcg_bit = 1, 3912 .clkr = { 3913 .enable_reg = 0x52010, 3914 .enable_mask = BIT(12), 3915 .hw.init = &(const struct clk_init_data) { 3916 .name = "gcc_pcie_2a_cfg_ahb_clk", 3917 .ops = &clk_branch2_ops, 3918 }, 3919 }, 3920 }; 3921 3922 static struct clk_branch gcc_pcie_2a_mstr_axi_clk = { 3923 .halt_reg = 0x9d01c, 3924 .halt_check = BRANCH_HALT_SKIP, 3925 .hwcg_reg = 0x9d01c, 3926 .hwcg_bit = 1, 3927 .clkr = { 3928 .enable_reg = 0x52010, 3929 .enable_mask = BIT(11), 3930 .hw.init = &(const struct clk_init_data) { 3931 .name = "gcc_pcie_2a_mstr_axi_clk", 3932 .ops = &clk_branch2_ops, 3933 }, 3934 }, 3935 }; 3936 3937 static struct clk_branch gcc_pcie_2a_pipe_clk = { 3938 .halt_reg = 0x9d030, 3939 .halt_check = BRANCH_HALT_SKIP, 3940 .clkr = { 3941 .enable_reg = 0x52010, 3942 .enable_mask = BIT(14), 3943 .hw.init = &(const struct clk_init_data) { 3944 .name = "gcc_pcie_2a_pipe_clk", 3945 .parent_hws = (const struct clk_hw*[]){ 3946 &gcc_pcie_2a_pipe_clk_src.clkr.hw, 3947 }, 3948 .num_parents = 1, 3949 .flags = CLK_SET_RATE_PARENT, 3950 .ops = &clk_branch2_ops, 3951 }, 3952 }, 3953 }; 3954 3955 static struct clk_branch gcc_pcie_2a_pipediv2_clk = { 3956 .halt_reg = 0x9d038, 3957 .halt_check = BRANCH_HALT_SKIP, 3958 .clkr = { 3959 .enable_reg = 0x52018, 3960 .enable_mask = BIT(22), 3961 .hw.init = &(const struct clk_init_data) { 3962 .name = "gcc_pcie_2a_pipediv2_clk", 3963 .parent_hws = (const struct clk_hw*[]){ 3964 &gcc_pcie_2a_pipe_div_clk_src.clkr.hw, 3965 }, 3966 .num_parents = 1, 3967 .flags = CLK_SET_RATE_PARENT, 3968 .ops = &clk_branch2_ops, 3969 }, 3970 }, 3971 }; 3972 3973 static struct clk_branch gcc_pcie_2a_slv_axi_clk = { 3974 .halt_reg = 0x9d014, 3975 .halt_check = BRANCH_HALT_VOTED, 3976 .hwcg_reg = 0x9d014, 3977 .hwcg_bit = 1, 3978 .clkr = { 3979 .enable_reg = 0x52010, 3980 .enable_mask = BIT(10), 3981 .hw.init = &(const struct clk_init_data) { 3982 .name = "gcc_pcie_2a_slv_axi_clk", 3983 .ops = &clk_branch2_ops, 3984 }, 3985 }, 3986 }; 3987 3988 static struct clk_branch gcc_pcie_2a_slv_q2a_axi_clk = { 3989 .halt_reg = 0x9d010, 3990 .halt_check = BRANCH_HALT_VOTED, 3991 .clkr = { 3992 .enable_reg = 0x52018, 3993 .enable_mask = BIT(12), 3994 .hw.init = &(const struct clk_init_data) { 3995 .name = "gcc_pcie_2a_slv_q2a_axi_clk", 3996 .ops = &clk_branch2_ops, 3997 }, 3998 }, 3999 }; 4000 4001 static struct clk_branch gcc_pcie_2b_aux_clk = { 4002 .halt_reg = 0x9e028, 4003 .halt_check = BRANCH_HALT_VOTED, 4004 .clkr = { 4005 .enable_reg = 0x52010, 4006 .enable_mask = BIT(20), 4007 .hw.init = &(const struct clk_init_data) { 4008 .name = "gcc_pcie_2b_aux_clk", 4009 .parent_hws = (const struct clk_hw*[]){ 4010 &gcc_pcie_2b_aux_clk_src.clkr.hw, 4011 }, 4012 .num_parents = 1, 4013 .flags = CLK_SET_RATE_PARENT, 4014 .ops = &clk_branch2_ops, 4015 }, 4016 }, 4017 }; 4018 4019 static struct clk_branch gcc_pcie_2b_cfg_ahb_clk = { 4020 .halt_reg = 0x9e024, 4021 .halt_check = BRANCH_HALT_VOTED, 4022 .hwcg_reg = 0x9e024, 4023 .hwcg_bit = 1, 4024 .clkr = { 4025 .enable_reg = 0x52010, 4026 .enable_mask = BIT(19), 4027 .hw.init = &(const struct clk_init_data) { 4028 .name = "gcc_pcie_2b_cfg_ahb_clk", 4029 .ops = &clk_branch2_ops, 4030 }, 4031 }, 4032 }; 4033 4034 static struct clk_branch gcc_pcie_2b_mstr_axi_clk = { 4035 .halt_reg = 0x9e01c, 4036 .halt_check = BRANCH_HALT_SKIP, 4037 .hwcg_reg = 0x9e01c, 4038 .hwcg_bit = 1, 4039 .clkr = { 4040 .enable_reg = 0x52010, 4041 .enable_mask = BIT(18), 4042 .hw.init = &(const struct clk_init_data) { 4043 .name = "gcc_pcie_2b_mstr_axi_clk", 4044 .ops = &clk_branch2_ops, 4045 }, 4046 }, 4047 }; 4048 4049 static struct clk_branch gcc_pcie_2b_pipe_clk = { 4050 .halt_reg = 0x9e030, 4051 .halt_check = BRANCH_HALT_SKIP, 4052 .clkr = { 4053 .enable_reg = 0x52010, 4054 .enable_mask = BIT(21), 4055 .hw.init = &(const struct clk_init_data) { 4056 .name = "gcc_pcie_2b_pipe_clk", 4057 .parent_hws = (const struct clk_hw*[]){ 4058 &gcc_pcie_2b_pipe_clk_src.clkr.hw, 4059 }, 4060 .num_parents = 1, 4061 .flags = CLK_SET_RATE_PARENT, 4062 .ops = &clk_branch2_ops, 4063 }, 4064 }, 4065 }; 4066 4067 static struct clk_branch gcc_pcie_2b_pipediv2_clk = { 4068 .halt_reg = 0x9e038, 4069 .halt_check = BRANCH_HALT_SKIP, 4070 .clkr = { 4071 .enable_reg = 0x52018, 4072 .enable_mask = BIT(23), 4073 .hw.init = &(const struct clk_init_data) { 4074 .name = "gcc_pcie_2b_pipediv2_clk", 4075 .parent_hws = (const struct clk_hw*[]){ 4076 &gcc_pcie_2b_pipe_div_clk_src.clkr.hw, 4077 }, 4078 .num_parents = 1, 4079 .flags = CLK_SET_RATE_PARENT, 4080 .ops = &clk_branch2_ops, 4081 }, 4082 }, 4083 }; 4084 4085 static struct clk_branch gcc_pcie_2b_slv_axi_clk = { 4086 .halt_reg = 0x9e014, 4087 .halt_check = BRANCH_HALT_VOTED, 4088 .hwcg_reg = 0x9e014, 4089 .hwcg_bit = 1, 4090 .clkr = { 4091 .enable_reg = 0x52010, 4092 .enable_mask = BIT(17), 4093 .hw.init = &(const struct clk_init_data) { 4094 .name = "gcc_pcie_2b_slv_axi_clk", 4095 .ops = &clk_branch2_ops, 4096 }, 4097 }, 4098 }; 4099 4100 static struct clk_branch gcc_pcie_2b_slv_q2a_axi_clk = { 4101 .halt_reg = 0x9e010, 4102 .halt_check = BRANCH_HALT_VOTED, 4103 .clkr = { 4104 .enable_reg = 0x52010, 4105 .enable_mask = BIT(16), 4106 .hw.init = &(const struct clk_init_data) { 4107 .name = "gcc_pcie_2b_slv_q2a_axi_clk", 4108 .ops = &clk_branch2_ops, 4109 }, 4110 }, 4111 }; 4112 4113 static struct clk_branch gcc_pcie_3a3b_clkref_clk = { 4114 .halt_reg = 0x8c038, 4115 .halt_check = BRANCH_HALT, 4116 .clkr = { 4117 .enable_reg = 0x8c038, 4118 .enable_mask = BIT(0), 4119 .hw.init = &(const struct clk_init_data) { 4120 .name = "gcc_pcie_3a3b_clkref_clk", 4121 .ops = &clk_branch2_ops, 4122 }, 4123 }, 4124 }; 4125 4126 static struct clk_branch gcc_pcie_3a_aux_clk = { 4127 .halt_reg = 0xa0028, 4128 .halt_check = BRANCH_HALT_VOTED, 4129 .clkr = { 4130 .enable_reg = 0x52010, 4131 .enable_mask = BIT(27), 4132 .hw.init = &(const struct clk_init_data) { 4133 .name = "gcc_pcie_3a_aux_clk", 4134 .parent_hws = (const struct clk_hw*[]){ 4135 &gcc_pcie_3a_aux_clk_src.clkr.hw, 4136 }, 4137 .num_parents = 1, 4138 .flags = CLK_SET_RATE_PARENT, 4139 .ops = &clk_branch2_ops, 4140 }, 4141 }, 4142 }; 4143 4144 static struct clk_branch gcc_pcie_3a_cfg_ahb_clk = { 4145 .halt_reg = 0xa0024, 4146 .halt_check = BRANCH_HALT_VOTED, 4147 .hwcg_reg = 0xa0024, 4148 .hwcg_bit = 1, 4149 .clkr = { 4150 .enable_reg = 0x52010, 4151 .enable_mask = BIT(26), 4152 .hw.init = &(const struct clk_init_data) { 4153 .name = "gcc_pcie_3a_cfg_ahb_clk", 4154 .ops = &clk_branch2_ops, 4155 }, 4156 }, 4157 }; 4158 4159 static struct clk_branch gcc_pcie_3a_mstr_axi_clk = { 4160 .halt_reg = 0xa001c, 4161 .halt_check = BRANCH_HALT_SKIP, 4162 .hwcg_reg = 0xa001c, 4163 .hwcg_bit = 1, 4164 .clkr = { 4165 .enable_reg = 0x52010, 4166 .enable_mask = BIT(25), 4167 .hw.init = &(const struct clk_init_data) { 4168 .name = "gcc_pcie_3a_mstr_axi_clk", 4169 .ops = &clk_branch2_ops, 4170 }, 4171 }, 4172 }; 4173 4174 static struct clk_branch gcc_pcie_3a_pipe_clk = { 4175 .halt_reg = 0xa0030, 4176 .halt_check = BRANCH_HALT_SKIP, 4177 .clkr = { 4178 .enable_reg = 0x52010, 4179 .enable_mask = BIT(28), 4180 .hw.init = &(const struct clk_init_data) { 4181 .name = "gcc_pcie_3a_pipe_clk", 4182 .parent_hws = (const struct clk_hw*[]){ 4183 &gcc_pcie_3a_pipe_clk_src.clkr.hw, 4184 }, 4185 .num_parents = 1, 4186 .flags = CLK_SET_RATE_PARENT, 4187 .ops = &clk_branch2_ops, 4188 }, 4189 }, 4190 }; 4191 4192 static struct clk_branch gcc_pcie_3a_pipediv2_clk = { 4193 .halt_reg = 0xa0038, 4194 .halt_check = BRANCH_HALT_SKIP, 4195 .clkr = { 4196 .enable_reg = 0x52018, 4197 .enable_mask = BIT(24), 4198 .hw.init = &(const struct clk_init_data) { 4199 .name = "gcc_pcie_3a_pipediv2_clk", 4200 .parent_hws = (const struct clk_hw*[]){ 4201 &gcc_pcie_3a_pipe_div_clk_src.clkr.hw, 4202 }, 4203 .num_parents = 1, 4204 .flags = CLK_SET_RATE_PARENT, 4205 .ops = &clk_branch2_ops, 4206 }, 4207 }, 4208 }; 4209 4210 static struct clk_branch gcc_pcie_3a_slv_axi_clk = { 4211 .halt_reg = 0xa0014, 4212 .halt_check = BRANCH_HALT_VOTED, 4213 .hwcg_reg = 0xa0014, 4214 .hwcg_bit = 1, 4215 .clkr = { 4216 .enable_reg = 0x52010, 4217 .enable_mask = BIT(24), 4218 .hw.init = &(const struct clk_init_data) { 4219 .name = "gcc_pcie_3a_slv_axi_clk", 4220 .ops = &clk_branch2_ops, 4221 }, 4222 }, 4223 }; 4224 4225 static struct clk_branch gcc_pcie_3a_slv_q2a_axi_clk = { 4226 .halt_reg = 0xa0010, 4227 .halt_check = BRANCH_HALT_VOTED, 4228 .clkr = { 4229 .enable_reg = 0x52010, 4230 .enable_mask = BIT(23), 4231 .hw.init = &(const struct clk_init_data) { 4232 .name = "gcc_pcie_3a_slv_q2a_axi_clk", 4233 .ops = &clk_branch2_ops, 4234 }, 4235 }, 4236 }; 4237 4238 static struct clk_branch gcc_pcie_3b_aux_clk = { 4239 .halt_reg = 0xa2028, 4240 .halt_check = BRANCH_HALT_VOTED, 4241 .clkr = { 4242 .enable_reg = 0x52018, 4243 .enable_mask = BIT(2), 4244 .hw.init = &(const struct clk_init_data) { 4245 .name = "gcc_pcie_3b_aux_clk", 4246 .parent_hws = (const struct clk_hw*[]){ 4247 &gcc_pcie_3b_aux_clk_src.clkr.hw, 4248 }, 4249 .num_parents = 1, 4250 .flags = CLK_SET_RATE_PARENT, 4251 .ops = &clk_branch2_ops, 4252 }, 4253 }, 4254 }; 4255 4256 static struct clk_branch gcc_pcie_3b_cfg_ahb_clk = { 4257 .halt_reg = 0xa2024, 4258 .halt_check = BRANCH_HALT_VOTED, 4259 .hwcg_reg = 0xa2024, 4260 .hwcg_bit = 1, 4261 .clkr = { 4262 .enable_reg = 0x52018, 4263 .enable_mask = BIT(1), 4264 .hw.init = &(const struct clk_init_data) { 4265 .name = "gcc_pcie_3b_cfg_ahb_clk", 4266 .ops = &clk_branch2_ops, 4267 }, 4268 }, 4269 }; 4270 4271 static struct clk_branch gcc_pcie_3b_mstr_axi_clk = { 4272 .halt_reg = 0xa201c, 4273 .halt_check = BRANCH_HALT_SKIP, 4274 .hwcg_reg = 0xa201c, 4275 .hwcg_bit = 1, 4276 .clkr = { 4277 .enable_reg = 0x52018, 4278 .enable_mask = BIT(0), 4279 .hw.init = &(const struct clk_init_data) { 4280 .name = "gcc_pcie_3b_mstr_axi_clk", 4281 .ops = &clk_branch2_ops, 4282 }, 4283 }, 4284 }; 4285 4286 static struct clk_branch gcc_pcie_3b_pipe_clk = { 4287 .halt_reg = 0xa2030, 4288 .halt_check = BRANCH_HALT_SKIP, 4289 .clkr = { 4290 .enable_reg = 0x52018, 4291 .enable_mask = BIT(3), 4292 .hw.init = &(const struct clk_init_data) { 4293 .name = "gcc_pcie_3b_pipe_clk", 4294 .parent_hws = (const struct clk_hw*[]){ 4295 &gcc_pcie_3b_pipe_clk_src.clkr.hw, 4296 }, 4297 .num_parents = 1, 4298 .flags = CLK_SET_RATE_PARENT, 4299 .ops = &clk_branch2_ops, 4300 }, 4301 }, 4302 }; 4303 4304 static struct clk_branch gcc_pcie_3b_pipediv2_clk = { 4305 .halt_reg = 0xa2038, 4306 .halt_check = BRANCH_HALT_SKIP, 4307 .clkr = { 4308 .enable_reg = 0x52018, 4309 .enable_mask = BIT(25), 4310 .hw.init = &(const struct clk_init_data) { 4311 .name = "gcc_pcie_3b_pipediv2_clk", 4312 .parent_hws = (const struct clk_hw*[]){ 4313 &gcc_pcie_3b_pipe_div_clk_src.clkr.hw, 4314 }, 4315 .num_parents = 1, 4316 .flags = CLK_SET_RATE_PARENT, 4317 .ops = &clk_branch2_ops, 4318 }, 4319 }, 4320 }; 4321 4322 static struct clk_branch gcc_pcie_3b_slv_axi_clk = { 4323 .halt_reg = 0xa2014, 4324 .halt_check = BRANCH_HALT_VOTED, 4325 .hwcg_reg = 0xa2014, 4326 .hwcg_bit = 1, 4327 .clkr = { 4328 .enable_reg = 0x52010, 4329 .enable_mask = BIT(31), 4330 .hw.init = &(const struct clk_init_data) { 4331 .name = "gcc_pcie_3b_slv_axi_clk", 4332 .ops = &clk_branch2_ops, 4333 }, 4334 }, 4335 }; 4336 4337 static struct clk_branch gcc_pcie_3b_slv_q2a_axi_clk = { 4338 .halt_reg = 0xa2010, 4339 .halt_check = BRANCH_HALT_VOTED, 4340 .clkr = { 4341 .enable_reg = 0x52010, 4342 .enable_mask = BIT(30), 4343 .hw.init = &(const struct clk_init_data) { 4344 .name = "gcc_pcie_3b_slv_q2a_axi_clk", 4345 .ops = &clk_branch2_ops, 4346 }, 4347 }, 4348 }; 4349 4350 static struct clk_branch gcc_pcie_4_aux_clk = { 4351 .halt_reg = 0x6b028, 4352 .halt_check = BRANCH_HALT_VOTED, 4353 .clkr = { 4354 .enable_reg = 0x52008, 4355 .enable_mask = BIT(3), 4356 .hw.init = &(const struct clk_init_data) { 4357 .name = "gcc_pcie_4_aux_clk", 4358 .parent_hws = (const struct clk_hw*[]){ 4359 &gcc_pcie_4_aux_clk_src.clkr.hw, 4360 }, 4361 .num_parents = 1, 4362 .flags = CLK_SET_RATE_PARENT, 4363 .ops = &clk_branch2_ops, 4364 }, 4365 }, 4366 }; 4367 4368 static struct clk_branch gcc_pcie_4_cfg_ahb_clk = { 4369 .halt_reg = 0x6b024, 4370 .halt_check = BRANCH_HALT_VOTED, 4371 .hwcg_reg = 0x6b024, 4372 .hwcg_bit = 1, 4373 .clkr = { 4374 .enable_reg = 0x52008, 4375 .enable_mask = BIT(2), 4376 .hw.init = &(const struct clk_init_data) { 4377 .name = "gcc_pcie_4_cfg_ahb_clk", 4378 .ops = &clk_branch2_ops, 4379 }, 4380 }, 4381 }; 4382 4383 static struct clk_branch gcc_pcie_4_clkref_clk = { 4384 .halt_reg = 0x8c030, 4385 .halt_check = BRANCH_HALT, 4386 .clkr = { 4387 .enable_reg = 0x8c030, 4388 .enable_mask = BIT(0), 4389 .hw.init = &(const struct clk_init_data) { 4390 .name = "gcc_pcie_4_clkref_clk", 4391 .ops = &clk_branch2_ops, 4392 }, 4393 }, 4394 }; 4395 4396 static struct clk_branch gcc_pcie_4_mstr_axi_clk = { 4397 .halt_reg = 0x6b01c, 4398 .halt_check = BRANCH_HALT_SKIP, 4399 .hwcg_reg = 0x6b01c, 4400 .hwcg_bit = 1, 4401 .clkr = { 4402 .enable_reg = 0x52008, 4403 .enable_mask = BIT(1), 4404 .hw.init = &(const struct clk_init_data) { 4405 .name = "gcc_pcie_4_mstr_axi_clk", 4406 .ops = &clk_branch2_ops, 4407 }, 4408 }, 4409 }; 4410 4411 static struct clk_branch gcc_pcie_4_pipe_clk = { 4412 .halt_reg = 0x6b030, 4413 .halt_check = BRANCH_HALT_SKIP, 4414 .clkr = { 4415 .enable_reg = 0x52008, 4416 .enable_mask = BIT(4), 4417 .hw.init = &(const struct clk_init_data) { 4418 .name = "gcc_pcie_4_pipe_clk", 4419 .parent_hws = (const struct clk_hw*[]){ 4420 &gcc_pcie_4_pipe_clk_src.clkr.hw, 4421 }, 4422 .num_parents = 1, 4423 .flags = CLK_SET_RATE_PARENT, 4424 .ops = &clk_branch2_ops, 4425 }, 4426 }, 4427 }; 4428 4429 static struct clk_branch gcc_pcie_4_pipediv2_clk = { 4430 .halt_reg = 0x6b038, 4431 .halt_check = BRANCH_HALT_SKIP, 4432 .clkr = { 4433 .enable_reg = 0x52018, 4434 .enable_mask = BIT(16), 4435 .hw.init = &(const struct clk_init_data) { 4436 .name = "gcc_pcie_4_pipediv2_clk", 4437 .parent_hws = (const struct clk_hw*[]){ 4438 &gcc_pcie_4_pipe_div_clk_src.clkr.hw, 4439 }, 4440 .num_parents = 1, 4441 .flags = CLK_SET_RATE_PARENT, 4442 .ops = &clk_branch2_ops, 4443 }, 4444 }, 4445 }; 4446 4447 static struct clk_branch gcc_pcie_4_slv_axi_clk = { 4448 .halt_reg = 0x6b014, 4449 .halt_check = BRANCH_HALT_VOTED, 4450 .hwcg_reg = 0x6b014, 4451 .hwcg_bit = 1, 4452 .clkr = { 4453 .enable_reg = 0x52008, 4454 .enable_mask = BIT(0), 4455 .hw.init = &(const struct clk_init_data) { 4456 .name = "gcc_pcie_4_slv_axi_clk", 4457 .ops = &clk_branch2_ops, 4458 }, 4459 }, 4460 }; 4461 4462 static struct clk_branch gcc_pcie_4_slv_q2a_axi_clk = { 4463 .halt_reg = 0x6b010, 4464 .halt_check = BRANCH_HALT_VOTED, 4465 .clkr = { 4466 .enable_reg = 0x52008, 4467 .enable_mask = BIT(5), 4468 .hw.init = &(const struct clk_init_data) { 4469 .name = "gcc_pcie_4_slv_q2a_axi_clk", 4470 .ops = &clk_branch2_ops, 4471 }, 4472 }, 4473 }; 4474 4475 static struct clk_branch gcc_pcie_rscc_ahb_clk = { 4476 .halt_reg = 0xae008, 4477 .halt_check = BRANCH_HALT_VOTED, 4478 .hwcg_reg = 0xae008, 4479 .hwcg_bit = 1, 4480 .clkr = { 4481 .enable_reg = 0x52020, 4482 .enable_mask = BIT(17), 4483 .hw.init = &(const struct clk_init_data) { 4484 .name = "gcc_pcie_rscc_ahb_clk", 4485 .ops = &clk_branch2_ops, 4486 }, 4487 }, 4488 }; 4489 4490 static struct clk_branch gcc_pcie_rscc_xo_clk = { 4491 .halt_reg = 0xae004, 4492 .halt_check = BRANCH_HALT_VOTED, 4493 .clkr = { 4494 .enable_reg = 0x52020, 4495 .enable_mask = BIT(16), 4496 .hw.init = &(const struct clk_init_data) { 4497 .name = "gcc_pcie_rscc_xo_clk", 4498 .parent_hws = (const struct clk_hw*[]){ 4499 &gcc_pcie_rscc_xo_clk_src.clkr.hw, 4500 }, 4501 .num_parents = 1, 4502 .flags = CLK_SET_RATE_PARENT, 4503 .ops = &clk_branch2_ops, 4504 }, 4505 }, 4506 }; 4507 4508 static struct clk_branch gcc_pcie_throttle_cfg_clk = { 4509 .halt_reg = 0xa6028, 4510 .halt_check = BRANCH_HALT_VOTED, 4511 .clkr = { 4512 .enable_reg = 0x52020, 4513 .enable_mask = BIT(15), 4514 .hw.init = &(const struct clk_init_data) { 4515 .name = "gcc_pcie_throttle_cfg_clk", 4516 .ops = &clk_branch2_ops, 4517 }, 4518 }, 4519 }; 4520 4521 static struct clk_branch gcc_pdm2_clk = { 4522 .halt_reg = 0x3300c, 4523 .halt_check = BRANCH_HALT, 4524 .clkr = { 4525 .enable_reg = 0x3300c, 4526 .enable_mask = BIT(0), 4527 .hw.init = &(const struct clk_init_data) { 4528 .name = "gcc_pdm2_clk", 4529 .parent_hws = (const struct clk_hw*[]){ 4530 &gcc_pdm2_clk_src.clkr.hw, 4531 }, 4532 .num_parents = 1, 4533 .flags = CLK_SET_RATE_PARENT, 4534 .ops = &clk_branch2_ops, 4535 }, 4536 }, 4537 }; 4538 4539 static struct clk_branch gcc_pdm_ahb_clk = { 4540 .halt_reg = 0x33004, 4541 .halt_check = BRANCH_HALT_VOTED, 4542 .hwcg_reg = 0x33004, 4543 .hwcg_bit = 1, 4544 .clkr = { 4545 .enable_reg = 0x33004, 4546 .enable_mask = BIT(0), 4547 .hw.init = &(const struct clk_init_data) { 4548 .name = "gcc_pdm_ahb_clk", 4549 .ops = &clk_branch2_ops, 4550 }, 4551 }, 4552 }; 4553 4554 static struct clk_branch gcc_pdm_xo4_clk = { 4555 .halt_reg = 0x33008, 4556 .halt_check = BRANCH_HALT, 4557 .clkr = { 4558 .enable_reg = 0x33008, 4559 .enable_mask = BIT(0), 4560 .hw.init = &(const struct clk_init_data) { 4561 .name = "gcc_pdm_xo4_clk", 4562 .ops = &clk_branch2_ops, 4563 }, 4564 }, 4565 }; 4566 4567 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 4568 .halt_reg = 0x26008, 4569 .halt_check = BRANCH_HALT_VOTED, 4570 .hwcg_reg = 0x26008, 4571 .hwcg_bit = 1, 4572 .clkr = { 4573 .enable_reg = 0x26008, 4574 .enable_mask = BIT(0), 4575 .hw.init = &(const struct clk_init_data) { 4576 .name = "gcc_qmip_camera_nrt_ahb_clk", 4577 .ops = &clk_branch2_ops, 4578 }, 4579 }, 4580 }; 4581 4582 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 4583 .halt_reg = 0x2600c, 4584 .halt_check = BRANCH_HALT_VOTED, 4585 .hwcg_reg = 0x2600c, 4586 .hwcg_bit = 1, 4587 .clkr = { 4588 .enable_reg = 0x2600c, 4589 .enable_mask = BIT(0), 4590 .hw.init = &(const struct clk_init_data) { 4591 .name = "gcc_qmip_camera_rt_ahb_clk", 4592 .ops = &clk_branch2_ops, 4593 }, 4594 }, 4595 }; 4596 4597 static struct clk_branch gcc_qmip_disp1_ahb_clk = { 4598 .halt_reg = 0xbb008, 4599 .halt_check = BRANCH_HALT_VOTED, 4600 .hwcg_reg = 0xbb008, 4601 .hwcg_bit = 1, 4602 .clkr = { 4603 .enable_reg = 0xbb008, 4604 .enable_mask = BIT(0), 4605 .hw.init = &(const struct clk_init_data) { 4606 .name = "gcc_qmip_disp1_ahb_clk", 4607 .ops = &clk_branch2_ops, 4608 }, 4609 }, 4610 }; 4611 4612 static struct clk_branch gcc_qmip_disp1_rot_ahb_clk = { 4613 .halt_reg = 0xbb00c, 4614 .halt_check = BRANCH_HALT_VOTED, 4615 .hwcg_reg = 0xbb00c, 4616 .hwcg_bit = 1, 4617 .clkr = { 4618 .enable_reg = 0xbb00c, 4619 .enable_mask = BIT(0), 4620 .hw.init = &(const struct clk_init_data) { 4621 .name = "gcc_qmip_disp1_rot_ahb_clk", 4622 .ops = &clk_branch2_ops, 4623 }, 4624 }, 4625 }; 4626 4627 static struct clk_branch gcc_qmip_disp_ahb_clk = { 4628 .halt_reg = 0x27008, 4629 .halt_check = BRANCH_HALT_VOTED, 4630 .hwcg_reg = 0x27008, 4631 .hwcg_bit = 1, 4632 .clkr = { 4633 .enable_reg = 0x27008, 4634 .enable_mask = BIT(0), 4635 .hw.init = &(const struct clk_init_data) { 4636 .name = "gcc_qmip_disp_ahb_clk", 4637 .ops = &clk_branch2_ops, 4638 }, 4639 }, 4640 }; 4641 4642 static struct clk_branch gcc_qmip_disp_rot_ahb_clk = { 4643 .halt_reg = 0x2700c, 4644 .halt_check = BRANCH_HALT_VOTED, 4645 .hwcg_reg = 0x2700c, 4646 .hwcg_bit = 1, 4647 .clkr = { 4648 .enable_reg = 0x2700c, 4649 .enable_mask = BIT(0), 4650 .hw.init = &(const struct clk_init_data) { 4651 .name = "gcc_qmip_disp_rot_ahb_clk", 4652 .ops = &clk_branch2_ops, 4653 }, 4654 }, 4655 }; 4656 4657 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 4658 .halt_reg = 0x28008, 4659 .halt_check = BRANCH_HALT_VOTED, 4660 .hwcg_reg = 0x28008, 4661 .hwcg_bit = 1, 4662 .clkr = { 4663 .enable_reg = 0x28008, 4664 .enable_mask = BIT(0), 4665 .hw.init = &(const struct clk_init_data) { 4666 .name = "gcc_qmip_video_cvp_ahb_clk", 4667 .ops = &clk_branch2_ops, 4668 }, 4669 }, 4670 }; 4671 4672 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 4673 .halt_reg = 0x2800c, 4674 .halt_check = BRANCH_HALT_VOTED, 4675 .hwcg_reg = 0x2800c, 4676 .hwcg_bit = 1, 4677 .clkr = { 4678 .enable_reg = 0x2800c, 4679 .enable_mask = BIT(0), 4680 .hw.init = &(const struct clk_init_data) { 4681 .name = "gcc_qmip_video_vcodec_ahb_clk", 4682 .ops = &clk_branch2_ops, 4683 }, 4684 }, 4685 }; 4686 4687 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 4688 .halt_reg = 0x17014, 4689 .halt_check = BRANCH_HALT_VOTED, 4690 .clkr = { 4691 .enable_reg = 0x52008, 4692 .enable_mask = BIT(9), 4693 .hw.init = &(const struct clk_init_data) { 4694 .name = "gcc_qupv3_wrap0_core_2x_clk", 4695 .ops = &clk_branch2_ops, 4696 }, 4697 }, 4698 }; 4699 4700 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 4701 .halt_reg = 0x1700c, 4702 .halt_check = BRANCH_HALT_VOTED, 4703 .clkr = { 4704 .enable_reg = 0x52008, 4705 .enable_mask = BIT(8), 4706 .hw.init = &(const struct clk_init_data) { 4707 .name = "gcc_qupv3_wrap0_core_clk", 4708 .ops = &clk_branch2_ops, 4709 }, 4710 }, 4711 }; 4712 4713 static struct clk_branch gcc_qupv3_wrap0_qspi0_clk = { 4714 .halt_reg = 0x17ac4, 4715 .halt_check = BRANCH_HALT_VOTED, 4716 .clkr = { 4717 .enable_reg = 0x52020, 4718 .enable_mask = BIT(0), 4719 .hw.init = &(const struct clk_init_data) { 4720 .name = "gcc_qupv3_wrap0_qspi0_clk", 4721 .parent_hws = (const struct clk_hw*[]){ 4722 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 4723 }, 4724 .num_parents = 1, 4725 .flags = CLK_SET_RATE_PARENT, 4726 .ops = &clk_branch2_ops, 4727 }, 4728 }, 4729 }; 4730 4731 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 4732 .halt_reg = 0x17144, 4733 .halt_check = BRANCH_HALT_VOTED, 4734 .clkr = { 4735 .enable_reg = 0x52008, 4736 .enable_mask = BIT(10), 4737 .hw.init = &(const struct clk_init_data) { 4738 .name = "gcc_qupv3_wrap0_s0_clk", 4739 .parent_hws = (const struct clk_hw*[]){ 4740 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 4741 }, 4742 .num_parents = 1, 4743 .flags = CLK_SET_RATE_PARENT, 4744 .ops = &clk_branch2_ops, 4745 }, 4746 }, 4747 }; 4748 4749 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 4750 .halt_reg = 0x17274, 4751 .halt_check = BRANCH_HALT_VOTED, 4752 .clkr = { 4753 .enable_reg = 0x52008, 4754 .enable_mask = BIT(11), 4755 .hw.init = &(const struct clk_init_data) { 4756 .name = "gcc_qupv3_wrap0_s1_clk", 4757 .parent_hws = (const struct clk_hw*[]){ 4758 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 4759 }, 4760 .num_parents = 1, 4761 .flags = CLK_SET_RATE_PARENT, 4762 .ops = &clk_branch2_ops, 4763 }, 4764 }, 4765 }; 4766 4767 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 4768 .halt_reg = 0x173a4, 4769 .halt_check = BRANCH_HALT_VOTED, 4770 .clkr = { 4771 .enable_reg = 0x52008, 4772 .enable_mask = BIT(12), 4773 .hw.init = &(const struct clk_init_data) { 4774 .name = "gcc_qupv3_wrap0_s2_clk", 4775 .parent_hws = (const struct clk_hw*[]){ 4776 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 4777 }, 4778 .num_parents = 1, 4779 .flags = CLK_SET_RATE_PARENT, 4780 .ops = &clk_branch2_ops, 4781 }, 4782 }, 4783 }; 4784 4785 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 4786 .halt_reg = 0x174d4, 4787 .halt_check = BRANCH_HALT_VOTED, 4788 .clkr = { 4789 .enable_reg = 0x52008, 4790 .enable_mask = BIT(13), 4791 .hw.init = &(const struct clk_init_data) { 4792 .name = "gcc_qupv3_wrap0_s3_clk", 4793 .parent_hws = (const struct clk_hw*[]){ 4794 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 4795 }, 4796 .num_parents = 1, 4797 .flags = CLK_SET_RATE_PARENT, 4798 .ops = &clk_branch2_ops, 4799 }, 4800 }, 4801 }; 4802 4803 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 4804 .halt_reg = 0x17604, 4805 .halt_check = BRANCH_HALT_VOTED, 4806 .clkr = { 4807 .enable_reg = 0x52008, 4808 .enable_mask = BIT(14), 4809 .hw.init = &(const struct clk_init_data) { 4810 .name = "gcc_qupv3_wrap0_s4_clk", 4811 .parent_hws = (const struct clk_hw*[]){ 4812 &gcc_qupv3_wrap0_s4_div_clk_src.clkr.hw, 4813 }, 4814 .num_parents = 1, 4815 .flags = CLK_SET_RATE_PARENT, 4816 .ops = &clk_branch2_ops, 4817 }, 4818 }, 4819 }; 4820 4821 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 4822 .halt_reg = 0x17734, 4823 .halt_check = BRANCH_HALT_VOTED, 4824 .clkr = { 4825 .enable_reg = 0x52008, 4826 .enable_mask = BIT(15), 4827 .hw.init = &(const struct clk_init_data) { 4828 .name = "gcc_qupv3_wrap0_s5_clk", 4829 .parent_hws = (const struct clk_hw*[]){ 4830 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 4831 }, 4832 .num_parents = 1, 4833 .flags = CLK_SET_RATE_PARENT, 4834 .ops = &clk_branch2_ops, 4835 }, 4836 }, 4837 }; 4838 4839 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 4840 .halt_reg = 0x17864, 4841 .halt_check = BRANCH_HALT_VOTED, 4842 .clkr = { 4843 .enable_reg = 0x52008, 4844 .enable_mask = BIT(16), 4845 .hw.init = &(const struct clk_init_data) { 4846 .name = "gcc_qupv3_wrap0_s6_clk", 4847 .parent_hws = (const struct clk_hw*[]){ 4848 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 4849 }, 4850 .num_parents = 1, 4851 .flags = CLK_SET_RATE_PARENT, 4852 .ops = &clk_branch2_ops, 4853 }, 4854 }, 4855 }; 4856 4857 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 4858 .halt_reg = 0x17994, 4859 .halt_check = BRANCH_HALT_VOTED, 4860 .clkr = { 4861 .enable_reg = 0x52008, 4862 .enable_mask = BIT(17), 4863 .hw.init = &(const struct clk_init_data) { 4864 .name = "gcc_qupv3_wrap0_s7_clk", 4865 .parent_hws = (const struct clk_hw*[]){ 4866 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 4867 }, 4868 .num_parents = 1, 4869 .flags = CLK_SET_RATE_PARENT, 4870 .ops = &clk_branch2_ops, 4871 }, 4872 }, 4873 }; 4874 4875 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 4876 .halt_reg = 0x18014, 4877 .halt_check = BRANCH_HALT_VOTED, 4878 .clkr = { 4879 .enable_reg = 0x52008, 4880 .enable_mask = BIT(18), 4881 .hw.init = &(const struct clk_init_data) { 4882 .name = "gcc_qupv3_wrap1_core_2x_clk", 4883 .ops = &clk_branch2_ops, 4884 }, 4885 }, 4886 }; 4887 4888 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 4889 .halt_reg = 0x1800c, 4890 .halt_check = BRANCH_HALT_VOTED, 4891 .clkr = { 4892 .enable_reg = 0x52008, 4893 .enable_mask = BIT(19), 4894 .hw.init = &(const struct clk_init_data) { 4895 .name = "gcc_qupv3_wrap1_core_clk", 4896 .ops = &clk_branch2_ops, 4897 }, 4898 }, 4899 }; 4900 4901 static struct clk_branch gcc_qupv3_wrap1_qspi0_clk = { 4902 .halt_reg = 0x18ac4, 4903 .halt_check = BRANCH_HALT_VOTED, 4904 .clkr = { 4905 .enable_reg = 0x52020, 4906 .enable_mask = BIT(2), 4907 .hw.init = &(const struct clk_init_data) { 4908 .name = "gcc_qupv3_wrap1_qspi0_clk", 4909 .parent_hws = (const struct clk_hw*[]){ 4910 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 4911 }, 4912 .num_parents = 1, 4913 .flags = CLK_SET_RATE_PARENT, 4914 .ops = &clk_branch2_ops, 4915 }, 4916 }, 4917 }; 4918 4919 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 4920 .halt_reg = 0x18144, 4921 .halt_check = BRANCH_HALT_VOTED, 4922 .clkr = { 4923 .enable_reg = 0x52008, 4924 .enable_mask = BIT(22), 4925 .hw.init = &(const struct clk_init_data) { 4926 .name = "gcc_qupv3_wrap1_s0_clk", 4927 .parent_hws = (const struct clk_hw*[]){ 4928 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 4929 }, 4930 .num_parents = 1, 4931 .flags = CLK_SET_RATE_PARENT, 4932 .ops = &clk_branch2_ops, 4933 }, 4934 }, 4935 }; 4936 4937 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 4938 .halt_reg = 0x18274, 4939 .halt_check = BRANCH_HALT_VOTED, 4940 .clkr = { 4941 .enable_reg = 0x52008, 4942 .enable_mask = BIT(23), 4943 .hw.init = &(const struct clk_init_data) { 4944 .name = "gcc_qupv3_wrap1_s1_clk", 4945 .parent_hws = (const struct clk_hw*[]){ 4946 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 4947 }, 4948 .num_parents = 1, 4949 .flags = CLK_SET_RATE_PARENT, 4950 .ops = &clk_branch2_ops, 4951 }, 4952 }, 4953 }; 4954 4955 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 4956 .halt_reg = 0x183a4, 4957 .halt_check = BRANCH_HALT_VOTED, 4958 .clkr = { 4959 .enable_reg = 0x52008, 4960 .enable_mask = BIT(24), 4961 .hw.init = &(const struct clk_init_data) { 4962 .name = "gcc_qupv3_wrap1_s2_clk", 4963 .parent_hws = (const struct clk_hw*[]){ 4964 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 4965 }, 4966 .num_parents = 1, 4967 .flags = CLK_SET_RATE_PARENT, 4968 .ops = &clk_branch2_ops, 4969 }, 4970 }, 4971 }; 4972 4973 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 4974 .halt_reg = 0x184d4, 4975 .halt_check = BRANCH_HALT_VOTED, 4976 .clkr = { 4977 .enable_reg = 0x52008, 4978 .enable_mask = BIT(25), 4979 .hw.init = &(const struct clk_init_data) { 4980 .name = "gcc_qupv3_wrap1_s3_clk", 4981 .parent_hws = (const struct clk_hw*[]){ 4982 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 4983 }, 4984 .num_parents = 1, 4985 .flags = CLK_SET_RATE_PARENT, 4986 .ops = &clk_branch2_ops, 4987 }, 4988 }, 4989 }; 4990 4991 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 4992 .halt_reg = 0x18604, 4993 .halt_check = BRANCH_HALT_VOTED, 4994 .clkr = { 4995 .enable_reg = 0x52008, 4996 .enable_mask = BIT(26), 4997 .hw.init = &(const struct clk_init_data) { 4998 .name = "gcc_qupv3_wrap1_s4_clk", 4999 .parent_hws = (const struct clk_hw*[]){ 5000 &gcc_qupv3_wrap1_s4_div_clk_src.clkr.hw, 5001 }, 5002 .num_parents = 1, 5003 .flags = CLK_SET_RATE_PARENT, 5004 .ops = &clk_branch2_ops, 5005 }, 5006 }, 5007 }; 5008 5009 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 5010 .halt_reg = 0x18734, 5011 .halt_check = BRANCH_HALT_VOTED, 5012 .clkr = { 5013 .enable_reg = 0x52008, 5014 .enable_mask = BIT(27), 5015 .hw.init = &(const struct clk_init_data) { 5016 .name = "gcc_qupv3_wrap1_s5_clk", 5017 .parent_hws = (const struct clk_hw*[]){ 5018 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 5019 }, 5020 .num_parents = 1, 5021 .flags = CLK_SET_RATE_PARENT, 5022 .ops = &clk_branch2_ops, 5023 }, 5024 }, 5025 }; 5026 5027 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 5028 .halt_reg = 0x18864, 5029 .halt_check = BRANCH_HALT_VOTED, 5030 .clkr = { 5031 .enable_reg = 0x52018, 5032 .enable_mask = BIT(27), 5033 .hw.init = &(const struct clk_init_data) { 5034 .name = "gcc_qupv3_wrap1_s6_clk", 5035 .parent_hws = (const struct clk_hw*[]){ 5036 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 5037 }, 5038 .num_parents = 1, 5039 .flags = CLK_SET_RATE_PARENT, 5040 .ops = &clk_branch2_ops, 5041 }, 5042 }, 5043 }; 5044 5045 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 5046 .halt_reg = 0x18994, 5047 .halt_check = BRANCH_HALT_VOTED, 5048 .clkr = { 5049 .enable_reg = 0x52018, 5050 .enable_mask = BIT(28), 5051 .hw.init = &(const struct clk_init_data) { 5052 .name = "gcc_qupv3_wrap1_s7_clk", 5053 .parent_hws = (const struct clk_hw*[]){ 5054 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 5055 }, 5056 .num_parents = 1, 5057 .flags = CLK_SET_RATE_PARENT, 5058 .ops = &clk_branch2_ops, 5059 }, 5060 }, 5061 }; 5062 5063 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 5064 .halt_reg = 0x1e014, 5065 .halt_check = BRANCH_HALT_VOTED, 5066 .clkr = { 5067 .enable_reg = 0x52010, 5068 .enable_mask = BIT(3), 5069 .hw.init = &(const struct clk_init_data) { 5070 .name = "gcc_qupv3_wrap2_core_2x_clk", 5071 .ops = &clk_branch2_ops, 5072 }, 5073 }, 5074 }; 5075 5076 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 5077 .halt_reg = 0x1e00c, 5078 .halt_check = BRANCH_HALT_VOTED, 5079 .clkr = { 5080 .enable_reg = 0x52010, 5081 .enable_mask = BIT(0), 5082 .hw.init = &(const struct clk_init_data) { 5083 .name = "gcc_qupv3_wrap2_core_clk", 5084 .ops = &clk_branch2_ops, 5085 }, 5086 }, 5087 }; 5088 5089 static struct clk_branch gcc_qupv3_wrap2_qspi0_clk = { 5090 .halt_reg = 0x1eac4, 5091 .halt_check = BRANCH_HALT_VOTED, 5092 .clkr = { 5093 .enable_reg = 0x52020, 5094 .enable_mask = BIT(4), 5095 .hw.init = &(const struct clk_init_data) { 5096 .name = "gcc_qupv3_wrap2_qspi0_clk", 5097 .parent_hws = (const struct clk_hw*[]){ 5098 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 5099 }, 5100 .num_parents = 1, 5101 .flags = CLK_SET_RATE_PARENT, 5102 .ops = &clk_branch2_ops, 5103 }, 5104 }, 5105 }; 5106 5107 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 5108 .halt_reg = 0x1e144, 5109 .halt_check = BRANCH_HALT_VOTED, 5110 .clkr = { 5111 .enable_reg = 0x52010, 5112 .enable_mask = BIT(4), 5113 .hw.init = &(const struct clk_init_data) { 5114 .name = "gcc_qupv3_wrap2_s0_clk", 5115 .parent_hws = (const struct clk_hw*[]){ 5116 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 5117 }, 5118 .num_parents = 1, 5119 .flags = CLK_SET_RATE_PARENT, 5120 .ops = &clk_branch2_ops, 5121 }, 5122 }, 5123 }; 5124 5125 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 5126 .halt_reg = 0x1e274, 5127 .halt_check = BRANCH_HALT_VOTED, 5128 .clkr = { 5129 .enable_reg = 0x52010, 5130 .enable_mask = BIT(5), 5131 .hw.init = &(const struct clk_init_data) { 5132 .name = "gcc_qupv3_wrap2_s1_clk", 5133 .parent_hws = (const struct clk_hw*[]){ 5134 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 5135 }, 5136 .num_parents = 1, 5137 .flags = CLK_SET_RATE_PARENT, 5138 .ops = &clk_branch2_ops, 5139 }, 5140 }, 5141 }; 5142 5143 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 5144 .halt_reg = 0x1e3a4, 5145 .halt_check = BRANCH_HALT_VOTED, 5146 .clkr = { 5147 .enable_reg = 0x52010, 5148 .enable_mask = BIT(6), 5149 .hw.init = &(const struct clk_init_data) { 5150 .name = "gcc_qupv3_wrap2_s2_clk", 5151 .parent_hws = (const struct clk_hw*[]){ 5152 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 5153 }, 5154 .num_parents = 1, 5155 .flags = CLK_SET_RATE_PARENT, 5156 .ops = &clk_branch2_ops, 5157 }, 5158 }, 5159 }; 5160 5161 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 5162 .halt_reg = 0x1e4d4, 5163 .halt_check = BRANCH_HALT_VOTED, 5164 .clkr = { 5165 .enable_reg = 0x52010, 5166 .enable_mask = BIT(7), 5167 .hw.init = &(const struct clk_init_data) { 5168 .name = "gcc_qupv3_wrap2_s3_clk", 5169 .parent_hws = (const struct clk_hw*[]){ 5170 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 5171 }, 5172 .num_parents = 1, 5173 .flags = CLK_SET_RATE_PARENT, 5174 .ops = &clk_branch2_ops, 5175 }, 5176 }, 5177 }; 5178 5179 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 5180 .halt_reg = 0x1e604, 5181 .halt_check = BRANCH_HALT_VOTED, 5182 .clkr = { 5183 .enable_reg = 0x52010, 5184 .enable_mask = BIT(8), 5185 .hw.init = &(const struct clk_init_data) { 5186 .name = "gcc_qupv3_wrap2_s4_clk", 5187 .parent_hws = (const struct clk_hw*[]){ 5188 &gcc_qupv3_wrap2_s4_div_clk_src.clkr.hw, 5189 }, 5190 .num_parents = 1, 5191 .flags = CLK_SET_RATE_PARENT, 5192 .ops = &clk_branch2_ops, 5193 }, 5194 }, 5195 }; 5196 5197 static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 5198 .halt_reg = 0x1e734, 5199 .halt_check = BRANCH_HALT_VOTED, 5200 .clkr = { 5201 .enable_reg = 0x52010, 5202 .enable_mask = BIT(9), 5203 .hw.init = &(const struct clk_init_data) { 5204 .name = "gcc_qupv3_wrap2_s5_clk", 5205 .parent_hws = (const struct clk_hw*[]){ 5206 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 5207 }, 5208 .num_parents = 1, 5209 .flags = CLK_SET_RATE_PARENT, 5210 .ops = &clk_branch2_ops, 5211 }, 5212 }, 5213 }; 5214 5215 static struct clk_branch gcc_qupv3_wrap2_s6_clk = { 5216 .halt_reg = 0x1e864, 5217 .halt_check = BRANCH_HALT_VOTED, 5218 .clkr = { 5219 .enable_reg = 0x52018, 5220 .enable_mask = BIT(29), 5221 .hw.init = &(const struct clk_init_data) { 5222 .name = "gcc_qupv3_wrap2_s6_clk", 5223 .parent_hws = (const struct clk_hw*[]){ 5224 &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, 5225 }, 5226 .num_parents = 1, 5227 .flags = CLK_SET_RATE_PARENT, 5228 .ops = &clk_branch2_ops, 5229 }, 5230 }, 5231 }; 5232 5233 static struct clk_branch gcc_qupv3_wrap2_s7_clk = { 5234 .halt_reg = 0x1e994, 5235 .halt_check = BRANCH_HALT_VOTED, 5236 .clkr = { 5237 .enable_reg = 0x52018, 5238 .enable_mask = BIT(30), 5239 .hw.init = &(const struct clk_init_data) { 5240 .name = "gcc_qupv3_wrap2_s7_clk", 5241 .parent_hws = (const struct clk_hw*[]){ 5242 &gcc_qupv3_wrap2_s7_clk_src.clkr.hw, 5243 }, 5244 .num_parents = 1, 5245 .flags = CLK_SET_RATE_PARENT, 5246 .ops = &clk_branch2_ops, 5247 }, 5248 }, 5249 }; 5250 5251 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 5252 .halt_reg = 0x17004, 5253 .halt_check = BRANCH_HALT_VOTED, 5254 .hwcg_reg = 0x17004, 5255 .hwcg_bit = 1, 5256 .clkr = { 5257 .enable_reg = 0x52008, 5258 .enable_mask = BIT(6), 5259 .hw.init = &(const struct clk_init_data) { 5260 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 5261 .ops = &clk_branch2_ops, 5262 }, 5263 }, 5264 }; 5265 5266 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 5267 .halt_reg = 0x17008, 5268 .halt_check = BRANCH_HALT_VOTED, 5269 .hwcg_reg = 0x17008, 5270 .hwcg_bit = 1, 5271 .clkr = { 5272 .enable_reg = 0x52008, 5273 .enable_mask = BIT(7), 5274 .hw.init = &(const struct clk_init_data) { 5275 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 5276 .ops = &clk_branch2_ops, 5277 }, 5278 }, 5279 }; 5280 5281 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 5282 .halt_reg = 0x18004, 5283 .halt_check = BRANCH_HALT_VOTED, 5284 .hwcg_reg = 0x18004, 5285 .hwcg_bit = 1, 5286 .clkr = { 5287 .enable_reg = 0x52008, 5288 .enable_mask = BIT(20), 5289 .hw.init = &(const struct clk_init_data) { 5290 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 5291 .ops = &clk_branch2_ops, 5292 }, 5293 }, 5294 }; 5295 5296 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 5297 .halt_reg = 0x18008, 5298 .halt_check = BRANCH_HALT_VOTED, 5299 .hwcg_reg = 0x18008, 5300 .hwcg_bit = 1, 5301 .clkr = { 5302 .enable_reg = 0x52008, 5303 .enable_mask = BIT(21), 5304 .hw.init = &(const struct clk_init_data) { 5305 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 5306 .ops = &clk_branch2_ops, 5307 }, 5308 }, 5309 }; 5310 5311 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 5312 .halt_reg = 0x1e004, 5313 .halt_check = BRANCH_HALT_VOTED, 5314 .hwcg_reg = 0x1e004, 5315 .hwcg_bit = 1, 5316 .clkr = { 5317 .enable_reg = 0x52010, 5318 .enable_mask = BIT(2), 5319 .hw.init = &(const struct clk_init_data) { 5320 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 5321 .ops = &clk_branch2_ops, 5322 }, 5323 }, 5324 }; 5325 5326 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 5327 .halt_reg = 0x1e008, 5328 .halt_check = BRANCH_HALT_VOTED, 5329 .hwcg_reg = 0x1e008, 5330 .hwcg_bit = 1, 5331 .clkr = { 5332 .enable_reg = 0x52010, 5333 .enable_mask = BIT(1), 5334 .hw.init = &(const struct clk_init_data) { 5335 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 5336 .ops = &clk_branch2_ops, 5337 }, 5338 }, 5339 }; 5340 5341 static struct clk_branch gcc_sdcc2_ahb_clk = { 5342 .halt_reg = 0x14008, 5343 .halt_check = BRANCH_HALT, 5344 .clkr = { 5345 .enable_reg = 0x14008, 5346 .enable_mask = BIT(0), 5347 .hw.init = &(const struct clk_init_data) { 5348 .name = "gcc_sdcc2_ahb_clk", 5349 .ops = &clk_branch2_ops, 5350 }, 5351 }, 5352 }; 5353 5354 static struct clk_branch gcc_sdcc2_apps_clk = { 5355 .halt_reg = 0x14004, 5356 .halt_check = BRANCH_HALT, 5357 .clkr = { 5358 .enable_reg = 0x14004, 5359 .enable_mask = BIT(0), 5360 .hw.init = &(const struct clk_init_data) { 5361 .name = "gcc_sdcc2_apps_clk", 5362 .parent_hws = (const struct clk_hw*[]){ 5363 &gcc_sdcc2_apps_clk_src.clkr.hw, 5364 }, 5365 .num_parents = 1, 5366 .flags = CLK_SET_RATE_PARENT, 5367 .ops = &clk_branch2_ops, 5368 }, 5369 }, 5370 }; 5371 5372 static struct clk_branch gcc_sdcc4_ahb_clk = { 5373 .halt_reg = 0x16008, 5374 .halt_check = BRANCH_HALT, 5375 .clkr = { 5376 .enable_reg = 0x16008, 5377 .enable_mask = BIT(0), 5378 .hw.init = &(const struct clk_init_data) { 5379 .name = "gcc_sdcc4_ahb_clk", 5380 .ops = &clk_branch2_ops, 5381 }, 5382 }, 5383 }; 5384 5385 static struct clk_branch gcc_sdcc4_apps_clk = { 5386 .halt_reg = 0x16004, 5387 .halt_check = BRANCH_HALT, 5388 .clkr = { 5389 .enable_reg = 0x16004, 5390 .enable_mask = BIT(0), 5391 .hw.init = &(const struct clk_init_data) { 5392 .name = "gcc_sdcc4_apps_clk", 5393 .parent_hws = (const struct clk_hw*[]){ 5394 &gcc_sdcc4_apps_clk_src.clkr.hw, 5395 }, 5396 .num_parents = 1, 5397 .flags = CLK_SET_RATE_PARENT, 5398 .ops = &clk_branch2_ops, 5399 }, 5400 }, 5401 }; 5402 5403 static struct clk_branch gcc_sys_noc_usb_axi_clk = { 5404 .halt_reg = 0x5d000, 5405 .halt_check = BRANCH_HALT_VOTED, 5406 .hwcg_reg = 0x5d000, 5407 .hwcg_bit = 1, 5408 .clkr = { 5409 .enable_reg = 0x5d000, 5410 .enable_mask = BIT(0), 5411 .hw.init = &(const struct clk_init_data) { 5412 .name = "gcc_sys_noc_usb_axi_clk", 5413 .ops = &clk_branch2_ops, 5414 }, 5415 }, 5416 }; 5417 5418 static struct clk_branch gcc_ufs_1_card_clkref_clk = { 5419 .halt_reg = 0x8c000, 5420 .halt_check = BRANCH_HALT, 5421 .clkr = { 5422 .enable_reg = 0x8c000, 5423 .enable_mask = BIT(0), 5424 .hw.init = &(const struct clk_init_data) { 5425 .name = "gcc_ufs_1_card_clkref_clk", 5426 .ops = &clk_branch2_ops, 5427 }, 5428 }, 5429 }; 5430 5431 static struct clk_branch gcc_ufs_card_ahb_clk = { 5432 .halt_reg = 0x75018, 5433 .halt_check = BRANCH_HALT_VOTED, 5434 .hwcg_reg = 0x75018, 5435 .hwcg_bit = 1, 5436 .clkr = { 5437 .enable_reg = 0x75018, 5438 .enable_mask = BIT(0), 5439 .hw.init = &(const struct clk_init_data) { 5440 .name = "gcc_ufs_card_ahb_clk", 5441 .ops = &clk_branch2_ops, 5442 }, 5443 }, 5444 }; 5445 5446 static struct clk_branch gcc_ufs_card_axi_clk = { 5447 .halt_reg = 0x75010, 5448 .halt_check = BRANCH_HALT_VOTED, 5449 .hwcg_reg = 0x75010, 5450 .hwcg_bit = 1, 5451 .clkr = { 5452 .enable_reg = 0x75010, 5453 .enable_mask = BIT(0), 5454 .hw.init = &(const struct clk_init_data) { 5455 .name = "gcc_ufs_card_axi_clk", 5456 .parent_hws = (const struct clk_hw*[]){ 5457 &gcc_ufs_card_axi_clk_src.clkr.hw, 5458 }, 5459 .num_parents = 1, 5460 .flags = CLK_SET_RATE_PARENT, 5461 .ops = &clk_branch2_ops, 5462 }, 5463 }, 5464 }; 5465 5466 static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = { 5467 .halt_reg = 0x75010, 5468 .halt_check = BRANCH_HALT_VOTED, 5469 .hwcg_reg = 0x75010, 5470 .hwcg_bit = 1, 5471 .clkr = { 5472 .enable_reg = 0x75010, 5473 .enable_mask = BIT(1), 5474 .hw.init = &(const struct clk_init_data) { 5475 .name = "gcc_ufs_card_axi_hw_ctl_clk", 5476 .parent_hws = (const struct clk_hw*[]){ 5477 &gcc_ufs_card_axi_clk_src.clkr.hw, 5478 }, 5479 .num_parents = 1, 5480 .flags = CLK_SET_RATE_PARENT, 5481 .ops = &clk_branch2_ops, 5482 }, 5483 }, 5484 }; 5485 5486 static struct clk_branch gcc_ufs_card_clkref_clk = { 5487 .halt_reg = 0x8c054, 5488 .halt_check = BRANCH_HALT, 5489 .clkr = { 5490 .enable_reg = 0x8c054, 5491 .enable_mask = BIT(0), 5492 .hw.init = &(const struct clk_init_data) { 5493 .name = "gcc_ufs_card_clkref_clk", 5494 .ops = &clk_branch2_ops, 5495 }, 5496 }, 5497 }; 5498 5499 static struct clk_branch gcc_ufs_card_ice_core_clk = { 5500 .halt_reg = 0x75064, 5501 .halt_check = BRANCH_HALT_VOTED, 5502 .hwcg_reg = 0x75064, 5503 .hwcg_bit = 1, 5504 .clkr = { 5505 .enable_reg = 0x75064, 5506 .enable_mask = BIT(0), 5507 .hw.init = &(const struct clk_init_data) { 5508 .name = "gcc_ufs_card_ice_core_clk", 5509 .parent_hws = (const struct clk_hw*[]){ 5510 &gcc_ufs_card_ice_core_clk_src.clkr.hw, 5511 }, 5512 .num_parents = 1, 5513 .flags = CLK_SET_RATE_PARENT, 5514 .ops = &clk_branch2_ops, 5515 }, 5516 }, 5517 }; 5518 5519 static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = { 5520 .halt_reg = 0x75064, 5521 .halt_check = BRANCH_HALT_VOTED, 5522 .hwcg_reg = 0x75064, 5523 .hwcg_bit = 1, 5524 .clkr = { 5525 .enable_reg = 0x75064, 5526 .enable_mask = BIT(1), 5527 .hw.init = &(const struct clk_init_data) { 5528 .name = "gcc_ufs_card_ice_core_hw_ctl_clk", 5529 .parent_hws = (const struct clk_hw*[]){ 5530 &gcc_ufs_card_ice_core_clk_src.clkr.hw, 5531 }, 5532 .num_parents = 1, 5533 .flags = CLK_SET_RATE_PARENT, 5534 .ops = &clk_branch2_ops, 5535 }, 5536 }, 5537 }; 5538 5539 static struct clk_branch gcc_ufs_card_phy_aux_clk = { 5540 .halt_reg = 0x7509c, 5541 .halt_check = BRANCH_HALT_VOTED, 5542 .hwcg_reg = 0x7509c, 5543 .hwcg_bit = 1, 5544 .clkr = { 5545 .enable_reg = 0x7509c, 5546 .enable_mask = BIT(0), 5547 .hw.init = &(const struct clk_init_data) { 5548 .name = "gcc_ufs_card_phy_aux_clk", 5549 .parent_hws = (const struct clk_hw*[]){ 5550 &gcc_ufs_card_phy_aux_clk_src.clkr.hw, 5551 }, 5552 .num_parents = 1, 5553 .flags = CLK_SET_RATE_PARENT, 5554 .ops = &clk_branch2_ops, 5555 }, 5556 }, 5557 }; 5558 5559 static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { 5560 .halt_reg = 0x7509c, 5561 .halt_check = BRANCH_HALT_VOTED, 5562 .hwcg_reg = 0x7509c, 5563 .hwcg_bit = 1, 5564 .clkr = { 5565 .enable_reg = 0x7509c, 5566 .enable_mask = BIT(1), 5567 .hw.init = &(const struct clk_init_data) { 5568 .name = "gcc_ufs_card_phy_aux_hw_ctl_clk", 5569 .parent_hws = (const struct clk_hw*[]){ 5570 &gcc_ufs_card_phy_aux_clk_src.clkr.hw, 5571 }, 5572 .num_parents = 1, 5573 .flags = CLK_SET_RATE_PARENT, 5574 .ops = &clk_branch2_ops, 5575 }, 5576 }, 5577 }; 5578 5579 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { 5580 .halt_reg = 0x75020, 5581 .halt_check = BRANCH_HALT_DELAY, 5582 .clkr = { 5583 .enable_reg = 0x75020, 5584 .enable_mask = BIT(0), 5585 .hw.init = &(const struct clk_init_data) { 5586 .name = "gcc_ufs_card_rx_symbol_0_clk", 5587 .parent_hws = (const struct clk_hw*[]){ 5588 &gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw, 5589 }, 5590 .num_parents = 1, 5591 .flags = CLK_SET_RATE_PARENT, 5592 .ops = &clk_branch2_ops, 5593 }, 5594 }, 5595 }; 5596 5597 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { 5598 .halt_reg = 0x750b8, 5599 .halt_check = BRANCH_HALT_DELAY, 5600 .clkr = { 5601 .enable_reg = 0x750b8, 5602 .enable_mask = BIT(0), 5603 .hw.init = &(const struct clk_init_data) { 5604 .name = "gcc_ufs_card_rx_symbol_1_clk", 5605 .parent_hws = (const struct clk_hw*[]){ 5606 &gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw, 5607 }, 5608 .num_parents = 1, 5609 .flags = CLK_SET_RATE_PARENT, 5610 .ops = &clk_branch2_ops, 5611 }, 5612 }, 5613 }; 5614 5615 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { 5616 .halt_reg = 0x7501c, 5617 .halt_check = BRANCH_HALT_DELAY, 5618 .clkr = { 5619 .enable_reg = 0x7501c, 5620 .enable_mask = BIT(0), 5621 .hw.init = &(const struct clk_init_data) { 5622 .name = "gcc_ufs_card_tx_symbol_0_clk", 5623 .parent_hws = (const struct clk_hw*[]){ 5624 &gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw, 5625 }, 5626 .num_parents = 1, 5627 .flags = CLK_SET_RATE_PARENT, 5628 .ops = &clk_branch2_ops, 5629 }, 5630 }, 5631 }; 5632 5633 static struct clk_branch gcc_ufs_card_unipro_core_clk = { 5634 .halt_reg = 0x7505c, 5635 .halt_check = BRANCH_HALT_VOTED, 5636 .hwcg_reg = 0x7505c, 5637 .hwcg_bit = 1, 5638 .clkr = { 5639 .enable_reg = 0x7505c, 5640 .enable_mask = BIT(0), 5641 .hw.init = &(const struct clk_init_data) { 5642 .name = "gcc_ufs_card_unipro_core_clk", 5643 .parent_hws = (const struct clk_hw*[]){ 5644 &gcc_ufs_card_unipro_core_clk_src.clkr.hw, 5645 }, 5646 .num_parents = 1, 5647 .flags = CLK_SET_RATE_PARENT, 5648 .ops = &clk_branch2_ops, 5649 }, 5650 }, 5651 }; 5652 5653 static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { 5654 .halt_reg = 0x7505c, 5655 .halt_check = BRANCH_HALT_VOTED, 5656 .hwcg_reg = 0x7505c, 5657 .hwcg_bit = 1, 5658 .clkr = { 5659 .enable_reg = 0x7505c, 5660 .enable_mask = BIT(1), 5661 .hw.init = &(const struct clk_init_data) { 5662 .name = "gcc_ufs_card_unipro_core_hw_ctl_clk", 5663 .parent_hws = (const struct clk_hw*[]){ 5664 &gcc_ufs_card_unipro_core_clk_src.clkr.hw, 5665 }, 5666 .num_parents = 1, 5667 .flags = CLK_SET_RATE_PARENT, 5668 .ops = &clk_branch2_ops, 5669 }, 5670 }, 5671 }; 5672 5673 static struct clk_branch gcc_ufs_phy_ahb_clk = { 5674 .halt_reg = 0x77018, 5675 .halt_check = BRANCH_HALT_VOTED, 5676 .hwcg_reg = 0x77018, 5677 .hwcg_bit = 1, 5678 .clkr = { 5679 .enable_reg = 0x77018, 5680 .enable_mask = BIT(0), 5681 .hw.init = &(const struct clk_init_data) { 5682 .name = "gcc_ufs_phy_ahb_clk", 5683 .ops = &clk_branch2_ops, 5684 }, 5685 }, 5686 }; 5687 5688 static struct clk_branch gcc_ufs_phy_axi_clk = { 5689 .halt_reg = 0x77010, 5690 .halt_check = BRANCH_HALT_VOTED, 5691 .hwcg_reg = 0x77010, 5692 .hwcg_bit = 1, 5693 .clkr = { 5694 .enable_reg = 0x77010, 5695 .enable_mask = BIT(0), 5696 .hw.init = &(const struct clk_init_data) { 5697 .name = "gcc_ufs_phy_axi_clk", 5698 .parent_hws = (const struct clk_hw*[]){ 5699 &gcc_ufs_phy_axi_clk_src.clkr.hw, 5700 }, 5701 .num_parents = 1, 5702 .flags = CLK_SET_RATE_PARENT, 5703 .ops = &clk_branch2_ops, 5704 }, 5705 }, 5706 }; 5707 5708 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { 5709 .halt_reg = 0x77010, 5710 .halt_check = BRANCH_HALT_VOTED, 5711 .hwcg_reg = 0x77010, 5712 .hwcg_bit = 1, 5713 .clkr = { 5714 .enable_reg = 0x77010, 5715 .enable_mask = BIT(1), 5716 .hw.init = &(const struct clk_init_data) { 5717 .name = "gcc_ufs_phy_axi_hw_ctl_clk", 5718 .parent_hws = (const struct clk_hw*[]){ 5719 &gcc_ufs_phy_axi_clk_src.clkr.hw, 5720 }, 5721 .num_parents = 1, 5722 .flags = CLK_SET_RATE_PARENT, 5723 .ops = &clk_branch2_ops, 5724 }, 5725 }, 5726 }; 5727 5728 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 5729 .halt_reg = 0x77064, 5730 .halt_check = BRANCH_HALT_VOTED, 5731 .hwcg_reg = 0x77064, 5732 .hwcg_bit = 1, 5733 .clkr = { 5734 .enable_reg = 0x77064, 5735 .enable_mask = BIT(0), 5736 .hw.init = &(const struct clk_init_data) { 5737 .name = "gcc_ufs_phy_ice_core_clk", 5738 .parent_hws = (const struct clk_hw*[]){ 5739 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 5740 }, 5741 .num_parents = 1, 5742 .flags = CLK_SET_RATE_PARENT, 5743 .ops = &clk_branch2_ops, 5744 }, 5745 }, 5746 }; 5747 5748 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { 5749 .halt_reg = 0x77064, 5750 .halt_check = BRANCH_HALT_VOTED, 5751 .hwcg_reg = 0x77064, 5752 .hwcg_bit = 1, 5753 .clkr = { 5754 .enable_reg = 0x77064, 5755 .enable_mask = BIT(1), 5756 .hw.init = &(const struct clk_init_data) { 5757 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", 5758 .parent_hws = (const struct clk_hw*[]){ 5759 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 5760 }, 5761 .num_parents = 1, 5762 .flags = CLK_SET_RATE_PARENT, 5763 .ops = &clk_branch2_ops, 5764 }, 5765 }, 5766 }; 5767 5768 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 5769 .halt_reg = 0x7709c, 5770 .halt_check = BRANCH_HALT_VOTED, 5771 .hwcg_reg = 0x7709c, 5772 .hwcg_bit = 1, 5773 .clkr = { 5774 .enable_reg = 0x7709c, 5775 .enable_mask = BIT(0), 5776 .hw.init = &(const struct clk_init_data) { 5777 .name = "gcc_ufs_phy_phy_aux_clk", 5778 .parent_hws = (const struct clk_hw*[]){ 5779 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 5780 }, 5781 .num_parents = 1, 5782 .flags = CLK_SET_RATE_PARENT, 5783 .ops = &clk_branch2_ops, 5784 }, 5785 }, 5786 }; 5787 5788 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { 5789 .halt_reg = 0x7709c, 5790 .halt_check = BRANCH_HALT_VOTED, 5791 .hwcg_reg = 0x7709c, 5792 .hwcg_bit = 1, 5793 .clkr = { 5794 .enable_reg = 0x7709c, 5795 .enable_mask = BIT(1), 5796 .hw.init = &(const struct clk_init_data) { 5797 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", 5798 .parent_hws = (const struct clk_hw*[]){ 5799 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 5800 }, 5801 .num_parents = 1, 5802 .flags = CLK_SET_RATE_PARENT, 5803 .ops = &clk_branch2_ops, 5804 }, 5805 }, 5806 }; 5807 5808 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 5809 .halt_reg = 0x77020, 5810 .halt_check = BRANCH_HALT_DELAY, 5811 .clkr = { 5812 .enable_reg = 0x77020, 5813 .enable_mask = BIT(0), 5814 .hw.init = &(const struct clk_init_data) { 5815 .name = "gcc_ufs_phy_rx_symbol_0_clk", 5816 .parent_hws = (const struct clk_hw*[]){ 5817 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 5818 }, 5819 .num_parents = 1, 5820 .flags = CLK_SET_RATE_PARENT, 5821 .ops = &clk_branch2_ops, 5822 }, 5823 }, 5824 }; 5825 5826 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 5827 .halt_reg = 0x770b8, 5828 .halt_check = BRANCH_HALT_DELAY, 5829 .clkr = { 5830 .enable_reg = 0x770b8, 5831 .enable_mask = BIT(0), 5832 .hw.init = &(const struct clk_init_data) { 5833 .name = "gcc_ufs_phy_rx_symbol_1_clk", 5834 .parent_hws = (const struct clk_hw*[]){ 5835 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 5836 }, 5837 .num_parents = 1, 5838 .flags = CLK_SET_RATE_PARENT, 5839 .ops = &clk_branch2_ops, 5840 }, 5841 }, 5842 }; 5843 5844 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 5845 .halt_reg = 0x7701c, 5846 .halt_check = BRANCH_HALT_DELAY, 5847 .clkr = { 5848 .enable_reg = 0x7701c, 5849 .enable_mask = BIT(0), 5850 .hw.init = &(const struct clk_init_data) { 5851 .name = "gcc_ufs_phy_tx_symbol_0_clk", 5852 .parent_hws = (const struct clk_hw*[]){ 5853 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 5854 }, 5855 .num_parents = 1, 5856 .flags = CLK_SET_RATE_PARENT, 5857 .ops = &clk_branch2_ops, 5858 }, 5859 }, 5860 }; 5861 5862 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 5863 .halt_reg = 0x7705c, 5864 .halt_check = BRANCH_HALT_VOTED, 5865 .hwcg_reg = 0x7705c, 5866 .hwcg_bit = 1, 5867 .clkr = { 5868 .enable_reg = 0x7705c, 5869 .enable_mask = BIT(0), 5870 .hw.init = &(const struct clk_init_data) { 5871 .name = "gcc_ufs_phy_unipro_core_clk", 5872 .parent_hws = (const struct clk_hw*[]){ 5873 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 5874 }, 5875 .num_parents = 1, 5876 .flags = CLK_SET_RATE_PARENT, 5877 .ops = &clk_branch2_ops, 5878 }, 5879 }, 5880 }; 5881 5882 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { 5883 .halt_reg = 0x7705c, 5884 .halt_check = BRANCH_HALT_VOTED, 5885 .hwcg_reg = 0x7705c, 5886 .hwcg_bit = 1, 5887 .clkr = { 5888 .enable_reg = 0x7705c, 5889 .enable_mask = BIT(1), 5890 .hw.init = &(const struct clk_init_data) { 5891 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", 5892 .parent_hws = (const struct clk_hw*[]){ 5893 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 5894 }, 5895 .num_parents = 1, 5896 .flags = CLK_SET_RATE_PARENT, 5897 .ops = &clk_branch2_ops, 5898 }, 5899 }, 5900 }; 5901 5902 static struct clk_branch gcc_ufs_ref_clkref_clk = { 5903 .halt_reg = 0x8c058, 5904 .halt_check = BRANCH_HALT, 5905 .clkr = { 5906 .enable_reg = 0x8c058, 5907 .enable_mask = BIT(0), 5908 .hw.init = &(const struct clk_init_data) { 5909 .name = "gcc_ufs_ref_clkref_clk", 5910 .ops = &clk_branch2_ops, 5911 }, 5912 }, 5913 }; 5914 5915 static struct clk_branch gcc_usb2_hs0_clkref_clk = { 5916 .halt_reg = 0x8c044, 5917 .halt_check = BRANCH_HALT, 5918 .clkr = { 5919 .enable_reg = 0x8c044, 5920 .enable_mask = BIT(0), 5921 .hw.init = &(const struct clk_init_data) { 5922 .name = "gcc_usb2_hs0_clkref_clk", 5923 .ops = &clk_branch2_ops, 5924 }, 5925 }, 5926 }; 5927 5928 static struct clk_branch gcc_usb2_hs1_clkref_clk = { 5929 .halt_reg = 0x8c048, 5930 .halt_check = BRANCH_HALT, 5931 .clkr = { 5932 .enable_reg = 0x8c048, 5933 .enable_mask = BIT(0), 5934 .hw.init = &(const struct clk_init_data) { 5935 .name = "gcc_usb2_hs1_clkref_clk", 5936 .ops = &clk_branch2_ops, 5937 }, 5938 }, 5939 }; 5940 5941 static struct clk_branch gcc_usb2_hs2_clkref_clk = { 5942 .halt_reg = 0x8c04c, 5943 .halt_check = BRANCH_HALT, 5944 .clkr = { 5945 .enable_reg = 0x8c04c, 5946 .enable_mask = BIT(0), 5947 .hw.init = &(const struct clk_init_data) { 5948 .name = "gcc_usb2_hs2_clkref_clk", 5949 .ops = &clk_branch2_ops, 5950 }, 5951 }, 5952 }; 5953 5954 static struct clk_branch gcc_usb2_hs3_clkref_clk = { 5955 .halt_reg = 0x8c050, 5956 .halt_check = BRANCH_HALT, 5957 .clkr = { 5958 .enable_reg = 0x8c050, 5959 .enable_mask = BIT(0), 5960 .hw.init = &(const struct clk_init_data) { 5961 .name = "gcc_usb2_hs3_clkref_clk", 5962 .ops = &clk_branch2_ops, 5963 }, 5964 }, 5965 }; 5966 5967 static struct clk_branch gcc_usb30_mp_master_clk = { 5968 .halt_reg = 0xab010, 5969 .halt_check = BRANCH_HALT, 5970 .clkr = { 5971 .enable_reg = 0xab010, 5972 .enable_mask = BIT(0), 5973 .hw.init = &(const struct clk_init_data) { 5974 .name = "gcc_usb30_mp_master_clk", 5975 .parent_hws = (const struct clk_hw*[]){ 5976 &gcc_usb30_mp_master_clk_src.clkr.hw, 5977 }, 5978 .num_parents = 1, 5979 .flags = CLK_SET_RATE_PARENT, 5980 .ops = &clk_branch2_ops, 5981 }, 5982 }, 5983 }; 5984 5985 static struct clk_branch gcc_usb30_mp_mock_utmi_clk = { 5986 .halt_reg = 0xab01c, 5987 .halt_check = BRANCH_HALT, 5988 .clkr = { 5989 .enable_reg = 0xab01c, 5990 .enable_mask = BIT(0), 5991 .hw.init = &(const struct clk_init_data) { 5992 .name = "gcc_usb30_mp_mock_utmi_clk", 5993 .parent_hws = (const struct clk_hw*[]){ 5994 &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr.hw, 5995 }, 5996 .num_parents = 1, 5997 .flags = CLK_SET_RATE_PARENT, 5998 .ops = &clk_branch2_ops, 5999 }, 6000 }, 6001 }; 6002 6003 static struct clk_branch gcc_usb30_mp_sleep_clk = { 6004 .halt_reg = 0xab018, 6005 .halt_check = BRANCH_HALT, 6006 .clkr = { 6007 .enable_reg = 0xab018, 6008 .enable_mask = BIT(0), 6009 .hw.init = &(const struct clk_init_data) { 6010 .name = "gcc_usb30_mp_sleep_clk", 6011 .ops = &clk_branch2_ops, 6012 }, 6013 }, 6014 }; 6015 6016 static struct clk_branch gcc_usb30_prim_master_clk = { 6017 .halt_reg = 0xf010, 6018 .halt_check = BRANCH_HALT, 6019 .clkr = { 6020 .enable_reg = 0xf010, 6021 .enable_mask = BIT(0), 6022 .hw.init = &(const struct clk_init_data) { 6023 .name = "gcc_usb30_prim_master_clk", 6024 .parent_hws = (const struct clk_hw*[]){ 6025 &gcc_usb30_prim_master_clk_src.clkr.hw, 6026 }, 6027 .num_parents = 1, 6028 .flags = CLK_SET_RATE_PARENT, 6029 .ops = &clk_branch2_ops, 6030 }, 6031 }, 6032 }; 6033 6034 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 6035 .halt_reg = 0xf01c, 6036 .halt_check = BRANCH_HALT, 6037 .clkr = { 6038 .enable_reg = 0xf01c, 6039 .enable_mask = BIT(0), 6040 .hw.init = &(const struct clk_init_data) { 6041 .name = "gcc_usb30_prim_mock_utmi_clk", 6042 .parent_hws = (const struct clk_hw*[]){ 6043 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 6044 }, 6045 .num_parents = 1, 6046 .flags = CLK_SET_RATE_PARENT, 6047 .ops = &clk_branch2_ops, 6048 }, 6049 }, 6050 }; 6051 6052 static struct clk_branch gcc_usb30_prim_sleep_clk = { 6053 .halt_reg = 0xf018, 6054 .halt_check = BRANCH_HALT, 6055 .clkr = { 6056 .enable_reg = 0xf018, 6057 .enable_mask = BIT(0), 6058 .hw.init = &(const struct clk_init_data) { 6059 .name = "gcc_usb30_prim_sleep_clk", 6060 .ops = &clk_branch2_ops, 6061 }, 6062 }, 6063 }; 6064 6065 static struct clk_branch gcc_usb30_sec_master_clk = { 6066 .halt_reg = 0x10010, 6067 .halt_check = BRANCH_HALT, 6068 .clkr = { 6069 .enable_reg = 0x10010, 6070 .enable_mask = BIT(0), 6071 .hw.init = &(const struct clk_init_data) { 6072 .name = "gcc_usb30_sec_master_clk", 6073 .parent_hws = (const struct clk_hw*[]){ 6074 &gcc_usb30_sec_master_clk_src.clkr.hw, 6075 }, 6076 .num_parents = 1, 6077 .flags = CLK_SET_RATE_PARENT, 6078 .ops = &clk_branch2_ops, 6079 }, 6080 }, 6081 }; 6082 6083 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { 6084 .halt_reg = 0x1001c, 6085 .halt_check = BRANCH_HALT, 6086 .clkr = { 6087 .enable_reg = 0x1001c, 6088 .enable_mask = BIT(0), 6089 .hw.init = &(const struct clk_init_data) { 6090 .name = "gcc_usb30_sec_mock_utmi_clk", 6091 .parent_hws = (const struct clk_hw*[]){ 6092 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw, 6093 }, 6094 .num_parents = 1, 6095 .flags = CLK_SET_RATE_PARENT, 6096 .ops = &clk_branch2_ops, 6097 }, 6098 }, 6099 }; 6100 6101 static struct clk_branch gcc_usb30_sec_sleep_clk = { 6102 .halt_reg = 0x10018, 6103 .halt_check = BRANCH_HALT, 6104 .clkr = { 6105 .enable_reg = 0x10018, 6106 .enable_mask = BIT(0), 6107 .hw.init = &(const struct clk_init_data) { 6108 .name = "gcc_usb30_sec_sleep_clk", 6109 .ops = &clk_branch2_ops, 6110 }, 6111 }, 6112 }; 6113 6114 static struct clk_branch gcc_usb3_mp0_clkref_clk = { 6115 .halt_reg = 0x8c03c, 6116 .halt_check = BRANCH_HALT, 6117 .clkr = { 6118 .enable_reg = 0x8c03c, 6119 .enable_mask = BIT(0), 6120 .hw.init = &(const struct clk_init_data) { 6121 .name = "gcc_usb3_mp0_clkref_clk", 6122 .ops = &clk_branch2_ops, 6123 }, 6124 }, 6125 }; 6126 6127 static struct clk_branch gcc_usb3_mp1_clkref_clk = { 6128 .halt_reg = 0x8c040, 6129 .halt_check = BRANCH_HALT, 6130 .clkr = { 6131 .enable_reg = 0x8c040, 6132 .enable_mask = BIT(0), 6133 .hw.init = &(const struct clk_init_data) { 6134 .name = "gcc_usb3_mp1_clkref_clk", 6135 .ops = &clk_branch2_ops, 6136 }, 6137 }, 6138 }; 6139 6140 static struct clk_branch gcc_usb3_mp_phy_aux_clk = { 6141 .halt_reg = 0xab054, 6142 .halt_check = BRANCH_HALT, 6143 .clkr = { 6144 .enable_reg = 0xab054, 6145 .enable_mask = BIT(0), 6146 .hw.init = &(const struct clk_init_data) { 6147 .name = "gcc_usb3_mp_phy_aux_clk", 6148 .parent_hws = (const struct clk_hw*[]){ 6149 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw, 6150 }, 6151 .num_parents = 1, 6152 .flags = CLK_SET_RATE_PARENT, 6153 .ops = &clk_branch2_ops, 6154 }, 6155 }, 6156 }; 6157 6158 static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = { 6159 .halt_reg = 0xab058, 6160 .halt_check = BRANCH_HALT, 6161 .clkr = { 6162 .enable_reg = 0xab058, 6163 .enable_mask = BIT(0), 6164 .hw.init = &(const struct clk_init_data) { 6165 .name = "gcc_usb3_mp_phy_com_aux_clk", 6166 .parent_hws = (const struct clk_hw*[]){ 6167 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw, 6168 }, 6169 .num_parents = 1, 6170 .flags = CLK_SET_RATE_PARENT, 6171 .ops = &clk_branch2_ops, 6172 }, 6173 }, 6174 }; 6175 6176 static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = { 6177 .halt_reg = 0xab05c, 6178 .halt_check = BRANCH_HALT_DELAY, 6179 .clkr = { 6180 .enable_reg = 0xab05c, 6181 .enable_mask = BIT(0), 6182 .hw.init = &(const struct clk_init_data) { 6183 .name = "gcc_usb3_mp_phy_pipe_0_clk", 6184 .parent_hws = (const struct clk_hw*[]){ 6185 &gcc_usb3_mp_phy_pipe_0_clk_src.clkr.hw, 6186 }, 6187 .num_parents = 1, 6188 .flags = CLK_SET_RATE_PARENT, 6189 .ops = &clk_branch2_ops, 6190 }, 6191 }, 6192 }; 6193 6194 static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = { 6195 .halt_reg = 0xab064, 6196 .halt_check = BRANCH_HALT_DELAY, 6197 .clkr = { 6198 .enable_reg = 0xab064, 6199 .enable_mask = BIT(0), 6200 .hw.init = &(const struct clk_init_data) { 6201 .name = "gcc_usb3_mp_phy_pipe_1_clk", 6202 .parent_hws = (const struct clk_hw*[]){ 6203 &gcc_usb3_mp_phy_pipe_1_clk_src.clkr.hw, 6204 }, 6205 .num_parents = 1, 6206 .flags = CLK_SET_RATE_PARENT, 6207 .ops = &clk_branch2_ops, 6208 }, 6209 }, 6210 }; 6211 6212 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 6213 .halt_reg = 0xf054, 6214 .halt_check = BRANCH_HALT, 6215 .clkr = { 6216 .enable_reg = 0xf054, 6217 .enable_mask = BIT(0), 6218 .hw.init = &(const struct clk_init_data) { 6219 .name = "gcc_usb3_prim_phy_aux_clk", 6220 .parent_hws = (const struct clk_hw*[]){ 6221 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 6222 }, 6223 .num_parents = 1, 6224 .flags = CLK_SET_RATE_PARENT, 6225 .ops = &clk_branch2_ops, 6226 }, 6227 }, 6228 }; 6229 6230 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 6231 .halt_reg = 0xf058, 6232 .halt_check = BRANCH_HALT, 6233 .clkr = { 6234 .enable_reg = 0xf058, 6235 .enable_mask = BIT(0), 6236 .hw.init = &(const struct clk_init_data) { 6237 .name = "gcc_usb3_prim_phy_com_aux_clk", 6238 .parent_hws = (const struct clk_hw*[]){ 6239 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 6240 }, 6241 .num_parents = 1, 6242 .flags = CLK_SET_RATE_PARENT, 6243 .ops = &clk_branch2_ops, 6244 }, 6245 }, 6246 }; 6247 6248 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 6249 .halt_reg = 0xf05c, 6250 .halt_check = BRANCH_HALT_DELAY, 6251 .hwcg_reg = 0xf05c, 6252 .hwcg_bit = 1, 6253 .clkr = { 6254 .enable_reg = 0xf05c, 6255 .enable_mask = BIT(0), 6256 .hw.init = &(const struct clk_init_data) { 6257 .name = "gcc_usb3_prim_phy_pipe_clk", 6258 .parent_hws = (const struct clk_hw*[]){ 6259 &gcc_usb34_prim_phy_pipe_clk_src.clkr.hw, 6260 }, 6261 .num_parents = 1, 6262 .flags = CLK_SET_RATE_PARENT, 6263 .ops = &clk_branch2_ops, 6264 }, 6265 }, 6266 }; 6267 6268 static struct clk_branch gcc_usb3_sec_phy_aux_clk = { 6269 .halt_reg = 0x10054, 6270 .halt_check = BRANCH_HALT, 6271 .clkr = { 6272 .enable_reg = 0x10054, 6273 .enable_mask = BIT(0), 6274 .hw.init = &(const struct clk_init_data) { 6275 .name = "gcc_usb3_sec_phy_aux_clk", 6276 .parent_hws = (const struct clk_hw*[]){ 6277 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 6278 }, 6279 .num_parents = 1, 6280 .flags = CLK_SET_RATE_PARENT, 6281 .ops = &clk_branch2_ops, 6282 }, 6283 }, 6284 }; 6285 6286 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { 6287 .halt_reg = 0x10058, 6288 .halt_check = BRANCH_HALT, 6289 .clkr = { 6290 .enable_reg = 0x10058, 6291 .enable_mask = BIT(0), 6292 .hw.init = &(const struct clk_init_data) { 6293 .name = "gcc_usb3_sec_phy_com_aux_clk", 6294 .parent_hws = (const struct clk_hw*[]){ 6295 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 6296 }, 6297 .num_parents = 1, 6298 .flags = CLK_SET_RATE_PARENT, 6299 .ops = &clk_branch2_ops, 6300 }, 6301 }, 6302 }; 6303 6304 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { 6305 .halt_reg = 0x1005c, 6306 .halt_check = BRANCH_HALT_DELAY, 6307 .hwcg_reg = 0x1005c, 6308 .hwcg_bit = 1, 6309 .clkr = { 6310 .enable_reg = 0x1005c, 6311 .enable_mask = BIT(0), 6312 .hw.init = &(const struct clk_init_data) { 6313 .name = "gcc_usb3_sec_phy_pipe_clk", 6314 .parent_hws = (const struct clk_hw*[]){ 6315 &gcc_usb34_sec_phy_pipe_clk_src.clkr.hw, 6316 }, 6317 .num_parents = 1, 6318 .flags = CLK_SET_RATE_PARENT, 6319 .ops = &clk_branch2_ops, 6320 }, 6321 }, 6322 }; 6323 6324 static struct clk_branch gcc_usb4_1_cfg_ahb_clk = { 6325 .halt_reg = 0xb808c, 6326 .halt_check = BRANCH_HALT_VOTED, 6327 .hwcg_reg = 0xb808c, 6328 .hwcg_bit = 1, 6329 .clkr = { 6330 .enable_reg = 0xb808c, 6331 .enable_mask = BIT(0), 6332 .hw.init = &(const struct clk_init_data) { 6333 .name = "gcc_usb4_1_cfg_ahb_clk", 6334 .ops = &clk_branch2_ops, 6335 }, 6336 }, 6337 }; 6338 6339 static struct clk_branch gcc_usb4_1_dp_clk = { 6340 .halt_reg = 0xb8048, 6341 .halt_check = BRANCH_HALT, 6342 .clkr = { 6343 .enable_reg = 0xb8048, 6344 .enable_mask = BIT(0), 6345 .hw.init = &(const struct clk_init_data) { 6346 .name = "gcc_usb4_1_dp_clk", 6347 .parent_hws = (const struct clk_hw*[]){ 6348 &gcc_usb4_1_phy_dp_clk_src.clkr.hw, 6349 }, 6350 .num_parents = 1, 6351 .flags = CLK_SET_RATE_PARENT, 6352 .ops = &clk_branch2_ops, 6353 }, 6354 }, 6355 }; 6356 6357 static struct clk_branch gcc_usb4_1_master_clk = { 6358 .halt_reg = 0xb8010, 6359 .halt_check = BRANCH_HALT, 6360 .clkr = { 6361 .enable_reg = 0xb8010, 6362 .enable_mask = BIT(0), 6363 .hw.init = &(const struct clk_init_data) { 6364 .name = "gcc_usb4_1_master_clk", 6365 .parent_hws = (const struct clk_hw*[]){ 6366 &gcc_usb4_1_master_clk_src.clkr.hw, 6367 }, 6368 .num_parents = 1, 6369 .flags = CLK_SET_RATE_PARENT, 6370 .ops = &clk_branch2_ops, 6371 }, 6372 }, 6373 }; 6374 6375 static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = { 6376 .halt_reg = 0xb80b4, 6377 .halt_check = BRANCH_HALT_DELAY, 6378 .clkr = { 6379 .enable_reg = 0xb80b4, 6380 .enable_mask = BIT(0), 6381 .hw.init = &(const struct clk_init_data) { 6382 .name = "gcc_usb4_1_phy_p2rr2p_pipe_clk", 6383 .parent_hws = (const struct clk_hw*[]){ 6384 &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr.hw, 6385 }, 6386 .num_parents = 1, 6387 .flags = CLK_SET_RATE_PARENT, 6388 .ops = &clk_branch2_ops, 6389 }, 6390 }, 6391 }; 6392 6393 static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = { 6394 .halt_reg = 0xb8038, 6395 .halt_check = BRANCH_HALT_DELAY, 6396 .clkr = { 6397 .enable_reg = 0x52020, 6398 .enable_mask = BIT(19), 6399 .hw.init = &(const struct clk_init_data) { 6400 .name = "gcc_usb4_1_phy_pcie_pipe_clk", 6401 .parent_hws = (const struct clk_hw*[]){ 6402 &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw, 6403 }, 6404 .num_parents = 1, 6405 .flags = CLK_SET_RATE_PARENT, 6406 .ops = &clk_branch2_ops, 6407 }, 6408 }, 6409 }; 6410 6411 static struct clk_branch gcc_usb4_1_phy_rx0_clk = { 6412 .halt_reg = 0xb8094, 6413 .halt_check = BRANCH_HALT, 6414 .clkr = { 6415 .enable_reg = 0xb8094, 6416 .enable_mask = BIT(0), 6417 .hw.init = &(const struct clk_init_data) { 6418 .name = "gcc_usb4_1_phy_rx0_clk", 6419 .parent_hws = (const struct clk_hw*[]){ 6420 &gcc_usb4_1_phy_rx0_clk_src.clkr.hw, 6421 }, 6422 .num_parents = 1, 6423 .flags = CLK_SET_RATE_PARENT, 6424 .ops = &clk_branch2_ops, 6425 }, 6426 }, 6427 }; 6428 6429 static struct clk_branch gcc_usb4_1_phy_rx1_clk = { 6430 .halt_reg = 0xb80a0, 6431 .halt_check = BRANCH_HALT, 6432 .clkr = { 6433 .enable_reg = 0xb80a0, 6434 .enable_mask = BIT(0), 6435 .hw.init = &(const struct clk_init_data) { 6436 .name = "gcc_usb4_1_phy_rx1_clk", 6437 .parent_hws = (const struct clk_hw*[]){ 6438 &gcc_usb4_1_phy_rx1_clk_src.clkr.hw, 6439 }, 6440 .num_parents = 1, 6441 .flags = CLK_SET_RATE_PARENT, 6442 .ops = &clk_branch2_ops, 6443 }, 6444 }, 6445 }; 6446 6447 static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = { 6448 .halt_reg = 0xb8088, 6449 .halt_check = BRANCH_HALT_DELAY, 6450 .hwcg_reg = 0xb8088, 6451 .hwcg_bit = 1, 6452 .clkr = { 6453 .enable_reg = 0xb8088, 6454 .enable_mask = BIT(0), 6455 .hw.init = &(const struct clk_init_data) { 6456 .name = "gcc_usb4_1_phy_usb_pipe_clk", 6457 .parent_hws = (const struct clk_hw*[]){ 6458 &gcc_usb34_sec_phy_pipe_clk_src.clkr.hw, 6459 }, 6460 .num_parents = 1, 6461 .flags = CLK_SET_RATE_PARENT, 6462 .ops = &clk_branch2_ops, 6463 }, 6464 }, 6465 }; 6466 6467 static struct clk_branch gcc_usb4_1_sb_if_clk = { 6468 .halt_reg = 0xb8034, 6469 .halt_check = BRANCH_HALT, 6470 .clkr = { 6471 .enable_reg = 0xb8034, 6472 .enable_mask = BIT(0), 6473 .hw.init = &(const struct clk_init_data) { 6474 .name = "gcc_usb4_1_sb_if_clk", 6475 .parent_hws = (const struct clk_hw*[]){ 6476 &gcc_usb4_1_sb_if_clk_src.clkr.hw, 6477 }, 6478 .num_parents = 1, 6479 .flags = CLK_SET_RATE_PARENT, 6480 .ops = &clk_branch2_ops, 6481 }, 6482 }, 6483 }; 6484 6485 static struct clk_branch gcc_usb4_1_sys_clk = { 6486 .halt_reg = 0xb8040, 6487 .halt_check = BRANCH_HALT, 6488 .clkr = { 6489 .enable_reg = 0xb8040, 6490 .enable_mask = BIT(0), 6491 .hw.init = &(const struct clk_init_data) { 6492 .name = "gcc_usb4_1_sys_clk", 6493 .parent_hws = (const struct clk_hw*[]){ 6494 &gcc_usb4_1_phy_sys_clk_src.clkr.hw, 6495 }, 6496 .num_parents = 1, 6497 .flags = CLK_SET_RATE_PARENT, 6498 .ops = &clk_branch2_ops, 6499 }, 6500 }, 6501 }; 6502 6503 static struct clk_branch gcc_usb4_1_tmu_clk = { 6504 .halt_reg = 0xb806c, 6505 .halt_check = BRANCH_HALT_VOTED, 6506 .hwcg_reg = 0xb806c, 6507 .hwcg_bit = 1, 6508 .clkr = { 6509 .enable_reg = 0xb806c, 6510 .enable_mask = BIT(0), 6511 .hw.init = &(const struct clk_init_data) { 6512 .name = "gcc_usb4_1_tmu_clk", 6513 .parent_hws = (const struct clk_hw*[]){ 6514 &gcc_usb4_1_tmu_clk_src.clkr.hw, 6515 }, 6516 .num_parents = 1, 6517 .flags = CLK_SET_RATE_PARENT, 6518 .ops = &clk_branch2_ops, 6519 }, 6520 }, 6521 }; 6522 6523 static struct clk_branch gcc_usb4_cfg_ahb_clk = { 6524 .halt_reg = 0x2a08c, 6525 .halt_check = BRANCH_HALT_VOTED, 6526 .hwcg_reg = 0x2a08c, 6527 .hwcg_bit = 1, 6528 .clkr = { 6529 .enable_reg = 0x2a08c, 6530 .enable_mask = BIT(0), 6531 .hw.init = &(const struct clk_init_data) { 6532 .name = "gcc_usb4_cfg_ahb_clk", 6533 .ops = &clk_branch2_ops, 6534 }, 6535 }, 6536 }; 6537 6538 static struct clk_branch gcc_usb4_clkref_clk = { 6539 .halt_reg = 0x8c010, 6540 .halt_check = BRANCH_HALT, 6541 .clkr = { 6542 .enable_reg = 0x8c010, 6543 .enable_mask = BIT(0), 6544 .hw.init = &(const struct clk_init_data) { 6545 .name = "gcc_usb4_clkref_clk", 6546 .ops = &clk_branch2_ops, 6547 }, 6548 }, 6549 }; 6550 6551 static struct clk_branch gcc_usb4_dp_clk = { 6552 .halt_reg = 0x2a048, 6553 .halt_check = BRANCH_HALT, 6554 .clkr = { 6555 .enable_reg = 0x2a048, 6556 .enable_mask = BIT(0), 6557 .hw.init = &(const struct clk_init_data) { 6558 .name = "gcc_usb4_dp_clk", 6559 .parent_hws = (const struct clk_hw*[]){ 6560 &gcc_usb4_phy_dp_clk_src.clkr.hw, 6561 }, 6562 .num_parents = 1, 6563 .flags = CLK_SET_RATE_PARENT, 6564 .ops = &clk_branch2_ops, 6565 }, 6566 }, 6567 }; 6568 6569 static struct clk_branch gcc_usb4_eud_clkref_clk = { 6570 .halt_reg = 0x8c02c, 6571 .halt_check = BRANCH_HALT, 6572 .clkr = { 6573 .enable_reg = 0x8c02c, 6574 .enable_mask = BIT(0), 6575 .hw.init = &(const struct clk_init_data) { 6576 .name = "gcc_usb4_eud_clkref_clk", 6577 .ops = &clk_branch2_ops, 6578 }, 6579 }, 6580 }; 6581 6582 static struct clk_branch gcc_usb4_master_clk = { 6583 .halt_reg = 0x2a010, 6584 .halt_check = BRANCH_HALT, 6585 .clkr = { 6586 .enable_reg = 0x2a010, 6587 .enable_mask = BIT(0), 6588 .hw.init = &(const struct clk_init_data) { 6589 .name = "gcc_usb4_master_clk", 6590 .parent_hws = (const struct clk_hw*[]){ 6591 &gcc_usb4_master_clk_src.clkr.hw, 6592 }, 6593 .num_parents = 1, 6594 .flags = CLK_SET_RATE_PARENT, 6595 .ops = &clk_branch2_ops, 6596 }, 6597 }, 6598 }; 6599 6600 static struct clk_branch gcc_usb4_phy_p2rr2p_pipe_clk = { 6601 .halt_reg = 0x2a0b4, 6602 .halt_check = BRANCH_HALT_DELAY, 6603 .clkr = { 6604 .enable_reg = 0x2a0b4, 6605 .enable_mask = BIT(0), 6606 .hw.init = &(const struct clk_init_data) { 6607 .name = "gcc_usb4_phy_p2rr2p_pipe_clk", 6608 .parent_hws = (const struct clk_hw*[]){ 6609 &gcc_usb4_phy_p2rr2p_pipe_clk_src.clkr.hw, 6610 }, 6611 .num_parents = 1, 6612 .flags = CLK_SET_RATE_PARENT, 6613 .ops = &clk_branch2_ops, 6614 }, 6615 }, 6616 }; 6617 6618 static struct clk_branch gcc_usb4_phy_pcie_pipe_clk = { 6619 .halt_reg = 0x2a038, 6620 .halt_check = BRANCH_HALT_DELAY, 6621 .clkr = { 6622 .enable_reg = 0x52020, 6623 .enable_mask = BIT(18), 6624 .hw.init = &(const struct clk_init_data) { 6625 .name = "gcc_usb4_phy_pcie_pipe_clk", 6626 .parent_hws = (const struct clk_hw*[]){ 6627 &gcc_usb4_phy_pcie_pipe_mux_clk_src.clkr.hw, 6628 }, 6629 .num_parents = 1, 6630 .flags = CLK_SET_RATE_PARENT, 6631 .ops = &clk_branch2_ops, 6632 }, 6633 }, 6634 }; 6635 6636 static struct clk_branch gcc_usb4_phy_rx0_clk = { 6637 .halt_reg = 0x2a094, 6638 .halt_check = BRANCH_HALT, 6639 .clkr = { 6640 .enable_reg = 0x2a094, 6641 .enable_mask = BIT(0), 6642 .hw.init = &(const struct clk_init_data) { 6643 .name = "gcc_usb4_phy_rx0_clk", 6644 .parent_hws = (const struct clk_hw*[]){ 6645 &gcc_usb4_phy_rx0_clk_src.clkr.hw, 6646 }, 6647 .num_parents = 1, 6648 .flags = CLK_SET_RATE_PARENT, 6649 .ops = &clk_branch2_ops, 6650 }, 6651 }, 6652 }; 6653 6654 static struct clk_branch gcc_usb4_phy_rx1_clk = { 6655 .halt_reg = 0x2a0a0, 6656 .halt_check = BRANCH_HALT, 6657 .clkr = { 6658 .enable_reg = 0x2a0a0, 6659 .enable_mask = BIT(0), 6660 .hw.init = &(const struct clk_init_data) { 6661 .name = "gcc_usb4_phy_rx1_clk", 6662 .parent_hws = (const struct clk_hw*[]){ 6663 &gcc_usb4_phy_rx1_clk_src.clkr.hw, 6664 }, 6665 .num_parents = 1, 6666 .flags = CLK_SET_RATE_PARENT, 6667 .ops = &clk_branch2_ops, 6668 }, 6669 }, 6670 }; 6671 6672 static struct clk_branch gcc_usb4_phy_usb_pipe_clk = { 6673 .halt_reg = 0x2a088, 6674 .halt_check = BRANCH_HALT_DELAY, 6675 .hwcg_reg = 0x2a088, 6676 .hwcg_bit = 1, 6677 .clkr = { 6678 .enable_reg = 0x2a088, 6679 .enable_mask = BIT(0), 6680 .hw.init = &(const struct clk_init_data) { 6681 .name = "gcc_usb4_phy_usb_pipe_clk", 6682 .parent_hws = (const struct clk_hw*[]){ 6683 &gcc_usb34_prim_phy_pipe_clk_src.clkr.hw, 6684 }, 6685 .num_parents = 1, 6686 .flags = CLK_SET_RATE_PARENT, 6687 .ops = &clk_branch2_ops, 6688 }, 6689 }, 6690 }; 6691 6692 static struct clk_branch gcc_usb4_sb_if_clk = { 6693 .halt_reg = 0x2a034, 6694 .halt_check = BRANCH_HALT, 6695 .clkr = { 6696 .enable_reg = 0x2a034, 6697 .enable_mask = BIT(0), 6698 .hw.init = &(const struct clk_init_data) { 6699 .name = "gcc_usb4_sb_if_clk", 6700 .parent_hws = (const struct clk_hw*[]){ 6701 &gcc_usb4_sb_if_clk_src.clkr.hw, 6702 }, 6703 .num_parents = 1, 6704 .flags = CLK_SET_RATE_PARENT, 6705 .ops = &clk_branch2_ops, 6706 }, 6707 }, 6708 }; 6709 6710 static struct clk_branch gcc_usb4_sys_clk = { 6711 .halt_reg = 0x2a040, 6712 .halt_check = BRANCH_HALT, 6713 .clkr = { 6714 .enable_reg = 0x2a040, 6715 .enable_mask = BIT(0), 6716 .hw.init = &(const struct clk_init_data) { 6717 .name = "gcc_usb4_sys_clk", 6718 .parent_hws = (const struct clk_hw*[]){ 6719 &gcc_usb4_phy_sys_clk_src.clkr.hw, 6720 }, 6721 .num_parents = 1, 6722 .flags = CLK_SET_RATE_PARENT, 6723 .ops = &clk_branch2_ops, 6724 }, 6725 }, 6726 }; 6727 6728 static struct clk_branch gcc_usb4_tmu_clk = { 6729 .halt_reg = 0x2a06c, 6730 .halt_check = BRANCH_HALT_VOTED, 6731 .hwcg_reg = 0x2a06c, 6732 .hwcg_bit = 1, 6733 .clkr = { 6734 .enable_reg = 0x2a06c, 6735 .enable_mask = BIT(0), 6736 .hw.init = &(const struct clk_init_data) { 6737 .name = "gcc_usb4_tmu_clk", 6738 .parent_hws = (const struct clk_hw*[]){ 6739 &gcc_usb4_tmu_clk_src.clkr.hw, 6740 }, 6741 .num_parents = 1, 6742 .flags = CLK_SET_RATE_PARENT, 6743 .ops = &clk_branch2_ops, 6744 }, 6745 }, 6746 }; 6747 6748 static struct clk_branch gcc_video_axi0_clk = { 6749 .halt_reg = 0x28010, 6750 .halt_check = BRANCH_HALT_SKIP, 6751 .hwcg_reg = 0x28010, 6752 .hwcg_bit = 1, 6753 .clkr = { 6754 .enable_reg = 0x28010, 6755 .enable_mask = BIT(0), 6756 .hw.init = &(const struct clk_init_data) { 6757 .name = "gcc_video_axi0_clk", 6758 .ops = &clk_branch2_ops, 6759 }, 6760 }, 6761 }; 6762 6763 static struct clk_branch gcc_video_axi1_clk = { 6764 .halt_reg = 0x28018, 6765 .halt_check = BRANCH_HALT_SKIP, 6766 .hwcg_reg = 0x28018, 6767 .hwcg_bit = 1, 6768 .clkr = { 6769 .enable_reg = 0x28018, 6770 .enable_mask = BIT(0), 6771 .hw.init = &(const struct clk_init_data) { 6772 .name = "gcc_video_axi1_clk", 6773 .ops = &clk_branch2_ops, 6774 }, 6775 }, 6776 }; 6777 6778 static struct clk_branch gcc_video_cvp_throttle_clk = { 6779 .halt_reg = 0x28024, 6780 .halt_check = BRANCH_HALT_SKIP, 6781 .hwcg_reg = 0x28024, 6782 .hwcg_bit = 1, 6783 .clkr = { 6784 .enable_reg = 0x28024, 6785 .enable_mask = BIT(0), 6786 .hw.init = &(const struct clk_init_data) { 6787 .name = "gcc_video_cvp_throttle_clk", 6788 .ops = &clk_branch2_ops, 6789 }, 6790 }, 6791 }; 6792 6793 static struct clk_branch gcc_video_vcodec_throttle_clk = { 6794 .halt_reg = 0x28020, 6795 .halt_check = BRANCH_HALT_SKIP, 6796 .hwcg_reg = 0x28020, 6797 .hwcg_bit = 1, 6798 .clkr = { 6799 .enable_reg = 0x28020, 6800 .enable_mask = BIT(0), 6801 .hw.init = &(const struct clk_init_data) { 6802 .name = "gcc_video_vcodec_throttle_clk", 6803 .ops = &clk_branch2_ops, 6804 }, 6805 }, 6806 }; 6807 6808 static struct gdsc pcie_0_tunnel_gdsc = { 6809 .gdscr = 0xa4004, 6810 .pd = { 6811 .name = "pcie_0_tunnel_gdsc", 6812 }, 6813 .pwrsts = PWRSTS_OFF_ON, 6814 }; 6815 6816 static struct gdsc pcie_1_tunnel_gdsc = { 6817 .gdscr = 0x8d004, 6818 .pd = { 6819 .name = "pcie_1_tunnel_gdsc", 6820 }, 6821 .pwrsts = PWRSTS_OFF_ON, 6822 }; 6823 6824 static struct gdsc pcie_2a_gdsc = { 6825 .gdscr = 0x9d004, 6826 .pd = { 6827 .name = "pcie_2a_gdsc", 6828 }, 6829 .pwrsts = PWRSTS_OFF_ON, 6830 }; 6831 6832 static struct gdsc pcie_2b_gdsc = { 6833 .gdscr = 0x9e004, 6834 .pd = { 6835 .name = "pcie_2b_gdsc", 6836 }, 6837 .pwrsts = PWRSTS_OFF_ON, 6838 }; 6839 6840 static struct gdsc pcie_3a_gdsc = { 6841 .gdscr = 0xa0004, 6842 .pd = { 6843 .name = "pcie_3a_gdsc", 6844 }, 6845 .pwrsts = PWRSTS_OFF_ON, 6846 }; 6847 6848 static struct gdsc pcie_3b_gdsc = { 6849 .gdscr = 0xa2004, 6850 .pd = { 6851 .name = "pcie_3b_gdsc", 6852 }, 6853 .pwrsts = PWRSTS_OFF_ON, 6854 }; 6855 6856 static struct gdsc pcie_4_gdsc = { 6857 .gdscr = 0x6b004, 6858 .pd = { 6859 .name = "pcie_4_gdsc", 6860 }, 6861 .pwrsts = PWRSTS_OFF_ON, 6862 }; 6863 6864 static struct gdsc ufs_card_gdsc = { 6865 .gdscr = 0x75004, 6866 .pd = { 6867 .name = "ufs_card_gdsc", 6868 }, 6869 .pwrsts = PWRSTS_OFF_ON, 6870 }; 6871 6872 static struct gdsc ufs_phy_gdsc = { 6873 .gdscr = 0x77004, 6874 .pd = { 6875 .name = "ufs_phy_gdsc", 6876 }, 6877 .pwrsts = PWRSTS_OFF_ON, 6878 }; 6879 6880 static struct gdsc usb30_mp_gdsc = { 6881 .gdscr = 0xab004, 6882 .pd = { 6883 .name = "usb30_mp_gdsc", 6884 }, 6885 .pwrsts = PWRSTS_OFF_ON, 6886 }; 6887 6888 static struct gdsc usb30_prim_gdsc = { 6889 .gdscr = 0xf004, 6890 .pd = { 6891 .name = "usb30_prim_gdsc", 6892 }, 6893 .pwrsts = PWRSTS_OFF_ON, 6894 }; 6895 6896 static struct gdsc usb30_sec_gdsc = { 6897 .gdscr = 0x10004, 6898 .pd = { 6899 .name = "usb30_sec_gdsc", 6900 }, 6901 .pwrsts = PWRSTS_OFF_ON, 6902 }; 6903 6904 static struct clk_regmap *gcc_sc8280xp_clocks[] = { 6905 [GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK] = &gcc_aggre_noc_pcie0_tunnel_axi_clk.clkr, 6906 [GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK] = &gcc_aggre_noc_pcie1_tunnel_axi_clk.clkr, 6907 [GCC_AGGRE_NOC_PCIE_4_AXI_CLK] = &gcc_aggre_noc_pcie_4_axi_clk.clkr, 6908 [GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK] = &gcc_aggre_noc_pcie_south_sf_axi_clk.clkr, 6909 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, 6910 [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr, 6911 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 6912 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, 6913 [GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr, 6914 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 6915 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, 6916 [GCC_AGGRE_USB4_1_AXI_CLK] = &gcc_aggre_usb4_1_axi_clk.clkr, 6917 [GCC_AGGRE_USB4_AXI_CLK] = &gcc_aggre_usb4_axi_clk.clkr, 6918 [GCC_AGGRE_USB_NOC_AXI_CLK] = &gcc_aggre_usb_noc_axi_clk.clkr, 6919 [GCC_AGGRE_USB_NOC_NORTH_AXI_CLK] = &gcc_aggre_usb_noc_north_axi_clk.clkr, 6920 [GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK] = &gcc_aggre_usb_noc_south_axi_clk.clkr, 6921 [GCC_AHB2PHY0_CLK] = &gcc_ahb2phy0_clk.clkr, 6922 [GCC_AHB2PHY2_CLK] = &gcc_ahb2phy2_clk.clkr, 6923 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 6924 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 6925 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 6926 [GCC_CAMERA_THROTTLE_NRT_AXI_CLK] = &gcc_camera_throttle_nrt_axi_clk.clkr, 6927 [GCC_CAMERA_THROTTLE_RT_AXI_CLK] = &gcc_camera_throttle_rt_axi_clk.clkr, 6928 [GCC_CAMERA_THROTTLE_XO_CLK] = &gcc_camera_throttle_xo_clk.clkr, 6929 [GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr, 6930 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 6931 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, 6932 [GCC_CNOC_PCIE0_TUNNEL_CLK] = &gcc_cnoc_pcie0_tunnel_clk.clkr, 6933 [GCC_CNOC_PCIE1_TUNNEL_CLK] = &gcc_cnoc_pcie1_tunnel_clk.clkr, 6934 [GCC_CNOC_PCIE4_QX_CLK] = &gcc_cnoc_pcie4_qx_clk.clkr, 6935 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 6936 [GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr, 6937 [GCC_DISP1_HF_AXI_CLK] = &gcc_disp1_hf_axi_clk.clkr, 6938 [GCC_DISP1_SF_AXI_CLK] = &gcc_disp1_sf_axi_clk.clkr, 6939 [GCC_DISP1_THROTTLE_NRT_AXI_CLK] = &gcc_disp1_throttle_nrt_axi_clk.clkr, 6940 [GCC_DISP1_THROTTLE_RT_AXI_CLK] = &gcc_disp1_throttle_rt_axi_clk.clkr, 6941 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 6942 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, 6943 [GCC_DISP_THROTTLE_NRT_AXI_CLK] = &gcc_disp_throttle_nrt_axi_clk.clkr, 6944 [GCC_DISP_THROTTLE_RT_AXI_CLK] = &gcc_disp_throttle_rt_axi_clk.clkr, 6945 [GCC_EMAC0_AXI_CLK] = &gcc_emac0_axi_clk.clkr, 6946 [GCC_EMAC0_PTP_CLK] = &gcc_emac0_ptp_clk.clkr, 6947 [GCC_EMAC0_PTP_CLK_SRC] = &gcc_emac0_ptp_clk_src.clkr, 6948 [GCC_EMAC0_RGMII_CLK] = &gcc_emac0_rgmii_clk.clkr, 6949 [GCC_EMAC0_RGMII_CLK_SRC] = &gcc_emac0_rgmii_clk_src.clkr, 6950 [GCC_EMAC0_SLV_AHB_CLK] = &gcc_emac0_slv_ahb_clk.clkr, 6951 [GCC_EMAC1_AXI_CLK] = &gcc_emac1_axi_clk.clkr, 6952 [GCC_EMAC1_PTP_CLK] = &gcc_emac1_ptp_clk.clkr, 6953 [GCC_EMAC1_PTP_CLK_SRC] = &gcc_emac1_ptp_clk_src.clkr, 6954 [GCC_EMAC1_RGMII_CLK] = &gcc_emac1_rgmii_clk.clkr, 6955 [GCC_EMAC1_RGMII_CLK_SRC] = &gcc_emac1_rgmii_clk_src.clkr, 6956 [GCC_EMAC1_SLV_AHB_CLK] = &gcc_emac1_slv_ahb_clk.clkr, 6957 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 6958 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 6959 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 6960 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 6961 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 6962 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 6963 [GCC_GP4_CLK] = &gcc_gp4_clk.clkr, 6964 [GCC_GP4_CLK_SRC] = &gcc_gp4_clk_src.clkr, 6965 [GCC_GP5_CLK] = &gcc_gp5_clk.clkr, 6966 [GCC_GP5_CLK_SRC] = &gcc_gp5_clk_src.clkr, 6967 [GCC_GPLL0] = &gcc_gpll0.clkr, 6968 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 6969 [GCC_GPLL2] = &gcc_gpll2.clkr, 6970 [GCC_GPLL4] = &gcc_gpll4.clkr, 6971 [GCC_GPLL7] = &gcc_gpll7.clkr, 6972 [GCC_GPLL8] = &gcc_gpll8.clkr, 6973 [GCC_GPLL9] = &gcc_gpll9.clkr, 6974 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 6975 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 6976 [GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr, 6977 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 6978 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 6979 [GCC_GPU_TCU_THROTTLE_AHB_CLK] = &gcc_gpu_tcu_throttle_ahb_clk.clkr, 6980 [GCC_GPU_TCU_THROTTLE_CLK] = &gcc_gpu_tcu_throttle_clk.clkr, 6981 [GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr, 6982 [GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr, 6983 [GCC_PCIE2A_PHY_RCHNG_CLK] = &gcc_pcie2a_phy_rchng_clk.clkr, 6984 [GCC_PCIE2B_PHY_RCHNG_CLK] = &gcc_pcie2b_phy_rchng_clk.clkr, 6985 [GCC_PCIE3A_PHY_RCHNG_CLK] = &gcc_pcie3a_phy_rchng_clk.clkr, 6986 [GCC_PCIE3B_PHY_RCHNG_CLK] = &gcc_pcie3b_phy_rchng_clk.clkr, 6987 [GCC_PCIE4_PHY_RCHNG_CLK] = &gcc_pcie4_phy_rchng_clk.clkr, 6988 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 6989 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 6990 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 6991 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 6992 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 6993 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 6994 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 6995 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 6996 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 6997 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 6998 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 6999 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 7000 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 7001 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 7002 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 7003 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 7004 [GCC_PCIE_2A2B_CLKREF_CLK] = &gcc_pcie_2a2b_clkref_clk.clkr, 7005 [GCC_PCIE_2A_AUX_CLK] = &gcc_pcie_2a_aux_clk.clkr, 7006 [GCC_PCIE_2A_AUX_CLK_SRC] = &gcc_pcie_2a_aux_clk_src.clkr, 7007 [GCC_PCIE_2A_CFG_AHB_CLK] = &gcc_pcie_2a_cfg_ahb_clk.clkr, 7008 [GCC_PCIE_2A_MSTR_AXI_CLK] = &gcc_pcie_2a_mstr_axi_clk.clkr, 7009 [GCC_PCIE_2A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2a_phy_rchng_clk_src.clkr, 7010 [GCC_PCIE_2A_PIPE_CLK] = &gcc_pcie_2a_pipe_clk.clkr, 7011 [GCC_PCIE_2A_PIPE_CLK_SRC] = &gcc_pcie_2a_pipe_clk_src.clkr, 7012 [GCC_PCIE_2A_PIPE_DIV_CLK_SRC] = &gcc_pcie_2a_pipe_div_clk_src.clkr, 7013 [GCC_PCIE_2A_PIPEDIV2_CLK] = &gcc_pcie_2a_pipediv2_clk.clkr, 7014 [GCC_PCIE_2A_SLV_AXI_CLK] = &gcc_pcie_2a_slv_axi_clk.clkr, 7015 [GCC_PCIE_2A_SLV_Q2A_AXI_CLK] = &gcc_pcie_2a_slv_q2a_axi_clk.clkr, 7016 [GCC_PCIE_2B_AUX_CLK] = &gcc_pcie_2b_aux_clk.clkr, 7017 [GCC_PCIE_2B_AUX_CLK_SRC] = &gcc_pcie_2b_aux_clk_src.clkr, 7018 [GCC_PCIE_2B_CFG_AHB_CLK] = &gcc_pcie_2b_cfg_ahb_clk.clkr, 7019 [GCC_PCIE_2B_MSTR_AXI_CLK] = &gcc_pcie_2b_mstr_axi_clk.clkr, 7020 [GCC_PCIE_2B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2b_phy_rchng_clk_src.clkr, 7021 [GCC_PCIE_2B_PIPE_CLK] = &gcc_pcie_2b_pipe_clk.clkr, 7022 [GCC_PCIE_2B_PIPE_CLK_SRC] = &gcc_pcie_2b_pipe_clk_src.clkr, 7023 [GCC_PCIE_2B_PIPE_DIV_CLK_SRC] = &gcc_pcie_2b_pipe_div_clk_src.clkr, 7024 [GCC_PCIE_2B_PIPEDIV2_CLK] = &gcc_pcie_2b_pipediv2_clk.clkr, 7025 [GCC_PCIE_2B_SLV_AXI_CLK] = &gcc_pcie_2b_slv_axi_clk.clkr, 7026 [GCC_PCIE_2B_SLV_Q2A_AXI_CLK] = &gcc_pcie_2b_slv_q2a_axi_clk.clkr, 7027 [GCC_PCIE_3A3B_CLKREF_CLK] = &gcc_pcie_3a3b_clkref_clk.clkr, 7028 [GCC_PCIE_3A_AUX_CLK] = &gcc_pcie_3a_aux_clk.clkr, 7029 [GCC_PCIE_3A_AUX_CLK_SRC] = &gcc_pcie_3a_aux_clk_src.clkr, 7030 [GCC_PCIE_3A_CFG_AHB_CLK] = &gcc_pcie_3a_cfg_ahb_clk.clkr, 7031 [GCC_PCIE_3A_MSTR_AXI_CLK] = &gcc_pcie_3a_mstr_axi_clk.clkr, 7032 [GCC_PCIE_3A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3a_phy_rchng_clk_src.clkr, 7033 [GCC_PCIE_3A_PIPE_CLK] = &gcc_pcie_3a_pipe_clk.clkr, 7034 [GCC_PCIE_3A_PIPE_CLK_SRC] = &gcc_pcie_3a_pipe_clk_src.clkr, 7035 [GCC_PCIE_3A_PIPE_DIV_CLK_SRC] = &gcc_pcie_3a_pipe_div_clk_src.clkr, 7036 [GCC_PCIE_3A_PIPEDIV2_CLK] = &gcc_pcie_3a_pipediv2_clk.clkr, 7037 [GCC_PCIE_3A_SLV_AXI_CLK] = &gcc_pcie_3a_slv_axi_clk.clkr, 7038 [GCC_PCIE_3A_SLV_Q2A_AXI_CLK] = &gcc_pcie_3a_slv_q2a_axi_clk.clkr, 7039 [GCC_PCIE_3B_AUX_CLK] = &gcc_pcie_3b_aux_clk.clkr, 7040 [GCC_PCIE_3B_AUX_CLK_SRC] = &gcc_pcie_3b_aux_clk_src.clkr, 7041 [GCC_PCIE_3B_CFG_AHB_CLK] = &gcc_pcie_3b_cfg_ahb_clk.clkr, 7042 [GCC_PCIE_3B_MSTR_AXI_CLK] = &gcc_pcie_3b_mstr_axi_clk.clkr, 7043 [GCC_PCIE_3B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3b_phy_rchng_clk_src.clkr, 7044 [GCC_PCIE_3B_PIPE_CLK] = &gcc_pcie_3b_pipe_clk.clkr, 7045 [GCC_PCIE_3B_PIPE_CLK_SRC] = &gcc_pcie_3b_pipe_clk_src.clkr, 7046 [GCC_PCIE_3B_PIPE_DIV_CLK_SRC] = &gcc_pcie_3b_pipe_div_clk_src.clkr, 7047 [GCC_PCIE_3B_PIPEDIV2_CLK] = &gcc_pcie_3b_pipediv2_clk.clkr, 7048 [GCC_PCIE_3B_SLV_AXI_CLK] = &gcc_pcie_3b_slv_axi_clk.clkr, 7049 [GCC_PCIE_3B_SLV_Q2A_AXI_CLK] = &gcc_pcie_3b_slv_q2a_axi_clk.clkr, 7050 [GCC_PCIE_4_AUX_CLK] = &gcc_pcie_4_aux_clk.clkr, 7051 [GCC_PCIE_4_AUX_CLK_SRC] = &gcc_pcie_4_aux_clk_src.clkr, 7052 [GCC_PCIE_4_CFG_AHB_CLK] = &gcc_pcie_4_cfg_ahb_clk.clkr, 7053 [GCC_PCIE_4_CLKREF_CLK] = &gcc_pcie_4_clkref_clk.clkr, 7054 [GCC_PCIE_4_MSTR_AXI_CLK] = &gcc_pcie_4_mstr_axi_clk.clkr, 7055 [GCC_PCIE_4_PHY_RCHNG_CLK_SRC] = &gcc_pcie_4_phy_rchng_clk_src.clkr, 7056 [GCC_PCIE_4_PIPE_CLK] = &gcc_pcie_4_pipe_clk.clkr, 7057 [GCC_PCIE_4_PIPE_CLK_SRC] = &gcc_pcie_4_pipe_clk_src.clkr, 7058 [GCC_PCIE_4_PIPE_DIV_CLK_SRC] = &gcc_pcie_4_pipe_div_clk_src.clkr, 7059 [GCC_PCIE_4_PIPEDIV2_CLK] = &gcc_pcie_4_pipediv2_clk.clkr, 7060 [GCC_PCIE_4_SLV_AXI_CLK] = &gcc_pcie_4_slv_axi_clk.clkr, 7061 [GCC_PCIE_4_SLV_Q2A_AXI_CLK] = &gcc_pcie_4_slv_q2a_axi_clk.clkr, 7062 [GCC_PCIE_RSCC_AHB_CLK] = &gcc_pcie_rscc_ahb_clk.clkr, 7063 [GCC_PCIE_RSCC_XO_CLK] = &gcc_pcie_rscc_xo_clk.clkr, 7064 [GCC_PCIE_RSCC_XO_CLK_SRC] = &gcc_pcie_rscc_xo_clk_src.clkr, 7065 [GCC_PCIE_THROTTLE_CFG_CLK] = &gcc_pcie_throttle_cfg_clk.clkr, 7066 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 7067 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 7068 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 7069 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 7070 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 7071 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 7072 [GCC_QMIP_DISP1_AHB_CLK] = &gcc_qmip_disp1_ahb_clk.clkr, 7073 [GCC_QMIP_DISP1_ROT_AHB_CLK] = &gcc_qmip_disp1_rot_ahb_clk.clkr, 7074 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 7075 [GCC_QMIP_DISP_ROT_AHB_CLK] = &gcc_qmip_disp_rot_ahb_clk.clkr, 7076 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 7077 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 7078 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 7079 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 7080 [GCC_QUPV3_WRAP0_QSPI0_CLK] = &gcc_qupv3_wrap0_qspi0_clk.clkr, 7081 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 7082 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 7083 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 7084 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 7085 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 7086 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 7087 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 7088 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 7089 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 7090 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 7091 [GCC_QUPV3_WRAP0_S4_DIV_CLK_SRC] = &gcc_qupv3_wrap0_s4_div_clk_src.clkr, 7092 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 7093 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 7094 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 7095 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 7096 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 7097 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 7098 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 7099 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 7100 [GCC_QUPV3_WRAP1_QSPI0_CLK] = &gcc_qupv3_wrap1_qspi0_clk.clkr, 7101 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 7102 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 7103 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 7104 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 7105 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 7106 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 7107 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 7108 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 7109 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 7110 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 7111 [GCC_QUPV3_WRAP1_S4_DIV_CLK_SRC] = &gcc_qupv3_wrap1_s4_div_clk_src.clkr, 7112 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 7113 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 7114 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 7115 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 7116 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 7117 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 7118 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 7119 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 7120 [GCC_QUPV3_WRAP2_QSPI0_CLK] = &gcc_qupv3_wrap2_qspi0_clk.clkr, 7121 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 7122 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 7123 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 7124 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 7125 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 7126 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 7127 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 7128 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 7129 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 7130 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 7131 [GCC_QUPV3_WRAP2_S4_DIV_CLK_SRC] = &gcc_qupv3_wrap2_s4_div_clk_src.clkr, 7132 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 7133 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 7134 [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr, 7135 [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr, 7136 [GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr, 7137 [GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr, 7138 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 7139 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 7140 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 7141 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 7142 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 7143 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 7144 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 7145 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 7146 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 7147 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 7148 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 7149 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 7150 [GCC_SYS_NOC_USB_AXI_CLK] = &gcc_sys_noc_usb_axi_clk.clkr, 7151 [GCC_UFS_1_CARD_CLKREF_CLK] = &gcc_ufs_1_card_clkref_clk.clkr, 7152 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, 7153 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, 7154 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, 7155 [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr, 7156 [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr, 7157 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, 7158 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, 7159 [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_card_ice_core_hw_ctl_clk.clkr, 7160 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, 7161 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, 7162 [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr, 7163 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, 7164 [GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_rx_symbol_0_clk_src.clkr, 7165 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, 7166 [GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_card_rx_symbol_1_clk_src.clkr, 7167 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, 7168 [GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_tx_symbol_0_clk_src.clkr, 7169 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, 7170 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr, 7171 [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr, 7172 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 7173 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 7174 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 7175 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, 7176 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 7177 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 7178 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, 7179 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 7180 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 7181 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, 7182 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 7183 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 7184 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 7185 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 7186 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 7187 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 7188 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 7189 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 7190 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, 7191 [GCC_UFS_REF_CLKREF_CLK] = &gcc_ufs_ref_clkref_clk.clkr, 7192 [GCC_USB2_HS0_CLKREF_CLK] = &gcc_usb2_hs0_clkref_clk.clkr, 7193 [GCC_USB2_HS1_CLKREF_CLK] = &gcc_usb2_hs1_clkref_clk.clkr, 7194 [GCC_USB2_HS2_CLKREF_CLK] = &gcc_usb2_hs2_clkref_clk.clkr, 7195 [GCC_USB2_HS3_CLKREF_CLK] = &gcc_usb2_hs3_clkref_clk.clkr, 7196 [GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr, 7197 [GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr, 7198 [GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr, 7199 [GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr, 7200 [GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr, 7201 [GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr, 7202 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 7203 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 7204 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 7205 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 7206 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 7207 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 7208 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, 7209 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, 7210 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, 7211 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr, 7212 [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr, 7213 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, 7214 [GCC_USB34_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb34_prim_phy_pipe_clk_src.clkr, 7215 [GCC_USB34_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb34_sec_phy_pipe_clk_src.clkr, 7216 [GCC_USB3_MP0_CLKREF_CLK] = &gcc_usb3_mp0_clkref_clk.clkr, 7217 [GCC_USB3_MP1_CLKREF_CLK] = &gcc_usb3_mp1_clkref_clk.clkr, 7218 [GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr, 7219 [GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr, 7220 [GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr, 7221 [GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr, 7222 [GCC_USB3_MP_PHY_PIPE_0_CLK_SRC] = &gcc_usb3_mp_phy_pipe_0_clk_src.clkr, 7223 [GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr, 7224 [GCC_USB3_MP_PHY_PIPE_1_CLK_SRC] = &gcc_usb3_mp_phy_pipe_1_clk_src.clkr, 7225 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 7226 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 7227 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 7228 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 7229 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 7230 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, 7231 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, 7232 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, 7233 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, 7234 [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr, 7235 [GCC_USB4_1_CFG_AHB_CLK] = &gcc_usb4_1_cfg_ahb_clk.clkr, 7236 [GCC_USB4_1_DP_CLK] = &gcc_usb4_1_dp_clk.clkr, 7237 [GCC_USB4_1_MASTER_CLK] = &gcc_usb4_1_master_clk.clkr, 7238 [GCC_USB4_1_MASTER_CLK_SRC] = &gcc_usb4_1_master_clk_src.clkr, 7239 [GCC_USB4_1_PHY_DP_CLK_SRC] = &gcc_usb4_1_phy_dp_clk_src.clkr, 7240 [GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr, 7241 [GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr, 7242 [GCC_USB4_1_PHY_PCIE_PIPE_CLK] = &gcc_usb4_1_phy_pcie_pipe_clk.clkr, 7243 [GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr, 7244 [GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr, 7245 [GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipegmux_clk_src.clkr, 7246 [GCC_USB4_1_PHY_RX0_CLK] = &gcc_usb4_1_phy_rx0_clk.clkr, 7247 [GCC_USB4_1_PHY_RX0_CLK_SRC] = &gcc_usb4_1_phy_rx0_clk_src.clkr, 7248 [GCC_USB4_1_PHY_RX1_CLK] = &gcc_usb4_1_phy_rx1_clk.clkr, 7249 [GCC_USB4_1_PHY_RX1_CLK_SRC] = &gcc_usb4_1_phy_rx1_clk_src.clkr, 7250 [GCC_USB4_1_PHY_SYS_CLK_SRC] = &gcc_usb4_1_phy_sys_clk_src.clkr, 7251 [GCC_USB4_1_PHY_USB_PIPE_CLK] = &gcc_usb4_1_phy_usb_pipe_clk.clkr, 7252 [GCC_USB4_1_SB_IF_CLK] = &gcc_usb4_1_sb_if_clk.clkr, 7253 [GCC_USB4_1_SB_IF_CLK_SRC] = &gcc_usb4_1_sb_if_clk_src.clkr, 7254 [GCC_USB4_1_SYS_CLK] = &gcc_usb4_1_sys_clk.clkr, 7255 [GCC_USB4_1_TMU_CLK] = &gcc_usb4_1_tmu_clk.clkr, 7256 [GCC_USB4_1_TMU_CLK_SRC] = &gcc_usb4_1_tmu_clk_src.clkr, 7257 [GCC_USB4_CFG_AHB_CLK] = &gcc_usb4_cfg_ahb_clk.clkr, 7258 [GCC_USB4_CLKREF_CLK] = &gcc_usb4_clkref_clk.clkr, 7259 [GCC_USB4_DP_CLK] = &gcc_usb4_dp_clk.clkr, 7260 [GCC_USB4_EUD_CLKREF_CLK] = &gcc_usb4_eud_clkref_clk.clkr, 7261 [GCC_USB4_MASTER_CLK] = &gcc_usb4_master_clk.clkr, 7262 [GCC_USB4_MASTER_CLK_SRC] = &gcc_usb4_master_clk_src.clkr, 7263 [GCC_USB4_PHY_DP_CLK_SRC] = &gcc_usb4_phy_dp_clk_src.clkr, 7264 [GCC_USB4_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_phy_p2rr2p_pipe_clk.clkr, 7265 [GCC_USB4_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_phy_p2rr2p_pipe_clk_src.clkr, 7266 [GCC_USB4_PHY_PCIE_PIPE_CLK] = &gcc_usb4_phy_pcie_pipe_clk.clkr, 7267 [GCC_USB4_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_phy_pcie_pipe_clk_src.clkr, 7268 [GCC_USB4_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_phy_pcie_pipe_mux_clk_src.clkr, 7269 [GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC] = &gcc_usb4_phy_pcie_pipegmux_clk_src.clkr, 7270 [GCC_USB4_PHY_RX0_CLK] = &gcc_usb4_phy_rx0_clk.clkr, 7271 [GCC_USB4_PHY_RX0_CLK_SRC] = &gcc_usb4_phy_rx0_clk_src.clkr, 7272 [GCC_USB4_PHY_RX1_CLK] = &gcc_usb4_phy_rx1_clk.clkr, 7273 [GCC_USB4_PHY_RX1_CLK_SRC] = &gcc_usb4_phy_rx1_clk_src.clkr, 7274 [GCC_USB4_PHY_SYS_CLK_SRC] = &gcc_usb4_phy_sys_clk_src.clkr, 7275 [GCC_USB4_PHY_USB_PIPE_CLK] = &gcc_usb4_phy_usb_pipe_clk.clkr, 7276 [GCC_USB4_SB_IF_CLK] = &gcc_usb4_sb_if_clk.clkr, 7277 [GCC_USB4_SB_IF_CLK_SRC] = &gcc_usb4_sb_if_clk_src.clkr, 7278 [GCC_USB4_SYS_CLK] = &gcc_usb4_sys_clk.clkr, 7279 [GCC_USB4_TMU_CLK] = &gcc_usb4_tmu_clk.clkr, 7280 [GCC_USB4_TMU_CLK_SRC] = &gcc_usb4_tmu_clk_src.clkr, 7281 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 7282 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 7283 [GCC_VIDEO_CVP_THROTTLE_CLK] = &gcc_video_cvp_throttle_clk.clkr, 7284 [GCC_VIDEO_VCODEC_THROTTLE_CLK] = &gcc_video_vcodec_throttle_clk.clkr, 7285 }; 7286 7287 static const struct qcom_reset_map gcc_sc8280xp_resets[] = { 7288 [GCC_EMAC0_BCR] = { 0xaa000 }, 7289 [GCC_EMAC1_BCR] = { 0xba000 }, 7290 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 7291 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 7292 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 7293 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, 7294 [GCC_PCIE_0_TUNNEL_BCR] = { 0xa4000 }, 7295 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, 7296 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, 7297 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 7298 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 }, 7299 [GCC_PCIE_1_TUNNEL_BCR] = { 0x8d000 }, 7300 [GCC_PCIE_2A_BCR] = { 0x9d000 }, 7301 [GCC_PCIE_2A_LINK_DOWN_BCR] = { 0x9d13c }, 7302 [GCC_PCIE_2A_NOCSR_COM_PHY_BCR] = { 0x9d148 }, 7303 [GCC_PCIE_2A_PHY_BCR] = { 0x9d144 }, 7304 [GCC_PCIE_2A_PHY_NOCSR_COM_PHY_BCR] = { 0x9d14c }, 7305 [GCC_PCIE_2B_BCR] = { 0x9e000 }, 7306 [GCC_PCIE_2B_LINK_DOWN_BCR] = { 0x9e084 }, 7307 [GCC_PCIE_2B_NOCSR_COM_PHY_BCR] = { 0x9e090 }, 7308 [GCC_PCIE_2B_PHY_BCR] = { 0x9e08c }, 7309 [GCC_PCIE_2B_PHY_NOCSR_COM_PHY_BCR] = { 0x9e094 }, 7310 [GCC_PCIE_3A_BCR] = { 0xa0000 }, 7311 [GCC_PCIE_3A_LINK_DOWN_BCR] = { 0xa00f0 }, 7312 [GCC_PCIE_3A_NOCSR_COM_PHY_BCR] = { 0xa00fc }, 7313 [GCC_PCIE_3A_PHY_BCR] = { 0xa00e0 }, 7314 [GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR] = { 0xa00e4 }, 7315 [GCC_PCIE_3B_BCR] = { 0xa2000 }, 7316 [GCC_PCIE_3B_LINK_DOWN_BCR] = { 0xa20e0 }, 7317 [GCC_PCIE_3B_NOCSR_COM_PHY_BCR] = { 0xa20ec }, 7318 [GCC_PCIE_3B_PHY_BCR] = { 0xa20e8 }, 7319 [GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR] = { 0xa20f0 }, 7320 [GCC_PCIE_4_BCR] = { 0x6b000 }, 7321 [GCC_PCIE_4_LINK_DOWN_BCR] = { 0x6b300 }, 7322 [GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0x6b30c }, 7323 [GCC_PCIE_4_PHY_BCR] = { 0x6b308 }, 7324 [GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0x6b310 }, 7325 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, 7326 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, 7327 [GCC_PCIE_RSCC_BCR] = { 0xae000 }, 7328 [GCC_QUSB2PHY_HS0_MP_BCR] = { 0x12008 }, 7329 [GCC_QUSB2PHY_HS1_MP_BCR] = { 0x1200c }, 7330 [GCC_QUSB2PHY_HS2_MP_BCR] = { 0x12010 }, 7331 [GCC_QUSB2PHY_HS3_MP_BCR] = { 0x12014 }, 7332 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 7333 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 7334 [GCC_SDCC2_BCR] = { 0x14000 }, 7335 [GCC_SDCC4_BCR] = { 0x16000 }, 7336 [GCC_UFS_CARD_BCR] = { 0x75000 }, 7337 [GCC_UFS_PHY_BCR] = { 0x77000 }, 7338 [GCC_USB2_PHY_PRIM_BCR] = { 0x50028 }, 7339 [GCC_USB2_PHY_SEC_BCR] = { 0x5002c }, 7340 [GCC_USB30_MP_BCR] = { 0xab000 }, 7341 [GCC_USB30_PRIM_BCR] = { 0xf000 }, 7342 [GCC_USB30_SEC_BCR] = { 0x10000 }, 7343 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 7344 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 7345 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 7346 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 7347 [GCC_USB3_UNIPHY_MP0_BCR] = { 0x50018 }, 7348 [GCC_USB3_UNIPHY_MP1_BCR] = { 0x5001c }, 7349 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 7350 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 7351 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x50020 }, 7352 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x50024 }, 7353 [GCC_USB4_1_BCR] = { 0xb8000 }, 7354 [GCC_USB4_1_DP_PHY_PRIM_BCR] = { 0xb9020 }, 7355 [GCC_USB4_1_DPPHY_AUX_BCR] = { 0xb9024 }, 7356 [GCC_USB4_1_PHY_PRIM_BCR] = { 0xb9018 }, 7357 [GCC_USB4_BCR] = { 0x2a000 }, 7358 [GCC_USB4_DP_PHY_PRIM_BCR] = { 0x4a008 }, 7359 [GCC_USB4_DPPHY_AUX_BCR] = { 0x4a00c }, 7360 [GCC_USB4_PHY_PRIM_BCR] = { 0x4a000 }, 7361 [GCC_USB4PHY_1_PHY_PRIM_BCR] = { 0xb901c }, 7362 [GCC_USB4PHY_PHY_PRIM_BCR] = { 0x4a004 }, 7363 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 7364 [GCC_VIDEO_BCR] = { 0x28000 }, 7365 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x28010, 2 }, 7366 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x28018, 2 }, 7367 }; 7368 7369 static struct gdsc *gcc_sc8280xp_gdscs[] = { 7370 [PCIE_0_TUNNEL_GDSC] = &pcie_0_tunnel_gdsc, 7371 [PCIE_1_TUNNEL_GDSC] = &pcie_1_tunnel_gdsc, 7372 [PCIE_2A_GDSC] = &pcie_2a_gdsc, 7373 [PCIE_2B_GDSC] = &pcie_2b_gdsc, 7374 [PCIE_3A_GDSC] = &pcie_3a_gdsc, 7375 [PCIE_3B_GDSC] = &pcie_3b_gdsc, 7376 [PCIE_4_GDSC] = &pcie_4_gdsc, 7377 [UFS_CARD_GDSC] = &ufs_card_gdsc, 7378 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 7379 [USB30_MP_GDSC] = &usb30_mp_gdsc, 7380 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 7381 [USB30_SEC_GDSC] = &usb30_sec_gdsc, 7382 }; 7383 7384 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 7385 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 7386 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 7387 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 7388 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 7389 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 7390 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 7391 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 7392 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 7393 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 7394 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 7395 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 7396 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 7397 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 7398 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 7399 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 7400 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 7401 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 7402 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 7403 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 7404 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 7405 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 7406 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 7407 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src), 7408 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src), 7409 }; 7410 7411 static const struct regmap_config gcc_sc8280xp_regmap_config = { 7412 .reg_bits = 32, 7413 .reg_stride = 4, 7414 .val_bits = 32, 7415 .max_register = 0xc3014, 7416 .fast_io = true, 7417 }; 7418 7419 static const struct qcom_cc_desc gcc_sc8280xp_desc = { 7420 .config = &gcc_sc8280xp_regmap_config, 7421 .clks = gcc_sc8280xp_clocks, 7422 .num_clks = ARRAY_SIZE(gcc_sc8280xp_clocks), 7423 .resets = gcc_sc8280xp_resets, 7424 .num_resets = ARRAY_SIZE(gcc_sc8280xp_resets), 7425 .gdscs = gcc_sc8280xp_gdscs, 7426 .num_gdscs = ARRAY_SIZE(gcc_sc8280xp_gdscs), 7427 }; 7428 7429 static int gcc_sc8280xp_probe(struct platform_device *pdev) 7430 { 7431 struct regmap *regmap; 7432 int ret; 7433 7434 regmap = qcom_cc_map(pdev, &gcc_sc8280xp_desc); 7435 if (IS_ERR(regmap)) 7436 return PTR_ERR(regmap); 7437 7438 /* 7439 * Keep the clocks always-ON 7440 * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK, 7441 * GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, 7442 * GCC_VIDEO_XO_CLK, GCC_DISP1_AHB_CLK, GCC_DISP1_XO_CLK 7443 */ 7444 regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); 7445 regmap_update_bits(regmap, 0x26020, BIT(0), BIT(0)); 7446 regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); 7447 regmap_update_bits(regmap, 0x27028, BIT(0), BIT(0)); 7448 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 7449 regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); 7450 regmap_update_bits(regmap, 0x28028, BIT(0), BIT(0)); 7451 regmap_update_bits(regmap, 0xbb004, BIT(0), BIT(0)); 7452 regmap_update_bits(regmap, 0xbb028, BIT(0), BIT(0)); 7453 7454 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); 7455 if (ret) 7456 return ret; 7457 7458 return qcom_cc_really_probe(pdev, &gcc_sc8280xp_desc, regmap); 7459 } 7460 7461 static const struct of_device_id gcc_sc8280xp_match_table[] = { 7462 { .compatible = "qcom,gcc-sc8280xp" }, 7463 { } 7464 }; 7465 MODULE_DEVICE_TABLE(of, gcc_sc8280xp_match_table); 7466 7467 static struct platform_driver gcc_sc8280xp_driver = { 7468 .probe = gcc_sc8280xp_probe, 7469 .driver = { 7470 .name = "gcc-sc8280xp", 7471 .of_match_table = gcc_sc8280xp_match_table, 7472 }, 7473 }; 7474 7475 static int __init gcc_sc8280xp_init(void) 7476 { 7477 return platform_driver_register(&gcc_sc8280xp_driver); 7478 } 7479 subsys_initcall(gcc_sc8280xp_init); 7480 7481 static void __exit gcc_sc8280xp_exit(void) 7482 { 7483 platform_driver_unregister(&gcc_sc8280xp_driver); 7484 } 7485 module_exit(gcc_sc8280xp_exit); 7486 7487 MODULE_DESCRIPTION("Qualcomm SC8280XP GCC driver"); 7488 MODULE_LICENSE("GPL"); 7489