xref: /openbmc/linux/drivers/clk/qcom/gcc-sc8280xp.c (revision 0352f880)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4  * Copyright (c) 2022, Linaro Ltd.
5  */
6 
7 #include <linux/clk-provider.h>
8 #include <linux/err.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/of.h>
13 #include <linux/regmap.h>
14 
15 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
16 
17 #include "clk-alpha-pll.h"
18 #include "clk-branch.h"
19 #include "clk-rcg.h"
20 #include "clk-regmap.h"
21 #include "clk-regmap-divider.h"
22 #include "clk-regmap-mux.h"
23 #include "clk-regmap-phy-mux.h"
24 #include "common.h"
25 #include "gdsc.h"
26 #include "reset.h"
27 
28 /* Need to match the order of clocks in DT binding */
29 enum {
30 	DT_BI_TCXO,
31 	DT_SLEEP_CLK,
32 	DT_UFS_PHY_RX_SYMBOL_0_CLK,
33 	DT_UFS_PHY_RX_SYMBOL_1_CLK,
34 	DT_UFS_PHY_TX_SYMBOL_0_CLK,
35 	DT_UFS_CARD_RX_SYMBOL_0_CLK,
36 	DT_UFS_CARD_RX_SYMBOL_1_CLK,
37 	DT_UFS_CARD_TX_SYMBOL_0_CLK,
38 	DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
39 	DT_GCC_USB4_PHY_PIPEGMUX_CLK_SRC,
40 	DT_GCC_USB4_PHY_DP_GMUX_CLK_SRC,
41 	DT_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC,
42 	DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK,
43 	DT_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
44 	DT_QUSB4PHY_GCC_USB4_RX0_CLK,
45 	DT_QUSB4PHY_GCC_USB4_RX1_CLK,
46 	DT_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK,
47 	DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,
48 	DT_GCC_USB4_1_PHY_DP_GMUX_CLK_SRC,
49 	DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,
50 	DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,
51 	DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
52 	DT_QUSB4PHY_1_GCC_USB4_RX0_CLK,
53 	DT_QUSB4PHY_1_GCC_USB4_RX1_CLK,
54 	DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK,
55 	DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK,
56 	DT_PCIE_2A_PIPE_CLK,
57 	DT_PCIE_2B_PIPE_CLK,
58 	DT_PCIE_3A_PIPE_CLK,
59 	DT_PCIE_3B_PIPE_CLK,
60 	DT_PCIE_4_PIPE_CLK,
61 	DT_RXC0_REF_CLK,
62 	DT_RXC1_REF_CLK,
63 };
64 
65 enum {
66 	P_BI_TCXO,
67 	P_GCC_GPLL0_OUT_EVEN,
68 	P_GCC_GPLL0_OUT_MAIN,
69 	P_GCC_GPLL2_OUT_MAIN,
70 	P_GCC_GPLL4_OUT_MAIN,
71 	P_GCC_GPLL7_OUT_MAIN,
72 	P_GCC_GPLL8_OUT_MAIN,
73 	P_GCC_GPLL9_OUT_MAIN,
74 	P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC,
75 	P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC,
76 	P_GCC_USB4_1_PHY_DP_GMUX_CLK_SRC,
77 	P_GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC,
78 	P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC,
79 	P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,
80 	P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,
81 	P_GCC_USB4_PHY_DP_GMUX_CLK_SRC,
82 	P_GCC_USB4_PHY_PCIE_PIPE_CLK_SRC,
83 	P_GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC,
84 	P_GCC_USB4_PHY_PIPEGMUX_CLK_SRC,
85 	P_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC,
86 	P_QUSB4PHY_1_GCC_USB4_RX0_CLK,
87 	P_QUSB4PHY_1_GCC_USB4_RX1_CLK,
88 	P_QUSB4PHY_GCC_USB4_RX0_CLK,
89 	P_QUSB4PHY_GCC_USB4_RX1_CLK,
90 	P_RXC0_REF_CLK,
91 	P_RXC1_REF_CLK,
92 	P_SLEEP_CLK,
93 	P_UFS_CARD_RX_SYMBOL_0_CLK,
94 	P_UFS_CARD_RX_SYMBOL_1_CLK,
95 	P_UFS_CARD_TX_SYMBOL_0_CLK,
96 	P_UFS_PHY_RX_SYMBOL_0_CLK,
97 	P_UFS_PHY_RX_SYMBOL_1_CLK,
98 	P_UFS_PHY_TX_SYMBOL_0_CLK,
99 	P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
100 	P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK,
101 	P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK,
102 	P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK,
103 	P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,
104 	P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
105 	P_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK,
106 	P_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
107 };
108 
109 static const struct clk_parent_data gcc_parent_data_tcxo = { .index = DT_BI_TCXO };
110 
111 static struct clk_alpha_pll gcc_gpll0 = {
112 	.offset = 0x0,
113 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
114 	.clkr = {
115 		.enable_reg = 0x52028,
116 		.enable_mask = BIT(0),
117 		.hw.init = &(const struct clk_init_data) {
118 			.name = "gcc_gpll0",
119 			.parent_data = &gcc_parent_data_tcxo,
120 			.num_parents = 1,
121 			.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
122 		},
123 	},
124 };
125 
126 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
127 	{ 0x1, 2 },
128 	{ }
129 };
130 
131 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
132 	.offset = 0x0,
133 	.post_div_shift = 8,
134 	.post_div_table = post_div_table_gcc_gpll0_out_even,
135 	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
136 	.width = 4,
137 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
138 	.clkr.hw.init = &(const struct clk_init_data) {
139 		.name = "gcc_gpll0_out_even",
140 		.parent_hws = (const struct clk_hw*[]){
141 			&gcc_gpll0.clkr.hw,
142 		},
143 		.num_parents = 1,
144 		.ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops,
145 	},
146 };
147 
148 static struct clk_alpha_pll gcc_gpll2 = {
149 	.offset = 0x2000,
150 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
151 	.clkr = {
152 		.enable_reg = 0x52028,
153 		.enable_mask = BIT(2),
154 		.hw.init = &(const struct clk_init_data) {
155 			.name = "gcc_gpll2",
156 			.parent_data = &gcc_parent_data_tcxo,
157 			.num_parents = 1,
158 			.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
159 		},
160 	},
161 };
162 
163 static struct clk_alpha_pll gcc_gpll4 = {
164 	.offset = 0x76000,
165 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
166 	.clkr = {
167 		.enable_reg = 0x52028,
168 		.enable_mask = BIT(4),
169 		.hw.init = &(const struct clk_init_data) {
170 			.name = "gcc_gpll4",
171 			.parent_data = &gcc_parent_data_tcxo,
172 			.num_parents = 1,
173 			.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
174 		},
175 	},
176 };
177 
178 static struct clk_alpha_pll gcc_gpll7 = {
179 	.offset = 0x1a000,
180 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
181 	.clkr = {
182 		.enable_reg = 0x52028,
183 		.enable_mask = BIT(7),
184 		.hw.init = &(const struct clk_init_data) {
185 			.name = "gcc_gpll7",
186 			.parent_data = &gcc_parent_data_tcxo,
187 			.num_parents = 1,
188 			.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
189 		},
190 	},
191 };
192 
193 static struct clk_alpha_pll gcc_gpll8 = {
194 	.offset = 0x1b000,
195 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
196 	.clkr = {
197 		.enable_reg = 0x52028,
198 		.enable_mask = BIT(8),
199 		.hw.init = &(const struct clk_init_data) {
200 			.name = "gcc_gpll8",
201 			.parent_data = &gcc_parent_data_tcxo,
202 			.num_parents = 1,
203 			.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
204 		},
205 	},
206 };
207 
208 static struct clk_alpha_pll gcc_gpll9 = {
209 	.offset = 0x1c000,
210 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
211 	.clkr = {
212 		.enable_reg = 0x52028,
213 		.enable_mask = BIT(9),
214 		.hw.init = &(const struct clk_init_data) {
215 			.name = "gcc_gpll9",
216 			.parent_data = &gcc_parent_data_tcxo,
217 			.num_parents = 1,
218 			.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
219 		},
220 	},
221 };
222 
223 static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src;
224 static struct clk_rcg2 gcc_usb4_phy_pcie_pipe_clk_src;
225 
226 static const struct parent_map gcc_parent_map_0[] = {
227 	{ P_BI_TCXO, 0 },
228 	{ P_GCC_GPLL0_OUT_MAIN, 1 },
229 	{ P_GCC_GPLL0_OUT_EVEN, 6 },
230 };
231 
232 static const struct clk_parent_data gcc_parent_data_0[] = {
233 	{ .index = DT_BI_TCXO },
234 	{ .hw = &gcc_gpll0.clkr.hw },
235 	{ .hw = &gcc_gpll0_out_even.clkr.hw },
236 };
237 
238 static const struct parent_map gcc_parent_map_1[] = {
239 	{ P_BI_TCXO, 0 },
240 	{ P_SLEEP_CLK, 5 },
241 };
242 
243 static const struct clk_parent_data gcc_parent_data_1[] = {
244 	{ .index = DT_BI_TCXO },
245 	{ .index = DT_SLEEP_CLK },
246 };
247 
248 static const struct parent_map gcc_parent_map_2[] = {
249 	{ P_BI_TCXO, 0 },
250 	{ P_GCC_GPLL0_OUT_MAIN, 1 },
251 	{ P_SLEEP_CLK, 5 },
252 	{ P_GCC_GPLL0_OUT_EVEN, 6 },
253 };
254 
255 static const struct clk_parent_data gcc_parent_data_2[] = {
256 	{ .index = DT_BI_TCXO },
257 	{ .hw = &gcc_gpll0.clkr.hw },
258 	{ .index = DT_SLEEP_CLK },
259 	{ .hw = &gcc_gpll0_out_even.clkr.hw },
260 };
261 
262 static const struct parent_map gcc_parent_map_3[] = {
263 	{ P_BI_TCXO, 0 },
264 };
265 
266 static const struct clk_parent_data gcc_parent_data_3[] = {
267 	{ .index = DT_BI_TCXO },
268 };
269 
270 static const struct parent_map gcc_parent_map_4[] = {
271 	{ P_BI_TCXO, 0 },
272 	{ P_GCC_GPLL7_OUT_MAIN, 2 },
273 	{ P_GCC_GPLL4_OUT_MAIN, 5 },
274 	{ P_GCC_GPLL0_OUT_EVEN, 6 },
275 };
276 
277 static const struct clk_parent_data gcc_parent_data_4[] = {
278 	{ .index = DT_BI_TCXO },
279 	{ .hw = &gcc_gpll7.clkr.hw },
280 	{ .hw = &gcc_gpll4.clkr.hw },
281 	{ .hw = &gcc_gpll0_out_even.clkr.hw },
282 };
283 
284 static const struct parent_map gcc_parent_map_5[] = {
285 	{ P_BI_TCXO, 0 },
286 	{ P_GCC_GPLL0_OUT_MAIN, 1 },
287 	{ P_GCC_GPLL8_OUT_MAIN, 2 },
288 	{ P_GCC_GPLL0_OUT_EVEN, 6 },
289 };
290 
291 static const struct clk_parent_data gcc_parent_data_5[] = {
292 	{ .index = DT_BI_TCXO },
293 	{ .hw = &gcc_gpll0.clkr.hw },
294 	{ .hw = &gcc_gpll8.clkr.hw },
295 	{ .hw = &gcc_gpll0_out_even.clkr.hw },
296 };
297 
298 static const struct parent_map gcc_parent_map_6[] = {
299 	{ P_BI_TCXO, 0 },
300 	{ P_GCC_GPLL0_OUT_MAIN, 1 },
301 	{ P_GCC_GPLL7_OUT_MAIN, 2 },
302 };
303 
304 static const struct clk_parent_data gcc_parent_data_6[] = {
305 	{ .index = DT_BI_TCXO },
306 	{ .hw = &gcc_gpll0.clkr.hw },
307 	{ .hw = &gcc_gpll7.clkr.hw },
308 };
309 
310 static const struct parent_map gcc_parent_map_7[] = {
311 	{ P_BI_TCXO, 0 },
312 	{ P_GCC_GPLL0_OUT_MAIN, 1 },
313 	{ P_GCC_GPLL2_OUT_MAIN, 2 },
314 };
315 
316 static const struct clk_parent_data gcc_parent_data_7[] = {
317 	{ .index = DT_BI_TCXO },
318 	{ .hw = &gcc_gpll0.clkr.hw },
319 	{ .hw = &gcc_gpll2.clkr.hw },
320 };
321 
322 static const struct parent_map gcc_parent_map_8[] = {
323 	{ P_BI_TCXO, 0 },
324 	{ P_GCC_GPLL7_OUT_MAIN, 2 },
325 	{ P_RXC0_REF_CLK, 3 },
326 	{ P_GCC_GPLL0_OUT_EVEN, 6 },
327 };
328 
329 static const struct clk_parent_data gcc_parent_data_8[] = {
330 	{ .index = DT_BI_TCXO },
331 	{ .hw = &gcc_gpll7.clkr.hw },
332 	{ .index = DT_RXC0_REF_CLK },
333 	{ .hw = &gcc_gpll0_out_even.clkr.hw },
334 };
335 
336 static const struct parent_map gcc_parent_map_9[] = {
337 	{ P_BI_TCXO, 0 },
338 	{ P_GCC_GPLL7_OUT_MAIN, 2 },
339 	{ P_RXC1_REF_CLK, 3 },
340 	{ P_GCC_GPLL0_OUT_EVEN, 6 },
341 };
342 
343 static const struct clk_parent_data gcc_parent_data_9[] = {
344 	{ .index = DT_BI_TCXO },
345 	{ .hw = &gcc_gpll7.clkr.hw },
346 	{ .index = DT_RXC1_REF_CLK },
347 	{ .hw = &gcc_gpll0_out_even.clkr.hw },
348 };
349 
350 static const struct parent_map gcc_parent_map_15[] = {
351 	{ P_BI_TCXO, 0 },
352 	{ P_GCC_GPLL0_OUT_MAIN, 1 },
353 	{ P_GCC_GPLL9_OUT_MAIN, 2 },
354 	{ P_GCC_GPLL4_OUT_MAIN, 5 },
355 	{ P_GCC_GPLL0_OUT_EVEN, 6 },
356 };
357 
358 static const struct clk_parent_data gcc_parent_data_15[] = {
359 	{ .index = DT_BI_TCXO },
360 	{ .hw = &gcc_gpll0.clkr.hw },
361 	{ .hw = &gcc_gpll9.clkr.hw },
362 	{ .hw = &gcc_gpll4.clkr.hw },
363 	{ .hw = &gcc_gpll0_out_even.clkr.hw },
364 };
365 
366 static const struct parent_map gcc_parent_map_16[] = {
367 	{ P_UFS_CARD_RX_SYMBOL_0_CLK, 0 },
368 	{ P_BI_TCXO, 2 },
369 };
370 
371 static const struct clk_parent_data gcc_parent_data_16[] = {
372 	{ .index = DT_UFS_CARD_RX_SYMBOL_0_CLK },
373 	{ .index = DT_BI_TCXO },
374 };
375 
376 static const struct parent_map gcc_parent_map_17[] = {
377 	{ P_UFS_CARD_RX_SYMBOL_1_CLK, 0 },
378 	{ P_BI_TCXO, 2 },
379 };
380 
381 static const struct clk_parent_data gcc_parent_data_17[] = {
382 	{ .index = DT_UFS_CARD_RX_SYMBOL_1_CLK },
383 	{ .index = DT_BI_TCXO },
384 };
385 
386 static const struct parent_map gcc_parent_map_18[] = {
387 	{ P_UFS_CARD_TX_SYMBOL_0_CLK, 0 },
388 	{ P_BI_TCXO, 2 },
389 };
390 
391 static const struct clk_parent_data gcc_parent_data_18[] = {
392 	{ .index = DT_UFS_CARD_TX_SYMBOL_0_CLK },
393 	{ .index = DT_BI_TCXO },
394 };
395 
396 static const struct parent_map gcc_parent_map_19[] = {
397 	{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
398 	{ P_BI_TCXO, 2 },
399 };
400 
401 static const struct clk_parent_data gcc_parent_data_19[] = {
402 	{ .index = DT_UFS_PHY_RX_SYMBOL_0_CLK },
403 	{ .index = DT_BI_TCXO },
404 };
405 
406 static const struct parent_map gcc_parent_map_20[] = {
407 	{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
408 	{ P_BI_TCXO, 2 },
409 };
410 
411 static const struct clk_parent_data gcc_parent_data_20[] = {
412 	{ .index = DT_UFS_PHY_RX_SYMBOL_1_CLK },
413 	{ .index = DT_BI_TCXO },
414 };
415 
416 static const struct parent_map gcc_parent_map_21[] = {
417 	{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
418 	{ P_BI_TCXO, 2 },
419 };
420 
421 static const struct clk_parent_data gcc_parent_data_21[] = {
422 	{ .index = DT_UFS_PHY_TX_SYMBOL_0_CLK },
423 	{ .index = DT_BI_TCXO },
424 };
425 
426 static const struct parent_map gcc_parent_map_22[] = {
427 	{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
428 	{ P_BI_TCXO, 2 },
429 };
430 
431 static const struct clk_parent_data gcc_parent_data_22[] = {
432 	{ .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK },
433 	{ .index = DT_BI_TCXO },
434 };
435 
436 static const struct parent_map gcc_parent_map_23[] = {
437 	{ P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK, 0 },
438 	{ P_BI_TCXO, 2 },
439 };
440 
441 static const struct clk_parent_data gcc_parent_data_23[] = {
442 	{ .index = DT_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK },
443 	{ .index = DT_BI_TCXO },
444 };
445 
446 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
447 	.reg = 0xf060,
448 	.shift = 0,
449 	.width = 2,
450 	.parent_map = gcc_parent_map_22,
451 	.clkr = {
452 		.hw.init = &(const struct clk_init_data) {
453 			.name = "gcc_usb3_prim_phy_pipe_clk_src",
454 			.parent_data = gcc_parent_data_22,
455 			.num_parents = ARRAY_SIZE(gcc_parent_data_22),
456 			.ops = &clk_regmap_mux_closest_ops,
457 		},
458 	},
459 };
460 
461 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
462 	.reg = 0x10060,
463 	.shift = 0,
464 	.width = 2,
465 	.parent_map = gcc_parent_map_23,
466 	.clkr = {
467 		.hw.init = &(const struct clk_init_data) {
468 			.name = "gcc_usb3_sec_phy_pipe_clk_src",
469 			.parent_data = gcc_parent_data_23,
470 			.num_parents = ARRAY_SIZE(gcc_parent_data_23),
471 			.ops = &clk_regmap_mux_closest_ops,
472 		},
473 	},
474 };
475 
476 static const struct parent_map gcc_parent_map_24[] = {
477 	{ P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK, 0 },
478 	{ P_BI_TCXO, 2 },
479 };
480 
481 static const struct clk_parent_data gcc_parent_data_24[] = {
482 	{ .index = DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK },
483 	{ .index = DT_BI_TCXO },
484 };
485 
486 static const struct parent_map gcc_parent_map_25[] = {
487 	{ P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK, 0 },
488 	{ P_BI_TCXO, 2 },
489 };
490 
491 static const struct clk_parent_data gcc_parent_data_25[] = {
492 	{ .index = DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK },
493 	{ .index = DT_BI_TCXO },
494 };
495 
496 static const struct parent_map gcc_parent_map_26[] = {
497 	{ P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 },
498 	{ P_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
499 	{ P_GCC_USB4_PHY_PIPEGMUX_CLK_SRC, 3 },
500 };
501 
502 static const struct clk_parent_data gcc_parent_data_26[] = {
503 	{ .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw },
504 	{ .index = DT_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
505 	{ .index = DT_GCC_USB4_PHY_PIPEGMUX_CLK_SRC },
506 };
507 
508 static const struct parent_map gcc_parent_map_27[] = {
509 	{ P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 0 },
510 	{ P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
511 	{ P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 3 },
512 };
513 
514 static const struct clk_parent_data gcc_parent_data_27[] = {
515 	{ .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw },
516 	{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
517 	{ .index = DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC },
518 };
519 
520 static const struct parent_map gcc_parent_map_28[] = {
521 	{ P_GCC_USB4_1_PHY_DP_GMUX_CLK_SRC, 0 },
522 	{ P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
523 };
524 
525 static const struct clk_parent_data gcc_parent_data_28[] = {
526 	{ .index = DT_GCC_USB4_1_PHY_DP_GMUX_CLK_SRC },
527 	{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
528 };
529 
530 static const struct parent_map gcc_parent_map_29[] = {
531 	{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
532 	{ P_BI_TCXO, 2 },
533 };
534 
535 static const struct clk_parent_data gcc_parent_data_29[] = {
536 	{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
537 	{ .index = DT_BI_TCXO },
538 };
539 
540 static const struct parent_map gcc_parent_map_30[] = {
541 	{ P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
542 	{ P_GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC, 1 },
543 };
544 
545 static const struct clk_parent_data gcc_parent_data_30[] = {
546 	{ .index = DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC },
547 	{ .hw = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr.hw },
548 };
549 
550 static struct clk_regmap_mux gcc_usb4_1_phy_pcie_pipegmux_clk_src = {
551 	.reg = 0xb80dc,
552 	.shift = 0,
553 	.width = 1,
554 	.parent_map = gcc_parent_map_30,
555 	.clkr = {
556 		.hw.init = &(const struct clk_init_data) {
557 			.name = "gcc_usb4_1_phy_pcie_pipegmux_clk_src",
558 			.parent_data = gcc_parent_data_30,
559 			.num_parents = ARRAY_SIZE(gcc_parent_data_30),
560 			.ops = &clk_regmap_mux_closest_ops,
561 		},
562 	},
563 };
564 
565 static const struct parent_map gcc_parent_map_31[] = {
566 	{ P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
567 	{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
568 };
569 
570 static const struct clk_parent_data gcc_parent_data_31[] = {
571 	{ .hw = &gcc_usb4_1_phy_pcie_pipegmux_clk_src.clkr.hw },
572 	{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
573 };
574 
575 static const struct parent_map gcc_parent_map_32[] = {
576 	{ P_QUSB4PHY_1_GCC_USB4_RX0_CLK, 0 },
577 	{ P_BI_TCXO, 2 },
578 };
579 
580 static const struct clk_parent_data gcc_parent_data_32[] = {
581 	{ .index = DT_QUSB4PHY_1_GCC_USB4_RX0_CLK },
582 	{ .index = DT_BI_TCXO },
583 };
584 
585 static const struct parent_map gcc_parent_map_33[] = {
586 	{ P_QUSB4PHY_1_GCC_USB4_RX1_CLK, 0 },
587 	{ P_BI_TCXO, 2 },
588 };
589 
590 static const struct clk_parent_data gcc_parent_data_33[] = {
591 	{ .index = DT_QUSB4PHY_1_GCC_USB4_RX1_CLK },
592 	{ .index = DT_BI_TCXO },
593 };
594 
595 static const struct parent_map gcc_parent_map_34[] = {
596 	{ P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
597 	{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
598 };
599 
600 static const struct clk_parent_data gcc_parent_data_34[] = {
601 	{ .index = DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC },
602 	{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
603 };
604 
605 static const struct parent_map gcc_parent_map_35[] = {
606 	{ P_GCC_USB4_PHY_DP_GMUX_CLK_SRC, 0 },
607 	{ P_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
608 };
609 
610 static const struct clk_parent_data gcc_parent_data_35[] = {
611 	{ .index = DT_GCC_USB4_PHY_DP_GMUX_CLK_SRC },
612 	{ .index = DT_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
613 };
614 
615 static const struct parent_map gcc_parent_map_36[] = {
616 	{ P_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
617 	{ P_BI_TCXO, 2 },
618 };
619 
620 static const struct clk_parent_data gcc_parent_data_36[] = {
621 	{ .index = DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK },
622 	{ .index = DT_BI_TCXO },
623 };
624 
625 static const struct parent_map gcc_parent_map_37[] = {
626 	{ P_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
627 	{ P_GCC_USB4_PHY_PCIE_PIPE_CLK_SRC, 1 },
628 };
629 
630 static const struct clk_parent_data gcc_parent_data_37[] = {
631 	{ .index = DT_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC },
632 	{ .hw = &gcc_usb4_phy_pcie_pipe_clk_src.clkr.hw },
633 };
634 
635 static struct clk_regmap_mux gcc_usb4_phy_pcie_pipegmux_clk_src = {
636 	.reg = 0x2a0dc,
637 	.shift = 0,
638 	.width = 1,
639 	.parent_map = gcc_parent_map_37,
640 	.clkr = {
641 		.hw.init = &(const struct clk_init_data) {
642 			.name = "gcc_usb4_phy_pcie_pipegmux_clk_src",
643 			.parent_data = gcc_parent_data_37,
644 			.num_parents = ARRAY_SIZE(gcc_parent_data_37),
645 			.ops = &clk_regmap_mux_closest_ops,
646 		},
647 	},
648 };
649 
650 static const struct parent_map gcc_parent_map_38[] = {
651 	{ P_GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
652 	{ P_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
653 };
654 
655 static const struct clk_parent_data gcc_parent_data_38[] = {
656 	{ .hw = &gcc_usb4_phy_pcie_pipegmux_clk_src.clkr.hw },
657 	{ .index = DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK },
658 };
659 
660 static const struct parent_map gcc_parent_map_39[] = {
661 	{ P_QUSB4PHY_GCC_USB4_RX0_CLK, 0 },
662 	{ P_BI_TCXO, 2 },
663 };
664 
665 static const struct clk_parent_data gcc_parent_data_39[] = {
666 	{ .index = DT_QUSB4PHY_GCC_USB4_RX0_CLK },
667 	{ .index = DT_BI_TCXO },
668 };
669 
670 static const struct parent_map gcc_parent_map_40[] = {
671 	{ P_QUSB4PHY_GCC_USB4_RX1_CLK, 0 },
672 	{ P_BI_TCXO, 2 },
673 };
674 
675 static const struct clk_parent_data gcc_parent_data_40[] = {
676 	{ .index = DT_QUSB4PHY_GCC_USB4_RX1_CLK },
677 	{ .index = DT_BI_TCXO },
678 };
679 
680 static const struct parent_map gcc_parent_map_41[] = {
681 	{ P_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
682 	{ P_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
683 };
684 
685 static const struct clk_parent_data gcc_parent_data_41[] = {
686 	{ .index = DT_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC },
687 	{ .index = DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK },
688 };
689 
690 static struct clk_regmap_phy_mux gcc_pcie_2a_pipe_clk_src = {
691 	.reg = 0x9d05c,
692 	.clkr = {
693 		.hw.init = &(const struct clk_init_data) {
694 			.name = "gcc_pcie_2a_pipe_clk_src",
695 			.parent_data = &(const struct clk_parent_data){
696 				.index = DT_PCIE_2A_PIPE_CLK,
697 			},
698 			.num_parents = 1,
699 			.ops = &clk_regmap_phy_mux_ops,
700 		},
701 	},
702 };
703 
704 static struct clk_regmap_phy_mux gcc_pcie_2b_pipe_clk_src = {
705 	.reg = 0x9e05c,
706 	.clkr = {
707 		.hw.init = &(const struct clk_init_data) {
708 			.name = "gcc_pcie_2b_pipe_clk_src",
709 			.parent_data = &(const struct clk_parent_data){
710 				.index = DT_PCIE_2B_PIPE_CLK,
711 			},
712 			.num_parents = 1,
713 			.ops = &clk_regmap_phy_mux_ops,
714 		},
715 	},
716 };
717 
718 static struct clk_regmap_phy_mux gcc_pcie_3a_pipe_clk_src = {
719 	.reg = 0xa005c,
720 	.clkr = {
721 		.hw.init = &(const struct clk_init_data) {
722 			.name = "gcc_pcie_3a_pipe_clk_src",
723 			.parent_data = &(const struct clk_parent_data){
724 				.index = DT_PCIE_3A_PIPE_CLK,
725 			},
726 			.num_parents = 1,
727 			.ops = &clk_regmap_phy_mux_ops,
728 		},
729 	},
730 };
731 
732 static struct clk_regmap_phy_mux gcc_pcie_3b_pipe_clk_src = {
733 	.reg = 0xa205c,
734 	.clkr = {
735 		.hw.init = &(const struct clk_init_data) {
736 			.name = "gcc_pcie_3b_pipe_clk_src",
737 			.parent_data = &(const struct clk_parent_data){
738 				.index = DT_PCIE_3B_PIPE_CLK,
739 			},
740 			.num_parents = 1,
741 			.ops = &clk_regmap_phy_mux_ops,
742 		},
743 	},
744 };
745 
746 static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src = {
747 	.reg = 0x6b05c,
748 	.clkr = {
749 		.hw.init = &(const struct clk_init_data) {
750 			.name = "gcc_pcie_4_pipe_clk_src",
751 			.parent_data = &(const struct clk_parent_data){
752 				.index = DT_PCIE_4_PIPE_CLK,
753 			},
754 			.num_parents = 1,
755 			.ops = &clk_regmap_phy_mux_ops,
756 		},
757 	},
758 };
759 
760 static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src = {
761 	.reg = 0x75058,
762 	.shift = 0,
763 	.width = 2,
764 	.parent_map = gcc_parent_map_16,
765 	.clkr = {
766 		.hw.init = &(const struct clk_init_data) {
767 			.name = "gcc_ufs_card_rx_symbol_0_clk_src",
768 			.parent_data = gcc_parent_data_16,
769 			.num_parents = ARRAY_SIZE(gcc_parent_data_16),
770 			.ops = &clk_regmap_mux_closest_ops,
771 		},
772 	},
773 };
774 
775 static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src = {
776 	.reg = 0x750c8,
777 	.shift = 0,
778 	.width = 2,
779 	.parent_map = gcc_parent_map_17,
780 	.clkr = {
781 		.hw.init = &(const struct clk_init_data) {
782 			.name = "gcc_ufs_card_rx_symbol_1_clk_src",
783 			.parent_data = gcc_parent_data_17,
784 			.num_parents = ARRAY_SIZE(gcc_parent_data_17),
785 			.ops = &clk_regmap_mux_closest_ops,
786 		},
787 	},
788 };
789 
790 static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src = {
791 	.reg = 0x75048,
792 	.shift = 0,
793 	.width = 2,
794 	.parent_map = gcc_parent_map_18,
795 	.clkr = {
796 		.hw.init = &(const struct clk_init_data) {
797 			.name = "gcc_ufs_card_tx_symbol_0_clk_src",
798 			.parent_data = gcc_parent_data_18,
799 			.num_parents = ARRAY_SIZE(gcc_parent_data_18),
800 			.ops = &clk_regmap_mux_closest_ops,
801 		},
802 	},
803 };
804 
805 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
806 	.reg = 0x77058,
807 	.shift = 0,
808 	.width = 2,
809 	.parent_map = gcc_parent_map_19,
810 	.clkr = {
811 		.hw.init = &(const struct clk_init_data) {
812 			.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
813 			.parent_data = gcc_parent_data_19,
814 			.num_parents = ARRAY_SIZE(gcc_parent_data_19),
815 			.ops = &clk_regmap_mux_closest_ops,
816 		},
817 	},
818 };
819 
820 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
821 	.reg = 0x770c8,
822 	.shift = 0,
823 	.width = 2,
824 	.parent_map = gcc_parent_map_20,
825 	.clkr = {
826 		.hw.init = &(const struct clk_init_data) {
827 			.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
828 			.parent_data = gcc_parent_data_20,
829 			.num_parents = ARRAY_SIZE(gcc_parent_data_20),
830 			.ops = &clk_regmap_mux_closest_ops,
831 		},
832 	},
833 };
834 
835 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
836 	.reg = 0x77048,
837 	.shift = 0,
838 	.width = 2,
839 	.parent_map = gcc_parent_map_21,
840 	.clkr = {
841 		.hw.init = &(const struct clk_init_data) {
842 			.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
843 			.parent_data = gcc_parent_data_21,
844 			.num_parents = ARRAY_SIZE(gcc_parent_data_21),
845 			.ops = &clk_regmap_mux_closest_ops,
846 		},
847 	},
848 };
849 
850 static struct clk_regmap_mux gcc_usb34_prim_phy_pipe_clk_src = {
851 	.reg = 0xf064,
852 	.shift = 0,
853 	.width = 2,
854 	.parent_map = gcc_parent_map_26,
855 	.clkr = {
856 		.hw.init = &(const struct clk_init_data) {
857 			.name = "gcc_usb34_prim_phy_pipe_clk_src",
858 			.parent_data = gcc_parent_data_26,
859 			.num_parents = ARRAY_SIZE(gcc_parent_data_26),
860 			.ops = &clk_regmap_mux_closest_ops,
861 		},
862 	},
863 };
864 
865 static struct clk_regmap_mux gcc_usb34_sec_phy_pipe_clk_src = {
866 	.reg = 0x10064,
867 	.shift = 0,
868 	.width = 2,
869 	.parent_map = gcc_parent_map_27,
870 	.clkr = {
871 		.hw.init = &(const struct clk_init_data) {
872 			.name = "gcc_usb34_sec_phy_pipe_clk_src",
873 			.parent_data = gcc_parent_data_27,
874 			.num_parents = ARRAY_SIZE(gcc_parent_data_27),
875 			.ops = &clk_regmap_mux_closest_ops,
876 		},
877 	},
878 };
879 
880 static struct clk_regmap_mux gcc_usb3_mp_phy_pipe_0_clk_src = {
881 	.reg = 0xab060,
882 	.shift = 0,
883 	.width = 2,
884 	.parent_map = gcc_parent_map_24,
885 	.clkr = {
886 		.hw.init = &(const struct clk_init_data) {
887 			.name = "gcc_usb3_mp_phy_pipe_0_clk_src",
888 			.parent_data = gcc_parent_data_24,
889 			.num_parents = ARRAY_SIZE(gcc_parent_data_24),
890 			.ops = &clk_regmap_mux_closest_ops,
891 		},
892 	},
893 };
894 
895 static struct clk_regmap_mux gcc_usb3_mp_phy_pipe_1_clk_src = {
896 	.reg = 0xab068,
897 	.shift = 0,
898 	.width = 2,
899 	.parent_map = gcc_parent_map_25,
900 	.clkr = {
901 		.hw.init = &(const struct clk_init_data) {
902 			.name = "gcc_usb3_mp_phy_pipe_1_clk_src",
903 			.parent_data = gcc_parent_data_25,
904 			.num_parents = ARRAY_SIZE(gcc_parent_data_25),
905 			.ops = &clk_regmap_mux_closest_ops,
906 		},
907 	},
908 };
909 
910 static struct clk_regmap_mux gcc_usb4_1_phy_dp_clk_src = {
911 	.reg = 0xb8050,
912 	.shift = 0,
913 	.width = 2,
914 	.parent_map = gcc_parent_map_28,
915 	.clkr = {
916 		.hw.init = &(const struct clk_init_data) {
917 			.name = "gcc_usb4_1_phy_dp_clk_src",
918 			.parent_data = gcc_parent_data_28,
919 			.num_parents = ARRAY_SIZE(gcc_parent_data_28),
920 			.ops = &clk_regmap_mux_closest_ops,
921 		},
922 	},
923 };
924 
925 static struct clk_regmap_mux gcc_usb4_1_phy_p2rr2p_pipe_clk_src = {
926 	.reg = 0xb80b0,
927 	.shift = 0,
928 	.width = 2,
929 	.parent_map = gcc_parent_map_29,
930 	.clkr = {
931 		.hw.init = &(const struct clk_init_data) {
932 			.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk_src",
933 			.parent_data = gcc_parent_data_29,
934 			.num_parents = ARRAY_SIZE(gcc_parent_data_29),
935 			.ops = &clk_regmap_mux_closest_ops,
936 		},
937 	},
938 };
939 
940 static struct clk_regmap_mux gcc_usb4_1_phy_pcie_pipe_mux_clk_src = {
941 	.reg = 0xb80e0,
942 	.shift = 0,
943 	.width = 2,
944 	.parent_map = gcc_parent_map_31,
945 	.clkr = {
946 		.hw.init = &(const struct clk_init_data) {
947 			.name = "gcc_usb4_1_phy_pcie_pipe_mux_clk_src",
948 			.parent_data = gcc_parent_data_31,
949 			.num_parents = ARRAY_SIZE(gcc_parent_data_31),
950 			.ops = &clk_regmap_mux_closest_ops,
951 		},
952 	},
953 };
954 
955 static struct clk_regmap_mux gcc_usb4_1_phy_rx0_clk_src = {
956 	.reg = 0xb8090,
957 	.shift = 0,
958 	.width = 2,
959 	.parent_map = gcc_parent_map_32,
960 	.clkr = {
961 		.hw.init = &(const struct clk_init_data) {
962 			.name = "gcc_usb4_1_phy_rx0_clk_src",
963 			.parent_data = gcc_parent_data_32,
964 			.num_parents = ARRAY_SIZE(gcc_parent_data_32),
965 			.ops = &clk_regmap_mux_closest_ops,
966 		},
967 	},
968 };
969 
970 static struct clk_regmap_mux gcc_usb4_1_phy_rx1_clk_src = {
971 	.reg = 0xb809c,
972 	.shift = 0,
973 	.width = 2,
974 	.parent_map = gcc_parent_map_33,
975 	.clkr = {
976 		.hw.init = &(const struct clk_init_data) {
977 			.name = "gcc_usb4_1_phy_rx1_clk_src",
978 			.parent_data = gcc_parent_data_33,
979 			.num_parents = ARRAY_SIZE(gcc_parent_data_33),
980 			.ops = &clk_regmap_mux_closest_ops,
981 		},
982 	},
983 };
984 
985 static struct clk_regmap_mux gcc_usb4_1_phy_sys_clk_src = {
986 	.reg = 0xb80c0,
987 	.shift = 0,
988 	.width = 2,
989 	.parent_map = gcc_parent_map_34,
990 	.clkr = {
991 		.hw.init = &(const struct clk_init_data) {
992 			.name = "gcc_usb4_1_phy_sys_clk_src",
993 			.parent_data = gcc_parent_data_34,
994 			.num_parents = ARRAY_SIZE(gcc_parent_data_34),
995 			.ops = &clk_regmap_mux_closest_ops,
996 		},
997 	},
998 };
999 
1000 static struct clk_regmap_mux gcc_usb4_phy_dp_clk_src = {
1001 	.reg = 0x2a050,
1002 	.shift = 0,
1003 	.width = 2,
1004 	.parent_map = gcc_parent_map_35,
1005 	.clkr = {
1006 		.hw.init = &(const struct clk_init_data) {
1007 			.name = "gcc_usb4_phy_dp_clk_src",
1008 			.parent_data = gcc_parent_data_35,
1009 			.num_parents = ARRAY_SIZE(gcc_parent_data_35),
1010 			.ops = &clk_regmap_mux_closest_ops,
1011 		},
1012 	},
1013 };
1014 
1015 static struct clk_regmap_mux gcc_usb4_phy_p2rr2p_pipe_clk_src = {
1016 	.reg = 0x2a0b0,
1017 	.shift = 0,
1018 	.width = 2,
1019 	.parent_map = gcc_parent_map_36,
1020 	.clkr = {
1021 		.hw.init = &(const struct clk_init_data) {
1022 			.name = "gcc_usb4_phy_p2rr2p_pipe_clk_src",
1023 			.parent_data = gcc_parent_data_36,
1024 			.num_parents = ARRAY_SIZE(gcc_parent_data_36),
1025 			.ops = &clk_regmap_mux_closest_ops,
1026 		},
1027 	},
1028 };
1029 
1030 static struct clk_regmap_mux gcc_usb4_phy_pcie_pipe_mux_clk_src = {
1031 	.reg = 0x2a0e0,
1032 	.shift = 0,
1033 	.width = 2,
1034 	.parent_map = gcc_parent_map_38,
1035 	.clkr = {
1036 		.hw.init = &(const struct clk_init_data) {
1037 			.name = "gcc_usb4_phy_pcie_pipe_mux_clk_src",
1038 			.parent_data = gcc_parent_data_38,
1039 			.num_parents = ARRAY_SIZE(gcc_parent_data_38),
1040 			.ops = &clk_regmap_mux_closest_ops,
1041 		},
1042 	},
1043 };
1044 
1045 static struct clk_regmap_mux gcc_usb4_phy_rx0_clk_src = {
1046 	.reg = 0x2a090,
1047 	.shift = 0,
1048 	.width = 2,
1049 	.parent_map = gcc_parent_map_39,
1050 	.clkr = {
1051 		.hw.init = &(const struct clk_init_data) {
1052 			.name = "gcc_usb4_phy_rx0_clk_src",
1053 			.parent_data = gcc_parent_data_39,
1054 			.num_parents = ARRAY_SIZE(gcc_parent_data_39),
1055 			.ops = &clk_regmap_mux_closest_ops,
1056 		},
1057 	},
1058 };
1059 
1060 static struct clk_regmap_mux gcc_usb4_phy_rx1_clk_src = {
1061 	.reg = 0x2a09c,
1062 	.shift = 0,
1063 	.width = 2,
1064 	.parent_map = gcc_parent_map_40,
1065 	.clkr = {
1066 		.hw.init = &(const struct clk_init_data) {
1067 			.name = "gcc_usb4_phy_rx1_clk_src",
1068 			.parent_data = gcc_parent_data_40,
1069 			.num_parents = ARRAY_SIZE(gcc_parent_data_40),
1070 			.ops = &clk_regmap_mux_closest_ops,
1071 		},
1072 	},
1073 };
1074 
1075 static struct clk_regmap_mux gcc_usb4_phy_sys_clk_src = {
1076 	.reg = 0x2a0c0,
1077 	.shift = 0,
1078 	.width = 2,
1079 	.parent_map = gcc_parent_map_41,
1080 	.clkr = {
1081 		.hw.init = &(const struct clk_init_data) {
1082 			.name = "gcc_usb4_phy_sys_clk_src",
1083 			.parent_data = gcc_parent_data_41,
1084 			.num_parents = ARRAY_SIZE(gcc_parent_data_41),
1085 			.ops = &clk_regmap_mux_closest_ops,
1086 		},
1087 	},
1088 };
1089 
1090 static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] = {
1091 	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1092 	F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
1093 	F(230400000, P_GCC_GPLL4_OUT_MAIN, 3.5, 0, 0),
1094 	{ }
1095 };
1096 
1097 static struct clk_rcg2 gcc_emac0_ptp_clk_src = {
1098 	.cmd_rcgr = 0xaa020,
1099 	.mnd_width = 0,
1100 	.hid_width = 5,
1101 	.parent_map = gcc_parent_map_4,
1102 	.freq_tbl = ftbl_gcc_emac0_ptp_clk_src,
1103 	.clkr.hw.init = &(const struct clk_init_data) {
1104 		.name = "gcc_emac0_ptp_clk_src",
1105 		.parent_data = gcc_parent_data_4,
1106 		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
1107 		.ops = &clk_rcg2_shared_ops,
1108 	},
1109 };
1110 
1111 static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] = {
1112 	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1113 	F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
1114 	F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0),
1115 	{ }
1116 };
1117 
1118 static struct clk_rcg2 gcc_emac0_rgmii_clk_src = {
1119 	.cmd_rcgr = 0xaa040,
1120 	.mnd_width = 8,
1121 	.hid_width = 5,
1122 	.parent_map = gcc_parent_map_8,
1123 	.freq_tbl = ftbl_gcc_emac0_rgmii_clk_src,
1124 	.clkr.hw.init = &(const struct clk_init_data) {
1125 		.name = "gcc_emac0_rgmii_clk_src",
1126 		.parent_data = gcc_parent_data_8,
1127 		.num_parents = ARRAY_SIZE(gcc_parent_data_8),
1128 		.ops = &clk_rcg2_shared_ops,
1129 	},
1130 };
1131 
1132 static struct clk_rcg2 gcc_emac1_ptp_clk_src = {
1133 	.cmd_rcgr = 0xba020,
1134 	.mnd_width = 0,
1135 	.hid_width = 5,
1136 	.parent_map = gcc_parent_map_4,
1137 	.freq_tbl = ftbl_gcc_emac0_ptp_clk_src,
1138 	.clkr.hw.init = &(const struct clk_init_data) {
1139 		.name = "gcc_emac1_ptp_clk_src",
1140 		.parent_data = gcc_parent_data_4,
1141 		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
1142 		.ops = &clk_rcg2_shared_ops,
1143 	},
1144 };
1145 
1146 static struct clk_rcg2 gcc_emac1_rgmii_clk_src = {
1147 	.cmd_rcgr = 0xba040,
1148 	.mnd_width = 8,
1149 	.hid_width = 5,
1150 	.parent_map = gcc_parent_map_9,
1151 	.freq_tbl = ftbl_gcc_emac0_rgmii_clk_src,
1152 	.clkr.hw.init = &(const struct clk_init_data) {
1153 		.name = "gcc_emac1_rgmii_clk_src",
1154 		.parent_data = gcc_parent_data_9,
1155 		.num_parents = ARRAY_SIZE(gcc_parent_data_9),
1156 		.ops = &clk_rcg2_shared_ops,
1157 	},
1158 };
1159 
1160 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
1161 	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1162 	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1163 	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1164 	{ }
1165 };
1166 
1167 static struct clk_rcg2 gcc_gp1_clk_src = {
1168 	.cmd_rcgr = 0x64004,
1169 	.mnd_width = 16,
1170 	.hid_width = 5,
1171 	.parent_map = gcc_parent_map_2,
1172 	.freq_tbl = ftbl_gcc_gp1_clk_src,
1173 	.clkr.hw.init = &(const struct clk_init_data) {
1174 		.name = "gcc_gp1_clk_src",
1175 		.parent_data = gcc_parent_data_2,
1176 		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1177 		.ops = &clk_rcg2_shared_ops,
1178 	},
1179 };
1180 
1181 static struct clk_rcg2 gcc_gp2_clk_src = {
1182 	.cmd_rcgr = 0x65004,
1183 	.mnd_width = 16,
1184 	.hid_width = 5,
1185 	.parent_map = gcc_parent_map_2,
1186 	.freq_tbl = ftbl_gcc_gp1_clk_src,
1187 	.clkr.hw.init = &(const struct clk_init_data) {
1188 		.name = "gcc_gp2_clk_src",
1189 		.parent_data = gcc_parent_data_2,
1190 		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1191 		.ops = &clk_rcg2_shared_ops,
1192 	},
1193 };
1194 
1195 static struct clk_rcg2 gcc_gp3_clk_src = {
1196 	.cmd_rcgr = 0x66004,
1197 	.mnd_width = 16,
1198 	.hid_width = 5,
1199 	.parent_map = gcc_parent_map_2,
1200 	.freq_tbl = ftbl_gcc_gp1_clk_src,
1201 	.clkr.hw.init = &(const struct clk_init_data) {
1202 		.name = "gcc_gp3_clk_src",
1203 		.parent_data = gcc_parent_data_2,
1204 		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1205 		.ops = &clk_rcg2_shared_ops,
1206 	},
1207 };
1208 
1209 static struct clk_rcg2 gcc_gp4_clk_src = {
1210 	.cmd_rcgr = 0xc2004,
1211 	.mnd_width = 16,
1212 	.hid_width = 5,
1213 	.parent_map = gcc_parent_map_2,
1214 	.freq_tbl = ftbl_gcc_gp1_clk_src,
1215 	.clkr.hw.init = &(const struct clk_init_data) {
1216 		.name = "gcc_gp4_clk_src",
1217 		.parent_data = gcc_parent_data_2,
1218 		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1219 		.ops = &clk_rcg2_shared_ops,
1220 	},
1221 };
1222 
1223 static struct clk_rcg2 gcc_gp5_clk_src = {
1224 	.cmd_rcgr = 0xc3004,
1225 	.mnd_width = 16,
1226 	.hid_width = 5,
1227 	.parent_map = gcc_parent_map_2,
1228 	.freq_tbl = ftbl_gcc_gp1_clk_src,
1229 	.clkr.hw.init = &(const struct clk_init_data) {
1230 		.name = "gcc_gp5_clk_src",
1231 		.parent_data = gcc_parent_data_2,
1232 		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1233 		.ops = &clk_rcg2_shared_ops,
1234 	},
1235 };
1236 
1237 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
1238 	F(9600000, P_BI_TCXO, 2, 0, 0),
1239 	F(19200000, P_BI_TCXO, 1, 0, 0),
1240 	{ }
1241 };
1242 
1243 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
1244 	.cmd_rcgr = 0xa4054,
1245 	.mnd_width = 16,
1246 	.hid_width = 5,
1247 	.parent_map = gcc_parent_map_1,
1248 	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1249 	.clkr.hw.init = &(const struct clk_init_data) {
1250 		.name = "gcc_pcie_0_aux_clk_src",
1251 		.parent_data = gcc_parent_data_1,
1252 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1253 		.ops = &clk_rcg2_shared_ops,
1254 	},
1255 };
1256 
1257 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
1258 	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1259 	{ }
1260 };
1261 
1262 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
1263 	.cmd_rcgr = 0xa403c,
1264 	.mnd_width = 0,
1265 	.hid_width = 5,
1266 	.parent_map = gcc_parent_map_0,
1267 	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1268 	.clkr.hw.init = &(const struct clk_init_data) {
1269 		.name = "gcc_pcie_0_phy_rchng_clk_src",
1270 		.parent_data = gcc_parent_data_0,
1271 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1272 		.ops = &clk_rcg2_shared_ops,
1273 	},
1274 };
1275 
1276 static const struct freq_tbl ftbl_gcc_pcie_1_aux_clk_src[] = {
1277 	F(19200000, P_BI_TCXO, 1, 0, 0),
1278 	{ }
1279 };
1280 
1281 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
1282 	.cmd_rcgr = 0x8d054,
1283 	.mnd_width = 16,
1284 	.hid_width = 5,
1285 	.parent_map = gcc_parent_map_1,
1286 	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
1287 	.clkr.hw.init = &(const struct clk_init_data) {
1288 		.name = "gcc_pcie_1_aux_clk_src",
1289 		.parent_data = gcc_parent_data_1,
1290 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1291 		.ops = &clk_rcg2_shared_ops,
1292 	},
1293 };
1294 
1295 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
1296 	.cmd_rcgr = 0x8d03c,
1297 	.mnd_width = 0,
1298 	.hid_width = 5,
1299 	.parent_map = gcc_parent_map_0,
1300 	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1301 	.clkr.hw.init = &(const struct clk_init_data) {
1302 		.name = "gcc_pcie_1_phy_rchng_clk_src",
1303 		.parent_data = gcc_parent_data_0,
1304 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1305 		.ops = &clk_rcg2_shared_ops,
1306 	},
1307 };
1308 
1309 static struct clk_rcg2 gcc_pcie_2a_aux_clk_src = {
1310 	.cmd_rcgr = 0x9d064,
1311 	.mnd_width = 16,
1312 	.hid_width = 5,
1313 	.parent_map = gcc_parent_map_1,
1314 	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
1315 	.clkr.hw.init = &(const struct clk_init_data) {
1316 		.name = "gcc_pcie_2a_aux_clk_src",
1317 		.parent_data = gcc_parent_data_1,
1318 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1319 		.ops = &clk_rcg2_shared_ops,
1320 	},
1321 };
1322 
1323 static struct clk_rcg2 gcc_pcie_2a_phy_rchng_clk_src = {
1324 	.cmd_rcgr = 0x9d044,
1325 	.mnd_width = 0,
1326 	.hid_width = 5,
1327 	.parent_map = gcc_parent_map_0,
1328 	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1329 	.clkr.hw.init = &(const struct clk_init_data) {
1330 		.name = "gcc_pcie_2a_phy_rchng_clk_src",
1331 		.parent_data = gcc_parent_data_0,
1332 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1333 		.ops = &clk_rcg2_shared_ops,
1334 	},
1335 };
1336 
1337 static struct clk_rcg2 gcc_pcie_2b_aux_clk_src = {
1338 	.cmd_rcgr = 0x9e064,
1339 	.mnd_width = 16,
1340 	.hid_width = 5,
1341 	.parent_map = gcc_parent_map_1,
1342 	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
1343 	.clkr.hw.init = &(const struct clk_init_data) {
1344 		.name = "gcc_pcie_2b_aux_clk_src",
1345 		.parent_data = gcc_parent_data_1,
1346 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1347 		.ops = &clk_rcg2_shared_ops,
1348 	},
1349 };
1350 
1351 static struct clk_rcg2 gcc_pcie_2b_phy_rchng_clk_src = {
1352 	.cmd_rcgr = 0x9e044,
1353 	.mnd_width = 0,
1354 	.hid_width = 5,
1355 	.parent_map = gcc_parent_map_0,
1356 	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1357 	.clkr.hw.init = &(const struct clk_init_data) {
1358 		.name = "gcc_pcie_2b_phy_rchng_clk_src",
1359 		.parent_data = gcc_parent_data_0,
1360 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1361 		.ops = &clk_rcg2_shared_ops,
1362 	},
1363 };
1364 
1365 static struct clk_rcg2 gcc_pcie_3a_aux_clk_src = {
1366 	.cmd_rcgr = 0xa0064,
1367 	.mnd_width = 16,
1368 	.hid_width = 5,
1369 	.parent_map = gcc_parent_map_1,
1370 	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
1371 	.clkr.hw.init = &(const struct clk_init_data) {
1372 		.name = "gcc_pcie_3a_aux_clk_src",
1373 		.parent_data = gcc_parent_data_1,
1374 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1375 		.ops = &clk_rcg2_shared_ops,
1376 	},
1377 };
1378 
1379 static struct clk_rcg2 gcc_pcie_3a_phy_rchng_clk_src = {
1380 	.cmd_rcgr = 0xa0044,
1381 	.mnd_width = 0,
1382 	.hid_width = 5,
1383 	.parent_map = gcc_parent_map_0,
1384 	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1385 	.clkr.hw.init = &(const struct clk_init_data) {
1386 		.name = "gcc_pcie_3a_phy_rchng_clk_src",
1387 		.parent_data = gcc_parent_data_0,
1388 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1389 		.ops = &clk_rcg2_shared_ops,
1390 	},
1391 };
1392 
1393 static struct clk_rcg2 gcc_pcie_3b_aux_clk_src = {
1394 	.cmd_rcgr = 0xa2064,
1395 	.mnd_width = 16,
1396 	.hid_width = 5,
1397 	.parent_map = gcc_parent_map_1,
1398 	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
1399 	.clkr.hw.init = &(const struct clk_init_data) {
1400 		.name = "gcc_pcie_3b_aux_clk_src",
1401 		.parent_data = gcc_parent_data_1,
1402 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1403 		.ops = &clk_rcg2_shared_ops,
1404 	},
1405 };
1406 
1407 static struct clk_rcg2 gcc_pcie_3b_phy_rchng_clk_src = {
1408 	.cmd_rcgr = 0xa2044,
1409 	.mnd_width = 0,
1410 	.hid_width = 5,
1411 	.parent_map = gcc_parent_map_0,
1412 	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1413 	.clkr.hw.init = &(const struct clk_init_data) {
1414 		.name = "gcc_pcie_3b_phy_rchng_clk_src",
1415 		.parent_data = gcc_parent_data_0,
1416 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1417 		.ops = &clk_rcg2_shared_ops,
1418 	},
1419 };
1420 
1421 static struct clk_rcg2 gcc_pcie_4_aux_clk_src = {
1422 	.cmd_rcgr = 0x6b064,
1423 	.mnd_width = 16,
1424 	.hid_width = 5,
1425 	.parent_map = gcc_parent_map_1,
1426 	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1427 	.clkr.hw.init = &(const struct clk_init_data) {
1428 		.name = "gcc_pcie_4_aux_clk_src",
1429 		.parent_data = gcc_parent_data_1,
1430 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1431 		.ops = &clk_rcg2_shared_ops,
1432 	},
1433 };
1434 
1435 static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src = {
1436 	.cmd_rcgr = 0x6b044,
1437 	.mnd_width = 0,
1438 	.hid_width = 5,
1439 	.parent_map = gcc_parent_map_0,
1440 	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1441 	.clkr.hw.init = &(const struct clk_init_data) {
1442 		.name = "gcc_pcie_4_phy_rchng_clk_src",
1443 		.parent_data = gcc_parent_data_0,
1444 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1445 		.ops = &clk_rcg2_shared_ops,
1446 	},
1447 };
1448 
1449 static struct clk_rcg2 gcc_pcie_rscc_xo_clk_src = {
1450 	.cmd_rcgr = 0xae00c,
1451 	.mnd_width = 0,
1452 	.hid_width = 5,
1453 	.parent_map = gcc_parent_map_3,
1454 	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
1455 	.clkr.hw.init = &(const struct clk_init_data) {
1456 		.name = "gcc_pcie_rscc_xo_clk_src",
1457 		.parent_data = gcc_parent_data_3,
1458 		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1459 		.ops = &clk_rcg2_shared_ops,
1460 	},
1461 };
1462 
1463 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
1464 	F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
1465 	{ }
1466 };
1467 
1468 static struct clk_rcg2 gcc_pdm2_clk_src = {
1469 	.cmd_rcgr = 0x33010,
1470 	.mnd_width = 0,
1471 	.hid_width = 5,
1472 	.parent_map = gcc_parent_map_0,
1473 	.freq_tbl = ftbl_gcc_pdm2_clk_src,
1474 	.clkr.hw.init = &(const struct clk_init_data) {
1475 		.name = "gcc_pdm2_clk_src",
1476 		.parent_data = gcc_parent_data_0,
1477 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1478 		.ops = &clk_rcg2_shared_ops,
1479 	},
1480 };
1481 
1482 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
1483 	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
1484 	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
1485 	F(19200000, P_BI_TCXO, 1, 0, 0),
1486 	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
1487 	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
1488 	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
1489 	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
1490 	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1491 	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
1492 	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
1493 	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1494 	{ }
1495 };
1496 
1497 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
1498 	.name = "gcc_qupv3_wrap0_s0_clk_src",
1499 	.parent_data = gcc_parent_data_0,
1500 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1501 	.flags = CLK_SET_RATE_PARENT,
1502 	.ops = &clk_rcg2_shared_ops,
1503 };
1504 
1505 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
1506 	.cmd_rcgr = 0x17148,
1507 	.mnd_width = 16,
1508 	.hid_width = 5,
1509 	.parent_map = gcc_parent_map_0,
1510 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1511 	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
1512 };
1513 
1514 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
1515 	.name = "gcc_qupv3_wrap0_s1_clk_src",
1516 	.parent_data = gcc_parent_data_0,
1517 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1518 	.flags = CLK_SET_RATE_PARENT,
1519 	.ops = &clk_rcg2_shared_ops,
1520 };
1521 
1522 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
1523 	.cmd_rcgr = 0x17278,
1524 	.mnd_width = 16,
1525 	.hid_width = 5,
1526 	.parent_map = gcc_parent_map_0,
1527 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1528 	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
1529 };
1530 
1531 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
1532 	.name = "gcc_qupv3_wrap0_s2_clk_src",
1533 	.parent_data = gcc_parent_data_0,
1534 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1535 	.flags = CLK_SET_RATE_PARENT,
1536 	.ops = &clk_rcg2_shared_ops,
1537 };
1538 
1539 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
1540 	.cmd_rcgr = 0x173a8,
1541 	.mnd_width = 16,
1542 	.hid_width = 5,
1543 	.parent_map = gcc_parent_map_0,
1544 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1545 	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
1546 };
1547 
1548 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
1549 	.name = "gcc_qupv3_wrap0_s3_clk_src",
1550 	.parent_data = gcc_parent_data_0,
1551 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1552 	.flags = CLK_SET_RATE_PARENT,
1553 	.ops = &clk_rcg2_shared_ops,
1554 };
1555 
1556 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
1557 	.cmd_rcgr = 0x174d8,
1558 	.mnd_width = 16,
1559 	.hid_width = 5,
1560 	.parent_map = gcc_parent_map_0,
1561 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1562 	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
1563 };
1564 
1565 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
1566 	.name = "gcc_qupv3_wrap0_s4_clk_src",
1567 	.parent_data = gcc_parent_data_0,
1568 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1569 	.flags = CLK_SET_RATE_PARENT,
1570 	.ops = &clk_rcg2_shared_ops,
1571 };
1572 
1573 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
1574 	.cmd_rcgr = 0x17608,
1575 	.mnd_width = 16,
1576 	.hid_width = 5,
1577 	.parent_map = gcc_parent_map_0,
1578 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1579 	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
1580 };
1581 
1582 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
1583 	.name = "gcc_qupv3_wrap0_s5_clk_src",
1584 	.parent_data = gcc_parent_data_0,
1585 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1586 	.flags = CLK_SET_RATE_PARENT,
1587 	.ops = &clk_rcg2_shared_ops,
1588 };
1589 
1590 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
1591 	.cmd_rcgr = 0x17738,
1592 	.mnd_width = 16,
1593 	.hid_width = 5,
1594 	.parent_map = gcc_parent_map_0,
1595 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1596 	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
1597 };
1598 
1599 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s6_clk_src[] = {
1600 	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
1601 	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
1602 	F(19200000, P_BI_TCXO, 1, 0, 0),
1603 	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
1604 	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
1605 	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
1606 	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
1607 	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1608 	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
1609 	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
1610 	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1611 	{ }
1612 };
1613 
1614 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
1615 	.name = "gcc_qupv3_wrap0_s6_clk_src",
1616 	.parent_data = gcc_parent_data_0,
1617 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1618 	.flags = CLK_SET_RATE_PARENT,
1619 	.ops = &clk_rcg2_shared_ops,
1620 };
1621 
1622 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
1623 	.cmd_rcgr = 0x17868,
1624 	.mnd_width = 16,
1625 	.hid_width = 5,
1626 	.parent_map = gcc_parent_map_0,
1627 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src,
1628 	.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
1629 };
1630 
1631 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
1632 	.name = "gcc_qupv3_wrap0_s7_clk_src",
1633 	.parent_data = gcc_parent_data_0,
1634 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1635 	.flags = CLK_SET_RATE_PARENT,
1636 	.ops = &clk_rcg2_shared_ops,
1637 };
1638 
1639 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
1640 	.cmd_rcgr = 0x17998,
1641 	.mnd_width = 16,
1642 	.hid_width = 5,
1643 	.parent_map = gcc_parent_map_0,
1644 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src,
1645 	.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
1646 };
1647 
1648 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
1649 	.name = "gcc_qupv3_wrap1_s0_clk_src",
1650 	.parent_data = gcc_parent_data_0,
1651 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1652 	.flags = CLK_SET_RATE_PARENT,
1653 	.ops = &clk_rcg2_shared_ops,
1654 };
1655 
1656 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
1657 	.cmd_rcgr = 0x18148,
1658 	.mnd_width = 16,
1659 	.hid_width = 5,
1660 	.parent_map = gcc_parent_map_0,
1661 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1662 	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
1663 };
1664 
1665 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
1666 	.name = "gcc_qupv3_wrap1_s1_clk_src",
1667 	.parent_data = gcc_parent_data_0,
1668 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1669 	.flags = CLK_SET_RATE_PARENT,
1670 	.ops = &clk_rcg2_shared_ops,
1671 };
1672 
1673 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
1674 	.cmd_rcgr = 0x18278,
1675 	.mnd_width = 16,
1676 	.hid_width = 5,
1677 	.parent_map = gcc_parent_map_0,
1678 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1679 	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
1680 };
1681 
1682 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
1683 	.name = "gcc_qupv3_wrap1_s2_clk_src",
1684 	.parent_data = gcc_parent_data_0,
1685 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1686 	.flags = CLK_SET_RATE_PARENT,
1687 	.ops = &clk_rcg2_shared_ops,
1688 };
1689 
1690 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
1691 	.cmd_rcgr = 0x183a8,
1692 	.mnd_width = 16,
1693 	.hid_width = 5,
1694 	.parent_map = gcc_parent_map_0,
1695 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1696 	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
1697 };
1698 
1699 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
1700 	.name = "gcc_qupv3_wrap1_s3_clk_src",
1701 	.parent_data = gcc_parent_data_0,
1702 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1703 	.flags = CLK_SET_RATE_PARENT,
1704 	.ops = &clk_rcg2_shared_ops,
1705 };
1706 
1707 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
1708 	.cmd_rcgr = 0x184d8,
1709 	.mnd_width = 16,
1710 	.hid_width = 5,
1711 	.parent_map = gcc_parent_map_0,
1712 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1713 	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
1714 };
1715 
1716 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
1717 	.name = "gcc_qupv3_wrap1_s4_clk_src",
1718 	.parent_data = gcc_parent_data_0,
1719 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1720 	.flags = CLK_SET_RATE_PARENT,
1721 	.ops = &clk_rcg2_shared_ops,
1722 };
1723 
1724 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
1725 	.cmd_rcgr = 0x18608,
1726 	.mnd_width = 16,
1727 	.hid_width = 5,
1728 	.parent_map = gcc_parent_map_0,
1729 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1730 	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
1731 };
1732 
1733 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
1734 	.name = "gcc_qupv3_wrap1_s5_clk_src",
1735 	.parent_data = gcc_parent_data_0,
1736 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1737 	.flags = CLK_SET_RATE_PARENT,
1738 	.ops = &clk_rcg2_shared_ops,
1739 };
1740 
1741 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
1742 	.cmd_rcgr = 0x18738,
1743 	.mnd_width = 16,
1744 	.hid_width = 5,
1745 	.parent_map = gcc_parent_map_0,
1746 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1747 	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
1748 };
1749 
1750 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
1751 	.name = "gcc_qupv3_wrap1_s6_clk_src",
1752 	.parent_data = gcc_parent_data_0,
1753 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1754 	.flags = CLK_SET_RATE_PARENT,
1755 	.ops = &clk_rcg2_shared_ops,
1756 };
1757 
1758 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
1759 	.cmd_rcgr = 0x18868,
1760 	.mnd_width = 16,
1761 	.hid_width = 5,
1762 	.parent_map = gcc_parent_map_0,
1763 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src,
1764 	.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
1765 };
1766 
1767 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
1768 	.name = "gcc_qupv3_wrap1_s7_clk_src",
1769 	.parent_data = gcc_parent_data_0,
1770 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1771 	.flags = CLK_SET_RATE_PARENT,
1772 	.ops = &clk_rcg2_shared_ops,
1773 };
1774 
1775 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
1776 	.cmd_rcgr = 0x18998,
1777 	.mnd_width = 16,
1778 	.hid_width = 5,
1779 	.parent_map = gcc_parent_map_0,
1780 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src,
1781 	.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
1782 };
1783 
1784 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
1785 	.name = "gcc_qupv3_wrap2_s0_clk_src",
1786 	.parent_data = gcc_parent_data_0,
1787 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1788 	.flags = CLK_SET_RATE_PARENT,
1789 	.ops = &clk_rcg2_shared_ops,
1790 };
1791 
1792 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
1793 	.cmd_rcgr = 0x1e148,
1794 	.mnd_width = 16,
1795 	.hid_width = 5,
1796 	.parent_map = gcc_parent_map_0,
1797 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1798 	.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
1799 };
1800 
1801 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
1802 	.name = "gcc_qupv3_wrap2_s1_clk_src",
1803 	.parent_data = gcc_parent_data_0,
1804 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1805 	.flags = CLK_SET_RATE_PARENT,
1806 	.ops = &clk_rcg2_shared_ops,
1807 };
1808 
1809 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
1810 	.cmd_rcgr = 0x1e278,
1811 	.mnd_width = 16,
1812 	.hid_width = 5,
1813 	.parent_map = gcc_parent_map_0,
1814 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1815 	.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
1816 };
1817 
1818 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
1819 	.name = "gcc_qupv3_wrap2_s2_clk_src",
1820 	.parent_data = gcc_parent_data_0,
1821 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1822 	.flags = CLK_SET_RATE_PARENT,
1823 	.ops = &clk_rcg2_shared_ops,
1824 };
1825 
1826 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
1827 	.cmd_rcgr = 0x1e3a8,
1828 	.mnd_width = 16,
1829 	.hid_width = 5,
1830 	.parent_map = gcc_parent_map_0,
1831 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1832 	.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
1833 };
1834 
1835 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
1836 	.name = "gcc_qupv3_wrap2_s3_clk_src",
1837 	.parent_data = gcc_parent_data_0,
1838 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1839 	.flags = CLK_SET_RATE_PARENT,
1840 	.ops = &clk_rcg2_shared_ops,
1841 };
1842 
1843 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
1844 	.cmd_rcgr = 0x1e4d8,
1845 	.mnd_width = 16,
1846 	.hid_width = 5,
1847 	.parent_map = gcc_parent_map_0,
1848 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1849 	.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
1850 };
1851 
1852 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
1853 	.name = "gcc_qupv3_wrap2_s4_clk_src",
1854 	.parent_data = gcc_parent_data_0,
1855 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1856 	.flags = CLK_SET_RATE_PARENT,
1857 	.ops = &clk_rcg2_shared_ops,
1858 };
1859 
1860 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
1861 	.cmd_rcgr = 0x1e608,
1862 	.mnd_width = 16,
1863 	.hid_width = 5,
1864 	.parent_map = gcc_parent_map_0,
1865 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1866 	.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
1867 };
1868 
1869 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
1870 	.name = "gcc_qupv3_wrap2_s5_clk_src",
1871 	.parent_data = gcc_parent_data_0,
1872 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1873 	.flags = CLK_SET_RATE_PARENT,
1874 	.ops = &clk_rcg2_shared_ops,
1875 };
1876 
1877 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
1878 	.cmd_rcgr = 0x1e738,
1879 	.mnd_width = 16,
1880 	.hid_width = 5,
1881 	.parent_map = gcc_parent_map_0,
1882 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1883 	.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
1884 };
1885 
1886 static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
1887 	.name = "gcc_qupv3_wrap2_s6_clk_src",
1888 	.parent_data = gcc_parent_data_0,
1889 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1890 	.flags = CLK_SET_RATE_PARENT,
1891 	.ops = &clk_rcg2_shared_ops,
1892 };
1893 
1894 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
1895 	.cmd_rcgr = 0x1e868,
1896 	.mnd_width = 16,
1897 	.hid_width = 5,
1898 	.parent_map = gcc_parent_map_0,
1899 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src,
1900 	.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
1901 };
1902 
1903 static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
1904 	.name = "gcc_qupv3_wrap2_s7_clk_src",
1905 	.parent_data = gcc_parent_data_0,
1906 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1907 	.flags = CLK_SET_RATE_PARENT,
1908 	.ops = &clk_rcg2_shared_ops,
1909 };
1910 
1911 static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
1912 	.cmd_rcgr = 0x1e998,
1913 	.mnd_width = 16,
1914 	.hid_width = 5,
1915 	.parent_map = gcc_parent_map_0,
1916 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src,
1917 	.clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init,
1918 };
1919 
1920 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
1921 	F(400000, P_BI_TCXO, 12, 1, 4),
1922 	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1923 	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1924 	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1925 	F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1926 	{ }
1927 };
1928 
1929 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
1930 	.cmd_rcgr = 0x1400c,
1931 	.mnd_width = 8,
1932 	.hid_width = 5,
1933 	.parent_map = gcc_parent_map_15,
1934 	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
1935 	.clkr.hw.init = &(const struct clk_init_data) {
1936 		.name = "gcc_sdcc2_apps_clk_src",
1937 		.parent_data = gcc_parent_data_15,
1938 		.num_parents = ARRAY_SIZE(gcc_parent_data_15),
1939 		.ops = &clk_rcg2_shared_ops,
1940 	},
1941 };
1942 
1943 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
1944 	F(400000, P_BI_TCXO, 12, 1, 4),
1945 	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1946 	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1947 	{ }
1948 };
1949 
1950 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
1951 	.cmd_rcgr = 0x1600c,
1952 	.mnd_width = 8,
1953 	.hid_width = 5,
1954 	.parent_map = gcc_parent_map_0,
1955 	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
1956 	.clkr.hw.init = &(const struct clk_init_data) {
1957 		.name = "gcc_sdcc4_apps_clk_src",
1958 		.parent_data = gcc_parent_data_0,
1959 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1960 		.ops = &clk_rcg2_shared_ops,
1961 	},
1962 };
1963 
1964 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
1965 	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1966 	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1967 	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1968 	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1969 	{ }
1970 };
1971 
1972 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
1973 	.cmd_rcgr = 0x75024,
1974 	.mnd_width = 8,
1975 	.hid_width = 5,
1976 	.parent_map = gcc_parent_map_0,
1977 	.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
1978 	.clkr.hw.init = &(const struct clk_init_data) {
1979 		.name = "gcc_ufs_card_axi_clk_src",
1980 		.parent_data = gcc_parent_data_0,
1981 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1982 		.ops = &clk_rcg2_shared_ops,
1983 	},
1984 };
1985 
1986 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
1987 	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1988 	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1989 	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1990 	{ }
1991 };
1992 
1993 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
1994 	.cmd_rcgr = 0x7506c,
1995 	.mnd_width = 0,
1996 	.hid_width = 5,
1997 	.parent_map = gcc_parent_map_0,
1998 	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1999 	.clkr.hw.init = &(const struct clk_init_data) {
2000 		.name = "gcc_ufs_card_ice_core_clk_src",
2001 		.parent_data = gcc_parent_data_0,
2002 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
2003 		.ops = &clk_rcg2_shared_ops,
2004 	},
2005 };
2006 
2007 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
2008 	.cmd_rcgr = 0x750a0,
2009 	.mnd_width = 0,
2010 	.hid_width = 5,
2011 	.parent_map = gcc_parent_map_3,
2012 	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
2013 	.clkr.hw.init = &(const struct clk_init_data) {
2014 		.name = "gcc_ufs_card_phy_aux_clk_src",
2015 		.parent_data = gcc_parent_data_3,
2016 		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
2017 		.ops = &clk_rcg2_shared_ops,
2018 	},
2019 };
2020 
2021 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
2022 	.cmd_rcgr = 0x75084,
2023 	.mnd_width = 0,
2024 	.hid_width = 5,
2025 	.parent_map = gcc_parent_map_0,
2026 	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
2027 	.clkr.hw.init = &(const struct clk_init_data) {
2028 		.name = "gcc_ufs_card_unipro_core_clk_src",
2029 		.parent_data = gcc_parent_data_0,
2030 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
2031 		.ops = &clk_rcg2_shared_ops,
2032 	},
2033 };
2034 
2035 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
2036 	.cmd_rcgr = 0x77024,
2037 	.mnd_width = 8,
2038 	.hid_width = 5,
2039 	.parent_map = gcc_parent_map_0,
2040 	.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
2041 	.clkr.hw.init = &(const struct clk_init_data) {
2042 		.name = "gcc_ufs_phy_axi_clk_src",
2043 		.parent_data = gcc_parent_data_0,
2044 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
2045 		.ops = &clk_rcg2_shared_ops,
2046 	},
2047 };
2048 
2049 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
2050 	.cmd_rcgr = 0x7706c,
2051 	.mnd_width = 0,
2052 	.hid_width = 5,
2053 	.parent_map = gcc_parent_map_0,
2054 	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
2055 	.clkr.hw.init = &(const struct clk_init_data) {
2056 		.name = "gcc_ufs_phy_ice_core_clk_src",
2057 		.parent_data = gcc_parent_data_0,
2058 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
2059 		.ops = &clk_rcg2_shared_ops,
2060 	},
2061 };
2062 
2063 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
2064 	.cmd_rcgr = 0x770a0,
2065 	.mnd_width = 0,
2066 	.hid_width = 5,
2067 	.parent_map = gcc_parent_map_3,
2068 	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2069 	.clkr.hw.init = &(const struct clk_init_data) {
2070 		.name = "gcc_ufs_phy_phy_aux_clk_src",
2071 		.parent_data = gcc_parent_data_3,
2072 		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
2073 		.ops = &clk_rcg2_shared_ops,
2074 	},
2075 };
2076 
2077 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
2078 	.cmd_rcgr = 0x77084,
2079 	.mnd_width = 0,
2080 	.hid_width = 5,
2081 	.parent_map = gcc_parent_map_0,
2082 	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
2083 	.clkr.hw.init = &(const struct clk_init_data) {
2084 		.name = "gcc_ufs_phy_unipro_core_clk_src",
2085 		.parent_data = gcc_parent_data_0,
2086 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
2087 		.ops = &clk_rcg2_shared_ops,
2088 	},
2089 };
2090 
2091 static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = {
2092 	F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
2093 	F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
2094 	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
2095 	F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
2096 	{ }
2097 };
2098 
2099 static struct clk_rcg2 gcc_usb30_mp_master_clk_src = {
2100 	.cmd_rcgr = 0xab020,
2101 	.mnd_width = 8,
2102 	.hid_width = 5,
2103 	.parent_map = gcc_parent_map_0,
2104 	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
2105 	.clkr.hw.init = &(const struct clk_init_data) {
2106 		.name = "gcc_usb30_mp_master_clk_src",
2107 		.parent_data = gcc_parent_data_0,
2108 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
2109 		.ops = &clk_rcg2_shared_ops,
2110 	},
2111 };
2112 
2113 static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = {
2114 	.cmd_rcgr = 0xab038,
2115 	.mnd_width = 0,
2116 	.hid_width = 5,
2117 	.parent_map = gcc_parent_map_0,
2118 	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
2119 	.clkr.hw.init = &(const struct clk_init_data) {
2120 		.name = "gcc_usb30_mp_mock_utmi_clk_src",
2121 		.parent_data = gcc_parent_data_0,
2122 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
2123 		.ops = &clk_rcg2_shared_ops,
2124 	},
2125 };
2126 
2127 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
2128 	.cmd_rcgr = 0xf020,
2129 	.mnd_width = 8,
2130 	.hid_width = 5,
2131 	.parent_map = gcc_parent_map_0,
2132 	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
2133 	.clkr.hw.init = &(const struct clk_init_data) {
2134 		.name = "gcc_usb30_prim_master_clk_src",
2135 		.parent_data = gcc_parent_data_0,
2136 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
2137 		.ops = &clk_rcg2_shared_ops,
2138 	},
2139 };
2140 
2141 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
2142 	.cmd_rcgr = 0xf038,
2143 	.mnd_width = 0,
2144 	.hid_width = 5,
2145 	.parent_map = gcc_parent_map_0,
2146 	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
2147 	.clkr.hw.init = &(const struct clk_init_data) {
2148 		.name = "gcc_usb30_prim_mock_utmi_clk_src",
2149 		.parent_data = gcc_parent_data_0,
2150 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
2151 		.ops = &clk_rcg2_shared_ops,
2152 	},
2153 };
2154 
2155 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
2156 	.cmd_rcgr = 0x10020,
2157 	.mnd_width = 8,
2158 	.hid_width = 5,
2159 	.parent_map = gcc_parent_map_0,
2160 	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
2161 	.clkr.hw.init = &(const struct clk_init_data) {
2162 		.name = "gcc_usb30_sec_master_clk_src",
2163 		.parent_data = gcc_parent_data_0,
2164 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
2165 		.ops = &clk_rcg2_shared_ops,
2166 	},
2167 };
2168 
2169 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
2170 	.cmd_rcgr = 0x10038,
2171 	.mnd_width = 0,
2172 	.hid_width = 5,
2173 	.parent_map = gcc_parent_map_0,
2174 	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
2175 	.clkr.hw.init = &(const struct clk_init_data) {
2176 		.name = "gcc_usb30_sec_mock_utmi_clk_src",
2177 		.parent_data = gcc_parent_data_0,
2178 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
2179 		.ops = &clk_rcg2_shared_ops,
2180 	},
2181 };
2182 
2183 static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = {
2184 	.cmd_rcgr = 0xab06c,
2185 	.mnd_width = 0,
2186 	.hid_width = 5,
2187 	.parent_map = gcc_parent_map_1,
2188 	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
2189 	.clkr.hw.init = &(const struct clk_init_data) {
2190 		.name = "gcc_usb3_mp_phy_aux_clk_src",
2191 		.parent_data = gcc_parent_data_1,
2192 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2193 		.ops = &clk_rcg2_shared_ops,
2194 	},
2195 };
2196 
2197 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
2198 	.cmd_rcgr = 0xf068,
2199 	.mnd_width = 0,
2200 	.hid_width = 5,
2201 	.parent_map = gcc_parent_map_1,
2202 	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
2203 	.clkr.hw.init = &(const struct clk_init_data) {
2204 		.name = "gcc_usb3_prim_phy_aux_clk_src",
2205 		.parent_data = gcc_parent_data_1,
2206 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2207 		.ops = &clk_rcg2_shared_ops,
2208 	},
2209 };
2210 
2211 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
2212 	.cmd_rcgr = 0x10068,
2213 	.mnd_width = 0,
2214 	.hid_width = 5,
2215 	.parent_map = gcc_parent_map_1,
2216 	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
2217 	.clkr.hw.init = &(const struct clk_init_data) {
2218 		.name = "gcc_usb3_sec_phy_aux_clk_src",
2219 		.parent_data = gcc_parent_data_1,
2220 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2221 		.ops = &clk_rcg2_shared_ops,
2222 	},
2223 };
2224 
2225 static const struct freq_tbl ftbl_gcc_usb4_1_master_clk_src[] = {
2226 	F(85714286, P_GCC_GPLL0_OUT_EVEN, 3.5, 0, 0),
2227 	F(175000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
2228 	F(350000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
2229 	{ }
2230 };
2231 
2232 static struct clk_rcg2 gcc_usb4_1_master_clk_src = {
2233 	.cmd_rcgr = 0xb8018,
2234 	.mnd_width = 8,
2235 	.hid_width = 5,
2236 	.parent_map = gcc_parent_map_5,
2237 	.freq_tbl = ftbl_gcc_usb4_1_master_clk_src,
2238 	.clkr.hw.init = &(const struct clk_init_data) {
2239 		.name = "gcc_usb4_1_master_clk_src",
2240 		.parent_data = gcc_parent_data_5,
2241 		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
2242 		.ops = &clk_rcg2_shared_ops,
2243 	},
2244 };
2245 
2246 static const struct freq_tbl ftbl_gcc_usb4_1_phy_pcie_pipe_clk_src[] = {
2247 	F(19200000, P_BI_TCXO, 1, 0, 0),
2248 	F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
2249 	F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0),
2250 	{ }
2251 };
2252 
2253 static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src = {
2254 	.cmd_rcgr = 0xb80c4,
2255 	.mnd_width = 0,
2256 	.hid_width = 5,
2257 	.parent_map = gcc_parent_map_6,
2258 	.freq_tbl = ftbl_gcc_usb4_1_phy_pcie_pipe_clk_src,
2259 	.clkr.hw.init = &(const struct clk_init_data) {
2260 		.name = "gcc_usb4_1_phy_pcie_pipe_clk_src",
2261 		.parent_data = gcc_parent_data_6,
2262 		.num_parents = ARRAY_SIZE(gcc_parent_data_6),
2263 		.ops = &clk_rcg2_shared_ops,
2264 	},
2265 };
2266 
2267 static struct clk_rcg2 gcc_usb4_1_sb_if_clk_src = {
2268 	.cmd_rcgr = 0xb8070,
2269 	.mnd_width = 0,
2270 	.hid_width = 5,
2271 	.parent_map = gcc_parent_map_1,
2272 	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
2273 	.clkr.hw.init = &(const struct clk_init_data) {
2274 		.name = "gcc_usb4_1_sb_if_clk_src",
2275 		.parent_data = gcc_parent_data_1,
2276 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2277 		.ops = &clk_rcg2_shared_ops,
2278 	},
2279 };
2280 
2281 static const struct freq_tbl ftbl_gcc_usb4_1_tmu_clk_src[] = {
2282 	F(19200000, P_BI_TCXO, 1, 0, 0),
2283 	F(250000000, P_GCC_GPLL2_OUT_MAIN, 4, 0, 0),
2284 	{ }
2285 };
2286 
2287 static struct clk_rcg2 gcc_usb4_1_tmu_clk_src = {
2288 	.cmd_rcgr = 0xb8054,
2289 	.mnd_width = 0,
2290 	.hid_width = 5,
2291 	.parent_map = gcc_parent_map_7,
2292 	.freq_tbl = ftbl_gcc_usb4_1_tmu_clk_src,
2293 	.clkr.hw.init = &(const struct clk_init_data) {
2294 		.name = "gcc_usb4_1_tmu_clk_src",
2295 		.parent_data = gcc_parent_data_7,
2296 		.num_parents = ARRAY_SIZE(gcc_parent_data_7),
2297 		.ops = &clk_rcg2_shared_ops,
2298 	},
2299 };
2300 
2301 static struct clk_rcg2 gcc_usb4_master_clk_src = {
2302 	.cmd_rcgr = 0x2a018,
2303 	.mnd_width = 8,
2304 	.hid_width = 5,
2305 	.parent_map = gcc_parent_map_5,
2306 	.freq_tbl = ftbl_gcc_usb4_1_master_clk_src,
2307 	.clkr.hw.init = &(const struct clk_init_data) {
2308 		.name = "gcc_usb4_master_clk_src",
2309 		.parent_data = gcc_parent_data_5,
2310 		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
2311 		.ops = &clk_rcg2_shared_ops,
2312 	},
2313 };
2314 
2315 static struct clk_rcg2 gcc_usb4_phy_pcie_pipe_clk_src = {
2316 	.cmd_rcgr = 0x2a0c4,
2317 	.mnd_width = 0,
2318 	.hid_width = 5,
2319 	.parent_map = gcc_parent_map_6,
2320 	.freq_tbl = ftbl_gcc_usb4_1_phy_pcie_pipe_clk_src,
2321 	.clkr.hw.init = &(const struct clk_init_data) {
2322 		.name = "gcc_usb4_phy_pcie_pipe_clk_src",
2323 		.parent_data = gcc_parent_data_6,
2324 		.num_parents = ARRAY_SIZE(gcc_parent_data_6),
2325 		.ops = &clk_rcg2_shared_ops,
2326 	},
2327 };
2328 
2329 static struct clk_rcg2 gcc_usb4_sb_if_clk_src = {
2330 	.cmd_rcgr = 0x2a070,
2331 	.mnd_width = 0,
2332 	.hid_width = 5,
2333 	.parent_map = gcc_parent_map_1,
2334 	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
2335 	.clkr.hw.init = &(const struct clk_init_data) {
2336 		.name = "gcc_usb4_sb_if_clk_src",
2337 		.parent_data = gcc_parent_data_1,
2338 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2339 		.ops = &clk_rcg2_shared_ops,
2340 	},
2341 };
2342 
2343 static struct clk_rcg2 gcc_usb4_tmu_clk_src = {
2344 	.cmd_rcgr = 0x2a054,
2345 	.mnd_width = 0,
2346 	.hid_width = 5,
2347 	.parent_map = gcc_parent_map_7,
2348 	.freq_tbl = ftbl_gcc_usb4_1_tmu_clk_src,
2349 	.clkr.hw.init = &(const struct clk_init_data) {
2350 		.name = "gcc_usb4_tmu_clk_src",
2351 		.parent_data = gcc_parent_data_7,
2352 		.num_parents = ARRAY_SIZE(gcc_parent_data_7),
2353 		.ops = &clk_rcg2_shared_ops,
2354 	},
2355 };
2356 
2357 static struct clk_regmap_div gcc_pcie_2a_pipe_div_clk_src = {
2358 	.reg = 0x9d060,
2359 	.shift = 0,
2360 	.width = 4,
2361 	.clkr.hw.init = &(const struct clk_init_data) {
2362 		.name = "gcc_pcie_2a_pipe_div_clk_src",
2363 		.parent_hws = (const struct clk_hw*[]){
2364 			&gcc_pcie_2a_pipe_clk_src.clkr.hw,
2365 		},
2366 		.num_parents = 1,
2367 		.flags = CLK_SET_RATE_PARENT,
2368 		.ops = &clk_regmap_div_ro_ops,
2369 	},
2370 };
2371 
2372 static struct clk_regmap_div gcc_pcie_2b_pipe_div_clk_src = {
2373 	.reg = 0x9e060,
2374 	.shift = 0,
2375 	.width = 4,
2376 	.clkr.hw.init = &(const struct clk_init_data) {
2377 		.name = "gcc_pcie_2b_pipe_div_clk_src",
2378 		.parent_hws = (const struct clk_hw*[]){
2379 			&gcc_pcie_2b_pipe_clk_src.clkr.hw,
2380 		},
2381 		.num_parents = 1,
2382 		.flags = CLK_SET_RATE_PARENT,
2383 		.ops = &clk_regmap_div_ro_ops,
2384 	},
2385 };
2386 
2387 static struct clk_regmap_div gcc_pcie_3a_pipe_div_clk_src = {
2388 	.reg = 0xa0060,
2389 	.shift = 0,
2390 	.width = 4,
2391 	.clkr.hw.init = &(const struct clk_init_data) {
2392 		.name = "gcc_pcie_3a_pipe_div_clk_src",
2393 		.parent_hws = (const struct clk_hw*[]){
2394 			&gcc_pcie_3a_pipe_clk_src.clkr.hw,
2395 		},
2396 		.num_parents = 1,
2397 		.flags = CLK_SET_RATE_PARENT,
2398 		.ops = &clk_regmap_div_ro_ops,
2399 	},
2400 };
2401 
2402 static struct clk_regmap_div gcc_pcie_3b_pipe_div_clk_src = {
2403 	.reg = 0xa2060,
2404 	.shift = 0,
2405 	.width = 4,
2406 	.clkr.hw.init = &(const struct clk_init_data) {
2407 		.name = "gcc_pcie_3b_pipe_div_clk_src",
2408 		.parent_hws = (const struct clk_hw*[]){
2409 			&gcc_pcie_3b_pipe_clk_src.clkr.hw,
2410 		},
2411 		.num_parents = 1,
2412 		.flags = CLK_SET_RATE_PARENT,
2413 		.ops = &clk_regmap_div_ro_ops,
2414 	},
2415 };
2416 
2417 static struct clk_regmap_div gcc_pcie_4_pipe_div_clk_src = {
2418 	.reg = 0x6b060,
2419 	.shift = 0,
2420 	.width = 4,
2421 	.clkr.hw.init = &(const struct clk_init_data) {
2422 		.name = "gcc_pcie_4_pipe_div_clk_src",
2423 		.parent_hws = (const struct clk_hw*[]){
2424 			&gcc_pcie_4_pipe_clk_src.clkr.hw,
2425 		},
2426 		.num_parents = 1,
2427 		.flags = CLK_SET_RATE_PARENT,
2428 		.ops = &clk_regmap_div_ro_ops,
2429 	},
2430 };
2431 
2432 static struct clk_regmap_div gcc_qupv3_wrap0_s4_div_clk_src = {
2433 	.reg = 0x17ac8,
2434 	.shift = 0,
2435 	.width = 4,
2436 	.clkr.hw.init = &(const struct clk_init_data) {
2437 		.name = "gcc_qupv3_wrap0_s4_div_clk_src",
2438 		.parent_hws = (const struct clk_hw*[]){
2439 			&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2440 		},
2441 		.num_parents = 1,
2442 		.flags = CLK_SET_RATE_PARENT,
2443 		.ops = &clk_regmap_div_ro_ops,
2444 	},
2445 };
2446 
2447 static struct clk_regmap_div gcc_qupv3_wrap1_s4_div_clk_src = {
2448 	.reg = 0x18ac8,
2449 	.shift = 0,
2450 	.width = 4,
2451 	.clkr.hw.init = &(const struct clk_init_data) {
2452 		.name = "gcc_qupv3_wrap1_s4_div_clk_src",
2453 		.parent_hws = (const struct clk_hw*[]){
2454 			&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2455 		},
2456 		.num_parents = 1,
2457 		.flags = CLK_SET_RATE_PARENT,
2458 		.ops = &clk_regmap_div_ro_ops,
2459 	},
2460 };
2461 
2462 static struct clk_regmap_div gcc_qupv3_wrap2_s4_div_clk_src = {
2463 	.reg = 0x1eac8,
2464 	.shift = 0,
2465 	.width = 4,
2466 	.clkr.hw.init = &(const struct clk_init_data) {
2467 		.name = "gcc_qupv3_wrap2_s4_div_clk_src",
2468 		.parent_hws = (const struct clk_hw*[]){
2469 			&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
2470 		},
2471 		.num_parents = 1,
2472 		.flags = CLK_SET_RATE_PARENT,
2473 		.ops = &clk_regmap_div_ro_ops,
2474 	},
2475 };
2476 
2477 static struct clk_regmap_div gcc_usb30_mp_mock_utmi_postdiv_clk_src = {
2478 	.reg = 0xab050,
2479 	.shift = 0,
2480 	.width = 4,
2481 	.clkr.hw.init = &(const struct clk_init_data) {
2482 		.name = "gcc_usb30_mp_mock_utmi_postdiv_clk_src",
2483 		.parent_hws = (const struct clk_hw*[]){
2484 			&gcc_usb30_mp_mock_utmi_clk_src.clkr.hw,
2485 		},
2486 		.num_parents = 1,
2487 		.flags = CLK_SET_RATE_PARENT,
2488 		.ops = &clk_regmap_div_ro_ops,
2489 	},
2490 };
2491 
2492 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
2493 	.reg = 0xf050,
2494 	.shift = 0,
2495 	.width = 4,
2496 	.clkr.hw.init = &(const struct clk_init_data) {
2497 		.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
2498 		.parent_hws = (const struct clk_hw*[]){
2499 			&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
2500 		},
2501 		.num_parents = 1,
2502 		.flags = CLK_SET_RATE_PARENT,
2503 		.ops = &clk_regmap_div_ro_ops,
2504 	},
2505 };
2506 
2507 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
2508 	.reg = 0x10050,
2509 	.shift = 0,
2510 	.width = 4,
2511 	.clkr.hw.init = &(const struct clk_init_data) {
2512 		.name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
2513 		.parent_hws = (const struct clk_hw*[]){
2514 			&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
2515 		},
2516 		.num_parents = 1,
2517 		.flags = CLK_SET_RATE_PARENT,
2518 		.ops = &clk_regmap_div_ro_ops,
2519 	},
2520 };
2521 
2522 static struct clk_branch gcc_aggre_noc_pcie0_tunnel_axi_clk = {
2523 	.halt_reg = 0xa41a8,
2524 	.halt_check = BRANCH_HALT_SKIP,
2525 	.hwcg_reg = 0xa41a8,
2526 	.hwcg_bit = 1,
2527 	.clkr = {
2528 		.enable_reg = 0x52018,
2529 		.enable_mask = BIT(14),
2530 		.hw.init = &(const struct clk_init_data) {
2531 			.name = "gcc_aggre_noc_pcie0_tunnel_axi_clk",
2532 			.ops = &clk_branch2_ops,
2533 		},
2534 	},
2535 };
2536 
2537 static struct clk_branch gcc_aggre_noc_pcie1_tunnel_axi_clk = {
2538 	.halt_reg = 0x8d07c,
2539 	.halt_check = BRANCH_HALT_SKIP,
2540 	.hwcg_reg = 0x8d07c,
2541 	.hwcg_bit = 1,
2542 	.clkr = {
2543 		.enable_reg = 0x52018,
2544 		.enable_mask = BIT(21),
2545 		.hw.init = &(const struct clk_init_data) {
2546 			.name = "gcc_aggre_noc_pcie1_tunnel_axi_clk",
2547 			.ops = &clk_branch2_ops,
2548 		},
2549 	},
2550 };
2551 
2552 static struct clk_branch gcc_aggre_noc_pcie_4_axi_clk = {
2553 	.halt_reg = 0x6b1b8,
2554 	.halt_check = BRANCH_HALT_SKIP,
2555 	.hwcg_reg = 0x6b1b8,
2556 	.hwcg_bit = 1,
2557 	.clkr = {
2558 		.enable_reg = 0x52000,
2559 		.enable_mask = BIT(12),
2560 		.hw.init = &(const struct clk_init_data) {
2561 			.name = "gcc_aggre_noc_pcie_4_axi_clk",
2562 			.ops = &clk_branch2_ops,
2563 		},
2564 	},
2565 };
2566 
2567 static struct clk_branch gcc_aggre_noc_pcie_south_sf_axi_clk = {
2568 	.halt_reg = 0xbf13c,
2569 	.halt_check = BRANCH_HALT_SKIP,
2570 	.hwcg_reg = 0xbf13c,
2571 	.hwcg_bit = 1,
2572 	.clkr = {
2573 		.enable_reg = 0x52018,
2574 		.enable_mask = BIT(13),
2575 		.hw.init = &(const struct clk_init_data) {
2576 			.name = "gcc_aggre_noc_pcie_south_sf_axi_clk",
2577 			.ops = &clk_branch2_ops,
2578 		},
2579 	},
2580 };
2581 
2582 static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
2583 	.halt_reg = 0x750cc,
2584 	.halt_check = BRANCH_HALT_VOTED,
2585 	.hwcg_reg = 0x750cc,
2586 	.hwcg_bit = 1,
2587 	.clkr = {
2588 		.enable_reg = 0x750cc,
2589 		.enable_mask = BIT(0),
2590 		.hw.init = &(const struct clk_init_data) {
2591 			.name = "gcc_aggre_ufs_card_axi_clk",
2592 			.parent_hws = (const struct clk_hw*[]){
2593 				&gcc_ufs_card_axi_clk_src.clkr.hw,
2594 			},
2595 			.num_parents = 1,
2596 			.flags = CLK_SET_RATE_PARENT,
2597 			.ops = &clk_branch2_ops,
2598 		},
2599 	},
2600 };
2601 
2602 static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
2603 	.halt_reg = 0x750cc,
2604 	.halt_check = BRANCH_HALT_VOTED,
2605 	.hwcg_reg = 0x750cc,
2606 	.hwcg_bit = 1,
2607 	.clkr = {
2608 		.enable_reg = 0x750cc,
2609 		.enable_mask = BIT(1),
2610 		.hw.init = &(const struct clk_init_data) {
2611 			.name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
2612 			.parent_hws = (const struct clk_hw*[]){
2613 				&gcc_ufs_card_axi_clk_src.clkr.hw,
2614 			},
2615 			.num_parents = 1,
2616 			.flags = CLK_SET_RATE_PARENT,
2617 			.ops = &clk_branch2_ops,
2618 		},
2619 	},
2620 };
2621 
2622 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
2623 	.halt_reg = 0x770cc,
2624 	.halt_check = BRANCH_HALT_VOTED,
2625 	.hwcg_reg = 0x770cc,
2626 	.hwcg_bit = 1,
2627 	.clkr = {
2628 		.enable_reg = 0x770cc,
2629 		.enable_mask = BIT(0),
2630 		.hw.init = &(const struct clk_init_data) {
2631 			.name = "gcc_aggre_ufs_phy_axi_clk",
2632 			.parent_hws = (const struct clk_hw*[]){
2633 				&gcc_ufs_phy_axi_clk_src.clkr.hw,
2634 			},
2635 			.num_parents = 1,
2636 			.flags = CLK_SET_RATE_PARENT,
2637 			.ops = &clk_branch2_ops,
2638 		},
2639 	},
2640 };
2641 
2642 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
2643 	.halt_reg = 0x770cc,
2644 	.halt_check = BRANCH_HALT_VOTED,
2645 	.hwcg_reg = 0x770cc,
2646 	.hwcg_bit = 1,
2647 	.clkr = {
2648 		.enable_reg = 0x770cc,
2649 		.enable_mask = BIT(1),
2650 		.hw.init = &(const struct clk_init_data) {
2651 			.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
2652 			.parent_hws = (const struct clk_hw*[]){
2653 				&gcc_ufs_phy_axi_clk_src.clkr.hw,
2654 			},
2655 			.num_parents = 1,
2656 			.flags = CLK_SET_RATE_PARENT,
2657 			.ops = &clk_branch2_ops,
2658 		},
2659 	},
2660 };
2661 
2662 static struct clk_branch gcc_aggre_usb3_mp_axi_clk = {
2663 	.halt_reg = 0xab084,
2664 	.halt_check = BRANCH_HALT_VOTED,
2665 	.hwcg_reg = 0xab084,
2666 	.hwcg_bit = 1,
2667 	.clkr = {
2668 		.enable_reg = 0xab084,
2669 		.enable_mask = BIT(0),
2670 		.hw.init = &(const struct clk_init_data) {
2671 			.name = "gcc_aggre_usb3_mp_axi_clk",
2672 			.parent_hws = (const struct clk_hw*[]){
2673 				&gcc_usb30_mp_master_clk_src.clkr.hw,
2674 			},
2675 			.num_parents = 1,
2676 			.flags = CLK_SET_RATE_PARENT,
2677 			.ops = &clk_branch2_ops,
2678 		},
2679 	},
2680 };
2681 
2682 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
2683 	.halt_reg = 0xf080,
2684 	.halt_check = BRANCH_HALT_VOTED,
2685 	.hwcg_reg = 0xf080,
2686 	.hwcg_bit = 1,
2687 	.clkr = {
2688 		.enable_reg = 0xf080,
2689 		.enable_mask = BIT(0),
2690 		.hw.init = &(const struct clk_init_data) {
2691 			.name = "gcc_aggre_usb3_prim_axi_clk",
2692 			.parent_hws = (const struct clk_hw*[]){
2693 				&gcc_usb30_prim_master_clk_src.clkr.hw,
2694 			},
2695 			.num_parents = 1,
2696 			.flags = CLK_SET_RATE_PARENT,
2697 			.ops = &clk_branch2_ops,
2698 		},
2699 	},
2700 };
2701 
2702 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
2703 	.halt_reg = 0x10080,
2704 	.halt_check = BRANCH_HALT_VOTED,
2705 	.hwcg_reg = 0x10080,
2706 	.hwcg_bit = 1,
2707 	.clkr = {
2708 		.enable_reg = 0x10080,
2709 		.enable_mask = BIT(0),
2710 		.hw.init = &(const struct clk_init_data) {
2711 			.name = "gcc_aggre_usb3_sec_axi_clk",
2712 			.parent_hws = (const struct clk_hw*[]){
2713 				&gcc_usb30_sec_master_clk_src.clkr.hw,
2714 			},
2715 			.num_parents = 1,
2716 			.flags = CLK_SET_RATE_PARENT,
2717 			.ops = &clk_branch2_ops,
2718 		},
2719 	},
2720 };
2721 
2722 static struct clk_branch gcc_aggre_usb4_1_axi_clk = {
2723 	.halt_reg = 0xb80e4,
2724 	.halt_check = BRANCH_HALT_VOTED,
2725 	.hwcg_reg = 0xb80e4,
2726 	.hwcg_bit = 1,
2727 	.clkr = {
2728 		.enable_reg = 0xb80e4,
2729 		.enable_mask = BIT(0),
2730 		.hw.init = &(const struct clk_init_data) {
2731 			.name = "gcc_aggre_usb4_1_axi_clk",
2732 			.parent_hws = (const struct clk_hw*[]){
2733 				&gcc_usb4_1_master_clk_src.clkr.hw,
2734 			},
2735 			.num_parents = 1,
2736 			.flags = CLK_SET_RATE_PARENT,
2737 			.ops = &clk_branch2_ops,
2738 		},
2739 	},
2740 };
2741 
2742 static struct clk_branch gcc_aggre_usb4_axi_clk = {
2743 	.halt_reg = 0x2a0e4,
2744 	.halt_check = BRANCH_HALT_VOTED,
2745 	.hwcg_reg = 0x2a0e4,
2746 	.hwcg_bit = 1,
2747 	.clkr = {
2748 		.enable_reg = 0x2a0e4,
2749 		.enable_mask = BIT(0),
2750 		.hw.init = &(const struct clk_init_data) {
2751 			.name = "gcc_aggre_usb4_axi_clk",
2752 			.parent_hws = (const struct clk_hw*[]){
2753 				&gcc_usb4_master_clk_src.clkr.hw,
2754 			},
2755 			.num_parents = 1,
2756 			.flags = CLK_SET_RATE_PARENT,
2757 			.ops = &clk_branch2_ops,
2758 		},
2759 	},
2760 };
2761 
2762 static struct clk_branch gcc_aggre_usb_noc_axi_clk = {
2763 	.halt_reg = 0x5d024,
2764 	.halt_check = BRANCH_HALT_VOTED,
2765 	.hwcg_reg = 0x5d024,
2766 	.hwcg_bit = 1,
2767 	.clkr = {
2768 		.enable_reg = 0x5d024,
2769 		.enable_mask = BIT(0),
2770 		.hw.init = &(const struct clk_init_data) {
2771 			.name = "gcc_aggre_usb_noc_axi_clk",
2772 			.ops = &clk_branch2_ops,
2773 		},
2774 	},
2775 };
2776 
2777 static struct clk_branch gcc_aggre_usb_noc_north_axi_clk = {
2778 	.halt_reg = 0x5d020,
2779 	.halt_check = BRANCH_HALT_VOTED,
2780 	.hwcg_reg = 0x5d020,
2781 	.hwcg_bit = 1,
2782 	.clkr = {
2783 		.enable_reg = 0x5d020,
2784 		.enable_mask = BIT(0),
2785 		.hw.init = &(const struct clk_init_data) {
2786 			.name = "gcc_aggre_usb_noc_north_axi_clk",
2787 			.ops = &clk_branch2_ops,
2788 		},
2789 	},
2790 };
2791 
2792 static struct clk_branch gcc_aggre_usb_noc_south_axi_clk = {
2793 	.halt_reg = 0x5d01c,
2794 	.halt_check = BRANCH_HALT_VOTED,
2795 	.hwcg_reg = 0x5d01c,
2796 	.hwcg_bit = 1,
2797 	.clkr = {
2798 		.enable_reg = 0x5d01c,
2799 		.enable_mask = BIT(0),
2800 		.hw.init = &(const struct clk_init_data) {
2801 			.name = "gcc_aggre_usb_noc_south_axi_clk",
2802 			.ops = &clk_branch2_ops,
2803 		},
2804 	},
2805 };
2806 
2807 static struct clk_branch gcc_ahb2phy0_clk = {
2808 	.halt_reg = 0x6a004,
2809 	.halt_check = BRANCH_HALT_VOTED,
2810 	.hwcg_reg = 0x6a004,
2811 	.hwcg_bit = 1,
2812 	.clkr = {
2813 		.enable_reg = 0x6a004,
2814 		.enable_mask = BIT(0),
2815 		.hw.init = &(const struct clk_init_data) {
2816 			.name = "gcc_ahb2phy0_clk",
2817 			.ops = &clk_branch2_ops,
2818 		},
2819 	},
2820 };
2821 
2822 static struct clk_branch gcc_ahb2phy2_clk = {
2823 	.halt_reg = 0x6a008,
2824 	.halt_check = BRANCH_HALT_VOTED,
2825 	.hwcg_reg = 0x6a008,
2826 	.hwcg_bit = 1,
2827 	.clkr = {
2828 		.enable_reg = 0x6a008,
2829 		.enable_mask = BIT(0),
2830 		.hw.init = &(const struct clk_init_data) {
2831 			.name = "gcc_ahb2phy2_clk",
2832 			.ops = &clk_branch2_ops,
2833 		},
2834 	},
2835 };
2836 
2837 static struct clk_branch gcc_boot_rom_ahb_clk = {
2838 	.halt_reg = 0x38004,
2839 	.halt_check = BRANCH_HALT_VOTED,
2840 	.hwcg_reg = 0x38004,
2841 	.hwcg_bit = 1,
2842 	.clkr = {
2843 		.enable_reg = 0x52000,
2844 		.enable_mask = BIT(10),
2845 		.hw.init = &(const struct clk_init_data) {
2846 			.name = "gcc_boot_rom_ahb_clk",
2847 			.ops = &clk_branch2_ops,
2848 		},
2849 	},
2850 };
2851 
2852 static struct clk_branch gcc_camera_hf_axi_clk = {
2853 	.halt_reg = 0x26010,
2854 	.halt_check = BRANCH_HALT_SKIP,
2855 	.hwcg_reg = 0x26010,
2856 	.hwcg_bit = 1,
2857 	.clkr = {
2858 		.enable_reg = 0x26010,
2859 		.enable_mask = BIT(0),
2860 		.hw.init = &(const struct clk_init_data) {
2861 			.name = "gcc_camera_hf_axi_clk",
2862 			.ops = &clk_branch2_ops,
2863 		},
2864 	},
2865 };
2866 
2867 static struct clk_branch gcc_camera_sf_axi_clk = {
2868 	.halt_reg = 0x26014,
2869 	.halt_check = BRANCH_HALT_SKIP,
2870 	.hwcg_reg = 0x26014,
2871 	.hwcg_bit = 1,
2872 	.clkr = {
2873 		.enable_reg = 0x26014,
2874 		.enable_mask = BIT(0),
2875 		.hw.init = &(const struct clk_init_data) {
2876 			.name = "gcc_camera_sf_axi_clk",
2877 			.ops = &clk_branch2_ops,
2878 		},
2879 	},
2880 };
2881 
2882 static struct clk_branch gcc_camera_throttle_nrt_axi_clk = {
2883 	.halt_reg = 0x2601c,
2884 	.halt_check = BRANCH_HALT_SKIP,
2885 	.hwcg_reg = 0x2601c,
2886 	.hwcg_bit = 1,
2887 	.clkr = {
2888 		.enable_reg = 0x2601c,
2889 		.enable_mask = BIT(0),
2890 		.hw.init = &(const struct clk_init_data) {
2891 			.name = "gcc_camera_throttle_nrt_axi_clk",
2892 			.ops = &clk_branch2_ops,
2893 		},
2894 	},
2895 };
2896 
2897 static struct clk_branch gcc_camera_throttle_rt_axi_clk = {
2898 	.halt_reg = 0x26018,
2899 	.halt_check = BRANCH_HALT_SKIP,
2900 	.hwcg_reg = 0x26018,
2901 	.hwcg_bit = 1,
2902 	.clkr = {
2903 		.enable_reg = 0x26018,
2904 		.enable_mask = BIT(0),
2905 		.hw.init = &(const struct clk_init_data) {
2906 			.name = "gcc_camera_throttle_rt_axi_clk",
2907 			.ops = &clk_branch2_ops,
2908 		},
2909 	},
2910 };
2911 
2912 static struct clk_branch gcc_camera_throttle_xo_clk = {
2913 	.halt_reg = 0x26024,
2914 	.halt_check = BRANCH_HALT,
2915 	.clkr = {
2916 		.enable_reg = 0x26024,
2917 		.enable_mask = BIT(0),
2918 		.hw.init = &(const struct clk_init_data) {
2919 			.name = "gcc_camera_throttle_xo_clk",
2920 			.ops = &clk_branch2_ops,
2921 		},
2922 	},
2923 };
2924 
2925 static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = {
2926 	.halt_reg = 0xab088,
2927 	.halt_check = BRANCH_HALT_VOTED,
2928 	.hwcg_reg = 0xab088,
2929 	.hwcg_bit = 1,
2930 	.clkr = {
2931 		.enable_reg = 0xab088,
2932 		.enable_mask = BIT(0),
2933 		.hw.init = &(const struct clk_init_data) {
2934 			.name = "gcc_cfg_noc_usb3_mp_axi_clk",
2935 			.parent_hws = (const struct clk_hw*[]){
2936 				&gcc_usb30_mp_master_clk_src.clkr.hw,
2937 			},
2938 			.num_parents = 1,
2939 			.flags = CLK_SET_RATE_PARENT,
2940 			.ops = &clk_branch2_ops,
2941 		},
2942 	},
2943 };
2944 
2945 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
2946 	.halt_reg = 0xf084,
2947 	.halt_check = BRANCH_HALT_VOTED,
2948 	.hwcg_reg = 0xf084,
2949 	.hwcg_bit = 1,
2950 	.clkr = {
2951 		.enable_reg = 0xf084,
2952 		.enable_mask = BIT(0),
2953 		.hw.init = &(const struct clk_init_data) {
2954 			.name = "gcc_cfg_noc_usb3_prim_axi_clk",
2955 			.parent_hws = (const struct clk_hw*[]){
2956 				&gcc_usb30_prim_master_clk_src.clkr.hw,
2957 			},
2958 			.num_parents = 1,
2959 			.flags = CLK_SET_RATE_PARENT,
2960 			.ops = &clk_branch2_ops,
2961 		},
2962 	},
2963 };
2964 
2965 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
2966 	.halt_reg = 0x10084,
2967 	.halt_check = BRANCH_HALT_VOTED,
2968 	.hwcg_reg = 0x10084,
2969 	.hwcg_bit = 1,
2970 	.clkr = {
2971 		.enable_reg = 0x10084,
2972 		.enable_mask = BIT(0),
2973 		.hw.init = &(const struct clk_init_data) {
2974 			.name = "gcc_cfg_noc_usb3_sec_axi_clk",
2975 			.parent_hws = (const struct clk_hw*[]){
2976 				&gcc_usb30_sec_master_clk_src.clkr.hw,
2977 			},
2978 			.num_parents = 1,
2979 			.flags = CLK_SET_RATE_PARENT,
2980 			.ops = &clk_branch2_ops,
2981 		},
2982 	},
2983 };
2984 
2985 static struct clk_branch gcc_cnoc_pcie0_tunnel_clk = {
2986 	.halt_reg = 0xa4074,
2987 	.halt_check = BRANCH_HALT_VOTED,
2988 	.clkr = {
2989 		.enable_reg = 0x52020,
2990 		.enable_mask = BIT(8),
2991 		.hw.init = &(const struct clk_init_data) {
2992 			.name = "gcc_cnoc_pcie0_tunnel_clk",
2993 			.ops = &clk_branch2_ops,
2994 		},
2995 	},
2996 };
2997 
2998 static struct clk_branch gcc_cnoc_pcie1_tunnel_clk = {
2999 	.halt_reg = 0x8d074,
3000 	.halt_check = BRANCH_HALT_VOTED,
3001 	.clkr = {
3002 		.enable_reg = 0x52020,
3003 		.enable_mask = BIT(9),
3004 		.hw.init = &(const struct clk_init_data) {
3005 			.name = "gcc_cnoc_pcie1_tunnel_clk",
3006 			.ops = &clk_branch2_ops,
3007 		},
3008 	},
3009 };
3010 
3011 static struct clk_branch gcc_cnoc_pcie4_qx_clk = {
3012 	.halt_reg = 0x6b084,
3013 	.halt_check = BRANCH_HALT_VOTED,
3014 	.hwcg_reg = 0x6b084,
3015 	.hwcg_bit = 1,
3016 	.clkr = {
3017 		.enable_reg = 0x52020,
3018 		.enable_mask = BIT(10),
3019 		.hw.init = &(const struct clk_init_data) {
3020 			.name = "gcc_cnoc_pcie4_qx_clk",
3021 			.ops = &clk_branch2_ops,
3022 		},
3023 	},
3024 };
3025 
3026 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
3027 	.halt_reg = 0x7115c,
3028 	.halt_check = BRANCH_HALT_SKIP,
3029 	.hwcg_reg = 0x7115c,
3030 	.hwcg_bit = 1,
3031 	.clkr = {
3032 		.enable_reg = 0x7115c,
3033 		.enable_mask = BIT(0),
3034 		.hw.init = &(const struct clk_init_data) {
3035 			.name = "gcc_ddrss_gpu_axi_clk",
3036 			.ops = &clk_branch2_aon_ops,
3037 		},
3038 	},
3039 };
3040 
3041 static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {
3042 	.halt_reg = 0xa602c,
3043 	.halt_check = BRANCH_HALT_SKIP,
3044 	.hwcg_reg = 0xa602c,
3045 	.hwcg_bit = 1,
3046 	.clkr = {
3047 		.enable_reg = 0x52000,
3048 		.enable_mask = BIT(19),
3049 		.hw.init = &(const struct clk_init_data) {
3050 			.name = "gcc_ddrss_pcie_sf_tbu_clk",
3051 			.ops = &clk_branch2_ops,
3052 		},
3053 	},
3054 };
3055 
3056 static struct clk_branch gcc_disp1_hf_axi_clk = {
3057 	.halt_reg = 0xbb010,
3058 	.halt_check = BRANCH_HALT_SKIP,
3059 	.hwcg_reg = 0xbb010,
3060 	.hwcg_bit = 1,
3061 	.clkr = {
3062 		.enable_reg = 0xbb010,
3063 		.enable_mask = BIT(0),
3064 		.hw.init = &(const struct clk_init_data) {
3065 			.name = "gcc_disp1_hf_axi_clk",
3066 			.ops = &clk_branch2_ops,
3067 		},
3068 	},
3069 };
3070 
3071 static struct clk_branch gcc_disp1_sf_axi_clk = {
3072 	.halt_reg = 0xbb018,
3073 	.halt_check = BRANCH_HALT_SKIP,
3074 	.hwcg_reg = 0xbb018,
3075 	.hwcg_bit = 1,
3076 	.clkr = {
3077 		.enable_reg = 0xbb018,
3078 		.enable_mask = BIT(0),
3079 		.hw.init = &(const struct clk_init_data) {
3080 			.name = "gcc_disp1_sf_axi_clk",
3081 			.ops = &clk_branch2_ops,
3082 		},
3083 	},
3084 };
3085 
3086 static struct clk_branch gcc_disp1_throttle_nrt_axi_clk = {
3087 	.halt_reg = 0xbb024,
3088 	.halt_check = BRANCH_HALT_SKIP,
3089 	.hwcg_reg = 0xbb024,
3090 	.hwcg_bit = 1,
3091 	.clkr = {
3092 		.enable_reg = 0xbb024,
3093 		.enable_mask = BIT(0),
3094 		.hw.init = &(const struct clk_init_data) {
3095 			.name = "gcc_disp1_throttle_nrt_axi_clk",
3096 			.ops = &clk_branch2_ops,
3097 		},
3098 	},
3099 };
3100 
3101 static struct clk_branch gcc_disp1_throttle_rt_axi_clk = {
3102 	.halt_reg = 0xbb020,
3103 	.halt_check = BRANCH_HALT_SKIP,
3104 	.hwcg_reg = 0xbb020,
3105 	.hwcg_bit = 1,
3106 	.clkr = {
3107 		.enable_reg = 0xbb020,
3108 		.enable_mask = BIT(0),
3109 		.hw.init = &(const struct clk_init_data) {
3110 			.name = "gcc_disp1_throttle_rt_axi_clk",
3111 			.ops = &clk_branch2_ops,
3112 		},
3113 	},
3114 };
3115 
3116 static struct clk_branch gcc_disp_hf_axi_clk = {
3117 	.halt_reg = 0x27010,
3118 	.halt_check = BRANCH_HALT_SKIP,
3119 	.hwcg_reg = 0x27010,
3120 	.hwcg_bit = 1,
3121 	.clkr = {
3122 		.enable_reg = 0x27010,
3123 		.enable_mask = BIT(0),
3124 		.hw.init = &(const struct clk_init_data) {
3125 			.name = "gcc_disp_hf_axi_clk",
3126 			.ops = &clk_branch2_ops,
3127 		},
3128 	},
3129 };
3130 
3131 static struct clk_branch gcc_disp_sf_axi_clk = {
3132 	.halt_reg = 0x27018,
3133 	.halt_check = BRANCH_HALT_SKIP,
3134 	.hwcg_reg = 0x27018,
3135 	.hwcg_bit = 1,
3136 	.clkr = {
3137 		.enable_reg = 0x27018,
3138 		.enable_mask = BIT(0),
3139 		.hw.init = &(const struct clk_init_data) {
3140 			.name = "gcc_disp_sf_axi_clk",
3141 			.ops = &clk_branch2_ops,
3142 		},
3143 	},
3144 };
3145 
3146 static struct clk_branch gcc_disp_throttle_nrt_axi_clk = {
3147 	.halt_reg = 0x27024,
3148 	.halt_check = BRANCH_HALT_SKIP,
3149 	.hwcg_reg = 0x27024,
3150 	.hwcg_bit = 1,
3151 	.clkr = {
3152 		.enable_reg = 0x27024,
3153 		.enable_mask = BIT(0),
3154 		.hw.init = &(const struct clk_init_data) {
3155 			.name = "gcc_disp_throttle_nrt_axi_clk",
3156 			.ops = &clk_branch2_ops,
3157 		},
3158 	},
3159 };
3160 
3161 static struct clk_branch gcc_disp_throttle_rt_axi_clk = {
3162 	.halt_reg = 0x27020,
3163 	.halt_check = BRANCH_HALT_SKIP,
3164 	.hwcg_reg = 0x27020,
3165 	.hwcg_bit = 1,
3166 	.clkr = {
3167 		.enable_reg = 0x27020,
3168 		.enable_mask = BIT(0),
3169 		.hw.init = &(const struct clk_init_data) {
3170 			.name = "gcc_disp_throttle_rt_axi_clk",
3171 			.ops = &clk_branch2_ops,
3172 		},
3173 	},
3174 };
3175 
3176 static struct clk_branch gcc_emac0_axi_clk = {
3177 	.halt_reg = 0xaa010,
3178 	.halt_check = BRANCH_HALT_VOTED,
3179 	.hwcg_reg = 0xaa010,
3180 	.hwcg_bit = 1,
3181 	.clkr = {
3182 		.enable_reg = 0xaa010,
3183 		.enable_mask = BIT(0),
3184 		.hw.init = &(const struct clk_init_data) {
3185 			.name = "gcc_emac0_axi_clk",
3186 			.ops = &clk_branch2_ops,
3187 		},
3188 	},
3189 };
3190 
3191 static struct clk_branch gcc_emac0_ptp_clk = {
3192 	.halt_reg = 0xaa01c,
3193 	.halt_check = BRANCH_HALT,
3194 	.clkr = {
3195 		.enable_reg = 0xaa01c,
3196 		.enable_mask = BIT(0),
3197 		.hw.init = &(const struct clk_init_data) {
3198 			.name = "gcc_emac0_ptp_clk",
3199 			.parent_hws = (const struct clk_hw*[]){
3200 				&gcc_emac0_ptp_clk_src.clkr.hw,
3201 			},
3202 			.num_parents = 1,
3203 			.flags = CLK_SET_RATE_PARENT,
3204 			.ops = &clk_branch2_ops,
3205 		},
3206 	},
3207 };
3208 
3209 static struct clk_branch gcc_emac0_rgmii_clk = {
3210 	.halt_reg = 0xaa038,
3211 	.halt_check = BRANCH_HALT,
3212 	.clkr = {
3213 		.enable_reg = 0xaa038,
3214 		.enable_mask = BIT(0),
3215 		.hw.init = &(const struct clk_init_data) {
3216 			.name = "gcc_emac0_rgmii_clk",
3217 			.parent_hws = (const struct clk_hw*[]){
3218 				&gcc_emac0_rgmii_clk_src.clkr.hw,
3219 			},
3220 			.num_parents = 1,
3221 			.flags = CLK_SET_RATE_PARENT,
3222 			.ops = &clk_branch2_ops,
3223 		},
3224 	},
3225 };
3226 
3227 static struct clk_branch gcc_emac0_slv_ahb_clk = {
3228 	.halt_reg = 0xaa018,
3229 	.halt_check = BRANCH_HALT_VOTED,
3230 	.hwcg_reg = 0xaa018,
3231 	.hwcg_bit = 1,
3232 	.clkr = {
3233 		.enable_reg = 0xaa018,
3234 		.enable_mask = BIT(0),
3235 		.hw.init = &(const struct clk_init_data) {
3236 			.name = "gcc_emac0_slv_ahb_clk",
3237 			.ops = &clk_branch2_ops,
3238 		},
3239 	},
3240 };
3241 
3242 static struct clk_branch gcc_emac1_axi_clk = {
3243 	.halt_reg = 0xba010,
3244 	.halt_check = BRANCH_HALT_VOTED,
3245 	.hwcg_reg = 0xba010,
3246 	.hwcg_bit = 1,
3247 	.clkr = {
3248 		.enable_reg = 0xba010,
3249 		.enable_mask = BIT(0),
3250 		.hw.init = &(const struct clk_init_data) {
3251 			.name = "gcc_emac1_axi_clk",
3252 			.ops = &clk_branch2_ops,
3253 		},
3254 	},
3255 };
3256 
3257 static struct clk_branch gcc_emac1_ptp_clk = {
3258 	.halt_reg = 0xba01c,
3259 	.halt_check = BRANCH_HALT,
3260 	.clkr = {
3261 		.enable_reg = 0xba01c,
3262 		.enable_mask = BIT(0),
3263 		.hw.init = &(const struct clk_init_data) {
3264 			.name = "gcc_emac1_ptp_clk",
3265 			.parent_hws = (const struct clk_hw*[]){
3266 				&gcc_emac1_ptp_clk_src.clkr.hw,
3267 			},
3268 			.num_parents = 1,
3269 			.flags = CLK_SET_RATE_PARENT,
3270 			.ops = &clk_branch2_ops,
3271 		},
3272 	},
3273 };
3274 
3275 static struct clk_branch gcc_emac1_rgmii_clk = {
3276 	.halt_reg = 0xba038,
3277 	.halt_check = BRANCH_HALT,
3278 	.clkr = {
3279 		.enable_reg = 0xba038,
3280 		.enable_mask = BIT(0),
3281 		.hw.init = &(const struct clk_init_data) {
3282 			.name = "gcc_emac1_rgmii_clk",
3283 			.parent_hws = (const struct clk_hw*[]){
3284 				&gcc_emac1_rgmii_clk_src.clkr.hw,
3285 			},
3286 			.num_parents = 1,
3287 			.flags = CLK_SET_RATE_PARENT,
3288 			.ops = &clk_branch2_ops,
3289 		},
3290 	},
3291 };
3292 
3293 static struct clk_branch gcc_emac1_slv_ahb_clk = {
3294 	.halt_reg = 0xba018,
3295 	.halt_check = BRANCH_HALT_VOTED,
3296 	.hwcg_reg = 0xba018,
3297 	.hwcg_bit = 1,
3298 	.clkr = {
3299 		.enable_reg = 0xba018,
3300 		.enable_mask = BIT(0),
3301 		.hw.init = &(const struct clk_init_data) {
3302 			.name = "gcc_emac1_slv_ahb_clk",
3303 			.ops = &clk_branch2_ops,
3304 		},
3305 	},
3306 };
3307 
3308 static struct clk_branch gcc_gp1_clk = {
3309 	.halt_reg = 0x64000,
3310 	.halt_check = BRANCH_HALT,
3311 	.clkr = {
3312 		.enable_reg = 0x64000,
3313 		.enable_mask = BIT(0),
3314 		.hw.init = &(const struct clk_init_data) {
3315 			.name = "gcc_gp1_clk",
3316 			.parent_hws = (const struct clk_hw*[]){
3317 				&gcc_gp1_clk_src.clkr.hw,
3318 			},
3319 			.num_parents = 1,
3320 			.flags = CLK_SET_RATE_PARENT,
3321 			.ops = &clk_branch2_ops,
3322 		},
3323 	},
3324 };
3325 
3326 static struct clk_branch gcc_gp2_clk = {
3327 	.halt_reg = 0x65000,
3328 	.halt_check = BRANCH_HALT,
3329 	.clkr = {
3330 		.enable_reg = 0x65000,
3331 		.enable_mask = BIT(0),
3332 		.hw.init = &(const struct clk_init_data) {
3333 			.name = "gcc_gp2_clk",
3334 			.parent_hws = (const struct clk_hw*[]){
3335 				&gcc_gp2_clk_src.clkr.hw,
3336 			},
3337 			.num_parents = 1,
3338 			.flags = CLK_SET_RATE_PARENT,
3339 			.ops = &clk_branch2_ops,
3340 		},
3341 	},
3342 };
3343 
3344 static struct clk_branch gcc_gp3_clk = {
3345 	.halt_reg = 0x66000,
3346 	.halt_check = BRANCH_HALT,
3347 	.clkr = {
3348 		.enable_reg = 0x66000,
3349 		.enable_mask = BIT(0),
3350 		.hw.init = &(const struct clk_init_data) {
3351 			.name = "gcc_gp3_clk",
3352 			.parent_hws = (const struct clk_hw*[]){
3353 				&gcc_gp3_clk_src.clkr.hw,
3354 			},
3355 			.num_parents = 1,
3356 			.flags = CLK_SET_RATE_PARENT,
3357 			.ops = &clk_branch2_ops,
3358 		},
3359 	},
3360 };
3361 
3362 static struct clk_branch gcc_gp4_clk = {
3363 	.halt_reg = 0xc2000,
3364 	.halt_check = BRANCH_HALT,
3365 	.clkr = {
3366 		.enable_reg = 0xc2000,
3367 		.enable_mask = BIT(0),
3368 		.hw.init = &(const struct clk_init_data) {
3369 			.name = "gcc_gp4_clk",
3370 			.parent_hws = (const struct clk_hw*[]){
3371 				&gcc_gp4_clk_src.clkr.hw,
3372 			},
3373 			.num_parents = 1,
3374 			.flags = CLK_SET_RATE_PARENT,
3375 			.ops = &clk_branch2_ops,
3376 		},
3377 	},
3378 };
3379 
3380 static struct clk_branch gcc_gp5_clk = {
3381 	.halt_reg = 0xc3000,
3382 	.halt_check = BRANCH_HALT,
3383 	.clkr = {
3384 		.enable_reg = 0xc3000,
3385 		.enable_mask = BIT(0),
3386 		.hw.init = &(const struct clk_init_data) {
3387 			.name = "gcc_gp5_clk",
3388 			.parent_hws = (const struct clk_hw*[]){
3389 				&gcc_gp5_clk_src.clkr.hw,
3390 			},
3391 			.num_parents = 1,
3392 			.flags = CLK_SET_RATE_PARENT,
3393 			.ops = &clk_branch2_ops,
3394 		},
3395 	},
3396 };
3397 
3398 static struct clk_branch gcc_gpu_gpll0_clk_src = {
3399 	.halt_check = BRANCH_HALT_DELAY,
3400 	.clkr = {
3401 		.enable_reg = 0x52000,
3402 		.enable_mask = BIT(15),
3403 		.hw.init = &(const struct clk_init_data) {
3404 			.name = "gcc_gpu_gpll0_clk_src",
3405 			.parent_hws = (const struct clk_hw*[]){
3406 				&gcc_gpll0.clkr.hw,
3407 			},
3408 			.num_parents = 1,
3409 			.flags = CLK_SET_RATE_PARENT,
3410 			.ops = &clk_branch2_ops,
3411 		},
3412 	},
3413 };
3414 
3415 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
3416 	.halt_check = BRANCH_HALT_DELAY,
3417 	.clkr = {
3418 		.enable_reg = 0x52000,
3419 		.enable_mask = BIT(16),
3420 		.hw.init = &(const struct clk_init_data) {
3421 			.name = "gcc_gpu_gpll0_div_clk_src",
3422 			.parent_hws = (const struct clk_hw*[]){
3423 				&gcc_gpll0_out_even.clkr.hw,
3424 			},
3425 			.num_parents = 1,
3426 			.flags = CLK_SET_RATE_PARENT,
3427 			.ops = &clk_branch2_ops,
3428 		},
3429 	},
3430 };
3431 
3432 static struct clk_branch gcc_gpu_iref_en = {
3433 	.halt_reg = 0x8c014,
3434 	.halt_check = BRANCH_HALT,
3435 	.clkr = {
3436 		.enable_reg = 0x8c014,
3437 		.enable_mask = BIT(0),
3438 		.hw.init = &(const struct clk_init_data) {
3439 			.name = "gcc_gpu_iref_en",
3440 			.ops = &clk_branch2_ops,
3441 		},
3442 	},
3443 };
3444 
3445 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
3446 	.halt_reg = 0x71010,
3447 	.halt_check = BRANCH_HALT_VOTED,
3448 	.hwcg_reg = 0x71010,
3449 	.hwcg_bit = 1,
3450 	.clkr = {
3451 		.enable_reg = 0x71010,
3452 		.enable_mask = BIT(0),
3453 		.hw.init = &(const struct clk_init_data) {
3454 			.name = "gcc_gpu_memnoc_gfx_clk",
3455 			.ops = &clk_branch2_aon_ops,
3456 		},
3457 	},
3458 };
3459 
3460 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
3461 	.halt_reg = 0x71020,
3462 	.halt_check = BRANCH_HALT,
3463 	.clkr = {
3464 		.enable_reg = 0x71020,
3465 		.enable_mask = BIT(0),
3466 		.hw.init = &(const struct clk_init_data) {
3467 			.name = "gcc_gpu_snoc_dvm_gfx_clk",
3468 			.ops = &clk_branch2_aon_ops,
3469 		},
3470 	},
3471 };
3472 
3473 static struct clk_branch gcc_gpu_tcu_throttle_ahb_clk = {
3474 	.halt_reg = 0x71008,
3475 	.halt_check = BRANCH_HALT_VOTED,
3476 	.hwcg_reg = 0x71008,
3477 	.hwcg_bit = 1,
3478 	.clkr = {
3479 		.enable_reg = 0x71008,
3480 		.enable_mask = BIT(0),
3481 		.hw.init = &(const struct clk_init_data) {
3482 			.name = "gcc_gpu_tcu_throttle_ahb_clk",
3483 			.ops = &clk_branch2_ops,
3484 		},
3485 	},
3486 };
3487 
3488 static struct clk_branch gcc_gpu_tcu_throttle_clk = {
3489 	.halt_reg = 0x71018,
3490 	.halt_check = BRANCH_HALT_VOTED,
3491 	.hwcg_reg = 0x71018,
3492 	.hwcg_bit = 1,
3493 	.clkr = {
3494 		.enable_reg = 0x71018,
3495 		.enable_mask = BIT(0),
3496 		.hw.init = &(const struct clk_init_data) {
3497 			.name = "gcc_gpu_tcu_throttle_clk",
3498 			.ops = &clk_branch2_ops,
3499 		},
3500 	},
3501 };
3502 
3503 static struct clk_branch gcc_pcie0_phy_rchng_clk = {
3504 	.halt_reg = 0xa4038,
3505 	.halt_check = BRANCH_HALT_VOTED,
3506 	.clkr = {
3507 		.enable_reg = 0x52018,
3508 		.enable_mask = BIT(11),
3509 		.hw.init = &(const struct clk_init_data) {
3510 			.name = "gcc_pcie0_phy_rchng_clk",
3511 			.parent_hws = (const struct clk_hw*[]){
3512 				&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
3513 			},
3514 			.num_parents = 1,
3515 			.flags = CLK_SET_RATE_PARENT,
3516 			.ops = &clk_branch2_ops,
3517 		},
3518 	},
3519 };
3520 
3521 static struct clk_branch gcc_pcie1_phy_rchng_clk = {
3522 	.halt_reg = 0x8d038,
3523 	.halt_check = BRANCH_HALT_VOTED,
3524 	.clkr = {
3525 		.enable_reg = 0x52000,
3526 		.enable_mask = BIT(23),
3527 		.hw.init = &(const struct clk_init_data) {
3528 			.name = "gcc_pcie1_phy_rchng_clk",
3529 			.parent_hws = (const struct clk_hw*[]){
3530 				&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
3531 			},
3532 			.num_parents = 1,
3533 			.flags = CLK_SET_RATE_PARENT,
3534 			.ops = &clk_branch2_ops,
3535 		},
3536 	},
3537 };
3538 
3539 static struct clk_branch gcc_pcie2a_phy_rchng_clk = {
3540 	.halt_reg = 0x9d040,
3541 	.halt_check = BRANCH_HALT_VOTED,
3542 	.clkr = {
3543 		.enable_reg = 0x52010,
3544 		.enable_mask = BIT(15),
3545 		.hw.init = &(const struct clk_init_data) {
3546 			.name = "gcc_pcie2a_phy_rchng_clk",
3547 			.parent_hws = (const struct clk_hw*[]){
3548 				&gcc_pcie_2a_phy_rchng_clk_src.clkr.hw,
3549 			},
3550 			.num_parents = 1,
3551 			.flags = CLK_SET_RATE_PARENT,
3552 			.ops = &clk_branch2_ops,
3553 		},
3554 	},
3555 };
3556 
3557 static struct clk_branch gcc_pcie2b_phy_rchng_clk = {
3558 	.halt_reg = 0x9e040,
3559 	.halt_check = BRANCH_HALT_VOTED,
3560 	.clkr = {
3561 		.enable_reg = 0x52010,
3562 		.enable_mask = BIT(22),
3563 		.hw.init = &(const struct clk_init_data) {
3564 			.name = "gcc_pcie2b_phy_rchng_clk",
3565 			.parent_hws = (const struct clk_hw*[]){
3566 				&gcc_pcie_2b_phy_rchng_clk_src.clkr.hw,
3567 			},
3568 			.num_parents = 1,
3569 			.flags = CLK_SET_RATE_PARENT,
3570 			.ops = &clk_branch2_ops,
3571 		},
3572 	},
3573 };
3574 
3575 static struct clk_branch gcc_pcie3a_phy_rchng_clk = {
3576 	.halt_reg = 0xa0040,
3577 	.halt_check = BRANCH_HALT_VOTED,
3578 	.clkr = {
3579 		.enable_reg = 0x52010,
3580 		.enable_mask = BIT(29),
3581 		.hw.init = &(const struct clk_init_data) {
3582 			.name = "gcc_pcie3a_phy_rchng_clk",
3583 			.parent_hws = (const struct clk_hw*[]){
3584 				&gcc_pcie_3a_phy_rchng_clk_src.clkr.hw,
3585 			},
3586 			.num_parents = 1,
3587 			.flags = CLK_SET_RATE_PARENT,
3588 			.ops = &clk_branch2_ops,
3589 		},
3590 	},
3591 };
3592 
3593 static struct clk_branch gcc_pcie3b_phy_rchng_clk = {
3594 	.halt_reg = 0xa2040,
3595 	.halt_check = BRANCH_HALT_VOTED,
3596 	.clkr = {
3597 		.enable_reg = 0x52018,
3598 		.enable_mask = BIT(4),
3599 		.hw.init = &(const struct clk_init_data) {
3600 			.name = "gcc_pcie3b_phy_rchng_clk",
3601 			.parent_hws = (const struct clk_hw*[]){
3602 				&gcc_pcie_3b_phy_rchng_clk_src.clkr.hw,
3603 			},
3604 			.num_parents = 1,
3605 			.flags = CLK_SET_RATE_PARENT,
3606 			.ops = &clk_branch2_ops,
3607 		},
3608 	},
3609 };
3610 
3611 static struct clk_branch gcc_pcie4_phy_rchng_clk = {
3612 	.halt_reg = 0x6b040,
3613 	.halt_check = BRANCH_HALT_VOTED,
3614 	.clkr = {
3615 		.enable_reg = 0x52000,
3616 		.enable_mask = BIT(22),
3617 		.hw.init = &(const struct clk_init_data) {
3618 			.name = "gcc_pcie4_phy_rchng_clk",
3619 			.parent_hws = (const struct clk_hw*[]){
3620 				&gcc_pcie_4_phy_rchng_clk_src.clkr.hw,
3621 			},
3622 			.num_parents = 1,
3623 			.flags = CLK_SET_RATE_PARENT,
3624 			.ops = &clk_branch2_ops,
3625 		},
3626 	},
3627 };
3628 
3629 static struct clk_branch gcc_pcie_0_aux_clk = {
3630 	.halt_reg = 0xa4028,
3631 	.halt_check = BRANCH_HALT_VOTED,
3632 	.clkr = {
3633 		.enable_reg = 0x52018,
3634 		.enable_mask = BIT(9),
3635 		.hw.init = &(const struct clk_init_data) {
3636 			.name = "gcc_pcie_0_aux_clk",
3637 			.parent_hws = (const struct clk_hw*[]){
3638 				&gcc_pcie_0_aux_clk_src.clkr.hw,
3639 			},
3640 			.num_parents = 1,
3641 			.flags = CLK_SET_RATE_PARENT,
3642 			.ops = &clk_branch2_ops,
3643 		},
3644 	},
3645 };
3646 
3647 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
3648 	.halt_reg = 0xa4024,
3649 	.halt_check = BRANCH_HALT_VOTED,
3650 	.hwcg_reg = 0xa4024,
3651 	.hwcg_bit = 1,
3652 	.clkr = {
3653 		.enable_reg = 0x52018,
3654 		.enable_mask = BIT(8),
3655 		.hw.init = &(const struct clk_init_data) {
3656 			.name = "gcc_pcie_0_cfg_ahb_clk",
3657 			.ops = &clk_branch2_ops,
3658 		},
3659 	},
3660 };
3661 
3662 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
3663 	.halt_reg = 0xa401c,
3664 	.halt_check = BRANCH_HALT_SKIP,
3665 	.hwcg_reg = 0xa401c,
3666 	.hwcg_bit = 1,
3667 	.clkr = {
3668 		.enable_reg = 0x52018,
3669 		.enable_mask = BIT(7),
3670 		.hw.init = &(const struct clk_init_data) {
3671 			.name = "gcc_pcie_0_mstr_axi_clk",
3672 			.ops = &clk_branch2_ops,
3673 		},
3674 	},
3675 };
3676 
3677 static struct clk_branch gcc_pcie_0_pipe_clk = {
3678 	.halt_reg = 0xa4030,
3679 	.halt_check = BRANCH_HALT_SKIP,
3680 	.clkr = {
3681 		.enable_reg = 0x52018,
3682 		.enable_mask = BIT(10),
3683 		.hw.init = &(const struct clk_init_data) {
3684 			.name = "gcc_pcie_0_pipe_clk",
3685 			.parent_hws = (const struct clk_hw*[]){
3686 				&gcc_usb4_phy_pcie_pipe_mux_clk_src.clkr.hw,
3687 			},
3688 			.num_parents = 1,
3689 			.flags = CLK_SET_RATE_PARENT,
3690 			.ops = &clk_branch2_ops,
3691 		},
3692 	},
3693 };
3694 
3695 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
3696 	.halt_reg = 0xa4014,
3697 	.halt_check = BRANCH_HALT_VOTED,
3698 	.hwcg_reg = 0xa4014,
3699 	.hwcg_bit = 1,
3700 	.clkr = {
3701 		.enable_reg = 0x52018,
3702 		.enable_mask = BIT(6),
3703 		.hw.init = &(const struct clk_init_data) {
3704 			.name = "gcc_pcie_0_slv_axi_clk",
3705 			.ops = &clk_branch2_ops,
3706 		},
3707 	},
3708 };
3709 
3710 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
3711 	.halt_reg = 0xa4010,
3712 	.halt_check = BRANCH_HALT_VOTED,
3713 	.clkr = {
3714 		.enable_reg = 0x52018,
3715 		.enable_mask = BIT(5),
3716 		.hw.init = &(const struct clk_init_data) {
3717 			.name = "gcc_pcie_0_slv_q2a_axi_clk",
3718 			.ops = &clk_branch2_ops,
3719 		},
3720 	},
3721 };
3722 
3723 static struct clk_branch gcc_pcie_1_aux_clk = {
3724 	.halt_reg = 0x8d028,
3725 	.halt_check = BRANCH_HALT_VOTED,
3726 	.clkr = {
3727 		.enable_reg = 0x52000,
3728 		.enable_mask = BIT(29),
3729 		.hw.init = &(const struct clk_init_data) {
3730 			.name = "gcc_pcie_1_aux_clk",
3731 			.parent_hws = (const struct clk_hw*[]){
3732 				&gcc_pcie_1_aux_clk_src.clkr.hw,
3733 			},
3734 			.num_parents = 1,
3735 			.flags = CLK_SET_RATE_PARENT,
3736 			.ops = &clk_branch2_ops,
3737 		},
3738 	},
3739 };
3740 
3741 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
3742 	.halt_reg = 0x8d024,
3743 	.halt_check = BRANCH_HALT_VOTED,
3744 	.hwcg_reg = 0x8d024,
3745 	.hwcg_bit = 1,
3746 	.clkr = {
3747 		.enable_reg = 0x52000,
3748 		.enable_mask = BIT(28),
3749 		.hw.init = &(const struct clk_init_data) {
3750 			.name = "gcc_pcie_1_cfg_ahb_clk",
3751 			.ops = &clk_branch2_ops,
3752 		},
3753 	},
3754 };
3755 
3756 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
3757 	.halt_reg = 0x8d01c,
3758 	.halt_check = BRANCH_HALT_SKIP,
3759 	.hwcg_reg = 0x8d01c,
3760 	.hwcg_bit = 1,
3761 	.clkr = {
3762 		.enable_reg = 0x52000,
3763 		.enable_mask = BIT(27),
3764 		.hw.init = &(const struct clk_init_data) {
3765 			.name = "gcc_pcie_1_mstr_axi_clk",
3766 			.ops = &clk_branch2_ops,
3767 		},
3768 	},
3769 };
3770 
3771 static struct clk_branch gcc_pcie_1_pipe_clk = {
3772 	.halt_reg = 0x8d030,
3773 	.halt_check = BRANCH_HALT_SKIP,
3774 	.clkr = {
3775 		.enable_reg = 0x52000,
3776 		.enable_mask = BIT(30),
3777 		.hw.init = &(const struct clk_init_data) {
3778 			.name = "gcc_pcie_1_pipe_clk",
3779 			.parent_hws = (const struct clk_hw*[]){
3780 				&gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,
3781 			},
3782 			.num_parents = 1,
3783 			.flags = CLK_SET_RATE_PARENT,
3784 			.ops = &clk_branch2_ops,
3785 		},
3786 	},
3787 };
3788 
3789 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
3790 	.halt_reg = 0x8d014,
3791 	.halt_check = BRANCH_HALT_VOTED,
3792 	.hwcg_reg = 0x8d014,
3793 	.hwcg_bit = 1,
3794 	.clkr = {
3795 		.enable_reg = 0x52000,
3796 		.enable_mask = BIT(26),
3797 		.hw.init = &(const struct clk_init_data) {
3798 			.name = "gcc_pcie_1_slv_axi_clk",
3799 			.ops = &clk_branch2_ops,
3800 		},
3801 	},
3802 };
3803 
3804 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
3805 	.halt_reg = 0x8d010,
3806 	.halt_check = BRANCH_HALT_VOTED,
3807 	.clkr = {
3808 		.enable_reg = 0x52000,
3809 		.enable_mask = BIT(25),
3810 		.hw.init = &(const struct clk_init_data) {
3811 			.name = "gcc_pcie_1_slv_q2a_axi_clk",
3812 			.ops = &clk_branch2_ops,
3813 		},
3814 	},
3815 };
3816 
3817 static struct clk_branch gcc_pcie_2a2b_clkref_clk = {
3818 	.halt_reg = 0x8c034,
3819 	.halt_check = BRANCH_HALT,
3820 	.clkr = {
3821 		.enable_reg = 0x8c034,
3822 		.enable_mask = BIT(0),
3823 		.hw.init = &(const struct clk_init_data) {
3824 			.name = "gcc_pcie_2a2b_clkref_clk",
3825 			.ops = &clk_branch2_ops,
3826 		},
3827 	},
3828 };
3829 
3830 static struct clk_branch gcc_pcie_2a_aux_clk = {
3831 	.halt_reg = 0x9d028,
3832 	.halt_check = BRANCH_HALT_VOTED,
3833 	.clkr = {
3834 		.enable_reg = 0x52010,
3835 		.enable_mask = BIT(13),
3836 		.hw.init = &(const struct clk_init_data) {
3837 			.name = "gcc_pcie_2a_aux_clk",
3838 			.parent_hws = (const struct clk_hw*[]){
3839 				&gcc_pcie_2a_aux_clk_src.clkr.hw,
3840 			},
3841 			.num_parents = 1,
3842 			.flags = CLK_SET_RATE_PARENT,
3843 			.ops = &clk_branch2_ops,
3844 		},
3845 	},
3846 };
3847 
3848 static struct clk_branch gcc_pcie_2a_cfg_ahb_clk = {
3849 	.halt_reg = 0x9d024,
3850 	.halt_check = BRANCH_HALT_VOTED,
3851 	.hwcg_reg = 0x9d024,
3852 	.hwcg_bit = 1,
3853 	.clkr = {
3854 		.enable_reg = 0x52010,
3855 		.enable_mask = BIT(12),
3856 		.hw.init = &(const struct clk_init_data) {
3857 			.name = "gcc_pcie_2a_cfg_ahb_clk",
3858 			.ops = &clk_branch2_ops,
3859 		},
3860 	},
3861 };
3862 
3863 static struct clk_branch gcc_pcie_2a_mstr_axi_clk = {
3864 	.halt_reg = 0x9d01c,
3865 	.halt_check = BRANCH_HALT_SKIP,
3866 	.hwcg_reg = 0x9d01c,
3867 	.hwcg_bit = 1,
3868 	.clkr = {
3869 		.enable_reg = 0x52010,
3870 		.enable_mask = BIT(11),
3871 		.hw.init = &(const struct clk_init_data) {
3872 			.name = "gcc_pcie_2a_mstr_axi_clk",
3873 			.ops = &clk_branch2_ops,
3874 		},
3875 	},
3876 };
3877 
3878 static struct clk_branch gcc_pcie_2a_pipe_clk = {
3879 	.halt_reg = 0x9d030,
3880 	.halt_check = BRANCH_HALT_SKIP,
3881 	.clkr = {
3882 		.enable_reg = 0x52010,
3883 		.enable_mask = BIT(14),
3884 		.hw.init = &(const struct clk_init_data) {
3885 			.name = "gcc_pcie_2a_pipe_clk",
3886 			.parent_hws = (const struct clk_hw*[]){
3887 				&gcc_pcie_2a_pipe_clk_src.clkr.hw,
3888 			},
3889 			.num_parents = 1,
3890 			.flags = CLK_SET_RATE_PARENT,
3891 			.ops = &clk_branch2_ops,
3892 		},
3893 	},
3894 };
3895 
3896 static struct clk_branch gcc_pcie_2a_pipediv2_clk = {
3897 	.halt_reg = 0x9d038,
3898 	.halt_check = BRANCH_HALT_SKIP,
3899 	.clkr = {
3900 		.enable_reg = 0x52018,
3901 		.enable_mask = BIT(22),
3902 		.hw.init = &(const struct clk_init_data) {
3903 			.name = "gcc_pcie_2a_pipediv2_clk",
3904 			.parent_hws = (const struct clk_hw*[]){
3905 				&gcc_pcie_2a_pipe_div_clk_src.clkr.hw,
3906 			},
3907 			.num_parents = 1,
3908 			.flags = CLK_SET_RATE_PARENT,
3909 			.ops = &clk_branch2_ops,
3910 		},
3911 	},
3912 };
3913 
3914 static struct clk_branch gcc_pcie_2a_slv_axi_clk = {
3915 	.halt_reg = 0x9d014,
3916 	.halt_check = BRANCH_HALT_VOTED,
3917 	.hwcg_reg = 0x9d014,
3918 	.hwcg_bit = 1,
3919 	.clkr = {
3920 		.enable_reg = 0x52010,
3921 		.enable_mask = BIT(10),
3922 		.hw.init = &(const struct clk_init_data) {
3923 			.name = "gcc_pcie_2a_slv_axi_clk",
3924 			.ops = &clk_branch2_ops,
3925 		},
3926 	},
3927 };
3928 
3929 static struct clk_branch gcc_pcie_2a_slv_q2a_axi_clk = {
3930 	.halt_reg = 0x9d010,
3931 	.halt_check = BRANCH_HALT_VOTED,
3932 	.clkr = {
3933 		.enable_reg = 0x52018,
3934 		.enable_mask = BIT(12),
3935 		.hw.init = &(const struct clk_init_data) {
3936 			.name = "gcc_pcie_2a_slv_q2a_axi_clk",
3937 			.ops = &clk_branch2_ops,
3938 		},
3939 	},
3940 };
3941 
3942 static struct clk_branch gcc_pcie_2b_aux_clk = {
3943 	.halt_reg = 0x9e028,
3944 	.halt_check = BRANCH_HALT_VOTED,
3945 	.clkr = {
3946 		.enable_reg = 0x52010,
3947 		.enable_mask = BIT(20),
3948 		.hw.init = &(const struct clk_init_data) {
3949 			.name = "gcc_pcie_2b_aux_clk",
3950 			.parent_hws = (const struct clk_hw*[]){
3951 				&gcc_pcie_2b_aux_clk_src.clkr.hw,
3952 			},
3953 			.num_parents = 1,
3954 			.flags = CLK_SET_RATE_PARENT,
3955 			.ops = &clk_branch2_ops,
3956 		},
3957 	},
3958 };
3959 
3960 static struct clk_branch gcc_pcie_2b_cfg_ahb_clk = {
3961 	.halt_reg = 0x9e024,
3962 	.halt_check = BRANCH_HALT_VOTED,
3963 	.hwcg_reg = 0x9e024,
3964 	.hwcg_bit = 1,
3965 	.clkr = {
3966 		.enable_reg = 0x52010,
3967 		.enable_mask = BIT(19),
3968 		.hw.init = &(const struct clk_init_data) {
3969 			.name = "gcc_pcie_2b_cfg_ahb_clk",
3970 			.ops = &clk_branch2_ops,
3971 		},
3972 	},
3973 };
3974 
3975 static struct clk_branch gcc_pcie_2b_mstr_axi_clk = {
3976 	.halt_reg = 0x9e01c,
3977 	.halt_check = BRANCH_HALT_SKIP,
3978 	.hwcg_reg = 0x9e01c,
3979 	.hwcg_bit = 1,
3980 	.clkr = {
3981 		.enable_reg = 0x52010,
3982 		.enable_mask = BIT(18),
3983 		.hw.init = &(const struct clk_init_data) {
3984 			.name = "gcc_pcie_2b_mstr_axi_clk",
3985 			.ops = &clk_branch2_ops,
3986 		},
3987 	},
3988 };
3989 
3990 static struct clk_branch gcc_pcie_2b_pipe_clk = {
3991 	.halt_reg = 0x9e030,
3992 	.halt_check = BRANCH_HALT_SKIP,
3993 	.clkr = {
3994 		.enable_reg = 0x52010,
3995 		.enable_mask = BIT(21),
3996 		.hw.init = &(const struct clk_init_data) {
3997 			.name = "gcc_pcie_2b_pipe_clk",
3998 			.parent_hws = (const struct clk_hw*[]){
3999 				&gcc_pcie_2b_pipe_clk_src.clkr.hw,
4000 			},
4001 			.num_parents = 1,
4002 			.flags = CLK_SET_RATE_PARENT,
4003 			.ops = &clk_branch2_ops,
4004 		},
4005 	},
4006 };
4007 
4008 static struct clk_branch gcc_pcie_2b_pipediv2_clk = {
4009 	.halt_reg = 0x9e038,
4010 	.halt_check = BRANCH_HALT_SKIP,
4011 	.clkr = {
4012 		.enable_reg = 0x52018,
4013 		.enable_mask = BIT(23),
4014 		.hw.init = &(const struct clk_init_data) {
4015 			.name = "gcc_pcie_2b_pipediv2_clk",
4016 			.parent_hws = (const struct clk_hw*[]){
4017 				&gcc_pcie_2b_pipe_div_clk_src.clkr.hw,
4018 			},
4019 			.num_parents = 1,
4020 			.flags = CLK_SET_RATE_PARENT,
4021 			.ops = &clk_branch2_ops,
4022 		},
4023 	},
4024 };
4025 
4026 static struct clk_branch gcc_pcie_2b_slv_axi_clk = {
4027 	.halt_reg = 0x9e014,
4028 	.halt_check = BRANCH_HALT_VOTED,
4029 	.hwcg_reg = 0x9e014,
4030 	.hwcg_bit = 1,
4031 	.clkr = {
4032 		.enable_reg = 0x52010,
4033 		.enable_mask = BIT(17),
4034 		.hw.init = &(const struct clk_init_data) {
4035 			.name = "gcc_pcie_2b_slv_axi_clk",
4036 			.ops = &clk_branch2_ops,
4037 		},
4038 	},
4039 };
4040 
4041 static struct clk_branch gcc_pcie_2b_slv_q2a_axi_clk = {
4042 	.halt_reg = 0x9e010,
4043 	.halt_check = BRANCH_HALT_VOTED,
4044 	.clkr = {
4045 		.enable_reg = 0x52010,
4046 		.enable_mask = BIT(16),
4047 		.hw.init = &(const struct clk_init_data) {
4048 			.name = "gcc_pcie_2b_slv_q2a_axi_clk",
4049 			.ops = &clk_branch2_ops,
4050 		},
4051 	},
4052 };
4053 
4054 static struct clk_branch gcc_pcie_3a3b_clkref_clk = {
4055 	.halt_reg = 0x8c038,
4056 	.halt_check = BRANCH_HALT,
4057 	.clkr = {
4058 		.enable_reg = 0x8c038,
4059 		.enable_mask = BIT(0),
4060 		.hw.init = &(const struct clk_init_data) {
4061 			.name = "gcc_pcie_3a3b_clkref_clk",
4062 			.ops = &clk_branch2_ops,
4063 		},
4064 	},
4065 };
4066 
4067 static struct clk_branch gcc_pcie_3a_aux_clk = {
4068 	.halt_reg = 0xa0028,
4069 	.halt_check = BRANCH_HALT_VOTED,
4070 	.clkr = {
4071 		.enable_reg = 0x52010,
4072 		.enable_mask = BIT(27),
4073 		.hw.init = &(const struct clk_init_data) {
4074 			.name = "gcc_pcie_3a_aux_clk",
4075 			.parent_hws = (const struct clk_hw*[]){
4076 				&gcc_pcie_3a_aux_clk_src.clkr.hw,
4077 			},
4078 			.num_parents = 1,
4079 			.flags = CLK_SET_RATE_PARENT,
4080 			.ops = &clk_branch2_ops,
4081 		},
4082 	},
4083 };
4084 
4085 static struct clk_branch gcc_pcie_3a_cfg_ahb_clk = {
4086 	.halt_reg = 0xa0024,
4087 	.halt_check = BRANCH_HALT_VOTED,
4088 	.hwcg_reg = 0xa0024,
4089 	.hwcg_bit = 1,
4090 	.clkr = {
4091 		.enable_reg = 0x52010,
4092 		.enable_mask = BIT(26),
4093 		.hw.init = &(const struct clk_init_data) {
4094 			.name = "gcc_pcie_3a_cfg_ahb_clk",
4095 			.ops = &clk_branch2_ops,
4096 		},
4097 	},
4098 };
4099 
4100 static struct clk_branch gcc_pcie_3a_mstr_axi_clk = {
4101 	.halt_reg = 0xa001c,
4102 	.halt_check = BRANCH_HALT_SKIP,
4103 	.hwcg_reg = 0xa001c,
4104 	.hwcg_bit = 1,
4105 	.clkr = {
4106 		.enable_reg = 0x52010,
4107 		.enable_mask = BIT(25),
4108 		.hw.init = &(const struct clk_init_data) {
4109 			.name = "gcc_pcie_3a_mstr_axi_clk",
4110 			.ops = &clk_branch2_ops,
4111 		},
4112 	},
4113 };
4114 
4115 static struct clk_branch gcc_pcie_3a_pipe_clk = {
4116 	.halt_reg = 0xa0030,
4117 	.halt_check = BRANCH_HALT_SKIP,
4118 	.clkr = {
4119 		.enable_reg = 0x52010,
4120 		.enable_mask = BIT(28),
4121 		.hw.init = &(const struct clk_init_data) {
4122 			.name = "gcc_pcie_3a_pipe_clk",
4123 			.parent_hws = (const struct clk_hw*[]){
4124 				&gcc_pcie_3a_pipe_clk_src.clkr.hw,
4125 			},
4126 			.num_parents = 1,
4127 			.flags = CLK_SET_RATE_PARENT,
4128 			.ops = &clk_branch2_ops,
4129 		},
4130 	},
4131 };
4132 
4133 static struct clk_branch gcc_pcie_3a_pipediv2_clk = {
4134 	.halt_reg = 0xa0038,
4135 	.halt_check = BRANCH_HALT_SKIP,
4136 	.clkr = {
4137 		.enable_reg = 0x52018,
4138 		.enable_mask = BIT(24),
4139 		.hw.init = &(const struct clk_init_data) {
4140 			.name = "gcc_pcie_3a_pipediv2_clk",
4141 			.parent_hws = (const struct clk_hw*[]){
4142 				&gcc_pcie_3a_pipe_div_clk_src.clkr.hw,
4143 			},
4144 			.num_parents = 1,
4145 			.flags = CLK_SET_RATE_PARENT,
4146 			.ops = &clk_branch2_ops,
4147 		},
4148 	},
4149 };
4150 
4151 static struct clk_branch gcc_pcie_3a_slv_axi_clk = {
4152 	.halt_reg = 0xa0014,
4153 	.halt_check = BRANCH_HALT_VOTED,
4154 	.hwcg_reg = 0xa0014,
4155 	.hwcg_bit = 1,
4156 	.clkr = {
4157 		.enable_reg = 0x52010,
4158 		.enable_mask = BIT(24),
4159 		.hw.init = &(const struct clk_init_data) {
4160 			.name = "gcc_pcie_3a_slv_axi_clk",
4161 			.ops = &clk_branch2_ops,
4162 		},
4163 	},
4164 };
4165 
4166 static struct clk_branch gcc_pcie_3a_slv_q2a_axi_clk = {
4167 	.halt_reg = 0xa0010,
4168 	.halt_check = BRANCH_HALT_VOTED,
4169 	.clkr = {
4170 		.enable_reg = 0x52010,
4171 		.enable_mask = BIT(23),
4172 		.hw.init = &(const struct clk_init_data) {
4173 			.name = "gcc_pcie_3a_slv_q2a_axi_clk",
4174 			.ops = &clk_branch2_ops,
4175 		},
4176 	},
4177 };
4178 
4179 static struct clk_branch gcc_pcie_3b_aux_clk = {
4180 	.halt_reg = 0xa2028,
4181 	.halt_check = BRANCH_HALT_VOTED,
4182 	.clkr = {
4183 		.enable_reg = 0x52018,
4184 		.enable_mask = BIT(2),
4185 		.hw.init = &(const struct clk_init_data) {
4186 			.name = "gcc_pcie_3b_aux_clk",
4187 			.parent_hws = (const struct clk_hw*[]){
4188 				&gcc_pcie_3b_aux_clk_src.clkr.hw,
4189 			},
4190 			.num_parents = 1,
4191 			.flags = CLK_SET_RATE_PARENT,
4192 			.ops = &clk_branch2_ops,
4193 		},
4194 	},
4195 };
4196 
4197 static struct clk_branch gcc_pcie_3b_cfg_ahb_clk = {
4198 	.halt_reg = 0xa2024,
4199 	.halt_check = BRANCH_HALT_VOTED,
4200 	.hwcg_reg = 0xa2024,
4201 	.hwcg_bit = 1,
4202 	.clkr = {
4203 		.enable_reg = 0x52018,
4204 		.enable_mask = BIT(1),
4205 		.hw.init = &(const struct clk_init_data) {
4206 			.name = "gcc_pcie_3b_cfg_ahb_clk",
4207 			.ops = &clk_branch2_ops,
4208 		},
4209 	},
4210 };
4211 
4212 static struct clk_branch gcc_pcie_3b_mstr_axi_clk = {
4213 	.halt_reg = 0xa201c,
4214 	.halt_check = BRANCH_HALT_SKIP,
4215 	.hwcg_reg = 0xa201c,
4216 	.hwcg_bit = 1,
4217 	.clkr = {
4218 		.enable_reg = 0x52018,
4219 		.enable_mask = BIT(0),
4220 		.hw.init = &(const struct clk_init_data) {
4221 			.name = "gcc_pcie_3b_mstr_axi_clk",
4222 			.ops = &clk_branch2_ops,
4223 		},
4224 	},
4225 };
4226 
4227 static struct clk_branch gcc_pcie_3b_pipe_clk = {
4228 	.halt_reg = 0xa2030,
4229 	.halt_check = BRANCH_HALT_SKIP,
4230 	.clkr = {
4231 		.enable_reg = 0x52018,
4232 		.enable_mask = BIT(3),
4233 		.hw.init = &(const struct clk_init_data) {
4234 			.name = "gcc_pcie_3b_pipe_clk",
4235 			.parent_hws = (const struct clk_hw*[]){
4236 				&gcc_pcie_3b_pipe_clk_src.clkr.hw,
4237 			},
4238 			.num_parents = 1,
4239 			.flags = CLK_SET_RATE_PARENT,
4240 			.ops = &clk_branch2_ops,
4241 		},
4242 	},
4243 };
4244 
4245 static struct clk_branch gcc_pcie_3b_pipediv2_clk = {
4246 	.halt_reg = 0xa2038,
4247 	.halt_check = BRANCH_HALT_SKIP,
4248 	.clkr = {
4249 		.enable_reg = 0x52018,
4250 		.enable_mask = BIT(25),
4251 		.hw.init = &(const struct clk_init_data) {
4252 			.name = "gcc_pcie_3b_pipediv2_clk",
4253 			.parent_hws = (const struct clk_hw*[]){
4254 				&gcc_pcie_3b_pipe_div_clk_src.clkr.hw,
4255 			},
4256 			.num_parents = 1,
4257 			.flags = CLK_SET_RATE_PARENT,
4258 			.ops = &clk_branch2_ops,
4259 		},
4260 	},
4261 };
4262 
4263 static struct clk_branch gcc_pcie_3b_slv_axi_clk = {
4264 	.halt_reg = 0xa2014,
4265 	.halt_check = BRANCH_HALT_VOTED,
4266 	.hwcg_reg = 0xa2014,
4267 	.hwcg_bit = 1,
4268 	.clkr = {
4269 		.enable_reg = 0x52010,
4270 		.enable_mask = BIT(31),
4271 		.hw.init = &(const struct clk_init_data) {
4272 			.name = "gcc_pcie_3b_slv_axi_clk",
4273 			.ops = &clk_branch2_ops,
4274 		},
4275 	},
4276 };
4277 
4278 static struct clk_branch gcc_pcie_3b_slv_q2a_axi_clk = {
4279 	.halt_reg = 0xa2010,
4280 	.halt_check = BRANCH_HALT_VOTED,
4281 	.clkr = {
4282 		.enable_reg = 0x52010,
4283 		.enable_mask = BIT(30),
4284 		.hw.init = &(const struct clk_init_data) {
4285 			.name = "gcc_pcie_3b_slv_q2a_axi_clk",
4286 			.ops = &clk_branch2_ops,
4287 		},
4288 	},
4289 };
4290 
4291 static struct clk_branch gcc_pcie_4_aux_clk = {
4292 	.halt_reg = 0x6b028,
4293 	.halt_check = BRANCH_HALT_VOTED,
4294 	.clkr = {
4295 		.enable_reg = 0x52008,
4296 		.enable_mask = BIT(3),
4297 		.hw.init = &(const struct clk_init_data) {
4298 			.name = "gcc_pcie_4_aux_clk",
4299 			.parent_hws = (const struct clk_hw*[]){
4300 				&gcc_pcie_4_aux_clk_src.clkr.hw,
4301 			},
4302 			.num_parents = 1,
4303 			.flags = CLK_SET_RATE_PARENT,
4304 			.ops = &clk_branch2_ops,
4305 		},
4306 	},
4307 };
4308 
4309 static struct clk_branch gcc_pcie_4_cfg_ahb_clk = {
4310 	.halt_reg = 0x6b024,
4311 	.halt_check = BRANCH_HALT_VOTED,
4312 	.hwcg_reg = 0x6b024,
4313 	.hwcg_bit = 1,
4314 	.clkr = {
4315 		.enable_reg = 0x52008,
4316 		.enable_mask = BIT(2),
4317 		.hw.init = &(const struct clk_init_data) {
4318 			.name = "gcc_pcie_4_cfg_ahb_clk",
4319 			.ops = &clk_branch2_ops,
4320 		},
4321 	},
4322 };
4323 
4324 static struct clk_branch gcc_pcie_4_clkref_clk = {
4325 	.halt_reg = 0x8c030,
4326 	.halt_check = BRANCH_HALT,
4327 	.clkr = {
4328 		.enable_reg = 0x8c030,
4329 		.enable_mask = BIT(0),
4330 		.hw.init = &(const struct clk_init_data) {
4331 			.name = "gcc_pcie_4_clkref_clk",
4332 			.ops = &clk_branch2_ops,
4333 		},
4334 	},
4335 };
4336 
4337 static struct clk_branch gcc_pcie_4_mstr_axi_clk = {
4338 	.halt_reg = 0x6b01c,
4339 	.halt_check = BRANCH_HALT_SKIP,
4340 	.hwcg_reg = 0x6b01c,
4341 	.hwcg_bit = 1,
4342 	.clkr = {
4343 		.enable_reg = 0x52008,
4344 		.enable_mask = BIT(1),
4345 		.hw.init = &(const struct clk_init_data) {
4346 			.name = "gcc_pcie_4_mstr_axi_clk",
4347 			.ops = &clk_branch2_ops,
4348 		},
4349 	},
4350 };
4351 
4352 static struct clk_branch gcc_pcie_4_pipe_clk = {
4353 	.halt_reg = 0x6b030,
4354 	.halt_check = BRANCH_HALT_SKIP,
4355 	.clkr = {
4356 		.enable_reg = 0x52008,
4357 		.enable_mask = BIT(4),
4358 		.hw.init = &(const struct clk_init_data) {
4359 			.name = "gcc_pcie_4_pipe_clk",
4360 			.parent_hws = (const struct clk_hw*[]){
4361 				&gcc_pcie_4_pipe_clk_src.clkr.hw,
4362 			},
4363 			.num_parents = 1,
4364 			.flags = CLK_SET_RATE_PARENT,
4365 			.ops = &clk_branch2_ops,
4366 		},
4367 	},
4368 };
4369 
4370 static struct clk_branch gcc_pcie_4_pipediv2_clk = {
4371 	.halt_reg = 0x6b038,
4372 	.halt_check = BRANCH_HALT_SKIP,
4373 	.clkr = {
4374 		.enable_reg = 0x52018,
4375 		.enable_mask = BIT(16),
4376 		.hw.init = &(const struct clk_init_data) {
4377 			.name = "gcc_pcie_4_pipediv2_clk",
4378 			.parent_hws = (const struct clk_hw*[]){
4379 				&gcc_pcie_4_pipe_div_clk_src.clkr.hw,
4380 			},
4381 			.num_parents = 1,
4382 			.flags = CLK_SET_RATE_PARENT,
4383 			.ops = &clk_branch2_ops,
4384 		},
4385 	},
4386 };
4387 
4388 static struct clk_branch gcc_pcie_4_slv_axi_clk = {
4389 	.halt_reg = 0x6b014,
4390 	.halt_check = BRANCH_HALT_VOTED,
4391 	.hwcg_reg = 0x6b014,
4392 	.hwcg_bit = 1,
4393 	.clkr = {
4394 		.enable_reg = 0x52008,
4395 		.enable_mask = BIT(0),
4396 		.hw.init = &(const struct clk_init_data) {
4397 			.name = "gcc_pcie_4_slv_axi_clk",
4398 			.ops = &clk_branch2_ops,
4399 		},
4400 	},
4401 };
4402 
4403 static struct clk_branch gcc_pcie_4_slv_q2a_axi_clk = {
4404 	.halt_reg = 0x6b010,
4405 	.halt_check = BRANCH_HALT_VOTED,
4406 	.clkr = {
4407 		.enable_reg = 0x52008,
4408 		.enable_mask = BIT(5),
4409 		.hw.init = &(const struct clk_init_data) {
4410 			.name = "gcc_pcie_4_slv_q2a_axi_clk",
4411 			.ops = &clk_branch2_ops,
4412 		},
4413 	},
4414 };
4415 
4416 static struct clk_branch gcc_pcie_rscc_ahb_clk = {
4417 	.halt_reg = 0xae008,
4418 	.halt_check = BRANCH_HALT_VOTED,
4419 	.hwcg_reg = 0xae008,
4420 	.hwcg_bit = 1,
4421 	.clkr = {
4422 		.enable_reg = 0x52020,
4423 		.enable_mask = BIT(17),
4424 		.hw.init = &(const struct clk_init_data) {
4425 			.name = "gcc_pcie_rscc_ahb_clk",
4426 			.ops = &clk_branch2_ops,
4427 		},
4428 	},
4429 };
4430 
4431 static struct clk_branch gcc_pcie_rscc_xo_clk = {
4432 	.halt_reg = 0xae004,
4433 	.halt_check = BRANCH_HALT_VOTED,
4434 	.clkr = {
4435 		.enable_reg = 0x52020,
4436 		.enable_mask = BIT(16),
4437 		.hw.init = &(const struct clk_init_data) {
4438 			.name = "gcc_pcie_rscc_xo_clk",
4439 			.parent_hws = (const struct clk_hw*[]){
4440 				&gcc_pcie_rscc_xo_clk_src.clkr.hw,
4441 			},
4442 			.num_parents = 1,
4443 			.flags = CLK_SET_RATE_PARENT,
4444 			.ops = &clk_branch2_ops,
4445 		},
4446 	},
4447 };
4448 
4449 static struct clk_branch gcc_pcie_throttle_cfg_clk = {
4450 	.halt_reg = 0xa6028,
4451 	.halt_check = BRANCH_HALT_VOTED,
4452 	.clkr = {
4453 		.enable_reg = 0x52020,
4454 		.enable_mask = BIT(15),
4455 		.hw.init = &(const struct clk_init_data) {
4456 			.name = "gcc_pcie_throttle_cfg_clk",
4457 			.ops = &clk_branch2_ops,
4458 		},
4459 	},
4460 };
4461 
4462 static struct clk_branch gcc_pdm2_clk = {
4463 	.halt_reg = 0x3300c,
4464 	.halt_check = BRANCH_HALT,
4465 	.clkr = {
4466 		.enable_reg = 0x3300c,
4467 		.enable_mask = BIT(0),
4468 		.hw.init = &(const struct clk_init_data) {
4469 			.name = "gcc_pdm2_clk",
4470 			.parent_hws = (const struct clk_hw*[]){
4471 				&gcc_pdm2_clk_src.clkr.hw,
4472 			},
4473 			.num_parents = 1,
4474 			.flags = CLK_SET_RATE_PARENT,
4475 			.ops = &clk_branch2_ops,
4476 		},
4477 	},
4478 };
4479 
4480 static struct clk_branch gcc_pdm_ahb_clk = {
4481 	.halt_reg = 0x33004,
4482 	.halt_check = BRANCH_HALT_VOTED,
4483 	.hwcg_reg = 0x33004,
4484 	.hwcg_bit = 1,
4485 	.clkr = {
4486 		.enable_reg = 0x33004,
4487 		.enable_mask = BIT(0),
4488 		.hw.init = &(const struct clk_init_data) {
4489 			.name = "gcc_pdm_ahb_clk",
4490 			.ops = &clk_branch2_ops,
4491 		},
4492 	},
4493 };
4494 
4495 static struct clk_branch gcc_pdm_xo4_clk = {
4496 	.halt_reg = 0x33008,
4497 	.halt_check = BRANCH_HALT,
4498 	.clkr = {
4499 		.enable_reg = 0x33008,
4500 		.enable_mask = BIT(0),
4501 		.hw.init = &(const struct clk_init_data) {
4502 			.name = "gcc_pdm_xo4_clk",
4503 			.ops = &clk_branch2_ops,
4504 		},
4505 	},
4506 };
4507 
4508 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
4509 	.halt_reg = 0x26008,
4510 	.halt_check = BRANCH_HALT_VOTED,
4511 	.hwcg_reg = 0x26008,
4512 	.hwcg_bit = 1,
4513 	.clkr = {
4514 		.enable_reg = 0x26008,
4515 		.enable_mask = BIT(0),
4516 		.hw.init = &(const struct clk_init_data) {
4517 			.name = "gcc_qmip_camera_nrt_ahb_clk",
4518 			.ops = &clk_branch2_ops,
4519 		},
4520 	},
4521 };
4522 
4523 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
4524 	.halt_reg = 0x2600c,
4525 	.halt_check = BRANCH_HALT_VOTED,
4526 	.hwcg_reg = 0x2600c,
4527 	.hwcg_bit = 1,
4528 	.clkr = {
4529 		.enable_reg = 0x2600c,
4530 		.enable_mask = BIT(0),
4531 		.hw.init = &(const struct clk_init_data) {
4532 			.name = "gcc_qmip_camera_rt_ahb_clk",
4533 			.ops = &clk_branch2_ops,
4534 		},
4535 	},
4536 };
4537 
4538 static struct clk_branch gcc_qmip_disp1_ahb_clk = {
4539 	.halt_reg = 0xbb008,
4540 	.halt_check = BRANCH_HALT_VOTED,
4541 	.hwcg_reg = 0xbb008,
4542 	.hwcg_bit = 1,
4543 	.clkr = {
4544 		.enable_reg = 0xbb008,
4545 		.enable_mask = BIT(0),
4546 		.hw.init = &(const struct clk_init_data) {
4547 			.name = "gcc_qmip_disp1_ahb_clk",
4548 			.ops = &clk_branch2_ops,
4549 		},
4550 	},
4551 };
4552 
4553 static struct clk_branch gcc_qmip_disp1_rot_ahb_clk = {
4554 	.halt_reg = 0xbb00c,
4555 	.halt_check = BRANCH_HALT_VOTED,
4556 	.hwcg_reg = 0xbb00c,
4557 	.hwcg_bit = 1,
4558 	.clkr = {
4559 		.enable_reg = 0xbb00c,
4560 		.enable_mask = BIT(0),
4561 		.hw.init = &(const struct clk_init_data) {
4562 			.name = "gcc_qmip_disp1_rot_ahb_clk",
4563 			.ops = &clk_branch2_ops,
4564 		},
4565 	},
4566 };
4567 
4568 static struct clk_branch gcc_qmip_disp_ahb_clk = {
4569 	.halt_reg = 0x27008,
4570 	.halt_check = BRANCH_HALT_VOTED,
4571 	.hwcg_reg = 0x27008,
4572 	.hwcg_bit = 1,
4573 	.clkr = {
4574 		.enable_reg = 0x27008,
4575 		.enable_mask = BIT(0),
4576 		.hw.init = &(const struct clk_init_data) {
4577 			.name = "gcc_qmip_disp_ahb_clk",
4578 			.ops = &clk_branch2_ops,
4579 		},
4580 	},
4581 };
4582 
4583 static struct clk_branch gcc_qmip_disp_rot_ahb_clk = {
4584 	.halt_reg = 0x2700c,
4585 	.halt_check = BRANCH_HALT_VOTED,
4586 	.hwcg_reg = 0x2700c,
4587 	.hwcg_bit = 1,
4588 	.clkr = {
4589 		.enable_reg = 0x2700c,
4590 		.enable_mask = BIT(0),
4591 		.hw.init = &(const struct clk_init_data) {
4592 			.name = "gcc_qmip_disp_rot_ahb_clk",
4593 			.ops = &clk_branch2_ops,
4594 		},
4595 	},
4596 };
4597 
4598 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
4599 	.halt_reg = 0x28008,
4600 	.halt_check = BRANCH_HALT_VOTED,
4601 	.hwcg_reg = 0x28008,
4602 	.hwcg_bit = 1,
4603 	.clkr = {
4604 		.enable_reg = 0x28008,
4605 		.enable_mask = BIT(0),
4606 		.hw.init = &(const struct clk_init_data) {
4607 			.name = "gcc_qmip_video_cvp_ahb_clk",
4608 			.ops = &clk_branch2_ops,
4609 		},
4610 	},
4611 };
4612 
4613 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
4614 	.halt_reg = 0x2800c,
4615 	.halt_check = BRANCH_HALT_VOTED,
4616 	.hwcg_reg = 0x2800c,
4617 	.hwcg_bit = 1,
4618 	.clkr = {
4619 		.enable_reg = 0x2800c,
4620 		.enable_mask = BIT(0),
4621 		.hw.init = &(const struct clk_init_data) {
4622 			.name = "gcc_qmip_video_vcodec_ahb_clk",
4623 			.ops = &clk_branch2_ops,
4624 		},
4625 	},
4626 };
4627 
4628 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
4629 	.halt_reg = 0x17014,
4630 	.halt_check = BRANCH_HALT_VOTED,
4631 	.clkr = {
4632 		.enable_reg = 0x52008,
4633 		.enable_mask = BIT(9),
4634 		.hw.init = &(const struct clk_init_data) {
4635 			.name = "gcc_qupv3_wrap0_core_2x_clk",
4636 			.ops = &clk_branch2_ops,
4637 		},
4638 	},
4639 };
4640 
4641 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
4642 	.halt_reg = 0x1700c,
4643 	.halt_check = BRANCH_HALT_VOTED,
4644 	.clkr = {
4645 		.enable_reg = 0x52008,
4646 		.enable_mask = BIT(8),
4647 		.hw.init = &(const struct clk_init_data) {
4648 			.name = "gcc_qupv3_wrap0_core_clk",
4649 			.ops = &clk_branch2_ops,
4650 		},
4651 	},
4652 };
4653 
4654 static struct clk_branch gcc_qupv3_wrap0_qspi0_clk = {
4655 	.halt_reg = 0x17ac4,
4656 	.halt_check = BRANCH_HALT_VOTED,
4657 	.clkr = {
4658 		.enable_reg = 0x52020,
4659 		.enable_mask = BIT(0),
4660 		.hw.init = &(const struct clk_init_data) {
4661 			.name = "gcc_qupv3_wrap0_qspi0_clk",
4662 			.parent_hws = (const struct clk_hw*[]){
4663 				&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
4664 			},
4665 			.num_parents = 1,
4666 			.flags = CLK_SET_RATE_PARENT,
4667 			.ops = &clk_branch2_ops,
4668 		},
4669 	},
4670 };
4671 
4672 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
4673 	.halt_reg = 0x17144,
4674 	.halt_check = BRANCH_HALT_VOTED,
4675 	.clkr = {
4676 		.enable_reg = 0x52008,
4677 		.enable_mask = BIT(10),
4678 		.hw.init = &(const struct clk_init_data) {
4679 			.name = "gcc_qupv3_wrap0_s0_clk",
4680 			.parent_hws = (const struct clk_hw*[]){
4681 				&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
4682 			},
4683 			.num_parents = 1,
4684 			.flags = CLK_SET_RATE_PARENT,
4685 			.ops = &clk_branch2_ops,
4686 		},
4687 	},
4688 };
4689 
4690 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
4691 	.halt_reg = 0x17274,
4692 	.halt_check = BRANCH_HALT_VOTED,
4693 	.clkr = {
4694 		.enable_reg = 0x52008,
4695 		.enable_mask = BIT(11),
4696 		.hw.init = &(const struct clk_init_data) {
4697 			.name = "gcc_qupv3_wrap0_s1_clk",
4698 			.parent_hws = (const struct clk_hw*[]){
4699 				&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
4700 			},
4701 			.num_parents = 1,
4702 			.flags = CLK_SET_RATE_PARENT,
4703 			.ops = &clk_branch2_ops,
4704 		},
4705 	},
4706 };
4707 
4708 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
4709 	.halt_reg = 0x173a4,
4710 	.halt_check = BRANCH_HALT_VOTED,
4711 	.clkr = {
4712 		.enable_reg = 0x52008,
4713 		.enable_mask = BIT(12),
4714 		.hw.init = &(const struct clk_init_data) {
4715 			.name = "gcc_qupv3_wrap0_s2_clk",
4716 			.parent_hws = (const struct clk_hw*[]){
4717 				&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
4718 			},
4719 			.num_parents = 1,
4720 			.flags = CLK_SET_RATE_PARENT,
4721 			.ops = &clk_branch2_ops,
4722 		},
4723 	},
4724 };
4725 
4726 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
4727 	.halt_reg = 0x174d4,
4728 	.halt_check = BRANCH_HALT_VOTED,
4729 	.clkr = {
4730 		.enable_reg = 0x52008,
4731 		.enable_mask = BIT(13),
4732 		.hw.init = &(const struct clk_init_data) {
4733 			.name = "gcc_qupv3_wrap0_s3_clk",
4734 			.parent_hws = (const struct clk_hw*[]){
4735 				&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
4736 			},
4737 			.num_parents = 1,
4738 			.flags = CLK_SET_RATE_PARENT,
4739 			.ops = &clk_branch2_ops,
4740 		},
4741 	},
4742 };
4743 
4744 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
4745 	.halt_reg = 0x17604,
4746 	.halt_check = BRANCH_HALT_VOTED,
4747 	.clkr = {
4748 		.enable_reg = 0x52008,
4749 		.enable_mask = BIT(14),
4750 		.hw.init = &(const struct clk_init_data) {
4751 			.name = "gcc_qupv3_wrap0_s4_clk",
4752 			.parent_hws = (const struct clk_hw*[]){
4753 				&gcc_qupv3_wrap0_s4_div_clk_src.clkr.hw,
4754 			},
4755 			.num_parents = 1,
4756 			.flags = CLK_SET_RATE_PARENT,
4757 			.ops = &clk_branch2_ops,
4758 		},
4759 	},
4760 };
4761 
4762 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
4763 	.halt_reg = 0x17734,
4764 	.halt_check = BRANCH_HALT_VOTED,
4765 	.clkr = {
4766 		.enable_reg = 0x52008,
4767 		.enable_mask = BIT(15),
4768 		.hw.init = &(const struct clk_init_data) {
4769 			.name = "gcc_qupv3_wrap0_s5_clk",
4770 			.parent_hws = (const struct clk_hw*[]){
4771 				&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
4772 			},
4773 			.num_parents = 1,
4774 			.flags = CLK_SET_RATE_PARENT,
4775 			.ops = &clk_branch2_ops,
4776 		},
4777 	},
4778 };
4779 
4780 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
4781 	.halt_reg = 0x17864,
4782 	.halt_check = BRANCH_HALT_VOTED,
4783 	.clkr = {
4784 		.enable_reg = 0x52008,
4785 		.enable_mask = BIT(16),
4786 		.hw.init = &(const struct clk_init_data) {
4787 			.name = "gcc_qupv3_wrap0_s6_clk",
4788 			.parent_hws = (const struct clk_hw*[]){
4789 				&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
4790 			},
4791 			.num_parents = 1,
4792 			.flags = CLK_SET_RATE_PARENT,
4793 			.ops = &clk_branch2_ops,
4794 		},
4795 	},
4796 };
4797 
4798 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
4799 	.halt_reg = 0x17994,
4800 	.halt_check = BRANCH_HALT_VOTED,
4801 	.clkr = {
4802 		.enable_reg = 0x52008,
4803 		.enable_mask = BIT(17),
4804 		.hw.init = &(const struct clk_init_data) {
4805 			.name = "gcc_qupv3_wrap0_s7_clk",
4806 			.parent_hws = (const struct clk_hw*[]){
4807 				&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
4808 			},
4809 			.num_parents = 1,
4810 			.flags = CLK_SET_RATE_PARENT,
4811 			.ops = &clk_branch2_ops,
4812 		},
4813 	},
4814 };
4815 
4816 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
4817 	.halt_reg = 0x18014,
4818 	.halt_check = BRANCH_HALT_VOTED,
4819 	.clkr = {
4820 		.enable_reg = 0x52008,
4821 		.enable_mask = BIT(18),
4822 		.hw.init = &(const struct clk_init_data) {
4823 			.name = "gcc_qupv3_wrap1_core_2x_clk",
4824 			.ops = &clk_branch2_ops,
4825 		},
4826 	},
4827 };
4828 
4829 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
4830 	.halt_reg = 0x1800c,
4831 	.halt_check = BRANCH_HALT_VOTED,
4832 	.clkr = {
4833 		.enable_reg = 0x52008,
4834 		.enable_mask = BIT(19),
4835 		.hw.init = &(const struct clk_init_data) {
4836 			.name = "gcc_qupv3_wrap1_core_clk",
4837 			.ops = &clk_branch2_ops,
4838 		},
4839 	},
4840 };
4841 
4842 static struct clk_branch gcc_qupv3_wrap1_qspi0_clk = {
4843 	.halt_reg = 0x18ac4,
4844 	.halt_check = BRANCH_HALT_VOTED,
4845 	.clkr = {
4846 		.enable_reg = 0x52020,
4847 		.enable_mask = BIT(2),
4848 		.hw.init = &(const struct clk_init_data) {
4849 			.name = "gcc_qupv3_wrap1_qspi0_clk",
4850 			.parent_hws = (const struct clk_hw*[]){
4851 				&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
4852 			},
4853 			.num_parents = 1,
4854 			.flags = CLK_SET_RATE_PARENT,
4855 			.ops = &clk_branch2_ops,
4856 		},
4857 	},
4858 };
4859 
4860 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
4861 	.halt_reg = 0x18144,
4862 	.halt_check = BRANCH_HALT_VOTED,
4863 	.clkr = {
4864 		.enable_reg = 0x52008,
4865 		.enable_mask = BIT(22),
4866 		.hw.init = &(const struct clk_init_data) {
4867 			.name = "gcc_qupv3_wrap1_s0_clk",
4868 			.parent_hws = (const struct clk_hw*[]){
4869 				&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
4870 			},
4871 			.num_parents = 1,
4872 			.flags = CLK_SET_RATE_PARENT,
4873 			.ops = &clk_branch2_ops,
4874 		},
4875 	},
4876 };
4877 
4878 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
4879 	.halt_reg = 0x18274,
4880 	.halt_check = BRANCH_HALT_VOTED,
4881 	.clkr = {
4882 		.enable_reg = 0x52008,
4883 		.enable_mask = BIT(23),
4884 		.hw.init = &(const struct clk_init_data) {
4885 			.name = "gcc_qupv3_wrap1_s1_clk",
4886 			.parent_hws = (const struct clk_hw*[]){
4887 				&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
4888 			},
4889 			.num_parents = 1,
4890 			.flags = CLK_SET_RATE_PARENT,
4891 			.ops = &clk_branch2_ops,
4892 		},
4893 	},
4894 };
4895 
4896 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
4897 	.halt_reg = 0x183a4,
4898 	.halt_check = BRANCH_HALT_VOTED,
4899 	.clkr = {
4900 		.enable_reg = 0x52008,
4901 		.enable_mask = BIT(24),
4902 		.hw.init = &(const struct clk_init_data) {
4903 			.name = "gcc_qupv3_wrap1_s2_clk",
4904 			.parent_hws = (const struct clk_hw*[]){
4905 				&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
4906 			},
4907 			.num_parents = 1,
4908 			.flags = CLK_SET_RATE_PARENT,
4909 			.ops = &clk_branch2_ops,
4910 		},
4911 	},
4912 };
4913 
4914 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
4915 	.halt_reg = 0x184d4,
4916 	.halt_check = BRANCH_HALT_VOTED,
4917 	.clkr = {
4918 		.enable_reg = 0x52008,
4919 		.enable_mask = BIT(25),
4920 		.hw.init = &(const struct clk_init_data) {
4921 			.name = "gcc_qupv3_wrap1_s3_clk",
4922 			.parent_hws = (const struct clk_hw*[]){
4923 				&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
4924 			},
4925 			.num_parents = 1,
4926 			.flags = CLK_SET_RATE_PARENT,
4927 			.ops = &clk_branch2_ops,
4928 		},
4929 	},
4930 };
4931 
4932 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
4933 	.halt_reg = 0x18604,
4934 	.halt_check = BRANCH_HALT_VOTED,
4935 	.clkr = {
4936 		.enable_reg = 0x52008,
4937 		.enable_mask = BIT(26),
4938 		.hw.init = &(const struct clk_init_data) {
4939 			.name = "gcc_qupv3_wrap1_s4_clk",
4940 			.parent_hws = (const struct clk_hw*[]){
4941 				&gcc_qupv3_wrap1_s4_div_clk_src.clkr.hw,
4942 			},
4943 			.num_parents = 1,
4944 			.flags = CLK_SET_RATE_PARENT,
4945 			.ops = &clk_branch2_ops,
4946 		},
4947 	},
4948 };
4949 
4950 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
4951 	.halt_reg = 0x18734,
4952 	.halt_check = BRANCH_HALT_VOTED,
4953 	.clkr = {
4954 		.enable_reg = 0x52008,
4955 		.enable_mask = BIT(27),
4956 		.hw.init = &(const struct clk_init_data) {
4957 			.name = "gcc_qupv3_wrap1_s5_clk",
4958 			.parent_hws = (const struct clk_hw*[]){
4959 				&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
4960 			},
4961 			.num_parents = 1,
4962 			.flags = CLK_SET_RATE_PARENT,
4963 			.ops = &clk_branch2_ops,
4964 		},
4965 	},
4966 };
4967 
4968 static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
4969 	.halt_reg = 0x18864,
4970 	.halt_check = BRANCH_HALT_VOTED,
4971 	.clkr = {
4972 		.enable_reg = 0x52018,
4973 		.enable_mask = BIT(27),
4974 		.hw.init = &(const struct clk_init_data) {
4975 			.name = "gcc_qupv3_wrap1_s6_clk",
4976 			.parent_hws = (const struct clk_hw*[]){
4977 				&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
4978 			},
4979 			.num_parents = 1,
4980 			.flags = CLK_SET_RATE_PARENT,
4981 			.ops = &clk_branch2_ops,
4982 		},
4983 	},
4984 };
4985 
4986 static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
4987 	.halt_reg = 0x18994,
4988 	.halt_check = BRANCH_HALT_VOTED,
4989 	.clkr = {
4990 		.enable_reg = 0x52018,
4991 		.enable_mask = BIT(28),
4992 		.hw.init = &(const struct clk_init_data) {
4993 			.name = "gcc_qupv3_wrap1_s7_clk",
4994 			.parent_hws = (const struct clk_hw*[]){
4995 				&gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
4996 			},
4997 			.num_parents = 1,
4998 			.flags = CLK_SET_RATE_PARENT,
4999 			.ops = &clk_branch2_ops,
5000 		},
5001 	},
5002 };
5003 
5004 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
5005 	.halt_reg = 0x1e014,
5006 	.halt_check = BRANCH_HALT_VOTED,
5007 	.clkr = {
5008 		.enable_reg = 0x52010,
5009 		.enable_mask = BIT(3),
5010 		.hw.init = &(const struct clk_init_data) {
5011 			.name = "gcc_qupv3_wrap2_core_2x_clk",
5012 			.ops = &clk_branch2_ops,
5013 		},
5014 	},
5015 };
5016 
5017 static struct clk_branch gcc_qupv3_wrap2_core_clk = {
5018 	.halt_reg = 0x1e00c,
5019 	.halt_check = BRANCH_HALT_VOTED,
5020 	.clkr = {
5021 		.enable_reg = 0x52010,
5022 		.enable_mask = BIT(0),
5023 		.hw.init = &(const struct clk_init_data) {
5024 			.name = "gcc_qupv3_wrap2_core_clk",
5025 			.ops = &clk_branch2_ops,
5026 		},
5027 	},
5028 };
5029 
5030 static struct clk_branch gcc_qupv3_wrap2_qspi0_clk = {
5031 	.halt_reg = 0x1eac4,
5032 	.halt_check = BRANCH_HALT_VOTED,
5033 	.clkr = {
5034 		.enable_reg = 0x52020,
5035 		.enable_mask = BIT(4),
5036 		.hw.init = &(const struct clk_init_data) {
5037 			.name = "gcc_qupv3_wrap2_qspi0_clk",
5038 			.parent_hws = (const struct clk_hw*[]){
5039 				&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
5040 			},
5041 			.num_parents = 1,
5042 			.flags = CLK_SET_RATE_PARENT,
5043 			.ops = &clk_branch2_ops,
5044 		},
5045 	},
5046 };
5047 
5048 static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
5049 	.halt_reg = 0x1e144,
5050 	.halt_check = BRANCH_HALT_VOTED,
5051 	.clkr = {
5052 		.enable_reg = 0x52010,
5053 		.enable_mask = BIT(4),
5054 		.hw.init = &(const struct clk_init_data) {
5055 			.name = "gcc_qupv3_wrap2_s0_clk",
5056 			.parent_hws = (const struct clk_hw*[]){
5057 				&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
5058 			},
5059 			.num_parents = 1,
5060 			.flags = CLK_SET_RATE_PARENT,
5061 			.ops = &clk_branch2_ops,
5062 		},
5063 	},
5064 };
5065 
5066 static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
5067 	.halt_reg = 0x1e274,
5068 	.halt_check = BRANCH_HALT_VOTED,
5069 	.clkr = {
5070 		.enable_reg = 0x52010,
5071 		.enable_mask = BIT(5),
5072 		.hw.init = &(const struct clk_init_data) {
5073 			.name = "gcc_qupv3_wrap2_s1_clk",
5074 			.parent_hws = (const struct clk_hw*[]){
5075 				&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
5076 			},
5077 			.num_parents = 1,
5078 			.flags = CLK_SET_RATE_PARENT,
5079 			.ops = &clk_branch2_ops,
5080 		},
5081 	},
5082 };
5083 
5084 static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
5085 	.halt_reg = 0x1e3a4,
5086 	.halt_check = BRANCH_HALT_VOTED,
5087 	.clkr = {
5088 		.enable_reg = 0x52010,
5089 		.enable_mask = BIT(6),
5090 		.hw.init = &(const struct clk_init_data) {
5091 			.name = "gcc_qupv3_wrap2_s2_clk",
5092 			.parent_hws = (const struct clk_hw*[]){
5093 				&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
5094 			},
5095 			.num_parents = 1,
5096 			.flags = CLK_SET_RATE_PARENT,
5097 			.ops = &clk_branch2_ops,
5098 		},
5099 	},
5100 };
5101 
5102 static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
5103 	.halt_reg = 0x1e4d4,
5104 	.halt_check = BRANCH_HALT_VOTED,
5105 	.clkr = {
5106 		.enable_reg = 0x52010,
5107 		.enable_mask = BIT(7),
5108 		.hw.init = &(const struct clk_init_data) {
5109 			.name = "gcc_qupv3_wrap2_s3_clk",
5110 			.parent_hws = (const struct clk_hw*[]){
5111 				&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
5112 			},
5113 			.num_parents = 1,
5114 			.flags = CLK_SET_RATE_PARENT,
5115 			.ops = &clk_branch2_ops,
5116 		},
5117 	},
5118 };
5119 
5120 static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
5121 	.halt_reg = 0x1e604,
5122 	.halt_check = BRANCH_HALT_VOTED,
5123 	.clkr = {
5124 		.enable_reg = 0x52010,
5125 		.enable_mask = BIT(8),
5126 		.hw.init = &(const struct clk_init_data) {
5127 			.name = "gcc_qupv3_wrap2_s4_clk",
5128 			.parent_hws = (const struct clk_hw*[]){
5129 				&gcc_qupv3_wrap2_s4_div_clk_src.clkr.hw,
5130 			},
5131 			.num_parents = 1,
5132 			.flags = CLK_SET_RATE_PARENT,
5133 			.ops = &clk_branch2_ops,
5134 		},
5135 	},
5136 };
5137 
5138 static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
5139 	.halt_reg = 0x1e734,
5140 	.halt_check = BRANCH_HALT_VOTED,
5141 	.clkr = {
5142 		.enable_reg = 0x52010,
5143 		.enable_mask = BIT(9),
5144 		.hw.init = &(const struct clk_init_data) {
5145 			.name = "gcc_qupv3_wrap2_s5_clk",
5146 			.parent_hws = (const struct clk_hw*[]){
5147 				&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
5148 			},
5149 			.num_parents = 1,
5150 			.flags = CLK_SET_RATE_PARENT,
5151 			.ops = &clk_branch2_ops,
5152 		},
5153 	},
5154 };
5155 
5156 static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
5157 	.halt_reg = 0x1e864,
5158 	.halt_check = BRANCH_HALT_VOTED,
5159 	.clkr = {
5160 		.enable_reg = 0x52018,
5161 		.enable_mask = BIT(29),
5162 		.hw.init = &(const struct clk_init_data) {
5163 			.name = "gcc_qupv3_wrap2_s6_clk",
5164 			.parent_hws = (const struct clk_hw*[]){
5165 				&gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
5166 			},
5167 			.num_parents = 1,
5168 			.flags = CLK_SET_RATE_PARENT,
5169 			.ops = &clk_branch2_ops,
5170 		},
5171 	},
5172 };
5173 
5174 static struct clk_branch gcc_qupv3_wrap2_s7_clk = {
5175 	.halt_reg = 0x1e994,
5176 	.halt_check = BRANCH_HALT_VOTED,
5177 	.clkr = {
5178 		.enable_reg = 0x52018,
5179 		.enable_mask = BIT(30),
5180 		.hw.init = &(const struct clk_init_data) {
5181 			.name = "gcc_qupv3_wrap2_s7_clk",
5182 			.parent_hws = (const struct clk_hw*[]){
5183 				&gcc_qupv3_wrap2_s7_clk_src.clkr.hw,
5184 			},
5185 			.num_parents = 1,
5186 			.flags = CLK_SET_RATE_PARENT,
5187 			.ops = &clk_branch2_ops,
5188 		},
5189 	},
5190 };
5191 
5192 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
5193 	.halt_reg = 0x17004,
5194 	.halt_check = BRANCH_HALT_VOTED,
5195 	.hwcg_reg = 0x17004,
5196 	.hwcg_bit = 1,
5197 	.clkr = {
5198 		.enable_reg = 0x52008,
5199 		.enable_mask = BIT(6),
5200 		.hw.init = &(const struct clk_init_data) {
5201 			.name = "gcc_qupv3_wrap_0_m_ahb_clk",
5202 			.ops = &clk_branch2_ops,
5203 		},
5204 	},
5205 };
5206 
5207 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
5208 	.halt_reg = 0x17008,
5209 	.halt_check = BRANCH_HALT_VOTED,
5210 	.hwcg_reg = 0x17008,
5211 	.hwcg_bit = 1,
5212 	.clkr = {
5213 		.enable_reg = 0x52008,
5214 		.enable_mask = BIT(7),
5215 		.hw.init = &(const struct clk_init_data) {
5216 			.name = "gcc_qupv3_wrap_0_s_ahb_clk",
5217 			.ops = &clk_branch2_ops,
5218 		},
5219 	},
5220 };
5221 
5222 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
5223 	.halt_reg = 0x18004,
5224 	.halt_check = BRANCH_HALT_VOTED,
5225 	.hwcg_reg = 0x18004,
5226 	.hwcg_bit = 1,
5227 	.clkr = {
5228 		.enable_reg = 0x52008,
5229 		.enable_mask = BIT(20),
5230 		.hw.init = &(const struct clk_init_data) {
5231 			.name = "gcc_qupv3_wrap_1_m_ahb_clk",
5232 			.ops = &clk_branch2_ops,
5233 		},
5234 	},
5235 };
5236 
5237 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
5238 	.halt_reg = 0x18008,
5239 	.halt_check = BRANCH_HALT_VOTED,
5240 	.hwcg_reg = 0x18008,
5241 	.hwcg_bit = 1,
5242 	.clkr = {
5243 		.enable_reg = 0x52008,
5244 		.enable_mask = BIT(21),
5245 		.hw.init = &(const struct clk_init_data) {
5246 			.name = "gcc_qupv3_wrap_1_s_ahb_clk",
5247 			.ops = &clk_branch2_ops,
5248 		},
5249 	},
5250 };
5251 
5252 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
5253 	.halt_reg = 0x1e004,
5254 	.halt_check = BRANCH_HALT_VOTED,
5255 	.hwcg_reg = 0x1e004,
5256 	.hwcg_bit = 1,
5257 	.clkr = {
5258 		.enable_reg = 0x52010,
5259 		.enable_mask = BIT(2),
5260 		.hw.init = &(const struct clk_init_data) {
5261 			.name = "gcc_qupv3_wrap_2_m_ahb_clk",
5262 			.ops = &clk_branch2_ops,
5263 		},
5264 	},
5265 };
5266 
5267 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
5268 	.halt_reg = 0x1e008,
5269 	.halt_check = BRANCH_HALT_VOTED,
5270 	.hwcg_reg = 0x1e008,
5271 	.hwcg_bit = 1,
5272 	.clkr = {
5273 		.enable_reg = 0x52010,
5274 		.enable_mask = BIT(1),
5275 		.hw.init = &(const struct clk_init_data) {
5276 			.name = "gcc_qupv3_wrap_2_s_ahb_clk",
5277 			.ops = &clk_branch2_ops,
5278 		},
5279 	},
5280 };
5281 
5282 static struct clk_branch gcc_sdcc2_ahb_clk = {
5283 	.halt_reg = 0x14008,
5284 	.halt_check = BRANCH_HALT,
5285 	.clkr = {
5286 		.enable_reg = 0x14008,
5287 		.enable_mask = BIT(0),
5288 		.hw.init = &(const struct clk_init_data) {
5289 			.name = "gcc_sdcc2_ahb_clk",
5290 			.ops = &clk_branch2_ops,
5291 		},
5292 	},
5293 };
5294 
5295 static struct clk_branch gcc_sdcc2_apps_clk = {
5296 	.halt_reg = 0x14004,
5297 	.halt_check = BRANCH_HALT,
5298 	.clkr = {
5299 		.enable_reg = 0x14004,
5300 		.enable_mask = BIT(0),
5301 		.hw.init = &(const struct clk_init_data) {
5302 			.name = "gcc_sdcc2_apps_clk",
5303 			.parent_hws = (const struct clk_hw*[]){
5304 				&gcc_sdcc2_apps_clk_src.clkr.hw,
5305 			},
5306 			.num_parents = 1,
5307 			.flags = CLK_SET_RATE_PARENT,
5308 			.ops = &clk_branch2_ops,
5309 		},
5310 	},
5311 };
5312 
5313 static struct clk_branch gcc_sdcc4_ahb_clk = {
5314 	.halt_reg = 0x16008,
5315 	.halt_check = BRANCH_HALT,
5316 	.clkr = {
5317 		.enable_reg = 0x16008,
5318 		.enable_mask = BIT(0),
5319 		.hw.init = &(const struct clk_init_data) {
5320 			.name = "gcc_sdcc4_ahb_clk",
5321 			.ops = &clk_branch2_ops,
5322 		},
5323 	},
5324 };
5325 
5326 static struct clk_branch gcc_sdcc4_apps_clk = {
5327 	.halt_reg = 0x16004,
5328 	.halt_check = BRANCH_HALT,
5329 	.clkr = {
5330 		.enable_reg = 0x16004,
5331 		.enable_mask = BIT(0),
5332 		.hw.init = &(const struct clk_init_data) {
5333 			.name = "gcc_sdcc4_apps_clk",
5334 			.parent_hws = (const struct clk_hw*[]){
5335 				&gcc_sdcc4_apps_clk_src.clkr.hw,
5336 			},
5337 			.num_parents = 1,
5338 			.flags = CLK_SET_RATE_PARENT,
5339 			.ops = &clk_branch2_ops,
5340 		},
5341 	},
5342 };
5343 
5344 static struct clk_branch gcc_sys_noc_usb_axi_clk = {
5345 	.halt_reg = 0x5d000,
5346 	.halt_check = BRANCH_HALT_VOTED,
5347 	.hwcg_reg = 0x5d000,
5348 	.hwcg_bit = 1,
5349 	.clkr = {
5350 		.enable_reg = 0x5d000,
5351 		.enable_mask = BIT(0),
5352 		.hw.init = &(const struct clk_init_data) {
5353 			.name = "gcc_sys_noc_usb_axi_clk",
5354 			.ops = &clk_branch2_ops,
5355 		},
5356 	},
5357 };
5358 
5359 static struct clk_branch gcc_ufs_1_card_clkref_clk = {
5360 	.halt_reg = 0x8c000,
5361 	.halt_check = BRANCH_HALT,
5362 	.clkr = {
5363 		.enable_reg = 0x8c000,
5364 		.enable_mask = BIT(0),
5365 		.hw.init = &(const struct clk_init_data) {
5366 			.name = "gcc_ufs_1_card_clkref_clk",
5367 			.ops = &clk_branch2_ops,
5368 		},
5369 	},
5370 };
5371 
5372 static struct clk_branch gcc_ufs_card_ahb_clk = {
5373 	.halt_reg = 0x75018,
5374 	.halt_check = BRANCH_HALT_VOTED,
5375 	.hwcg_reg = 0x75018,
5376 	.hwcg_bit = 1,
5377 	.clkr = {
5378 		.enable_reg = 0x75018,
5379 		.enable_mask = BIT(0),
5380 		.hw.init = &(const struct clk_init_data) {
5381 			.name = "gcc_ufs_card_ahb_clk",
5382 			.ops = &clk_branch2_ops,
5383 		},
5384 	},
5385 };
5386 
5387 static struct clk_branch gcc_ufs_card_axi_clk = {
5388 	.halt_reg = 0x75010,
5389 	.halt_check = BRANCH_HALT_VOTED,
5390 	.hwcg_reg = 0x75010,
5391 	.hwcg_bit = 1,
5392 	.clkr = {
5393 		.enable_reg = 0x75010,
5394 		.enable_mask = BIT(0),
5395 		.hw.init = &(const struct clk_init_data) {
5396 			.name = "gcc_ufs_card_axi_clk",
5397 			.parent_hws = (const struct clk_hw*[]){
5398 				&gcc_ufs_card_axi_clk_src.clkr.hw,
5399 			},
5400 			.num_parents = 1,
5401 			.flags = CLK_SET_RATE_PARENT,
5402 			.ops = &clk_branch2_ops,
5403 		},
5404 	},
5405 };
5406 
5407 static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
5408 	.halt_reg = 0x75010,
5409 	.halt_check = BRANCH_HALT_VOTED,
5410 	.hwcg_reg = 0x75010,
5411 	.hwcg_bit = 1,
5412 	.clkr = {
5413 		.enable_reg = 0x75010,
5414 		.enable_mask = BIT(1),
5415 		.hw.init = &(const struct clk_init_data) {
5416 			.name = "gcc_ufs_card_axi_hw_ctl_clk",
5417 			.parent_hws = (const struct clk_hw*[]){
5418 				&gcc_ufs_card_axi_clk_src.clkr.hw,
5419 			},
5420 			.num_parents = 1,
5421 			.flags = CLK_SET_RATE_PARENT,
5422 			.ops = &clk_branch2_ops,
5423 		},
5424 	},
5425 };
5426 
5427 static struct clk_branch gcc_ufs_card_clkref_clk = {
5428 	.halt_reg = 0x8c054,
5429 	.halt_check = BRANCH_HALT,
5430 	.clkr = {
5431 		.enable_reg = 0x8c054,
5432 		.enable_mask = BIT(0),
5433 		.hw.init = &(const struct clk_init_data) {
5434 			.name = "gcc_ufs_card_clkref_clk",
5435 			.ops = &clk_branch2_ops,
5436 		},
5437 	},
5438 };
5439 
5440 static struct clk_branch gcc_ufs_card_ice_core_clk = {
5441 	.halt_reg = 0x75064,
5442 	.halt_check = BRANCH_HALT_VOTED,
5443 	.hwcg_reg = 0x75064,
5444 	.hwcg_bit = 1,
5445 	.clkr = {
5446 		.enable_reg = 0x75064,
5447 		.enable_mask = BIT(0),
5448 		.hw.init = &(const struct clk_init_data) {
5449 			.name = "gcc_ufs_card_ice_core_clk",
5450 			.parent_hws = (const struct clk_hw*[]){
5451 				&gcc_ufs_card_ice_core_clk_src.clkr.hw,
5452 			},
5453 			.num_parents = 1,
5454 			.flags = CLK_SET_RATE_PARENT,
5455 			.ops = &clk_branch2_ops,
5456 		},
5457 	},
5458 };
5459 
5460 static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
5461 	.halt_reg = 0x75064,
5462 	.halt_check = BRANCH_HALT_VOTED,
5463 	.hwcg_reg = 0x75064,
5464 	.hwcg_bit = 1,
5465 	.clkr = {
5466 		.enable_reg = 0x75064,
5467 		.enable_mask = BIT(1),
5468 		.hw.init = &(const struct clk_init_data) {
5469 			.name = "gcc_ufs_card_ice_core_hw_ctl_clk",
5470 			.parent_hws = (const struct clk_hw*[]){
5471 				&gcc_ufs_card_ice_core_clk_src.clkr.hw,
5472 			},
5473 			.num_parents = 1,
5474 			.flags = CLK_SET_RATE_PARENT,
5475 			.ops = &clk_branch2_ops,
5476 		},
5477 	},
5478 };
5479 
5480 static struct clk_branch gcc_ufs_card_phy_aux_clk = {
5481 	.halt_reg = 0x7509c,
5482 	.halt_check = BRANCH_HALT_VOTED,
5483 	.hwcg_reg = 0x7509c,
5484 	.hwcg_bit = 1,
5485 	.clkr = {
5486 		.enable_reg = 0x7509c,
5487 		.enable_mask = BIT(0),
5488 		.hw.init = &(const struct clk_init_data) {
5489 			.name = "gcc_ufs_card_phy_aux_clk",
5490 			.parent_hws = (const struct clk_hw*[]){
5491 				&gcc_ufs_card_phy_aux_clk_src.clkr.hw,
5492 			},
5493 			.num_parents = 1,
5494 			.flags = CLK_SET_RATE_PARENT,
5495 			.ops = &clk_branch2_ops,
5496 		},
5497 	},
5498 };
5499 
5500 static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
5501 	.halt_reg = 0x7509c,
5502 	.halt_check = BRANCH_HALT_VOTED,
5503 	.hwcg_reg = 0x7509c,
5504 	.hwcg_bit = 1,
5505 	.clkr = {
5506 		.enable_reg = 0x7509c,
5507 		.enable_mask = BIT(1),
5508 		.hw.init = &(const struct clk_init_data) {
5509 			.name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
5510 			.parent_hws = (const struct clk_hw*[]){
5511 				&gcc_ufs_card_phy_aux_clk_src.clkr.hw,
5512 			},
5513 			.num_parents = 1,
5514 			.flags = CLK_SET_RATE_PARENT,
5515 			.ops = &clk_branch2_ops,
5516 		},
5517 	},
5518 };
5519 
5520 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
5521 	.halt_reg = 0x75020,
5522 	.halt_check = BRANCH_HALT_DELAY,
5523 	.clkr = {
5524 		.enable_reg = 0x75020,
5525 		.enable_mask = BIT(0),
5526 		.hw.init = &(const struct clk_init_data) {
5527 			.name = "gcc_ufs_card_rx_symbol_0_clk",
5528 			.parent_hws = (const struct clk_hw*[]){
5529 				&gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw,
5530 			},
5531 			.num_parents = 1,
5532 			.flags = CLK_SET_RATE_PARENT,
5533 			.ops = &clk_branch2_ops,
5534 		},
5535 	},
5536 };
5537 
5538 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
5539 	.halt_reg = 0x750b8,
5540 	.halt_check = BRANCH_HALT_DELAY,
5541 	.clkr = {
5542 		.enable_reg = 0x750b8,
5543 		.enable_mask = BIT(0),
5544 		.hw.init = &(const struct clk_init_data) {
5545 			.name = "gcc_ufs_card_rx_symbol_1_clk",
5546 			.parent_hws = (const struct clk_hw*[]){
5547 				&gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw,
5548 			},
5549 			.num_parents = 1,
5550 			.flags = CLK_SET_RATE_PARENT,
5551 			.ops = &clk_branch2_ops,
5552 		},
5553 	},
5554 };
5555 
5556 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
5557 	.halt_reg = 0x7501c,
5558 	.halt_check = BRANCH_HALT_DELAY,
5559 	.clkr = {
5560 		.enable_reg = 0x7501c,
5561 		.enable_mask = BIT(0),
5562 		.hw.init = &(const struct clk_init_data) {
5563 			.name = "gcc_ufs_card_tx_symbol_0_clk",
5564 			.parent_hws = (const struct clk_hw*[]){
5565 				&gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw,
5566 			},
5567 			.num_parents = 1,
5568 			.flags = CLK_SET_RATE_PARENT,
5569 			.ops = &clk_branch2_ops,
5570 		},
5571 	},
5572 };
5573 
5574 static struct clk_branch gcc_ufs_card_unipro_core_clk = {
5575 	.halt_reg = 0x7505c,
5576 	.halt_check = BRANCH_HALT_VOTED,
5577 	.hwcg_reg = 0x7505c,
5578 	.hwcg_bit = 1,
5579 	.clkr = {
5580 		.enable_reg = 0x7505c,
5581 		.enable_mask = BIT(0),
5582 		.hw.init = &(const struct clk_init_data) {
5583 			.name = "gcc_ufs_card_unipro_core_clk",
5584 			.parent_hws = (const struct clk_hw*[]){
5585 				&gcc_ufs_card_unipro_core_clk_src.clkr.hw,
5586 			},
5587 			.num_parents = 1,
5588 			.flags = CLK_SET_RATE_PARENT,
5589 			.ops = &clk_branch2_ops,
5590 		},
5591 	},
5592 };
5593 
5594 static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
5595 	.halt_reg = 0x7505c,
5596 	.halt_check = BRANCH_HALT_VOTED,
5597 	.hwcg_reg = 0x7505c,
5598 	.hwcg_bit = 1,
5599 	.clkr = {
5600 		.enable_reg = 0x7505c,
5601 		.enable_mask = BIT(1),
5602 		.hw.init = &(const struct clk_init_data) {
5603 			.name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
5604 			.parent_hws = (const struct clk_hw*[]){
5605 				&gcc_ufs_card_unipro_core_clk_src.clkr.hw,
5606 			},
5607 			.num_parents = 1,
5608 			.flags = CLK_SET_RATE_PARENT,
5609 			.ops = &clk_branch2_ops,
5610 		},
5611 	},
5612 };
5613 
5614 static struct clk_branch gcc_ufs_phy_ahb_clk = {
5615 	.halt_reg = 0x77018,
5616 	.halt_check = BRANCH_HALT_VOTED,
5617 	.hwcg_reg = 0x77018,
5618 	.hwcg_bit = 1,
5619 	.clkr = {
5620 		.enable_reg = 0x77018,
5621 		.enable_mask = BIT(0),
5622 		.hw.init = &(const struct clk_init_data) {
5623 			.name = "gcc_ufs_phy_ahb_clk",
5624 			.ops = &clk_branch2_ops,
5625 		},
5626 	},
5627 };
5628 
5629 static struct clk_branch gcc_ufs_phy_axi_clk = {
5630 	.halt_reg = 0x77010,
5631 	.halt_check = BRANCH_HALT_VOTED,
5632 	.hwcg_reg = 0x77010,
5633 	.hwcg_bit = 1,
5634 	.clkr = {
5635 		.enable_reg = 0x77010,
5636 		.enable_mask = BIT(0),
5637 		.hw.init = &(const struct clk_init_data) {
5638 			.name = "gcc_ufs_phy_axi_clk",
5639 			.parent_hws = (const struct clk_hw*[]){
5640 				&gcc_ufs_phy_axi_clk_src.clkr.hw,
5641 			},
5642 			.num_parents = 1,
5643 			.flags = CLK_SET_RATE_PARENT,
5644 			.ops = &clk_branch2_ops,
5645 		},
5646 	},
5647 };
5648 
5649 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
5650 	.halt_reg = 0x77010,
5651 	.halt_check = BRANCH_HALT_VOTED,
5652 	.hwcg_reg = 0x77010,
5653 	.hwcg_bit = 1,
5654 	.clkr = {
5655 		.enable_reg = 0x77010,
5656 		.enable_mask = BIT(1),
5657 		.hw.init = &(const struct clk_init_data) {
5658 			.name = "gcc_ufs_phy_axi_hw_ctl_clk",
5659 			.parent_hws = (const struct clk_hw*[]){
5660 				&gcc_ufs_phy_axi_clk_src.clkr.hw,
5661 			},
5662 			.num_parents = 1,
5663 			.flags = CLK_SET_RATE_PARENT,
5664 			.ops = &clk_branch2_ops,
5665 		},
5666 	},
5667 };
5668 
5669 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
5670 	.halt_reg = 0x77064,
5671 	.halt_check = BRANCH_HALT_VOTED,
5672 	.hwcg_reg = 0x77064,
5673 	.hwcg_bit = 1,
5674 	.clkr = {
5675 		.enable_reg = 0x77064,
5676 		.enable_mask = BIT(0),
5677 		.hw.init = &(const struct clk_init_data) {
5678 			.name = "gcc_ufs_phy_ice_core_clk",
5679 			.parent_hws = (const struct clk_hw*[]){
5680 				&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
5681 			},
5682 			.num_parents = 1,
5683 			.flags = CLK_SET_RATE_PARENT,
5684 			.ops = &clk_branch2_ops,
5685 		},
5686 	},
5687 };
5688 
5689 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
5690 	.halt_reg = 0x77064,
5691 	.halt_check = BRANCH_HALT_VOTED,
5692 	.hwcg_reg = 0x77064,
5693 	.hwcg_bit = 1,
5694 	.clkr = {
5695 		.enable_reg = 0x77064,
5696 		.enable_mask = BIT(1),
5697 		.hw.init = &(const struct clk_init_data) {
5698 			.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
5699 			.parent_hws = (const struct clk_hw*[]){
5700 				&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
5701 			},
5702 			.num_parents = 1,
5703 			.flags = CLK_SET_RATE_PARENT,
5704 			.ops = &clk_branch2_ops,
5705 		},
5706 	},
5707 };
5708 
5709 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
5710 	.halt_reg = 0x7709c,
5711 	.halt_check = BRANCH_HALT_VOTED,
5712 	.hwcg_reg = 0x7709c,
5713 	.hwcg_bit = 1,
5714 	.clkr = {
5715 		.enable_reg = 0x7709c,
5716 		.enable_mask = BIT(0),
5717 		.hw.init = &(const struct clk_init_data) {
5718 			.name = "gcc_ufs_phy_phy_aux_clk",
5719 			.parent_hws = (const struct clk_hw*[]){
5720 				&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
5721 			},
5722 			.num_parents = 1,
5723 			.flags = CLK_SET_RATE_PARENT,
5724 			.ops = &clk_branch2_ops,
5725 		},
5726 	},
5727 };
5728 
5729 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
5730 	.halt_reg = 0x7709c,
5731 	.halt_check = BRANCH_HALT_VOTED,
5732 	.hwcg_reg = 0x7709c,
5733 	.hwcg_bit = 1,
5734 	.clkr = {
5735 		.enable_reg = 0x7709c,
5736 		.enable_mask = BIT(1),
5737 		.hw.init = &(const struct clk_init_data) {
5738 			.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
5739 			.parent_hws = (const struct clk_hw*[]){
5740 				&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
5741 			},
5742 			.num_parents = 1,
5743 			.flags = CLK_SET_RATE_PARENT,
5744 			.ops = &clk_branch2_ops,
5745 		},
5746 	},
5747 };
5748 
5749 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
5750 	.halt_reg = 0x77020,
5751 	.halt_check = BRANCH_HALT_DELAY,
5752 	.clkr = {
5753 		.enable_reg = 0x77020,
5754 		.enable_mask = BIT(0),
5755 		.hw.init = &(const struct clk_init_data) {
5756 			.name = "gcc_ufs_phy_rx_symbol_0_clk",
5757 			.parent_hws = (const struct clk_hw*[]){
5758 				&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
5759 			},
5760 			.num_parents = 1,
5761 			.flags = CLK_SET_RATE_PARENT,
5762 			.ops = &clk_branch2_ops,
5763 		},
5764 	},
5765 };
5766 
5767 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
5768 	.halt_reg = 0x770b8,
5769 	.halt_check = BRANCH_HALT_DELAY,
5770 	.clkr = {
5771 		.enable_reg = 0x770b8,
5772 		.enable_mask = BIT(0),
5773 		.hw.init = &(const struct clk_init_data) {
5774 			.name = "gcc_ufs_phy_rx_symbol_1_clk",
5775 			.parent_hws = (const struct clk_hw*[]){
5776 				&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
5777 			},
5778 			.num_parents = 1,
5779 			.flags = CLK_SET_RATE_PARENT,
5780 			.ops = &clk_branch2_ops,
5781 		},
5782 	},
5783 };
5784 
5785 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
5786 	.halt_reg = 0x7701c,
5787 	.halt_check = BRANCH_HALT_DELAY,
5788 	.clkr = {
5789 		.enable_reg = 0x7701c,
5790 		.enable_mask = BIT(0),
5791 		.hw.init = &(const struct clk_init_data) {
5792 			.name = "gcc_ufs_phy_tx_symbol_0_clk",
5793 			.parent_hws = (const struct clk_hw*[]){
5794 				&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
5795 			},
5796 			.num_parents = 1,
5797 			.flags = CLK_SET_RATE_PARENT,
5798 			.ops = &clk_branch2_ops,
5799 		},
5800 	},
5801 };
5802 
5803 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
5804 	.halt_reg = 0x7705c,
5805 	.halt_check = BRANCH_HALT_VOTED,
5806 	.hwcg_reg = 0x7705c,
5807 	.hwcg_bit = 1,
5808 	.clkr = {
5809 		.enable_reg = 0x7705c,
5810 		.enable_mask = BIT(0),
5811 		.hw.init = &(const struct clk_init_data) {
5812 			.name = "gcc_ufs_phy_unipro_core_clk",
5813 			.parent_hws = (const struct clk_hw*[]){
5814 				&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
5815 			},
5816 			.num_parents = 1,
5817 			.flags = CLK_SET_RATE_PARENT,
5818 			.ops = &clk_branch2_ops,
5819 		},
5820 	},
5821 };
5822 
5823 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
5824 	.halt_reg = 0x7705c,
5825 	.halt_check = BRANCH_HALT_VOTED,
5826 	.hwcg_reg = 0x7705c,
5827 	.hwcg_bit = 1,
5828 	.clkr = {
5829 		.enable_reg = 0x7705c,
5830 		.enable_mask = BIT(1),
5831 		.hw.init = &(const struct clk_init_data) {
5832 			.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
5833 			.parent_hws = (const struct clk_hw*[]){
5834 				&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
5835 			},
5836 			.num_parents = 1,
5837 			.flags = CLK_SET_RATE_PARENT,
5838 			.ops = &clk_branch2_ops,
5839 		},
5840 	},
5841 };
5842 
5843 static struct clk_branch gcc_ufs_ref_clkref_clk = {
5844 	.halt_reg = 0x8c058,
5845 	.halt_check = BRANCH_HALT,
5846 	.clkr = {
5847 		.enable_reg = 0x8c058,
5848 		.enable_mask = BIT(0),
5849 		.hw.init = &(const struct clk_init_data) {
5850 			.name = "gcc_ufs_ref_clkref_clk",
5851 			.ops = &clk_branch2_ops,
5852 		},
5853 	},
5854 };
5855 
5856 static struct clk_branch gcc_usb2_hs0_clkref_clk = {
5857 	.halt_reg = 0x8c044,
5858 	.halt_check = BRANCH_HALT,
5859 	.clkr = {
5860 		.enable_reg = 0x8c044,
5861 		.enable_mask = BIT(0),
5862 		.hw.init = &(const struct clk_init_data) {
5863 			.name = "gcc_usb2_hs0_clkref_clk",
5864 			.ops = &clk_branch2_ops,
5865 		},
5866 	},
5867 };
5868 
5869 static struct clk_branch gcc_usb2_hs1_clkref_clk = {
5870 	.halt_reg = 0x8c048,
5871 	.halt_check = BRANCH_HALT,
5872 	.clkr = {
5873 		.enable_reg = 0x8c048,
5874 		.enable_mask = BIT(0),
5875 		.hw.init = &(const struct clk_init_data) {
5876 			.name = "gcc_usb2_hs1_clkref_clk",
5877 			.ops = &clk_branch2_ops,
5878 		},
5879 	},
5880 };
5881 
5882 static struct clk_branch gcc_usb2_hs2_clkref_clk = {
5883 	.halt_reg = 0x8c04c,
5884 	.halt_check = BRANCH_HALT,
5885 	.clkr = {
5886 		.enable_reg = 0x8c04c,
5887 		.enable_mask = BIT(0),
5888 		.hw.init = &(const struct clk_init_data) {
5889 			.name = "gcc_usb2_hs2_clkref_clk",
5890 			.ops = &clk_branch2_ops,
5891 		},
5892 	},
5893 };
5894 
5895 static struct clk_branch gcc_usb2_hs3_clkref_clk = {
5896 	.halt_reg = 0x8c050,
5897 	.halt_check = BRANCH_HALT,
5898 	.clkr = {
5899 		.enable_reg = 0x8c050,
5900 		.enable_mask = BIT(0),
5901 		.hw.init = &(const struct clk_init_data) {
5902 			.name = "gcc_usb2_hs3_clkref_clk",
5903 			.ops = &clk_branch2_ops,
5904 		},
5905 	},
5906 };
5907 
5908 static struct clk_branch gcc_usb30_mp_master_clk = {
5909 	.halt_reg = 0xab010,
5910 	.halt_check = BRANCH_HALT,
5911 	.clkr = {
5912 		.enable_reg = 0xab010,
5913 		.enable_mask = BIT(0),
5914 		.hw.init = &(const struct clk_init_data) {
5915 			.name = "gcc_usb30_mp_master_clk",
5916 			.parent_hws = (const struct clk_hw*[]){
5917 				&gcc_usb30_mp_master_clk_src.clkr.hw,
5918 			},
5919 			.num_parents = 1,
5920 			.flags = CLK_SET_RATE_PARENT,
5921 			.ops = &clk_branch2_ops,
5922 		},
5923 	},
5924 };
5925 
5926 static struct clk_branch gcc_usb30_mp_mock_utmi_clk = {
5927 	.halt_reg = 0xab01c,
5928 	.halt_check = BRANCH_HALT,
5929 	.clkr = {
5930 		.enable_reg = 0xab01c,
5931 		.enable_mask = BIT(0),
5932 		.hw.init = &(const struct clk_init_data) {
5933 			.name = "gcc_usb30_mp_mock_utmi_clk",
5934 			.parent_hws = (const struct clk_hw*[]){
5935 				&gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr.hw,
5936 			},
5937 			.num_parents = 1,
5938 			.flags = CLK_SET_RATE_PARENT,
5939 			.ops = &clk_branch2_ops,
5940 		},
5941 	},
5942 };
5943 
5944 static struct clk_branch gcc_usb30_mp_sleep_clk = {
5945 	.halt_reg = 0xab018,
5946 	.halt_check = BRANCH_HALT,
5947 	.clkr = {
5948 		.enable_reg = 0xab018,
5949 		.enable_mask = BIT(0),
5950 		.hw.init = &(const struct clk_init_data) {
5951 			.name = "gcc_usb30_mp_sleep_clk",
5952 			.ops = &clk_branch2_ops,
5953 		},
5954 	},
5955 };
5956 
5957 static struct clk_branch gcc_usb30_prim_master_clk = {
5958 	.halt_reg = 0xf010,
5959 	.halt_check = BRANCH_HALT,
5960 	.clkr = {
5961 		.enable_reg = 0xf010,
5962 		.enable_mask = BIT(0),
5963 		.hw.init = &(const struct clk_init_data) {
5964 			.name = "gcc_usb30_prim_master_clk",
5965 			.parent_hws = (const struct clk_hw*[]){
5966 				&gcc_usb30_prim_master_clk_src.clkr.hw,
5967 			},
5968 			.num_parents = 1,
5969 			.flags = CLK_SET_RATE_PARENT,
5970 			.ops = &clk_branch2_ops,
5971 		},
5972 	},
5973 };
5974 
5975 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
5976 	.halt_reg = 0xf01c,
5977 	.halt_check = BRANCH_HALT,
5978 	.clkr = {
5979 		.enable_reg = 0xf01c,
5980 		.enable_mask = BIT(0),
5981 		.hw.init = &(const struct clk_init_data) {
5982 			.name = "gcc_usb30_prim_mock_utmi_clk",
5983 			.parent_hws = (const struct clk_hw*[]){
5984 				&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
5985 			},
5986 			.num_parents = 1,
5987 			.flags = CLK_SET_RATE_PARENT,
5988 			.ops = &clk_branch2_ops,
5989 		},
5990 	},
5991 };
5992 
5993 static struct clk_branch gcc_usb30_prim_sleep_clk = {
5994 	.halt_reg = 0xf018,
5995 	.halt_check = BRANCH_HALT,
5996 	.clkr = {
5997 		.enable_reg = 0xf018,
5998 		.enable_mask = BIT(0),
5999 		.hw.init = &(const struct clk_init_data) {
6000 			.name = "gcc_usb30_prim_sleep_clk",
6001 			.ops = &clk_branch2_ops,
6002 		},
6003 	},
6004 };
6005 
6006 static struct clk_branch gcc_usb30_sec_master_clk = {
6007 	.halt_reg = 0x10010,
6008 	.halt_check = BRANCH_HALT,
6009 	.clkr = {
6010 		.enable_reg = 0x10010,
6011 		.enable_mask = BIT(0),
6012 		.hw.init = &(const struct clk_init_data) {
6013 			.name = "gcc_usb30_sec_master_clk",
6014 			.parent_hws = (const struct clk_hw*[]){
6015 				&gcc_usb30_sec_master_clk_src.clkr.hw,
6016 			},
6017 			.num_parents = 1,
6018 			.flags = CLK_SET_RATE_PARENT,
6019 			.ops = &clk_branch2_ops,
6020 		},
6021 	},
6022 };
6023 
6024 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
6025 	.halt_reg = 0x1001c,
6026 	.halt_check = BRANCH_HALT,
6027 	.clkr = {
6028 		.enable_reg = 0x1001c,
6029 		.enable_mask = BIT(0),
6030 		.hw.init = &(const struct clk_init_data) {
6031 			.name = "gcc_usb30_sec_mock_utmi_clk",
6032 			.parent_hws = (const struct clk_hw*[]){
6033 				&gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
6034 			},
6035 			.num_parents = 1,
6036 			.flags = CLK_SET_RATE_PARENT,
6037 			.ops = &clk_branch2_ops,
6038 		},
6039 	},
6040 };
6041 
6042 static struct clk_branch gcc_usb30_sec_sleep_clk = {
6043 	.halt_reg = 0x10018,
6044 	.halt_check = BRANCH_HALT,
6045 	.clkr = {
6046 		.enable_reg = 0x10018,
6047 		.enable_mask = BIT(0),
6048 		.hw.init = &(const struct clk_init_data) {
6049 			.name = "gcc_usb30_sec_sleep_clk",
6050 			.ops = &clk_branch2_ops,
6051 		},
6052 	},
6053 };
6054 
6055 static struct clk_branch gcc_usb3_mp0_clkref_clk = {
6056 	.halt_reg = 0x8c03c,
6057 	.halt_check = BRANCH_HALT,
6058 	.clkr = {
6059 		.enable_reg = 0x8c03c,
6060 		.enable_mask = BIT(0),
6061 		.hw.init = &(const struct clk_init_data) {
6062 			.name = "gcc_usb3_mp0_clkref_clk",
6063 			.ops = &clk_branch2_ops,
6064 		},
6065 	},
6066 };
6067 
6068 static struct clk_branch gcc_usb3_mp1_clkref_clk = {
6069 	.halt_reg = 0x8c040,
6070 	.halt_check = BRANCH_HALT,
6071 	.clkr = {
6072 		.enable_reg = 0x8c040,
6073 		.enable_mask = BIT(0),
6074 		.hw.init = &(const struct clk_init_data) {
6075 			.name = "gcc_usb3_mp1_clkref_clk",
6076 			.ops = &clk_branch2_ops,
6077 		},
6078 	},
6079 };
6080 
6081 static struct clk_branch gcc_usb3_mp_phy_aux_clk = {
6082 	.halt_reg = 0xab054,
6083 	.halt_check = BRANCH_HALT,
6084 	.clkr = {
6085 		.enable_reg = 0xab054,
6086 		.enable_mask = BIT(0),
6087 		.hw.init = &(const struct clk_init_data) {
6088 			.name = "gcc_usb3_mp_phy_aux_clk",
6089 			.parent_hws = (const struct clk_hw*[]){
6090 				&gcc_usb3_mp_phy_aux_clk_src.clkr.hw,
6091 			},
6092 			.num_parents = 1,
6093 			.flags = CLK_SET_RATE_PARENT,
6094 			.ops = &clk_branch2_ops,
6095 		},
6096 	},
6097 };
6098 
6099 static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = {
6100 	.halt_reg = 0xab058,
6101 	.halt_check = BRANCH_HALT,
6102 	.clkr = {
6103 		.enable_reg = 0xab058,
6104 		.enable_mask = BIT(0),
6105 		.hw.init = &(const struct clk_init_data) {
6106 			.name = "gcc_usb3_mp_phy_com_aux_clk",
6107 			.parent_hws = (const struct clk_hw*[]){
6108 				&gcc_usb3_mp_phy_aux_clk_src.clkr.hw,
6109 			},
6110 			.num_parents = 1,
6111 			.flags = CLK_SET_RATE_PARENT,
6112 			.ops = &clk_branch2_ops,
6113 		},
6114 	},
6115 };
6116 
6117 static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = {
6118 	.halt_reg = 0xab05c,
6119 	.halt_check = BRANCH_HALT_DELAY,
6120 	.clkr = {
6121 		.enable_reg = 0xab05c,
6122 		.enable_mask = BIT(0),
6123 		.hw.init = &(const struct clk_init_data) {
6124 			.name = "gcc_usb3_mp_phy_pipe_0_clk",
6125 			.parent_hws = (const struct clk_hw*[]){
6126 				&gcc_usb3_mp_phy_pipe_0_clk_src.clkr.hw,
6127 			},
6128 			.num_parents = 1,
6129 			.flags = CLK_SET_RATE_PARENT,
6130 			.ops = &clk_branch2_ops,
6131 		},
6132 	},
6133 };
6134 
6135 static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = {
6136 	.halt_reg = 0xab064,
6137 	.halt_check = BRANCH_HALT_DELAY,
6138 	.clkr = {
6139 		.enable_reg = 0xab064,
6140 		.enable_mask = BIT(0),
6141 		.hw.init = &(const struct clk_init_data) {
6142 			.name = "gcc_usb3_mp_phy_pipe_1_clk",
6143 			.parent_hws = (const struct clk_hw*[]){
6144 				&gcc_usb3_mp_phy_pipe_1_clk_src.clkr.hw,
6145 			},
6146 			.num_parents = 1,
6147 			.flags = CLK_SET_RATE_PARENT,
6148 			.ops = &clk_branch2_ops,
6149 		},
6150 	},
6151 };
6152 
6153 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
6154 	.halt_reg = 0xf054,
6155 	.halt_check = BRANCH_HALT,
6156 	.clkr = {
6157 		.enable_reg = 0xf054,
6158 		.enable_mask = BIT(0),
6159 		.hw.init = &(const struct clk_init_data) {
6160 			.name = "gcc_usb3_prim_phy_aux_clk",
6161 			.parent_hws = (const struct clk_hw*[]){
6162 				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
6163 			},
6164 			.num_parents = 1,
6165 			.flags = CLK_SET_RATE_PARENT,
6166 			.ops = &clk_branch2_ops,
6167 		},
6168 	},
6169 };
6170 
6171 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
6172 	.halt_reg = 0xf058,
6173 	.halt_check = BRANCH_HALT,
6174 	.clkr = {
6175 		.enable_reg = 0xf058,
6176 		.enable_mask = BIT(0),
6177 		.hw.init = &(const struct clk_init_data) {
6178 			.name = "gcc_usb3_prim_phy_com_aux_clk",
6179 			.parent_hws = (const struct clk_hw*[]){
6180 				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
6181 			},
6182 			.num_parents = 1,
6183 			.flags = CLK_SET_RATE_PARENT,
6184 			.ops = &clk_branch2_ops,
6185 		},
6186 	},
6187 };
6188 
6189 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
6190 	.halt_reg = 0xf05c,
6191 	.halt_check = BRANCH_HALT_DELAY,
6192 	.hwcg_reg = 0xf05c,
6193 	.hwcg_bit = 1,
6194 	.clkr = {
6195 		.enable_reg = 0xf05c,
6196 		.enable_mask = BIT(0),
6197 		.hw.init = &(const struct clk_init_data) {
6198 			.name = "gcc_usb3_prim_phy_pipe_clk",
6199 			.parent_hws = (const struct clk_hw*[]){
6200 				&gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,
6201 			},
6202 			.num_parents = 1,
6203 			.flags = CLK_SET_RATE_PARENT,
6204 			.ops = &clk_branch2_ops,
6205 		},
6206 	},
6207 };
6208 
6209 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
6210 	.halt_reg = 0x10054,
6211 	.halt_check = BRANCH_HALT,
6212 	.clkr = {
6213 		.enable_reg = 0x10054,
6214 		.enable_mask = BIT(0),
6215 		.hw.init = &(const struct clk_init_data) {
6216 			.name = "gcc_usb3_sec_phy_aux_clk",
6217 			.parent_hws = (const struct clk_hw*[]){
6218 				&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
6219 			},
6220 			.num_parents = 1,
6221 			.flags = CLK_SET_RATE_PARENT,
6222 			.ops = &clk_branch2_ops,
6223 		},
6224 	},
6225 };
6226 
6227 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
6228 	.halt_reg = 0x10058,
6229 	.halt_check = BRANCH_HALT,
6230 	.clkr = {
6231 		.enable_reg = 0x10058,
6232 		.enable_mask = BIT(0),
6233 		.hw.init = &(const struct clk_init_data) {
6234 			.name = "gcc_usb3_sec_phy_com_aux_clk",
6235 			.parent_hws = (const struct clk_hw*[]){
6236 				&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
6237 			},
6238 			.num_parents = 1,
6239 			.flags = CLK_SET_RATE_PARENT,
6240 			.ops = &clk_branch2_ops,
6241 		},
6242 	},
6243 };
6244 
6245 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
6246 	.halt_reg = 0x1005c,
6247 	.halt_check = BRANCH_HALT_DELAY,
6248 	.hwcg_reg = 0x1005c,
6249 	.hwcg_bit = 1,
6250 	.clkr = {
6251 		.enable_reg = 0x1005c,
6252 		.enable_mask = BIT(0),
6253 		.hw.init = &(const struct clk_init_data) {
6254 			.name = "gcc_usb3_sec_phy_pipe_clk",
6255 			.parent_hws = (const struct clk_hw*[]){
6256 				&gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,
6257 			},
6258 			.num_parents = 1,
6259 			.flags = CLK_SET_RATE_PARENT,
6260 			.ops = &clk_branch2_ops,
6261 		},
6262 	},
6263 };
6264 
6265 static struct clk_branch gcc_usb4_1_cfg_ahb_clk = {
6266 	.halt_reg = 0xb808c,
6267 	.halt_check = BRANCH_HALT_VOTED,
6268 	.hwcg_reg = 0xb808c,
6269 	.hwcg_bit = 1,
6270 	.clkr = {
6271 		.enable_reg = 0xb808c,
6272 		.enable_mask = BIT(0),
6273 		.hw.init = &(const struct clk_init_data) {
6274 			.name = "gcc_usb4_1_cfg_ahb_clk",
6275 			.ops = &clk_branch2_ops,
6276 		},
6277 	},
6278 };
6279 
6280 static struct clk_branch gcc_usb4_1_dp_clk = {
6281 	.halt_reg = 0xb8048,
6282 	.halt_check = BRANCH_HALT,
6283 	.clkr = {
6284 		.enable_reg = 0xb8048,
6285 		.enable_mask = BIT(0),
6286 		.hw.init = &(const struct clk_init_data) {
6287 			.name = "gcc_usb4_1_dp_clk",
6288 			.parent_hws = (const struct clk_hw*[]){
6289 				&gcc_usb4_1_phy_dp_clk_src.clkr.hw,
6290 			},
6291 			.num_parents = 1,
6292 			.flags = CLK_SET_RATE_PARENT,
6293 			.ops = &clk_branch2_ops,
6294 		},
6295 	},
6296 };
6297 
6298 static struct clk_branch gcc_usb4_1_master_clk = {
6299 	.halt_reg = 0xb8010,
6300 	.halt_check = BRANCH_HALT,
6301 	.clkr = {
6302 		.enable_reg = 0xb8010,
6303 		.enable_mask = BIT(0),
6304 		.hw.init = &(const struct clk_init_data) {
6305 			.name = "gcc_usb4_1_master_clk",
6306 			.parent_hws = (const struct clk_hw*[]){
6307 				&gcc_usb4_1_master_clk_src.clkr.hw,
6308 			},
6309 			.num_parents = 1,
6310 			.flags = CLK_SET_RATE_PARENT,
6311 			.ops = &clk_branch2_ops,
6312 		},
6313 	},
6314 };
6315 
6316 static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = {
6317 	.halt_reg = 0xb80b4,
6318 	.halt_check = BRANCH_HALT_DELAY,
6319 	.clkr = {
6320 		.enable_reg = 0xb80b4,
6321 		.enable_mask = BIT(0),
6322 		.hw.init = &(const struct clk_init_data) {
6323 			.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk",
6324 			.parent_hws = (const struct clk_hw*[]){
6325 				&gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr.hw,
6326 			},
6327 			.num_parents = 1,
6328 			.flags = CLK_SET_RATE_PARENT,
6329 			.ops = &clk_branch2_ops,
6330 		},
6331 	},
6332 };
6333 
6334 static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = {
6335 	.halt_reg = 0xb8038,
6336 	.halt_check = BRANCH_HALT_DELAY,
6337 	.clkr = {
6338 		.enable_reg = 0x52020,
6339 		.enable_mask = BIT(19),
6340 		.hw.init = &(const struct clk_init_data) {
6341 			.name = "gcc_usb4_1_phy_pcie_pipe_clk",
6342 			.parent_hws = (const struct clk_hw*[]){
6343 				&gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,
6344 			},
6345 			.num_parents = 1,
6346 			.flags = CLK_SET_RATE_PARENT,
6347 			.ops = &clk_branch2_ops,
6348 		},
6349 	},
6350 };
6351 
6352 static struct clk_branch gcc_usb4_1_phy_rx0_clk = {
6353 	.halt_reg = 0xb8094,
6354 	.halt_check = BRANCH_HALT,
6355 	.clkr = {
6356 		.enable_reg = 0xb8094,
6357 		.enable_mask = BIT(0),
6358 		.hw.init = &(const struct clk_init_data) {
6359 			.name = "gcc_usb4_1_phy_rx0_clk",
6360 			.parent_hws = (const struct clk_hw*[]){
6361 				&gcc_usb4_1_phy_rx0_clk_src.clkr.hw,
6362 			},
6363 			.num_parents = 1,
6364 			.flags = CLK_SET_RATE_PARENT,
6365 			.ops = &clk_branch2_ops,
6366 		},
6367 	},
6368 };
6369 
6370 static struct clk_branch gcc_usb4_1_phy_rx1_clk = {
6371 	.halt_reg = 0xb80a0,
6372 	.halt_check = BRANCH_HALT,
6373 	.clkr = {
6374 		.enable_reg = 0xb80a0,
6375 		.enable_mask = BIT(0),
6376 		.hw.init = &(const struct clk_init_data) {
6377 			.name = "gcc_usb4_1_phy_rx1_clk",
6378 			.parent_hws = (const struct clk_hw*[]){
6379 				&gcc_usb4_1_phy_rx1_clk_src.clkr.hw,
6380 			},
6381 			.num_parents = 1,
6382 			.flags = CLK_SET_RATE_PARENT,
6383 			.ops = &clk_branch2_ops,
6384 		},
6385 	},
6386 };
6387 
6388 static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = {
6389 	.halt_reg = 0xb8088,
6390 	.halt_check = BRANCH_HALT_DELAY,
6391 	.hwcg_reg = 0xb8088,
6392 	.hwcg_bit = 1,
6393 	.clkr = {
6394 		.enable_reg = 0xb8088,
6395 		.enable_mask = BIT(0),
6396 		.hw.init = &(const struct clk_init_data) {
6397 			.name = "gcc_usb4_1_phy_usb_pipe_clk",
6398 			.parent_hws = (const struct clk_hw*[]){
6399 				&gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,
6400 			},
6401 			.num_parents = 1,
6402 			.flags = CLK_SET_RATE_PARENT,
6403 			.ops = &clk_branch2_ops,
6404 		},
6405 	},
6406 };
6407 
6408 static struct clk_branch gcc_usb4_1_sb_if_clk = {
6409 	.halt_reg = 0xb8034,
6410 	.halt_check = BRANCH_HALT,
6411 	.clkr = {
6412 		.enable_reg = 0xb8034,
6413 		.enable_mask = BIT(0),
6414 		.hw.init = &(const struct clk_init_data) {
6415 			.name = "gcc_usb4_1_sb_if_clk",
6416 			.parent_hws = (const struct clk_hw*[]){
6417 				&gcc_usb4_1_sb_if_clk_src.clkr.hw,
6418 			},
6419 			.num_parents = 1,
6420 			.flags = CLK_SET_RATE_PARENT,
6421 			.ops = &clk_branch2_ops,
6422 		},
6423 	},
6424 };
6425 
6426 static struct clk_branch gcc_usb4_1_sys_clk = {
6427 	.halt_reg = 0xb8040,
6428 	.halt_check = BRANCH_HALT,
6429 	.clkr = {
6430 		.enable_reg = 0xb8040,
6431 		.enable_mask = BIT(0),
6432 		.hw.init = &(const struct clk_init_data) {
6433 			.name = "gcc_usb4_1_sys_clk",
6434 			.parent_hws = (const struct clk_hw*[]){
6435 				&gcc_usb4_1_phy_sys_clk_src.clkr.hw,
6436 			},
6437 			.num_parents = 1,
6438 			.flags = CLK_SET_RATE_PARENT,
6439 			.ops = &clk_branch2_ops,
6440 		},
6441 	},
6442 };
6443 
6444 static struct clk_branch gcc_usb4_1_tmu_clk = {
6445 	.halt_reg = 0xb806c,
6446 	.halt_check = BRANCH_HALT_VOTED,
6447 	.hwcg_reg = 0xb806c,
6448 	.hwcg_bit = 1,
6449 	.clkr = {
6450 		.enable_reg = 0xb806c,
6451 		.enable_mask = BIT(0),
6452 		.hw.init = &(const struct clk_init_data) {
6453 			.name = "gcc_usb4_1_tmu_clk",
6454 			.parent_hws = (const struct clk_hw*[]){
6455 				&gcc_usb4_1_tmu_clk_src.clkr.hw,
6456 			},
6457 			.num_parents = 1,
6458 			.flags = CLK_SET_RATE_PARENT,
6459 			.ops = &clk_branch2_ops,
6460 		},
6461 	},
6462 };
6463 
6464 static struct clk_branch gcc_usb4_cfg_ahb_clk = {
6465 	.halt_reg = 0x2a08c,
6466 	.halt_check = BRANCH_HALT_VOTED,
6467 	.hwcg_reg = 0x2a08c,
6468 	.hwcg_bit = 1,
6469 	.clkr = {
6470 		.enable_reg = 0x2a08c,
6471 		.enable_mask = BIT(0),
6472 		.hw.init = &(const struct clk_init_data) {
6473 			.name = "gcc_usb4_cfg_ahb_clk",
6474 			.ops = &clk_branch2_ops,
6475 		},
6476 	},
6477 };
6478 
6479 static struct clk_branch gcc_usb4_clkref_clk = {
6480 	.halt_reg = 0x8c010,
6481 	.halt_check = BRANCH_HALT,
6482 	.clkr = {
6483 		.enable_reg = 0x8c010,
6484 		.enable_mask = BIT(0),
6485 		.hw.init = &(const struct clk_init_data) {
6486 			.name = "gcc_usb4_clkref_clk",
6487 			.ops = &clk_branch2_ops,
6488 		},
6489 	},
6490 };
6491 
6492 static struct clk_branch gcc_usb4_dp_clk = {
6493 	.halt_reg = 0x2a048,
6494 	.halt_check = BRANCH_HALT,
6495 	.clkr = {
6496 		.enable_reg = 0x2a048,
6497 		.enable_mask = BIT(0),
6498 		.hw.init = &(const struct clk_init_data) {
6499 			.name = "gcc_usb4_dp_clk",
6500 			.parent_hws = (const struct clk_hw*[]){
6501 				&gcc_usb4_phy_dp_clk_src.clkr.hw,
6502 			},
6503 			.num_parents = 1,
6504 			.flags = CLK_SET_RATE_PARENT,
6505 			.ops = &clk_branch2_ops,
6506 		},
6507 	},
6508 };
6509 
6510 static struct clk_branch gcc_usb4_eud_clkref_clk = {
6511 	.halt_reg = 0x8c02c,
6512 	.halt_check = BRANCH_HALT,
6513 	.clkr = {
6514 		.enable_reg = 0x8c02c,
6515 		.enable_mask = BIT(0),
6516 		.hw.init = &(const struct clk_init_data) {
6517 			.name = "gcc_usb4_eud_clkref_clk",
6518 			.ops = &clk_branch2_ops,
6519 		},
6520 	},
6521 };
6522 
6523 static struct clk_branch gcc_usb4_master_clk = {
6524 	.halt_reg = 0x2a010,
6525 	.halt_check = BRANCH_HALT,
6526 	.clkr = {
6527 		.enable_reg = 0x2a010,
6528 		.enable_mask = BIT(0),
6529 		.hw.init = &(const struct clk_init_data) {
6530 			.name = "gcc_usb4_master_clk",
6531 			.parent_hws = (const struct clk_hw*[]){
6532 				&gcc_usb4_master_clk_src.clkr.hw,
6533 			},
6534 			.num_parents = 1,
6535 			.flags = CLK_SET_RATE_PARENT,
6536 			.ops = &clk_branch2_ops,
6537 		},
6538 	},
6539 };
6540 
6541 static struct clk_branch gcc_usb4_phy_p2rr2p_pipe_clk = {
6542 	.halt_reg = 0x2a0b4,
6543 	.halt_check = BRANCH_HALT_DELAY,
6544 	.clkr = {
6545 		.enable_reg = 0x2a0b4,
6546 		.enable_mask = BIT(0),
6547 		.hw.init = &(const struct clk_init_data) {
6548 			.name = "gcc_usb4_phy_p2rr2p_pipe_clk",
6549 			.parent_hws = (const struct clk_hw*[]){
6550 				&gcc_usb4_phy_p2rr2p_pipe_clk_src.clkr.hw,
6551 			},
6552 			.num_parents = 1,
6553 			.flags = CLK_SET_RATE_PARENT,
6554 			.ops = &clk_branch2_ops,
6555 		},
6556 	},
6557 };
6558 
6559 static struct clk_branch gcc_usb4_phy_pcie_pipe_clk = {
6560 	.halt_reg = 0x2a038,
6561 	.halt_check = BRANCH_HALT_DELAY,
6562 	.clkr = {
6563 		.enable_reg = 0x52020,
6564 		.enable_mask = BIT(18),
6565 		.hw.init = &(const struct clk_init_data) {
6566 			.name = "gcc_usb4_phy_pcie_pipe_clk",
6567 			.parent_hws = (const struct clk_hw*[]){
6568 				&gcc_usb4_phy_pcie_pipe_mux_clk_src.clkr.hw,
6569 			},
6570 			.num_parents = 1,
6571 			.flags = CLK_SET_RATE_PARENT,
6572 			.ops = &clk_branch2_ops,
6573 		},
6574 	},
6575 };
6576 
6577 static struct clk_branch gcc_usb4_phy_rx0_clk = {
6578 	.halt_reg = 0x2a094,
6579 	.halt_check = BRANCH_HALT,
6580 	.clkr = {
6581 		.enable_reg = 0x2a094,
6582 		.enable_mask = BIT(0),
6583 		.hw.init = &(const struct clk_init_data) {
6584 			.name = "gcc_usb4_phy_rx0_clk",
6585 			.parent_hws = (const struct clk_hw*[]){
6586 				&gcc_usb4_phy_rx0_clk_src.clkr.hw,
6587 			},
6588 			.num_parents = 1,
6589 			.flags = CLK_SET_RATE_PARENT,
6590 			.ops = &clk_branch2_ops,
6591 		},
6592 	},
6593 };
6594 
6595 static struct clk_branch gcc_usb4_phy_rx1_clk = {
6596 	.halt_reg = 0x2a0a0,
6597 	.halt_check = BRANCH_HALT,
6598 	.clkr = {
6599 		.enable_reg = 0x2a0a0,
6600 		.enable_mask = BIT(0),
6601 		.hw.init = &(const struct clk_init_data) {
6602 			.name = "gcc_usb4_phy_rx1_clk",
6603 			.parent_hws = (const struct clk_hw*[]){
6604 				&gcc_usb4_phy_rx1_clk_src.clkr.hw,
6605 			},
6606 			.num_parents = 1,
6607 			.flags = CLK_SET_RATE_PARENT,
6608 			.ops = &clk_branch2_ops,
6609 		},
6610 	},
6611 };
6612 
6613 static struct clk_branch gcc_usb4_phy_usb_pipe_clk = {
6614 	.halt_reg = 0x2a088,
6615 	.halt_check = BRANCH_HALT_DELAY,
6616 	.hwcg_reg = 0x2a088,
6617 	.hwcg_bit = 1,
6618 	.clkr = {
6619 		.enable_reg = 0x2a088,
6620 		.enable_mask = BIT(0),
6621 		.hw.init = &(const struct clk_init_data) {
6622 			.name = "gcc_usb4_phy_usb_pipe_clk",
6623 			.parent_hws = (const struct clk_hw*[]){
6624 				&gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,
6625 			},
6626 			.num_parents = 1,
6627 			.flags = CLK_SET_RATE_PARENT,
6628 			.ops = &clk_branch2_ops,
6629 		},
6630 	},
6631 };
6632 
6633 static struct clk_branch gcc_usb4_sb_if_clk = {
6634 	.halt_reg = 0x2a034,
6635 	.halt_check = BRANCH_HALT,
6636 	.clkr = {
6637 		.enable_reg = 0x2a034,
6638 		.enable_mask = BIT(0),
6639 		.hw.init = &(const struct clk_init_data) {
6640 			.name = "gcc_usb4_sb_if_clk",
6641 			.parent_hws = (const struct clk_hw*[]){
6642 				&gcc_usb4_sb_if_clk_src.clkr.hw,
6643 			},
6644 			.num_parents = 1,
6645 			.flags = CLK_SET_RATE_PARENT,
6646 			.ops = &clk_branch2_ops,
6647 		},
6648 	},
6649 };
6650 
6651 static struct clk_branch gcc_usb4_sys_clk = {
6652 	.halt_reg = 0x2a040,
6653 	.halt_check = BRANCH_HALT,
6654 	.clkr = {
6655 		.enable_reg = 0x2a040,
6656 		.enable_mask = BIT(0),
6657 		.hw.init = &(const struct clk_init_data) {
6658 			.name = "gcc_usb4_sys_clk",
6659 			.parent_hws = (const struct clk_hw*[]){
6660 				&gcc_usb4_phy_sys_clk_src.clkr.hw,
6661 			},
6662 			.num_parents = 1,
6663 			.flags = CLK_SET_RATE_PARENT,
6664 			.ops = &clk_branch2_ops,
6665 		},
6666 	},
6667 };
6668 
6669 static struct clk_branch gcc_usb4_tmu_clk = {
6670 	.halt_reg = 0x2a06c,
6671 	.halt_check = BRANCH_HALT_VOTED,
6672 	.hwcg_reg = 0x2a06c,
6673 	.hwcg_bit = 1,
6674 	.clkr = {
6675 		.enable_reg = 0x2a06c,
6676 		.enable_mask = BIT(0),
6677 		.hw.init = &(const struct clk_init_data) {
6678 			.name = "gcc_usb4_tmu_clk",
6679 			.parent_hws = (const struct clk_hw*[]){
6680 				&gcc_usb4_tmu_clk_src.clkr.hw,
6681 			},
6682 			.num_parents = 1,
6683 			.flags = CLK_SET_RATE_PARENT,
6684 			.ops = &clk_branch2_ops,
6685 		},
6686 	},
6687 };
6688 
6689 static struct clk_branch gcc_video_axi0_clk = {
6690 	.halt_reg = 0x28010,
6691 	.halt_check = BRANCH_HALT_SKIP,
6692 	.hwcg_reg = 0x28010,
6693 	.hwcg_bit = 1,
6694 	.clkr = {
6695 		.enable_reg = 0x28010,
6696 		.enable_mask = BIT(0),
6697 		.hw.init = &(const struct clk_init_data) {
6698 			.name = "gcc_video_axi0_clk",
6699 			.ops = &clk_branch2_ops,
6700 		},
6701 	},
6702 };
6703 
6704 static struct clk_branch gcc_video_axi1_clk = {
6705 	.halt_reg = 0x28018,
6706 	.halt_check = BRANCH_HALT_SKIP,
6707 	.hwcg_reg = 0x28018,
6708 	.hwcg_bit = 1,
6709 	.clkr = {
6710 		.enable_reg = 0x28018,
6711 		.enable_mask = BIT(0),
6712 		.hw.init = &(const struct clk_init_data) {
6713 			.name = "gcc_video_axi1_clk",
6714 			.ops = &clk_branch2_ops,
6715 		},
6716 	},
6717 };
6718 
6719 static struct clk_branch gcc_video_cvp_throttle_clk = {
6720 	.halt_reg = 0x28024,
6721 	.halt_check = BRANCH_HALT_SKIP,
6722 	.hwcg_reg = 0x28024,
6723 	.hwcg_bit = 1,
6724 	.clkr = {
6725 		.enable_reg = 0x28024,
6726 		.enable_mask = BIT(0),
6727 		.hw.init = &(const struct clk_init_data) {
6728 			.name = "gcc_video_cvp_throttle_clk",
6729 			.ops = &clk_branch2_ops,
6730 		},
6731 	},
6732 };
6733 
6734 static struct clk_branch gcc_video_vcodec_throttle_clk = {
6735 	.halt_reg = 0x28020,
6736 	.halt_check = BRANCH_HALT_SKIP,
6737 	.hwcg_reg = 0x28020,
6738 	.hwcg_bit = 1,
6739 	.clkr = {
6740 		.enable_reg = 0x28020,
6741 		.enable_mask = BIT(0),
6742 		.hw.init = &(const struct clk_init_data) {
6743 			.name = "gcc_video_vcodec_throttle_clk",
6744 			.ops = &clk_branch2_ops,
6745 		},
6746 	},
6747 };
6748 
6749 static struct gdsc pcie_0_tunnel_gdsc = {
6750 	.gdscr = 0xa4004,
6751 	.collapse_ctrl = 0x52128,
6752 	.collapse_mask = BIT(0),
6753 	.pd = {
6754 		.name = "pcie_0_tunnel_gdsc",
6755 	},
6756 	.pwrsts = PWRSTS_OFF_ON,
6757 	.flags = VOTABLE,
6758 };
6759 
6760 static struct gdsc pcie_1_tunnel_gdsc = {
6761 	.gdscr = 0x8d004,
6762 	.collapse_ctrl = 0x52128,
6763 	.collapse_mask = BIT(1),
6764 	.pd = {
6765 		.name = "pcie_1_tunnel_gdsc",
6766 	},
6767 	.pwrsts = PWRSTS_OFF_ON,
6768 	.flags = VOTABLE,
6769 };
6770 
6771 /*
6772  * The Qualcomm PCIe driver does not yet implement suspend so to keep the
6773  * PCIe power domains always-on for now.
6774  */
6775 static struct gdsc pcie_2a_gdsc = {
6776 	.gdscr = 0x9d004,
6777 	.collapse_ctrl = 0x52128,
6778 	.collapse_mask = BIT(2),
6779 	.pd = {
6780 		.name = "pcie_2a_gdsc",
6781 	},
6782 	.pwrsts = PWRSTS_OFF_ON,
6783 	.flags = VOTABLE | ALWAYS_ON,
6784 };
6785 
6786 static struct gdsc pcie_2b_gdsc = {
6787 	.gdscr = 0x9e004,
6788 	.collapse_ctrl = 0x52128,
6789 	.collapse_mask = BIT(3),
6790 	.pd = {
6791 		.name = "pcie_2b_gdsc",
6792 	},
6793 	.pwrsts = PWRSTS_OFF_ON,
6794 	.flags = VOTABLE | ALWAYS_ON,
6795 };
6796 
6797 static struct gdsc pcie_3a_gdsc = {
6798 	.gdscr = 0xa0004,
6799 	.collapse_ctrl = 0x52128,
6800 	.collapse_mask = BIT(4),
6801 	.pd = {
6802 		.name = "pcie_3a_gdsc",
6803 	},
6804 	.pwrsts = PWRSTS_OFF_ON,
6805 	.flags = VOTABLE | ALWAYS_ON,
6806 };
6807 
6808 static struct gdsc pcie_3b_gdsc = {
6809 	.gdscr = 0xa2004,
6810 	.collapse_ctrl = 0x52128,
6811 	.collapse_mask = BIT(5),
6812 	.pd = {
6813 		.name = "pcie_3b_gdsc",
6814 	},
6815 	.pwrsts = PWRSTS_OFF_ON,
6816 	.flags = VOTABLE | ALWAYS_ON,
6817 };
6818 
6819 static struct gdsc pcie_4_gdsc = {
6820 	.gdscr = 0x6b004,
6821 	.collapse_ctrl = 0x52128,
6822 	.collapse_mask = BIT(6),
6823 	.pd = {
6824 		.name = "pcie_4_gdsc",
6825 	},
6826 	.pwrsts = PWRSTS_OFF_ON,
6827 	.flags = VOTABLE | ALWAYS_ON,
6828 };
6829 
6830 static struct gdsc ufs_card_gdsc = {
6831 	.gdscr = 0x75004,
6832 	.pd = {
6833 		.name = "ufs_card_gdsc",
6834 	},
6835 	.pwrsts = PWRSTS_OFF_ON,
6836 };
6837 
6838 static struct gdsc ufs_phy_gdsc = {
6839 	.gdscr = 0x77004,
6840 	.pd = {
6841 		.name = "ufs_phy_gdsc",
6842 	},
6843 	.pwrsts = PWRSTS_OFF_ON,
6844 };
6845 
6846 static struct gdsc usb30_mp_gdsc = {
6847 	.gdscr = 0xab004,
6848 	.pd = {
6849 		.name = "usb30_mp_gdsc",
6850 	},
6851 	.pwrsts = PWRSTS_RET_ON,
6852 };
6853 
6854 static struct gdsc usb30_prim_gdsc = {
6855 	.gdscr = 0xf004,
6856 	.pd = {
6857 		.name = "usb30_prim_gdsc",
6858 	},
6859 	.pwrsts = PWRSTS_RET_ON,
6860 };
6861 
6862 static struct gdsc usb30_sec_gdsc = {
6863 	.gdscr = 0x10004,
6864 	.pd = {
6865 		.name = "usb30_sec_gdsc",
6866 	},
6867 	.pwrsts = PWRSTS_RET_ON,
6868 };
6869 
6870 static struct clk_regmap *gcc_sc8280xp_clocks[] = {
6871 	[GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK] = &gcc_aggre_noc_pcie0_tunnel_axi_clk.clkr,
6872 	[GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK] = &gcc_aggre_noc_pcie1_tunnel_axi_clk.clkr,
6873 	[GCC_AGGRE_NOC_PCIE_4_AXI_CLK] = &gcc_aggre_noc_pcie_4_axi_clk.clkr,
6874 	[GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK] = &gcc_aggre_noc_pcie_south_sf_axi_clk.clkr,
6875 	[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
6876 	[GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
6877 	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
6878 	[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
6879 	[GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr,
6880 	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
6881 	[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
6882 	[GCC_AGGRE_USB4_1_AXI_CLK] = &gcc_aggre_usb4_1_axi_clk.clkr,
6883 	[GCC_AGGRE_USB4_AXI_CLK] = &gcc_aggre_usb4_axi_clk.clkr,
6884 	[GCC_AGGRE_USB_NOC_AXI_CLK] = &gcc_aggre_usb_noc_axi_clk.clkr,
6885 	[GCC_AGGRE_USB_NOC_NORTH_AXI_CLK] = &gcc_aggre_usb_noc_north_axi_clk.clkr,
6886 	[GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK] = &gcc_aggre_usb_noc_south_axi_clk.clkr,
6887 	[GCC_AHB2PHY0_CLK] = &gcc_ahb2phy0_clk.clkr,
6888 	[GCC_AHB2PHY2_CLK] = &gcc_ahb2phy2_clk.clkr,
6889 	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
6890 	[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
6891 	[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
6892 	[GCC_CAMERA_THROTTLE_NRT_AXI_CLK] = &gcc_camera_throttle_nrt_axi_clk.clkr,
6893 	[GCC_CAMERA_THROTTLE_RT_AXI_CLK] = &gcc_camera_throttle_rt_axi_clk.clkr,
6894 	[GCC_CAMERA_THROTTLE_XO_CLK] = &gcc_camera_throttle_xo_clk.clkr,
6895 	[GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr,
6896 	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
6897 	[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
6898 	[GCC_CNOC_PCIE0_TUNNEL_CLK] = &gcc_cnoc_pcie0_tunnel_clk.clkr,
6899 	[GCC_CNOC_PCIE1_TUNNEL_CLK] = &gcc_cnoc_pcie1_tunnel_clk.clkr,
6900 	[GCC_CNOC_PCIE4_QX_CLK] = &gcc_cnoc_pcie4_qx_clk.clkr,
6901 	[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
6902 	[GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,
6903 	[GCC_DISP1_HF_AXI_CLK] = &gcc_disp1_hf_axi_clk.clkr,
6904 	[GCC_DISP1_SF_AXI_CLK] = &gcc_disp1_sf_axi_clk.clkr,
6905 	[GCC_DISP1_THROTTLE_NRT_AXI_CLK] = &gcc_disp1_throttle_nrt_axi_clk.clkr,
6906 	[GCC_DISP1_THROTTLE_RT_AXI_CLK] = &gcc_disp1_throttle_rt_axi_clk.clkr,
6907 	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
6908 	[GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
6909 	[GCC_DISP_THROTTLE_NRT_AXI_CLK] = &gcc_disp_throttle_nrt_axi_clk.clkr,
6910 	[GCC_DISP_THROTTLE_RT_AXI_CLK] = &gcc_disp_throttle_rt_axi_clk.clkr,
6911 	[GCC_EMAC0_AXI_CLK] = &gcc_emac0_axi_clk.clkr,
6912 	[GCC_EMAC0_PTP_CLK] = &gcc_emac0_ptp_clk.clkr,
6913 	[GCC_EMAC0_PTP_CLK_SRC] = &gcc_emac0_ptp_clk_src.clkr,
6914 	[GCC_EMAC0_RGMII_CLK] = &gcc_emac0_rgmii_clk.clkr,
6915 	[GCC_EMAC0_RGMII_CLK_SRC] = &gcc_emac0_rgmii_clk_src.clkr,
6916 	[GCC_EMAC0_SLV_AHB_CLK] = &gcc_emac0_slv_ahb_clk.clkr,
6917 	[GCC_EMAC1_AXI_CLK] = &gcc_emac1_axi_clk.clkr,
6918 	[GCC_EMAC1_PTP_CLK] = &gcc_emac1_ptp_clk.clkr,
6919 	[GCC_EMAC1_PTP_CLK_SRC] = &gcc_emac1_ptp_clk_src.clkr,
6920 	[GCC_EMAC1_RGMII_CLK] = &gcc_emac1_rgmii_clk.clkr,
6921 	[GCC_EMAC1_RGMII_CLK_SRC] = &gcc_emac1_rgmii_clk_src.clkr,
6922 	[GCC_EMAC1_SLV_AHB_CLK] = &gcc_emac1_slv_ahb_clk.clkr,
6923 	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
6924 	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
6925 	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
6926 	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
6927 	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
6928 	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
6929 	[GCC_GP4_CLK] = &gcc_gp4_clk.clkr,
6930 	[GCC_GP4_CLK_SRC] = &gcc_gp4_clk_src.clkr,
6931 	[GCC_GP5_CLK] = &gcc_gp5_clk.clkr,
6932 	[GCC_GP5_CLK_SRC] = &gcc_gp5_clk_src.clkr,
6933 	[GCC_GPLL0] = &gcc_gpll0.clkr,
6934 	[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
6935 	[GCC_GPLL2] = &gcc_gpll2.clkr,
6936 	[GCC_GPLL4] = &gcc_gpll4.clkr,
6937 	[GCC_GPLL7] = &gcc_gpll7.clkr,
6938 	[GCC_GPLL8] = &gcc_gpll8.clkr,
6939 	[GCC_GPLL9] = &gcc_gpll9.clkr,
6940 	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
6941 	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
6942 	[GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr,
6943 	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
6944 	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
6945 	[GCC_GPU_TCU_THROTTLE_AHB_CLK] = &gcc_gpu_tcu_throttle_ahb_clk.clkr,
6946 	[GCC_GPU_TCU_THROTTLE_CLK] = &gcc_gpu_tcu_throttle_clk.clkr,
6947 	[GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr,
6948 	[GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr,
6949 	[GCC_PCIE2A_PHY_RCHNG_CLK] = &gcc_pcie2a_phy_rchng_clk.clkr,
6950 	[GCC_PCIE2B_PHY_RCHNG_CLK] = &gcc_pcie2b_phy_rchng_clk.clkr,
6951 	[GCC_PCIE3A_PHY_RCHNG_CLK] = &gcc_pcie3a_phy_rchng_clk.clkr,
6952 	[GCC_PCIE3B_PHY_RCHNG_CLK] = &gcc_pcie3b_phy_rchng_clk.clkr,
6953 	[GCC_PCIE4_PHY_RCHNG_CLK] = &gcc_pcie4_phy_rchng_clk.clkr,
6954 	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
6955 	[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
6956 	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
6957 	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
6958 	[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
6959 	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
6960 	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
6961 	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
6962 	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
6963 	[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
6964 	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
6965 	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
6966 	[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
6967 	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
6968 	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
6969 	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
6970 	[GCC_PCIE_2A2B_CLKREF_CLK] = &gcc_pcie_2a2b_clkref_clk.clkr,
6971 	[GCC_PCIE_2A_AUX_CLK] = &gcc_pcie_2a_aux_clk.clkr,
6972 	[GCC_PCIE_2A_AUX_CLK_SRC] = &gcc_pcie_2a_aux_clk_src.clkr,
6973 	[GCC_PCIE_2A_CFG_AHB_CLK] = &gcc_pcie_2a_cfg_ahb_clk.clkr,
6974 	[GCC_PCIE_2A_MSTR_AXI_CLK] = &gcc_pcie_2a_mstr_axi_clk.clkr,
6975 	[GCC_PCIE_2A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2a_phy_rchng_clk_src.clkr,
6976 	[GCC_PCIE_2A_PIPE_CLK] = &gcc_pcie_2a_pipe_clk.clkr,
6977 	[GCC_PCIE_2A_PIPE_CLK_SRC] = &gcc_pcie_2a_pipe_clk_src.clkr,
6978 	[GCC_PCIE_2A_PIPE_DIV_CLK_SRC] = &gcc_pcie_2a_pipe_div_clk_src.clkr,
6979 	[GCC_PCIE_2A_PIPEDIV2_CLK] = &gcc_pcie_2a_pipediv2_clk.clkr,
6980 	[GCC_PCIE_2A_SLV_AXI_CLK] = &gcc_pcie_2a_slv_axi_clk.clkr,
6981 	[GCC_PCIE_2A_SLV_Q2A_AXI_CLK] = &gcc_pcie_2a_slv_q2a_axi_clk.clkr,
6982 	[GCC_PCIE_2B_AUX_CLK] = &gcc_pcie_2b_aux_clk.clkr,
6983 	[GCC_PCIE_2B_AUX_CLK_SRC] = &gcc_pcie_2b_aux_clk_src.clkr,
6984 	[GCC_PCIE_2B_CFG_AHB_CLK] = &gcc_pcie_2b_cfg_ahb_clk.clkr,
6985 	[GCC_PCIE_2B_MSTR_AXI_CLK] = &gcc_pcie_2b_mstr_axi_clk.clkr,
6986 	[GCC_PCIE_2B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2b_phy_rchng_clk_src.clkr,
6987 	[GCC_PCIE_2B_PIPE_CLK] = &gcc_pcie_2b_pipe_clk.clkr,
6988 	[GCC_PCIE_2B_PIPE_CLK_SRC] = &gcc_pcie_2b_pipe_clk_src.clkr,
6989 	[GCC_PCIE_2B_PIPE_DIV_CLK_SRC] = &gcc_pcie_2b_pipe_div_clk_src.clkr,
6990 	[GCC_PCIE_2B_PIPEDIV2_CLK] = &gcc_pcie_2b_pipediv2_clk.clkr,
6991 	[GCC_PCIE_2B_SLV_AXI_CLK] = &gcc_pcie_2b_slv_axi_clk.clkr,
6992 	[GCC_PCIE_2B_SLV_Q2A_AXI_CLK] = &gcc_pcie_2b_slv_q2a_axi_clk.clkr,
6993 	[GCC_PCIE_3A3B_CLKREF_CLK] = &gcc_pcie_3a3b_clkref_clk.clkr,
6994 	[GCC_PCIE_3A_AUX_CLK] = &gcc_pcie_3a_aux_clk.clkr,
6995 	[GCC_PCIE_3A_AUX_CLK_SRC] = &gcc_pcie_3a_aux_clk_src.clkr,
6996 	[GCC_PCIE_3A_CFG_AHB_CLK] = &gcc_pcie_3a_cfg_ahb_clk.clkr,
6997 	[GCC_PCIE_3A_MSTR_AXI_CLK] = &gcc_pcie_3a_mstr_axi_clk.clkr,
6998 	[GCC_PCIE_3A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3a_phy_rchng_clk_src.clkr,
6999 	[GCC_PCIE_3A_PIPE_CLK] = &gcc_pcie_3a_pipe_clk.clkr,
7000 	[GCC_PCIE_3A_PIPE_CLK_SRC] = &gcc_pcie_3a_pipe_clk_src.clkr,
7001 	[GCC_PCIE_3A_PIPE_DIV_CLK_SRC] = &gcc_pcie_3a_pipe_div_clk_src.clkr,
7002 	[GCC_PCIE_3A_PIPEDIV2_CLK] = &gcc_pcie_3a_pipediv2_clk.clkr,
7003 	[GCC_PCIE_3A_SLV_AXI_CLK] = &gcc_pcie_3a_slv_axi_clk.clkr,
7004 	[GCC_PCIE_3A_SLV_Q2A_AXI_CLK] = &gcc_pcie_3a_slv_q2a_axi_clk.clkr,
7005 	[GCC_PCIE_3B_AUX_CLK] = &gcc_pcie_3b_aux_clk.clkr,
7006 	[GCC_PCIE_3B_AUX_CLK_SRC] = &gcc_pcie_3b_aux_clk_src.clkr,
7007 	[GCC_PCIE_3B_CFG_AHB_CLK] = &gcc_pcie_3b_cfg_ahb_clk.clkr,
7008 	[GCC_PCIE_3B_MSTR_AXI_CLK] = &gcc_pcie_3b_mstr_axi_clk.clkr,
7009 	[GCC_PCIE_3B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3b_phy_rchng_clk_src.clkr,
7010 	[GCC_PCIE_3B_PIPE_CLK] = &gcc_pcie_3b_pipe_clk.clkr,
7011 	[GCC_PCIE_3B_PIPE_CLK_SRC] = &gcc_pcie_3b_pipe_clk_src.clkr,
7012 	[GCC_PCIE_3B_PIPE_DIV_CLK_SRC] = &gcc_pcie_3b_pipe_div_clk_src.clkr,
7013 	[GCC_PCIE_3B_PIPEDIV2_CLK] = &gcc_pcie_3b_pipediv2_clk.clkr,
7014 	[GCC_PCIE_3B_SLV_AXI_CLK] = &gcc_pcie_3b_slv_axi_clk.clkr,
7015 	[GCC_PCIE_3B_SLV_Q2A_AXI_CLK] = &gcc_pcie_3b_slv_q2a_axi_clk.clkr,
7016 	[GCC_PCIE_4_AUX_CLK] = &gcc_pcie_4_aux_clk.clkr,
7017 	[GCC_PCIE_4_AUX_CLK_SRC] = &gcc_pcie_4_aux_clk_src.clkr,
7018 	[GCC_PCIE_4_CFG_AHB_CLK] = &gcc_pcie_4_cfg_ahb_clk.clkr,
7019 	[GCC_PCIE_4_CLKREF_CLK] = &gcc_pcie_4_clkref_clk.clkr,
7020 	[GCC_PCIE_4_MSTR_AXI_CLK] = &gcc_pcie_4_mstr_axi_clk.clkr,
7021 	[GCC_PCIE_4_PHY_RCHNG_CLK_SRC] = &gcc_pcie_4_phy_rchng_clk_src.clkr,
7022 	[GCC_PCIE_4_PIPE_CLK] = &gcc_pcie_4_pipe_clk.clkr,
7023 	[GCC_PCIE_4_PIPE_CLK_SRC] = &gcc_pcie_4_pipe_clk_src.clkr,
7024 	[GCC_PCIE_4_PIPE_DIV_CLK_SRC] = &gcc_pcie_4_pipe_div_clk_src.clkr,
7025 	[GCC_PCIE_4_PIPEDIV2_CLK] = &gcc_pcie_4_pipediv2_clk.clkr,
7026 	[GCC_PCIE_4_SLV_AXI_CLK] = &gcc_pcie_4_slv_axi_clk.clkr,
7027 	[GCC_PCIE_4_SLV_Q2A_AXI_CLK] = &gcc_pcie_4_slv_q2a_axi_clk.clkr,
7028 	[GCC_PCIE_RSCC_AHB_CLK] = &gcc_pcie_rscc_ahb_clk.clkr,
7029 	[GCC_PCIE_RSCC_XO_CLK] = &gcc_pcie_rscc_xo_clk.clkr,
7030 	[GCC_PCIE_RSCC_XO_CLK_SRC] = &gcc_pcie_rscc_xo_clk_src.clkr,
7031 	[GCC_PCIE_THROTTLE_CFG_CLK] = &gcc_pcie_throttle_cfg_clk.clkr,
7032 	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
7033 	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
7034 	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
7035 	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
7036 	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
7037 	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
7038 	[GCC_QMIP_DISP1_AHB_CLK] = &gcc_qmip_disp1_ahb_clk.clkr,
7039 	[GCC_QMIP_DISP1_ROT_AHB_CLK] = &gcc_qmip_disp1_rot_ahb_clk.clkr,
7040 	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
7041 	[GCC_QMIP_DISP_ROT_AHB_CLK] = &gcc_qmip_disp_rot_ahb_clk.clkr,
7042 	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
7043 	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
7044 	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
7045 	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
7046 	[GCC_QUPV3_WRAP0_QSPI0_CLK] = &gcc_qupv3_wrap0_qspi0_clk.clkr,
7047 	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
7048 	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
7049 	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
7050 	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
7051 	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
7052 	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
7053 	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
7054 	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
7055 	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
7056 	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
7057 	[GCC_QUPV3_WRAP0_S4_DIV_CLK_SRC] = &gcc_qupv3_wrap0_s4_div_clk_src.clkr,
7058 	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
7059 	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
7060 	[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
7061 	[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
7062 	[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
7063 	[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
7064 	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
7065 	[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
7066 	[GCC_QUPV3_WRAP1_QSPI0_CLK] = &gcc_qupv3_wrap1_qspi0_clk.clkr,
7067 	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
7068 	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
7069 	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
7070 	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
7071 	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
7072 	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
7073 	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
7074 	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
7075 	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
7076 	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
7077 	[GCC_QUPV3_WRAP1_S4_DIV_CLK_SRC] = &gcc_qupv3_wrap1_s4_div_clk_src.clkr,
7078 	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
7079 	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
7080 	[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
7081 	[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
7082 	[GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
7083 	[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
7084 	[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
7085 	[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
7086 	[GCC_QUPV3_WRAP2_QSPI0_CLK] = &gcc_qupv3_wrap2_qspi0_clk.clkr,
7087 	[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
7088 	[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
7089 	[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
7090 	[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
7091 	[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
7092 	[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
7093 	[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
7094 	[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
7095 	[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
7096 	[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
7097 	[GCC_QUPV3_WRAP2_S4_DIV_CLK_SRC] = &gcc_qupv3_wrap2_s4_div_clk_src.clkr,
7098 	[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
7099 	[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
7100 	[GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
7101 	[GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
7102 	[GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr,
7103 	[GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr,
7104 	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
7105 	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
7106 	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
7107 	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
7108 	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
7109 	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
7110 	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
7111 	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
7112 	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
7113 	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
7114 	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
7115 	[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
7116 	[GCC_SYS_NOC_USB_AXI_CLK] = &gcc_sys_noc_usb_axi_clk.clkr,
7117 	[GCC_UFS_1_CARD_CLKREF_CLK] = &gcc_ufs_1_card_clkref_clk.clkr,
7118 	[GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
7119 	[GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
7120 	[GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
7121 	[GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
7122 	[GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
7123 	[GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
7124 	[GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
7125 	[GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
7126 	[GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
7127 	[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
7128 	[GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
7129 	[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
7130 	[GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_rx_symbol_0_clk_src.clkr,
7131 	[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
7132 	[GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_card_rx_symbol_1_clk_src.clkr,
7133 	[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
7134 	[GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_tx_symbol_0_clk_src.clkr,
7135 	[GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
7136 	[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr,
7137 	[GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
7138 	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
7139 	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
7140 	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
7141 	[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
7142 	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
7143 	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
7144 	[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
7145 	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
7146 	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
7147 	[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
7148 	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
7149 	[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
7150 	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
7151 	[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
7152 	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
7153 	[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
7154 	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
7155 	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
7156 	[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
7157 	[GCC_UFS_REF_CLKREF_CLK] = &gcc_ufs_ref_clkref_clk.clkr,
7158 	[GCC_USB2_HS0_CLKREF_CLK] = &gcc_usb2_hs0_clkref_clk.clkr,
7159 	[GCC_USB2_HS1_CLKREF_CLK] = &gcc_usb2_hs1_clkref_clk.clkr,
7160 	[GCC_USB2_HS2_CLKREF_CLK] = &gcc_usb2_hs2_clkref_clk.clkr,
7161 	[GCC_USB2_HS3_CLKREF_CLK] = &gcc_usb2_hs3_clkref_clk.clkr,
7162 	[GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr,
7163 	[GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr,
7164 	[GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr,
7165 	[GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr,
7166 	[GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr,
7167 	[GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr,
7168 	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
7169 	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
7170 	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
7171 	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
7172 	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
7173 	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
7174 	[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
7175 	[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
7176 	[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
7177 	[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
7178 	[GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
7179 	[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
7180 	[GCC_USB34_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb34_prim_phy_pipe_clk_src.clkr,
7181 	[GCC_USB34_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb34_sec_phy_pipe_clk_src.clkr,
7182 	[GCC_USB3_MP0_CLKREF_CLK] = &gcc_usb3_mp0_clkref_clk.clkr,
7183 	[GCC_USB3_MP1_CLKREF_CLK] = &gcc_usb3_mp1_clkref_clk.clkr,
7184 	[GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr,
7185 	[GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr,
7186 	[GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr,
7187 	[GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr,
7188 	[GCC_USB3_MP_PHY_PIPE_0_CLK_SRC] = &gcc_usb3_mp_phy_pipe_0_clk_src.clkr,
7189 	[GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr,
7190 	[GCC_USB3_MP_PHY_PIPE_1_CLK_SRC] = &gcc_usb3_mp_phy_pipe_1_clk_src.clkr,
7191 	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
7192 	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
7193 	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
7194 	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
7195 	[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
7196 	[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
7197 	[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
7198 	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
7199 	[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
7200 	[GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
7201 	[GCC_USB4_1_CFG_AHB_CLK] = &gcc_usb4_1_cfg_ahb_clk.clkr,
7202 	[GCC_USB4_1_DP_CLK] = &gcc_usb4_1_dp_clk.clkr,
7203 	[GCC_USB4_1_MASTER_CLK] = &gcc_usb4_1_master_clk.clkr,
7204 	[GCC_USB4_1_MASTER_CLK_SRC] = &gcc_usb4_1_master_clk_src.clkr,
7205 	[GCC_USB4_1_PHY_DP_CLK_SRC] = &gcc_usb4_1_phy_dp_clk_src.clkr,
7206 	[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr,
7207 	[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr,
7208 	[GCC_USB4_1_PHY_PCIE_PIPE_CLK] = &gcc_usb4_1_phy_pcie_pipe_clk.clkr,
7209 	[GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr,
7210 	[GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr,
7211 	[GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipegmux_clk_src.clkr,
7212 	[GCC_USB4_1_PHY_RX0_CLK] = &gcc_usb4_1_phy_rx0_clk.clkr,
7213 	[GCC_USB4_1_PHY_RX0_CLK_SRC] = &gcc_usb4_1_phy_rx0_clk_src.clkr,
7214 	[GCC_USB4_1_PHY_RX1_CLK] = &gcc_usb4_1_phy_rx1_clk.clkr,
7215 	[GCC_USB4_1_PHY_RX1_CLK_SRC] = &gcc_usb4_1_phy_rx1_clk_src.clkr,
7216 	[GCC_USB4_1_PHY_SYS_CLK_SRC] = &gcc_usb4_1_phy_sys_clk_src.clkr,
7217 	[GCC_USB4_1_PHY_USB_PIPE_CLK] = &gcc_usb4_1_phy_usb_pipe_clk.clkr,
7218 	[GCC_USB4_1_SB_IF_CLK] = &gcc_usb4_1_sb_if_clk.clkr,
7219 	[GCC_USB4_1_SB_IF_CLK_SRC] = &gcc_usb4_1_sb_if_clk_src.clkr,
7220 	[GCC_USB4_1_SYS_CLK] = &gcc_usb4_1_sys_clk.clkr,
7221 	[GCC_USB4_1_TMU_CLK] = &gcc_usb4_1_tmu_clk.clkr,
7222 	[GCC_USB4_1_TMU_CLK_SRC] = &gcc_usb4_1_tmu_clk_src.clkr,
7223 	[GCC_USB4_CFG_AHB_CLK] = &gcc_usb4_cfg_ahb_clk.clkr,
7224 	[GCC_USB4_CLKREF_CLK] = &gcc_usb4_clkref_clk.clkr,
7225 	[GCC_USB4_DP_CLK] = &gcc_usb4_dp_clk.clkr,
7226 	[GCC_USB4_EUD_CLKREF_CLK] = &gcc_usb4_eud_clkref_clk.clkr,
7227 	[GCC_USB4_MASTER_CLK] = &gcc_usb4_master_clk.clkr,
7228 	[GCC_USB4_MASTER_CLK_SRC] = &gcc_usb4_master_clk_src.clkr,
7229 	[GCC_USB4_PHY_DP_CLK_SRC] = &gcc_usb4_phy_dp_clk_src.clkr,
7230 	[GCC_USB4_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_phy_p2rr2p_pipe_clk.clkr,
7231 	[GCC_USB4_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_phy_p2rr2p_pipe_clk_src.clkr,
7232 	[GCC_USB4_PHY_PCIE_PIPE_CLK] = &gcc_usb4_phy_pcie_pipe_clk.clkr,
7233 	[GCC_USB4_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_phy_pcie_pipe_clk_src.clkr,
7234 	[GCC_USB4_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_phy_pcie_pipe_mux_clk_src.clkr,
7235 	[GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC] = &gcc_usb4_phy_pcie_pipegmux_clk_src.clkr,
7236 	[GCC_USB4_PHY_RX0_CLK] = &gcc_usb4_phy_rx0_clk.clkr,
7237 	[GCC_USB4_PHY_RX0_CLK_SRC] = &gcc_usb4_phy_rx0_clk_src.clkr,
7238 	[GCC_USB4_PHY_RX1_CLK] = &gcc_usb4_phy_rx1_clk.clkr,
7239 	[GCC_USB4_PHY_RX1_CLK_SRC] = &gcc_usb4_phy_rx1_clk_src.clkr,
7240 	[GCC_USB4_PHY_SYS_CLK_SRC] = &gcc_usb4_phy_sys_clk_src.clkr,
7241 	[GCC_USB4_PHY_USB_PIPE_CLK] = &gcc_usb4_phy_usb_pipe_clk.clkr,
7242 	[GCC_USB4_SB_IF_CLK] = &gcc_usb4_sb_if_clk.clkr,
7243 	[GCC_USB4_SB_IF_CLK_SRC] = &gcc_usb4_sb_if_clk_src.clkr,
7244 	[GCC_USB4_SYS_CLK] = &gcc_usb4_sys_clk.clkr,
7245 	[GCC_USB4_TMU_CLK] = &gcc_usb4_tmu_clk.clkr,
7246 	[GCC_USB4_TMU_CLK_SRC] = &gcc_usb4_tmu_clk_src.clkr,
7247 	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
7248 	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
7249 	[GCC_VIDEO_CVP_THROTTLE_CLK] = &gcc_video_cvp_throttle_clk.clkr,
7250 	[GCC_VIDEO_VCODEC_THROTTLE_CLK] = &gcc_video_vcodec_throttle_clk.clkr,
7251 };
7252 
7253 static const struct qcom_reset_map gcc_sc8280xp_resets[] = {
7254 	[GCC_EMAC0_BCR] = { 0xaa000 },
7255 	[GCC_EMAC1_BCR] = { 0xba000 },
7256 	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
7257 	[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
7258 	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
7259 	[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
7260 	[GCC_PCIE_0_TUNNEL_BCR] = { 0xa4000 },
7261 	[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
7262 	[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
7263 	[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
7264 	[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 },
7265 	[GCC_PCIE_1_TUNNEL_BCR] = { 0x8d000 },
7266 	[GCC_PCIE_2A_BCR] = { 0x9d000 },
7267 	[GCC_PCIE_2A_LINK_DOWN_BCR] = { 0x9d13c },
7268 	[GCC_PCIE_2A_NOCSR_COM_PHY_BCR] = { 0x9d148 },
7269 	[GCC_PCIE_2A_PHY_BCR] = { 0x9d144 },
7270 	[GCC_PCIE_2A_PHY_NOCSR_COM_PHY_BCR] = { 0x9d14c },
7271 	[GCC_PCIE_2B_BCR] = { 0x9e000 },
7272 	[GCC_PCIE_2B_LINK_DOWN_BCR] = { 0x9e084 },
7273 	[GCC_PCIE_2B_NOCSR_COM_PHY_BCR] = { 0x9e090 },
7274 	[GCC_PCIE_2B_PHY_BCR] = { 0x9e08c },
7275 	[GCC_PCIE_2B_PHY_NOCSR_COM_PHY_BCR] = { 0x9e094 },
7276 	[GCC_PCIE_3A_BCR] = { 0xa0000 },
7277 	[GCC_PCIE_3A_LINK_DOWN_BCR] = { 0xa00f0 },
7278 	[GCC_PCIE_3A_NOCSR_COM_PHY_BCR] = { 0xa00fc },
7279 	[GCC_PCIE_3A_PHY_BCR] = { 0xa00e0 },
7280 	[GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR] = { 0xa00e4 },
7281 	[GCC_PCIE_3B_BCR] = { 0xa2000 },
7282 	[GCC_PCIE_3B_LINK_DOWN_BCR] = { 0xa20e0 },
7283 	[GCC_PCIE_3B_NOCSR_COM_PHY_BCR] = { 0xa20ec },
7284 	[GCC_PCIE_3B_PHY_BCR] = { 0xa20e8 },
7285 	[GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR] = { 0xa20f0 },
7286 	[GCC_PCIE_4_BCR] = { 0x6b000 },
7287 	[GCC_PCIE_4_LINK_DOWN_BCR] = { 0x6b300 },
7288 	[GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0x6b30c },
7289 	[GCC_PCIE_4_PHY_BCR] = { 0x6b308 },
7290 	[GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0x6b310 },
7291 	[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
7292 	[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
7293 	[GCC_PCIE_RSCC_BCR] = { 0xae000 },
7294 	[GCC_QUSB2PHY_HS0_MP_BCR] = { 0x12008 },
7295 	[GCC_QUSB2PHY_HS1_MP_BCR] = { 0x1200c },
7296 	[GCC_QUSB2PHY_HS2_MP_BCR] = { 0x12010 },
7297 	[GCC_QUSB2PHY_HS3_MP_BCR] = { 0x12014 },
7298 	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
7299 	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
7300 	[GCC_SDCC2_BCR] = { 0x14000 },
7301 	[GCC_SDCC4_BCR] = { 0x16000 },
7302 	[GCC_UFS_CARD_BCR] = { 0x75000 },
7303 	[GCC_UFS_PHY_BCR] = { 0x77000 },
7304 	[GCC_USB2_PHY_PRIM_BCR] = { 0x50028 },
7305 	[GCC_USB2_PHY_SEC_BCR] = { 0x5002c },
7306 	[GCC_USB30_MP_BCR] = { 0xab000 },
7307 	[GCC_USB30_PRIM_BCR] = { 0xf000 },
7308 	[GCC_USB30_SEC_BCR] = { 0x10000 },
7309 	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
7310 	[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
7311 	[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
7312 	[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
7313 	[GCC_USB3_UNIPHY_MP0_BCR] = { 0x50018 },
7314 	[GCC_USB3_UNIPHY_MP1_BCR] = { 0x5001c },
7315 	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
7316 	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
7317 	[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x50020 },
7318 	[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x50024 },
7319 	[GCC_USB4_1_BCR] = { 0xb8000 },
7320 	[GCC_USB4_1_DP_PHY_PRIM_BCR] = { 0xb9020 },
7321 	[GCC_USB4_1_DPPHY_AUX_BCR] = { 0xb9024 },
7322 	[GCC_USB4_1_PHY_PRIM_BCR] = { 0xb9018 },
7323 	[GCC_USB4_BCR] = { 0x2a000 },
7324 	[GCC_USB4_DP_PHY_PRIM_BCR] = { 0x4a008 },
7325 	[GCC_USB4_DPPHY_AUX_BCR] = { 0x4a00c },
7326 	[GCC_USB4_PHY_PRIM_BCR] = { 0x4a000 },
7327 	[GCC_USB4PHY_1_PHY_PRIM_BCR] = { 0xb901c },
7328 	[GCC_USB4PHY_PHY_PRIM_BCR] = { 0x4a004 },
7329 	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
7330 	[GCC_VIDEO_BCR] = { 0x28000 },
7331 	[GCC_VIDEO_AXI0_CLK_ARES] = { 0x28010, 2 },
7332 	[GCC_VIDEO_AXI1_CLK_ARES] = { 0x28018, 2 },
7333 };
7334 
7335 static struct gdsc *gcc_sc8280xp_gdscs[] = {
7336 	[PCIE_0_TUNNEL_GDSC] = &pcie_0_tunnel_gdsc,
7337 	[PCIE_1_TUNNEL_GDSC] = &pcie_1_tunnel_gdsc,
7338 	[PCIE_2A_GDSC] = &pcie_2a_gdsc,
7339 	[PCIE_2B_GDSC] = &pcie_2b_gdsc,
7340 	[PCIE_3A_GDSC] = &pcie_3a_gdsc,
7341 	[PCIE_3B_GDSC] = &pcie_3b_gdsc,
7342 	[PCIE_4_GDSC] = &pcie_4_gdsc,
7343 	[UFS_CARD_GDSC] = &ufs_card_gdsc,
7344 	[UFS_PHY_GDSC] = &ufs_phy_gdsc,
7345 	[USB30_MP_GDSC] = &usb30_mp_gdsc,
7346 	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
7347 	[USB30_SEC_GDSC] = &usb30_sec_gdsc,
7348 };
7349 
7350 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
7351 	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
7352 	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
7353 	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
7354 	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
7355 	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
7356 	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
7357 	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
7358 	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
7359 	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
7360 	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
7361 	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
7362 	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
7363 	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
7364 	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
7365 	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
7366 	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
7367 	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
7368 	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
7369 	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
7370 	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
7371 	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
7372 	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
7373 	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
7374 	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src),
7375 };
7376 
7377 static const struct regmap_config gcc_sc8280xp_regmap_config = {
7378 	.reg_bits = 32,
7379 	.reg_stride = 4,
7380 	.val_bits = 32,
7381 	.max_register = 0xc3014,
7382 	.fast_io = true,
7383 };
7384 
7385 static const struct qcom_cc_desc gcc_sc8280xp_desc = {
7386 	.config = &gcc_sc8280xp_regmap_config,
7387 	.clks = gcc_sc8280xp_clocks,
7388 	.num_clks = ARRAY_SIZE(gcc_sc8280xp_clocks),
7389 	.resets = gcc_sc8280xp_resets,
7390 	.num_resets = ARRAY_SIZE(gcc_sc8280xp_resets),
7391 	.gdscs = gcc_sc8280xp_gdscs,
7392 	.num_gdscs = ARRAY_SIZE(gcc_sc8280xp_gdscs),
7393 };
7394 
7395 static int gcc_sc8280xp_probe(struct platform_device *pdev)
7396 {
7397 	struct regmap *regmap;
7398 	int ret;
7399 
7400 	regmap = qcom_cc_map(pdev, &gcc_sc8280xp_desc);
7401 	if (IS_ERR(regmap))
7402 		return PTR_ERR(regmap);
7403 
7404 	/*
7405 	 * Keep the clocks always-ON
7406 	 * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK,
7407 	 * GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK,
7408 	 * GCC_VIDEO_XO_CLK, GCC_DISP1_AHB_CLK, GCC_DISP1_XO_CLK
7409 	 */
7410 	regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
7411 	regmap_update_bits(regmap, 0x26020, BIT(0), BIT(0));
7412 	regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
7413 	regmap_update_bits(regmap, 0x27028, BIT(0), BIT(0));
7414 	regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
7415 	regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0));
7416 	regmap_update_bits(regmap, 0x28028, BIT(0), BIT(0));
7417 	regmap_update_bits(regmap, 0xbb004, BIT(0), BIT(0));
7418 	regmap_update_bits(regmap, 0xbb028, BIT(0), BIT(0));
7419 
7420 	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
7421 	if (ret)
7422 		return ret;
7423 
7424 	return qcom_cc_really_probe(pdev, &gcc_sc8280xp_desc, regmap);
7425 }
7426 
7427 static const struct of_device_id gcc_sc8280xp_match_table[] = {
7428 	{ .compatible = "qcom,gcc-sc8280xp" },
7429 	{ }
7430 };
7431 MODULE_DEVICE_TABLE(of, gcc_sc8280xp_match_table);
7432 
7433 static struct platform_driver gcc_sc8280xp_driver = {
7434 	.probe = gcc_sc8280xp_probe,
7435 	.driver = {
7436 		.name = "gcc-sc8280xp",
7437 		.of_match_table = gcc_sc8280xp_match_table,
7438 	},
7439 };
7440 
7441 static int __init gcc_sc8280xp_init(void)
7442 {
7443 	return platform_driver_register(&gcc_sc8280xp_driver);
7444 }
7445 subsys_initcall(gcc_sc8280xp_init);
7446 
7447 static void __exit gcc_sc8280xp_exit(void)
7448 {
7449 	platform_driver_unregister(&gcc_sc8280xp_driver);
7450 }
7451 module_exit(gcc_sc8280xp_exit);
7452 
7453 MODULE_DESCRIPTION("Qualcomm SC8280XP GCC driver");
7454 MODULE_LICENSE("GPL");
7455