1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020-2021, Linaro Ltd. 5 */ 6 7 #include <linux/bitops.h> 8 #include <linux/clk-provider.h> 9 #include <linux/err.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 #include <linux/reset-controller.h> 16 17 #include <dt-bindings/clock/qcom,gcc-sc8180x.h> 18 19 #include "common.h" 20 #include "clk-alpha-pll.h" 21 #include "clk-branch.h" 22 #include "clk-pll.h" 23 #include "clk-rcg.h" 24 #include "clk-regmap.h" 25 #include "gdsc.h" 26 #include "reset.h" 27 28 enum { 29 P_AUD_REF_CLK, 30 P_BI_TCXO, 31 P_GPLL0_OUT_EVEN, 32 P_GPLL0_OUT_MAIN, 33 P_GPLL1_OUT_MAIN, 34 P_GPLL2_OUT_MAIN, 35 P_GPLL4_OUT_MAIN, 36 P_GPLL5_OUT_MAIN, 37 P_GPLL7_OUT_MAIN, 38 P_GPLL9_OUT_MAIN, 39 P_SLEEP_CLK, 40 }; 41 42 static struct pll_vco trion_vco[] = { 43 { 249600000, 2000000000, 0 }, 44 }; 45 46 static struct clk_alpha_pll gpll0 = { 47 .offset = 0x0, 48 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 49 .vco_table = trion_vco, 50 .num_vco = ARRAY_SIZE(trion_vco), 51 .clkr = { 52 .enable_reg = 0x52000, 53 .enable_mask = BIT(0), 54 .hw.init = &(struct clk_init_data){ 55 .name = "gpll0", 56 .parent_data = &(const struct clk_parent_data){ 57 .fw_name = "bi_tcxo", 58 }, 59 .num_parents = 1, 60 .ops = &clk_alpha_pll_fixed_trion_ops, 61 }, 62 }, 63 }; 64 65 static const struct clk_div_table post_div_table_trion_even[] = { 66 { 0x0, 1 }, 67 { 0x1, 2 }, 68 { 0x3, 4 }, 69 { 0x7, 8 }, 70 { } 71 }; 72 73 static struct clk_alpha_pll_postdiv gpll0_out_even = { 74 .offset = 0x0, 75 .post_div_shift = 8, 76 .post_div_table = post_div_table_trion_even, 77 .num_post_div = ARRAY_SIZE(post_div_table_trion_even), 78 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 79 .width = 4, 80 .clkr.hw.init = &(struct clk_init_data){ 81 .name = "gpll0_out_even", 82 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 83 .num_parents = 1, 84 .ops = &clk_alpha_pll_postdiv_trion_ops, 85 }, 86 }; 87 88 static struct clk_alpha_pll gpll1 = { 89 .offset = 0x1000, 90 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 91 .vco_table = trion_vco, 92 .num_vco = ARRAY_SIZE(trion_vco), 93 .clkr = { 94 .enable_reg = 0x52000, 95 .enable_mask = BIT(1), 96 .hw.init = &(struct clk_init_data){ 97 .name = "gpll1", 98 .parent_data = &(const struct clk_parent_data){ 99 .fw_name = "bi_tcxo", 100 }, 101 .num_parents = 1, 102 .ops = &clk_alpha_pll_fixed_trion_ops, 103 }, 104 }, 105 }; 106 107 static struct clk_alpha_pll gpll4 = { 108 .offset = 0x76000, 109 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 110 .vco_table = trion_vco, 111 .num_vco = ARRAY_SIZE(trion_vco), 112 .clkr = { 113 .enable_reg = 0x52000, 114 .enable_mask = BIT(4), 115 .hw.init = &(struct clk_init_data){ 116 .name = "gpll4", 117 .parent_data = &(const struct clk_parent_data){ 118 .fw_name = "bi_tcxo", 119 }, 120 .num_parents = 1, 121 .ops = &clk_alpha_pll_fixed_trion_ops, 122 }, 123 }, 124 }; 125 126 static struct clk_alpha_pll gpll7 = { 127 .offset = 0x1a000, 128 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 129 .vco_table = trion_vco, 130 .num_vco = ARRAY_SIZE(trion_vco), 131 .clkr = { 132 .enable_reg = 0x52000, 133 .enable_mask = BIT(7), 134 .hw.init = &(struct clk_init_data){ 135 .name = "gpll7", 136 .parent_data = &(const struct clk_parent_data){ 137 .fw_name = "bi_tcxo", 138 }, 139 .num_parents = 1, 140 .ops = &clk_alpha_pll_fixed_trion_ops, 141 }, 142 }, 143 }; 144 145 static struct clk_alpha_pll gpll9 = { 146 .offset = 0x1c000, 147 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 148 .clkr = { 149 .enable_reg = 0x52000, 150 .enable_mask = BIT(9), 151 .hw.init = &(const struct clk_init_data) { 152 .name = "gpll9", 153 .parent_data = &(const struct clk_parent_data) { 154 .fw_name = "bi_tcxo", 155 }, 156 .num_parents = 1, 157 .ops = &clk_alpha_pll_fixed_trion_ops, 158 }, 159 }, 160 }; 161 162 static const struct parent_map gcc_parent_map_0[] = { 163 { P_BI_TCXO, 0 }, 164 { P_GPLL0_OUT_MAIN, 1 }, 165 { P_GPLL0_OUT_EVEN, 6 }, 166 }; 167 168 static const struct clk_parent_data gcc_parents_0[] = { 169 { .fw_name = "bi_tcxo" }, 170 { .hw = &gpll0.clkr.hw }, 171 { .hw = &gpll0_out_even.clkr.hw }, 172 }; 173 174 static const struct parent_map gcc_parent_map_1[] = { 175 { P_BI_TCXO, 0 }, 176 { P_GPLL0_OUT_MAIN, 1 }, 177 { P_SLEEP_CLK, 5 }, 178 { P_GPLL0_OUT_EVEN, 6 }, 179 }; 180 181 static const struct clk_parent_data gcc_parents_1[] = { 182 { .fw_name = "bi_tcxo", }, 183 { .hw = &gpll0.clkr.hw }, 184 { .fw_name = "sleep_clk", }, 185 { .hw = &gpll0_out_even.clkr.hw }, 186 }; 187 188 static const struct parent_map gcc_parent_map_2[] = { 189 { P_BI_TCXO, 0 }, 190 { P_SLEEP_CLK, 5 }, 191 }; 192 193 static const struct clk_parent_data gcc_parents_2[] = { 194 { .fw_name = "bi_tcxo", }, 195 { .fw_name = "sleep_clk", }, 196 }; 197 198 static const struct parent_map gcc_parent_map_3[] = { 199 { P_BI_TCXO, 0 }, 200 { P_GPLL0_OUT_MAIN, 1 }, 201 { P_GPLL2_OUT_MAIN, 2 }, 202 { P_GPLL5_OUT_MAIN, 3 }, 203 { P_GPLL1_OUT_MAIN, 4 }, 204 { P_GPLL4_OUT_MAIN, 5 }, 205 { P_GPLL0_OUT_EVEN, 6 }, 206 }; 207 208 static const struct clk_parent_data gcc_parents_3[] = { 209 { .fw_name = "bi_tcxo", }, 210 { .hw = &gpll0.clkr.hw }, 211 { .name = "gpll2" }, 212 { .name = "gpll5" }, 213 { .hw = &gpll1.clkr.hw }, 214 { .hw = &gpll4.clkr.hw }, 215 { .hw = &gpll0_out_even.clkr.hw }, 216 }; 217 218 static const struct parent_map gcc_parent_map_4[] = { 219 { P_BI_TCXO, 0 }, 220 }; 221 222 static const struct clk_parent_data gcc_parents_4[] = { 223 { .fw_name = "bi_tcxo", }, 224 }; 225 226 static const struct parent_map gcc_parent_map_5[] = { 227 { P_BI_TCXO, 0 }, 228 { P_GPLL0_OUT_MAIN, 1 }, 229 }; 230 231 static const struct clk_parent_data gcc_parents_5[] = { 232 { .fw_name = "bi_tcxo", }, 233 { .hw = &gpll0.clkr.hw }, 234 }; 235 236 static const struct parent_map gcc_parent_map_6[] = { 237 { P_BI_TCXO, 0 }, 238 { P_GPLL0_OUT_MAIN, 1 }, 239 { P_GPLL7_OUT_MAIN, 3 }, 240 { P_GPLL0_OUT_EVEN, 6 }, 241 }; 242 243 static const struct clk_parent_data gcc_parents_6[] = { 244 { .fw_name = "bi_tcxo", }, 245 { .hw = &gpll0.clkr.hw }, 246 { .hw = &gpll7.clkr.hw }, 247 { .hw = &gpll0_out_even.clkr.hw }, 248 }; 249 250 static const struct parent_map gcc_parent_map_7[] = { 251 { P_BI_TCXO, 0 }, 252 { P_GPLL0_OUT_MAIN, 1 }, 253 { P_GPLL9_OUT_MAIN, 2 }, 254 { P_GPLL4_OUT_MAIN, 5 }, 255 { P_GPLL0_OUT_EVEN, 6 }, 256 }; 257 258 static const struct clk_parent_data gcc_parents_7[] = { 259 { .fw_name = "bi_tcxo", }, 260 { .hw = &gpll0.clkr.hw }, 261 { .hw = &gpll9.clkr.hw }, 262 { .hw = &gpll4.clkr.hw }, 263 { .hw = &gpll0_out_even.clkr.hw }, 264 }; 265 266 static const struct parent_map gcc_parent_map_8[] = { 267 { P_BI_TCXO, 0 }, 268 { P_GPLL0_OUT_MAIN, 1 }, 269 { P_AUD_REF_CLK, 2 }, 270 { P_GPLL0_OUT_EVEN, 6 }, 271 }; 272 273 static const struct clk_parent_data gcc_parents_8[] = { 274 { .fw_name = "bi_tcxo", }, 275 { .hw = &gpll0.clkr.hw }, 276 { .name = "aud_ref_clk" }, 277 { .hw = &gpll0_out_even.clkr.hw }, 278 }; 279 280 static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = { 281 F(19200000, P_BI_TCXO, 1, 0, 0), 282 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 283 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), 284 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), 285 { } 286 }; 287 288 static struct clk_rcg2 gcc_emac_ptp_clk_src = { 289 .cmd_rcgr = 0x6038, 290 .mnd_width = 0, 291 .hid_width = 5, 292 .parent_map = gcc_parent_map_6, 293 .freq_tbl = ftbl_gcc_emac_ptp_clk_src, 294 .clkr.hw.init = &(struct clk_init_data){ 295 .name = "gcc_emac_ptp_clk_src", 296 .parent_data = gcc_parents_6, 297 .num_parents = ARRAY_SIZE(gcc_parents_6), 298 .flags = CLK_SET_RATE_PARENT, 299 .ops = &clk_rcg2_ops, 300 }, 301 }; 302 303 static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = { 304 F(2500000, P_BI_TCXO, 1, 25, 192), 305 F(5000000, P_BI_TCXO, 1, 25, 96), 306 F(19200000, P_BI_TCXO, 1, 0, 0), 307 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 308 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 309 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), 310 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), 311 { } 312 }; 313 314 static struct clk_rcg2 gcc_emac_rgmii_clk_src = { 315 .cmd_rcgr = 0x601c, 316 .mnd_width = 8, 317 .hid_width = 5, 318 .parent_map = gcc_parent_map_6, 319 .freq_tbl = ftbl_gcc_emac_rgmii_clk_src, 320 .clkr.hw.init = &(struct clk_init_data){ 321 .name = "gcc_emac_rgmii_clk_src", 322 .parent_data = gcc_parents_6, 323 .num_parents = ARRAY_SIZE(gcc_parents_6), 324 .flags = CLK_SET_RATE_PARENT, 325 .ops = &clk_rcg2_ops, 326 }, 327 }; 328 329 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 330 F(19200000, P_BI_TCXO, 1, 0, 0), 331 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 332 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 333 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 334 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 335 { } 336 }; 337 338 static struct clk_rcg2 gcc_gp1_clk_src = { 339 .cmd_rcgr = 0x64004, 340 .mnd_width = 8, 341 .hid_width = 5, 342 .parent_map = gcc_parent_map_1, 343 .freq_tbl = ftbl_gcc_gp1_clk_src, 344 .clkr.hw.init = &(struct clk_init_data){ 345 .name = "gcc_gp1_clk_src", 346 .parent_data = gcc_parents_1, 347 .num_parents = ARRAY_SIZE(gcc_parents_1), 348 .flags = CLK_SET_RATE_PARENT, 349 .ops = &clk_rcg2_ops, 350 }, 351 }; 352 353 static struct clk_rcg2 gcc_gp2_clk_src = { 354 .cmd_rcgr = 0x65004, 355 .mnd_width = 8, 356 .hid_width = 5, 357 .parent_map = gcc_parent_map_1, 358 .freq_tbl = ftbl_gcc_gp1_clk_src, 359 .clkr.hw.init = &(struct clk_init_data){ 360 .name = "gcc_gp2_clk_src", 361 .parent_data = gcc_parents_1, 362 .num_parents = ARRAY_SIZE(gcc_parents_1), 363 .flags = CLK_SET_RATE_PARENT, 364 .ops = &clk_rcg2_ops, 365 }, 366 }; 367 368 static struct clk_rcg2 gcc_gp3_clk_src = { 369 .cmd_rcgr = 0x66004, 370 .mnd_width = 8, 371 .hid_width = 5, 372 .parent_map = gcc_parent_map_1, 373 .freq_tbl = ftbl_gcc_gp1_clk_src, 374 .clkr.hw.init = &(struct clk_init_data){ 375 .name = "gcc_gp3_clk_src", 376 .parent_data = gcc_parents_1, 377 .num_parents = ARRAY_SIZE(gcc_parents_1), 378 .flags = CLK_SET_RATE_PARENT, 379 .ops = &clk_rcg2_ops, 380 }, 381 }; 382 383 static struct clk_rcg2 gcc_gp4_clk_src = { 384 .cmd_rcgr = 0xbe004, 385 .mnd_width = 8, 386 .hid_width = 5, 387 .parent_map = gcc_parent_map_1, 388 .freq_tbl = ftbl_gcc_gp1_clk_src, 389 .clkr.hw.init = &(struct clk_init_data){ 390 .name = "gcc_gp4_clk_src", 391 .parent_data = gcc_parents_1, 392 .num_parents = ARRAY_SIZE(gcc_parents_1), 393 .flags = CLK_SET_RATE_PARENT, 394 .ops = &clk_rcg2_ops, 395 }, 396 }; 397 398 static struct clk_rcg2 gcc_gp5_clk_src = { 399 .cmd_rcgr = 0xbf004, 400 .mnd_width = 8, 401 .hid_width = 5, 402 .parent_map = gcc_parent_map_1, 403 .freq_tbl = ftbl_gcc_gp1_clk_src, 404 .clkr.hw.init = &(struct clk_init_data){ 405 .name = "gcc_gp5_clk_src", 406 .parent_data = gcc_parents_1, 407 .num_parents = ARRAY_SIZE(gcc_parents_1), 408 .flags = CLK_SET_RATE_PARENT, 409 .ops = &clk_rcg2_ops, 410 }, 411 }; 412 413 static const struct freq_tbl ftbl_gcc_npu_axi_clk_src[] = { 414 F(19200000, P_BI_TCXO, 1, 0, 0), 415 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), 416 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 417 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 418 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 419 F(403000000, P_GPLL4_OUT_MAIN, 2, 0, 0), 420 F(533000000, P_GPLL1_OUT_MAIN, 2, 0, 0), 421 { } 422 }; 423 424 static struct clk_rcg2 gcc_npu_axi_clk_src = { 425 .cmd_rcgr = 0x4d014, 426 .mnd_width = 0, 427 .hid_width = 5, 428 .parent_map = gcc_parent_map_3, 429 .freq_tbl = ftbl_gcc_npu_axi_clk_src, 430 .clkr.hw.init = &(struct clk_init_data){ 431 .name = "gcc_npu_axi_clk_src", 432 .parent_data = gcc_parents_3, 433 .num_parents = ARRAY_SIZE(gcc_parents_3), 434 .flags = CLK_SET_RATE_PARENT, 435 .ops = &clk_rcg2_ops, 436 }, 437 }; 438 439 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 440 F(9600000, P_BI_TCXO, 2, 0, 0), 441 F(19200000, P_BI_TCXO, 1, 0, 0), 442 { } 443 }; 444 445 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 446 .cmd_rcgr = 0x6b02c, 447 .mnd_width = 16, 448 .hid_width = 5, 449 .parent_map = gcc_parent_map_2, 450 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 451 .clkr.hw.init = &(struct clk_init_data){ 452 .name = "gcc_pcie_0_aux_clk_src", 453 .parent_data = gcc_parents_2, 454 .num_parents = ARRAY_SIZE(gcc_parents_2), 455 .flags = CLK_SET_RATE_PARENT, 456 .ops = &clk_rcg2_ops, 457 }, 458 }; 459 460 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 461 .cmd_rcgr = 0x8d02c, 462 .mnd_width = 16, 463 .hid_width = 5, 464 .parent_map = gcc_parent_map_2, 465 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 466 .clkr.hw.init = &(struct clk_init_data){ 467 .name = "gcc_pcie_1_aux_clk_src", 468 .parent_data = gcc_parents_2, 469 .num_parents = ARRAY_SIZE(gcc_parents_2), 470 .flags = CLK_SET_RATE_PARENT, 471 .ops = &clk_rcg2_ops, 472 }, 473 }; 474 475 static struct clk_rcg2 gcc_pcie_2_aux_clk_src = { 476 .cmd_rcgr = 0x9d02c, 477 .mnd_width = 16, 478 .hid_width = 5, 479 .parent_map = gcc_parent_map_2, 480 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 481 .clkr.hw.init = &(struct clk_init_data){ 482 .name = "gcc_pcie_2_aux_clk_src", 483 .parent_data = gcc_parents_2, 484 .num_parents = ARRAY_SIZE(gcc_parents_2), 485 .flags = CLK_SET_RATE_PARENT, 486 .ops = &clk_rcg2_ops, 487 }, 488 }; 489 490 static struct clk_rcg2 gcc_pcie_3_aux_clk_src = { 491 .cmd_rcgr = 0xa302c, 492 .mnd_width = 16, 493 .hid_width = 5, 494 .parent_map = gcc_parent_map_2, 495 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 496 .clkr.hw.init = &(struct clk_init_data){ 497 .name = "gcc_pcie_3_aux_clk_src", 498 .parent_data = gcc_parents_2, 499 .num_parents = ARRAY_SIZE(gcc_parents_2), 500 .flags = CLK_SET_RATE_PARENT, 501 .ops = &clk_rcg2_ops, 502 }, 503 }; 504 505 static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { 506 F(19200000, P_BI_TCXO, 1, 0, 0), 507 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 508 { } 509 }; 510 511 static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { 512 .cmd_rcgr = 0x6f014, 513 .mnd_width = 0, 514 .hid_width = 5, 515 .parent_map = gcc_parent_map_0, 516 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, 517 .clkr.hw.init = &(struct clk_init_data){ 518 .name = "gcc_pcie_phy_refgen_clk_src", 519 .parent_data = gcc_parents_0, 520 .num_parents = ARRAY_SIZE(gcc_parents_0), 521 .flags = CLK_SET_RATE_PARENT, 522 .ops = &clk_rcg2_ops, 523 }, 524 }; 525 526 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 527 F(9600000, P_BI_TCXO, 2, 0, 0), 528 F(19200000, P_BI_TCXO, 1, 0, 0), 529 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 530 { } 531 }; 532 533 static struct clk_rcg2 gcc_pdm2_clk_src = { 534 .cmd_rcgr = 0x33010, 535 .mnd_width = 0, 536 .hid_width = 5, 537 .parent_map = gcc_parent_map_0, 538 .freq_tbl = ftbl_gcc_pdm2_clk_src, 539 .clkr.hw.init = &(struct clk_init_data){ 540 .name = "gcc_pdm2_clk_src", 541 .parent_data = gcc_parents_0, 542 .num_parents = ARRAY_SIZE(gcc_parents_0), 543 .flags = CLK_SET_RATE_PARENT, 544 .ops = &clk_rcg2_ops, 545 }, 546 }; 547 548 static const struct freq_tbl ftbl_gcc_qspi_1_core_clk_src[] = { 549 F(19200000, P_BI_TCXO, 1, 0, 0), 550 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 551 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 552 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 553 { } 554 }; 555 556 static struct clk_rcg2 gcc_qspi_1_core_clk_src = { 557 .cmd_rcgr = 0x4a00c, 558 .mnd_width = 0, 559 .hid_width = 5, 560 .parent_map = gcc_parent_map_0, 561 .freq_tbl = ftbl_gcc_qspi_1_core_clk_src, 562 .clkr.hw.init = &(struct clk_init_data){ 563 .name = "gcc_qspi_1_core_clk_src", 564 .parent_data = gcc_parents_0, 565 .num_parents = ARRAY_SIZE(gcc_parents_0), 566 .flags = CLK_SET_RATE_PARENT, 567 .ops = &clk_rcg2_ops, 568 }, 569 }; 570 571 static struct clk_rcg2 gcc_qspi_core_clk_src = { 572 .cmd_rcgr = 0x4b008, 573 .mnd_width = 0, 574 .hid_width = 5, 575 .parent_map = gcc_parent_map_0, 576 .freq_tbl = ftbl_gcc_qspi_1_core_clk_src, 577 .clkr.hw.init = &(struct clk_init_data){ 578 .name = "gcc_qspi_core_clk_src", 579 .parent_data = gcc_parents_0, 580 .num_parents = ARRAY_SIZE(gcc_parents_0), 581 .flags = CLK_SET_RATE_PARENT, 582 .ops = &clk_rcg2_ops, 583 }, 584 }; 585 586 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 587 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 588 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 589 F(19200000, P_BI_TCXO, 1, 0, 0), 590 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 591 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 592 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 593 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 594 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 595 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 596 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 597 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 598 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 599 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), 600 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), 601 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), 602 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), 603 F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75), 604 { } 605 }; 606 607 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 608 .cmd_rcgr = 0x17148, 609 .mnd_width = 16, 610 .hid_width = 5, 611 .parent_map = gcc_parent_map_0, 612 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 613 .clkr.hw.init = &(struct clk_init_data){ 614 .name = "gcc_qupv3_wrap0_s0_clk_src", 615 .parent_data = gcc_parents_0, 616 .num_parents = ARRAY_SIZE(gcc_parents_0), 617 .flags = CLK_SET_RATE_PARENT, 618 .ops = &clk_rcg2_ops, 619 }, 620 }; 621 622 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 623 .cmd_rcgr = 0x17278, 624 .mnd_width = 16, 625 .hid_width = 5, 626 .parent_map = gcc_parent_map_0, 627 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 628 .clkr.hw.init = &(struct clk_init_data){ 629 .name = "gcc_qupv3_wrap0_s1_clk_src", 630 .parent_data = gcc_parents_0, 631 .num_parents = ARRAY_SIZE(gcc_parents_0), 632 .flags = CLK_SET_RATE_PARENT, 633 .ops = &clk_rcg2_ops, 634 }, 635 }; 636 637 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 638 .cmd_rcgr = 0x173a8, 639 .mnd_width = 16, 640 .hid_width = 5, 641 .parent_map = gcc_parent_map_0, 642 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 643 .clkr.hw.init = &(struct clk_init_data){ 644 .name = "gcc_qupv3_wrap0_s2_clk_src", 645 .parent_data = gcc_parents_0, 646 .num_parents = ARRAY_SIZE(gcc_parents_0), 647 .flags = CLK_SET_RATE_PARENT, 648 .ops = &clk_rcg2_ops, 649 }, 650 }; 651 652 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 653 .cmd_rcgr = 0x174d8, 654 .mnd_width = 16, 655 .hid_width = 5, 656 .parent_map = gcc_parent_map_0, 657 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 658 .clkr.hw.init = &(struct clk_init_data){ 659 .name = "gcc_qupv3_wrap0_s3_clk_src", 660 .parent_data = gcc_parents_0, 661 .num_parents = ARRAY_SIZE(gcc_parents_0), 662 .flags = CLK_SET_RATE_PARENT, 663 .ops = &clk_rcg2_ops, 664 }, 665 }; 666 667 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 668 .cmd_rcgr = 0x17608, 669 .mnd_width = 16, 670 .hid_width = 5, 671 .parent_map = gcc_parent_map_0, 672 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 673 .clkr.hw.init = &(struct clk_init_data){ 674 .name = "gcc_qupv3_wrap0_s4_clk_src", 675 .parent_data = gcc_parents_0, 676 .num_parents = ARRAY_SIZE(gcc_parents_0), 677 .flags = CLK_SET_RATE_PARENT, 678 .ops = &clk_rcg2_ops, 679 }, 680 }; 681 682 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 683 .cmd_rcgr = 0x17738, 684 .mnd_width = 16, 685 .hid_width = 5, 686 .parent_map = gcc_parent_map_0, 687 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 688 .clkr.hw.init = &(struct clk_init_data){ 689 .name = "gcc_qupv3_wrap0_s5_clk_src", 690 .parent_data = gcc_parents_0, 691 .num_parents = ARRAY_SIZE(gcc_parents_0), 692 .flags = CLK_SET_RATE_PARENT, 693 .ops = &clk_rcg2_ops, 694 }, 695 }; 696 697 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 698 .cmd_rcgr = 0x17868, 699 .mnd_width = 16, 700 .hid_width = 5, 701 .parent_map = gcc_parent_map_0, 702 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 703 .clkr.hw.init = &(struct clk_init_data){ 704 .name = "gcc_qupv3_wrap0_s6_clk_src", 705 .parent_data = gcc_parents_0, 706 .num_parents = ARRAY_SIZE(gcc_parents_0), 707 .flags = CLK_SET_RATE_PARENT, 708 .ops = &clk_rcg2_ops, 709 }, 710 }; 711 712 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 713 .cmd_rcgr = 0x17998, 714 .mnd_width = 16, 715 .hid_width = 5, 716 .parent_map = gcc_parent_map_0, 717 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 718 .clkr.hw.init = &(struct clk_init_data){ 719 .name = "gcc_qupv3_wrap0_s7_clk_src", 720 .parent_data = gcc_parents_0, 721 .num_parents = ARRAY_SIZE(gcc_parents_0), 722 .flags = CLK_SET_RATE_PARENT, 723 .ops = &clk_rcg2_ops, 724 }, 725 }; 726 727 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 728 .cmd_rcgr = 0x18148, 729 .mnd_width = 16, 730 .hid_width = 5, 731 .parent_map = gcc_parent_map_0, 732 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 733 .clkr.hw.init = &(struct clk_init_data){ 734 .name = "gcc_qupv3_wrap1_s0_clk_src", 735 .parent_data = gcc_parents_0, 736 .num_parents = ARRAY_SIZE(gcc_parents_0), 737 .flags = CLK_SET_RATE_PARENT, 738 .ops = &clk_rcg2_ops, 739 }, 740 }; 741 742 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 743 .cmd_rcgr = 0x18278, 744 .mnd_width = 16, 745 .hid_width = 5, 746 .parent_map = gcc_parent_map_0, 747 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 748 .clkr.hw.init = &(struct clk_init_data){ 749 .name = "gcc_qupv3_wrap1_s1_clk_src", 750 .parent_data = gcc_parents_0, 751 .num_parents = ARRAY_SIZE(gcc_parents_0), 752 .flags = CLK_SET_RATE_PARENT, 753 .ops = &clk_rcg2_ops, 754 }, 755 }; 756 757 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 758 .cmd_rcgr = 0x183a8, 759 .mnd_width = 16, 760 .hid_width = 5, 761 .parent_map = gcc_parent_map_0, 762 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 763 .clkr.hw.init = &(struct clk_init_data){ 764 .name = "gcc_qupv3_wrap1_s2_clk_src", 765 .parent_data = gcc_parents_0, 766 .num_parents = ARRAY_SIZE(gcc_parents_0), 767 .flags = CLK_SET_RATE_PARENT, 768 .ops = &clk_rcg2_ops, 769 }, 770 }; 771 772 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 773 .cmd_rcgr = 0x184d8, 774 .mnd_width = 16, 775 .hid_width = 5, 776 .parent_map = gcc_parent_map_0, 777 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 778 .clkr.hw.init = &(struct clk_init_data){ 779 .name = "gcc_qupv3_wrap1_s3_clk_src", 780 .parent_data = gcc_parents_0, 781 .num_parents = ARRAY_SIZE(gcc_parents_0), 782 .flags = CLK_SET_RATE_PARENT, 783 .ops = &clk_rcg2_ops, 784 }, 785 }; 786 787 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 788 .cmd_rcgr = 0x18608, 789 .mnd_width = 16, 790 .hid_width = 5, 791 .parent_map = gcc_parent_map_0, 792 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 793 .clkr.hw.init = &(struct clk_init_data){ 794 .name = "gcc_qupv3_wrap1_s4_clk_src", 795 .parent_data = gcc_parents_0, 796 .num_parents = ARRAY_SIZE(gcc_parents_0), 797 .flags = CLK_SET_RATE_PARENT, 798 .ops = &clk_rcg2_ops, 799 }, 800 }; 801 802 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 803 .cmd_rcgr = 0x18738, 804 .mnd_width = 16, 805 .hid_width = 5, 806 .parent_map = gcc_parent_map_0, 807 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 808 .clkr.hw.init = &(struct clk_init_data){ 809 .name = "gcc_qupv3_wrap1_s5_clk_src", 810 .parent_data = gcc_parents_0, 811 .num_parents = ARRAY_SIZE(gcc_parents_0), 812 .flags = CLK_SET_RATE_PARENT, 813 .ops = &clk_rcg2_ops, 814 }, 815 }; 816 817 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 818 .cmd_rcgr = 0x1e148, 819 .mnd_width = 16, 820 .hid_width = 5, 821 .parent_map = gcc_parent_map_0, 822 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 823 .clkr.hw.init = &(struct clk_init_data){ 824 .name = "gcc_qupv3_wrap2_s0_clk_src", 825 .parent_data = gcc_parents_0, 826 .num_parents = ARRAY_SIZE(gcc_parents_0), 827 .flags = CLK_SET_RATE_PARENT, 828 .ops = &clk_rcg2_ops, 829 }, 830 }; 831 832 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 833 .cmd_rcgr = 0x1e278, 834 .mnd_width = 16, 835 .hid_width = 5, 836 .parent_map = gcc_parent_map_0, 837 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 838 .clkr.hw.init = &(struct clk_init_data){ 839 .name = "gcc_qupv3_wrap2_s1_clk_src", 840 .parent_data = gcc_parents_0, 841 .num_parents = ARRAY_SIZE(gcc_parents_0), 842 .flags = CLK_SET_RATE_PARENT, 843 .ops = &clk_rcg2_ops, 844 }, 845 }; 846 847 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 848 .cmd_rcgr = 0x1e3a8, 849 .mnd_width = 16, 850 .hid_width = 5, 851 .parent_map = gcc_parent_map_0, 852 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 853 .clkr.hw.init = &(struct clk_init_data){ 854 .name = "gcc_qupv3_wrap2_s2_clk_src", 855 .parent_data = gcc_parents_0, 856 .num_parents = ARRAY_SIZE(gcc_parents_0), 857 .flags = CLK_SET_RATE_PARENT, 858 .ops = &clk_rcg2_ops, 859 }, 860 }; 861 862 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 863 .cmd_rcgr = 0x1e4d8, 864 .mnd_width = 16, 865 .hid_width = 5, 866 .parent_map = gcc_parent_map_0, 867 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 868 .clkr.hw.init = &(struct clk_init_data){ 869 .name = "gcc_qupv3_wrap2_s3_clk_src", 870 .parent_data = gcc_parents_0, 871 .num_parents = ARRAY_SIZE(gcc_parents_0), 872 .flags = CLK_SET_RATE_PARENT, 873 .ops = &clk_rcg2_ops, 874 }, 875 }; 876 877 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 878 .cmd_rcgr = 0x1e608, 879 .mnd_width = 16, 880 .hid_width = 5, 881 .parent_map = gcc_parent_map_0, 882 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 883 .clkr.hw.init = &(struct clk_init_data){ 884 .name = "gcc_qupv3_wrap2_s4_clk_src", 885 .parent_data = gcc_parents_0, 886 .num_parents = ARRAY_SIZE(gcc_parents_0), 887 .flags = CLK_SET_RATE_PARENT, 888 .ops = &clk_rcg2_ops, 889 }, 890 }; 891 892 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 893 .cmd_rcgr = 0x1e738, 894 .mnd_width = 16, 895 .hid_width = 5, 896 .parent_map = gcc_parent_map_0, 897 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 898 .clkr.hw.init = &(struct clk_init_data){ 899 .name = "gcc_qupv3_wrap2_s5_clk_src", 900 .parent_data = gcc_parents_0, 901 .num_parents = ARRAY_SIZE(gcc_parents_0), 902 .flags = CLK_SET_RATE_PARENT, 903 .ops = &clk_rcg2_ops, 904 }, 905 }; 906 907 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 908 F(400000, P_BI_TCXO, 12, 1, 4), 909 F(9600000, P_BI_TCXO, 2, 0, 0), 910 F(19200000, P_BI_TCXO, 1, 0, 0), 911 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 912 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 913 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 914 F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0), 915 { } 916 }; 917 918 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 919 .cmd_rcgr = 0x1400c, 920 .mnd_width = 8, 921 .hid_width = 5, 922 .parent_map = gcc_parent_map_7, 923 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 924 .clkr.hw.init = &(struct clk_init_data){ 925 .name = "gcc_sdcc2_apps_clk_src", 926 .parent_data = gcc_parents_7, 927 .num_parents = ARRAY_SIZE(gcc_parents_7), 928 .flags = CLK_SET_RATE_PARENT, 929 .ops = &clk_rcg2_floor_ops, 930 }, 931 }; 932 933 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 934 F(400000, P_BI_TCXO, 12, 1, 4), 935 F(9600000, P_BI_TCXO, 2, 0, 0), 936 F(19200000, P_BI_TCXO, 1, 0, 0), 937 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 938 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 939 { } 940 }; 941 942 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 943 .cmd_rcgr = 0x1600c, 944 .mnd_width = 8, 945 .hid_width = 5, 946 .parent_map = gcc_parent_map_5, 947 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 948 .clkr.hw.init = &(struct clk_init_data){ 949 .name = "gcc_sdcc4_apps_clk_src", 950 .parent_data = gcc_parents_5, 951 .num_parents = ARRAY_SIZE(gcc_parents_5), 952 .flags = CLK_SET_RATE_PARENT, 953 .ops = &clk_rcg2_floor_ops, 954 }, 955 }; 956 957 static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { 958 F(105495, P_BI_TCXO, 2, 1, 91), 959 { } 960 }; 961 962 static struct clk_rcg2 gcc_tsif_ref_clk_src = { 963 .cmd_rcgr = 0x36010, 964 .mnd_width = 8, 965 .hid_width = 5, 966 .parent_map = gcc_parent_map_8, 967 .freq_tbl = ftbl_gcc_tsif_ref_clk_src, 968 .clkr.hw.init = &(struct clk_init_data){ 969 .name = "gcc_tsif_ref_clk_src", 970 .parent_data = gcc_parents_8, 971 .num_parents = ARRAY_SIZE(gcc_parents_8), 972 .flags = CLK_SET_RATE_PARENT, 973 .ops = &clk_rcg2_ops, 974 }, 975 }; 976 977 static const struct freq_tbl ftbl_gcc_ufs_card_2_axi_clk_src[] = { 978 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 979 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 980 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 981 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 982 { } 983 }; 984 985 static struct clk_rcg2 gcc_ufs_card_2_axi_clk_src = { 986 .cmd_rcgr = 0xa2020, 987 .mnd_width = 8, 988 .hid_width = 5, 989 .parent_map = gcc_parent_map_0, 990 .freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src, 991 .clkr.hw.init = &(struct clk_init_data){ 992 .name = "gcc_ufs_card_2_axi_clk_src", 993 .parent_data = gcc_parents_0, 994 .num_parents = ARRAY_SIZE(gcc_parents_0), 995 .flags = CLK_SET_RATE_PARENT, 996 .ops = &clk_rcg2_ops, 997 }, 998 }; 999 1000 static struct clk_rcg2 gcc_ufs_card_2_ice_core_clk_src = { 1001 .cmd_rcgr = 0xa2060, 1002 .mnd_width = 0, 1003 .hid_width = 5, 1004 .parent_map = gcc_parent_map_0, 1005 .freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src, 1006 .clkr.hw.init = &(struct clk_init_data){ 1007 .name = "gcc_ufs_card_2_ice_core_clk_src", 1008 .parent_data = gcc_parents_0, 1009 .num_parents = ARRAY_SIZE(gcc_parents_0), 1010 .flags = CLK_SET_RATE_PARENT, 1011 .ops = &clk_rcg2_ops, 1012 }, 1013 }; 1014 1015 static const struct freq_tbl ftbl_gcc_ufs_card_2_phy_aux_clk_src[] = { 1016 F(19200000, P_BI_TCXO, 1, 0, 0), 1017 { } 1018 }; 1019 1020 static struct clk_rcg2 gcc_ufs_card_2_phy_aux_clk_src = { 1021 .cmd_rcgr = 0xa2094, 1022 .mnd_width = 0, 1023 .hid_width = 5, 1024 .parent_map = gcc_parent_map_4, 1025 .freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src, 1026 .clkr.hw.init = &(struct clk_init_data){ 1027 .name = "gcc_ufs_card_2_phy_aux_clk_src", 1028 .parent_data = gcc_parents_4, 1029 .num_parents = ARRAY_SIZE(gcc_parents_4), 1030 .flags = CLK_SET_RATE_PARENT, 1031 .ops = &clk_rcg2_ops, 1032 }, 1033 }; 1034 1035 static struct clk_rcg2 gcc_ufs_card_2_unipro_core_clk_src = { 1036 .cmd_rcgr = 0xa2078, 1037 .mnd_width = 0, 1038 .hid_width = 5, 1039 .parent_map = gcc_parent_map_0, 1040 .freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src, 1041 .clkr.hw.init = &(struct clk_init_data){ 1042 .name = "gcc_ufs_card_2_unipro_core_clk_src", 1043 .parent_data = gcc_parents_0, 1044 .num_parents = ARRAY_SIZE(gcc_parents_0), 1045 .flags = CLK_SET_RATE_PARENT, 1046 .ops = &clk_rcg2_ops, 1047 }, 1048 }; 1049 1050 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { 1051 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 1052 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 1053 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 1054 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 1055 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 1056 { } 1057 }; 1058 1059 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { 1060 .cmd_rcgr = 0x75020, 1061 .mnd_width = 8, 1062 .hid_width = 5, 1063 .parent_map = gcc_parent_map_0, 1064 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, 1065 .clkr.hw.init = &(struct clk_init_data){ 1066 .name = "gcc_ufs_card_axi_clk_src", 1067 .parent_data = gcc_parents_0, 1068 .num_parents = ARRAY_SIZE(gcc_parents_0), 1069 .flags = CLK_SET_RATE_PARENT, 1070 .ops = &clk_rcg2_ops, 1071 }, 1072 }; 1073 1074 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { 1075 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 1076 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 1077 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 1078 { } 1079 }; 1080 1081 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { 1082 .cmd_rcgr = 0x75060, 1083 .mnd_width = 0, 1084 .hid_width = 5, 1085 .parent_map = gcc_parent_map_0, 1086 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 1087 .clkr.hw.init = &(struct clk_init_data){ 1088 .name = "gcc_ufs_card_ice_core_clk_src", 1089 .parent_data = gcc_parents_0, 1090 .num_parents = ARRAY_SIZE(gcc_parents_0), 1091 .flags = CLK_SET_RATE_PARENT, 1092 .ops = &clk_rcg2_ops, 1093 }, 1094 }; 1095 1096 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { 1097 .cmd_rcgr = 0x75094, 1098 .mnd_width = 0, 1099 .hid_width = 5, 1100 .parent_map = gcc_parent_map_4, 1101 .freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src, 1102 .clkr.hw.init = &(struct clk_init_data){ 1103 .name = "gcc_ufs_card_phy_aux_clk_src", 1104 .parent_data = gcc_parents_4, 1105 .num_parents = ARRAY_SIZE(gcc_parents_4), 1106 .flags = CLK_SET_RATE_PARENT, 1107 .ops = &clk_rcg2_ops, 1108 }, 1109 }; 1110 1111 static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { 1112 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 1113 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 1114 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 1115 { } 1116 }; 1117 1118 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { 1119 .cmd_rcgr = 0x75078, 1120 .mnd_width = 0, 1121 .hid_width = 5, 1122 .parent_map = gcc_parent_map_0, 1123 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, 1124 .clkr.hw.init = &(struct clk_init_data){ 1125 .name = "gcc_ufs_card_unipro_core_clk_src", 1126 .parent_data = gcc_parents_0, 1127 .num_parents = ARRAY_SIZE(gcc_parents_0), 1128 .flags = CLK_SET_RATE_PARENT, 1129 .ops = &clk_rcg2_ops, 1130 }, 1131 }; 1132 1133 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1134 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 1135 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 1136 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 1137 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 1138 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 1139 { } 1140 }; 1141 1142 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1143 .cmd_rcgr = 0x77020, 1144 .mnd_width = 8, 1145 .hid_width = 5, 1146 .parent_map = gcc_parent_map_0, 1147 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1148 .clkr.hw.init = &(struct clk_init_data){ 1149 .name = "gcc_ufs_phy_axi_clk_src", 1150 .parent_data = gcc_parents_0, 1151 .num_parents = ARRAY_SIZE(gcc_parents_0), 1152 .flags = CLK_SET_RATE_PARENT, 1153 .ops = &clk_rcg2_ops, 1154 }, 1155 }; 1156 1157 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1158 .cmd_rcgr = 0x77060, 1159 .mnd_width = 0, 1160 .hid_width = 5, 1161 .parent_map = gcc_parent_map_0, 1162 .freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src, 1163 .clkr.hw.init = &(struct clk_init_data){ 1164 .name = "gcc_ufs_phy_ice_core_clk_src", 1165 .parent_data = gcc_parents_0, 1166 .num_parents = ARRAY_SIZE(gcc_parents_0), 1167 .flags = CLK_SET_RATE_PARENT, 1168 .ops = &clk_rcg2_ops, 1169 }, 1170 }; 1171 1172 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1173 .cmd_rcgr = 0x77094, 1174 .mnd_width = 0, 1175 .hid_width = 5, 1176 .parent_map = gcc_parent_map_4, 1177 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1178 .clkr.hw.init = &(struct clk_init_data){ 1179 .name = "gcc_ufs_phy_phy_aux_clk_src", 1180 .parent_data = gcc_parents_4, 1181 .num_parents = ARRAY_SIZE(gcc_parents_4), 1182 .flags = CLK_SET_RATE_PARENT, 1183 .ops = &clk_rcg2_ops, 1184 }, 1185 }; 1186 1187 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1188 .cmd_rcgr = 0x77078, 1189 .mnd_width = 0, 1190 .hid_width = 5, 1191 .parent_map = gcc_parent_map_0, 1192 .freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src, 1193 .clkr.hw.init = &(struct clk_init_data){ 1194 .name = "gcc_ufs_phy_unipro_core_clk_src", 1195 .parent_data = gcc_parents_0, 1196 .num_parents = ARRAY_SIZE(gcc_parents_0), 1197 .flags = CLK_SET_RATE_PARENT, 1198 .ops = &clk_rcg2_ops, 1199 }, 1200 }; 1201 1202 static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = { 1203 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), 1204 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), 1205 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 1206 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 1207 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 1208 { } 1209 }; 1210 1211 static struct clk_rcg2 gcc_usb30_mp_master_clk_src = { 1212 .cmd_rcgr = 0xa601c, 1213 .mnd_width = 8, 1214 .hid_width = 5, 1215 .parent_map = gcc_parent_map_0, 1216 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 1217 .clkr.hw.init = &(struct clk_init_data){ 1218 .name = "gcc_usb30_mp_master_clk_src", 1219 .parent_data = gcc_parents_0, 1220 .num_parents = ARRAY_SIZE(gcc_parents_0), 1221 .flags = CLK_SET_RATE_PARENT, 1222 .ops = &clk_rcg2_ops, 1223 }, 1224 }; 1225 1226 static const struct freq_tbl ftbl_gcc_usb30_mp_mock_utmi_clk_src[] = { 1227 F(19200000, P_BI_TCXO, 1, 0, 0), 1228 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), 1229 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0), 1230 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 1231 { } 1232 }; 1233 1234 static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = { 1235 .cmd_rcgr = 0xa6034, 1236 .mnd_width = 0, 1237 .hid_width = 5, 1238 .parent_map = gcc_parent_map_0, 1239 .freq_tbl = ftbl_gcc_usb30_mp_mock_utmi_clk_src, 1240 .clkr.hw.init = &(struct clk_init_data){ 1241 .name = "gcc_usb30_mp_mock_utmi_clk_src", 1242 .parent_data = gcc_parents_0, 1243 .num_parents = ARRAY_SIZE(gcc_parents_0), 1244 .flags = CLK_SET_RATE_PARENT, 1245 .ops = &clk_rcg2_ops, 1246 }, 1247 }; 1248 1249 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1250 .cmd_rcgr = 0xf01c, 1251 .mnd_width = 8, 1252 .hid_width = 5, 1253 .parent_map = gcc_parent_map_0, 1254 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 1255 .clkr.hw.init = &(struct clk_init_data){ 1256 .name = "gcc_usb30_prim_master_clk_src", 1257 .parent_data = gcc_parents_0, 1258 .num_parents = ARRAY_SIZE(gcc_parents_0), 1259 .flags = CLK_SET_RATE_PARENT, 1260 .ops = &clk_rcg2_ops, 1261 }, 1262 }; 1263 1264 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1265 .cmd_rcgr = 0xf034, 1266 .mnd_width = 0, 1267 .hid_width = 5, 1268 .parent_map = gcc_parent_map_0, 1269 .freq_tbl = ftbl_gcc_usb30_mp_mock_utmi_clk_src, 1270 .clkr.hw.init = &(struct clk_init_data){ 1271 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1272 .parent_data = gcc_parents_0, 1273 .num_parents = ARRAY_SIZE(gcc_parents_0), 1274 .flags = CLK_SET_RATE_PARENT, 1275 .ops = &clk_rcg2_ops, 1276 }, 1277 }; 1278 1279 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { 1280 .cmd_rcgr = 0x1001c, 1281 .mnd_width = 8, 1282 .hid_width = 5, 1283 .parent_map = gcc_parent_map_0, 1284 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 1285 .clkr.hw.init = &(struct clk_init_data){ 1286 .name = "gcc_usb30_sec_master_clk_src", 1287 .parent_data = gcc_parents_0, 1288 .num_parents = ARRAY_SIZE(gcc_parents_0), 1289 .flags = CLK_SET_RATE_PARENT, 1290 .ops = &clk_rcg2_ops, 1291 }, 1292 }; 1293 1294 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { 1295 .cmd_rcgr = 0x10034, 1296 .mnd_width = 0, 1297 .hid_width = 5, 1298 .parent_map = gcc_parent_map_0, 1299 .freq_tbl = ftbl_gcc_usb30_mp_mock_utmi_clk_src, 1300 .clkr.hw.init = &(struct clk_init_data){ 1301 .name = "gcc_usb30_sec_mock_utmi_clk_src", 1302 .parent_data = gcc_parents_0, 1303 .num_parents = ARRAY_SIZE(gcc_parents_0), 1304 .flags = CLK_SET_RATE_PARENT, 1305 .ops = &clk_rcg2_ops, 1306 }, 1307 }; 1308 1309 static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = { 1310 .cmd_rcgr = 0xa6068, 1311 .mnd_width = 0, 1312 .hid_width = 5, 1313 .parent_map = gcc_parent_map_2, 1314 .freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src, 1315 .clkr.hw.init = &(struct clk_init_data){ 1316 .name = "gcc_usb3_mp_phy_aux_clk_src", 1317 .parent_data = gcc_parents_2, 1318 .num_parents = ARRAY_SIZE(gcc_parents_2), 1319 .flags = CLK_SET_RATE_PARENT, 1320 .ops = &clk_rcg2_ops, 1321 }, 1322 }; 1323 1324 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1325 .cmd_rcgr = 0xf060, 1326 .mnd_width = 0, 1327 .hid_width = 5, 1328 .parent_map = gcc_parent_map_2, 1329 .freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src, 1330 .clkr.hw.init = &(struct clk_init_data){ 1331 .name = "gcc_usb3_prim_phy_aux_clk_src", 1332 .parent_data = gcc_parents_2, 1333 .num_parents = ARRAY_SIZE(gcc_parents_2), 1334 .flags = CLK_SET_RATE_PARENT, 1335 .ops = &clk_rcg2_ops, 1336 }, 1337 }; 1338 1339 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { 1340 .cmd_rcgr = 0x10060, 1341 .mnd_width = 0, 1342 .hid_width = 5, 1343 .parent_map = gcc_parent_map_2, 1344 .freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src, 1345 .clkr.hw.init = &(struct clk_init_data){ 1346 .name = "gcc_usb3_sec_phy_aux_clk_src", 1347 .parent_data = gcc_parents_2, 1348 .num_parents = ARRAY_SIZE(gcc_parents_2), 1349 .flags = CLK_SET_RATE_PARENT, 1350 .ops = &clk_rcg2_ops, 1351 }, 1352 }; 1353 1354 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { 1355 .halt_reg = 0x90018, 1356 .halt_check = BRANCH_HALT, 1357 .clkr = { 1358 .enable_reg = 0x90018, 1359 .enable_mask = BIT(0), 1360 .hw.init = &(struct clk_init_data){ 1361 .name = "gcc_aggre_noc_pcie_tbu_clk", 1362 .ops = &clk_branch2_ops, 1363 }, 1364 }, 1365 }; 1366 1367 static struct clk_branch gcc_aggre_ufs_card_axi_clk = { 1368 .halt_reg = 0x750c0, 1369 .halt_check = BRANCH_HALT, 1370 .hwcg_reg = 0x750c0, 1371 .hwcg_bit = 1, 1372 .clkr = { 1373 .enable_reg = 0x750c0, 1374 .enable_mask = BIT(0), 1375 .hw.init = &(struct clk_init_data){ 1376 .name = "gcc_aggre_ufs_card_axi_clk", 1377 .parent_hws = (const struct clk_hw *[]){ 1378 &gcc_ufs_card_axi_clk_src.clkr.hw 1379 }, 1380 .num_parents = 1, 1381 .flags = CLK_SET_RATE_PARENT, 1382 .ops = &clk_branch2_ops, 1383 }, 1384 }, 1385 }; 1386 1387 static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = { 1388 .halt_reg = 0x750c0, 1389 .halt_check = BRANCH_HALT, 1390 .hwcg_reg = 0x750c0, 1391 .hwcg_bit = 1, 1392 .clkr = { 1393 .enable_reg = 0x750c0, 1394 .enable_mask = BIT(1), 1395 .hw.init = &(struct clk_init_data){ 1396 .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk", 1397 .parent_hws = (const struct clk_hw *[]){ 1398 &gcc_aggre_ufs_card_axi_clk.clkr.hw 1399 }, 1400 .num_parents = 1, 1401 .flags = CLK_SET_RATE_PARENT, 1402 .ops = &clk_branch_simple_ops, 1403 }, 1404 }, 1405 }; 1406 1407 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1408 .halt_reg = 0x770c0, 1409 .halt_check = BRANCH_HALT, 1410 .hwcg_reg = 0x770c0, 1411 .hwcg_bit = 1, 1412 .clkr = { 1413 .enable_reg = 0x770c0, 1414 .enable_mask = BIT(0), 1415 .hw.init = &(struct clk_init_data){ 1416 .name = "gcc_aggre_ufs_phy_axi_clk", 1417 .parent_hws = (const struct clk_hw *[]){ 1418 &gcc_ufs_phy_axi_clk_src.clkr.hw 1419 }, 1420 .num_parents = 1, 1421 .flags = CLK_SET_RATE_PARENT, 1422 .ops = &clk_branch2_ops, 1423 }, 1424 }, 1425 }; 1426 1427 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { 1428 .halt_reg = 0x770c0, 1429 .halt_check = BRANCH_HALT, 1430 .hwcg_reg = 0x770c0, 1431 .hwcg_bit = 1, 1432 .clkr = { 1433 .enable_reg = 0x770c0, 1434 .enable_mask = BIT(1), 1435 .hw.init = &(struct clk_init_data){ 1436 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", 1437 .parent_hws = (const struct clk_hw *[]){ 1438 &gcc_aggre_ufs_phy_axi_clk.clkr.hw 1439 }, 1440 .num_parents = 1, 1441 .flags = CLK_SET_RATE_PARENT, 1442 .ops = &clk_branch_simple_ops, 1443 }, 1444 }, 1445 }; 1446 1447 static struct clk_branch gcc_aggre_usb3_mp_axi_clk = { 1448 .halt_reg = 0xa6084, 1449 .halt_check = BRANCH_HALT, 1450 .clkr = { 1451 .enable_reg = 0xa6084, 1452 .enable_mask = BIT(0), 1453 .hw.init = &(struct clk_init_data){ 1454 .name = "gcc_aggre_usb3_mp_axi_clk", 1455 .parent_hws = (const struct clk_hw *[]){ 1456 &gcc_usb30_mp_master_clk_src.clkr.hw 1457 }, 1458 .num_parents = 1, 1459 .flags = CLK_SET_RATE_PARENT, 1460 .ops = &clk_branch2_ops, 1461 }, 1462 }, 1463 }; 1464 1465 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1466 .halt_reg = 0xf07c, 1467 .halt_check = BRANCH_HALT, 1468 .clkr = { 1469 .enable_reg = 0xf07c, 1470 .enable_mask = BIT(0), 1471 .hw.init = &(struct clk_init_data){ 1472 .name = "gcc_aggre_usb3_prim_axi_clk", 1473 .parent_hws = (const struct clk_hw *[]){ 1474 &gcc_usb30_prim_master_clk_src.clkr.hw 1475 }, 1476 .num_parents = 1, 1477 .flags = CLK_SET_RATE_PARENT, 1478 .ops = &clk_branch2_ops, 1479 }, 1480 }, 1481 }; 1482 1483 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { 1484 .halt_reg = 0x1007c, 1485 .halt_check = BRANCH_HALT, 1486 .clkr = { 1487 .enable_reg = 0x1007c, 1488 .enable_mask = BIT(0), 1489 .hw.init = &(struct clk_init_data){ 1490 .name = "gcc_aggre_usb3_sec_axi_clk", 1491 .parent_hws = (const struct clk_hw *[]){ 1492 &gcc_usb30_sec_master_clk_src.clkr.hw 1493 }, 1494 .num_parents = 1, 1495 .flags = CLK_SET_RATE_PARENT, 1496 .ops = &clk_branch2_ops, 1497 }, 1498 }, 1499 }; 1500 1501 static struct clk_branch gcc_boot_rom_ahb_clk = { 1502 .halt_reg = 0x38004, 1503 .halt_check = BRANCH_HALT_VOTED, 1504 .hwcg_reg = 0x38004, 1505 .hwcg_bit = 1, 1506 .clkr = { 1507 .enable_reg = 0x52004, 1508 .enable_mask = BIT(10), 1509 .hw.init = &(struct clk_init_data){ 1510 .name = "gcc_boot_rom_ahb_clk", 1511 .ops = &clk_branch2_ops, 1512 }, 1513 }, 1514 }; 1515 1516 static struct clk_branch gcc_camera_hf_axi_clk = { 1517 .halt_reg = 0xb030, 1518 .halt_check = BRANCH_HALT, 1519 .clkr = { 1520 .enable_reg = 0xb030, 1521 .enable_mask = BIT(0), 1522 .hw.init = &(struct clk_init_data){ 1523 .name = "gcc_camera_hf_axi_clk", 1524 .ops = &clk_branch2_ops, 1525 }, 1526 }, 1527 }; 1528 1529 static struct clk_branch gcc_camera_sf_axi_clk = { 1530 .halt_reg = 0xb034, 1531 .halt_check = BRANCH_HALT, 1532 .clkr = { 1533 .enable_reg = 0xb034, 1534 .enable_mask = BIT(0), 1535 .hw.init = &(struct clk_init_data){ 1536 .name = "gcc_camera_sf_axi_clk", 1537 .ops = &clk_branch2_ops, 1538 }, 1539 }, 1540 }; 1541 1542 static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = { 1543 .halt_reg = 0xa609c, 1544 .halt_check = BRANCH_HALT, 1545 .clkr = { 1546 .enable_reg = 0xa609c, 1547 .enable_mask = BIT(0), 1548 .hw.init = &(struct clk_init_data){ 1549 .name = "gcc_cfg_noc_usb3_mp_axi_clk", 1550 .parent_hws = (const struct clk_hw *[]){ 1551 &gcc_usb30_mp_master_clk_src.clkr.hw 1552 }, 1553 .num_parents = 1, 1554 .flags = CLK_SET_RATE_PARENT, 1555 .ops = &clk_branch2_ops, 1556 }, 1557 }, 1558 }; 1559 1560 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1561 .halt_reg = 0xf078, 1562 .halt_check = BRANCH_HALT, 1563 .clkr = { 1564 .enable_reg = 0xf078, 1565 .enable_mask = BIT(0), 1566 .hw.init = &(struct clk_init_data){ 1567 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1568 .parent_hws = (const struct clk_hw *[]){ 1569 &gcc_usb30_prim_master_clk_src.clkr.hw 1570 }, 1571 .num_parents = 1, 1572 .flags = CLK_SET_RATE_PARENT, 1573 .ops = &clk_branch2_ops, 1574 }, 1575 }, 1576 }; 1577 1578 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { 1579 .halt_reg = 0x10078, 1580 .halt_check = BRANCH_HALT, 1581 .clkr = { 1582 .enable_reg = 0x10078, 1583 .enable_mask = BIT(0), 1584 .hw.init = &(struct clk_init_data){ 1585 .name = "gcc_cfg_noc_usb3_sec_axi_clk", 1586 .parent_hws = (const struct clk_hw *[]){ 1587 &gcc_usb30_sec_master_clk_src.clkr.hw 1588 }, 1589 .num_parents = 1, 1590 .flags = CLK_SET_RATE_PARENT, 1591 .ops = &clk_branch2_ops, 1592 }, 1593 }, 1594 }; 1595 1596 static struct clk_branch gcc_cpuss_rbcpr_clk = { 1597 .halt_reg = 0x48008, 1598 .halt_check = BRANCH_HALT, 1599 .clkr = { 1600 .enable_reg = 0x48008, 1601 .enable_mask = BIT(0), 1602 .hw.init = &(struct clk_init_data){ 1603 .name = "gcc_cpuss_rbcpr_clk", 1604 .ops = &clk_branch2_ops, 1605 }, 1606 }, 1607 }; 1608 1609 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1610 .halt_reg = 0x71154, 1611 .halt_check = BRANCH_VOTED, 1612 .clkr = { 1613 .enable_reg = 0x71154, 1614 .enable_mask = BIT(0), 1615 .hw.init = &(struct clk_init_data){ 1616 .name = "gcc_ddrss_gpu_axi_clk", 1617 .ops = &clk_branch2_ops, 1618 }, 1619 }, 1620 }; 1621 1622 static struct clk_branch gcc_disp_hf_axi_clk = { 1623 .halt_reg = 0xb038, 1624 .halt_check = BRANCH_HALT, 1625 .clkr = { 1626 .enable_reg = 0xb038, 1627 .enable_mask = BIT(0), 1628 .hw.init = &(struct clk_init_data){ 1629 .name = "gcc_disp_hf_axi_clk", 1630 .ops = &clk_branch2_ops, 1631 }, 1632 }, 1633 }; 1634 1635 static struct clk_branch gcc_disp_sf_axi_clk = { 1636 .halt_reg = 0xb03c, 1637 .halt_check = BRANCH_HALT, 1638 .clkr = { 1639 .enable_reg = 0xb03c, 1640 .enable_mask = BIT(0), 1641 .hw.init = &(struct clk_init_data){ 1642 .name = "gcc_disp_sf_axi_clk", 1643 .ops = &clk_branch2_ops, 1644 }, 1645 }, 1646 }; 1647 1648 static struct clk_branch gcc_emac_axi_clk = { 1649 .halt_reg = 0x6010, 1650 .halt_check = BRANCH_HALT, 1651 .clkr = { 1652 .enable_reg = 0x6010, 1653 .enable_mask = BIT(0), 1654 .hw.init = &(struct clk_init_data){ 1655 .name = "gcc_emac_axi_clk", 1656 .ops = &clk_branch2_ops, 1657 }, 1658 }, 1659 }; 1660 1661 static struct clk_branch gcc_emac_ptp_clk = { 1662 .halt_reg = 0x6034, 1663 .halt_check = BRANCH_HALT, 1664 .clkr = { 1665 .enable_reg = 0x6034, 1666 .enable_mask = BIT(0), 1667 .hw.init = &(struct clk_init_data){ 1668 .name = "gcc_emac_ptp_clk", 1669 .parent_hws = (const struct clk_hw *[]){ 1670 &gcc_emac_ptp_clk_src.clkr.hw 1671 }, 1672 .num_parents = 1, 1673 .flags = CLK_SET_RATE_PARENT, 1674 .ops = &clk_branch2_ops, 1675 }, 1676 }, 1677 }; 1678 1679 static struct clk_branch gcc_emac_rgmii_clk = { 1680 .halt_reg = 0x6018, 1681 .halt_check = BRANCH_HALT, 1682 .clkr = { 1683 .enable_reg = 0x6018, 1684 .enable_mask = BIT(0), 1685 .hw.init = &(struct clk_init_data){ 1686 .name = "gcc_emac_rgmii_clk", 1687 .parent_hws = (const struct clk_hw *[]){ 1688 &gcc_emac_rgmii_clk_src.clkr.hw 1689 }, 1690 .num_parents = 1, 1691 .flags = CLK_SET_RATE_PARENT, 1692 .ops = &clk_branch2_ops, 1693 }, 1694 }, 1695 }; 1696 1697 static struct clk_branch gcc_emac_slv_ahb_clk = { 1698 .halt_reg = 0x6014, 1699 .halt_check = BRANCH_HALT, 1700 .hwcg_reg = 0x6014, 1701 .hwcg_bit = 1, 1702 .clkr = { 1703 .enable_reg = 0x6014, 1704 .enable_mask = BIT(0), 1705 .hw.init = &(struct clk_init_data){ 1706 .name = "gcc_emac_slv_ahb_clk", 1707 .ops = &clk_branch2_ops, 1708 }, 1709 }, 1710 }; 1711 1712 static struct clk_branch gcc_gp1_clk = { 1713 .halt_reg = 0x64000, 1714 .halt_check = BRANCH_HALT, 1715 .clkr = { 1716 .enable_reg = 0x64000, 1717 .enable_mask = BIT(0), 1718 .hw.init = &(struct clk_init_data){ 1719 .name = "gcc_gp1_clk", 1720 .parent_hws = (const struct clk_hw *[]){ 1721 &gcc_gp1_clk_src.clkr.hw 1722 }, 1723 .num_parents = 1, 1724 .flags = CLK_SET_RATE_PARENT, 1725 .ops = &clk_branch2_ops, 1726 }, 1727 }, 1728 }; 1729 1730 static struct clk_branch gcc_gp2_clk = { 1731 .halt_reg = 0x65000, 1732 .halt_check = BRANCH_HALT, 1733 .clkr = { 1734 .enable_reg = 0x65000, 1735 .enable_mask = BIT(0), 1736 .hw.init = &(struct clk_init_data){ 1737 .name = "gcc_gp2_clk", 1738 .parent_hws = (const struct clk_hw *[]){ 1739 &gcc_gp2_clk_src.clkr.hw 1740 }, 1741 .num_parents = 1, 1742 .flags = CLK_SET_RATE_PARENT, 1743 .ops = &clk_branch2_ops, 1744 }, 1745 }, 1746 }; 1747 1748 static struct clk_branch gcc_gp3_clk = { 1749 .halt_reg = 0x66000, 1750 .halt_check = BRANCH_HALT, 1751 .clkr = { 1752 .enable_reg = 0x66000, 1753 .enable_mask = BIT(0), 1754 .hw.init = &(struct clk_init_data){ 1755 .name = "gcc_gp3_clk", 1756 .parent_hws = (const struct clk_hw *[]){ 1757 &gcc_gp3_clk_src.clkr.hw 1758 }, 1759 .num_parents = 1, 1760 .flags = CLK_SET_RATE_PARENT, 1761 .ops = &clk_branch2_ops, 1762 }, 1763 }, 1764 }; 1765 1766 static struct clk_branch gcc_gp4_clk = { 1767 .halt_reg = 0xbe000, 1768 .halt_check = BRANCH_HALT, 1769 .clkr = { 1770 .enable_reg = 0xbe000, 1771 .enable_mask = BIT(0), 1772 .hw.init = &(struct clk_init_data){ 1773 .name = "gcc_gp4_clk", 1774 .parent_hws = (const struct clk_hw *[]){ 1775 &gcc_gp4_clk_src.clkr.hw 1776 }, 1777 .num_parents = 1, 1778 .flags = CLK_SET_RATE_PARENT, 1779 .ops = &clk_branch2_ops, 1780 }, 1781 }, 1782 }; 1783 1784 static struct clk_branch gcc_gp5_clk = { 1785 .halt_reg = 0xbf000, 1786 .halt_check = BRANCH_HALT, 1787 .clkr = { 1788 .enable_reg = 0xbf000, 1789 .enable_mask = BIT(0), 1790 .hw.init = &(struct clk_init_data){ 1791 .name = "gcc_gp5_clk", 1792 .parent_hws = (const struct clk_hw *[]){ 1793 &gcc_gp5_clk_src.clkr.hw 1794 }, 1795 .num_parents = 1, 1796 .flags = CLK_SET_RATE_PARENT, 1797 .ops = &clk_branch2_ops, 1798 }, 1799 }, 1800 }; 1801 1802 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1803 .halt_check = BRANCH_HALT_DELAY, 1804 .clkr = { 1805 .enable_reg = 0x52004, 1806 .enable_mask = BIT(15), 1807 .hw.init = &(struct clk_init_data){ 1808 .name = "gcc_gpu_gpll0_clk_src", 1809 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 1810 .num_parents = 1, 1811 .flags = CLK_SET_RATE_PARENT, 1812 .ops = &clk_branch2_ops, 1813 }, 1814 }, 1815 }; 1816 1817 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1818 .halt_check = BRANCH_HALT_DELAY, 1819 .clkr = { 1820 .enable_reg = 0x52004, 1821 .enable_mask = BIT(16), 1822 .hw.init = &(struct clk_init_data){ 1823 .name = "gcc_gpu_gpll0_div_clk_src", 1824 .parent_hws = (const struct clk_hw *[]){ 1825 &gpll0_out_even.clkr.hw 1826 }, 1827 .num_parents = 1, 1828 .flags = CLK_SET_RATE_PARENT, 1829 .ops = &clk_branch2_ops, 1830 }, 1831 }, 1832 }; 1833 1834 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1835 .halt_reg = 0x7100c, 1836 .halt_check = BRANCH_VOTED, 1837 .clkr = { 1838 .enable_reg = 0x7100c, 1839 .enable_mask = BIT(0), 1840 .hw.init = &(struct clk_init_data){ 1841 .name = "gcc_gpu_memnoc_gfx_clk", 1842 .ops = &clk_branch2_ops, 1843 }, 1844 }, 1845 }; 1846 1847 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1848 .halt_reg = 0x71018, 1849 .halt_check = BRANCH_HALT, 1850 .clkr = { 1851 .enable_reg = 0x71018, 1852 .enable_mask = BIT(0), 1853 .hw.init = &(struct clk_init_data){ 1854 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1855 .ops = &clk_branch2_ops, 1856 }, 1857 }, 1858 }; 1859 1860 static struct clk_branch gcc_npu_at_clk = { 1861 .halt_reg = 0x4d010, 1862 .halt_check = BRANCH_VOTED, 1863 .clkr = { 1864 .enable_reg = 0x4d010, 1865 .enable_mask = BIT(0), 1866 .hw.init = &(struct clk_init_data){ 1867 .name = "gcc_npu_at_clk", 1868 .ops = &clk_branch2_ops, 1869 }, 1870 }, 1871 }; 1872 1873 static struct clk_branch gcc_npu_axi_clk = { 1874 .halt_reg = 0x4d008, 1875 .halt_check = BRANCH_VOTED, 1876 .clkr = { 1877 .enable_reg = 0x4d008, 1878 .enable_mask = BIT(0), 1879 .hw.init = &(struct clk_init_data){ 1880 .name = "gcc_npu_axi_clk", 1881 .parent_hws = (const struct clk_hw *[]){ 1882 &gcc_npu_axi_clk_src.clkr.hw 1883 }, 1884 .num_parents = 1, 1885 .flags = CLK_SET_RATE_PARENT, 1886 .ops = &clk_branch2_ops, 1887 }, 1888 }, 1889 }; 1890 1891 static struct clk_branch gcc_npu_gpll0_clk_src = { 1892 .halt_check = BRANCH_HALT_DELAY, 1893 .clkr = { 1894 .enable_reg = 0x52004, 1895 .enable_mask = BIT(18), 1896 .hw.init = &(struct clk_init_data){ 1897 .name = "gcc_npu_gpll0_clk_src", 1898 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 1899 .num_parents = 1, 1900 .flags = CLK_SET_RATE_PARENT, 1901 .ops = &clk_branch2_ops, 1902 }, 1903 }, 1904 }; 1905 1906 static struct clk_branch gcc_npu_gpll0_div_clk_src = { 1907 .halt_check = BRANCH_HALT_DELAY, 1908 .clkr = { 1909 .enable_reg = 0x52004, 1910 .enable_mask = BIT(19), 1911 .hw.init = &(struct clk_init_data){ 1912 .name = "gcc_npu_gpll0_div_clk_src", 1913 .parent_hws = (const struct clk_hw *[]){ 1914 &gpll0_out_even.clkr.hw 1915 }, 1916 .num_parents = 1, 1917 .flags = CLK_SET_RATE_PARENT, 1918 .ops = &clk_branch2_ops, 1919 }, 1920 }, 1921 }; 1922 1923 static struct clk_branch gcc_npu_trig_clk = { 1924 .halt_reg = 0x4d00c, 1925 .halt_check = BRANCH_VOTED, 1926 .clkr = { 1927 .enable_reg = 0x4d00c, 1928 .enable_mask = BIT(0), 1929 .hw.init = &(struct clk_init_data){ 1930 .name = "gcc_npu_trig_clk", 1931 .ops = &clk_branch2_ops, 1932 }, 1933 }, 1934 }; 1935 1936 static struct clk_branch gcc_pcie0_phy_refgen_clk = { 1937 .halt_reg = 0x6f02c, 1938 .halt_check = BRANCH_HALT, 1939 .clkr = { 1940 .enable_reg = 0x6f02c, 1941 .enable_mask = BIT(0), 1942 .hw.init = &(struct clk_init_data){ 1943 .name = "gcc_pcie0_phy_refgen_clk", 1944 .parent_hws = (const struct clk_hw *[]){ 1945 &gcc_pcie_phy_refgen_clk_src.clkr.hw 1946 }, 1947 .num_parents = 1, 1948 .flags = CLK_SET_RATE_PARENT, 1949 .ops = &clk_branch2_ops, 1950 }, 1951 }, 1952 }; 1953 1954 static struct clk_branch gcc_pcie1_phy_refgen_clk = { 1955 .halt_reg = 0x6f030, 1956 .halt_check = BRANCH_HALT, 1957 .clkr = { 1958 .enable_reg = 0x6f030, 1959 .enable_mask = BIT(0), 1960 .hw.init = &(struct clk_init_data){ 1961 .name = "gcc_pcie1_phy_refgen_clk", 1962 .parent_hws = (const struct clk_hw *[]){ 1963 &gcc_pcie_phy_refgen_clk_src.clkr.hw 1964 }, 1965 .num_parents = 1, 1966 .flags = CLK_SET_RATE_PARENT, 1967 .ops = &clk_branch2_ops, 1968 }, 1969 }, 1970 }; 1971 1972 static struct clk_branch gcc_pcie2_phy_refgen_clk = { 1973 .halt_reg = 0x6f034, 1974 .halt_check = BRANCH_HALT, 1975 .clkr = { 1976 .enable_reg = 0x6f034, 1977 .enable_mask = BIT(0), 1978 .hw.init = &(struct clk_init_data){ 1979 .name = "gcc_pcie2_phy_refgen_clk", 1980 .parent_hws = (const struct clk_hw *[]){ 1981 &gcc_pcie_phy_refgen_clk_src.clkr.hw 1982 }, 1983 .num_parents = 1, 1984 .flags = CLK_SET_RATE_PARENT, 1985 .ops = &clk_branch2_ops, 1986 }, 1987 }, 1988 }; 1989 1990 static struct clk_branch gcc_pcie3_phy_refgen_clk = { 1991 .halt_reg = 0x6f038, 1992 .halt_check = BRANCH_HALT, 1993 .clkr = { 1994 .enable_reg = 0x6f038, 1995 .enable_mask = BIT(0), 1996 .hw.init = &(struct clk_init_data){ 1997 .name = "gcc_pcie3_phy_refgen_clk", 1998 .parent_hws = (const struct clk_hw *[]){ 1999 &gcc_pcie_phy_refgen_clk_src.clkr.hw 2000 }, 2001 .num_parents = 1, 2002 .flags = CLK_SET_RATE_PARENT, 2003 .ops = &clk_branch2_ops, 2004 }, 2005 }, 2006 }; 2007 2008 static struct clk_branch gcc_pcie_0_aux_clk = { 2009 .halt_reg = 0x6b020, 2010 .halt_check = BRANCH_HALT_VOTED, 2011 .clkr = { 2012 .enable_reg = 0x5200c, 2013 .enable_mask = BIT(3), 2014 .hw.init = &(struct clk_init_data){ 2015 .name = "gcc_pcie_0_aux_clk", 2016 .parent_hws = (const struct clk_hw *[]){ 2017 &gcc_pcie_0_aux_clk_src.clkr.hw 2018 }, 2019 .num_parents = 1, 2020 .flags = CLK_SET_RATE_PARENT, 2021 .ops = &clk_branch2_ops, 2022 }, 2023 }, 2024 }; 2025 2026 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 2027 .halt_reg = 0x6b01c, 2028 .halt_check = BRANCH_HALT_VOTED, 2029 .hwcg_reg = 0x6b01c, 2030 .hwcg_bit = 1, 2031 .clkr = { 2032 .enable_reg = 0x5200c, 2033 .enable_mask = BIT(2), 2034 .hw.init = &(struct clk_init_data){ 2035 .name = "gcc_pcie_0_cfg_ahb_clk", 2036 .ops = &clk_branch2_ops, 2037 }, 2038 }, 2039 }; 2040 2041 static struct clk_branch gcc_pcie_0_clkref_clk = { 2042 .halt_reg = 0x8c00c, 2043 .halt_check = BRANCH_HALT, 2044 .clkr = { 2045 .enable_reg = 0x8c00c, 2046 .enable_mask = BIT(0), 2047 .hw.init = &(struct clk_init_data){ 2048 .name = "gcc_pcie_0_clkref_clk", 2049 .ops = &clk_branch2_ops, 2050 }, 2051 }, 2052 }; 2053 2054 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 2055 .halt_reg = 0x6b018, 2056 .halt_check = BRANCH_HALT_VOTED, 2057 .clkr = { 2058 .enable_reg = 0x5200c, 2059 .enable_mask = BIT(1), 2060 .hw.init = &(struct clk_init_data){ 2061 .name = "gcc_pcie_0_mstr_axi_clk", 2062 .ops = &clk_branch2_ops, 2063 }, 2064 }, 2065 }; 2066 2067 static struct clk_branch gcc_pcie_0_pipe_clk = { 2068 .halt_reg = 0x6b024, 2069 .halt_check = BRANCH_HALT_SKIP, 2070 .clkr = { 2071 .enable_reg = 0x5200c, 2072 .enable_mask = BIT(4), 2073 .hw.init = &(struct clk_init_data){ 2074 .name = "gcc_pcie_0_pipe_clk", 2075 .ops = &clk_branch2_ops, 2076 }, 2077 }, 2078 }; 2079 2080 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 2081 .halt_reg = 0x6b014, 2082 .halt_check = BRANCH_HALT_VOTED, 2083 .hwcg_reg = 0x6b014, 2084 .hwcg_bit = 1, 2085 .clkr = { 2086 .enable_reg = 0x5200c, 2087 .enable_mask = BIT(0), 2088 .hw.init = &(struct clk_init_data){ 2089 .name = "gcc_pcie_0_slv_axi_clk", 2090 .ops = &clk_branch2_ops, 2091 }, 2092 }, 2093 }; 2094 2095 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 2096 .halt_reg = 0x6b010, 2097 .halt_check = BRANCH_HALT_VOTED, 2098 .clkr = { 2099 .enable_reg = 0x5200c, 2100 .enable_mask = BIT(5), 2101 .hw.init = &(struct clk_init_data){ 2102 .name = "gcc_pcie_0_slv_q2a_axi_clk", 2103 .ops = &clk_branch2_ops, 2104 }, 2105 }, 2106 }; 2107 2108 static struct clk_branch gcc_pcie_1_aux_clk = { 2109 .halt_reg = 0x8d020, 2110 .halt_check = BRANCH_HALT_VOTED, 2111 .clkr = { 2112 .enable_reg = 0x52004, 2113 .enable_mask = BIT(29), 2114 .hw.init = &(struct clk_init_data){ 2115 .name = "gcc_pcie_1_aux_clk", 2116 .parent_hws = (const struct clk_hw *[]){ 2117 &gcc_pcie_1_aux_clk_src.clkr.hw 2118 }, 2119 .num_parents = 1, 2120 .flags = CLK_SET_RATE_PARENT, 2121 .ops = &clk_branch2_ops, 2122 }, 2123 }, 2124 }; 2125 2126 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 2127 .halt_reg = 0x8d01c, 2128 .halt_check = BRANCH_HALT_VOTED, 2129 .hwcg_reg = 0x8d01c, 2130 .hwcg_bit = 1, 2131 .clkr = { 2132 .enable_reg = 0x52004, 2133 .enable_mask = BIT(28), 2134 .hw.init = &(struct clk_init_data){ 2135 .name = "gcc_pcie_1_cfg_ahb_clk", 2136 .ops = &clk_branch2_ops, 2137 }, 2138 }, 2139 }; 2140 2141 static struct clk_branch gcc_pcie_1_clkref_clk = { 2142 .halt_reg = 0x8c02c, 2143 .halt_check = BRANCH_HALT, 2144 .clkr = { 2145 .enable_reg = 0x8c02c, 2146 .enable_mask = BIT(0), 2147 .hw.init = &(struct clk_init_data){ 2148 .name = "gcc_pcie_1_clkref_clk", 2149 .ops = &clk_branch2_ops, 2150 }, 2151 }, 2152 }; 2153 2154 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 2155 .halt_reg = 0x8d018, 2156 .halt_check = BRANCH_HALT_VOTED, 2157 .clkr = { 2158 .enable_reg = 0x52004, 2159 .enable_mask = BIT(27), 2160 .hw.init = &(struct clk_init_data){ 2161 .name = "gcc_pcie_1_mstr_axi_clk", 2162 .ops = &clk_branch2_ops, 2163 }, 2164 }, 2165 }; 2166 2167 static struct clk_branch gcc_pcie_1_pipe_clk = { 2168 .halt_reg = 0x8d024, 2169 .halt_check = BRANCH_HALT_SKIP, 2170 .clkr = { 2171 .enable_reg = 0x52004, 2172 .enable_mask = BIT(30), 2173 .hw.init = &(struct clk_init_data){ 2174 .name = "gcc_pcie_1_pipe_clk", 2175 .ops = &clk_branch2_ops, 2176 }, 2177 }, 2178 }; 2179 2180 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 2181 .halt_reg = 0x8d014, 2182 .halt_check = BRANCH_HALT_VOTED, 2183 .hwcg_reg = 0x8d014, 2184 .hwcg_bit = 1, 2185 .clkr = { 2186 .enable_reg = 0x52004, 2187 .enable_mask = BIT(26), 2188 .hw.init = &(struct clk_init_data){ 2189 .name = "gcc_pcie_1_slv_axi_clk", 2190 .ops = &clk_branch2_ops, 2191 }, 2192 }, 2193 }; 2194 2195 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 2196 .halt_reg = 0x8d010, 2197 .halt_check = BRANCH_HALT_VOTED, 2198 .clkr = { 2199 .enable_reg = 0x52004, 2200 .enable_mask = BIT(25), 2201 .hw.init = &(struct clk_init_data){ 2202 .name = "gcc_pcie_1_slv_q2a_axi_clk", 2203 .ops = &clk_branch2_ops, 2204 }, 2205 }, 2206 }; 2207 2208 static struct clk_branch gcc_pcie_2_aux_clk = { 2209 .halt_reg = 0x9d020, 2210 .halt_check = BRANCH_HALT_VOTED, 2211 .clkr = { 2212 .enable_reg = 0x52014, 2213 .enable_mask = BIT(14), 2214 .hw.init = &(struct clk_init_data){ 2215 .name = "gcc_pcie_2_aux_clk", 2216 .parent_hws = (const struct clk_hw *[]){ 2217 &gcc_pcie_2_aux_clk_src.clkr.hw 2218 }, 2219 .num_parents = 1, 2220 .flags = CLK_SET_RATE_PARENT, 2221 .ops = &clk_branch2_ops, 2222 }, 2223 }, 2224 }; 2225 2226 static struct clk_branch gcc_pcie_2_cfg_ahb_clk = { 2227 .halt_reg = 0x9d01c, 2228 .halt_check = BRANCH_HALT_VOTED, 2229 .hwcg_reg = 0x9d01c, 2230 .hwcg_bit = 1, 2231 .clkr = { 2232 .enable_reg = 0x52014, 2233 .enable_mask = BIT(13), 2234 .hw.init = &(struct clk_init_data){ 2235 .name = "gcc_pcie_2_cfg_ahb_clk", 2236 .ops = &clk_branch2_ops, 2237 }, 2238 }, 2239 }; 2240 2241 static struct clk_branch gcc_pcie_2_clkref_clk = { 2242 .halt_reg = 0x8c014, 2243 .halt_check = BRANCH_HALT, 2244 .clkr = { 2245 .enable_reg = 0x8c014, 2246 .enable_mask = BIT(0), 2247 .hw.init = &(struct clk_init_data){ 2248 .name = "gcc_pcie_2_clkref_clk", 2249 .ops = &clk_branch2_ops, 2250 }, 2251 }, 2252 }; 2253 2254 static struct clk_branch gcc_pcie_2_mstr_axi_clk = { 2255 .halt_reg = 0x9d018, 2256 .halt_check = BRANCH_HALT_VOTED, 2257 .clkr = { 2258 .enable_reg = 0x52014, 2259 .enable_mask = BIT(12), 2260 .hw.init = &(struct clk_init_data){ 2261 .name = "gcc_pcie_2_mstr_axi_clk", 2262 .ops = &clk_branch2_ops, 2263 }, 2264 }, 2265 }; 2266 2267 static struct clk_branch gcc_pcie_2_pipe_clk = { 2268 .halt_reg = 0x9d024, 2269 .halt_check = BRANCH_HALT_SKIP, 2270 .clkr = { 2271 .enable_reg = 0x52014, 2272 .enable_mask = BIT(15), 2273 .hw.init = &(struct clk_init_data){ 2274 .name = "gcc_pcie_2_pipe_clk", 2275 .ops = &clk_branch2_ops, 2276 }, 2277 }, 2278 }; 2279 2280 static struct clk_branch gcc_pcie_2_slv_axi_clk = { 2281 .halt_reg = 0x9d014, 2282 .halt_check = BRANCH_HALT_VOTED, 2283 .hwcg_reg = 0x9d014, 2284 .hwcg_bit = 1, 2285 .clkr = { 2286 .enable_reg = 0x52014, 2287 .enable_mask = BIT(11), 2288 .hw.init = &(struct clk_init_data){ 2289 .name = "gcc_pcie_2_slv_axi_clk", 2290 .ops = &clk_branch2_ops, 2291 }, 2292 }, 2293 }; 2294 2295 static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = { 2296 .halt_reg = 0x9d010, 2297 .halt_check = BRANCH_HALT_VOTED, 2298 .clkr = { 2299 .enable_reg = 0x52014, 2300 .enable_mask = BIT(10), 2301 .hw.init = &(struct clk_init_data){ 2302 .name = "gcc_pcie_2_slv_q2a_axi_clk", 2303 .ops = &clk_branch2_ops, 2304 }, 2305 }, 2306 }; 2307 2308 static struct clk_branch gcc_pcie_3_aux_clk = { 2309 .halt_reg = 0xa3020, 2310 .halt_check = BRANCH_HALT_VOTED, 2311 .clkr = { 2312 .enable_reg = 0x52014, 2313 .enable_mask = BIT(20), 2314 .hw.init = &(struct clk_init_data){ 2315 .name = "gcc_pcie_3_aux_clk", 2316 .parent_hws = (const struct clk_hw *[]){ 2317 &gcc_pcie_3_aux_clk_src.clkr.hw 2318 }, 2319 .num_parents = 1, 2320 .flags = CLK_SET_RATE_PARENT, 2321 .ops = &clk_branch2_ops, 2322 }, 2323 }, 2324 }; 2325 2326 static struct clk_branch gcc_pcie_3_cfg_ahb_clk = { 2327 .halt_reg = 0xa301c, 2328 .halt_check = BRANCH_HALT_VOTED, 2329 .hwcg_reg = 0xa301c, 2330 .hwcg_bit = 1, 2331 .clkr = { 2332 .enable_reg = 0x52014, 2333 .enable_mask = BIT(19), 2334 .hw.init = &(struct clk_init_data){ 2335 .name = "gcc_pcie_3_cfg_ahb_clk", 2336 .ops = &clk_branch2_ops, 2337 }, 2338 }, 2339 }; 2340 2341 static struct clk_branch gcc_pcie_3_clkref_clk = { 2342 .halt_reg = 0x8c018, 2343 .halt_check = BRANCH_HALT, 2344 .clkr = { 2345 .enable_reg = 0x8c018, 2346 .enable_mask = BIT(0), 2347 .hw.init = &(struct clk_init_data){ 2348 .name = "gcc_pcie_3_clkref_clk", 2349 .ops = &clk_branch2_ops, 2350 }, 2351 }, 2352 }; 2353 2354 static struct clk_branch gcc_pcie_3_mstr_axi_clk = { 2355 .halt_reg = 0xa3018, 2356 .halt_check = BRANCH_HALT_VOTED, 2357 .clkr = { 2358 .enable_reg = 0x52014, 2359 .enable_mask = BIT(18), 2360 .hw.init = &(struct clk_init_data){ 2361 .name = "gcc_pcie_3_mstr_axi_clk", 2362 .ops = &clk_branch2_ops, 2363 }, 2364 }, 2365 }; 2366 2367 static struct clk_branch gcc_pcie_3_pipe_clk = { 2368 .halt_reg = 0xa3024, 2369 .halt_check = BRANCH_HALT_SKIP, 2370 .clkr = { 2371 .enable_reg = 0x52014, 2372 .enable_mask = BIT(21), 2373 .hw.init = &(struct clk_init_data){ 2374 .name = "gcc_pcie_3_pipe_clk", 2375 .ops = &clk_branch2_ops, 2376 }, 2377 }, 2378 }; 2379 2380 static struct clk_branch gcc_pcie_3_slv_axi_clk = { 2381 .halt_reg = 0xa3014, 2382 .halt_check = BRANCH_HALT_VOTED, 2383 .hwcg_reg = 0xa3014, 2384 .hwcg_bit = 1, 2385 .clkr = { 2386 .enable_reg = 0x52014, 2387 .enable_mask = BIT(17), 2388 .hw.init = &(struct clk_init_data){ 2389 .name = "gcc_pcie_3_slv_axi_clk", 2390 .ops = &clk_branch2_ops, 2391 }, 2392 }, 2393 }; 2394 2395 static struct clk_branch gcc_pcie_3_slv_q2a_axi_clk = { 2396 .halt_reg = 0xa3010, 2397 .halt_check = BRANCH_HALT_VOTED, 2398 .clkr = { 2399 .enable_reg = 0x52014, 2400 .enable_mask = BIT(16), 2401 .hw.init = &(struct clk_init_data){ 2402 .name = "gcc_pcie_3_slv_q2a_axi_clk", 2403 .ops = &clk_branch2_ops, 2404 }, 2405 }, 2406 }; 2407 2408 static struct clk_branch gcc_pcie_phy_aux_clk = { 2409 .halt_reg = 0x6f004, 2410 .halt_check = BRANCH_HALT, 2411 .clkr = { 2412 .enable_reg = 0x6f004, 2413 .enable_mask = BIT(0), 2414 .hw.init = &(struct clk_init_data){ 2415 .name = "gcc_pcie_phy_aux_clk", 2416 .parent_hws = (const struct clk_hw *[]){ 2417 &gcc_pcie_0_aux_clk_src.clkr.hw 2418 }, 2419 .num_parents = 1, 2420 .flags = CLK_SET_RATE_PARENT, 2421 .ops = &clk_branch2_ops, 2422 }, 2423 }, 2424 }; 2425 2426 static struct clk_branch gcc_pdm2_clk = { 2427 .halt_reg = 0x3300c, 2428 .halt_check = BRANCH_HALT, 2429 .clkr = { 2430 .enable_reg = 0x3300c, 2431 .enable_mask = BIT(0), 2432 .hw.init = &(struct clk_init_data){ 2433 .name = "gcc_pdm2_clk", 2434 .parent_hws = (const struct clk_hw *[]){ 2435 &gcc_pdm2_clk_src.clkr.hw 2436 }, 2437 .num_parents = 1, 2438 .flags = CLK_SET_RATE_PARENT, 2439 .ops = &clk_branch2_ops, 2440 }, 2441 }, 2442 }; 2443 2444 static struct clk_branch gcc_pdm_ahb_clk = { 2445 .halt_reg = 0x33004, 2446 .halt_check = BRANCH_HALT, 2447 .hwcg_reg = 0x33004, 2448 .hwcg_bit = 1, 2449 .clkr = { 2450 .enable_reg = 0x33004, 2451 .enable_mask = BIT(0), 2452 .hw.init = &(struct clk_init_data){ 2453 .name = "gcc_pdm_ahb_clk", 2454 .ops = &clk_branch2_ops, 2455 }, 2456 }, 2457 }; 2458 2459 static struct clk_branch gcc_pdm_xo4_clk = { 2460 .halt_reg = 0x33008, 2461 .halt_check = BRANCH_HALT, 2462 .clkr = { 2463 .enable_reg = 0x33008, 2464 .enable_mask = BIT(0), 2465 .hw.init = &(struct clk_init_data){ 2466 .name = "gcc_pdm_xo4_clk", 2467 .ops = &clk_branch2_ops, 2468 }, 2469 }, 2470 }; 2471 2472 static struct clk_branch gcc_prng_ahb_clk = { 2473 .halt_reg = 0x34004, 2474 .halt_check = BRANCH_HALT_VOTED, 2475 .clkr = { 2476 .enable_reg = 0x52004, 2477 .enable_mask = BIT(13), 2478 .hw.init = &(struct clk_init_data){ 2479 .name = "gcc_prng_ahb_clk", 2480 .ops = &clk_branch2_ops, 2481 }, 2482 }, 2483 }; 2484 2485 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2486 .halt_reg = 0xb018, 2487 .halt_check = BRANCH_HALT, 2488 .hwcg_reg = 0xb018, 2489 .hwcg_bit = 1, 2490 .clkr = { 2491 .enable_reg = 0xb018, 2492 .enable_mask = BIT(0), 2493 .hw.init = &(struct clk_init_data){ 2494 .name = "gcc_qmip_camera_nrt_ahb_clk", 2495 .ops = &clk_branch2_ops, 2496 }, 2497 }, 2498 }; 2499 2500 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2501 .halt_reg = 0xb01c, 2502 .halt_check = BRANCH_HALT, 2503 .hwcg_reg = 0xb01c, 2504 .hwcg_bit = 1, 2505 .clkr = { 2506 .enable_reg = 0xb01c, 2507 .enable_mask = BIT(0), 2508 .hw.init = &(struct clk_init_data){ 2509 .name = "gcc_qmip_camera_rt_ahb_clk", 2510 .ops = &clk_branch2_ops, 2511 }, 2512 }, 2513 }; 2514 2515 static struct clk_branch gcc_qmip_disp_ahb_clk = { 2516 .halt_reg = 0xb020, 2517 .halt_check = BRANCH_HALT, 2518 .hwcg_reg = 0xb020, 2519 .hwcg_bit = 1, 2520 .clkr = { 2521 .enable_reg = 0xb020, 2522 .enable_mask = BIT(0), 2523 .hw.init = &(struct clk_init_data){ 2524 .name = "gcc_qmip_disp_ahb_clk", 2525 .ops = &clk_branch2_ops, 2526 }, 2527 }, 2528 }; 2529 2530 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 2531 .halt_reg = 0xb010, 2532 .halt_check = BRANCH_HALT, 2533 .hwcg_reg = 0xb010, 2534 .hwcg_bit = 1, 2535 .clkr = { 2536 .enable_reg = 0xb010, 2537 .enable_mask = BIT(0), 2538 .hw.init = &(struct clk_init_data){ 2539 .name = "gcc_qmip_video_cvp_ahb_clk", 2540 .ops = &clk_branch2_ops, 2541 }, 2542 }, 2543 }; 2544 2545 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2546 .halt_reg = 0xb014, 2547 .halt_check = BRANCH_HALT, 2548 .hwcg_reg = 0xb014, 2549 .hwcg_bit = 1, 2550 .clkr = { 2551 .enable_reg = 0xb014, 2552 .enable_mask = BIT(0), 2553 .hw.init = &(struct clk_init_data){ 2554 .name = "gcc_qmip_video_vcodec_ahb_clk", 2555 .ops = &clk_branch2_ops, 2556 }, 2557 }, 2558 }; 2559 2560 static struct clk_branch gcc_qspi_1_cnoc_periph_ahb_clk = { 2561 .halt_reg = 0x4a004, 2562 .halt_check = BRANCH_HALT, 2563 .clkr = { 2564 .enable_reg = 0x4a004, 2565 .enable_mask = BIT(0), 2566 .hw.init = &(struct clk_init_data){ 2567 .name = "gcc_qspi_1_cnoc_periph_ahb_clk", 2568 .ops = &clk_branch2_ops, 2569 }, 2570 }, 2571 }; 2572 2573 static struct clk_branch gcc_qspi_1_core_clk = { 2574 .halt_reg = 0x4a008, 2575 .halt_check = BRANCH_HALT, 2576 .clkr = { 2577 .enable_reg = 0x4a008, 2578 .enable_mask = BIT(0), 2579 .hw.init = &(struct clk_init_data){ 2580 .name = "gcc_qspi_1_core_clk", 2581 .parent_hws = (const struct clk_hw *[]){ 2582 &gcc_qspi_1_core_clk_src.clkr.hw 2583 }, 2584 .num_parents = 1, 2585 .flags = CLK_SET_RATE_PARENT, 2586 .ops = &clk_branch2_ops, 2587 }, 2588 }, 2589 }; 2590 2591 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { 2592 .halt_reg = 0x4b000, 2593 .halt_check = BRANCH_HALT, 2594 .clkr = { 2595 .enable_reg = 0x4b000, 2596 .enable_mask = BIT(0), 2597 .hw.init = &(struct clk_init_data){ 2598 .name = "gcc_qspi_cnoc_periph_ahb_clk", 2599 .ops = &clk_branch2_ops, 2600 }, 2601 }, 2602 }; 2603 2604 static struct clk_branch gcc_qspi_core_clk = { 2605 .halt_reg = 0x4b004, 2606 .halt_check = BRANCH_HALT, 2607 .clkr = { 2608 .enable_reg = 0x4b004, 2609 .enable_mask = BIT(0), 2610 .hw.init = &(struct clk_init_data){ 2611 .name = "gcc_qspi_core_clk", 2612 .parent_hws = (const struct clk_hw *[]){ 2613 &gcc_qspi_core_clk_src.clkr.hw 2614 }, 2615 .num_parents = 1, 2616 .flags = CLK_SET_RATE_PARENT, 2617 .ops = &clk_branch2_ops, 2618 }, 2619 }, 2620 }; 2621 2622 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2623 .halt_reg = 0x17144, 2624 .halt_check = BRANCH_HALT_VOTED, 2625 .clkr = { 2626 .enable_reg = 0x5200c, 2627 .enable_mask = BIT(10), 2628 .hw.init = &(struct clk_init_data){ 2629 .name = "gcc_qupv3_wrap0_s0_clk", 2630 .parent_hws = (const struct clk_hw *[]){ 2631 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw 2632 }, 2633 .num_parents = 1, 2634 .flags = CLK_SET_RATE_PARENT, 2635 .ops = &clk_branch2_ops, 2636 }, 2637 }, 2638 }; 2639 2640 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2641 .halt_reg = 0x17274, 2642 .halt_check = BRANCH_HALT_VOTED, 2643 .clkr = { 2644 .enable_reg = 0x5200c, 2645 .enable_mask = BIT(11), 2646 .hw.init = &(struct clk_init_data){ 2647 .name = "gcc_qupv3_wrap0_s1_clk", 2648 .parent_hws = (const struct clk_hw *[]){ 2649 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw 2650 }, 2651 .num_parents = 1, 2652 .flags = CLK_SET_RATE_PARENT, 2653 .ops = &clk_branch2_ops, 2654 }, 2655 }, 2656 }; 2657 2658 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2659 .halt_reg = 0x173a4, 2660 .halt_check = BRANCH_HALT_VOTED, 2661 .clkr = { 2662 .enable_reg = 0x5200c, 2663 .enable_mask = BIT(12), 2664 .hw.init = &(struct clk_init_data){ 2665 .name = "gcc_qupv3_wrap0_s2_clk", 2666 .parent_hws = (const struct clk_hw *[]){ 2667 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw 2668 }, 2669 .num_parents = 1, 2670 .flags = CLK_SET_RATE_PARENT, 2671 .ops = &clk_branch2_ops, 2672 }, 2673 }, 2674 }; 2675 2676 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2677 .halt_reg = 0x174d4, 2678 .halt_check = BRANCH_HALT_VOTED, 2679 .clkr = { 2680 .enable_reg = 0x5200c, 2681 .enable_mask = BIT(13), 2682 .hw.init = &(struct clk_init_data){ 2683 .name = "gcc_qupv3_wrap0_s3_clk", 2684 .parent_hws = (const struct clk_hw *[]){ 2685 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw 2686 }, 2687 .num_parents = 1, 2688 .flags = CLK_SET_RATE_PARENT, 2689 .ops = &clk_branch2_ops, 2690 }, 2691 }, 2692 }; 2693 2694 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2695 .halt_reg = 0x17604, 2696 .halt_check = BRANCH_HALT_VOTED, 2697 .clkr = { 2698 .enable_reg = 0x5200c, 2699 .enable_mask = BIT(14), 2700 .hw.init = &(struct clk_init_data){ 2701 .name = "gcc_qupv3_wrap0_s4_clk", 2702 .parent_hws = (const struct clk_hw *[]){ 2703 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw 2704 }, 2705 .num_parents = 1, 2706 .flags = CLK_SET_RATE_PARENT, 2707 .ops = &clk_branch2_ops, 2708 }, 2709 }, 2710 }; 2711 2712 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2713 .halt_reg = 0x17734, 2714 .halt_check = BRANCH_HALT_VOTED, 2715 .clkr = { 2716 .enable_reg = 0x5200c, 2717 .enable_mask = BIT(15), 2718 .hw.init = &(struct clk_init_data){ 2719 .name = "gcc_qupv3_wrap0_s5_clk", 2720 .parent_hws = (const struct clk_hw *[]){ 2721 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw 2722 }, 2723 .num_parents = 1, 2724 .flags = CLK_SET_RATE_PARENT, 2725 .ops = &clk_branch2_ops, 2726 }, 2727 }, 2728 }; 2729 2730 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 2731 .halt_reg = 0x17864, 2732 .halt_check = BRANCH_HALT_VOTED, 2733 .clkr = { 2734 .enable_reg = 0x5200c, 2735 .enable_mask = BIT(16), 2736 .hw.init = &(struct clk_init_data){ 2737 .name = "gcc_qupv3_wrap0_s6_clk", 2738 .parent_hws = (const struct clk_hw *[]){ 2739 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw 2740 }, 2741 .num_parents = 1, 2742 .flags = CLK_SET_RATE_PARENT, 2743 .ops = &clk_branch2_ops, 2744 }, 2745 }, 2746 }; 2747 2748 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 2749 .halt_reg = 0x17994, 2750 .halt_check = BRANCH_HALT_VOTED, 2751 .clkr = { 2752 .enable_reg = 0x5200c, 2753 .enable_mask = BIT(17), 2754 .hw.init = &(struct clk_init_data){ 2755 .name = "gcc_qupv3_wrap0_s7_clk", 2756 .parent_hws = (const struct clk_hw *[]){ 2757 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw 2758 }, 2759 .num_parents = 1, 2760 .flags = CLK_SET_RATE_PARENT, 2761 .ops = &clk_branch2_ops, 2762 }, 2763 }, 2764 }; 2765 2766 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2767 .halt_reg = 0x18144, 2768 .halt_check = BRANCH_HALT_VOTED, 2769 .clkr = { 2770 .enable_reg = 0x5200c, 2771 .enable_mask = BIT(22), 2772 .hw.init = &(struct clk_init_data){ 2773 .name = "gcc_qupv3_wrap1_s0_clk", 2774 .parent_hws = (const struct clk_hw *[]){ 2775 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw 2776 }, 2777 .num_parents = 1, 2778 .flags = CLK_SET_RATE_PARENT, 2779 .ops = &clk_branch2_ops, 2780 }, 2781 }, 2782 }; 2783 2784 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2785 .halt_reg = 0x18274, 2786 .halt_check = BRANCH_HALT_VOTED, 2787 .clkr = { 2788 .enable_reg = 0x5200c, 2789 .enable_mask = BIT(23), 2790 .hw.init = &(struct clk_init_data){ 2791 .name = "gcc_qupv3_wrap1_s1_clk", 2792 .parent_hws = (const struct clk_hw *[]){ 2793 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw 2794 }, 2795 .num_parents = 1, 2796 .flags = CLK_SET_RATE_PARENT, 2797 .ops = &clk_branch2_ops, 2798 }, 2799 }, 2800 }; 2801 2802 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2803 .halt_reg = 0x183a4, 2804 .halt_check = BRANCH_HALT_VOTED, 2805 .clkr = { 2806 .enable_reg = 0x5200c, 2807 .enable_mask = BIT(24), 2808 .hw.init = &(struct clk_init_data){ 2809 .name = "gcc_qupv3_wrap1_s2_clk", 2810 .parent_hws = (const struct clk_hw *[]){ 2811 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw 2812 }, 2813 .num_parents = 1, 2814 .flags = CLK_SET_RATE_PARENT, 2815 .ops = &clk_branch2_ops, 2816 }, 2817 }, 2818 }; 2819 2820 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2821 .halt_reg = 0x184d4, 2822 .halt_check = BRANCH_HALT_VOTED, 2823 .clkr = { 2824 .enable_reg = 0x5200c, 2825 .enable_mask = BIT(25), 2826 .hw.init = &(struct clk_init_data){ 2827 .name = "gcc_qupv3_wrap1_s3_clk", 2828 .parent_hws = (const struct clk_hw *[]){ 2829 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw 2830 }, 2831 .num_parents = 1, 2832 .flags = CLK_SET_RATE_PARENT, 2833 .ops = &clk_branch2_ops, 2834 }, 2835 }, 2836 }; 2837 2838 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2839 .halt_reg = 0x18604, 2840 .halt_check = BRANCH_HALT_VOTED, 2841 .clkr = { 2842 .enable_reg = 0x5200c, 2843 .enable_mask = BIT(26), 2844 .hw.init = &(struct clk_init_data){ 2845 .name = "gcc_qupv3_wrap1_s4_clk", 2846 .parent_hws = (const struct clk_hw *[]){ 2847 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw 2848 }, 2849 .num_parents = 1, 2850 .flags = CLK_SET_RATE_PARENT, 2851 .ops = &clk_branch2_ops, 2852 }, 2853 }, 2854 }; 2855 2856 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2857 .halt_reg = 0x18734, 2858 .halt_check = BRANCH_HALT_VOTED, 2859 .clkr = { 2860 .enable_reg = 0x5200c, 2861 .enable_mask = BIT(27), 2862 .hw.init = &(struct clk_init_data){ 2863 .name = "gcc_qupv3_wrap1_s5_clk", 2864 .parent_hws = (const struct clk_hw *[]){ 2865 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw 2866 }, 2867 .num_parents = 1, 2868 .flags = CLK_SET_RATE_PARENT, 2869 .ops = &clk_branch2_ops, 2870 }, 2871 }, 2872 }; 2873 2874 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 2875 .halt_reg = 0x1e144, 2876 .halt_check = BRANCH_HALT_VOTED, 2877 .clkr = { 2878 .enable_reg = 0x52014, 2879 .enable_mask = BIT(4), 2880 .hw.init = &(struct clk_init_data){ 2881 .name = "gcc_qupv3_wrap2_s0_clk", 2882 .parent_hws = (const struct clk_hw *[]){ 2883 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw 2884 }, 2885 .num_parents = 1, 2886 .flags = CLK_SET_RATE_PARENT, 2887 .ops = &clk_branch2_ops, 2888 }, 2889 }, 2890 }; 2891 2892 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 2893 .halt_reg = 0x1e274, 2894 .halt_check = BRANCH_HALT_VOTED, 2895 .clkr = { 2896 .enable_reg = 0x52014, 2897 .enable_mask = BIT(5), 2898 .hw.init = &(struct clk_init_data){ 2899 .name = "gcc_qupv3_wrap2_s1_clk", 2900 .parent_hws = (const struct clk_hw *[]){ 2901 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw 2902 }, 2903 .num_parents = 1, 2904 .flags = CLK_SET_RATE_PARENT, 2905 .ops = &clk_branch2_ops, 2906 }, 2907 }, 2908 }; 2909 2910 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 2911 .halt_reg = 0x1e3a4, 2912 .halt_check = BRANCH_HALT_VOTED, 2913 .clkr = { 2914 .enable_reg = 0x52014, 2915 .enable_mask = BIT(6), 2916 .hw.init = &(struct clk_init_data){ 2917 .name = "gcc_qupv3_wrap2_s2_clk", 2918 .parent_hws = (const struct clk_hw *[]){ 2919 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw 2920 }, 2921 .num_parents = 1, 2922 .flags = CLK_SET_RATE_PARENT, 2923 .ops = &clk_branch2_ops, 2924 }, 2925 }, 2926 }; 2927 2928 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 2929 .halt_reg = 0x1e4d4, 2930 .halt_check = BRANCH_HALT_VOTED, 2931 .clkr = { 2932 .enable_reg = 0x52014, 2933 .enable_mask = BIT(7), 2934 .hw.init = &(struct clk_init_data){ 2935 .name = "gcc_qupv3_wrap2_s3_clk", 2936 .parent_hws = (const struct clk_hw *[]){ 2937 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw 2938 }, 2939 .num_parents = 1, 2940 .flags = CLK_SET_RATE_PARENT, 2941 .ops = &clk_branch2_ops, 2942 }, 2943 }, 2944 }; 2945 2946 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 2947 .halt_reg = 0x1e604, 2948 .halt_check = BRANCH_HALT_VOTED, 2949 .clkr = { 2950 .enable_reg = 0x52014, 2951 .enable_mask = BIT(8), 2952 .hw.init = &(struct clk_init_data){ 2953 .name = "gcc_qupv3_wrap2_s4_clk", 2954 .parent_hws = (const struct clk_hw *[]){ 2955 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw 2956 }, 2957 .num_parents = 1, 2958 .flags = CLK_SET_RATE_PARENT, 2959 .ops = &clk_branch2_ops, 2960 }, 2961 }, 2962 }; 2963 2964 static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 2965 .halt_reg = 0x1e734, 2966 .halt_check = BRANCH_HALT_VOTED, 2967 .clkr = { 2968 .enable_reg = 0x52014, 2969 .enable_mask = BIT(9), 2970 .hw.init = &(struct clk_init_data){ 2971 .name = "gcc_qupv3_wrap2_s5_clk", 2972 .parent_hws = (const struct clk_hw *[]){ 2973 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw 2974 }, 2975 .num_parents = 1, 2976 .flags = CLK_SET_RATE_PARENT, 2977 .ops = &clk_branch2_ops, 2978 }, 2979 }, 2980 }; 2981 2982 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2983 .halt_reg = 0x17004, 2984 .halt_check = BRANCH_HALT_VOTED, 2985 .clkr = { 2986 .enable_reg = 0x5200c, 2987 .enable_mask = BIT(6), 2988 .hw.init = &(struct clk_init_data){ 2989 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2990 .ops = &clk_branch2_ops, 2991 }, 2992 }, 2993 }; 2994 2995 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2996 .halt_reg = 0x17008, 2997 .halt_check = BRANCH_HALT_VOTED, 2998 .hwcg_reg = 0x17008, 2999 .hwcg_bit = 1, 3000 .clkr = { 3001 .enable_reg = 0x5200c, 3002 .enable_mask = BIT(7), 3003 .hw.init = &(struct clk_init_data){ 3004 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 3005 .ops = &clk_branch2_ops, 3006 }, 3007 }, 3008 }; 3009 3010 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 3011 .halt_reg = 0x18004, 3012 .halt_check = BRANCH_HALT_VOTED, 3013 .clkr = { 3014 .enable_reg = 0x5200c, 3015 .enable_mask = BIT(20), 3016 .hw.init = &(struct clk_init_data){ 3017 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 3018 .ops = &clk_branch2_ops, 3019 }, 3020 }, 3021 }; 3022 3023 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 3024 .halt_reg = 0x18008, 3025 .halt_check = BRANCH_HALT_VOTED, 3026 .hwcg_reg = 0x18008, 3027 .hwcg_bit = 1, 3028 .clkr = { 3029 .enable_reg = 0x5200c, 3030 .enable_mask = BIT(21), 3031 .hw.init = &(struct clk_init_data){ 3032 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 3033 .ops = &clk_branch2_ops, 3034 }, 3035 }, 3036 }; 3037 3038 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 3039 .halt_reg = 0x1e004, 3040 .halt_check = BRANCH_HALT_VOTED, 3041 .clkr = { 3042 .enable_reg = 0x52014, 3043 .enable_mask = BIT(2), 3044 .hw.init = &(struct clk_init_data){ 3045 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 3046 .ops = &clk_branch2_ops, 3047 }, 3048 }, 3049 }; 3050 3051 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 3052 .halt_reg = 0x1e008, 3053 .halt_check = BRANCH_HALT_VOTED, 3054 .hwcg_reg = 0x1e008, 3055 .hwcg_bit = 1, 3056 .clkr = { 3057 .enable_reg = 0x52014, 3058 .enable_mask = BIT(1), 3059 .hw.init = &(struct clk_init_data){ 3060 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 3061 .ops = &clk_branch2_ops, 3062 }, 3063 }, 3064 }; 3065 3066 static struct clk_branch gcc_sdcc2_ahb_clk = { 3067 .halt_reg = 0x14008, 3068 .halt_check = BRANCH_HALT, 3069 .clkr = { 3070 .enable_reg = 0x14008, 3071 .enable_mask = BIT(0), 3072 .hw.init = &(struct clk_init_data){ 3073 .name = "gcc_sdcc2_ahb_clk", 3074 .ops = &clk_branch2_ops, 3075 }, 3076 }, 3077 }; 3078 3079 static struct clk_branch gcc_sdcc2_apps_clk = { 3080 .halt_reg = 0x14004, 3081 .halt_check = BRANCH_HALT, 3082 .clkr = { 3083 .enable_reg = 0x14004, 3084 .enable_mask = BIT(0), 3085 .hw.init = &(struct clk_init_data){ 3086 .name = "gcc_sdcc2_apps_clk", 3087 .parent_hws = (const struct clk_hw *[]){ 3088 &gcc_sdcc2_apps_clk_src.clkr.hw 3089 }, 3090 .num_parents = 1, 3091 .flags = CLK_SET_RATE_PARENT, 3092 .ops = &clk_branch2_ops, 3093 }, 3094 }, 3095 }; 3096 3097 static struct clk_branch gcc_sdcc4_ahb_clk = { 3098 .halt_reg = 0x16008, 3099 .halt_check = BRANCH_HALT, 3100 .clkr = { 3101 .enable_reg = 0x16008, 3102 .enable_mask = BIT(0), 3103 .hw.init = &(struct clk_init_data){ 3104 .name = "gcc_sdcc4_ahb_clk", 3105 .ops = &clk_branch2_ops, 3106 }, 3107 }, 3108 }; 3109 3110 static struct clk_branch gcc_sdcc4_apps_clk = { 3111 .halt_reg = 0x16004, 3112 .halt_check = BRANCH_HALT, 3113 .clkr = { 3114 .enable_reg = 0x16004, 3115 .enable_mask = BIT(0), 3116 .hw.init = &(struct clk_init_data){ 3117 .name = "gcc_sdcc4_apps_clk", 3118 .parent_hws = (const struct clk_hw *[]){ 3119 &gcc_sdcc4_apps_clk_src.clkr.hw 3120 }, 3121 .num_parents = 1, 3122 .flags = CLK_SET_RATE_PARENT, 3123 .ops = &clk_branch2_ops, 3124 }, 3125 }, 3126 }; 3127 3128 static struct clk_branch gcc_tsif_ahb_clk = { 3129 .halt_reg = 0x36004, 3130 .halt_check = BRANCH_HALT, 3131 .clkr = { 3132 .enable_reg = 0x36004, 3133 .enable_mask = BIT(0), 3134 .hw.init = &(struct clk_init_data){ 3135 .name = "gcc_tsif_ahb_clk", 3136 .ops = &clk_branch2_ops, 3137 }, 3138 }, 3139 }; 3140 3141 static struct clk_branch gcc_tsif_inactivity_timers_clk = { 3142 .halt_reg = 0x3600c, 3143 .halt_check = BRANCH_HALT, 3144 .clkr = { 3145 .enable_reg = 0x3600c, 3146 .enable_mask = BIT(0), 3147 .hw.init = &(struct clk_init_data){ 3148 .name = "gcc_tsif_inactivity_timers_clk", 3149 .ops = &clk_branch2_ops, 3150 }, 3151 }, 3152 }; 3153 3154 static struct clk_branch gcc_tsif_ref_clk = { 3155 .halt_reg = 0x36008, 3156 .halt_check = BRANCH_HALT, 3157 .clkr = { 3158 .enable_reg = 0x36008, 3159 .enable_mask = BIT(0), 3160 .hw.init = &(struct clk_init_data){ 3161 .name = "gcc_tsif_ref_clk", 3162 .parent_hws = (const struct clk_hw *[]){ 3163 &gcc_tsif_ref_clk_src.clkr.hw 3164 }, 3165 .num_parents = 1, 3166 .flags = CLK_SET_RATE_PARENT, 3167 .ops = &clk_branch2_ops, 3168 }, 3169 }, 3170 }; 3171 3172 static struct clk_branch gcc_ufs_card_2_ahb_clk = { 3173 .halt_reg = 0xa2014, 3174 .halt_check = BRANCH_HALT, 3175 .hwcg_reg = 0xa2014, 3176 .hwcg_bit = 1, 3177 .clkr = { 3178 .enable_reg = 0xa2014, 3179 .enable_mask = BIT(0), 3180 .hw.init = &(struct clk_init_data){ 3181 .name = "gcc_ufs_card_2_ahb_clk", 3182 .ops = &clk_branch2_ops, 3183 }, 3184 }, 3185 }; 3186 3187 static struct clk_branch gcc_ufs_card_2_axi_clk = { 3188 .halt_reg = 0xa2010, 3189 .halt_check = BRANCH_HALT, 3190 .hwcg_reg = 0xa2010, 3191 .hwcg_bit = 1, 3192 .clkr = { 3193 .enable_reg = 0xa2010, 3194 .enable_mask = BIT(0), 3195 .hw.init = &(struct clk_init_data){ 3196 .name = "gcc_ufs_card_2_axi_clk", 3197 .parent_hws = (const struct clk_hw *[]){ 3198 &gcc_ufs_card_2_axi_clk_src.clkr.hw 3199 }, 3200 .num_parents = 1, 3201 .flags = CLK_SET_RATE_PARENT, 3202 .ops = &clk_branch2_ops, 3203 }, 3204 }, 3205 }; 3206 3207 static struct clk_branch gcc_ufs_card_2_ice_core_clk = { 3208 .halt_reg = 0xa205c, 3209 .halt_check = BRANCH_HALT, 3210 .hwcg_reg = 0xa205c, 3211 .hwcg_bit = 1, 3212 .clkr = { 3213 .enable_reg = 0xa205c, 3214 .enable_mask = BIT(0), 3215 .hw.init = &(struct clk_init_data){ 3216 .name = "gcc_ufs_card_2_ice_core_clk", 3217 .parent_hws = (const struct clk_hw *[]){ 3218 &gcc_ufs_card_2_ice_core_clk_src.clkr.hw 3219 }, 3220 .num_parents = 1, 3221 .flags = CLK_SET_RATE_PARENT, 3222 .ops = &clk_branch2_ops, 3223 }, 3224 }, 3225 }; 3226 3227 static struct clk_branch gcc_ufs_card_2_phy_aux_clk = { 3228 .halt_reg = 0xa2090, 3229 .halt_check = BRANCH_HALT, 3230 .hwcg_reg = 0xa2090, 3231 .hwcg_bit = 1, 3232 .clkr = { 3233 .enable_reg = 0xa2090, 3234 .enable_mask = BIT(0), 3235 .hw.init = &(struct clk_init_data){ 3236 .name = "gcc_ufs_card_2_phy_aux_clk", 3237 .parent_hws = (const struct clk_hw *[]){ 3238 &gcc_ufs_card_2_phy_aux_clk_src.clkr.hw 3239 }, 3240 .num_parents = 1, 3241 .flags = CLK_SET_RATE_PARENT, 3242 .ops = &clk_branch2_ops, 3243 }, 3244 }, 3245 }; 3246 3247 static struct clk_branch gcc_ufs_card_2_rx_symbol_0_clk = { 3248 .halt_reg = 0xa201c, 3249 .halt_check = BRANCH_HALT, 3250 .clkr = { 3251 .enable_reg = 0xa201c, 3252 .enable_mask = BIT(0), 3253 .hw.init = &(struct clk_init_data){ 3254 .name = "gcc_ufs_card_2_rx_symbol_0_clk", 3255 .ops = &clk_branch2_ops, 3256 }, 3257 }, 3258 }; 3259 3260 static struct clk_branch gcc_ufs_card_2_rx_symbol_1_clk = { 3261 .halt_reg = 0xa20ac, 3262 .halt_check = BRANCH_HALT, 3263 .clkr = { 3264 .enable_reg = 0xa20ac, 3265 .enable_mask = BIT(0), 3266 .hw.init = &(struct clk_init_data){ 3267 .name = "gcc_ufs_card_2_rx_symbol_1_clk", 3268 .ops = &clk_branch2_ops, 3269 }, 3270 }, 3271 }; 3272 3273 static struct clk_branch gcc_ufs_card_2_tx_symbol_0_clk = { 3274 .halt_reg = 0xa2018, 3275 .halt_check = BRANCH_HALT, 3276 .clkr = { 3277 .enable_reg = 0xa2018, 3278 .enable_mask = BIT(0), 3279 .hw.init = &(struct clk_init_data){ 3280 .name = "gcc_ufs_card_2_tx_symbol_0_clk", 3281 .ops = &clk_branch2_ops, 3282 }, 3283 }, 3284 }; 3285 3286 static struct clk_branch gcc_ufs_card_2_unipro_core_clk = { 3287 .halt_reg = 0xa2058, 3288 .halt_check = BRANCH_HALT, 3289 .hwcg_reg = 0xa2058, 3290 .hwcg_bit = 1, 3291 .clkr = { 3292 .enable_reg = 0xa2058, 3293 .enable_mask = BIT(0), 3294 .hw.init = &(struct clk_init_data){ 3295 .name = "gcc_ufs_card_2_unipro_core_clk", 3296 .parent_hws = (const struct clk_hw *[]){ 3297 &gcc_ufs_card_2_unipro_core_clk_src.clkr.hw 3298 }, 3299 .num_parents = 1, 3300 .flags = CLK_SET_RATE_PARENT, 3301 .ops = &clk_branch2_ops, 3302 }, 3303 }, 3304 }; 3305 3306 static struct clk_branch gcc_ufs_card_ahb_clk = { 3307 .halt_reg = 0x75014, 3308 .halt_check = BRANCH_HALT, 3309 .hwcg_reg = 0x75014, 3310 .hwcg_bit = 1, 3311 .clkr = { 3312 .enable_reg = 0x75014, 3313 .enable_mask = BIT(0), 3314 .hw.init = &(struct clk_init_data){ 3315 .name = "gcc_ufs_card_ahb_clk", 3316 .ops = &clk_branch2_ops, 3317 }, 3318 }, 3319 }; 3320 3321 static struct clk_branch gcc_ufs_card_axi_clk = { 3322 .halt_reg = 0x75010, 3323 .halt_check = BRANCH_HALT, 3324 .hwcg_reg = 0x75010, 3325 .hwcg_bit = 1, 3326 .clkr = { 3327 .enable_reg = 0x75010, 3328 .enable_mask = BIT(0), 3329 .hw.init = &(struct clk_init_data){ 3330 .name = "gcc_ufs_card_axi_clk", 3331 .parent_hws = (const struct clk_hw *[]){ 3332 &gcc_ufs_card_axi_clk_src.clkr.hw 3333 }, 3334 .num_parents = 1, 3335 .flags = CLK_SET_RATE_PARENT, 3336 .ops = &clk_branch2_ops, 3337 }, 3338 }, 3339 }; 3340 3341 static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = { 3342 .halt_reg = 0x75010, 3343 .halt_check = BRANCH_HALT, 3344 .hwcg_reg = 0x75010, 3345 .hwcg_bit = 1, 3346 .clkr = { 3347 .enable_reg = 0x75010, 3348 .enable_mask = BIT(1), 3349 .hw.init = &(struct clk_init_data){ 3350 .name = "gcc_ufs_card_axi_hw_ctl_clk", 3351 .parent_hws = (const struct clk_hw *[]){ 3352 &gcc_ufs_card_axi_clk.clkr.hw 3353 }, 3354 .num_parents = 1, 3355 .flags = CLK_SET_RATE_PARENT, 3356 .ops = &clk_branch_simple_ops, 3357 }, 3358 }, 3359 }; 3360 3361 static struct clk_branch gcc_ufs_card_ice_core_clk = { 3362 .halt_reg = 0x7505c, 3363 .halt_check = BRANCH_HALT, 3364 .hwcg_reg = 0x7505c, 3365 .hwcg_bit = 1, 3366 .clkr = { 3367 .enable_reg = 0x7505c, 3368 .enable_mask = BIT(0), 3369 .hw.init = &(struct clk_init_data){ 3370 .name = "gcc_ufs_card_ice_core_clk", 3371 .parent_hws = (const struct clk_hw *[]){ 3372 &gcc_ufs_card_ice_core_clk_src.clkr.hw 3373 }, 3374 .num_parents = 1, 3375 .flags = CLK_SET_RATE_PARENT, 3376 .ops = &clk_branch2_ops, 3377 }, 3378 }, 3379 }; 3380 3381 static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = { 3382 .halt_reg = 0x7505c, 3383 .halt_check = BRANCH_HALT, 3384 .hwcg_reg = 0x7505c, 3385 .hwcg_bit = 1, 3386 .clkr = { 3387 .enable_reg = 0x7505c, 3388 .enable_mask = BIT(1), 3389 .hw.init = &(struct clk_init_data){ 3390 .name = "gcc_ufs_card_ice_core_hw_ctl_clk", 3391 .parent_hws = (const struct clk_hw *[]){ 3392 &gcc_ufs_card_ice_core_clk.clkr.hw 3393 }, 3394 .num_parents = 1, 3395 .flags = CLK_SET_RATE_PARENT, 3396 .ops = &clk_branch_simple_ops, 3397 }, 3398 }, 3399 }; 3400 3401 static struct clk_branch gcc_ufs_card_phy_aux_clk = { 3402 .halt_reg = 0x75090, 3403 .halt_check = BRANCH_HALT, 3404 .hwcg_reg = 0x75090, 3405 .hwcg_bit = 1, 3406 .clkr = { 3407 .enable_reg = 0x75090, 3408 .enable_mask = BIT(0), 3409 .hw.init = &(struct clk_init_data){ 3410 .name = "gcc_ufs_card_phy_aux_clk", 3411 .parent_hws = (const struct clk_hw *[]){ 3412 &gcc_ufs_card_phy_aux_clk_src.clkr.hw 3413 }, 3414 .num_parents = 1, 3415 .flags = CLK_SET_RATE_PARENT, 3416 .ops = &clk_branch2_ops, 3417 }, 3418 }, 3419 }; 3420 3421 static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { 3422 .halt_reg = 0x75090, 3423 .halt_check = BRANCH_HALT, 3424 .hwcg_reg = 0x75090, 3425 .hwcg_bit = 1, 3426 .clkr = { 3427 .enable_reg = 0x75090, 3428 .enable_mask = BIT(1), 3429 .hw.init = &(struct clk_init_data){ 3430 .name = "gcc_ufs_card_phy_aux_hw_ctl_clk", 3431 .parent_hws = (const struct clk_hw *[]){ 3432 &gcc_ufs_card_phy_aux_clk.clkr.hw 3433 }, 3434 .num_parents = 1, 3435 .flags = CLK_SET_RATE_PARENT, 3436 .ops = &clk_branch_simple_ops, 3437 }, 3438 }, 3439 }; 3440 3441 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { 3442 .halt_reg = 0x7501c, 3443 .halt_check = BRANCH_HALT_DELAY, 3444 .clkr = { 3445 .enable_reg = 0x7501c, 3446 .enable_mask = BIT(0), 3447 .hw.init = &(struct clk_init_data){ 3448 .name = "gcc_ufs_card_rx_symbol_0_clk", 3449 .ops = &clk_branch2_ops, 3450 }, 3451 }, 3452 }; 3453 3454 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { 3455 .halt_reg = 0x750ac, 3456 .halt_check = BRANCH_HALT_DELAY, 3457 .clkr = { 3458 .enable_reg = 0x750ac, 3459 .enable_mask = BIT(0), 3460 .hw.init = &(struct clk_init_data){ 3461 .name = "gcc_ufs_card_rx_symbol_1_clk", 3462 .ops = &clk_branch2_ops, 3463 }, 3464 }, 3465 }; 3466 3467 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { 3468 .halt_reg = 0x75018, 3469 .halt_check = BRANCH_HALT_DELAY, 3470 .clkr = { 3471 .enable_reg = 0x75018, 3472 .enable_mask = BIT(0), 3473 .hw.init = &(struct clk_init_data){ 3474 .name = "gcc_ufs_card_tx_symbol_0_clk", 3475 .ops = &clk_branch2_ops, 3476 }, 3477 }, 3478 }; 3479 3480 static struct clk_branch gcc_ufs_card_unipro_core_clk = { 3481 .halt_reg = 0x75058, 3482 .halt_check = BRANCH_HALT, 3483 .hwcg_reg = 0x75058, 3484 .hwcg_bit = 1, 3485 .clkr = { 3486 .enable_reg = 0x75058, 3487 .enable_mask = BIT(0), 3488 .hw.init = &(struct clk_init_data){ 3489 .name = "gcc_ufs_card_unipro_core_clk", 3490 .parent_hws = (const struct clk_hw *[]){ 3491 &gcc_ufs_card_unipro_core_clk_src.clkr.hw 3492 }, 3493 .num_parents = 1, 3494 .flags = CLK_SET_RATE_PARENT, 3495 .ops = &clk_branch2_ops, 3496 }, 3497 }, 3498 }; 3499 3500 static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { 3501 .halt_reg = 0x75058, 3502 .halt_check = BRANCH_HALT, 3503 .hwcg_reg = 0x75058, 3504 .hwcg_bit = 1, 3505 .clkr = { 3506 .enable_reg = 0x75058, 3507 .enable_mask = BIT(1), 3508 .hw.init = &(struct clk_init_data){ 3509 .name = "gcc_ufs_card_unipro_core_hw_ctl_clk", 3510 .parent_hws = (const struct clk_hw *[]){ 3511 &gcc_ufs_card_unipro_core_clk.clkr.hw 3512 }, 3513 .num_parents = 1, 3514 .flags = CLK_SET_RATE_PARENT, 3515 .ops = &clk_branch_simple_ops, 3516 }, 3517 }, 3518 }; 3519 3520 static struct clk_branch gcc_ufs_phy_ahb_clk = { 3521 .halt_reg = 0x77014, 3522 .halt_check = BRANCH_HALT, 3523 .hwcg_reg = 0x77014, 3524 .hwcg_bit = 1, 3525 .clkr = { 3526 .enable_reg = 0x77014, 3527 .enable_mask = BIT(0), 3528 .hw.init = &(struct clk_init_data){ 3529 .name = "gcc_ufs_phy_ahb_clk", 3530 .ops = &clk_branch2_ops, 3531 }, 3532 }, 3533 }; 3534 3535 static struct clk_branch gcc_ufs_phy_axi_clk = { 3536 .halt_reg = 0x77010, 3537 .halt_check = BRANCH_HALT, 3538 .hwcg_reg = 0x77010, 3539 .hwcg_bit = 1, 3540 .clkr = { 3541 .enable_reg = 0x77010, 3542 .enable_mask = BIT(0), 3543 .hw.init = &(struct clk_init_data){ 3544 .name = "gcc_ufs_phy_axi_clk", 3545 .parent_hws = (const struct clk_hw *[]){ 3546 &gcc_ufs_phy_axi_clk_src.clkr.hw 3547 }, 3548 .num_parents = 1, 3549 .flags = CLK_SET_RATE_PARENT, 3550 .ops = &clk_branch2_ops, 3551 }, 3552 }, 3553 }; 3554 3555 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { 3556 .halt_reg = 0x77010, 3557 .halt_check = BRANCH_HALT, 3558 .hwcg_reg = 0x77010, 3559 .hwcg_bit = 1, 3560 .clkr = { 3561 .enable_reg = 0x77010, 3562 .enable_mask = BIT(1), 3563 .hw.init = &(struct clk_init_data){ 3564 .name = "gcc_ufs_phy_axi_hw_ctl_clk", 3565 .parent_hws = (const struct clk_hw *[]){ 3566 &gcc_ufs_phy_axi_clk.clkr.hw 3567 }, 3568 .num_parents = 1, 3569 .flags = CLK_SET_RATE_PARENT, 3570 .ops = &clk_branch_simple_ops, 3571 }, 3572 }, 3573 }; 3574 3575 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 3576 .halt_reg = 0x7705c, 3577 .halt_check = BRANCH_HALT, 3578 .hwcg_reg = 0x7705c, 3579 .hwcg_bit = 1, 3580 .clkr = { 3581 .enable_reg = 0x7705c, 3582 .enable_mask = BIT(0), 3583 .hw.init = &(struct clk_init_data){ 3584 .name = "gcc_ufs_phy_ice_core_clk", 3585 .parent_hws = (const struct clk_hw *[]){ 3586 &gcc_ufs_phy_ice_core_clk_src.clkr.hw 3587 }, 3588 .num_parents = 1, 3589 .flags = CLK_SET_RATE_PARENT, 3590 .ops = &clk_branch2_ops, 3591 }, 3592 }, 3593 }; 3594 3595 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { 3596 .halt_reg = 0x7705c, 3597 .halt_check = BRANCH_HALT, 3598 .hwcg_reg = 0x7705c, 3599 .hwcg_bit = 1, 3600 .clkr = { 3601 .enable_reg = 0x7705c, 3602 .enable_mask = BIT(1), 3603 .hw.init = &(struct clk_init_data){ 3604 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", 3605 .parent_hws = (const struct clk_hw *[]){ 3606 &gcc_ufs_phy_ice_core_clk.clkr.hw 3607 }, 3608 .num_parents = 1, 3609 .flags = CLK_SET_RATE_PARENT, 3610 .ops = &clk_branch_simple_ops, 3611 }, 3612 }, 3613 }; 3614 3615 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 3616 .halt_reg = 0x77090, 3617 .halt_check = BRANCH_HALT, 3618 .hwcg_reg = 0x77090, 3619 .hwcg_bit = 1, 3620 .clkr = { 3621 .enable_reg = 0x77090, 3622 .enable_mask = BIT(0), 3623 .hw.init = &(struct clk_init_data){ 3624 .name = "gcc_ufs_phy_phy_aux_clk", 3625 .parent_hws = (const struct clk_hw *[]){ 3626 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw 3627 }, 3628 .num_parents = 1, 3629 .flags = CLK_SET_RATE_PARENT, 3630 .ops = &clk_branch2_ops, 3631 }, 3632 }, 3633 }; 3634 3635 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { 3636 .halt_reg = 0x77090, 3637 .halt_check = BRANCH_HALT, 3638 .hwcg_reg = 0x77090, 3639 .hwcg_bit = 1, 3640 .clkr = { 3641 .enable_reg = 0x77090, 3642 .enable_mask = BIT(1), 3643 .hw.init = &(struct clk_init_data){ 3644 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", 3645 .parent_hws = (const struct clk_hw *[]){ 3646 &gcc_ufs_phy_phy_aux_clk.clkr.hw 3647 }, 3648 .num_parents = 1, 3649 .flags = CLK_SET_RATE_PARENT, 3650 .ops = &clk_branch_simple_ops, 3651 }, 3652 }, 3653 }; 3654 3655 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 3656 .halt_reg = 0x7701c, 3657 .halt_check = BRANCH_HALT_SKIP, 3658 .clkr = { 3659 .enable_reg = 0x7701c, 3660 .enable_mask = BIT(0), 3661 .hw.init = &(struct clk_init_data){ 3662 .name = "gcc_ufs_phy_rx_symbol_0_clk", 3663 .ops = &clk_branch2_ops, 3664 }, 3665 }, 3666 }; 3667 3668 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 3669 .halt_reg = 0x770ac, 3670 .halt_check = BRANCH_HALT_SKIP, 3671 .clkr = { 3672 .enable_reg = 0x770ac, 3673 .enable_mask = BIT(0), 3674 .hw.init = &(struct clk_init_data){ 3675 .name = "gcc_ufs_phy_rx_symbol_1_clk", 3676 .ops = &clk_branch2_ops, 3677 }, 3678 }, 3679 }; 3680 3681 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 3682 .halt_reg = 0x77018, 3683 .halt_check = BRANCH_HALT_SKIP, 3684 .clkr = { 3685 .enable_reg = 0x77018, 3686 .enable_mask = BIT(0), 3687 .hw.init = &(struct clk_init_data){ 3688 .name = "gcc_ufs_phy_tx_symbol_0_clk", 3689 .ops = &clk_branch2_ops, 3690 }, 3691 }, 3692 }; 3693 3694 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 3695 .halt_reg = 0x77058, 3696 .halt_check = BRANCH_HALT, 3697 .hwcg_reg = 0x77058, 3698 .hwcg_bit = 1, 3699 .clkr = { 3700 .enable_reg = 0x77058, 3701 .enable_mask = BIT(0), 3702 .hw.init = &(struct clk_init_data){ 3703 .name = "gcc_ufs_phy_unipro_core_clk", 3704 .parent_hws = (const struct clk_hw *[]){ 3705 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw 3706 }, 3707 .num_parents = 1, 3708 .flags = CLK_SET_RATE_PARENT, 3709 .ops = &clk_branch2_ops, 3710 }, 3711 }, 3712 }; 3713 3714 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { 3715 .halt_reg = 0x77058, 3716 .halt_check = BRANCH_HALT, 3717 .hwcg_reg = 0x77058, 3718 .hwcg_bit = 1, 3719 .clkr = { 3720 .enable_reg = 0x77058, 3721 .enable_mask = BIT(1), 3722 .hw.init = &(struct clk_init_data){ 3723 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", 3724 .parent_hws = (const struct clk_hw *[]){ 3725 &gcc_ufs_phy_unipro_core_clk.clkr.hw 3726 }, 3727 .num_parents = 1, 3728 .flags = CLK_SET_RATE_PARENT, 3729 .ops = &clk_branch_simple_ops, 3730 }, 3731 }, 3732 }; 3733 3734 static struct clk_branch gcc_usb30_mp_master_clk = { 3735 .halt_reg = 0xa6010, 3736 .halt_check = BRANCH_HALT, 3737 .clkr = { 3738 .enable_reg = 0xa6010, 3739 .enable_mask = BIT(0), 3740 .hw.init = &(struct clk_init_data){ 3741 .name = "gcc_usb30_mp_master_clk", 3742 .parent_hws = (const struct clk_hw *[]){ 3743 &gcc_usb30_mp_master_clk_src.clkr.hw }, 3744 .num_parents = 1, 3745 .flags = CLK_SET_RATE_PARENT, 3746 .ops = &clk_branch2_ops, 3747 }, 3748 }, 3749 }; 3750 3751 static struct clk_branch gcc_usb30_mp_mock_utmi_clk = { 3752 .halt_reg = 0xa6018, 3753 .halt_check = BRANCH_HALT, 3754 .clkr = { 3755 .enable_reg = 0xa6018, 3756 .enable_mask = BIT(0), 3757 .hw.init = &(struct clk_init_data){ 3758 .name = "gcc_usb30_mp_mock_utmi_clk", 3759 .parent_hws = (const struct clk_hw *[]){ 3760 &gcc_usb30_mp_mock_utmi_clk_src.clkr.hw 3761 }, 3762 .num_parents = 1, 3763 .flags = CLK_SET_RATE_PARENT, 3764 .ops = &clk_branch2_ops, 3765 }, 3766 }, 3767 }; 3768 3769 static struct clk_branch gcc_usb30_mp_sleep_clk = { 3770 .halt_reg = 0xa6014, 3771 .halt_check = BRANCH_HALT, 3772 .clkr = { 3773 .enable_reg = 0xa6014, 3774 .enable_mask = BIT(0), 3775 .hw.init = &(struct clk_init_data){ 3776 .name = "gcc_usb30_mp_sleep_clk", 3777 .ops = &clk_branch2_ops, 3778 }, 3779 }, 3780 }; 3781 3782 static struct clk_branch gcc_usb30_prim_master_clk = { 3783 .halt_reg = 0xf010, 3784 .halt_check = BRANCH_HALT, 3785 .clkr = { 3786 .enable_reg = 0xf010, 3787 .enable_mask = BIT(0), 3788 .hw.init = &(struct clk_init_data){ 3789 .name = "gcc_usb30_prim_master_clk", 3790 .parent_hws = (const struct clk_hw *[]){ 3791 &gcc_usb30_prim_master_clk_src.clkr.hw }, 3792 .num_parents = 1, 3793 .flags = CLK_SET_RATE_PARENT, 3794 .ops = &clk_branch2_ops, 3795 }, 3796 }, 3797 }; 3798 3799 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 3800 .halt_reg = 0xf018, 3801 .halt_check = BRANCH_HALT, 3802 .clkr = { 3803 .enable_reg = 0xf018, 3804 .enable_mask = BIT(0), 3805 .hw.init = &(struct clk_init_data){ 3806 .name = "gcc_usb30_prim_mock_utmi_clk", 3807 .parent_hws = (const struct clk_hw *[]){ 3808 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw 3809 }, 3810 .num_parents = 1, 3811 .flags = CLK_SET_RATE_PARENT, 3812 .ops = &clk_branch2_ops, 3813 }, 3814 }, 3815 }; 3816 3817 static struct clk_branch gcc_usb30_prim_sleep_clk = { 3818 .halt_reg = 0xf014, 3819 .halt_check = BRANCH_HALT, 3820 .clkr = { 3821 .enable_reg = 0xf014, 3822 .enable_mask = BIT(0), 3823 .hw.init = &(struct clk_init_data){ 3824 .name = "gcc_usb30_prim_sleep_clk", 3825 .ops = &clk_branch2_ops, 3826 }, 3827 }, 3828 }; 3829 3830 static struct clk_branch gcc_usb30_sec_master_clk = { 3831 .halt_reg = 0x10010, 3832 .halt_check = BRANCH_HALT, 3833 .clkr = { 3834 .enable_reg = 0x10010, 3835 .enable_mask = BIT(0), 3836 .hw.init = &(struct clk_init_data){ 3837 .name = "gcc_usb30_sec_master_clk", 3838 .parent_hws = (const struct clk_hw *[]){ 3839 &gcc_usb30_sec_master_clk_src.clkr.hw }, 3840 .num_parents = 1, 3841 .flags = CLK_SET_RATE_PARENT, 3842 .ops = &clk_branch2_ops, 3843 }, 3844 }, 3845 }; 3846 3847 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { 3848 .halt_reg = 0x10018, 3849 .halt_check = BRANCH_HALT, 3850 .clkr = { 3851 .enable_reg = 0x10018, 3852 .enable_mask = BIT(0), 3853 .hw.init = &(struct clk_init_data){ 3854 .name = "gcc_usb30_sec_mock_utmi_clk", 3855 .parent_hws = (const struct clk_hw *[]){ 3856 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw 3857 }, 3858 .num_parents = 1, 3859 .flags = CLK_SET_RATE_PARENT, 3860 .ops = &clk_branch2_ops, 3861 }, 3862 }, 3863 }; 3864 3865 static struct clk_branch gcc_usb30_sec_sleep_clk = { 3866 .halt_reg = 0x10014, 3867 .halt_check = BRANCH_HALT, 3868 .clkr = { 3869 .enable_reg = 0x10014, 3870 .enable_mask = BIT(0), 3871 .hw.init = &(struct clk_init_data){ 3872 .name = "gcc_usb30_sec_sleep_clk", 3873 .ops = &clk_branch2_ops, 3874 }, 3875 }, 3876 }; 3877 3878 static struct clk_branch gcc_usb3_mp_phy_aux_clk = { 3879 .halt_reg = 0xa6050, 3880 .halt_check = BRANCH_HALT, 3881 .clkr = { 3882 .enable_reg = 0xa6050, 3883 .enable_mask = BIT(0), 3884 .hw.init = &(struct clk_init_data){ 3885 .name = "gcc_usb3_mp_phy_aux_clk", 3886 .parent_hws = (const struct clk_hw *[]){ 3887 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw 3888 }, 3889 .num_parents = 1, 3890 .flags = CLK_SET_RATE_PARENT, 3891 .ops = &clk_branch2_ops, 3892 }, 3893 }, 3894 }; 3895 3896 static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = { 3897 .halt_reg = 0xa6054, 3898 .halt_check = BRANCH_HALT, 3899 .clkr = { 3900 .enable_reg = 0xa6054, 3901 .enable_mask = BIT(0), 3902 .hw.init = &(struct clk_init_data){ 3903 .name = "gcc_usb3_mp_phy_com_aux_clk", 3904 .parent_hws = (const struct clk_hw *[]){ 3905 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw 3906 }, 3907 .num_parents = 1, 3908 .flags = CLK_SET_RATE_PARENT, 3909 .ops = &clk_branch2_ops, 3910 }, 3911 }, 3912 }; 3913 3914 static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = { 3915 .halt_reg = 0xa6058, 3916 .halt_check = BRANCH_HALT_SKIP, 3917 .clkr = { 3918 .enable_reg = 0xa6058, 3919 .enable_mask = BIT(0), 3920 .hw.init = &(struct clk_init_data){ 3921 .name = "gcc_usb3_mp_phy_pipe_0_clk", 3922 .ops = &clk_branch2_ops, 3923 }, 3924 }, 3925 }; 3926 3927 static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = { 3928 .halt_reg = 0xa605c, 3929 .halt_check = BRANCH_HALT_SKIP, 3930 .clkr = { 3931 .enable_reg = 0xa605c, 3932 .enable_mask = BIT(0), 3933 .hw.init = &(struct clk_init_data){ 3934 .name = "gcc_usb3_mp_phy_pipe_1_clk", 3935 .ops = &clk_branch2_ops, 3936 }, 3937 }, 3938 }; 3939 3940 static struct clk_branch gcc_usb3_prim_clkref_clk = { 3941 .halt_reg = 0x8c008, 3942 .halt_check = BRANCH_HALT, 3943 .clkr = { 3944 .enable_reg = 0x8c008, 3945 .enable_mask = BIT(0), 3946 .hw.init = &(struct clk_init_data){ 3947 .name = "gcc_usb3_prim_clkref_clk", 3948 .ops = &clk_branch2_ops, 3949 }, 3950 }, 3951 }; 3952 3953 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 3954 .halt_reg = 0xf050, 3955 .halt_check = BRANCH_HALT, 3956 .clkr = { 3957 .enable_reg = 0xf050, 3958 .enable_mask = BIT(0), 3959 .hw.init = &(struct clk_init_data){ 3960 .name = "gcc_usb3_prim_phy_aux_clk", 3961 .parent_hws = (const struct clk_hw *[]){ 3962 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw 3963 }, 3964 .num_parents = 1, 3965 .flags = CLK_SET_RATE_PARENT, 3966 .ops = &clk_branch2_ops, 3967 }, 3968 }, 3969 }; 3970 3971 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3972 .halt_reg = 0xf054, 3973 .halt_check = BRANCH_HALT, 3974 .clkr = { 3975 .enable_reg = 0xf054, 3976 .enable_mask = BIT(0), 3977 .hw.init = &(struct clk_init_data){ 3978 .name = "gcc_usb3_prim_phy_com_aux_clk", 3979 .parent_hws = (const struct clk_hw *[]){ 3980 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw 3981 }, 3982 .num_parents = 1, 3983 .flags = CLK_SET_RATE_PARENT, 3984 .ops = &clk_branch2_ops, 3985 }, 3986 }, 3987 }; 3988 3989 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3990 .halt_reg = 0xf058, 3991 .halt_check = BRANCH_HALT_SKIP, 3992 .clkr = { 3993 .enable_reg = 0xf058, 3994 .enable_mask = BIT(0), 3995 .hw.init = &(struct clk_init_data){ 3996 .name = "gcc_usb3_prim_phy_pipe_clk", 3997 .ops = &clk_branch2_ops, 3998 }, 3999 }, 4000 }; 4001 4002 static struct clk_branch gcc_usb3_sec_clkref_clk = { 4003 .halt_reg = 0x8c028, 4004 .halt_check = BRANCH_HALT, 4005 .clkr = { 4006 .enable_reg = 0x8c028, 4007 .enable_mask = BIT(0), 4008 .hw.init = &(struct clk_init_data){ 4009 .name = "gcc_usb3_sec_clkref_clk", 4010 .ops = &clk_branch2_ops, 4011 }, 4012 }, 4013 }; 4014 4015 static struct clk_branch gcc_usb3_sec_phy_aux_clk = { 4016 .halt_reg = 0x10050, 4017 .halt_check = BRANCH_HALT, 4018 .clkr = { 4019 .enable_reg = 0x10050, 4020 .enable_mask = BIT(0), 4021 .hw.init = &(struct clk_init_data){ 4022 .name = "gcc_usb3_sec_phy_aux_clk", 4023 .parent_hws = (const struct clk_hw *[]){ 4024 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw 4025 }, 4026 .num_parents = 1, 4027 .flags = CLK_SET_RATE_PARENT, 4028 .ops = &clk_branch2_ops, 4029 }, 4030 }, 4031 }; 4032 4033 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { 4034 .halt_reg = 0x10054, 4035 .halt_check = BRANCH_HALT, 4036 .clkr = { 4037 .enable_reg = 0x10054, 4038 .enable_mask = BIT(0), 4039 .hw.init = &(struct clk_init_data){ 4040 .name = "gcc_usb3_sec_phy_com_aux_clk", 4041 .parent_hws = (const struct clk_hw *[]){ 4042 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw 4043 }, 4044 .num_parents = 1, 4045 .flags = CLK_SET_RATE_PARENT, 4046 .ops = &clk_branch2_ops, 4047 }, 4048 }, 4049 }; 4050 4051 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { 4052 .halt_reg = 0x10058, 4053 .halt_check = BRANCH_HALT_SKIP, 4054 .clkr = { 4055 .enable_reg = 0x10058, 4056 .enable_mask = BIT(0), 4057 .hw.init = &(struct clk_init_data){ 4058 .name = "gcc_usb3_sec_phy_pipe_clk", 4059 .ops = &clk_branch2_ops, 4060 }, 4061 }, 4062 }; 4063 4064 static struct clk_branch gcc_video_axi0_clk = { 4065 .halt_reg = 0xb024, 4066 .halt_check = BRANCH_HALT, 4067 .clkr = { 4068 .enable_reg = 0xb024, 4069 .enable_mask = BIT(0), 4070 .hw.init = &(struct clk_init_data){ 4071 .name = "gcc_video_axi0_clk", 4072 .ops = &clk_branch2_ops, 4073 }, 4074 }, 4075 }; 4076 4077 static struct clk_branch gcc_video_axi1_clk = { 4078 .halt_reg = 0xb028, 4079 .halt_check = BRANCH_HALT, 4080 .clkr = { 4081 .enable_reg = 0xb028, 4082 .enable_mask = BIT(0), 4083 .hw.init = &(struct clk_init_data){ 4084 .name = "gcc_video_axi1_clk", 4085 .ops = &clk_branch2_ops, 4086 }, 4087 }, 4088 }; 4089 4090 static struct clk_branch gcc_video_axic_clk = { 4091 .halt_reg = 0xb02c, 4092 .halt_check = BRANCH_HALT, 4093 .clkr = { 4094 .enable_reg = 0xb02c, 4095 .enable_mask = BIT(0), 4096 .hw.init = &(struct clk_init_data){ 4097 .name = "gcc_video_axic_clk", 4098 .ops = &clk_branch2_ops, 4099 }, 4100 }, 4101 }; 4102 4103 static struct gdsc usb30_sec_gdsc = { 4104 .gdscr = 0x10004, 4105 .pd = { 4106 .name = "usb30_sec_gdsc", 4107 }, 4108 .pwrsts = PWRSTS_OFF_ON, 4109 .flags = POLL_CFG_GDSCR, 4110 }; 4111 4112 static struct gdsc emac_gdsc = { 4113 .gdscr = 0x6004, 4114 .pd = { 4115 .name = "emac_gdsc", 4116 }, 4117 .pwrsts = PWRSTS_OFF_ON, 4118 .flags = POLL_CFG_GDSCR, 4119 }; 4120 4121 static struct gdsc usb30_prim_gdsc = { 4122 .gdscr = 0xf004, 4123 .pd = { 4124 .name = "usb30_prim_gdsc", 4125 }, 4126 .pwrsts = PWRSTS_OFF_ON, 4127 .flags = POLL_CFG_GDSCR, 4128 }; 4129 4130 static struct gdsc pcie_0_gdsc = { 4131 .gdscr = 0x6b004, 4132 .pd = { 4133 .name = "pcie_0_gdsc", 4134 }, 4135 .pwrsts = PWRSTS_OFF_ON, 4136 .flags = POLL_CFG_GDSCR, 4137 }; 4138 4139 static struct gdsc ufs_card_gdsc = { 4140 .gdscr = 0x75004, 4141 .pd = { 4142 .name = "ufs_card_gdsc", 4143 }, 4144 .pwrsts = PWRSTS_OFF_ON, 4145 .flags = POLL_CFG_GDSCR, 4146 }; 4147 4148 static struct gdsc ufs_phy_gdsc = { 4149 .gdscr = 0x77004, 4150 .pd = { 4151 .name = "ufs_phy_gdsc", 4152 }, 4153 .pwrsts = PWRSTS_OFF_ON, 4154 .flags = POLL_CFG_GDSCR, 4155 }; 4156 4157 static struct gdsc pcie_1_gdsc = { 4158 .gdscr = 0x8d004, 4159 .pd = { 4160 .name = "pcie_1_gdsc", 4161 }, 4162 .pwrsts = PWRSTS_OFF_ON, 4163 .flags = POLL_CFG_GDSCR, 4164 }; 4165 4166 static struct gdsc pcie_2_gdsc = { 4167 .gdscr = 0x9d004, 4168 .pd = { 4169 .name = "pcie_2_gdsc", 4170 }, 4171 .pwrsts = PWRSTS_OFF_ON, 4172 .flags = POLL_CFG_GDSCR, 4173 }; 4174 4175 static struct gdsc ufs_card_2_gdsc = { 4176 .gdscr = 0xa2004, 4177 .pd = { 4178 .name = "ufs_card_2_gdsc", 4179 }, 4180 .pwrsts = PWRSTS_OFF_ON, 4181 .flags = POLL_CFG_GDSCR, 4182 }; 4183 4184 static struct gdsc pcie_3_gdsc = { 4185 .gdscr = 0xa3004, 4186 .pd = { 4187 .name = "pcie_3_gdsc", 4188 }, 4189 .pwrsts = PWRSTS_OFF_ON, 4190 .flags = POLL_CFG_GDSCR, 4191 }; 4192 4193 static struct gdsc usb30_mp_gdsc = { 4194 .gdscr = 0xa6004, 4195 .pd = { 4196 .name = "usb30_mp_gdsc", 4197 }, 4198 .pwrsts = PWRSTS_OFF_ON, 4199 .flags = POLL_CFG_GDSCR, 4200 }; 4201 4202 static struct clk_regmap *gcc_sc8180x_clocks[] = { 4203 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, 4204 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, 4205 [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr, 4206 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 4207 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, 4208 [GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr, 4209 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 4210 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, 4211 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 4212 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 4213 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 4214 [GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr, 4215 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 4216 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, 4217 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, 4218 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 4219 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 4220 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, 4221 [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr, 4222 [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr, 4223 [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr, 4224 [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr, 4225 [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr, 4226 [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr, 4227 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 4228 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 4229 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 4230 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 4231 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 4232 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 4233 [GCC_GP4_CLK] = &gcc_gp4_clk.clkr, 4234 [GCC_GP4_CLK_SRC] = &gcc_gp4_clk_src.clkr, 4235 [GCC_GP5_CLK] = &gcc_gp5_clk.clkr, 4236 [GCC_GP5_CLK_SRC] = &gcc_gp5_clk_src.clkr, 4237 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 4238 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 4239 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 4240 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 4241 [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr, 4242 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, 4243 [GCC_NPU_AXI_CLK_SRC] = &gcc_npu_axi_clk_src.clkr, 4244 [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr, 4245 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr, 4246 [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr, 4247 [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr, 4248 [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr, 4249 [GCC_PCIE2_PHY_REFGEN_CLK] = &gcc_pcie2_phy_refgen_clk.clkr, 4250 [GCC_PCIE3_PHY_REFGEN_CLK] = &gcc_pcie3_phy_refgen_clk.clkr, 4251 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 4252 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 4253 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 4254 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr, 4255 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 4256 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 4257 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 4258 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 4259 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 4260 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 4261 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 4262 [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr, 4263 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 4264 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 4265 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 4266 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 4267 [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr, 4268 [GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr, 4269 [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr, 4270 [GCC_PCIE_2_CLKREF_CLK] = &gcc_pcie_2_clkref_clk.clkr, 4271 [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr, 4272 [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr, 4273 [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr, 4274 [GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr, 4275 [GCC_PCIE_3_AUX_CLK] = &gcc_pcie_3_aux_clk.clkr, 4276 [GCC_PCIE_3_AUX_CLK_SRC] = &gcc_pcie_3_aux_clk_src.clkr, 4277 [GCC_PCIE_3_CFG_AHB_CLK] = &gcc_pcie_3_cfg_ahb_clk.clkr, 4278 [GCC_PCIE_3_CLKREF_CLK] = &gcc_pcie_3_clkref_clk.clkr, 4279 [GCC_PCIE_3_MSTR_AXI_CLK] = &gcc_pcie_3_mstr_axi_clk.clkr, 4280 [GCC_PCIE_3_PIPE_CLK] = &gcc_pcie_3_pipe_clk.clkr, 4281 [GCC_PCIE_3_SLV_AXI_CLK] = &gcc_pcie_3_slv_axi_clk.clkr, 4282 [GCC_PCIE_3_SLV_Q2A_AXI_CLK] = &gcc_pcie_3_slv_q2a_axi_clk.clkr, 4283 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, 4284 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, 4285 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 4286 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 4287 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 4288 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 4289 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 4290 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 4291 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 4292 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 4293 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 4294 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 4295 [GCC_QSPI_1_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_1_cnoc_periph_ahb_clk.clkr, 4296 [GCC_QSPI_1_CORE_CLK] = &gcc_qspi_1_core_clk.clkr, 4297 [GCC_QSPI_1_CORE_CLK_SRC] = &gcc_qspi_1_core_clk_src.clkr, 4298 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, 4299 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, 4300 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, 4301 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 4302 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 4303 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 4304 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 4305 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 4306 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 4307 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 4308 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 4309 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 4310 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 4311 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 4312 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 4313 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 4314 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 4315 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 4316 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 4317 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 4318 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 4319 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 4320 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 4321 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 4322 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 4323 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 4324 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 4325 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 4326 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 4327 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 4328 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 4329 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 4330 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 4331 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 4332 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 4333 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 4334 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 4335 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 4336 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 4337 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 4338 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 4339 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 4340 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 4341 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 4342 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 4343 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 4344 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 4345 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 4346 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 4347 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 4348 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 4349 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 4350 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 4351 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 4352 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 4353 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 4354 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, 4355 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 4356 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, 4357 [GCC_UFS_CARD_2_AHB_CLK] = &gcc_ufs_card_2_ahb_clk.clkr, 4358 [GCC_UFS_CARD_2_AXI_CLK] = &gcc_ufs_card_2_axi_clk.clkr, 4359 [GCC_UFS_CARD_2_AXI_CLK_SRC] = &gcc_ufs_card_2_axi_clk_src.clkr, 4360 [GCC_UFS_CARD_2_ICE_CORE_CLK] = &gcc_ufs_card_2_ice_core_clk.clkr, 4361 [GCC_UFS_CARD_2_ICE_CORE_CLK_SRC] = &gcc_ufs_card_2_ice_core_clk_src.clkr, 4362 [GCC_UFS_CARD_2_PHY_AUX_CLK] = &gcc_ufs_card_2_phy_aux_clk.clkr, 4363 [GCC_UFS_CARD_2_PHY_AUX_CLK_SRC] = &gcc_ufs_card_2_phy_aux_clk_src.clkr, 4364 [GCC_UFS_CARD_2_RX_SYMBOL_0_CLK] = &gcc_ufs_card_2_rx_symbol_0_clk.clkr, 4365 [GCC_UFS_CARD_2_RX_SYMBOL_1_CLK] = &gcc_ufs_card_2_rx_symbol_1_clk.clkr, 4366 [GCC_UFS_CARD_2_TX_SYMBOL_0_CLK] = &gcc_ufs_card_2_tx_symbol_0_clk.clkr, 4367 [GCC_UFS_CARD_2_UNIPRO_CORE_CLK] = &gcc_ufs_card_2_unipro_core_clk.clkr, 4368 [GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_2_unipro_core_clk_src.clkr, 4369 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, 4370 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, 4371 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, 4372 [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr, 4373 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, 4374 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, 4375 [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_card_ice_core_hw_ctl_clk.clkr, 4376 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, 4377 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, 4378 [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr, 4379 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, 4380 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, 4381 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, 4382 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, 4383 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr, 4384 [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr, 4385 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 4386 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 4387 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 4388 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, 4389 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 4390 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 4391 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, 4392 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 4393 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 4394 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, 4395 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 4396 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 4397 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 4398 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 4399 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 4400 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, 4401 [GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr, 4402 [GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr, 4403 [GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr, 4404 [GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr, 4405 [GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr, 4406 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 4407 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 4408 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 4409 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 4410 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 4411 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, 4412 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, 4413 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, 4414 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr, 4415 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, 4416 [GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr, 4417 [GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr, 4418 [GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr, 4419 [GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr, 4420 [GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr, 4421 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 4422 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 4423 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 4424 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 4425 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 4426 [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr, 4427 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, 4428 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, 4429 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, 4430 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, 4431 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 4432 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 4433 [GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr, 4434 [GPLL0] = &gpll0.clkr, 4435 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 4436 [GPLL1] = &gpll1.clkr, 4437 [GPLL4] = &gpll4.clkr, 4438 [GPLL7] = &gpll7.clkr, 4439 [GPLL9] = &gpll9.clkr, 4440 }; 4441 4442 static const struct qcom_reset_map gcc_sc8180x_resets[] = { 4443 [GCC_EMAC_BCR] = { 0x6000 }, 4444 [GCC_GPU_BCR] = { 0x71000 }, 4445 [GCC_MMSS_BCR] = { 0xb000 }, 4446 [GCC_NPU_BCR] = { 0x4d000 }, 4447 [GCC_PCIE_0_BCR] = { 0x6b000 }, 4448 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 4449 [GCC_PCIE_1_BCR] = { 0x8d000 }, 4450 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 4451 [GCC_PCIE_2_BCR] = { 0x9d000 }, 4452 [GCC_PCIE_2_PHY_BCR] = { 0xa701c }, 4453 [GCC_PCIE_3_BCR] = { 0xa3000 }, 4454 [GCC_PCIE_3_PHY_BCR] = { 0xa801c }, 4455 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 4456 [GCC_PDM_BCR] = { 0x33000 }, 4457 [GCC_PRNG_BCR] = { 0x34000 }, 4458 [GCC_QSPI_1_BCR] = { 0x4a000 }, 4459 [GCC_QSPI_BCR] = { 0x24008 }, 4460 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, 4461 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 4462 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, 4463 [GCC_QUSB2PHY_5_BCR] = { 0x12010 }, 4464 [GCC_QUSB2PHY_MP0_BCR] = { 0x12008 }, 4465 [GCC_QUSB2PHY_MP1_BCR] = { 0x1200c }, 4466 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 4467 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 4468 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x50000 }, 4469 [GCC_USB3_PHY_PRIM_SP1_BCR] = { 0x50004 }, 4470 [GCC_USB3_DP_PHY_PRIM_SP0_BCR] = { 0x50010 }, 4471 [GCC_USB3_DP_PHY_PRIM_SP1_BCR] = { 0x50014 }, 4472 [GCC_USB3_PHY_SEC_BCR] = { 0x50018 }, 4473 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x5001c }, 4474 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50020 }, 4475 [GCC_SDCC2_BCR] = { 0x14000 }, 4476 [GCC_SDCC4_BCR] = { 0x16000 }, 4477 [GCC_TSIF_BCR] = { 0x36000 }, 4478 [GCC_UFS_CARD_2_BCR] = { 0xa2000 }, 4479 [GCC_UFS_CARD_BCR] = { 0x75000 }, 4480 [GCC_UFS_PHY_BCR] = { 0x77000 }, 4481 [GCC_USB30_MP_BCR] = { 0xa6000 }, 4482 [GCC_USB30_PRIM_BCR] = { 0xf000 }, 4483 [GCC_USB30_SEC_BCR] = { 0x10000 }, 4484 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 4485 [GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 }, 4486 [GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 }, 4487 [GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 }, 4488 }; 4489 4490 static struct gdsc *gcc_sc8180x_gdscs[] = { 4491 [EMAC_GDSC] = &emac_gdsc, 4492 [PCIE_0_GDSC] = &pcie_0_gdsc, 4493 [PCIE_1_GDSC] = &pcie_1_gdsc, 4494 [PCIE_2_GDSC] = &pcie_2_gdsc, 4495 [PCIE_3_GDSC] = &pcie_3_gdsc, 4496 [UFS_CARD_GDSC] = &ufs_card_gdsc, 4497 [UFS_CARD_2_GDSC] = &ufs_card_2_gdsc, 4498 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 4499 [USB30_MP_GDSC] = &usb30_mp_gdsc, 4500 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 4501 [USB30_SEC_GDSC] = &usb30_sec_gdsc, 4502 }; 4503 4504 static const struct regmap_config gcc_sc8180x_regmap_config = { 4505 .reg_bits = 32, 4506 .reg_stride = 4, 4507 .val_bits = 32, 4508 .max_register = 0xc0004, 4509 .fast_io = true, 4510 }; 4511 4512 static const struct qcom_cc_desc gcc_sc8180x_desc = { 4513 .config = &gcc_sc8180x_regmap_config, 4514 .clks = gcc_sc8180x_clocks, 4515 .num_clks = ARRAY_SIZE(gcc_sc8180x_clocks), 4516 .resets = gcc_sc8180x_resets, 4517 .num_resets = ARRAY_SIZE(gcc_sc8180x_resets), 4518 .gdscs = gcc_sc8180x_gdscs, 4519 .num_gdscs = ARRAY_SIZE(gcc_sc8180x_gdscs), 4520 }; 4521 4522 static const struct of_device_id gcc_sc8180x_match_table[] = { 4523 { .compatible = "qcom,gcc-sc8180x" }, 4524 { } 4525 }; 4526 MODULE_DEVICE_TABLE(of, gcc_sc8180x_match_table); 4527 4528 static int gcc_sc8180x_probe(struct platform_device *pdev) 4529 { 4530 struct regmap *regmap; 4531 4532 regmap = qcom_cc_map(pdev, &gcc_sc8180x_desc); 4533 if (IS_ERR(regmap)) 4534 return PTR_ERR(regmap); 4535 4536 /* 4537 * Enable the following always-on clocks: 4538 * GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK, 4539 * GCC_VIDEO_XO_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_XO_CLK, 4540 * GCC_CPUSS_GNOC_CLK, GCC_CPUSS_DVM_BUS_CLK, GCC_NPU_CFG_AHB_CLK and 4541 * GCC_GPU_CFG_AHB_CLK 4542 */ 4543 regmap_update_bits(regmap, 0xb004, BIT(0), BIT(0)); 4544 regmap_update_bits(regmap, 0xb008, BIT(0), BIT(0)); 4545 regmap_update_bits(regmap, 0xb00c, BIT(0), BIT(0)); 4546 regmap_update_bits(regmap, 0xb040, BIT(0), BIT(0)); 4547 regmap_update_bits(regmap, 0xb044, BIT(0), BIT(0)); 4548 regmap_update_bits(regmap, 0xb048, BIT(0), BIT(0)); 4549 regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); 4550 regmap_update_bits(regmap, 0x48190, BIT(0), BIT(0)); 4551 regmap_update_bits(regmap, 0x4d004, BIT(0), BIT(0)); 4552 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 4553 4554 /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ 4555 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); 4556 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 4557 4558 return qcom_cc_really_probe(pdev, &gcc_sc8180x_desc, regmap); 4559 } 4560 4561 static struct platform_driver gcc_sc8180x_driver = { 4562 .probe = gcc_sc8180x_probe, 4563 .driver = { 4564 .name = "gcc-sc8180x", 4565 .of_match_table = gcc_sc8180x_match_table, 4566 }, 4567 }; 4568 4569 static int __init gcc_sc8180x_init(void) 4570 { 4571 return platform_driver_register(&gcc_sc8180x_driver); 4572 } 4573 core_initcall(gcc_sc8180x_init); 4574 4575 static void __exit gcc_sc8180x_exit(void) 4576 { 4577 platform_driver_unregister(&gcc_sc8180x_driver); 4578 } 4579 module_exit(gcc_sc8180x_exit); 4580 4581 MODULE_DESCRIPTION("QTI GCC SC8180x driver"); 4582 MODULE_LICENSE("GPL v2"); 4583