1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/kernel.h> 8 #include <linux/module.h> 9 #include <linux/of_device.h> 10 #include <linux/of.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/clock/qcom,gcc-sc7280.h> 14 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap-divider.h" 19 #include "clk-regmap-mux.h" 20 #include "common.h" 21 #include "gdsc.h" 22 #include "reset.h" 23 24 enum { 25 P_BI_TCXO, 26 P_GCC_GPLL0_OUT_EVEN, 27 P_GCC_GPLL0_OUT_MAIN, 28 P_GCC_GPLL0_OUT_ODD, 29 P_GCC_GPLL10_OUT_MAIN, 30 P_GCC_GPLL4_OUT_MAIN, 31 P_GCC_GPLL9_OUT_MAIN, 32 P_PCIE_0_PIPE_CLK, 33 P_PCIE_1_PIPE_CLK, 34 P_SLEEP_CLK, 35 P_UFS_PHY_RX_SYMBOL_0_CLK, 36 P_UFS_PHY_RX_SYMBOL_1_CLK, 37 P_UFS_PHY_TX_SYMBOL_0_CLK, 38 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 39 P_GCC_MSS_GPLL0_MAIN_DIV_CLK, 40 }; 41 42 static struct clk_alpha_pll gcc_gpll0 = { 43 .offset = 0x0, 44 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 45 .clkr = { 46 .enable_reg = 0x52010, 47 .enable_mask = BIT(0), 48 .hw.init = &(struct clk_init_data){ 49 .name = "gcc_gpll0", 50 .parent_data = &(const struct clk_parent_data){ 51 .fw_name = "bi_tcxo", 52 }, 53 .num_parents = 1, 54 .ops = &clk_alpha_pll_fixed_lucid_ops, 55 }, 56 }, 57 }; 58 59 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 60 { 0x1, 2 }, 61 { } 62 }; 63 64 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 65 .offset = 0x0, 66 .post_div_shift = 8, 67 .post_div_table = post_div_table_gcc_gpll0_out_even, 68 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 69 .width = 4, 70 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 71 .clkr.hw.init = &(struct clk_init_data){ 72 .name = "gcc_gpll0_out_even", 73 .parent_hws = (const struct clk_hw*[]){ 74 &gcc_gpll0.clkr.hw, 75 }, 76 .num_parents = 1, 77 .ops = &clk_alpha_pll_postdiv_lucid_ops, 78 }, 79 }; 80 81 static const struct clk_div_table post_div_table_gcc_gpll0_out_odd[] = { 82 { 0x3, 3 }, 83 { } 84 }; 85 86 static struct clk_alpha_pll_postdiv gcc_gpll0_out_odd = { 87 .offset = 0x0, 88 .post_div_shift = 12, 89 .post_div_table = post_div_table_gcc_gpll0_out_odd, 90 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_odd), 91 .width = 4, 92 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 93 .clkr.hw.init = &(struct clk_init_data){ 94 .name = "gcc_gpll0_out_odd", 95 .parent_hws = (const struct clk_hw*[]){ 96 &gcc_gpll0.clkr.hw, 97 }, 98 .num_parents = 1, 99 .ops = &clk_alpha_pll_postdiv_lucid_ops, 100 }, 101 }; 102 103 static struct clk_alpha_pll gcc_gpll1 = { 104 .offset = 0x1000, 105 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 106 .clkr = { 107 .enable_reg = 0x52010, 108 .enable_mask = BIT(1), 109 .hw.init = &(struct clk_init_data){ 110 .name = "gcc_gpll1", 111 .parent_data = &(const struct clk_parent_data){ 112 .fw_name = "bi_tcxo", 113 }, 114 .num_parents = 1, 115 .ops = &clk_alpha_pll_fixed_lucid_ops, 116 }, 117 }, 118 }; 119 120 static struct clk_alpha_pll gcc_gpll10 = { 121 .offset = 0x1e000, 122 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 123 .clkr = { 124 .enable_reg = 0x52010, 125 .enable_mask = BIT(9), 126 .hw.init = &(struct clk_init_data){ 127 .name = "gcc_gpll10", 128 .parent_data = &(const struct clk_parent_data){ 129 .fw_name = "bi_tcxo", 130 }, 131 .num_parents = 1, 132 .ops = &clk_alpha_pll_fixed_lucid_ops, 133 }, 134 }, 135 }; 136 137 static struct clk_alpha_pll gcc_gpll4 = { 138 .offset = 0x76000, 139 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 140 .clkr = { 141 .enable_reg = 0x52010, 142 .enable_mask = BIT(4), 143 .hw.init = &(struct clk_init_data){ 144 .name = "gcc_gpll4", 145 .parent_data = &(const struct clk_parent_data){ 146 .fw_name = "bi_tcxo", 147 }, 148 .num_parents = 1, 149 .ops = &clk_alpha_pll_fixed_lucid_ops, 150 }, 151 }, 152 }; 153 154 static struct clk_alpha_pll gcc_gpll9 = { 155 .offset = 0x1c000, 156 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 157 .clkr = { 158 .enable_reg = 0x52010, 159 .enable_mask = BIT(8), 160 .hw.init = &(struct clk_init_data){ 161 .name = "gcc_gpll9", 162 .parent_data = &(const struct clk_parent_data){ 163 .fw_name = "bi_tcxo", 164 }, 165 .num_parents = 1, 166 .ops = &clk_alpha_pll_fixed_lucid_ops, 167 }, 168 }, 169 }; 170 171 static struct clk_branch gcc_mss_gpll0_main_div_clk_src = { 172 .halt_check = BRANCH_HALT_DELAY, 173 .clkr = { 174 .enable_reg = 0x52000, 175 .enable_mask = BIT(17), 176 .hw.init = &(struct clk_init_data){ 177 .name = "gcc_mss_gpll0_main_div_clk_src", 178 .parent_hws = (const struct clk_hw*[]){ 179 &gcc_gpll0_out_even.clkr.hw, 180 }, 181 .num_parents = 1, 182 .flags = CLK_SET_RATE_PARENT, 183 .ops = &clk_branch2_ops, 184 }, 185 }, 186 }; 187 188 static const struct parent_map gcc_parent_map_0[] = { 189 { P_BI_TCXO, 0 }, 190 { P_GCC_GPLL0_OUT_MAIN, 1 }, 191 { P_GCC_GPLL0_OUT_EVEN, 6 }, 192 }; 193 194 static const struct clk_parent_data gcc_parent_data_0[] = { 195 { .fw_name = "bi_tcxo" }, 196 { .hw = &gcc_gpll0.clkr.hw }, 197 { .hw = &gcc_gpll0_out_even.clkr.hw }, 198 }; 199 200 static const struct parent_map gcc_parent_map_1[] = { 201 { P_BI_TCXO, 0 }, 202 { P_GCC_GPLL0_OUT_MAIN, 1 }, 203 { P_GCC_GPLL0_OUT_ODD, 3 }, 204 { P_GCC_GPLL0_OUT_EVEN, 6 }, 205 }; 206 207 static const struct clk_parent_data gcc_parent_data_1[] = { 208 { .fw_name = "bi_tcxo" }, 209 { .hw = &gcc_gpll0.clkr.hw }, 210 { .hw = &gcc_gpll0_out_odd.clkr.hw }, 211 { .hw = &gcc_gpll0_out_even.clkr.hw }, 212 }; 213 214 static const struct parent_map gcc_parent_map_2[] = { 215 { P_BI_TCXO, 0 }, 216 { P_SLEEP_CLK, 5 }, 217 }; 218 219 static const struct clk_parent_data gcc_parent_data_2[] = { 220 { .fw_name = "bi_tcxo" }, 221 { .fw_name = "sleep_clk" }, 222 }; 223 224 static const struct parent_map gcc_parent_map_3[] = { 225 { P_BI_TCXO, 0 }, 226 }; 227 228 static const struct clk_parent_data gcc_parent_data_3[] = { 229 { .fw_name = "bi_tcxo" }, 230 }; 231 232 static const struct parent_map gcc_parent_map_4[] = { 233 { P_BI_TCXO, 0 }, 234 { P_GCC_GPLL0_OUT_MAIN, 1 }, 235 { P_GCC_GPLL0_OUT_ODD, 3 }, 236 { P_SLEEP_CLK, 5 }, 237 { P_GCC_GPLL0_OUT_EVEN, 6 }, 238 }; 239 240 static const struct clk_parent_data gcc_parent_data_4[] = { 241 { .fw_name = "bi_tcxo" }, 242 { .hw = &gcc_gpll0.clkr.hw }, 243 { .hw = &gcc_gpll0_out_odd.clkr.hw }, 244 { .fw_name = "sleep_clk" }, 245 { .hw = &gcc_gpll0_out_even.clkr.hw }, 246 }; 247 248 static const struct parent_map gcc_parent_map_5[] = { 249 { P_BI_TCXO, 0 }, 250 { P_GCC_GPLL0_OUT_EVEN, 6 }, 251 }; 252 253 static const struct clk_parent_data gcc_parent_data_5[] = { 254 { .fw_name = "bi_tcxo" }, 255 { .hw = &gcc_gpll0_out_even.clkr.hw }, 256 }; 257 258 static const struct parent_map gcc_parent_map_6[] = { 259 { P_PCIE_0_PIPE_CLK, 0 }, 260 { P_BI_TCXO, 2 }, 261 }; 262 263 static const struct clk_parent_data gcc_parent_data_6[] = { 264 { .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" }, 265 { .fw_name = "bi_tcxo" }, 266 }; 267 268 static const struct parent_map gcc_parent_map_7[] = { 269 { P_PCIE_1_PIPE_CLK, 0 }, 270 { P_BI_TCXO, 2 }, 271 }; 272 273 static const struct clk_parent_data gcc_parent_data_7[] = { 274 { .fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk" }, 275 { .fw_name = "bi_tcxo" }, 276 }; 277 278 static const struct parent_map gcc_parent_map_8[] = { 279 { P_BI_TCXO, 0 }, 280 { P_GCC_GPLL0_OUT_MAIN, 1 }, 281 { P_GCC_GPLL0_OUT_ODD, 3 }, 282 { P_GCC_GPLL10_OUT_MAIN, 5 }, 283 { P_GCC_GPLL0_OUT_EVEN, 6 }, 284 }; 285 286 static const struct clk_parent_data gcc_parent_data_8[] = { 287 { .fw_name = "bi_tcxo" }, 288 { .hw = &gcc_gpll0.clkr.hw }, 289 { .hw = &gcc_gpll0_out_odd.clkr.hw }, 290 { .hw = &gcc_gpll10.clkr.hw }, 291 { .hw = &gcc_gpll0_out_even.clkr.hw }, 292 }; 293 294 static const struct parent_map gcc_parent_map_9[] = { 295 { P_BI_TCXO, 0 }, 296 { P_GCC_GPLL0_OUT_MAIN, 1 }, 297 { P_GCC_GPLL9_OUT_MAIN, 2 }, 298 { P_GCC_GPLL0_OUT_ODD, 3 }, 299 { P_GCC_GPLL4_OUT_MAIN, 5 }, 300 { P_GCC_GPLL0_OUT_EVEN, 6 }, 301 }; 302 303 static const struct clk_parent_data gcc_parent_data_9[] = { 304 { .fw_name = "bi_tcxo" }, 305 { .hw = &gcc_gpll0.clkr.hw }, 306 { .hw = &gcc_gpll9.clkr.hw }, 307 { .hw = &gcc_gpll0_out_odd.clkr.hw }, 308 { .hw = &gcc_gpll4.clkr.hw }, 309 { .hw = &gcc_gpll0_out_even.clkr.hw }, 310 }; 311 312 static const struct parent_map gcc_parent_map_10[] = { 313 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, 314 { P_BI_TCXO, 2 }, 315 }; 316 317 static const struct clk_parent_data gcc_parent_data_10[] = { 318 { .fw_name = "ufs_phy_rx_symbol_0_clk" }, 319 { .fw_name = "bi_tcxo" }, 320 }; 321 322 static const struct parent_map gcc_parent_map_11[] = { 323 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, 324 { P_BI_TCXO, 2 }, 325 }; 326 327 static const struct clk_parent_data gcc_parent_data_11[] = { 328 { .fw_name = "ufs_phy_rx_symbol_1_clk" }, 329 { .fw_name = "bi_tcxo" }, 330 }; 331 332 static const struct parent_map gcc_parent_map_12[] = { 333 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, 334 { P_BI_TCXO, 2 }, 335 }; 336 337 static const struct clk_parent_data gcc_parent_data_12[] = { 338 { .fw_name = "ufs_phy_tx_symbol_0_clk" }, 339 { .fw_name = "bi_tcxo" }, 340 }; 341 342 static const struct parent_map gcc_parent_map_13[] = { 343 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 344 { P_BI_TCXO, 2 }, 345 }; 346 347 static const struct clk_parent_data gcc_parent_data_13[] = { 348 { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" }, 349 { .fw_name = "bi_tcxo" }, 350 }; 351 352 static const struct parent_map gcc_parent_map_14[] = { 353 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 354 { P_BI_TCXO, 2 }, 355 }; 356 357 static const struct clk_parent_data gcc_parent_data_14[] = { 358 { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" }, 359 { .fw_name = "bi_tcxo" }, 360 }; 361 362 static const struct parent_map gcc_parent_map_15[] = { 363 { P_BI_TCXO, 0 }, 364 { P_GCC_MSS_GPLL0_MAIN_DIV_CLK, 1 }, 365 }; 366 367 static const struct clk_parent_data gcc_parent_data_15[] = { 368 { .fw_name = "bi_tcxo" }, 369 { .hw = &gcc_mss_gpll0_main_div_clk_src.clkr.hw }, 370 }; 371 372 static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { 373 .reg = 0x6b054, 374 .shift = 0, 375 .width = 2, 376 .safe_src_parent = P_BI_TCXO, 377 .parent_map = gcc_parent_map_6, 378 .clkr = { 379 .hw.init = &(struct clk_init_data){ 380 .name = "gcc_pcie_0_pipe_clk_src", 381 .parent_data = gcc_parent_data_6, 382 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 383 .ops = &clk_regmap_mux_safe_ops, 384 }, 385 }, 386 }; 387 388 static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { 389 .reg = 0x8d054, 390 .shift = 0, 391 .width = 2, 392 .safe_src_parent = P_BI_TCXO, 393 .parent_map = gcc_parent_map_7, 394 .clkr = { 395 .hw.init = &(struct clk_init_data){ 396 .name = "gcc_pcie_1_pipe_clk_src", 397 .parent_data = gcc_parent_data_7, 398 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 399 .ops = &clk_regmap_mux_safe_ops, 400 }, 401 }, 402 }; 403 404 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 405 .reg = 0x77058, 406 .shift = 0, 407 .width = 2, 408 .parent_map = gcc_parent_map_10, 409 .clkr = { 410 .hw.init = &(struct clk_init_data){ 411 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 412 .parent_data = gcc_parent_data_10, 413 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 414 .ops = &clk_regmap_mux_closest_ops, 415 }, 416 }, 417 }; 418 419 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 420 .reg = 0x770c8, 421 .shift = 0, 422 .width = 2, 423 .parent_map = gcc_parent_map_11, 424 .clkr = { 425 .hw.init = &(struct clk_init_data){ 426 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 427 .parent_data = gcc_parent_data_11, 428 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 429 .ops = &clk_regmap_mux_closest_ops, 430 }, 431 }, 432 }; 433 434 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 435 .reg = 0x77048, 436 .shift = 0, 437 .width = 2, 438 .parent_map = gcc_parent_map_12, 439 .clkr = { 440 .hw.init = &(struct clk_init_data){ 441 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 442 .parent_data = gcc_parent_data_12, 443 .num_parents = ARRAY_SIZE(gcc_parent_data_12), 444 .ops = &clk_regmap_mux_closest_ops, 445 }, 446 }, 447 }; 448 449 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 450 .reg = 0xf060, 451 .shift = 0, 452 .width = 2, 453 .parent_map = gcc_parent_map_13, 454 .clkr = { 455 .hw.init = &(struct clk_init_data){ 456 .name = "gcc_usb3_prim_phy_pipe_clk_src", 457 .parent_data = gcc_parent_data_13, 458 .num_parents = ARRAY_SIZE(gcc_parent_data_13), 459 .ops = &clk_regmap_mux_closest_ops, 460 }, 461 }, 462 }; 463 464 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = { 465 .reg = 0x9e060, 466 .shift = 0, 467 .width = 2, 468 .parent_map = gcc_parent_map_14, 469 .clkr = { 470 .hw.init = &(struct clk_init_data){ 471 .name = "gcc_usb3_sec_phy_pipe_clk_src", 472 .parent_data = gcc_parent_data_14, 473 .num_parents = ARRAY_SIZE(gcc_parent_data_14), 474 .ops = &clk_regmap_mux_closest_ops, 475 }, 476 }, 477 }; 478 479 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 480 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 481 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 482 F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0), 483 { } 484 }; 485 486 static struct clk_rcg2 gcc_gp1_clk_src = { 487 .cmd_rcgr = 0x64004, 488 .mnd_width = 16, 489 .hid_width = 5, 490 .parent_map = gcc_parent_map_4, 491 .freq_tbl = ftbl_gcc_gp1_clk_src, 492 .clkr.hw.init = &(struct clk_init_data){ 493 .name = "gcc_gp1_clk_src", 494 .parent_data = gcc_parent_data_4, 495 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 496 .ops = &clk_rcg2_ops, 497 }, 498 }; 499 500 static struct clk_rcg2 gcc_gp2_clk_src = { 501 .cmd_rcgr = 0x65004, 502 .mnd_width = 16, 503 .hid_width = 5, 504 .parent_map = gcc_parent_map_4, 505 .freq_tbl = ftbl_gcc_gp1_clk_src, 506 .clkr.hw.init = &(struct clk_init_data){ 507 .name = "gcc_gp2_clk_src", 508 .parent_data = gcc_parent_data_4, 509 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 510 .ops = &clk_rcg2_ops, 511 }, 512 }; 513 514 static struct clk_rcg2 gcc_gp3_clk_src = { 515 .cmd_rcgr = 0x66004, 516 .mnd_width = 16, 517 .hid_width = 5, 518 .parent_map = gcc_parent_map_4, 519 .freq_tbl = ftbl_gcc_gp1_clk_src, 520 .clkr.hw.init = &(struct clk_init_data){ 521 .name = "gcc_gp3_clk_src", 522 .parent_data = gcc_parent_data_4, 523 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 524 .ops = &clk_rcg2_ops, 525 }, 526 }; 527 528 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 529 F(9600000, P_BI_TCXO, 2, 0, 0), 530 F(19200000, P_BI_TCXO, 1, 0, 0), 531 { } 532 }; 533 534 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 535 .cmd_rcgr = 0x6b058, 536 .mnd_width = 16, 537 .hid_width = 5, 538 .parent_map = gcc_parent_map_2, 539 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 540 .clkr.hw.init = &(struct clk_init_data){ 541 .name = "gcc_pcie_0_aux_clk_src", 542 .parent_data = gcc_parent_data_2, 543 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 544 .ops = &clk_rcg2_ops, 545 }, 546 }; 547 548 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 549 F(19200000, P_BI_TCXO, 1, 0, 0), 550 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 551 { } 552 }; 553 554 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 555 .cmd_rcgr = 0x6b03c, 556 .mnd_width = 0, 557 .hid_width = 5, 558 .parent_map = gcc_parent_map_0, 559 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 560 .clkr.hw.init = &(struct clk_init_data){ 561 .name = "gcc_pcie_0_phy_rchng_clk_src", 562 .parent_data = gcc_parent_data_0, 563 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 564 .ops = &clk_rcg2_ops, 565 }, 566 }; 567 568 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 569 .cmd_rcgr = 0x8d058, 570 .mnd_width = 16, 571 .hid_width = 5, 572 .parent_map = gcc_parent_map_2, 573 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 574 .clkr.hw.init = &(struct clk_init_data){ 575 .name = "gcc_pcie_1_aux_clk_src", 576 .parent_data = gcc_parent_data_2, 577 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 578 .ops = &clk_rcg2_ops, 579 }, 580 }; 581 582 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 583 .cmd_rcgr = 0x8d03c, 584 .mnd_width = 0, 585 .hid_width = 5, 586 .parent_map = gcc_parent_map_0, 587 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 588 .clkr.hw.init = &(struct clk_init_data){ 589 .name = "gcc_pcie_1_phy_rchng_clk_src", 590 .parent_data = gcc_parent_data_0, 591 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 592 .flags = CLK_SET_RATE_PARENT, 593 .ops = &clk_rcg2_ops, 594 }, 595 }; 596 597 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 598 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0), 599 { } 600 }; 601 602 static struct clk_rcg2 gcc_pdm2_clk_src = { 603 .cmd_rcgr = 0x33010, 604 .mnd_width = 0, 605 .hid_width = 5, 606 .parent_map = gcc_parent_map_0, 607 .freq_tbl = ftbl_gcc_pdm2_clk_src, 608 .clkr.hw.init = &(struct clk_init_data){ 609 .name = "gcc_pdm2_clk_src", 610 .parent_data = gcc_parent_data_0, 611 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 612 .flags = CLK_SET_RATE_PARENT, 613 .ops = &clk_rcg2_ops, 614 }, 615 }; 616 617 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { 618 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 619 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 620 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 621 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 622 { } 623 }; 624 625 static struct clk_rcg2 gcc_qspi_core_clk_src = { 626 .cmd_rcgr = 0x4b00c, 627 .mnd_width = 0, 628 .hid_width = 5, 629 .parent_map = gcc_parent_map_0, 630 .freq_tbl = ftbl_gcc_qspi_core_clk_src, 631 .clkr.hw.init = &(struct clk_init_data){ 632 .name = "gcc_qspi_core_clk_src", 633 .parent_data = gcc_parent_data_0, 634 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 635 .ops = &clk_rcg2_floor_ops, 636 }, 637 }; 638 639 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 640 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 641 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 642 F(19200000, P_BI_TCXO, 1, 0, 0), 643 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 644 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 645 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 646 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 647 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 648 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 649 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 650 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 651 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 652 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 653 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 654 F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0), 655 { } 656 }; 657 658 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 659 .name = "gcc_qupv3_wrap0_s0_clk_src", 660 .parent_data = gcc_parent_data_0, 661 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 662 .ops = &clk_rcg2_ops, 663 }; 664 665 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 666 .cmd_rcgr = 0x17010, 667 .mnd_width = 16, 668 .hid_width = 5, 669 .parent_map = gcc_parent_map_0, 670 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 671 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 672 }; 673 674 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 675 .name = "gcc_qupv3_wrap0_s1_clk_src", 676 .parent_data = gcc_parent_data_0, 677 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 678 .ops = &clk_rcg2_ops, 679 }; 680 681 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 682 .cmd_rcgr = 0x17140, 683 .mnd_width = 16, 684 .hid_width = 5, 685 .parent_map = gcc_parent_map_0, 686 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 687 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 688 }; 689 690 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = { 691 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 692 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 693 F(19200000, P_BI_TCXO, 1, 0, 0), 694 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 695 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 696 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 697 F(52174000, P_GCC_GPLL0_OUT_MAIN, 1, 2, 23), 698 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 699 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 700 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 701 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 702 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 703 { } 704 }; 705 706 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 707 .name = "gcc_qupv3_wrap0_s2_clk_src", 708 .parent_data = gcc_parent_data_0, 709 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 710 .ops = &clk_rcg2_ops, 711 }; 712 713 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 714 .cmd_rcgr = 0x17270, 715 .mnd_width = 16, 716 .hid_width = 5, 717 .parent_map = gcc_parent_map_0, 718 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 719 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 720 }; 721 722 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 723 .name = "gcc_qupv3_wrap0_s3_clk_src", 724 .parent_data = gcc_parent_data_0, 725 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 726 .ops = &clk_rcg2_ops, 727 }; 728 729 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 730 .cmd_rcgr = 0x173a0, 731 .mnd_width = 16, 732 .hid_width = 5, 733 .parent_map = gcc_parent_map_0, 734 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 735 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 736 }; 737 738 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 739 .name = "gcc_qupv3_wrap0_s4_clk_src", 740 .parent_data = gcc_parent_data_0, 741 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 742 .ops = &clk_rcg2_ops, 743 }; 744 745 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 746 .cmd_rcgr = 0x174d0, 747 .mnd_width = 16, 748 .hid_width = 5, 749 .parent_map = gcc_parent_map_0, 750 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 751 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 752 }; 753 754 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 755 .name = "gcc_qupv3_wrap0_s5_clk_src", 756 .parent_data = gcc_parent_data_0, 757 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 758 .ops = &clk_rcg2_ops, 759 }; 760 761 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 762 .cmd_rcgr = 0x17600, 763 .mnd_width = 16, 764 .hid_width = 5, 765 .parent_map = gcc_parent_map_0, 766 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 767 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 768 }; 769 770 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 771 .name = "gcc_qupv3_wrap0_s6_clk_src", 772 .parent_data = gcc_parent_data_0, 773 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 774 .ops = &clk_rcg2_ops, 775 }; 776 777 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 778 .cmd_rcgr = 0x17730, 779 .mnd_width = 16, 780 .hid_width = 5, 781 .parent_map = gcc_parent_map_0, 782 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 783 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 784 }; 785 786 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 787 .name = "gcc_qupv3_wrap0_s7_clk_src", 788 .parent_data = gcc_parent_data_0, 789 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 790 .ops = &clk_rcg2_ops, 791 }; 792 793 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 794 .cmd_rcgr = 0x17860, 795 .mnd_width = 16, 796 .hid_width = 5, 797 .parent_map = gcc_parent_map_0, 798 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 799 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 800 }; 801 802 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 803 .name = "gcc_qupv3_wrap1_s0_clk_src", 804 .parent_data = gcc_parent_data_0, 805 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 806 .ops = &clk_rcg2_ops, 807 }; 808 809 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 810 .cmd_rcgr = 0x18010, 811 .mnd_width = 16, 812 .hid_width = 5, 813 .parent_map = gcc_parent_map_0, 814 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 815 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 816 }; 817 818 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 819 .name = "gcc_qupv3_wrap1_s1_clk_src", 820 .parent_data = gcc_parent_data_0, 821 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 822 .ops = &clk_rcg2_ops, 823 }; 824 825 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 826 .cmd_rcgr = 0x18140, 827 .mnd_width = 16, 828 .hid_width = 5, 829 .parent_map = gcc_parent_map_0, 830 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 831 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 832 }; 833 834 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 835 .name = "gcc_qupv3_wrap1_s2_clk_src", 836 .parent_data = gcc_parent_data_0, 837 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 838 .ops = &clk_rcg2_ops, 839 }; 840 841 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 842 .cmd_rcgr = 0x18270, 843 .mnd_width = 16, 844 .hid_width = 5, 845 .parent_map = gcc_parent_map_0, 846 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 847 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 848 }; 849 850 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 851 .name = "gcc_qupv3_wrap1_s3_clk_src", 852 .parent_data = gcc_parent_data_0, 853 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 854 .ops = &clk_rcg2_ops, 855 }; 856 857 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 858 .cmd_rcgr = 0x183a0, 859 .mnd_width = 16, 860 .hid_width = 5, 861 .parent_map = gcc_parent_map_0, 862 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 863 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 864 }; 865 866 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 867 .name = "gcc_qupv3_wrap1_s4_clk_src", 868 .parent_data = gcc_parent_data_0, 869 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 870 .ops = &clk_rcg2_ops, 871 }; 872 873 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 874 .cmd_rcgr = 0x184d0, 875 .mnd_width = 16, 876 .hid_width = 5, 877 .parent_map = gcc_parent_map_0, 878 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 879 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 880 }; 881 882 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 883 .name = "gcc_qupv3_wrap1_s5_clk_src", 884 .parent_data = gcc_parent_data_0, 885 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 886 .ops = &clk_rcg2_ops, 887 }; 888 889 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 890 .cmd_rcgr = 0x18600, 891 .mnd_width = 16, 892 .hid_width = 5, 893 .parent_map = gcc_parent_map_0, 894 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 895 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 896 }; 897 898 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 899 .name = "gcc_qupv3_wrap1_s6_clk_src", 900 .parent_data = gcc_parent_data_0, 901 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 902 .ops = &clk_rcg2_ops, 903 }; 904 905 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 906 .cmd_rcgr = 0x18730, 907 .mnd_width = 16, 908 .hid_width = 5, 909 .parent_map = gcc_parent_map_0, 910 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 911 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 912 }; 913 914 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 915 .name = "gcc_qupv3_wrap1_s7_clk_src", 916 .parent_data = gcc_parent_data_0, 917 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 918 .ops = &clk_rcg2_ops, 919 }; 920 921 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 922 .cmd_rcgr = 0x18860, 923 .mnd_width = 16, 924 .hid_width = 5, 925 .parent_map = gcc_parent_map_0, 926 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 927 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 928 }; 929 930 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 931 F(144000, P_BI_TCXO, 16, 3, 25), 932 F(400000, P_BI_TCXO, 12, 1, 4), 933 F(19200000, P_BI_TCXO, 1, 0, 0), 934 F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3), 935 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 936 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 937 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 938 F(192000000, P_GCC_GPLL10_OUT_MAIN, 2, 0, 0), 939 F(384000000, P_GCC_GPLL10_OUT_MAIN, 1, 0, 0), 940 { } 941 }; 942 943 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 944 .cmd_rcgr = 0x7500c, 945 .mnd_width = 8, 946 .hid_width = 5, 947 .parent_map = gcc_parent_map_8, 948 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 949 .clkr.hw.init = &(struct clk_init_data){ 950 .name = "gcc_sdcc1_apps_clk_src", 951 .parent_data = gcc_parent_data_8, 952 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 953 .ops = &clk_rcg2_floor_ops, 954 }, 955 }; 956 957 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 958 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 959 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 960 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0), 961 { } 962 }; 963 964 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 965 .cmd_rcgr = 0x7502c, 966 .mnd_width = 0, 967 .hid_width = 5, 968 .parent_map = gcc_parent_map_1, 969 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 970 .clkr.hw.init = &(struct clk_init_data){ 971 .name = "gcc_sdcc1_ice_core_clk_src", 972 .parent_data = gcc_parent_data_1, 973 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 974 .ops = &clk_rcg2_floor_ops, 975 }, 976 }; 977 978 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 979 F(400000, P_BI_TCXO, 12, 1, 4), 980 F(19200000, P_BI_TCXO, 1, 0, 0), 981 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 982 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 983 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 984 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 985 { } 986 }; 987 988 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 989 .cmd_rcgr = 0x1400c, 990 .mnd_width = 8, 991 .hid_width = 5, 992 .parent_map = gcc_parent_map_9, 993 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 994 .clkr.hw.init = &(struct clk_init_data){ 995 .name = "gcc_sdcc2_apps_clk_src", 996 .parent_data = gcc_parent_data_9, 997 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 998 .flags = CLK_OPS_PARENT_ENABLE, 999 .ops = &clk_rcg2_floor_ops, 1000 }, 1001 }; 1002 1003 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 1004 F(400000, P_BI_TCXO, 12, 1, 4), 1005 F(19200000, P_BI_TCXO, 1, 0, 0), 1006 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1007 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 1008 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1009 { } 1010 }; 1011 1012 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 1013 .cmd_rcgr = 0x1600c, 1014 .mnd_width = 8, 1015 .hid_width = 5, 1016 .parent_map = gcc_parent_map_1, 1017 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 1018 .clkr.hw.init = &(struct clk_init_data){ 1019 .name = "gcc_sdcc4_apps_clk_src", 1020 .parent_data = gcc_parent_data_1, 1021 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1022 .ops = &clk_rcg2_floor_ops, 1023 }, 1024 }; 1025 1026 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1027 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1028 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1029 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 1030 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0), 1031 { } 1032 }; 1033 1034 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1035 .cmd_rcgr = 0x77024, 1036 .mnd_width = 8, 1037 .hid_width = 5, 1038 .parent_map = gcc_parent_map_0, 1039 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1040 .clkr.hw.init = &(struct clk_init_data){ 1041 .name = "gcc_ufs_phy_axi_clk_src", 1042 .parent_data = gcc_parent_data_0, 1043 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1044 .ops = &clk_rcg2_ops, 1045 }, 1046 }; 1047 1048 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1049 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1050 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 1051 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0), 1052 { } 1053 }; 1054 1055 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1056 .cmd_rcgr = 0x7706c, 1057 .mnd_width = 0, 1058 .hid_width = 5, 1059 .parent_map = gcc_parent_map_0, 1060 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1061 .clkr.hw.init = &(struct clk_init_data){ 1062 .name = "gcc_ufs_phy_ice_core_clk_src", 1063 .parent_data = gcc_parent_data_0, 1064 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1065 .ops = &clk_rcg2_ops, 1066 }, 1067 }; 1068 1069 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1070 .cmd_rcgr = 0x770a0, 1071 .mnd_width = 0, 1072 .hid_width = 5, 1073 .parent_map = gcc_parent_map_3, 1074 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1075 .clkr.hw.init = &(struct clk_init_data){ 1076 .name = "gcc_ufs_phy_phy_aux_clk_src", 1077 .parent_data = gcc_parent_data_3, 1078 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1079 .ops = &clk_rcg2_ops, 1080 }, 1081 }; 1082 1083 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1084 .cmd_rcgr = 0x77084, 1085 .mnd_width = 0, 1086 .hid_width = 5, 1087 .parent_map = gcc_parent_map_0, 1088 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1089 .clkr.hw.init = &(struct clk_init_data){ 1090 .name = "gcc_ufs_phy_unipro_core_clk_src", 1091 .parent_data = gcc_parent_data_0, 1092 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1093 .ops = &clk_rcg2_ops, 1094 }, 1095 }; 1096 1097 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1098 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 1099 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1100 F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0), 1101 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1102 { } 1103 }; 1104 1105 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1106 .cmd_rcgr = 0xf020, 1107 .mnd_width = 8, 1108 .hid_width = 5, 1109 .parent_map = gcc_parent_map_1, 1110 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1111 .clkr.hw.init = &(struct clk_init_data){ 1112 .name = "gcc_usb30_prim_master_clk_src", 1113 .parent_data = gcc_parent_data_1, 1114 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1115 .ops = &clk_rcg2_ops, 1116 }, 1117 }; 1118 1119 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 1120 F(19200000, P_BI_TCXO, 1, 0, 0), 1121 { } 1122 }; 1123 1124 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1125 .cmd_rcgr = 0xf038, 1126 .mnd_width = 0, 1127 .hid_width = 5, 1128 .parent_map = gcc_parent_map_3, 1129 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1130 .clkr.hw.init = &(struct clk_init_data){ 1131 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1132 .parent_data = gcc_parent_data_3, 1133 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1134 .ops = &clk_rcg2_ops, 1135 }, 1136 }; 1137 1138 static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk_src[] = { 1139 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0), 1140 F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0), 1141 { } 1142 }; 1143 1144 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { 1145 .cmd_rcgr = 0x9e020, 1146 .mnd_width = 8, 1147 .hid_width = 5, 1148 .parent_map = gcc_parent_map_5, 1149 .freq_tbl = ftbl_gcc_usb30_sec_master_clk_src, 1150 .clkr.hw.init = &(struct clk_init_data){ 1151 .name = "gcc_usb30_sec_master_clk_src", 1152 .parent_data = gcc_parent_data_5, 1153 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1154 .ops = &clk_rcg2_ops, 1155 }, 1156 }; 1157 1158 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { 1159 .cmd_rcgr = 0x9e038, 1160 .mnd_width = 0, 1161 .hid_width = 5, 1162 .parent_map = gcc_parent_map_3, 1163 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1164 .clkr.hw.init = &(struct clk_init_data){ 1165 .name = "gcc_usb30_sec_mock_utmi_clk_src", 1166 .parent_data = gcc_parent_data_3, 1167 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1168 .ops = &clk_rcg2_ops, 1169 }, 1170 }; 1171 1172 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1173 .cmd_rcgr = 0xf064, 1174 .mnd_width = 0, 1175 .hid_width = 5, 1176 .parent_map = gcc_parent_map_2, 1177 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1178 .clkr.hw.init = &(struct clk_init_data){ 1179 .name = "gcc_usb3_prim_phy_aux_clk_src", 1180 .parent_data = gcc_parent_data_2, 1181 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1182 .ops = &clk_rcg2_ops, 1183 }, 1184 }; 1185 1186 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { 1187 .cmd_rcgr = 0x9e064, 1188 .mnd_width = 0, 1189 .hid_width = 5, 1190 .parent_map = gcc_parent_map_2, 1191 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1192 .clkr.hw.init = &(struct clk_init_data){ 1193 .name = "gcc_usb3_sec_phy_aux_clk_src", 1194 .parent_data = gcc_parent_data_2, 1195 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1196 .ops = &clk_rcg2_ops, 1197 }, 1198 }; 1199 1200 static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = { 1201 F(4800000, P_BI_TCXO, 4, 0, 0), 1202 F(19200000, P_BI_TCXO, 1, 0, 0), 1203 { } 1204 }; 1205 1206 static struct clk_rcg2 gcc_sec_ctrl_clk_src = { 1207 .cmd_rcgr = 0x3d02c, 1208 .mnd_width = 0, 1209 .hid_width = 5, 1210 .parent_map = gcc_parent_map_3, 1211 .freq_tbl = ftbl_gcc_sec_ctrl_clk_src, 1212 .clkr.hw.init = &(struct clk_init_data){ 1213 .name = "gcc_sec_ctrl_clk_src", 1214 .parent_data = gcc_parent_data_3, 1215 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1216 .ops = &clk_rcg2_ops, 1217 }, 1218 }; 1219 1220 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1221 .reg = 0xf050, 1222 .shift = 0, 1223 .width = 4, 1224 .clkr.hw.init = &(struct clk_init_data) { 1225 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1226 .parent_hws = (const struct clk_hw*[]){ 1227 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1228 }, 1229 .num_parents = 1, 1230 .flags = CLK_SET_RATE_PARENT, 1231 .ops = &clk_regmap_div_ro_ops, 1232 }, 1233 }; 1234 1235 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = { 1236 .reg = 0x9e050, 1237 .shift = 0, 1238 .width = 4, 1239 .clkr.hw.init = &(struct clk_init_data) { 1240 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src", 1241 .parent_hws = (const struct clk_hw*[]){ 1242 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, 1243 }, 1244 .num_parents = 1, 1245 .flags = CLK_SET_RATE_PARENT, 1246 .ops = &clk_regmap_div_ro_ops, 1247 }, 1248 }; 1249 1250 static struct clk_branch gcc_pcie_clkref_en = { 1251 .halt_reg = 0x8c004, 1252 .halt_check = BRANCH_HALT, 1253 .clkr = { 1254 .enable_reg = 0x8c004, 1255 .enable_mask = BIT(0), 1256 .hw.init = &(struct clk_init_data){ 1257 .name = "gcc_pcie_clkref_en", 1258 .ops = &clk_branch2_ops, 1259 }, 1260 }, 1261 }; 1262 1263 static struct clk_branch gcc_edp_clkref_en = { 1264 .halt_reg = 0x8c008, 1265 .halt_check = BRANCH_HALT, 1266 .clkr = { 1267 .enable_reg = 0x8c008, 1268 .enable_mask = BIT(0), 1269 .hw.init = &(struct clk_init_data){ 1270 .name = "gcc_edp_clkref_en", 1271 .ops = &clk_branch2_ops, 1272 }, 1273 }, 1274 }; 1275 1276 static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = { 1277 .halt_reg = 0x6b080, 1278 .halt_check = BRANCH_HALT_SKIP, 1279 .hwcg_reg = 0x6b080, 1280 .hwcg_bit = 1, 1281 .clkr = { 1282 .enable_reg = 0x52000, 1283 .enable_mask = BIT(12), 1284 .hw.init = &(struct clk_init_data){ 1285 .name = "gcc_aggre_noc_pcie_0_axi_clk", 1286 .ops = &clk_branch2_ops, 1287 }, 1288 }, 1289 }; 1290 1291 static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = { 1292 .halt_reg = 0x8d084, 1293 .halt_check = BRANCH_HALT_SKIP, 1294 .hwcg_reg = 0x8d084, 1295 .hwcg_bit = 1, 1296 .clkr = { 1297 .enable_reg = 0x52000, 1298 .enable_mask = BIT(11), 1299 .hw.init = &(struct clk_init_data){ 1300 .name = "gcc_aggre_noc_pcie_1_axi_clk", 1301 .ops = &clk_branch2_ops, 1302 }, 1303 }, 1304 }; 1305 1306 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { 1307 .halt_reg = 0x90010, 1308 .halt_check = BRANCH_HALT_VOTED, 1309 .hwcg_reg = 0x90010, 1310 .hwcg_bit = 1, 1311 .clkr = { 1312 .enable_reg = 0x52000, 1313 .enable_mask = BIT(18), 1314 .hw.init = &(struct clk_init_data){ 1315 .name = "gcc_aggre_noc_pcie_tbu_clk", 1316 .ops = &clk_branch2_ops, 1317 }, 1318 }, 1319 }; 1320 1321 static struct clk_branch gcc_aggre_noc_pcie_center_sf_axi_clk = { 1322 .halt_reg = 0x8d088, 1323 .halt_check = BRANCH_HALT_VOTED, 1324 .hwcg_reg = 0x8d088, 1325 .hwcg_bit = 1, 1326 .clkr = { 1327 .enable_reg = 0x52008, 1328 .enable_mask = BIT(28), 1329 .hw.init = &(struct clk_init_data){ 1330 .name = "gcc_aggre_noc_pcie_center_sf_axi_clk", 1331 .ops = &clk_branch2_ops, 1332 }, 1333 }, 1334 }; 1335 1336 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1337 .halt_reg = 0x770cc, 1338 .halt_check = BRANCH_HALT_VOTED, 1339 .hwcg_reg = 0x770cc, 1340 .hwcg_bit = 1, 1341 .clkr = { 1342 .enable_reg = 0x770cc, 1343 .enable_mask = BIT(0), 1344 .hw.init = &(struct clk_init_data){ 1345 .name = "gcc_aggre_ufs_phy_axi_clk", 1346 .parent_hws = (const struct clk_hw*[]){ 1347 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1348 }, 1349 .num_parents = 1, 1350 .flags = CLK_SET_RATE_PARENT, 1351 .ops = &clk_branch2_ops, 1352 }, 1353 }, 1354 }; 1355 1356 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1357 .halt_reg = 0xf080, 1358 .halt_check = BRANCH_HALT_VOTED, 1359 .hwcg_reg = 0xf080, 1360 .hwcg_bit = 1, 1361 .clkr = { 1362 .enable_reg = 0xf080, 1363 .enable_mask = BIT(0), 1364 .hw.init = &(struct clk_init_data){ 1365 .name = "gcc_aggre_usb3_prim_axi_clk", 1366 .parent_hws = (const struct clk_hw*[]){ 1367 &gcc_usb30_prim_master_clk_src.clkr.hw, 1368 }, 1369 .num_parents = 1, 1370 .flags = CLK_SET_RATE_PARENT, 1371 .ops = &clk_branch2_ops, 1372 }, 1373 }, 1374 }; 1375 1376 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { 1377 .halt_reg = 0x9e080, 1378 .halt_check = BRANCH_HALT_VOTED, 1379 .hwcg_reg = 0x9e080, 1380 .hwcg_bit = 1, 1381 .clkr = { 1382 .enable_reg = 0x9e080, 1383 .enable_mask = BIT(0), 1384 .hw.init = &(struct clk_init_data){ 1385 .name = "gcc_aggre_usb3_sec_axi_clk", 1386 .parent_hws = (const struct clk_hw*[]){ 1387 &gcc_usb30_sec_master_clk_src.clkr.hw, 1388 }, 1389 .num_parents = 1, 1390 .flags = CLK_SET_RATE_PARENT, 1391 .ops = &clk_branch2_ops, 1392 }, 1393 }, 1394 }; 1395 1396 static struct clk_branch gcc_camera_hf_axi_clk = { 1397 .halt_reg = 0x26010, 1398 .halt_check = BRANCH_HALT_SKIP, 1399 .hwcg_reg = 0x26010, 1400 .hwcg_bit = 1, 1401 .clkr = { 1402 .enable_reg = 0x26010, 1403 .enable_mask = BIT(0), 1404 .hw.init = &(struct clk_init_data){ 1405 .name = "gcc_camera_hf_axi_clk", 1406 .ops = &clk_branch2_ops, 1407 }, 1408 }, 1409 }; 1410 1411 static struct clk_branch gcc_camera_sf_axi_clk = { 1412 .halt_reg = 0x2601c, 1413 .halt_check = BRANCH_HALT_SKIP, 1414 .hwcg_reg = 0x2601c, 1415 .hwcg_bit = 1, 1416 .clkr = { 1417 .enable_reg = 0x2601c, 1418 .enable_mask = BIT(0), 1419 .hw.init = &(struct clk_init_data){ 1420 .name = "gcc_camera_sf_axi_clk", 1421 .ops = &clk_branch2_ops, 1422 }, 1423 }, 1424 }; 1425 1426 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1427 .halt_reg = 0xf07c, 1428 .halt_check = BRANCH_HALT_VOTED, 1429 .hwcg_reg = 0xf07c, 1430 .hwcg_bit = 1, 1431 .clkr = { 1432 .enable_reg = 0xf07c, 1433 .enable_mask = BIT(0), 1434 .hw.init = &(struct clk_init_data){ 1435 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1436 .parent_hws = (const struct clk_hw*[]){ 1437 &gcc_usb30_prim_master_clk_src.clkr.hw, 1438 }, 1439 .num_parents = 1, 1440 .flags = CLK_SET_RATE_PARENT, 1441 .ops = &clk_branch2_ops, 1442 }, 1443 }, 1444 }; 1445 1446 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { 1447 .halt_reg = 0x9e07c, 1448 .halt_check = BRANCH_HALT_VOTED, 1449 .hwcg_reg = 0x9e07c, 1450 .hwcg_bit = 1, 1451 .clkr = { 1452 .enable_reg = 0x9e07c, 1453 .enable_mask = BIT(0), 1454 .hw.init = &(struct clk_init_data){ 1455 .name = "gcc_cfg_noc_usb3_sec_axi_clk", 1456 .parent_hws = (const struct clk_hw*[]){ 1457 &gcc_usb30_sec_master_clk_src.clkr.hw, 1458 }, 1459 .num_parents = 1, 1460 .flags = CLK_SET_RATE_PARENT, 1461 .ops = &clk_branch2_ops, 1462 }, 1463 }, 1464 }; 1465 1466 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1467 .halt_reg = 0x71154, 1468 .halt_check = BRANCH_HALT_SKIP, 1469 .hwcg_reg = 0x71154, 1470 .hwcg_bit = 1, 1471 .clkr = { 1472 .enable_reg = 0x71154, 1473 .enable_mask = BIT(0), 1474 .hw.init = &(struct clk_init_data){ 1475 .name = "gcc_ddrss_gpu_axi_clk", 1476 .ops = &clk_branch2_aon_ops, 1477 }, 1478 }, 1479 }; 1480 1481 static struct clk_branch gcc_ddrss_pcie_sf_clk = { 1482 .halt_reg = 0x8d080, 1483 .halt_check = BRANCH_HALT_SKIP, 1484 .hwcg_reg = 0x8d080, 1485 .hwcg_bit = 1, 1486 .clkr = { 1487 .enable_reg = 0x52000, 1488 .enable_mask = BIT(19), 1489 .hw.init = &(struct clk_init_data){ 1490 .name = "gcc_ddrss_pcie_sf_clk", 1491 .ops = &clk_branch2_ops, 1492 }, 1493 }, 1494 }; 1495 1496 static struct clk_branch gcc_disp_gpll0_clk_src = { 1497 .halt_check = BRANCH_HALT_DELAY, 1498 .clkr = { 1499 .enable_reg = 0x52000, 1500 .enable_mask = BIT(7), 1501 .hw.init = &(struct clk_init_data){ 1502 .name = "gcc_disp_gpll0_clk_src", 1503 .parent_hws = (const struct clk_hw*[]){ 1504 &gcc_gpll0.clkr.hw, 1505 }, 1506 .num_parents = 1, 1507 .flags = CLK_SET_RATE_PARENT, 1508 .ops = &clk_branch2_ops, 1509 }, 1510 }, 1511 }; 1512 1513 static struct clk_branch gcc_disp_hf_axi_clk = { 1514 .halt_reg = 0x2700c, 1515 .halt_check = BRANCH_HALT_SKIP, 1516 .hwcg_reg = 0x2700c, 1517 .hwcg_bit = 1, 1518 .clkr = { 1519 .enable_reg = 0x2700c, 1520 .enable_mask = BIT(0), 1521 .hw.init = &(struct clk_init_data){ 1522 .name = "gcc_disp_hf_axi_clk", 1523 .ops = &clk_branch2_ops, 1524 }, 1525 }, 1526 }; 1527 1528 static struct clk_branch gcc_disp_sf_axi_clk = { 1529 .halt_reg = 0x27014, 1530 .halt_check = BRANCH_HALT_SKIP, 1531 .hwcg_reg = 0x27014, 1532 .hwcg_bit = 1, 1533 .clkr = { 1534 .enable_reg = 0x27014, 1535 .enable_mask = BIT(0), 1536 .hw.init = &(struct clk_init_data){ 1537 .name = "gcc_disp_sf_axi_clk", 1538 .ops = &clk_branch2_ops, 1539 }, 1540 }, 1541 }; 1542 1543 static struct clk_branch gcc_gp1_clk = { 1544 .halt_reg = 0x64000, 1545 .halt_check = BRANCH_HALT, 1546 .clkr = { 1547 .enable_reg = 0x64000, 1548 .enable_mask = BIT(0), 1549 .hw.init = &(struct clk_init_data){ 1550 .name = "gcc_gp1_clk", 1551 .parent_hws = (const struct clk_hw*[]){ 1552 &gcc_gp1_clk_src.clkr.hw, 1553 }, 1554 .num_parents = 1, 1555 .flags = CLK_SET_RATE_PARENT, 1556 .ops = &clk_branch2_ops, 1557 }, 1558 }, 1559 }; 1560 1561 static struct clk_branch gcc_gp2_clk = { 1562 .halt_reg = 0x65000, 1563 .halt_check = BRANCH_HALT, 1564 .clkr = { 1565 .enable_reg = 0x65000, 1566 .enable_mask = BIT(0), 1567 .hw.init = &(struct clk_init_data){ 1568 .name = "gcc_gp2_clk", 1569 .parent_hws = (const struct clk_hw*[]){ 1570 &gcc_gp2_clk_src.clkr.hw, 1571 }, 1572 .num_parents = 1, 1573 .flags = CLK_SET_RATE_PARENT, 1574 .ops = &clk_branch2_ops, 1575 }, 1576 }, 1577 }; 1578 1579 static struct clk_branch gcc_gp3_clk = { 1580 .halt_reg = 0x66000, 1581 .halt_check = BRANCH_HALT, 1582 .clkr = { 1583 .enable_reg = 0x66000, 1584 .enable_mask = BIT(0), 1585 .hw.init = &(struct clk_init_data){ 1586 .name = "gcc_gp3_clk", 1587 .parent_hws = (const struct clk_hw*[]){ 1588 &gcc_gp3_clk_src.clkr.hw, 1589 }, 1590 .num_parents = 1, 1591 .flags = CLK_SET_RATE_PARENT, 1592 .ops = &clk_branch2_ops, 1593 }, 1594 }, 1595 }; 1596 1597 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1598 .halt_check = BRANCH_HALT_DELAY, 1599 .clkr = { 1600 .enable_reg = 0x52000, 1601 .enable_mask = BIT(15), 1602 .hw.init = &(struct clk_init_data){ 1603 .name = "gcc_gpu_gpll0_clk_src", 1604 .parent_hws = (const struct clk_hw*[]){ 1605 &gcc_gpll0.clkr.hw, 1606 }, 1607 .num_parents = 1, 1608 .flags = CLK_SET_RATE_PARENT, 1609 .ops = &clk_branch2_ops, 1610 }, 1611 }, 1612 }; 1613 1614 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1615 .halt_check = BRANCH_HALT_DELAY, 1616 .clkr = { 1617 .enable_reg = 0x52000, 1618 .enable_mask = BIT(16), 1619 .hw.init = &(struct clk_init_data){ 1620 .name = "gcc_gpu_gpll0_div_clk_src", 1621 .parent_hws = (const struct clk_hw*[]){ 1622 &gcc_gpll0_out_even.clkr.hw, 1623 }, 1624 .num_parents = 1, 1625 .flags = CLK_SET_RATE_PARENT, 1626 .ops = &clk_branch2_ops, 1627 }, 1628 }, 1629 }; 1630 1631 static struct clk_branch gcc_gpu_iref_en = { 1632 .halt_reg = 0x8c014, 1633 .halt_check = BRANCH_HALT, 1634 .clkr = { 1635 .enable_reg = 0x8c014, 1636 .enable_mask = BIT(0), 1637 .hw.init = &(struct clk_init_data){ 1638 .name = "gcc_gpu_iref_en", 1639 .ops = &clk_branch2_ops, 1640 }, 1641 }, 1642 }; 1643 1644 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1645 .halt_reg = 0x7100c, 1646 .halt_check = BRANCH_HALT_VOTED, 1647 .hwcg_reg = 0x7100c, 1648 .hwcg_bit = 1, 1649 .clkr = { 1650 .enable_reg = 0x7100c, 1651 .enable_mask = BIT(0), 1652 .hw.init = &(struct clk_init_data){ 1653 .name = "gcc_gpu_memnoc_gfx_clk", 1654 .ops = &clk_branch2_aon_ops, 1655 }, 1656 }, 1657 }; 1658 1659 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1660 .halt_reg = 0x71018, 1661 .halt_check = BRANCH_HALT, 1662 .clkr = { 1663 .enable_reg = 0x71018, 1664 .enable_mask = BIT(0), 1665 .hw.init = &(struct clk_init_data){ 1666 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1667 .ops = &clk_branch2_aon_ops, 1668 }, 1669 }, 1670 }; 1671 1672 static struct clk_branch gcc_pcie0_phy_rchng_clk = { 1673 .halt_reg = 0x6b038, 1674 .halt_check = BRANCH_HALT_VOTED, 1675 .clkr = { 1676 .enable_reg = 0x52000, 1677 .enable_mask = BIT(22), 1678 .hw.init = &(struct clk_init_data){ 1679 .name = "gcc_pcie0_phy_rchng_clk", 1680 .parent_hws = (const struct clk_hw*[]){ 1681 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1682 }, 1683 .num_parents = 1, 1684 .flags = CLK_SET_RATE_PARENT, 1685 .ops = &clk_branch2_ops, 1686 }, 1687 }, 1688 }; 1689 1690 static struct clk_branch gcc_pcie1_phy_rchng_clk = { 1691 .halt_reg = 0x8d038, 1692 .halt_check = BRANCH_HALT_VOTED, 1693 .clkr = { 1694 .enable_reg = 0x52000, 1695 .enable_mask = BIT(23), 1696 .hw.init = &(struct clk_init_data){ 1697 .name = "gcc_pcie1_phy_rchng_clk", 1698 .parent_hws = (const struct clk_hw*[]){ 1699 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 1700 }, 1701 .num_parents = 1, 1702 .flags = CLK_SET_RATE_PARENT, 1703 .ops = &clk_branch2_ops, 1704 }, 1705 }, 1706 }; 1707 1708 static struct clk_branch gcc_pcie_0_aux_clk = { 1709 .halt_reg = 0x6b028, 1710 .halt_check = BRANCH_HALT_VOTED, 1711 .clkr = { 1712 .enable_reg = 0x52008, 1713 .enable_mask = BIT(3), 1714 .hw.init = &(struct clk_init_data){ 1715 .name = "gcc_pcie_0_aux_clk", 1716 .parent_hws = (const struct clk_hw*[]){ 1717 &gcc_pcie_0_aux_clk_src.clkr.hw, 1718 }, 1719 .num_parents = 1, 1720 .flags = CLK_SET_RATE_PARENT, 1721 .ops = &clk_branch2_ops, 1722 }, 1723 }, 1724 }; 1725 1726 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1727 .halt_reg = 0x6b024, 1728 .halt_check = BRANCH_HALT_VOTED, 1729 .hwcg_reg = 0x6b024, 1730 .hwcg_bit = 1, 1731 .clkr = { 1732 .enable_reg = 0x52008, 1733 .enable_mask = BIT(2), 1734 .hw.init = &(struct clk_init_data){ 1735 .name = "gcc_pcie_0_cfg_ahb_clk", 1736 .ops = &clk_branch2_ops, 1737 }, 1738 }, 1739 }; 1740 1741 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1742 .halt_reg = 0x6b01c, 1743 .halt_check = BRANCH_HALT_SKIP, 1744 .clkr = { 1745 .enable_reg = 0x52008, 1746 .enable_mask = BIT(1), 1747 .hw.init = &(struct clk_init_data){ 1748 .name = "gcc_pcie_0_mstr_axi_clk", 1749 .ops = &clk_branch2_ops, 1750 }, 1751 }, 1752 }; 1753 1754 static struct clk_branch gcc_pcie_0_pipe_clk = { 1755 .halt_reg = 0x6b030, 1756 .halt_check = BRANCH_HALT_SKIP, 1757 .clkr = { 1758 .enable_reg = 0x52008, 1759 .enable_mask = BIT(4), 1760 .hw.init = &(struct clk_init_data){ 1761 .name = "gcc_pcie_0_pipe_clk", 1762 .parent_hws = (const struct clk_hw*[]){ 1763 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1764 }, 1765 .num_parents = 1, 1766 .flags = CLK_SET_RATE_PARENT, 1767 .ops = &clk_branch2_ops, 1768 }, 1769 }, 1770 }; 1771 1772 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1773 .halt_reg = 0x6b014, 1774 .halt_check = BRANCH_HALT_VOTED, 1775 .clkr = { 1776 .enable_reg = 0x52008, 1777 .enable_mask = BIT(0), 1778 .hw.init = &(struct clk_init_data){ 1779 .name = "gcc_pcie_0_slv_axi_clk", 1780 .ops = &clk_branch2_ops, 1781 }, 1782 }, 1783 }; 1784 1785 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1786 .halt_reg = 0x6b010, 1787 .halt_check = BRANCH_HALT_VOTED, 1788 .clkr = { 1789 .enable_reg = 0x52008, 1790 .enable_mask = BIT(5), 1791 .hw.init = &(struct clk_init_data){ 1792 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1793 .ops = &clk_branch2_ops, 1794 }, 1795 }, 1796 }; 1797 1798 static struct clk_branch gcc_pcie_1_aux_clk = { 1799 .halt_reg = 0x8d028, 1800 .halt_check = BRANCH_HALT_VOTED, 1801 .clkr = { 1802 .enable_reg = 0x52000, 1803 .enable_mask = BIT(29), 1804 .hw.init = &(struct clk_init_data){ 1805 .name = "gcc_pcie_1_aux_clk", 1806 .parent_hws = (const struct clk_hw*[]){ 1807 &gcc_pcie_1_aux_clk_src.clkr.hw, 1808 }, 1809 .num_parents = 1, 1810 .flags = CLK_SET_RATE_PARENT, 1811 .ops = &clk_branch2_ops, 1812 }, 1813 }, 1814 }; 1815 1816 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1817 .halt_reg = 0x8d024, 1818 .halt_check = BRANCH_HALT_VOTED, 1819 .hwcg_reg = 0x8d024, 1820 .hwcg_bit = 1, 1821 .clkr = { 1822 .enable_reg = 0x52000, 1823 .enable_mask = BIT(28), 1824 .hw.init = &(struct clk_init_data){ 1825 .name = "gcc_pcie_1_cfg_ahb_clk", 1826 .ops = &clk_branch2_ops, 1827 }, 1828 }, 1829 }; 1830 1831 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1832 .halt_reg = 0x8d01c, 1833 .halt_check = BRANCH_HALT_SKIP, 1834 .clkr = { 1835 .enable_reg = 0x52000, 1836 .enable_mask = BIT(27), 1837 .hw.init = &(struct clk_init_data){ 1838 .name = "gcc_pcie_1_mstr_axi_clk", 1839 .ops = &clk_branch2_ops, 1840 }, 1841 }, 1842 }; 1843 1844 static struct clk_branch gcc_pcie_1_pipe_clk = { 1845 .halt_reg = 0x8d030, 1846 .halt_check = BRANCH_HALT_SKIP, 1847 .clkr = { 1848 .enable_reg = 0x52000, 1849 .enable_mask = BIT(30), 1850 .hw.init = &(struct clk_init_data){ 1851 .name = "gcc_pcie_1_pipe_clk", 1852 .parent_hws = (const struct clk_hw*[]){ 1853 &gcc_pcie_1_pipe_clk_src.clkr.hw, 1854 }, 1855 .num_parents = 1, 1856 .flags = CLK_SET_RATE_PARENT, 1857 .ops = &clk_branch2_ops, 1858 }, 1859 }, 1860 }; 1861 1862 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1863 .halt_reg = 0x8d014, 1864 .halt_check = BRANCH_HALT_VOTED, 1865 .clkr = { 1866 .enable_reg = 0x52000, 1867 .enable_mask = BIT(26), 1868 .hw.init = &(struct clk_init_data){ 1869 .name = "gcc_pcie_1_slv_axi_clk", 1870 .ops = &clk_branch2_ops, 1871 }, 1872 }, 1873 }; 1874 1875 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 1876 .halt_reg = 0x8d010, 1877 .halt_check = BRANCH_HALT_VOTED, 1878 .clkr = { 1879 .enable_reg = 0x52000, 1880 .enable_mask = BIT(25), 1881 .hw.init = &(struct clk_init_data){ 1882 .name = "gcc_pcie_1_slv_q2a_axi_clk", 1883 .ops = &clk_branch2_ops, 1884 }, 1885 }, 1886 }; 1887 1888 static struct clk_branch gcc_pcie_throttle_core_clk = { 1889 .halt_reg = 0x90018, 1890 .halt_check = BRANCH_HALT_SKIP, 1891 .hwcg_reg = 0x90018, 1892 .hwcg_bit = 1, 1893 .clkr = { 1894 .enable_reg = 0x52000, 1895 .enable_mask = BIT(20), 1896 .hw.init = &(struct clk_init_data){ 1897 .name = "gcc_pcie_throttle_core_clk", 1898 .ops = &clk_branch2_ops, 1899 }, 1900 }, 1901 }; 1902 1903 static struct clk_branch gcc_pdm2_clk = { 1904 .halt_reg = 0x3300c, 1905 .halt_check = BRANCH_HALT, 1906 .clkr = { 1907 .enable_reg = 0x3300c, 1908 .enable_mask = BIT(0), 1909 .hw.init = &(struct clk_init_data){ 1910 .name = "gcc_pdm2_clk", 1911 .parent_hws = (const struct clk_hw*[]){ 1912 &gcc_pdm2_clk_src.clkr.hw, 1913 }, 1914 .num_parents = 1, 1915 .flags = CLK_SET_RATE_PARENT, 1916 .ops = &clk_branch2_ops, 1917 }, 1918 }, 1919 }; 1920 1921 static struct clk_branch gcc_pdm_ahb_clk = { 1922 .halt_reg = 0x33004, 1923 .halt_check = BRANCH_HALT_VOTED, 1924 .hwcg_reg = 0x33004, 1925 .hwcg_bit = 1, 1926 .clkr = { 1927 .enable_reg = 0x33004, 1928 .enable_mask = BIT(0), 1929 .hw.init = &(struct clk_init_data){ 1930 .name = "gcc_pdm_ahb_clk", 1931 .ops = &clk_branch2_ops, 1932 }, 1933 }, 1934 }; 1935 1936 static struct clk_branch gcc_pdm_xo4_clk = { 1937 .halt_reg = 0x33008, 1938 .halt_check = BRANCH_HALT, 1939 .clkr = { 1940 .enable_reg = 0x33008, 1941 .enable_mask = BIT(0), 1942 .hw.init = &(struct clk_init_data){ 1943 .name = "gcc_pdm_xo4_clk", 1944 .ops = &clk_branch2_ops, 1945 }, 1946 }, 1947 }; 1948 1949 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 1950 .halt_reg = 0x26008, 1951 .halt_check = BRANCH_HALT_VOTED, 1952 .hwcg_reg = 0x26008, 1953 .hwcg_bit = 1, 1954 .clkr = { 1955 .enable_reg = 0x26008, 1956 .enable_mask = BIT(0), 1957 .hw.init = &(struct clk_init_data){ 1958 .name = "gcc_qmip_camera_nrt_ahb_clk", 1959 .ops = &clk_branch2_ops, 1960 }, 1961 }, 1962 }; 1963 1964 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 1965 .halt_reg = 0x2600c, 1966 .halt_check = BRANCH_HALT_VOTED, 1967 .hwcg_reg = 0x2600c, 1968 .hwcg_bit = 1, 1969 .clkr = { 1970 .enable_reg = 0x2600c, 1971 .enable_mask = BIT(0), 1972 .hw.init = &(struct clk_init_data){ 1973 .name = "gcc_qmip_camera_rt_ahb_clk", 1974 .ops = &clk_branch2_ops, 1975 }, 1976 }, 1977 }; 1978 1979 static struct clk_branch gcc_qmip_disp_ahb_clk = { 1980 .halt_reg = 0x27008, 1981 .halt_check = BRANCH_HALT_VOTED, 1982 .clkr = { 1983 .enable_reg = 0x27008, 1984 .enable_mask = BIT(0), 1985 .hw.init = &(struct clk_init_data){ 1986 .name = "gcc_qmip_disp_ahb_clk", 1987 .ops = &clk_branch2_ops, 1988 }, 1989 }, 1990 }; 1991 1992 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 1993 .halt_reg = 0x28008, 1994 .halt_check = BRANCH_HALT_VOTED, 1995 .hwcg_reg = 0x28008, 1996 .hwcg_bit = 1, 1997 .clkr = { 1998 .enable_reg = 0x28008, 1999 .enable_mask = BIT(0), 2000 .hw.init = &(struct clk_init_data){ 2001 .name = "gcc_qmip_video_vcodec_ahb_clk", 2002 .ops = &clk_branch2_ops, 2003 }, 2004 }, 2005 }; 2006 2007 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { 2008 .halt_reg = 0x4b004, 2009 .halt_check = BRANCH_HALT, 2010 .hwcg_reg = 0x4b004, 2011 .hwcg_bit = 1, 2012 .clkr = { 2013 .enable_reg = 0x4b004, 2014 .enable_mask = BIT(0), 2015 .hw.init = &(struct clk_init_data){ 2016 .name = "gcc_qspi_cnoc_periph_ahb_clk", 2017 .ops = &clk_branch2_ops, 2018 }, 2019 }, 2020 }; 2021 2022 static struct clk_branch gcc_qspi_core_clk = { 2023 .halt_reg = 0x4b008, 2024 .halt_check = BRANCH_HALT, 2025 .clkr = { 2026 .enable_reg = 0x4b008, 2027 .enable_mask = BIT(0), 2028 .hw.init = &(struct clk_init_data){ 2029 .name = "gcc_qspi_core_clk", 2030 .parent_hws = (const struct clk_hw*[]){ 2031 &gcc_qspi_core_clk_src.clkr.hw, 2032 }, 2033 .num_parents = 1, 2034 .flags = CLK_SET_RATE_PARENT, 2035 .ops = &clk_branch2_ops, 2036 }, 2037 }, 2038 }; 2039 2040 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2041 .halt_reg = 0x23008, 2042 .halt_check = BRANCH_HALT_VOTED, 2043 .clkr = { 2044 .enable_reg = 0x52008, 2045 .enable_mask = BIT(9), 2046 .hw.init = &(struct clk_init_data){ 2047 .name = "gcc_qupv3_wrap0_core_2x_clk", 2048 .ops = &clk_branch2_ops, 2049 }, 2050 }, 2051 }; 2052 2053 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2054 .halt_reg = 0x23000, 2055 .halt_check = BRANCH_HALT_VOTED, 2056 .clkr = { 2057 .enable_reg = 0x52008, 2058 .enable_mask = BIT(8), 2059 .hw.init = &(struct clk_init_data){ 2060 .name = "gcc_qupv3_wrap0_core_clk", 2061 .ops = &clk_branch2_ops, 2062 }, 2063 }, 2064 }; 2065 2066 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2067 .halt_reg = 0x1700c, 2068 .halt_check = BRANCH_HALT_VOTED, 2069 .clkr = { 2070 .enable_reg = 0x52008, 2071 .enable_mask = BIT(10), 2072 .hw.init = &(struct clk_init_data){ 2073 .name = "gcc_qupv3_wrap0_s0_clk", 2074 .parent_hws = (const struct clk_hw*[]){ 2075 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 2076 }, 2077 .num_parents = 1, 2078 .flags = CLK_SET_RATE_PARENT, 2079 .ops = &clk_branch2_ops, 2080 }, 2081 }, 2082 }; 2083 2084 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2085 .halt_reg = 0x1713c, 2086 .halt_check = BRANCH_HALT_VOTED, 2087 .clkr = { 2088 .enable_reg = 0x52008, 2089 .enable_mask = BIT(11), 2090 .hw.init = &(struct clk_init_data){ 2091 .name = "gcc_qupv3_wrap0_s1_clk", 2092 .parent_hws = (const struct clk_hw*[]){ 2093 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 2094 }, 2095 .num_parents = 1, 2096 .flags = CLK_SET_RATE_PARENT, 2097 .ops = &clk_branch2_ops, 2098 }, 2099 }, 2100 }; 2101 2102 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2103 .halt_reg = 0x1726c, 2104 .halt_check = BRANCH_HALT_VOTED, 2105 .clkr = { 2106 .enable_reg = 0x52008, 2107 .enable_mask = BIT(12), 2108 .hw.init = &(struct clk_init_data){ 2109 .name = "gcc_qupv3_wrap0_s2_clk", 2110 .parent_hws = (const struct clk_hw*[]){ 2111 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2112 }, 2113 .num_parents = 1, 2114 .flags = CLK_SET_RATE_PARENT, 2115 .ops = &clk_branch2_ops, 2116 }, 2117 }, 2118 }; 2119 2120 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2121 .halt_reg = 0x1739c, 2122 .halt_check = BRANCH_HALT_VOTED, 2123 .clkr = { 2124 .enable_reg = 0x52008, 2125 .enable_mask = BIT(13), 2126 .hw.init = &(struct clk_init_data){ 2127 .name = "gcc_qupv3_wrap0_s3_clk", 2128 .parent_hws = (const struct clk_hw*[]){ 2129 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2130 }, 2131 .num_parents = 1, 2132 .flags = CLK_SET_RATE_PARENT, 2133 .ops = &clk_branch2_ops, 2134 }, 2135 }, 2136 }; 2137 2138 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2139 .halt_reg = 0x174cc, 2140 .halt_check = BRANCH_HALT_VOTED, 2141 .clkr = { 2142 .enable_reg = 0x52008, 2143 .enable_mask = BIT(14), 2144 .hw.init = &(struct clk_init_data){ 2145 .name = "gcc_qupv3_wrap0_s4_clk", 2146 .parent_hws = (const struct clk_hw*[]){ 2147 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2148 }, 2149 .num_parents = 1, 2150 .flags = CLK_SET_RATE_PARENT, 2151 .ops = &clk_branch2_ops, 2152 }, 2153 }, 2154 }; 2155 2156 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2157 .halt_reg = 0x175fc, 2158 .halt_check = BRANCH_HALT_VOTED, 2159 .clkr = { 2160 .enable_reg = 0x52008, 2161 .enable_mask = BIT(15), 2162 .hw.init = &(struct clk_init_data){ 2163 .name = "gcc_qupv3_wrap0_s5_clk", 2164 .parent_hws = (const struct clk_hw*[]){ 2165 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2166 }, 2167 .num_parents = 1, 2168 .flags = CLK_SET_RATE_PARENT, 2169 .ops = &clk_branch2_ops, 2170 }, 2171 }, 2172 }; 2173 2174 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 2175 .halt_reg = 0x1772c, 2176 .halt_check = BRANCH_HALT_VOTED, 2177 .clkr = { 2178 .enable_reg = 0x52008, 2179 .enable_mask = BIT(16), 2180 .hw.init = &(struct clk_init_data){ 2181 .name = "gcc_qupv3_wrap0_s6_clk", 2182 .parent_hws = (const struct clk_hw*[]){ 2183 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 2184 }, 2185 .num_parents = 1, 2186 .flags = CLK_SET_RATE_PARENT, 2187 .ops = &clk_branch2_ops, 2188 }, 2189 }, 2190 }; 2191 2192 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 2193 .halt_reg = 0x1785c, 2194 .halt_check = BRANCH_HALT_VOTED, 2195 .clkr = { 2196 .enable_reg = 0x52008, 2197 .enable_mask = BIT(17), 2198 .hw.init = &(struct clk_init_data){ 2199 .name = "gcc_qupv3_wrap0_s7_clk", 2200 .parent_hws = (const struct clk_hw*[]){ 2201 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 2202 }, 2203 .num_parents = 1, 2204 .flags = CLK_SET_RATE_PARENT, 2205 .ops = &clk_branch2_ops, 2206 }, 2207 }, 2208 }; 2209 2210 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2211 .halt_reg = 0x23140, 2212 .halt_check = BRANCH_HALT_VOTED, 2213 .clkr = { 2214 .enable_reg = 0x52008, 2215 .enable_mask = BIT(18), 2216 .hw.init = &(struct clk_init_data){ 2217 .name = "gcc_qupv3_wrap1_core_2x_clk", 2218 .ops = &clk_branch2_ops, 2219 }, 2220 }, 2221 }; 2222 2223 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2224 .halt_reg = 0x23138, 2225 .halt_check = BRANCH_HALT_VOTED, 2226 .clkr = { 2227 .enable_reg = 0x52008, 2228 .enable_mask = BIT(19), 2229 .hw.init = &(struct clk_init_data){ 2230 .name = "gcc_qupv3_wrap1_core_clk", 2231 .ops = &clk_branch2_ops, 2232 }, 2233 }, 2234 }; 2235 2236 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2237 .halt_reg = 0x1800c, 2238 .halt_check = BRANCH_HALT_VOTED, 2239 .clkr = { 2240 .enable_reg = 0x52008, 2241 .enable_mask = BIT(22), 2242 .hw.init = &(struct clk_init_data){ 2243 .name = "gcc_qupv3_wrap1_s0_clk", 2244 .parent_hws = (const struct clk_hw*[]){ 2245 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2246 }, 2247 .num_parents = 1, 2248 .flags = CLK_SET_RATE_PARENT, 2249 .ops = &clk_branch2_ops, 2250 }, 2251 }, 2252 }; 2253 2254 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2255 .halt_reg = 0x1813c, 2256 .halt_check = BRANCH_HALT_VOTED, 2257 .clkr = { 2258 .enable_reg = 0x52008, 2259 .enable_mask = BIT(23), 2260 .hw.init = &(struct clk_init_data){ 2261 .name = "gcc_qupv3_wrap1_s1_clk", 2262 .parent_hws = (const struct clk_hw*[]){ 2263 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2264 }, 2265 .num_parents = 1, 2266 .flags = CLK_SET_RATE_PARENT, 2267 .ops = &clk_branch2_ops, 2268 }, 2269 }, 2270 }; 2271 2272 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2273 .halt_reg = 0x1826c, 2274 .halt_check = BRANCH_HALT_VOTED, 2275 .clkr = { 2276 .enable_reg = 0x52008, 2277 .enable_mask = BIT(24), 2278 .hw.init = &(struct clk_init_data){ 2279 .name = "gcc_qupv3_wrap1_s2_clk", 2280 .parent_hws = (const struct clk_hw*[]){ 2281 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2282 }, 2283 .num_parents = 1, 2284 .flags = CLK_SET_RATE_PARENT, 2285 .ops = &clk_branch2_ops, 2286 }, 2287 }, 2288 }; 2289 2290 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2291 .halt_reg = 0x1839c, 2292 .halt_check = BRANCH_HALT_VOTED, 2293 .clkr = { 2294 .enable_reg = 0x52008, 2295 .enable_mask = BIT(25), 2296 .hw.init = &(struct clk_init_data){ 2297 .name = "gcc_qupv3_wrap1_s3_clk", 2298 .parent_hws = (const struct clk_hw*[]){ 2299 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2300 }, 2301 .num_parents = 1, 2302 .flags = CLK_SET_RATE_PARENT, 2303 .ops = &clk_branch2_ops, 2304 }, 2305 }, 2306 }; 2307 2308 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2309 .halt_reg = 0x184cc, 2310 .halt_check = BRANCH_HALT_VOTED, 2311 .clkr = { 2312 .enable_reg = 0x52008, 2313 .enable_mask = BIT(26), 2314 .hw.init = &(struct clk_init_data){ 2315 .name = "gcc_qupv3_wrap1_s4_clk", 2316 .parent_hws = (const struct clk_hw*[]){ 2317 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2318 }, 2319 .num_parents = 1, 2320 .flags = CLK_SET_RATE_PARENT, 2321 .ops = &clk_branch2_ops, 2322 }, 2323 }, 2324 }; 2325 2326 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2327 .halt_reg = 0x185fc, 2328 .halt_check = BRANCH_HALT_VOTED, 2329 .clkr = { 2330 .enable_reg = 0x52008, 2331 .enable_mask = BIT(27), 2332 .hw.init = &(struct clk_init_data){ 2333 .name = "gcc_qupv3_wrap1_s5_clk", 2334 .parent_hws = (const struct clk_hw*[]){ 2335 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2336 }, 2337 .num_parents = 1, 2338 .flags = CLK_SET_RATE_PARENT, 2339 .ops = &clk_branch2_ops, 2340 }, 2341 }, 2342 }; 2343 2344 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 2345 .halt_reg = 0x1872c, 2346 .halt_check = BRANCH_HALT_VOTED, 2347 .clkr = { 2348 .enable_reg = 0x52000, 2349 .enable_mask = BIT(13), 2350 .hw.init = &(struct clk_init_data){ 2351 .name = "gcc_qupv3_wrap1_s6_clk", 2352 .parent_hws = (const struct clk_hw*[]){ 2353 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 2354 }, 2355 .num_parents = 1, 2356 .flags = CLK_SET_RATE_PARENT, 2357 .ops = &clk_branch2_ops, 2358 }, 2359 }, 2360 }; 2361 2362 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 2363 .halt_reg = 0x1885c, 2364 .halt_check = BRANCH_HALT_VOTED, 2365 .clkr = { 2366 .enable_reg = 0x52000, 2367 .enable_mask = BIT(14), 2368 .hw.init = &(struct clk_init_data){ 2369 .name = "gcc_qupv3_wrap1_s7_clk", 2370 .parent_hws = (const struct clk_hw*[]){ 2371 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 2372 }, 2373 .num_parents = 1, 2374 .flags = CLK_SET_RATE_PARENT, 2375 .ops = &clk_branch2_ops, 2376 }, 2377 }, 2378 }; 2379 2380 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2381 .halt_reg = 0x17004, 2382 .halt_check = BRANCH_HALT_VOTED, 2383 .hwcg_reg = 0x17004, 2384 .hwcg_bit = 1, 2385 .clkr = { 2386 .enable_reg = 0x52008, 2387 .enable_mask = BIT(6), 2388 .hw.init = &(struct clk_init_data){ 2389 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2390 .ops = &clk_branch2_ops, 2391 }, 2392 }, 2393 }; 2394 2395 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2396 .halt_reg = 0x17008, 2397 .halt_check = BRANCH_HALT_VOTED, 2398 .hwcg_reg = 0x17008, 2399 .hwcg_bit = 1, 2400 .clkr = { 2401 .enable_reg = 0x52008, 2402 .enable_mask = BIT(7), 2403 .hw.init = &(struct clk_init_data){ 2404 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2405 .ops = &clk_branch2_ops, 2406 }, 2407 }, 2408 }; 2409 2410 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2411 .halt_reg = 0x18004, 2412 .halt_check = BRANCH_HALT_VOTED, 2413 .hwcg_reg = 0x18004, 2414 .hwcg_bit = 1, 2415 .clkr = { 2416 .enable_reg = 0x52008, 2417 .enable_mask = BIT(20), 2418 .hw.init = &(struct clk_init_data){ 2419 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2420 .ops = &clk_branch2_ops, 2421 }, 2422 }, 2423 }; 2424 2425 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2426 .halt_reg = 0x18008, 2427 .halt_check = BRANCH_HALT_VOTED, 2428 .hwcg_reg = 0x18008, 2429 .hwcg_bit = 1, 2430 .clkr = { 2431 .enable_reg = 0x52008, 2432 .enable_mask = BIT(21), 2433 .hw.init = &(struct clk_init_data){ 2434 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2435 .ops = &clk_branch2_ops, 2436 }, 2437 }, 2438 }; 2439 2440 static struct clk_branch gcc_sdcc1_ahb_clk = { 2441 .halt_reg = 0x75004, 2442 .halt_check = BRANCH_HALT, 2443 .clkr = { 2444 .enable_reg = 0x75004, 2445 .enable_mask = BIT(0), 2446 .hw.init = &(struct clk_init_data){ 2447 .name = "gcc_sdcc1_ahb_clk", 2448 .ops = &clk_branch2_ops, 2449 }, 2450 }, 2451 }; 2452 2453 static struct clk_branch gcc_sdcc1_apps_clk = { 2454 .halt_reg = 0x75008, 2455 .halt_check = BRANCH_HALT, 2456 .clkr = { 2457 .enable_reg = 0x75008, 2458 .enable_mask = BIT(0), 2459 .hw.init = &(struct clk_init_data){ 2460 .name = "gcc_sdcc1_apps_clk", 2461 .parent_hws = (const struct clk_hw*[]){ 2462 &gcc_sdcc1_apps_clk_src.clkr.hw, 2463 }, 2464 .num_parents = 1, 2465 .flags = CLK_SET_RATE_PARENT, 2466 .ops = &clk_branch2_ops, 2467 }, 2468 }, 2469 }; 2470 2471 static struct clk_branch gcc_sdcc1_ice_core_clk = { 2472 .halt_reg = 0x75024, 2473 .halt_check = BRANCH_HALT_VOTED, 2474 .hwcg_reg = 0x75024, 2475 .hwcg_bit = 1, 2476 .clkr = { 2477 .enable_reg = 0x75024, 2478 .enable_mask = BIT(0), 2479 .hw.init = &(struct clk_init_data){ 2480 .name = "gcc_sdcc1_ice_core_clk", 2481 .parent_hws = (const struct clk_hw*[]){ 2482 &gcc_sdcc1_ice_core_clk_src.clkr.hw, 2483 }, 2484 .num_parents = 1, 2485 .flags = CLK_SET_RATE_PARENT, 2486 .ops = &clk_branch2_ops, 2487 }, 2488 }, 2489 }; 2490 2491 static struct clk_branch gcc_sdcc2_ahb_clk = { 2492 .halt_reg = 0x14008, 2493 .halt_check = BRANCH_HALT, 2494 .clkr = { 2495 .enable_reg = 0x14008, 2496 .enable_mask = BIT(0), 2497 .hw.init = &(struct clk_init_data){ 2498 .name = "gcc_sdcc2_ahb_clk", 2499 .ops = &clk_branch2_ops, 2500 }, 2501 }, 2502 }; 2503 2504 static struct clk_branch gcc_sdcc2_apps_clk = { 2505 .halt_reg = 0x14004, 2506 .halt_check = BRANCH_HALT, 2507 .clkr = { 2508 .enable_reg = 0x14004, 2509 .enable_mask = BIT(0), 2510 .hw.init = &(struct clk_init_data){ 2511 .name = "gcc_sdcc2_apps_clk", 2512 .parent_hws = (const struct clk_hw*[]){ 2513 &gcc_sdcc2_apps_clk_src.clkr.hw, 2514 }, 2515 .num_parents = 1, 2516 .flags = CLK_SET_RATE_PARENT, 2517 .ops = &clk_branch2_ops, 2518 }, 2519 }, 2520 }; 2521 2522 static struct clk_branch gcc_sdcc4_ahb_clk = { 2523 .halt_reg = 0x16008, 2524 .halt_check = BRANCH_HALT, 2525 .clkr = { 2526 .enable_reg = 0x16008, 2527 .enable_mask = BIT(0), 2528 .hw.init = &(struct clk_init_data){ 2529 .name = "gcc_sdcc4_ahb_clk", 2530 .ops = &clk_branch2_ops, 2531 }, 2532 }, 2533 }; 2534 2535 static struct clk_branch gcc_sdcc4_apps_clk = { 2536 .halt_reg = 0x16004, 2537 .halt_check = BRANCH_HALT, 2538 .clkr = { 2539 .enable_reg = 0x16004, 2540 .enable_mask = BIT(0), 2541 .hw.init = &(struct clk_init_data){ 2542 .name = "gcc_sdcc4_apps_clk", 2543 .parent_hws = (const struct clk_hw*[]){ 2544 &gcc_sdcc4_apps_clk_src.clkr.hw, 2545 }, 2546 .num_parents = 1, 2547 .flags = CLK_SET_RATE_PARENT, 2548 .ops = &clk_branch2_ops, 2549 }, 2550 }, 2551 }; 2552 2553 static struct clk_branch gcc_throttle_pcie_ahb_clk = { 2554 .halt_reg = 0x9001c, 2555 .halt_check = BRANCH_HALT, 2556 .clkr = { 2557 .enable_reg = 0x9001c, 2558 .enable_mask = BIT(0), 2559 .hw.init = &(struct clk_init_data){ 2560 .name = "gcc_throttle_pcie_ahb_clk", 2561 .ops = &clk_branch2_ops, 2562 }, 2563 }, 2564 }; 2565 2566 static struct clk_branch gcc_titan_nrt_throttle_core_clk = { 2567 .halt_reg = 0x26024, 2568 .halt_check = BRANCH_HALT_SKIP, 2569 .hwcg_reg = 0x26024, 2570 .hwcg_bit = 1, 2571 .clkr = { 2572 .enable_reg = 0x26024, 2573 .enable_mask = BIT(0), 2574 .hw.init = &(struct clk_init_data){ 2575 .name = "gcc_titan_nrt_throttle_core_clk", 2576 .ops = &clk_branch2_ops, 2577 }, 2578 }, 2579 }; 2580 2581 static struct clk_branch gcc_titan_rt_throttle_core_clk = { 2582 .halt_reg = 0x26018, 2583 .halt_check = BRANCH_HALT_SKIP, 2584 .hwcg_reg = 0x26018, 2585 .hwcg_bit = 1, 2586 .clkr = { 2587 .enable_reg = 0x26018, 2588 .enable_mask = BIT(0), 2589 .hw.init = &(struct clk_init_data){ 2590 .name = "gcc_titan_rt_throttle_core_clk", 2591 .ops = &clk_branch2_ops, 2592 }, 2593 }, 2594 }; 2595 2596 static struct clk_branch gcc_ufs_1_clkref_en = { 2597 .halt_reg = 0x8c000, 2598 .halt_check = BRANCH_HALT, 2599 .clkr = { 2600 .enable_reg = 0x8c000, 2601 .enable_mask = BIT(0), 2602 .hw.init = &(struct clk_init_data){ 2603 .name = "gcc_ufs_1_clkref_en", 2604 .ops = &clk_branch2_ops, 2605 }, 2606 }, 2607 }; 2608 2609 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2610 .halt_reg = 0x77018, 2611 .halt_check = BRANCH_HALT_VOTED, 2612 .hwcg_reg = 0x77018, 2613 .hwcg_bit = 1, 2614 .clkr = { 2615 .enable_reg = 0x77018, 2616 .enable_mask = BIT(0), 2617 .hw.init = &(struct clk_init_data){ 2618 .name = "gcc_ufs_phy_ahb_clk", 2619 .ops = &clk_branch2_ops, 2620 }, 2621 }, 2622 }; 2623 2624 static struct clk_branch gcc_ufs_phy_axi_clk = { 2625 .halt_reg = 0x77010, 2626 .halt_check = BRANCH_HALT_VOTED, 2627 .hwcg_reg = 0x77010, 2628 .hwcg_bit = 1, 2629 .clkr = { 2630 .enable_reg = 0x77010, 2631 .enable_mask = BIT(0), 2632 .hw.init = &(struct clk_init_data){ 2633 .name = "gcc_ufs_phy_axi_clk", 2634 .parent_hws = (const struct clk_hw*[]){ 2635 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2636 }, 2637 .num_parents = 1, 2638 .flags = CLK_SET_RATE_PARENT, 2639 .ops = &clk_branch2_ops, 2640 }, 2641 }, 2642 }; 2643 2644 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2645 .halt_reg = 0x77064, 2646 .halt_check = BRANCH_HALT_VOTED, 2647 .hwcg_reg = 0x77064, 2648 .hwcg_bit = 1, 2649 .clkr = { 2650 .enable_reg = 0x77064, 2651 .enable_mask = BIT(0), 2652 .hw.init = &(struct clk_init_data){ 2653 .name = "gcc_ufs_phy_ice_core_clk", 2654 .parent_hws = (const struct clk_hw*[]){ 2655 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2656 }, 2657 .num_parents = 1, 2658 .flags = CLK_SET_RATE_PARENT, 2659 .ops = &clk_branch2_ops, 2660 }, 2661 }, 2662 }; 2663 2664 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2665 .halt_reg = 0x7709c, 2666 .halt_check = BRANCH_HALT_VOTED, 2667 .hwcg_reg = 0x7709c, 2668 .hwcg_bit = 1, 2669 .clkr = { 2670 .enable_reg = 0x7709c, 2671 .enable_mask = BIT(0), 2672 .hw.init = &(struct clk_init_data){ 2673 .name = "gcc_ufs_phy_phy_aux_clk", 2674 .parent_hws = (const struct clk_hw*[]){ 2675 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2676 }, 2677 .num_parents = 1, 2678 .flags = CLK_SET_RATE_PARENT, 2679 .ops = &clk_branch2_ops, 2680 }, 2681 }, 2682 }; 2683 2684 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2685 .halt_reg = 0x77020, 2686 .halt_check = BRANCH_HALT_DELAY, 2687 .clkr = { 2688 .enable_reg = 0x77020, 2689 .enable_mask = BIT(0), 2690 .hw.init = &(struct clk_init_data){ 2691 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2692 .parent_hws = (const struct clk_hw*[]){ 2693 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 2694 }, 2695 .num_parents = 1, 2696 .flags = CLK_SET_RATE_PARENT, 2697 .ops = &clk_branch2_ops, 2698 }, 2699 }, 2700 }; 2701 2702 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2703 .halt_reg = 0x770b8, 2704 .halt_check = BRANCH_HALT_DELAY, 2705 .clkr = { 2706 .enable_reg = 0x770b8, 2707 .enable_mask = BIT(0), 2708 .hw.init = &(struct clk_init_data){ 2709 .name = "gcc_ufs_phy_rx_symbol_1_clk", 2710 .parent_hws = (const struct clk_hw*[]){ 2711 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 2712 }, 2713 .num_parents = 1, 2714 .flags = CLK_SET_RATE_PARENT, 2715 .ops = &clk_branch2_ops, 2716 }, 2717 }, 2718 }; 2719 2720 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2721 .halt_reg = 0x7701c, 2722 .halt_check = BRANCH_HALT_DELAY, 2723 .clkr = { 2724 .enable_reg = 0x7701c, 2725 .enable_mask = BIT(0), 2726 .hw.init = &(struct clk_init_data){ 2727 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2728 .parent_hws = (const struct clk_hw*[]){ 2729 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 2730 }, 2731 .num_parents = 1, 2732 .flags = CLK_SET_RATE_PARENT, 2733 .ops = &clk_branch2_ops, 2734 }, 2735 }, 2736 }; 2737 2738 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2739 .halt_reg = 0x7705c, 2740 .halt_check = BRANCH_HALT_VOTED, 2741 .hwcg_reg = 0x7705c, 2742 .hwcg_bit = 1, 2743 .clkr = { 2744 .enable_reg = 0x7705c, 2745 .enable_mask = BIT(0), 2746 .hw.init = &(struct clk_init_data){ 2747 .name = "gcc_ufs_phy_unipro_core_clk", 2748 .parent_hws = (const struct clk_hw*[]){ 2749 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2750 }, 2751 .num_parents = 1, 2752 .flags = CLK_SET_RATE_PARENT, 2753 .ops = &clk_branch2_ops, 2754 }, 2755 }, 2756 }; 2757 2758 static struct clk_branch gcc_usb30_prim_master_clk = { 2759 .halt_reg = 0xf010, 2760 .halt_check = BRANCH_HALT, 2761 .clkr = { 2762 .enable_reg = 0xf010, 2763 .enable_mask = BIT(0), 2764 .hw.init = &(struct clk_init_data){ 2765 .name = "gcc_usb30_prim_master_clk", 2766 .parent_hws = (const struct clk_hw*[]){ 2767 &gcc_usb30_prim_master_clk_src.clkr.hw, 2768 }, 2769 .num_parents = 1, 2770 .flags = CLK_SET_RATE_PARENT, 2771 .ops = &clk_branch2_ops, 2772 }, 2773 }, 2774 }; 2775 2776 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2777 .halt_reg = 0xf01c, 2778 .halt_check = BRANCH_HALT, 2779 .clkr = { 2780 .enable_reg = 0xf01c, 2781 .enable_mask = BIT(0), 2782 .hw.init = &(struct clk_init_data){ 2783 .name = "gcc_usb30_prim_mock_utmi_clk", 2784 .parent_data = &(const struct clk_parent_data){ 2785 .hw = 2786 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2787 }, 2788 .num_parents = 1, 2789 .flags = CLK_SET_RATE_PARENT, 2790 .ops = &clk_branch2_ops, 2791 }, 2792 }, 2793 }; 2794 2795 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2796 .halt_reg = 0xf018, 2797 .halt_check = BRANCH_HALT, 2798 .clkr = { 2799 .enable_reg = 0xf018, 2800 .enable_mask = BIT(0), 2801 .hw.init = &(struct clk_init_data){ 2802 .name = "gcc_usb30_prim_sleep_clk", 2803 .ops = &clk_branch2_ops, 2804 }, 2805 }, 2806 }; 2807 2808 static struct clk_branch gcc_usb30_sec_master_clk = { 2809 .halt_reg = 0x9e010, 2810 .halt_check = BRANCH_HALT, 2811 .clkr = { 2812 .enable_reg = 0x9e010, 2813 .enable_mask = BIT(0), 2814 .hw.init = &(struct clk_init_data){ 2815 .name = "gcc_usb30_sec_master_clk", 2816 .parent_hws = (const struct clk_hw*[]){ 2817 &gcc_usb30_sec_master_clk_src.clkr.hw, 2818 }, 2819 .num_parents = 1, 2820 .flags = CLK_SET_RATE_PARENT, 2821 .ops = &clk_branch2_ops, 2822 }, 2823 }, 2824 }; 2825 2826 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { 2827 .halt_reg = 0x9e01c, 2828 .halt_check = BRANCH_HALT, 2829 .clkr = { 2830 .enable_reg = 0x9e01c, 2831 .enable_mask = BIT(0), 2832 .hw.init = &(struct clk_init_data){ 2833 .name = "gcc_usb30_sec_mock_utmi_clk", 2834 .parent_data = &(const struct clk_parent_data){ 2835 .hw = 2836 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw, 2837 }, 2838 .num_parents = 1, 2839 .flags = CLK_SET_RATE_PARENT, 2840 .ops = &clk_branch2_ops, 2841 }, 2842 }, 2843 }; 2844 2845 static struct clk_branch gcc_usb30_sec_sleep_clk = { 2846 .halt_reg = 0x9e018, 2847 .halt_check = BRANCH_HALT, 2848 .clkr = { 2849 .enable_reg = 0x9e018, 2850 .enable_mask = BIT(0), 2851 .hw.init = &(struct clk_init_data){ 2852 .name = "gcc_usb30_sec_sleep_clk", 2853 .ops = &clk_branch2_ops, 2854 }, 2855 }, 2856 }; 2857 2858 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2859 .halt_reg = 0xf054, 2860 .halt_check = BRANCH_HALT, 2861 .clkr = { 2862 .enable_reg = 0xf054, 2863 .enable_mask = BIT(0), 2864 .hw.init = &(struct clk_init_data){ 2865 .name = "gcc_usb3_prim_phy_aux_clk", 2866 .parent_hws = (const struct clk_hw*[]){ 2867 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2868 }, 2869 .num_parents = 1, 2870 .flags = CLK_SET_RATE_PARENT, 2871 .ops = &clk_branch2_ops, 2872 }, 2873 }, 2874 }; 2875 2876 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2877 .halt_reg = 0xf058, 2878 .halt_check = BRANCH_HALT, 2879 .clkr = { 2880 .enable_reg = 0xf058, 2881 .enable_mask = BIT(0), 2882 .hw.init = &(struct clk_init_data){ 2883 .name = "gcc_usb3_prim_phy_com_aux_clk", 2884 .parent_hws = (const struct clk_hw*[]){ 2885 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2886 }, 2887 .num_parents = 1, 2888 .flags = CLK_SET_RATE_PARENT, 2889 .ops = &clk_branch2_ops, 2890 }, 2891 }, 2892 }; 2893 2894 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2895 .halt_reg = 0xf05c, 2896 .halt_check = BRANCH_HALT_DELAY, 2897 .hwcg_reg = 0xf05c, 2898 .hwcg_bit = 1, 2899 .clkr = { 2900 .enable_reg = 0xf05c, 2901 .enable_mask = BIT(0), 2902 .hw.init = &(struct clk_init_data){ 2903 .name = "gcc_usb3_prim_phy_pipe_clk", 2904 .parent_hws = (const struct clk_hw*[]){ 2905 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 2906 }, 2907 .num_parents = 1, 2908 .flags = CLK_SET_RATE_PARENT, 2909 .ops = &clk_branch2_ops, 2910 }, 2911 }, 2912 }; 2913 2914 static struct clk_branch gcc_cfg_noc_lpass_clk = { 2915 .halt_reg = 0x47020, 2916 .halt_check = BRANCH_HALT, 2917 .clkr = { 2918 .enable_reg = 0x47020, 2919 .enable_mask = BIT(0), 2920 .hw.init = &(struct clk_init_data){ 2921 .name = "gcc_cfg_noc_lpass_clk", 2922 .ops = &clk_branch2_aon_ops, 2923 }, 2924 }, 2925 }; 2926 static struct clk_branch gcc_mss_cfg_ahb_clk = { 2927 .halt_reg = 0x8a000, 2928 .halt_check = BRANCH_HALT, 2929 .clkr = { 2930 .enable_reg = 0x8a000, 2931 .enable_mask = BIT(0), 2932 .hw.init = &(struct clk_init_data){ 2933 .name = "gcc_mss_cfg_ahb_clk", 2934 .ops = &clk_branch2_ops, 2935 }, 2936 }, 2937 }; 2938 2939 static struct clk_branch gcc_mss_offline_axi_clk = { 2940 .halt_reg = 0x8a004, 2941 .halt_check = BRANCH_HALT_DELAY, 2942 .clkr = { 2943 .enable_reg = 0x8a004, 2944 .enable_mask = BIT(0), 2945 .hw.init = &(struct clk_init_data){ 2946 .name = "gcc_mss_offline_axi_clk", 2947 .ops = &clk_branch2_ops, 2948 }, 2949 }, 2950 }; 2951 2952 static struct clk_branch gcc_mss_snoc_axi_clk = { 2953 .halt_reg = 0x8a154, 2954 .halt_check = BRANCH_HALT_DELAY, 2955 .clkr = { 2956 .enable_reg = 0x8a154, 2957 .enable_mask = BIT(0), 2958 .hw.init = &(struct clk_init_data){ 2959 .name = "gcc_mss_snoc_axi_clk", 2960 .ops = &clk_branch2_ops, 2961 }, 2962 }, 2963 }; 2964 2965 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = { 2966 .halt_reg = 0x8a158, 2967 .halt_check = BRANCH_HALT, 2968 .clkr = { 2969 .enable_reg = 0x8a158, 2970 .enable_mask = BIT(0), 2971 .hw.init = &(struct clk_init_data){ 2972 .name = "gcc_mss_q6_memnoc_axi_clk", 2973 .ops = &clk_branch2_ops, 2974 }, 2975 }, 2976 }; 2977 2978 static struct clk_regmap_mux gcc_mss_q6ss_boot_clk_src = { 2979 .reg = 0x8a2a4, 2980 .shift = 0, 2981 .width = 1, 2982 .parent_map = gcc_parent_map_15, 2983 .clkr = { 2984 .hw.init = &(struct clk_init_data){ 2985 .name = "gcc_mss_q6ss_boot_clk_src", 2986 .parent_data = gcc_parent_data_15, 2987 .num_parents = ARRAY_SIZE(gcc_parent_data_15), 2988 .ops = &clk_regmap_mux_closest_ops, 2989 }, 2990 }, 2991 }; 2992 2993 static struct clk_branch gcc_usb3_sec_phy_aux_clk = { 2994 .halt_reg = 0x9e054, 2995 .halt_check = BRANCH_HALT, 2996 .clkr = { 2997 .enable_reg = 0x9e054, 2998 .enable_mask = BIT(0), 2999 .hw.init = &(struct clk_init_data){ 3000 .name = "gcc_usb3_sec_phy_aux_clk", 3001 .parent_hws = (const struct clk_hw*[]){ 3002 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 3003 }, 3004 .num_parents = 1, 3005 .flags = CLK_SET_RATE_PARENT, 3006 .ops = &clk_branch2_ops, 3007 }, 3008 }, 3009 }; 3010 3011 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { 3012 .halt_reg = 0x9e058, 3013 .halt_check = BRANCH_HALT, 3014 .clkr = { 3015 .enable_reg = 0x9e058, 3016 .enable_mask = BIT(0), 3017 .hw.init = &(struct clk_init_data){ 3018 .name = "gcc_usb3_sec_phy_com_aux_clk", 3019 .parent_hws = (const struct clk_hw*[]){ 3020 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 3021 }, 3022 .num_parents = 1, 3023 .flags = CLK_SET_RATE_PARENT, 3024 .ops = &clk_branch2_ops, 3025 }, 3026 }, 3027 }; 3028 3029 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { 3030 .halt_reg = 0x9e05c, 3031 .halt_check = BRANCH_HALT_SKIP, 3032 .hwcg_reg = 0x9e05c, 3033 .hwcg_bit = 1, 3034 .clkr = { 3035 .enable_reg = 0x9e05c, 3036 .enable_mask = BIT(0), 3037 .hw.init = &(struct clk_init_data){ 3038 .name = "gcc_usb3_sec_phy_pipe_clk", 3039 .parent_hws = (const struct clk_hw*[]){ 3040 &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw, 3041 }, 3042 .num_parents = 1, 3043 .flags = CLK_SET_RATE_PARENT, 3044 .ops = &clk_branch2_ops, 3045 }, 3046 }, 3047 }; 3048 3049 static struct clk_branch gcc_video_axi0_clk = { 3050 .halt_reg = 0x2800c, 3051 .halt_check = BRANCH_HALT_SKIP, 3052 .hwcg_reg = 0x2800c, 3053 .hwcg_bit = 1, 3054 .clkr = { 3055 .enable_reg = 0x2800c, 3056 .enable_mask = BIT(0), 3057 .hw.init = &(struct clk_init_data){ 3058 .name = "gcc_video_axi0_clk", 3059 .ops = &clk_branch2_ops, 3060 }, 3061 }, 3062 }; 3063 3064 static struct clk_branch gcc_video_mvp_throttle_core_clk = { 3065 .halt_reg = 0x28010, 3066 .halt_check = BRANCH_HALT_SKIP, 3067 .hwcg_reg = 0x28010, 3068 .hwcg_bit = 1, 3069 .clkr = { 3070 .enable_reg = 0x28010, 3071 .enable_mask = BIT(0), 3072 .hw.init = &(struct clk_init_data){ 3073 .name = "gcc_video_mvp_throttle_core_clk", 3074 .ops = &clk_branch2_ops, 3075 }, 3076 }, 3077 }; 3078 3079 static struct clk_branch gcc_wpss_ahb_clk = { 3080 .halt_reg = 0x9d154, 3081 .halt_check = BRANCH_HALT, 3082 .clkr = { 3083 .enable_reg = 0x9d154, 3084 .enable_mask = BIT(0), 3085 .hw.init = &(struct clk_init_data){ 3086 .name = "gcc_wpss_ahb_clk", 3087 .ops = &clk_branch2_ops, 3088 }, 3089 }, 3090 }; 3091 3092 static struct clk_branch gcc_wpss_ahb_bdg_mst_clk = { 3093 .halt_reg = 0x9d158, 3094 .halt_check = BRANCH_HALT, 3095 .clkr = { 3096 .enable_reg = 0x9d158, 3097 .enable_mask = BIT(0), 3098 .hw.init = &(struct clk_init_data){ 3099 .name = "gcc_wpss_ahb_bdg_mst_clk", 3100 .ops = &clk_branch2_ops, 3101 }, 3102 }, 3103 }; 3104 3105 static struct clk_branch gcc_wpss_rscp_clk = { 3106 .halt_reg = 0x9d16c, 3107 .halt_check = BRANCH_HALT, 3108 .clkr = { 3109 .enable_reg = 0x9d16c, 3110 .enable_mask = BIT(0), 3111 .hw.init = &(struct clk_init_data){ 3112 .name = "gcc_wpss_rscp_clk", 3113 .ops = &clk_branch2_ops, 3114 }, 3115 }, 3116 }; 3117 3118 static struct gdsc gcc_pcie_0_gdsc = { 3119 .gdscr = 0x6b004, 3120 .pd = { 3121 .name = "gcc_pcie_0_gdsc", 3122 }, 3123 .pwrsts = PWRSTS_OFF_ON, 3124 .flags = VOTABLE, 3125 }; 3126 3127 static struct gdsc gcc_pcie_1_gdsc = { 3128 .gdscr = 0x8d004, 3129 .pd = { 3130 .name = "gcc_pcie_1_gdsc", 3131 }, 3132 .pwrsts = PWRSTS_OFF_ON, 3133 .flags = VOTABLE, 3134 }; 3135 3136 static struct gdsc gcc_ufs_phy_gdsc = { 3137 .gdscr = 0x77004, 3138 .pd = { 3139 .name = "gcc_ufs_phy_gdsc", 3140 }, 3141 .pwrsts = PWRSTS_OFF_ON, 3142 .flags = VOTABLE, 3143 }; 3144 3145 static struct gdsc gcc_usb30_prim_gdsc = { 3146 .gdscr = 0xf004, 3147 .pd = { 3148 .name = "gcc_usb30_prim_gdsc", 3149 }, 3150 .pwrsts = PWRSTS_OFF_ON, 3151 .flags = VOTABLE, 3152 }; 3153 3154 static struct gdsc gcc_usb30_sec_gdsc = { 3155 .gdscr = 0x9e004, 3156 .pd = { 3157 .name = "gcc_usb30_sec_gdsc", 3158 }, 3159 .pwrsts = PWRSTS_OFF_ON, 3160 .flags = VOTABLE, 3161 }; 3162 3163 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { 3164 .gdscr = 0x7d050, 3165 .pd = { 3166 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", 3167 }, 3168 .pwrsts = PWRSTS_OFF_ON, 3169 .flags = VOTABLE, 3170 }; 3171 3172 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = { 3173 .gdscr = 0x7d058, 3174 .pd = { 3175 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", 3176 }, 3177 .pwrsts = PWRSTS_OFF_ON, 3178 .flags = VOTABLE, 3179 }; 3180 3181 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = { 3182 .gdscr = 0x7d054, 3183 .pd = { 3184 .name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc", 3185 }, 3186 .pwrsts = PWRSTS_OFF_ON, 3187 .flags = VOTABLE, 3188 }; 3189 3190 static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { 3191 .gdscr = 0x7d05c, 3192 .pd = { 3193 .name = "hlos1_vote_turing_mmu_tbu0_gdsc", 3194 }, 3195 .pwrsts = PWRSTS_OFF_ON, 3196 .flags = VOTABLE, 3197 }; 3198 3199 static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = { 3200 .gdscr = 0x7d060, 3201 .pd = { 3202 .name = "hlos1_vote_turing_mmu_tbu1_gdsc", 3203 }, 3204 .pwrsts = PWRSTS_OFF_ON, 3205 .flags = VOTABLE, 3206 }; 3207 3208 static struct clk_regmap *gcc_sc7280_clocks[] = { 3209 [GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr, 3210 [GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr, 3211 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 3212 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 3213 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, 3214 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 3215 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 3216 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3217 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, 3218 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 3219 [GCC_DDRSS_PCIE_SF_CLK] = &gcc_ddrss_pcie_sf_clk.clkr, 3220 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 3221 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3222 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, 3223 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3224 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3225 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3226 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3227 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3228 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3229 [GCC_GPLL0] = &gcc_gpll0.clkr, 3230 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 3231 [GCC_GPLL0_OUT_ODD] = &gcc_gpll0_out_odd.clkr, 3232 [GCC_GPLL1] = &gcc_gpll1.clkr, 3233 [GCC_GPLL10] = &gcc_gpll10.clkr, 3234 [GCC_GPLL4] = &gcc_gpll4.clkr, 3235 [GCC_GPLL9] = &gcc_gpll9.clkr, 3236 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3237 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3238 [GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr, 3239 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3240 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3241 [GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr, 3242 [GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr, 3243 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3244 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 3245 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3246 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3247 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 3248 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3249 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 3250 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3251 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 3252 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 3253 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 3254 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 3255 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 3256 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 3257 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 3258 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr, 3259 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 3260 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 3261 [GCC_PCIE_THROTTLE_CORE_CLK] = &gcc_pcie_throttle_core_clk.clkr, 3262 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3263 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3264 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3265 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3266 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3267 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3268 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3269 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3270 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, 3271 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, 3272 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, 3273 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 3274 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 3275 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3276 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3277 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3278 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3279 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3280 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3281 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3282 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3283 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3284 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3285 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3286 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3287 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 3288 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 3289 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 3290 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 3291 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3292 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3293 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3294 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3295 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3296 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3297 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3298 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3299 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3300 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3301 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3302 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3303 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3304 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3305 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 3306 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 3307 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 3308 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 3309 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3310 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3311 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3312 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3313 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3314 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3315 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 3316 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 3317 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 3318 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3319 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3320 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3321 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3322 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3323 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 3324 [GCC_THROTTLE_PCIE_AHB_CLK] = &gcc_throttle_pcie_ahb_clk.clkr, 3325 [GCC_TITAN_NRT_THROTTLE_CORE_CLK] = 3326 &gcc_titan_nrt_throttle_core_clk.clkr, 3327 [GCC_TITAN_RT_THROTTLE_CORE_CLK] = &gcc_titan_rt_throttle_core_clk.clkr, 3328 [GCC_UFS_1_CLKREF_EN] = &gcc_ufs_1_clkref_en.clkr, 3329 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3330 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3331 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3332 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3333 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3334 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3335 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3336 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3337 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = 3338 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 3339 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3340 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = 3341 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 3342 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3343 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = 3344 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 3345 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3346 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 3347 &gcc_ufs_phy_unipro_core_clk_src.clkr, 3348 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3349 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3350 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3351 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 3352 &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3353 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = 3354 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3355 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3356 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, 3357 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, 3358 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, 3359 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = 3360 &gcc_usb30_sec_mock_utmi_clk_src.clkr, 3361 [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = 3362 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr, 3363 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, 3364 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3365 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3366 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3367 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3368 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 3369 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, 3370 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, 3371 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, 3372 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, 3373 [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr, 3374 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3375 [GCC_VIDEO_MVP_THROTTLE_CORE_CLK] = 3376 &gcc_video_mvp_throttle_core_clk.clkr, 3377 [GCC_CFG_NOC_LPASS_CLK] = &gcc_cfg_noc_lpass_clk.clkr, 3378 [GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC] = &gcc_mss_gpll0_main_div_clk_src.clkr, 3379 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 3380 [GCC_MSS_OFFLINE_AXI_CLK] = &gcc_mss_offline_axi_clk.clkr, 3381 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, 3382 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr, 3383 [GCC_MSS_Q6SS_BOOT_CLK_SRC] = &gcc_mss_q6ss_boot_clk_src.clkr, 3384 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, 3385 [GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK] = 3386 &gcc_aggre_noc_pcie_center_sf_axi_clk.clkr, 3387 [GCC_PCIE_CLKREF_EN] = &gcc_pcie_clkref_en.clkr, 3388 [GCC_EDP_CLKREF_EN] = &gcc_edp_clkref_en.clkr, 3389 [GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr, 3390 [GCC_WPSS_AHB_CLK] = &gcc_wpss_ahb_clk.clkr, 3391 [GCC_WPSS_AHB_BDG_MST_CLK] = &gcc_wpss_ahb_bdg_mst_clk.clkr, 3392 [GCC_WPSS_RSCP_CLK] = &gcc_wpss_rscp_clk.clkr, 3393 }; 3394 3395 static struct gdsc *gcc_sc7280_gdscs[] = { 3396 [GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc, 3397 [GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc, 3398 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, 3399 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 3400 [GCC_USB30_SEC_GDSC] = &gcc_usb30_sec_gdsc, 3401 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, 3402 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, 3403 [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc, 3404 [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc, 3405 [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, 3406 }; 3407 3408 static const struct qcom_reset_map gcc_sc7280_resets[] = { 3409 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3410 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3411 [GCC_PCIE_1_BCR] = { 0x8d000 }, 3412 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 3413 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3414 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3415 [GCC_SDCC1_BCR] = { 0x75000 }, 3416 [GCC_SDCC2_BCR] = { 0x14000 }, 3417 [GCC_SDCC4_BCR] = { 0x16000 }, 3418 [GCC_UFS_PHY_BCR] = { 0x77000 }, 3419 [GCC_USB30_PRIM_BCR] = { 0xf000 }, 3420 [GCC_USB30_SEC_BCR] = { 0x9e000 }, 3421 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 3422 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 3423 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3424 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 3425 }; 3426 3427 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3428 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3429 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3430 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3431 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3432 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3433 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3434 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 3435 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 3436 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3437 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3438 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 3439 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3440 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3441 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3442 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 3443 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 3444 }; 3445 3446 static const struct regmap_config gcc_sc7280_regmap_config = { 3447 .reg_bits = 32, 3448 .reg_stride = 4, 3449 .val_bits = 32, 3450 .max_register = 0x9f128, 3451 .fast_io = true, 3452 }; 3453 3454 static const struct qcom_cc_desc gcc_sc7280_desc = { 3455 .config = &gcc_sc7280_regmap_config, 3456 .clks = gcc_sc7280_clocks, 3457 .num_clks = ARRAY_SIZE(gcc_sc7280_clocks), 3458 .resets = gcc_sc7280_resets, 3459 .num_resets = ARRAY_SIZE(gcc_sc7280_resets), 3460 .gdscs = gcc_sc7280_gdscs, 3461 .num_gdscs = ARRAY_SIZE(gcc_sc7280_gdscs), 3462 }; 3463 3464 static const struct of_device_id gcc_sc7280_match_table[] = { 3465 { .compatible = "qcom,gcc-sc7280" }, 3466 { } 3467 }; 3468 MODULE_DEVICE_TABLE(of, gcc_sc7280_match_table); 3469 3470 static int gcc_sc7280_probe(struct platform_device *pdev) 3471 { 3472 struct regmap *regmap; 3473 int ret; 3474 3475 regmap = qcom_cc_map(pdev, &gcc_sc7280_desc); 3476 if (IS_ERR(regmap)) 3477 return PTR_ERR(regmap); 3478 3479 /* 3480 * Keep the clocks always-ON 3481 * GCC_CAMERA_AHB_CLK/XO_CLK, GCC_DISP_AHB_CLK/XO_CLK 3482 * GCC_VIDEO_AHB_CLK/XO_CLK, GCC_GPU_CFG_AHB_CLK 3483 */ 3484 regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); 3485 regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); 3486 regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); 3487 regmap_update_bits(regmap, 0x2701C, BIT(0), BIT(0)); 3488 regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); 3489 regmap_update_bits(regmap, 0x28014, BIT(0), BIT(0)); 3490 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 3491 3492 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3493 ARRAY_SIZE(gcc_dfs_clocks)); 3494 if (ret) 3495 return ret; 3496 3497 return qcom_cc_really_probe(pdev, &gcc_sc7280_desc, regmap); 3498 } 3499 3500 static struct platform_driver gcc_sc7280_driver = { 3501 .probe = gcc_sc7280_probe, 3502 .driver = { 3503 .name = "gcc-sc7280", 3504 .of_match_table = gcc_sc7280_match_table, 3505 }, 3506 }; 3507 3508 static int __init gcc_sc7280_init(void) 3509 { 3510 return platform_driver_register(&gcc_sc7280_driver); 3511 } 3512 subsys_initcall(gcc_sc7280_init); 3513 3514 static void __exit gcc_sc7280_exit(void) 3515 { 3516 platform_driver_unregister(&gcc_sc7280_driver); 3517 } 3518 module_exit(gcc_sc7280_exit); 3519 3520 MODULE_DESCRIPTION("QTI GCC SC7280 Driver"); 3521 MODULE_LICENSE("GPL v2"); 3522