1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/kernel.h> 8 #include <linux/module.h> 9 #include <linux/of_device.h> 10 #include <linux/of.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/clock/qcom,gcc-sc7280.h> 14 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap-divider.h" 19 #include "clk-regmap-mux.h" 20 #include "common.h" 21 #include "gdsc.h" 22 #include "reset.h" 23 24 enum { 25 P_BI_TCXO, 26 P_GCC_GPLL0_OUT_EVEN, 27 P_GCC_GPLL0_OUT_MAIN, 28 P_GCC_GPLL0_OUT_ODD, 29 P_GCC_GPLL10_OUT_MAIN, 30 P_GCC_GPLL4_OUT_MAIN, 31 P_GCC_GPLL9_OUT_MAIN, 32 P_PCIE_0_PIPE_CLK, 33 P_PCIE_1_PIPE_CLK, 34 P_SLEEP_CLK, 35 P_UFS_PHY_RX_SYMBOL_0_CLK, 36 P_UFS_PHY_RX_SYMBOL_1_CLK, 37 P_UFS_PHY_TX_SYMBOL_0_CLK, 38 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 39 P_GCC_MSS_GPLL0_MAIN_DIV_CLK, 40 }; 41 42 static struct clk_alpha_pll gcc_gpll0 = { 43 .offset = 0x0, 44 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 45 .clkr = { 46 .enable_reg = 0x52010, 47 .enable_mask = BIT(0), 48 .hw.init = &(struct clk_init_data){ 49 .name = "gcc_gpll0", 50 .parent_data = &(const struct clk_parent_data){ 51 .fw_name = "bi_tcxo", 52 }, 53 .num_parents = 1, 54 .ops = &clk_alpha_pll_fixed_lucid_ops, 55 }, 56 }, 57 }; 58 59 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 60 { 0x1, 2 }, 61 { } 62 }; 63 64 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 65 .offset = 0x0, 66 .post_div_shift = 8, 67 .post_div_table = post_div_table_gcc_gpll0_out_even, 68 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 69 .width = 4, 70 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 71 .clkr.hw.init = &(struct clk_init_data){ 72 .name = "gcc_gpll0_out_even", 73 .parent_hws = (const struct clk_hw*[]){ 74 &gcc_gpll0.clkr.hw, 75 }, 76 .num_parents = 1, 77 .ops = &clk_alpha_pll_postdiv_lucid_ops, 78 }, 79 }; 80 81 static const struct clk_div_table post_div_table_gcc_gpll0_out_odd[] = { 82 { 0x3, 3 }, 83 { } 84 }; 85 86 static struct clk_alpha_pll_postdiv gcc_gpll0_out_odd = { 87 .offset = 0x0, 88 .post_div_shift = 12, 89 .post_div_table = post_div_table_gcc_gpll0_out_odd, 90 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_odd), 91 .width = 4, 92 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 93 .clkr.hw.init = &(struct clk_init_data){ 94 .name = "gcc_gpll0_out_odd", 95 .parent_hws = (const struct clk_hw*[]){ 96 &gcc_gpll0.clkr.hw, 97 }, 98 .num_parents = 1, 99 .ops = &clk_alpha_pll_postdiv_lucid_ops, 100 }, 101 }; 102 103 static struct clk_alpha_pll gcc_gpll1 = { 104 .offset = 0x1000, 105 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 106 .clkr = { 107 .enable_reg = 0x52010, 108 .enable_mask = BIT(1), 109 .hw.init = &(struct clk_init_data){ 110 .name = "gcc_gpll1", 111 .parent_data = &(const struct clk_parent_data){ 112 .fw_name = "bi_tcxo", 113 }, 114 .num_parents = 1, 115 .ops = &clk_alpha_pll_fixed_lucid_ops, 116 }, 117 }, 118 }; 119 120 static struct clk_alpha_pll gcc_gpll10 = { 121 .offset = 0x1e000, 122 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 123 .clkr = { 124 .enable_reg = 0x52010, 125 .enable_mask = BIT(9), 126 .hw.init = &(struct clk_init_data){ 127 .name = "gcc_gpll10", 128 .parent_data = &(const struct clk_parent_data){ 129 .fw_name = "bi_tcxo", 130 }, 131 .num_parents = 1, 132 .ops = &clk_alpha_pll_fixed_lucid_ops, 133 }, 134 }, 135 }; 136 137 static struct clk_alpha_pll gcc_gpll4 = { 138 .offset = 0x76000, 139 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 140 .clkr = { 141 .enable_reg = 0x52010, 142 .enable_mask = BIT(4), 143 .hw.init = &(struct clk_init_data){ 144 .name = "gcc_gpll4", 145 .parent_data = &(const struct clk_parent_data){ 146 .fw_name = "bi_tcxo", 147 }, 148 .num_parents = 1, 149 .ops = &clk_alpha_pll_fixed_lucid_ops, 150 }, 151 }, 152 }; 153 154 static struct clk_alpha_pll gcc_gpll9 = { 155 .offset = 0x1c000, 156 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 157 .clkr = { 158 .enable_reg = 0x52010, 159 .enable_mask = BIT(8), 160 .hw.init = &(struct clk_init_data){ 161 .name = "gcc_gpll9", 162 .parent_data = &(const struct clk_parent_data){ 163 .fw_name = "bi_tcxo", 164 }, 165 .num_parents = 1, 166 .ops = &clk_alpha_pll_fixed_lucid_ops, 167 }, 168 }, 169 }; 170 171 static struct clk_branch gcc_mss_gpll0_main_div_clk_src = { 172 .halt_check = BRANCH_HALT_DELAY, 173 .clkr = { 174 .enable_reg = 0x52000, 175 .enable_mask = BIT(17), 176 .hw.init = &(struct clk_init_data){ 177 .name = "gcc_mss_gpll0_main_div_clk_src", 178 .parent_hws = (const struct clk_hw*[]){ 179 &gcc_gpll0_out_even.clkr.hw, 180 }, 181 .num_parents = 1, 182 .flags = CLK_SET_RATE_PARENT, 183 .ops = &clk_branch2_ops, 184 }, 185 }, 186 }; 187 188 static const struct parent_map gcc_parent_map_0[] = { 189 { P_BI_TCXO, 0 }, 190 { P_GCC_GPLL0_OUT_MAIN, 1 }, 191 { P_GCC_GPLL0_OUT_EVEN, 6 }, 192 }; 193 194 static const struct clk_parent_data gcc_parent_data_0[] = { 195 { .fw_name = "bi_tcxo" }, 196 { .hw = &gcc_gpll0.clkr.hw }, 197 { .hw = &gcc_gpll0_out_even.clkr.hw }, 198 }; 199 200 static const struct clk_parent_data gcc_parent_data_0_ao[] = { 201 { .fw_name = "bi_tcxo_ao" }, 202 { .hw = &gcc_gpll0.clkr.hw }, 203 { .hw = &gcc_gpll0_out_even.clkr.hw }, 204 }; 205 206 static const struct parent_map gcc_parent_map_1[] = { 207 { P_BI_TCXO, 0 }, 208 { P_GCC_GPLL0_OUT_MAIN, 1 }, 209 { P_GCC_GPLL0_OUT_ODD, 3 }, 210 { P_GCC_GPLL0_OUT_EVEN, 6 }, 211 }; 212 213 static const struct clk_parent_data gcc_parent_data_1[] = { 214 { .fw_name = "bi_tcxo" }, 215 { .hw = &gcc_gpll0.clkr.hw }, 216 { .hw = &gcc_gpll0_out_odd.clkr.hw }, 217 { .hw = &gcc_gpll0_out_even.clkr.hw }, 218 }; 219 220 static const struct parent_map gcc_parent_map_2[] = { 221 { P_BI_TCXO, 0 }, 222 { P_SLEEP_CLK, 5 }, 223 }; 224 225 static const struct clk_parent_data gcc_parent_data_2[] = { 226 { .fw_name = "bi_tcxo" }, 227 { .fw_name = "sleep_clk" }, 228 }; 229 230 static const struct parent_map gcc_parent_map_3[] = { 231 { P_BI_TCXO, 0 }, 232 }; 233 234 static const struct clk_parent_data gcc_parent_data_3[] = { 235 { .fw_name = "bi_tcxo" }, 236 }; 237 238 static const struct parent_map gcc_parent_map_4[] = { 239 { P_BI_TCXO, 0 }, 240 { P_GCC_GPLL0_OUT_MAIN, 1 }, 241 { P_GCC_GPLL0_OUT_ODD, 3 }, 242 { P_SLEEP_CLK, 5 }, 243 { P_GCC_GPLL0_OUT_EVEN, 6 }, 244 }; 245 246 static const struct clk_parent_data gcc_parent_data_4[] = { 247 { .fw_name = "bi_tcxo" }, 248 { .hw = &gcc_gpll0.clkr.hw }, 249 { .hw = &gcc_gpll0_out_odd.clkr.hw }, 250 { .fw_name = "sleep_clk" }, 251 { .hw = &gcc_gpll0_out_even.clkr.hw }, 252 }; 253 254 static const struct parent_map gcc_parent_map_5[] = { 255 { P_BI_TCXO, 0 }, 256 { P_GCC_GPLL0_OUT_EVEN, 6 }, 257 }; 258 259 static const struct clk_parent_data gcc_parent_data_5[] = { 260 { .fw_name = "bi_tcxo" }, 261 { .hw = &gcc_gpll0_out_even.clkr.hw }, 262 }; 263 264 static const struct parent_map gcc_parent_map_6[] = { 265 { P_PCIE_0_PIPE_CLK, 0 }, 266 { P_BI_TCXO, 2 }, 267 }; 268 269 static const struct clk_parent_data gcc_parent_data_6[] = { 270 { .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" }, 271 { .fw_name = "bi_tcxo" }, 272 }; 273 274 static const struct parent_map gcc_parent_map_7[] = { 275 { P_PCIE_1_PIPE_CLK, 0 }, 276 { P_BI_TCXO, 2 }, 277 }; 278 279 static const struct clk_parent_data gcc_parent_data_7[] = { 280 { .fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk" }, 281 { .fw_name = "bi_tcxo" }, 282 }; 283 284 static const struct parent_map gcc_parent_map_8[] = { 285 { P_BI_TCXO, 0 }, 286 { P_GCC_GPLL0_OUT_MAIN, 1 }, 287 { P_GCC_GPLL0_OUT_ODD, 3 }, 288 { P_GCC_GPLL10_OUT_MAIN, 5 }, 289 { P_GCC_GPLL0_OUT_EVEN, 6 }, 290 }; 291 292 static const struct clk_parent_data gcc_parent_data_8[] = { 293 { .fw_name = "bi_tcxo" }, 294 { .hw = &gcc_gpll0.clkr.hw }, 295 { .hw = &gcc_gpll0_out_odd.clkr.hw }, 296 { .hw = &gcc_gpll10.clkr.hw }, 297 { .hw = &gcc_gpll0_out_even.clkr.hw }, 298 }; 299 300 static const struct parent_map gcc_parent_map_9[] = { 301 { P_BI_TCXO, 0 }, 302 { P_GCC_GPLL0_OUT_MAIN, 1 }, 303 { P_GCC_GPLL9_OUT_MAIN, 2 }, 304 { P_GCC_GPLL0_OUT_ODD, 3 }, 305 { P_GCC_GPLL4_OUT_MAIN, 5 }, 306 { P_GCC_GPLL0_OUT_EVEN, 6 }, 307 }; 308 309 static const struct clk_parent_data gcc_parent_data_9[] = { 310 { .fw_name = "bi_tcxo" }, 311 { .hw = &gcc_gpll0.clkr.hw }, 312 { .hw = &gcc_gpll9.clkr.hw }, 313 { .hw = &gcc_gpll0_out_odd.clkr.hw }, 314 { .hw = &gcc_gpll4.clkr.hw }, 315 { .hw = &gcc_gpll0_out_even.clkr.hw }, 316 }; 317 318 static const struct parent_map gcc_parent_map_10[] = { 319 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, 320 { P_BI_TCXO, 2 }, 321 }; 322 323 static const struct clk_parent_data gcc_parent_data_10[] = { 324 { .fw_name = "ufs_phy_rx_symbol_0_clk" }, 325 { .fw_name = "bi_tcxo" }, 326 }; 327 328 static const struct parent_map gcc_parent_map_11[] = { 329 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, 330 { P_BI_TCXO, 2 }, 331 }; 332 333 static const struct clk_parent_data gcc_parent_data_11[] = { 334 { .fw_name = "ufs_phy_rx_symbol_1_clk" }, 335 { .fw_name = "bi_tcxo" }, 336 }; 337 338 static const struct parent_map gcc_parent_map_12[] = { 339 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, 340 { P_BI_TCXO, 2 }, 341 }; 342 343 static const struct clk_parent_data gcc_parent_data_12[] = { 344 { .fw_name = "ufs_phy_tx_symbol_0_clk" }, 345 { .fw_name = "bi_tcxo" }, 346 }; 347 348 static const struct parent_map gcc_parent_map_13[] = { 349 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 350 { P_BI_TCXO, 2 }, 351 }; 352 353 static const struct clk_parent_data gcc_parent_data_13[] = { 354 { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" }, 355 { .fw_name = "bi_tcxo" }, 356 }; 357 358 static const struct parent_map gcc_parent_map_14[] = { 359 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 360 { P_BI_TCXO, 2 }, 361 }; 362 363 static const struct clk_parent_data gcc_parent_data_14[] = { 364 { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" }, 365 { .fw_name = "bi_tcxo" }, 366 }; 367 368 static const struct parent_map gcc_parent_map_15[] = { 369 { P_BI_TCXO, 0 }, 370 { P_GCC_MSS_GPLL0_MAIN_DIV_CLK, 1 }, 371 }; 372 373 static const struct clk_parent_data gcc_parent_data_15[] = { 374 { .fw_name = "bi_tcxo" }, 375 { .hw = &gcc_mss_gpll0_main_div_clk_src.clkr.hw }, 376 }; 377 378 static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { 379 .reg = 0x6b054, 380 .shift = 0, 381 .width = 2, 382 .parent_map = gcc_parent_map_6, 383 .clkr = { 384 .hw.init = &(struct clk_init_data){ 385 .name = "gcc_pcie_0_pipe_clk_src", 386 .parent_data = gcc_parent_data_6, 387 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 388 .ops = &clk_regmap_mux_closest_ops, 389 }, 390 }, 391 }; 392 393 static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { 394 .reg = 0x8d054, 395 .shift = 0, 396 .width = 2, 397 .parent_map = gcc_parent_map_7, 398 .clkr = { 399 .hw.init = &(struct clk_init_data){ 400 .name = "gcc_pcie_1_pipe_clk_src", 401 .parent_data = gcc_parent_data_7, 402 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 403 .ops = &clk_regmap_mux_closest_ops, 404 }, 405 }, 406 }; 407 408 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 409 .reg = 0x77058, 410 .shift = 0, 411 .width = 2, 412 .parent_map = gcc_parent_map_10, 413 .clkr = { 414 .hw.init = &(struct clk_init_data){ 415 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 416 .parent_data = gcc_parent_data_10, 417 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 418 .ops = &clk_regmap_mux_closest_ops, 419 }, 420 }, 421 }; 422 423 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 424 .reg = 0x770c8, 425 .shift = 0, 426 .width = 2, 427 .parent_map = gcc_parent_map_11, 428 .clkr = { 429 .hw.init = &(struct clk_init_data){ 430 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 431 .parent_data = gcc_parent_data_11, 432 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 433 .ops = &clk_regmap_mux_closest_ops, 434 }, 435 }, 436 }; 437 438 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 439 .reg = 0x77048, 440 .shift = 0, 441 .width = 2, 442 .parent_map = gcc_parent_map_12, 443 .clkr = { 444 .hw.init = &(struct clk_init_data){ 445 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 446 .parent_data = gcc_parent_data_12, 447 .num_parents = ARRAY_SIZE(gcc_parent_data_12), 448 .ops = &clk_regmap_mux_closest_ops, 449 }, 450 }, 451 }; 452 453 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 454 .reg = 0xf060, 455 .shift = 0, 456 .width = 2, 457 .parent_map = gcc_parent_map_13, 458 .clkr = { 459 .hw.init = &(struct clk_init_data){ 460 .name = "gcc_usb3_prim_phy_pipe_clk_src", 461 .parent_data = gcc_parent_data_13, 462 .num_parents = ARRAY_SIZE(gcc_parent_data_13), 463 .ops = &clk_regmap_mux_closest_ops, 464 }, 465 }, 466 }; 467 468 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = { 469 .reg = 0x9e060, 470 .shift = 0, 471 .width = 2, 472 .parent_map = gcc_parent_map_14, 473 .clkr = { 474 .hw.init = &(struct clk_init_data){ 475 .name = "gcc_usb3_sec_phy_pipe_clk_src", 476 .parent_data = gcc_parent_data_14, 477 .num_parents = ARRAY_SIZE(gcc_parent_data_14), 478 .ops = &clk_regmap_mux_closest_ops, 479 }, 480 }, 481 }; 482 483 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 484 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 485 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 486 F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0), 487 { } 488 }; 489 490 static struct clk_rcg2 gcc_gp1_clk_src = { 491 .cmd_rcgr = 0x64004, 492 .mnd_width = 16, 493 .hid_width = 5, 494 .parent_map = gcc_parent_map_4, 495 .freq_tbl = ftbl_gcc_gp1_clk_src, 496 .clkr.hw.init = &(struct clk_init_data){ 497 .name = "gcc_gp1_clk_src", 498 .parent_data = gcc_parent_data_4, 499 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 500 .ops = &clk_rcg2_ops, 501 }, 502 }; 503 504 static struct clk_rcg2 gcc_gp2_clk_src = { 505 .cmd_rcgr = 0x65004, 506 .mnd_width = 16, 507 .hid_width = 5, 508 .parent_map = gcc_parent_map_4, 509 .freq_tbl = ftbl_gcc_gp1_clk_src, 510 .clkr.hw.init = &(struct clk_init_data){ 511 .name = "gcc_gp2_clk_src", 512 .parent_data = gcc_parent_data_4, 513 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 514 .ops = &clk_rcg2_ops, 515 }, 516 }; 517 518 static struct clk_rcg2 gcc_gp3_clk_src = { 519 .cmd_rcgr = 0x66004, 520 .mnd_width = 16, 521 .hid_width = 5, 522 .parent_map = gcc_parent_map_4, 523 .freq_tbl = ftbl_gcc_gp1_clk_src, 524 .clkr.hw.init = &(struct clk_init_data){ 525 .name = "gcc_gp3_clk_src", 526 .parent_data = gcc_parent_data_4, 527 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 528 .ops = &clk_rcg2_ops, 529 }, 530 }; 531 532 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 533 F(9600000, P_BI_TCXO, 2, 0, 0), 534 F(19200000, P_BI_TCXO, 1, 0, 0), 535 { } 536 }; 537 538 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 539 .cmd_rcgr = 0x6b058, 540 .mnd_width = 16, 541 .hid_width = 5, 542 .parent_map = gcc_parent_map_2, 543 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 544 .clkr.hw.init = &(struct clk_init_data){ 545 .name = "gcc_pcie_0_aux_clk_src", 546 .parent_data = gcc_parent_data_2, 547 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 548 .ops = &clk_rcg2_ops, 549 }, 550 }; 551 552 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 553 F(19200000, P_BI_TCXO, 1, 0, 0), 554 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 555 { } 556 }; 557 558 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 559 .cmd_rcgr = 0x6b03c, 560 .mnd_width = 0, 561 .hid_width = 5, 562 .parent_map = gcc_parent_map_0, 563 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 564 .clkr.hw.init = &(struct clk_init_data){ 565 .name = "gcc_pcie_0_phy_rchng_clk_src", 566 .parent_data = gcc_parent_data_0, 567 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 568 .ops = &clk_rcg2_ops, 569 }, 570 }; 571 572 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 573 .cmd_rcgr = 0x8d058, 574 .mnd_width = 16, 575 .hid_width = 5, 576 .parent_map = gcc_parent_map_2, 577 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 578 .clkr.hw.init = &(struct clk_init_data){ 579 .name = "gcc_pcie_1_aux_clk_src", 580 .parent_data = gcc_parent_data_2, 581 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 582 .ops = &clk_rcg2_ops, 583 }, 584 }; 585 586 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 587 .cmd_rcgr = 0x8d03c, 588 .mnd_width = 0, 589 .hid_width = 5, 590 .parent_map = gcc_parent_map_0, 591 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 592 .clkr.hw.init = &(struct clk_init_data){ 593 .name = "gcc_pcie_1_phy_rchng_clk_src", 594 .parent_data = gcc_parent_data_0, 595 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 596 .flags = CLK_SET_RATE_PARENT, 597 .ops = &clk_rcg2_ops, 598 }, 599 }; 600 601 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 602 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0), 603 { } 604 }; 605 606 static struct clk_rcg2 gcc_pdm2_clk_src = { 607 .cmd_rcgr = 0x33010, 608 .mnd_width = 0, 609 .hid_width = 5, 610 .parent_map = gcc_parent_map_0, 611 .freq_tbl = ftbl_gcc_pdm2_clk_src, 612 .clkr.hw.init = &(struct clk_init_data){ 613 .name = "gcc_pdm2_clk_src", 614 .parent_data = gcc_parent_data_0, 615 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 616 .flags = CLK_SET_RATE_PARENT, 617 .ops = &clk_rcg2_ops, 618 }, 619 }; 620 621 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { 622 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 623 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 624 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 625 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 626 { } 627 }; 628 629 static struct clk_rcg2 gcc_qspi_core_clk_src = { 630 .cmd_rcgr = 0x4b00c, 631 .mnd_width = 0, 632 .hid_width = 5, 633 .parent_map = gcc_parent_map_0, 634 .freq_tbl = ftbl_gcc_qspi_core_clk_src, 635 .clkr.hw.init = &(struct clk_init_data){ 636 .name = "gcc_qspi_core_clk_src", 637 .parent_data = gcc_parent_data_0, 638 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 639 .ops = &clk_rcg2_floor_ops, 640 }, 641 }; 642 643 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 644 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 645 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 646 F(19200000, P_BI_TCXO, 1, 0, 0), 647 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 648 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 649 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 650 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 651 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 652 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 653 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 654 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 655 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 656 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 657 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 658 F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0), 659 { } 660 }; 661 662 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 663 .name = "gcc_qupv3_wrap0_s0_clk_src", 664 .parent_data = gcc_parent_data_0, 665 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 666 .ops = &clk_rcg2_ops, 667 }; 668 669 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 670 .cmd_rcgr = 0x17010, 671 .mnd_width = 16, 672 .hid_width = 5, 673 .parent_map = gcc_parent_map_0, 674 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 675 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 676 }; 677 678 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 679 .name = "gcc_qupv3_wrap0_s1_clk_src", 680 .parent_data = gcc_parent_data_0, 681 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 682 .ops = &clk_rcg2_ops, 683 }; 684 685 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 686 .cmd_rcgr = 0x17140, 687 .mnd_width = 16, 688 .hid_width = 5, 689 .parent_map = gcc_parent_map_0, 690 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 691 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 692 }; 693 694 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = { 695 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 696 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 697 F(19200000, P_BI_TCXO, 1, 0, 0), 698 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 699 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 700 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 701 F(52174000, P_GCC_GPLL0_OUT_MAIN, 1, 2, 23), 702 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 703 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 704 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 705 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 706 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 707 { } 708 }; 709 710 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 711 .name = "gcc_qupv3_wrap0_s2_clk_src", 712 .parent_data = gcc_parent_data_0, 713 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 714 .ops = &clk_rcg2_ops, 715 }; 716 717 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 718 .cmd_rcgr = 0x17270, 719 .mnd_width = 16, 720 .hid_width = 5, 721 .parent_map = gcc_parent_map_0, 722 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 723 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 724 }; 725 726 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 727 .name = "gcc_qupv3_wrap0_s3_clk_src", 728 .parent_data = gcc_parent_data_0, 729 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 730 .ops = &clk_rcg2_ops, 731 }; 732 733 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 734 .cmd_rcgr = 0x173a0, 735 .mnd_width = 16, 736 .hid_width = 5, 737 .parent_map = gcc_parent_map_0, 738 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 739 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 740 }; 741 742 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 743 .name = "gcc_qupv3_wrap0_s4_clk_src", 744 .parent_data = gcc_parent_data_0, 745 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 746 .ops = &clk_rcg2_ops, 747 }; 748 749 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 750 .cmd_rcgr = 0x174d0, 751 .mnd_width = 16, 752 .hid_width = 5, 753 .parent_map = gcc_parent_map_0, 754 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 755 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 756 }; 757 758 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 759 .name = "gcc_qupv3_wrap0_s5_clk_src", 760 .parent_data = gcc_parent_data_0, 761 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 762 .ops = &clk_rcg2_ops, 763 }; 764 765 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 766 .cmd_rcgr = 0x17600, 767 .mnd_width = 16, 768 .hid_width = 5, 769 .parent_map = gcc_parent_map_0, 770 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 771 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 772 }; 773 774 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 775 .name = "gcc_qupv3_wrap0_s6_clk_src", 776 .parent_data = gcc_parent_data_0, 777 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 778 .ops = &clk_rcg2_ops, 779 }; 780 781 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 782 .cmd_rcgr = 0x17730, 783 .mnd_width = 16, 784 .hid_width = 5, 785 .parent_map = gcc_parent_map_0, 786 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 787 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 788 }; 789 790 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 791 .name = "gcc_qupv3_wrap0_s7_clk_src", 792 .parent_data = gcc_parent_data_0, 793 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 794 .ops = &clk_rcg2_ops, 795 }; 796 797 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 798 .cmd_rcgr = 0x17860, 799 .mnd_width = 16, 800 .hid_width = 5, 801 .parent_map = gcc_parent_map_0, 802 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 803 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 804 }; 805 806 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 807 .name = "gcc_qupv3_wrap1_s0_clk_src", 808 .parent_data = gcc_parent_data_0, 809 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 810 .ops = &clk_rcg2_ops, 811 }; 812 813 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 814 .cmd_rcgr = 0x18010, 815 .mnd_width = 16, 816 .hid_width = 5, 817 .parent_map = gcc_parent_map_0, 818 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 819 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 820 }; 821 822 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 823 .name = "gcc_qupv3_wrap1_s1_clk_src", 824 .parent_data = gcc_parent_data_0, 825 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 826 .ops = &clk_rcg2_ops, 827 }; 828 829 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 830 .cmd_rcgr = 0x18140, 831 .mnd_width = 16, 832 .hid_width = 5, 833 .parent_map = gcc_parent_map_0, 834 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 835 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 836 }; 837 838 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 839 .name = "gcc_qupv3_wrap1_s2_clk_src", 840 .parent_data = gcc_parent_data_0, 841 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 842 .ops = &clk_rcg2_ops, 843 }; 844 845 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 846 .cmd_rcgr = 0x18270, 847 .mnd_width = 16, 848 .hid_width = 5, 849 .parent_map = gcc_parent_map_0, 850 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 851 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 852 }; 853 854 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 855 .name = "gcc_qupv3_wrap1_s3_clk_src", 856 .parent_data = gcc_parent_data_0, 857 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 858 .ops = &clk_rcg2_ops, 859 }; 860 861 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 862 .cmd_rcgr = 0x183a0, 863 .mnd_width = 16, 864 .hid_width = 5, 865 .parent_map = gcc_parent_map_0, 866 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 867 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 868 }; 869 870 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 871 .name = "gcc_qupv3_wrap1_s4_clk_src", 872 .parent_data = gcc_parent_data_0, 873 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 874 .ops = &clk_rcg2_ops, 875 }; 876 877 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 878 .cmd_rcgr = 0x184d0, 879 .mnd_width = 16, 880 .hid_width = 5, 881 .parent_map = gcc_parent_map_0, 882 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 883 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 884 }; 885 886 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 887 .name = "gcc_qupv3_wrap1_s5_clk_src", 888 .parent_data = gcc_parent_data_0, 889 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 890 .ops = &clk_rcg2_ops, 891 }; 892 893 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 894 .cmd_rcgr = 0x18600, 895 .mnd_width = 16, 896 .hid_width = 5, 897 .parent_map = gcc_parent_map_0, 898 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 899 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 900 }; 901 902 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 903 .name = "gcc_qupv3_wrap1_s6_clk_src", 904 .parent_data = gcc_parent_data_0, 905 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 906 .ops = &clk_rcg2_ops, 907 }; 908 909 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 910 .cmd_rcgr = 0x18730, 911 .mnd_width = 16, 912 .hid_width = 5, 913 .parent_map = gcc_parent_map_0, 914 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 915 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 916 }; 917 918 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 919 .name = "gcc_qupv3_wrap1_s7_clk_src", 920 .parent_data = gcc_parent_data_0, 921 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 922 .ops = &clk_rcg2_ops, 923 }; 924 925 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 926 .cmd_rcgr = 0x18860, 927 .mnd_width = 16, 928 .hid_width = 5, 929 .parent_map = gcc_parent_map_0, 930 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 931 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 932 }; 933 934 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 935 F(144000, P_BI_TCXO, 16, 3, 25), 936 F(400000, P_BI_TCXO, 12, 1, 4), 937 F(19200000, P_BI_TCXO, 1, 0, 0), 938 F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3), 939 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 940 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 941 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 942 F(192000000, P_GCC_GPLL10_OUT_MAIN, 2, 0, 0), 943 F(384000000, P_GCC_GPLL10_OUT_MAIN, 1, 0, 0), 944 { } 945 }; 946 947 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 948 .cmd_rcgr = 0x7500c, 949 .mnd_width = 8, 950 .hid_width = 5, 951 .parent_map = gcc_parent_map_8, 952 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 953 .clkr.hw.init = &(struct clk_init_data){ 954 .name = "gcc_sdcc1_apps_clk_src", 955 .parent_data = gcc_parent_data_8, 956 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 957 .ops = &clk_rcg2_floor_ops, 958 }, 959 }; 960 961 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 962 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 963 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 964 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0), 965 { } 966 }; 967 968 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 969 .cmd_rcgr = 0x7502c, 970 .mnd_width = 0, 971 .hid_width = 5, 972 .parent_map = gcc_parent_map_1, 973 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 974 .clkr.hw.init = &(struct clk_init_data){ 975 .name = "gcc_sdcc1_ice_core_clk_src", 976 .parent_data = gcc_parent_data_1, 977 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 978 .ops = &clk_rcg2_floor_ops, 979 }, 980 }; 981 982 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 983 F(400000, P_BI_TCXO, 12, 1, 4), 984 F(19200000, P_BI_TCXO, 1, 0, 0), 985 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 986 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 987 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 988 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 989 { } 990 }; 991 992 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 993 .cmd_rcgr = 0x1400c, 994 .mnd_width = 8, 995 .hid_width = 5, 996 .parent_map = gcc_parent_map_9, 997 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 998 .clkr.hw.init = &(struct clk_init_data){ 999 .name = "gcc_sdcc2_apps_clk_src", 1000 .parent_data = gcc_parent_data_9, 1001 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 1002 .flags = CLK_OPS_PARENT_ENABLE, 1003 .ops = &clk_rcg2_floor_ops, 1004 }, 1005 }; 1006 1007 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 1008 F(400000, P_BI_TCXO, 12, 1, 4), 1009 F(19200000, P_BI_TCXO, 1, 0, 0), 1010 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1011 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 1012 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1013 { } 1014 }; 1015 1016 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 1017 .cmd_rcgr = 0x1600c, 1018 .mnd_width = 8, 1019 .hid_width = 5, 1020 .parent_map = gcc_parent_map_1, 1021 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 1022 .clkr.hw.init = &(struct clk_init_data){ 1023 .name = "gcc_sdcc4_apps_clk_src", 1024 .parent_data = gcc_parent_data_1, 1025 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1026 .ops = &clk_rcg2_floor_ops, 1027 }, 1028 }; 1029 1030 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1031 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1032 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1033 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 1034 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0), 1035 { } 1036 }; 1037 1038 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1039 .cmd_rcgr = 0x77024, 1040 .mnd_width = 8, 1041 .hid_width = 5, 1042 .parent_map = gcc_parent_map_0, 1043 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1044 .clkr.hw.init = &(struct clk_init_data){ 1045 .name = "gcc_ufs_phy_axi_clk_src", 1046 .parent_data = gcc_parent_data_0, 1047 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1048 .ops = &clk_rcg2_ops, 1049 }, 1050 }; 1051 1052 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1053 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1054 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 1055 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0), 1056 { } 1057 }; 1058 1059 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1060 .cmd_rcgr = 0x7706c, 1061 .mnd_width = 0, 1062 .hid_width = 5, 1063 .parent_map = gcc_parent_map_0, 1064 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1065 .clkr.hw.init = &(struct clk_init_data){ 1066 .name = "gcc_ufs_phy_ice_core_clk_src", 1067 .parent_data = gcc_parent_data_0, 1068 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1069 .ops = &clk_rcg2_ops, 1070 }, 1071 }; 1072 1073 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1074 .cmd_rcgr = 0x770a0, 1075 .mnd_width = 0, 1076 .hid_width = 5, 1077 .parent_map = gcc_parent_map_3, 1078 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1079 .clkr.hw.init = &(struct clk_init_data){ 1080 .name = "gcc_ufs_phy_phy_aux_clk_src", 1081 .parent_data = gcc_parent_data_3, 1082 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1083 .ops = &clk_rcg2_ops, 1084 }, 1085 }; 1086 1087 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1088 .cmd_rcgr = 0x77084, 1089 .mnd_width = 0, 1090 .hid_width = 5, 1091 .parent_map = gcc_parent_map_0, 1092 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1093 .clkr.hw.init = &(struct clk_init_data){ 1094 .name = "gcc_ufs_phy_unipro_core_clk_src", 1095 .parent_data = gcc_parent_data_0, 1096 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1097 .ops = &clk_rcg2_ops, 1098 }, 1099 }; 1100 1101 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1102 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 1103 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1104 F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0), 1105 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1106 { } 1107 }; 1108 1109 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1110 .cmd_rcgr = 0xf020, 1111 .mnd_width = 8, 1112 .hid_width = 5, 1113 .parent_map = gcc_parent_map_1, 1114 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1115 .clkr.hw.init = &(struct clk_init_data){ 1116 .name = "gcc_usb30_prim_master_clk_src", 1117 .parent_data = gcc_parent_data_1, 1118 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1119 .ops = &clk_rcg2_ops, 1120 }, 1121 }; 1122 1123 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 1124 F(19200000, P_BI_TCXO, 1, 0, 0), 1125 { } 1126 }; 1127 1128 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1129 .cmd_rcgr = 0xf038, 1130 .mnd_width = 0, 1131 .hid_width = 5, 1132 .parent_map = gcc_parent_map_3, 1133 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1134 .clkr.hw.init = &(struct clk_init_data){ 1135 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1136 .parent_data = gcc_parent_data_3, 1137 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1138 .ops = &clk_rcg2_ops, 1139 }, 1140 }; 1141 1142 static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk_src[] = { 1143 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0), 1144 F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0), 1145 { } 1146 }; 1147 1148 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { 1149 .cmd_rcgr = 0x9e020, 1150 .mnd_width = 8, 1151 .hid_width = 5, 1152 .parent_map = gcc_parent_map_5, 1153 .freq_tbl = ftbl_gcc_usb30_sec_master_clk_src, 1154 .clkr.hw.init = &(struct clk_init_data){ 1155 .name = "gcc_usb30_sec_master_clk_src", 1156 .parent_data = gcc_parent_data_5, 1157 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1158 .ops = &clk_rcg2_ops, 1159 }, 1160 }; 1161 1162 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { 1163 .cmd_rcgr = 0x9e038, 1164 .mnd_width = 0, 1165 .hid_width = 5, 1166 .parent_map = gcc_parent_map_3, 1167 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1168 .clkr.hw.init = &(struct clk_init_data){ 1169 .name = "gcc_usb30_sec_mock_utmi_clk_src", 1170 .parent_data = gcc_parent_data_3, 1171 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1172 .ops = &clk_rcg2_ops, 1173 }, 1174 }; 1175 1176 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1177 .cmd_rcgr = 0xf064, 1178 .mnd_width = 0, 1179 .hid_width = 5, 1180 .parent_map = gcc_parent_map_2, 1181 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1182 .clkr.hw.init = &(struct clk_init_data){ 1183 .name = "gcc_usb3_prim_phy_aux_clk_src", 1184 .parent_data = gcc_parent_data_2, 1185 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1186 .ops = &clk_rcg2_ops, 1187 }, 1188 }; 1189 1190 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { 1191 .cmd_rcgr = 0x9e064, 1192 .mnd_width = 0, 1193 .hid_width = 5, 1194 .parent_map = gcc_parent_map_2, 1195 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1196 .clkr.hw.init = &(struct clk_init_data){ 1197 .name = "gcc_usb3_sec_phy_aux_clk_src", 1198 .parent_data = gcc_parent_data_2, 1199 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1200 .ops = &clk_rcg2_ops, 1201 }, 1202 }; 1203 1204 static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = { 1205 F(4800000, P_BI_TCXO, 4, 0, 0), 1206 F(19200000, P_BI_TCXO, 1, 0, 0), 1207 { } 1208 }; 1209 1210 static struct clk_rcg2 gcc_sec_ctrl_clk_src = { 1211 .cmd_rcgr = 0x3d02c, 1212 .mnd_width = 0, 1213 .hid_width = 5, 1214 .parent_map = gcc_parent_map_3, 1215 .freq_tbl = ftbl_gcc_sec_ctrl_clk_src, 1216 .clkr.hw.init = &(struct clk_init_data){ 1217 .name = "gcc_sec_ctrl_clk_src", 1218 .parent_data = gcc_parent_data_3, 1219 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1220 .ops = &clk_rcg2_ops, 1221 }, 1222 }; 1223 1224 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1225 .reg = 0xf050, 1226 .shift = 0, 1227 .width = 4, 1228 .clkr.hw.init = &(struct clk_init_data) { 1229 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1230 .parent_hws = (const struct clk_hw*[]){ 1231 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1232 }, 1233 .num_parents = 1, 1234 .flags = CLK_SET_RATE_PARENT, 1235 .ops = &clk_regmap_div_ro_ops, 1236 }, 1237 }; 1238 1239 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = { 1240 .reg = 0x9e050, 1241 .shift = 0, 1242 .width = 4, 1243 .clkr.hw.init = &(struct clk_init_data) { 1244 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src", 1245 .parent_hws = (const struct clk_hw*[]){ 1246 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, 1247 }, 1248 .num_parents = 1, 1249 .flags = CLK_SET_RATE_PARENT, 1250 .ops = &clk_regmap_div_ro_ops, 1251 }, 1252 }; 1253 1254 static struct clk_branch gcc_pcie_clkref_en = { 1255 .halt_reg = 0x8c004, 1256 .halt_check = BRANCH_HALT, 1257 .clkr = { 1258 .enable_reg = 0x8c004, 1259 .enable_mask = BIT(0), 1260 .hw.init = &(struct clk_init_data){ 1261 .name = "gcc_pcie_clkref_en", 1262 .ops = &clk_branch2_ops, 1263 }, 1264 }, 1265 }; 1266 1267 static struct clk_branch gcc_edp_clkref_en = { 1268 .halt_reg = 0x8c008, 1269 .halt_check = BRANCH_HALT, 1270 .clkr = { 1271 .enable_reg = 0x8c008, 1272 .enable_mask = BIT(0), 1273 .hw.init = &(struct clk_init_data){ 1274 .name = "gcc_edp_clkref_en", 1275 .ops = &clk_branch2_ops, 1276 }, 1277 }, 1278 }; 1279 1280 static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = { 1281 .halt_reg = 0x6b080, 1282 .halt_check = BRANCH_HALT_SKIP, 1283 .hwcg_reg = 0x6b080, 1284 .hwcg_bit = 1, 1285 .clkr = { 1286 .enable_reg = 0x52000, 1287 .enable_mask = BIT(12), 1288 .hw.init = &(struct clk_init_data){ 1289 .name = "gcc_aggre_noc_pcie_0_axi_clk", 1290 .ops = &clk_branch2_ops, 1291 }, 1292 }, 1293 }; 1294 1295 static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = { 1296 .halt_reg = 0x8d084, 1297 .halt_check = BRANCH_HALT_SKIP, 1298 .hwcg_reg = 0x8d084, 1299 .hwcg_bit = 1, 1300 .clkr = { 1301 .enable_reg = 0x52000, 1302 .enable_mask = BIT(11), 1303 .hw.init = &(struct clk_init_data){ 1304 .name = "gcc_aggre_noc_pcie_1_axi_clk", 1305 .ops = &clk_branch2_ops, 1306 }, 1307 }, 1308 }; 1309 1310 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { 1311 .halt_reg = 0x90010, 1312 .halt_check = BRANCH_HALT_VOTED, 1313 .hwcg_reg = 0x90010, 1314 .hwcg_bit = 1, 1315 .clkr = { 1316 .enable_reg = 0x52000, 1317 .enable_mask = BIT(18), 1318 .hw.init = &(struct clk_init_data){ 1319 .name = "gcc_aggre_noc_pcie_tbu_clk", 1320 .ops = &clk_branch2_ops, 1321 }, 1322 }, 1323 }; 1324 1325 static struct clk_branch gcc_aggre_noc_pcie_center_sf_axi_clk = { 1326 .halt_reg = 0x8d088, 1327 .halt_check = BRANCH_HALT_VOTED, 1328 .hwcg_reg = 0x8d088, 1329 .hwcg_bit = 1, 1330 .clkr = { 1331 .enable_reg = 0x52008, 1332 .enable_mask = BIT(28), 1333 .hw.init = &(struct clk_init_data){ 1334 .name = "gcc_aggre_noc_pcie_center_sf_axi_clk", 1335 .ops = &clk_branch2_ops, 1336 }, 1337 }, 1338 }; 1339 1340 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1341 .halt_reg = 0x770cc, 1342 .halt_check = BRANCH_HALT_VOTED, 1343 .hwcg_reg = 0x770cc, 1344 .hwcg_bit = 1, 1345 .clkr = { 1346 .enable_reg = 0x770cc, 1347 .enable_mask = BIT(0), 1348 .hw.init = &(struct clk_init_data){ 1349 .name = "gcc_aggre_ufs_phy_axi_clk", 1350 .parent_hws = (const struct clk_hw*[]){ 1351 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1352 }, 1353 .num_parents = 1, 1354 .flags = CLK_SET_RATE_PARENT, 1355 .ops = &clk_branch2_ops, 1356 }, 1357 }, 1358 }; 1359 1360 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1361 .halt_reg = 0xf080, 1362 .halt_check = BRANCH_HALT_VOTED, 1363 .hwcg_reg = 0xf080, 1364 .hwcg_bit = 1, 1365 .clkr = { 1366 .enable_reg = 0xf080, 1367 .enable_mask = BIT(0), 1368 .hw.init = &(struct clk_init_data){ 1369 .name = "gcc_aggre_usb3_prim_axi_clk", 1370 .parent_hws = (const struct clk_hw*[]){ 1371 &gcc_usb30_prim_master_clk_src.clkr.hw, 1372 }, 1373 .num_parents = 1, 1374 .flags = CLK_SET_RATE_PARENT, 1375 .ops = &clk_branch2_ops, 1376 }, 1377 }, 1378 }; 1379 1380 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { 1381 .halt_reg = 0x9e080, 1382 .halt_check = BRANCH_HALT_VOTED, 1383 .hwcg_reg = 0x9e080, 1384 .hwcg_bit = 1, 1385 .clkr = { 1386 .enable_reg = 0x9e080, 1387 .enable_mask = BIT(0), 1388 .hw.init = &(struct clk_init_data){ 1389 .name = "gcc_aggre_usb3_sec_axi_clk", 1390 .parent_hws = (const struct clk_hw*[]){ 1391 &gcc_usb30_sec_master_clk_src.clkr.hw, 1392 }, 1393 .num_parents = 1, 1394 .flags = CLK_SET_RATE_PARENT, 1395 .ops = &clk_branch2_ops, 1396 }, 1397 }, 1398 }; 1399 1400 static struct clk_branch gcc_camera_hf_axi_clk = { 1401 .halt_reg = 0x26010, 1402 .halt_check = BRANCH_HALT_SKIP, 1403 .hwcg_reg = 0x26010, 1404 .hwcg_bit = 1, 1405 .clkr = { 1406 .enable_reg = 0x26010, 1407 .enable_mask = BIT(0), 1408 .hw.init = &(struct clk_init_data){ 1409 .name = "gcc_camera_hf_axi_clk", 1410 .ops = &clk_branch2_ops, 1411 }, 1412 }, 1413 }; 1414 1415 static struct clk_branch gcc_camera_sf_axi_clk = { 1416 .halt_reg = 0x2601c, 1417 .halt_check = BRANCH_HALT_SKIP, 1418 .hwcg_reg = 0x2601c, 1419 .hwcg_bit = 1, 1420 .clkr = { 1421 .enable_reg = 0x2601c, 1422 .enable_mask = BIT(0), 1423 .hw.init = &(struct clk_init_data){ 1424 .name = "gcc_camera_sf_axi_clk", 1425 .ops = &clk_branch2_ops, 1426 }, 1427 }, 1428 }; 1429 1430 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1431 .halt_reg = 0xf07c, 1432 .halt_check = BRANCH_HALT_VOTED, 1433 .hwcg_reg = 0xf07c, 1434 .hwcg_bit = 1, 1435 .clkr = { 1436 .enable_reg = 0xf07c, 1437 .enable_mask = BIT(0), 1438 .hw.init = &(struct clk_init_data){ 1439 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1440 .parent_hws = (const struct clk_hw*[]){ 1441 &gcc_usb30_prim_master_clk_src.clkr.hw, 1442 }, 1443 .num_parents = 1, 1444 .flags = CLK_SET_RATE_PARENT, 1445 .ops = &clk_branch2_ops, 1446 }, 1447 }, 1448 }; 1449 1450 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { 1451 .halt_reg = 0x9e07c, 1452 .halt_check = BRANCH_HALT_VOTED, 1453 .hwcg_reg = 0x9e07c, 1454 .hwcg_bit = 1, 1455 .clkr = { 1456 .enable_reg = 0x9e07c, 1457 .enable_mask = BIT(0), 1458 .hw.init = &(struct clk_init_data){ 1459 .name = "gcc_cfg_noc_usb3_sec_axi_clk", 1460 .parent_hws = (const struct clk_hw*[]){ 1461 &gcc_usb30_sec_master_clk_src.clkr.hw, 1462 }, 1463 .num_parents = 1, 1464 .flags = CLK_SET_RATE_PARENT, 1465 .ops = &clk_branch2_ops, 1466 }, 1467 }, 1468 }; 1469 1470 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1471 .halt_reg = 0x71154, 1472 .halt_check = BRANCH_HALT_SKIP, 1473 .hwcg_reg = 0x71154, 1474 .hwcg_bit = 1, 1475 .clkr = { 1476 .enable_reg = 0x71154, 1477 .enable_mask = BIT(0), 1478 .hw.init = &(struct clk_init_data){ 1479 .name = "gcc_ddrss_gpu_axi_clk", 1480 .ops = &clk_branch2_aon_ops, 1481 }, 1482 }, 1483 }; 1484 1485 static struct clk_branch gcc_ddrss_pcie_sf_clk = { 1486 .halt_reg = 0x8d080, 1487 .halt_check = BRANCH_HALT_SKIP, 1488 .hwcg_reg = 0x8d080, 1489 .hwcg_bit = 1, 1490 .clkr = { 1491 .enable_reg = 0x52000, 1492 .enable_mask = BIT(19), 1493 .hw.init = &(struct clk_init_data){ 1494 .name = "gcc_ddrss_pcie_sf_clk", 1495 .ops = &clk_branch2_ops, 1496 }, 1497 }, 1498 }; 1499 1500 static struct clk_branch gcc_disp_gpll0_clk_src = { 1501 .halt_check = BRANCH_HALT_DELAY, 1502 .clkr = { 1503 .enable_reg = 0x52000, 1504 .enable_mask = BIT(7), 1505 .hw.init = &(struct clk_init_data){ 1506 .name = "gcc_disp_gpll0_clk_src", 1507 .parent_hws = (const struct clk_hw*[]){ 1508 &gcc_gpll0.clkr.hw, 1509 }, 1510 .num_parents = 1, 1511 .flags = CLK_SET_RATE_PARENT, 1512 .ops = &clk_branch2_ops, 1513 }, 1514 }, 1515 }; 1516 1517 static struct clk_branch gcc_disp_hf_axi_clk = { 1518 .halt_reg = 0x2700c, 1519 .halt_check = BRANCH_HALT_SKIP, 1520 .hwcg_reg = 0x2700c, 1521 .hwcg_bit = 1, 1522 .clkr = { 1523 .enable_reg = 0x2700c, 1524 .enable_mask = BIT(0), 1525 .hw.init = &(struct clk_init_data){ 1526 .name = "gcc_disp_hf_axi_clk", 1527 .ops = &clk_branch2_ops, 1528 }, 1529 }, 1530 }; 1531 1532 static struct clk_branch gcc_disp_sf_axi_clk = { 1533 .halt_reg = 0x27014, 1534 .halt_check = BRANCH_HALT_SKIP, 1535 .hwcg_reg = 0x27014, 1536 .hwcg_bit = 1, 1537 .clkr = { 1538 .enable_reg = 0x27014, 1539 .enable_mask = BIT(0), 1540 .hw.init = &(struct clk_init_data){ 1541 .name = "gcc_disp_sf_axi_clk", 1542 .ops = &clk_branch2_ops, 1543 }, 1544 }, 1545 }; 1546 1547 static struct clk_branch gcc_gp1_clk = { 1548 .halt_reg = 0x64000, 1549 .halt_check = BRANCH_HALT, 1550 .clkr = { 1551 .enable_reg = 0x64000, 1552 .enable_mask = BIT(0), 1553 .hw.init = &(struct clk_init_data){ 1554 .name = "gcc_gp1_clk", 1555 .parent_hws = (const struct clk_hw*[]){ 1556 &gcc_gp1_clk_src.clkr.hw, 1557 }, 1558 .num_parents = 1, 1559 .flags = CLK_SET_RATE_PARENT, 1560 .ops = &clk_branch2_ops, 1561 }, 1562 }, 1563 }; 1564 1565 static struct clk_branch gcc_gp2_clk = { 1566 .halt_reg = 0x65000, 1567 .halt_check = BRANCH_HALT, 1568 .clkr = { 1569 .enable_reg = 0x65000, 1570 .enable_mask = BIT(0), 1571 .hw.init = &(struct clk_init_data){ 1572 .name = "gcc_gp2_clk", 1573 .parent_hws = (const struct clk_hw*[]){ 1574 &gcc_gp2_clk_src.clkr.hw, 1575 }, 1576 .num_parents = 1, 1577 .flags = CLK_SET_RATE_PARENT, 1578 .ops = &clk_branch2_ops, 1579 }, 1580 }, 1581 }; 1582 1583 static struct clk_branch gcc_gp3_clk = { 1584 .halt_reg = 0x66000, 1585 .halt_check = BRANCH_HALT, 1586 .clkr = { 1587 .enable_reg = 0x66000, 1588 .enable_mask = BIT(0), 1589 .hw.init = &(struct clk_init_data){ 1590 .name = "gcc_gp3_clk", 1591 .parent_hws = (const struct clk_hw*[]){ 1592 &gcc_gp3_clk_src.clkr.hw, 1593 }, 1594 .num_parents = 1, 1595 .flags = CLK_SET_RATE_PARENT, 1596 .ops = &clk_branch2_ops, 1597 }, 1598 }, 1599 }; 1600 1601 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1602 .halt_check = BRANCH_HALT_DELAY, 1603 .clkr = { 1604 .enable_reg = 0x52000, 1605 .enable_mask = BIT(15), 1606 .hw.init = &(struct clk_init_data){ 1607 .name = "gcc_gpu_gpll0_clk_src", 1608 .parent_hws = (const struct clk_hw*[]){ 1609 &gcc_gpll0.clkr.hw, 1610 }, 1611 .num_parents = 1, 1612 .flags = CLK_SET_RATE_PARENT, 1613 .ops = &clk_branch2_ops, 1614 }, 1615 }, 1616 }; 1617 1618 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1619 .halt_check = BRANCH_HALT_DELAY, 1620 .clkr = { 1621 .enable_reg = 0x52000, 1622 .enable_mask = BIT(16), 1623 .hw.init = &(struct clk_init_data){ 1624 .name = "gcc_gpu_gpll0_div_clk_src", 1625 .parent_hws = (const struct clk_hw*[]){ 1626 &gcc_gpll0_out_even.clkr.hw, 1627 }, 1628 .num_parents = 1, 1629 .flags = CLK_SET_RATE_PARENT, 1630 .ops = &clk_branch2_ops, 1631 }, 1632 }, 1633 }; 1634 1635 static struct clk_branch gcc_gpu_iref_en = { 1636 .halt_reg = 0x8c014, 1637 .halt_check = BRANCH_HALT, 1638 .clkr = { 1639 .enable_reg = 0x8c014, 1640 .enable_mask = BIT(0), 1641 .hw.init = &(struct clk_init_data){ 1642 .name = "gcc_gpu_iref_en", 1643 .ops = &clk_branch2_ops, 1644 }, 1645 }, 1646 }; 1647 1648 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1649 .halt_reg = 0x7100c, 1650 .halt_check = BRANCH_HALT_VOTED, 1651 .hwcg_reg = 0x7100c, 1652 .hwcg_bit = 1, 1653 .clkr = { 1654 .enable_reg = 0x7100c, 1655 .enable_mask = BIT(0), 1656 .hw.init = &(struct clk_init_data){ 1657 .name = "gcc_gpu_memnoc_gfx_clk", 1658 .ops = &clk_branch2_aon_ops, 1659 }, 1660 }, 1661 }; 1662 1663 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1664 .halt_reg = 0x71018, 1665 .halt_check = BRANCH_HALT, 1666 .clkr = { 1667 .enable_reg = 0x71018, 1668 .enable_mask = BIT(0), 1669 .hw.init = &(struct clk_init_data){ 1670 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1671 .ops = &clk_branch2_aon_ops, 1672 }, 1673 }, 1674 }; 1675 1676 static struct clk_branch gcc_pcie0_phy_rchng_clk = { 1677 .halt_reg = 0x6b038, 1678 .halt_check = BRANCH_HALT_VOTED, 1679 .clkr = { 1680 .enable_reg = 0x52000, 1681 .enable_mask = BIT(22), 1682 .hw.init = &(struct clk_init_data){ 1683 .name = "gcc_pcie0_phy_rchng_clk", 1684 .parent_hws = (const struct clk_hw*[]){ 1685 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1686 }, 1687 .num_parents = 1, 1688 .flags = CLK_SET_RATE_PARENT, 1689 .ops = &clk_branch2_ops, 1690 }, 1691 }, 1692 }; 1693 1694 static struct clk_branch gcc_pcie1_phy_rchng_clk = { 1695 .halt_reg = 0x8d038, 1696 .halt_check = BRANCH_HALT_VOTED, 1697 .clkr = { 1698 .enable_reg = 0x52000, 1699 .enable_mask = BIT(23), 1700 .hw.init = &(struct clk_init_data){ 1701 .name = "gcc_pcie1_phy_rchng_clk", 1702 .parent_hws = (const struct clk_hw*[]){ 1703 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 1704 }, 1705 .num_parents = 1, 1706 .flags = CLK_SET_RATE_PARENT, 1707 .ops = &clk_branch2_ops, 1708 }, 1709 }, 1710 }; 1711 1712 static struct clk_branch gcc_pcie_0_aux_clk = { 1713 .halt_reg = 0x6b028, 1714 .halt_check = BRANCH_HALT_VOTED, 1715 .clkr = { 1716 .enable_reg = 0x52008, 1717 .enable_mask = BIT(3), 1718 .hw.init = &(struct clk_init_data){ 1719 .name = "gcc_pcie_0_aux_clk", 1720 .parent_hws = (const struct clk_hw*[]){ 1721 &gcc_pcie_0_aux_clk_src.clkr.hw, 1722 }, 1723 .num_parents = 1, 1724 .flags = CLK_SET_RATE_PARENT, 1725 .ops = &clk_branch2_ops, 1726 }, 1727 }, 1728 }; 1729 1730 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1731 .halt_reg = 0x6b024, 1732 .halt_check = BRANCH_HALT_VOTED, 1733 .hwcg_reg = 0x6b024, 1734 .hwcg_bit = 1, 1735 .clkr = { 1736 .enable_reg = 0x52008, 1737 .enable_mask = BIT(2), 1738 .hw.init = &(struct clk_init_data){ 1739 .name = "gcc_pcie_0_cfg_ahb_clk", 1740 .ops = &clk_branch2_ops, 1741 }, 1742 }, 1743 }; 1744 1745 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1746 .halt_reg = 0x6b01c, 1747 .halt_check = BRANCH_HALT_SKIP, 1748 .clkr = { 1749 .enable_reg = 0x52008, 1750 .enable_mask = BIT(1), 1751 .hw.init = &(struct clk_init_data){ 1752 .name = "gcc_pcie_0_mstr_axi_clk", 1753 .ops = &clk_branch2_ops, 1754 }, 1755 }, 1756 }; 1757 1758 static struct clk_branch gcc_pcie_0_pipe_clk = { 1759 .halt_reg = 0x6b030, 1760 .halt_check = BRANCH_HALT_SKIP, 1761 .clkr = { 1762 .enable_reg = 0x52008, 1763 .enable_mask = BIT(4), 1764 .hw.init = &(struct clk_init_data){ 1765 .name = "gcc_pcie_0_pipe_clk", 1766 .parent_hws = (const struct clk_hw*[]){ 1767 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1768 }, 1769 .num_parents = 1, 1770 .flags = CLK_SET_RATE_PARENT, 1771 .ops = &clk_branch2_ops, 1772 }, 1773 }, 1774 }; 1775 1776 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1777 .halt_reg = 0x6b014, 1778 .halt_check = BRANCH_HALT_VOTED, 1779 .clkr = { 1780 .enable_reg = 0x52008, 1781 .enable_mask = BIT(0), 1782 .hw.init = &(struct clk_init_data){ 1783 .name = "gcc_pcie_0_slv_axi_clk", 1784 .ops = &clk_branch2_ops, 1785 }, 1786 }, 1787 }; 1788 1789 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1790 .halt_reg = 0x6b010, 1791 .halt_check = BRANCH_HALT_VOTED, 1792 .clkr = { 1793 .enable_reg = 0x52008, 1794 .enable_mask = BIT(5), 1795 .hw.init = &(struct clk_init_data){ 1796 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1797 .ops = &clk_branch2_ops, 1798 }, 1799 }, 1800 }; 1801 1802 static struct clk_branch gcc_pcie_1_aux_clk = { 1803 .halt_reg = 0x8d028, 1804 .halt_check = BRANCH_HALT_VOTED, 1805 .clkr = { 1806 .enable_reg = 0x52000, 1807 .enable_mask = BIT(29), 1808 .hw.init = &(struct clk_init_data){ 1809 .name = "gcc_pcie_1_aux_clk", 1810 .parent_hws = (const struct clk_hw*[]){ 1811 &gcc_pcie_1_aux_clk_src.clkr.hw, 1812 }, 1813 .num_parents = 1, 1814 .flags = CLK_SET_RATE_PARENT, 1815 .ops = &clk_branch2_ops, 1816 }, 1817 }, 1818 }; 1819 1820 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1821 .halt_reg = 0x8d024, 1822 .halt_check = BRANCH_HALT_VOTED, 1823 .hwcg_reg = 0x8d024, 1824 .hwcg_bit = 1, 1825 .clkr = { 1826 .enable_reg = 0x52000, 1827 .enable_mask = BIT(28), 1828 .hw.init = &(struct clk_init_data){ 1829 .name = "gcc_pcie_1_cfg_ahb_clk", 1830 .ops = &clk_branch2_ops, 1831 }, 1832 }, 1833 }; 1834 1835 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1836 .halt_reg = 0x8d01c, 1837 .halt_check = BRANCH_HALT_SKIP, 1838 .clkr = { 1839 .enable_reg = 0x52000, 1840 .enable_mask = BIT(27), 1841 .hw.init = &(struct clk_init_data){ 1842 .name = "gcc_pcie_1_mstr_axi_clk", 1843 .ops = &clk_branch2_ops, 1844 }, 1845 }, 1846 }; 1847 1848 static struct clk_branch gcc_pcie_1_pipe_clk = { 1849 .halt_reg = 0x8d030, 1850 .halt_check = BRANCH_HALT_SKIP, 1851 .clkr = { 1852 .enable_reg = 0x52000, 1853 .enable_mask = BIT(30), 1854 .hw.init = &(struct clk_init_data){ 1855 .name = "gcc_pcie_1_pipe_clk", 1856 .parent_hws = (const struct clk_hw*[]){ 1857 &gcc_pcie_1_pipe_clk_src.clkr.hw, 1858 }, 1859 .num_parents = 1, 1860 .flags = CLK_SET_RATE_PARENT, 1861 .ops = &clk_branch2_ops, 1862 }, 1863 }, 1864 }; 1865 1866 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1867 .halt_reg = 0x8d014, 1868 .halt_check = BRANCH_HALT_VOTED, 1869 .clkr = { 1870 .enable_reg = 0x52000, 1871 .enable_mask = BIT(26), 1872 .hw.init = &(struct clk_init_data){ 1873 .name = "gcc_pcie_1_slv_axi_clk", 1874 .ops = &clk_branch2_ops, 1875 }, 1876 }, 1877 }; 1878 1879 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 1880 .halt_reg = 0x8d010, 1881 .halt_check = BRANCH_HALT_VOTED, 1882 .clkr = { 1883 .enable_reg = 0x52000, 1884 .enable_mask = BIT(25), 1885 .hw.init = &(struct clk_init_data){ 1886 .name = "gcc_pcie_1_slv_q2a_axi_clk", 1887 .ops = &clk_branch2_ops, 1888 }, 1889 }, 1890 }; 1891 1892 static struct clk_branch gcc_pcie_throttle_core_clk = { 1893 .halt_reg = 0x90018, 1894 .halt_check = BRANCH_HALT_SKIP, 1895 .hwcg_reg = 0x90018, 1896 .hwcg_bit = 1, 1897 .clkr = { 1898 .enable_reg = 0x52000, 1899 .enable_mask = BIT(20), 1900 .hw.init = &(struct clk_init_data){ 1901 .name = "gcc_pcie_throttle_core_clk", 1902 .ops = &clk_branch2_ops, 1903 }, 1904 }, 1905 }; 1906 1907 static struct clk_branch gcc_pdm2_clk = { 1908 .halt_reg = 0x3300c, 1909 .halt_check = BRANCH_HALT, 1910 .clkr = { 1911 .enable_reg = 0x3300c, 1912 .enable_mask = BIT(0), 1913 .hw.init = &(struct clk_init_data){ 1914 .name = "gcc_pdm2_clk", 1915 .parent_hws = (const struct clk_hw*[]){ 1916 &gcc_pdm2_clk_src.clkr.hw, 1917 }, 1918 .num_parents = 1, 1919 .flags = CLK_SET_RATE_PARENT, 1920 .ops = &clk_branch2_ops, 1921 }, 1922 }, 1923 }; 1924 1925 static struct clk_branch gcc_pdm_ahb_clk = { 1926 .halt_reg = 0x33004, 1927 .halt_check = BRANCH_HALT_VOTED, 1928 .hwcg_reg = 0x33004, 1929 .hwcg_bit = 1, 1930 .clkr = { 1931 .enable_reg = 0x33004, 1932 .enable_mask = BIT(0), 1933 .hw.init = &(struct clk_init_data){ 1934 .name = "gcc_pdm_ahb_clk", 1935 .ops = &clk_branch2_ops, 1936 }, 1937 }, 1938 }; 1939 1940 static struct clk_branch gcc_pdm_xo4_clk = { 1941 .halt_reg = 0x33008, 1942 .halt_check = BRANCH_HALT, 1943 .clkr = { 1944 .enable_reg = 0x33008, 1945 .enable_mask = BIT(0), 1946 .hw.init = &(struct clk_init_data){ 1947 .name = "gcc_pdm_xo4_clk", 1948 .ops = &clk_branch2_ops, 1949 }, 1950 }, 1951 }; 1952 1953 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 1954 .halt_reg = 0x26008, 1955 .halt_check = BRANCH_HALT_VOTED, 1956 .hwcg_reg = 0x26008, 1957 .hwcg_bit = 1, 1958 .clkr = { 1959 .enable_reg = 0x26008, 1960 .enable_mask = BIT(0), 1961 .hw.init = &(struct clk_init_data){ 1962 .name = "gcc_qmip_camera_nrt_ahb_clk", 1963 .ops = &clk_branch2_ops, 1964 }, 1965 }, 1966 }; 1967 1968 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 1969 .halt_reg = 0x2600c, 1970 .halt_check = BRANCH_HALT_VOTED, 1971 .hwcg_reg = 0x2600c, 1972 .hwcg_bit = 1, 1973 .clkr = { 1974 .enable_reg = 0x2600c, 1975 .enable_mask = BIT(0), 1976 .hw.init = &(struct clk_init_data){ 1977 .name = "gcc_qmip_camera_rt_ahb_clk", 1978 .ops = &clk_branch2_ops, 1979 }, 1980 }, 1981 }; 1982 1983 static struct clk_branch gcc_qmip_disp_ahb_clk = { 1984 .halt_reg = 0x27008, 1985 .halt_check = BRANCH_HALT_VOTED, 1986 .clkr = { 1987 .enable_reg = 0x27008, 1988 .enable_mask = BIT(0), 1989 .hw.init = &(struct clk_init_data){ 1990 .name = "gcc_qmip_disp_ahb_clk", 1991 .ops = &clk_branch2_ops, 1992 }, 1993 }, 1994 }; 1995 1996 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 1997 .halt_reg = 0x28008, 1998 .halt_check = BRANCH_HALT_VOTED, 1999 .hwcg_reg = 0x28008, 2000 .hwcg_bit = 1, 2001 .clkr = { 2002 .enable_reg = 0x28008, 2003 .enable_mask = BIT(0), 2004 .hw.init = &(struct clk_init_data){ 2005 .name = "gcc_qmip_video_vcodec_ahb_clk", 2006 .ops = &clk_branch2_ops, 2007 }, 2008 }, 2009 }; 2010 2011 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { 2012 .halt_reg = 0x4b004, 2013 .halt_check = BRANCH_HALT, 2014 .hwcg_reg = 0x4b004, 2015 .hwcg_bit = 1, 2016 .clkr = { 2017 .enable_reg = 0x4b004, 2018 .enable_mask = BIT(0), 2019 .hw.init = &(struct clk_init_data){ 2020 .name = "gcc_qspi_cnoc_periph_ahb_clk", 2021 .ops = &clk_branch2_ops, 2022 }, 2023 }, 2024 }; 2025 2026 static struct clk_branch gcc_qspi_core_clk = { 2027 .halt_reg = 0x4b008, 2028 .halt_check = BRANCH_HALT, 2029 .clkr = { 2030 .enable_reg = 0x4b008, 2031 .enable_mask = BIT(0), 2032 .hw.init = &(struct clk_init_data){ 2033 .name = "gcc_qspi_core_clk", 2034 .parent_hws = (const struct clk_hw*[]){ 2035 &gcc_qspi_core_clk_src.clkr.hw, 2036 }, 2037 .num_parents = 1, 2038 .flags = CLK_SET_RATE_PARENT, 2039 .ops = &clk_branch2_ops, 2040 }, 2041 }, 2042 }; 2043 2044 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2045 .halt_reg = 0x23008, 2046 .halt_check = BRANCH_HALT_VOTED, 2047 .clkr = { 2048 .enable_reg = 0x52008, 2049 .enable_mask = BIT(9), 2050 .hw.init = &(struct clk_init_data){ 2051 .name = "gcc_qupv3_wrap0_core_2x_clk", 2052 .ops = &clk_branch2_ops, 2053 }, 2054 }, 2055 }; 2056 2057 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2058 .halt_reg = 0x23000, 2059 .halt_check = BRANCH_HALT_VOTED, 2060 .clkr = { 2061 .enable_reg = 0x52008, 2062 .enable_mask = BIT(8), 2063 .hw.init = &(struct clk_init_data){ 2064 .name = "gcc_qupv3_wrap0_core_clk", 2065 .ops = &clk_branch2_ops, 2066 }, 2067 }, 2068 }; 2069 2070 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2071 .halt_reg = 0x1700c, 2072 .halt_check = BRANCH_HALT_VOTED, 2073 .clkr = { 2074 .enable_reg = 0x52008, 2075 .enable_mask = BIT(10), 2076 .hw.init = &(struct clk_init_data){ 2077 .name = "gcc_qupv3_wrap0_s0_clk", 2078 .parent_hws = (const struct clk_hw*[]){ 2079 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 2080 }, 2081 .num_parents = 1, 2082 .flags = CLK_SET_RATE_PARENT, 2083 .ops = &clk_branch2_ops, 2084 }, 2085 }, 2086 }; 2087 2088 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2089 .halt_reg = 0x1713c, 2090 .halt_check = BRANCH_HALT_VOTED, 2091 .clkr = { 2092 .enable_reg = 0x52008, 2093 .enable_mask = BIT(11), 2094 .hw.init = &(struct clk_init_data){ 2095 .name = "gcc_qupv3_wrap0_s1_clk", 2096 .parent_hws = (const struct clk_hw*[]){ 2097 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 2098 }, 2099 .num_parents = 1, 2100 .flags = CLK_SET_RATE_PARENT, 2101 .ops = &clk_branch2_ops, 2102 }, 2103 }, 2104 }; 2105 2106 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2107 .halt_reg = 0x1726c, 2108 .halt_check = BRANCH_HALT_VOTED, 2109 .clkr = { 2110 .enable_reg = 0x52008, 2111 .enable_mask = BIT(12), 2112 .hw.init = &(struct clk_init_data){ 2113 .name = "gcc_qupv3_wrap0_s2_clk", 2114 .parent_hws = (const struct clk_hw*[]){ 2115 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2116 }, 2117 .num_parents = 1, 2118 .flags = CLK_SET_RATE_PARENT, 2119 .ops = &clk_branch2_ops, 2120 }, 2121 }, 2122 }; 2123 2124 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2125 .halt_reg = 0x1739c, 2126 .halt_check = BRANCH_HALT_VOTED, 2127 .clkr = { 2128 .enable_reg = 0x52008, 2129 .enable_mask = BIT(13), 2130 .hw.init = &(struct clk_init_data){ 2131 .name = "gcc_qupv3_wrap0_s3_clk", 2132 .parent_hws = (const struct clk_hw*[]){ 2133 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2134 }, 2135 .num_parents = 1, 2136 .flags = CLK_SET_RATE_PARENT, 2137 .ops = &clk_branch2_ops, 2138 }, 2139 }, 2140 }; 2141 2142 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2143 .halt_reg = 0x174cc, 2144 .halt_check = BRANCH_HALT_VOTED, 2145 .clkr = { 2146 .enable_reg = 0x52008, 2147 .enable_mask = BIT(14), 2148 .hw.init = &(struct clk_init_data){ 2149 .name = "gcc_qupv3_wrap0_s4_clk", 2150 .parent_hws = (const struct clk_hw*[]){ 2151 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2152 }, 2153 .num_parents = 1, 2154 .flags = CLK_SET_RATE_PARENT, 2155 .ops = &clk_branch2_ops, 2156 }, 2157 }, 2158 }; 2159 2160 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2161 .halt_reg = 0x175fc, 2162 .halt_check = BRANCH_HALT_VOTED, 2163 .clkr = { 2164 .enable_reg = 0x52008, 2165 .enable_mask = BIT(15), 2166 .hw.init = &(struct clk_init_data){ 2167 .name = "gcc_qupv3_wrap0_s5_clk", 2168 .parent_hws = (const struct clk_hw*[]){ 2169 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2170 }, 2171 .num_parents = 1, 2172 .flags = CLK_SET_RATE_PARENT, 2173 .ops = &clk_branch2_ops, 2174 }, 2175 }, 2176 }; 2177 2178 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 2179 .halt_reg = 0x1772c, 2180 .halt_check = BRANCH_HALT_VOTED, 2181 .clkr = { 2182 .enable_reg = 0x52008, 2183 .enable_mask = BIT(16), 2184 .hw.init = &(struct clk_init_data){ 2185 .name = "gcc_qupv3_wrap0_s6_clk", 2186 .parent_hws = (const struct clk_hw*[]){ 2187 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 2188 }, 2189 .num_parents = 1, 2190 .flags = CLK_SET_RATE_PARENT, 2191 .ops = &clk_branch2_ops, 2192 }, 2193 }, 2194 }; 2195 2196 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 2197 .halt_reg = 0x1785c, 2198 .halt_check = BRANCH_HALT_VOTED, 2199 .clkr = { 2200 .enable_reg = 0x52008, 2201 .enable_mask = BIT(17), 2202 .hw.init = &(struct clk_init_data){ 2203 .name = "gcc_qupv3_wrap0_s7_clk", 2204 .parent_hws = (const struct clk_hw*[]){ 2205 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 2206 }, 2207 .num_parents = 1, 2208 .flags = CLK_SET_RATE_PARENT, 2209 .ops = &clk_branch2_ops, 2210 }, 2211 }, 2212 }; 2213 2214 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2215 .halt_reg = 0x23140, 2216 .halt_check = BRANCH_HALT_VOTED, 2217 .clkr = { 2218 .enable_reg = 0x52008, 2219 .enable_mask = BIT(18), 2220 .hw.init = &(struct clk_init_data){ 2221 .name = "gcc_qupv3_wrap1_core_2x_clk", 2222 .ops = &clk_branch2_ops, 2223 }, 2224 }, 2225 }; 2226 2227 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2228 .halt_reg = 0x23138, 2229 .halt_check = BRANCH_HALT_VOTED, 2230 .clkr = { 2231 .enable_reg = 0x52008, 2232 .enable_mask = BIT(19), 2233 .hw.init = &(struct clk_init_data){ 2234 .name = "gcc_qupv3_wrap1_core_clk", 2235 .ops = &clk_branch2_ops, 2236 }, 2237 }, 2238 }; 2239 2240 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2241 .halt_reg = 0x1800c, 2242 .halt_check = BRANCH_HALT_VOTED, 2243 .clkr = { 2244 .enable_reg = 0x52008, 2245 .enable_mask = BIT(22), 2246 .hw.init = &(struct clk_init_data){ 2247 .name = "gcc_qupv3_wrap1_s0_clk", 2248 .parent_hws = (const struct clk_hw*[]){ 2249 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2250 }, 2251 .num_parents = 1, 2252 .flags = CLK_SET_RATE_PARENT, 2253 .ops = &clk_branch2_ops, 2254 }, 2255 }, 2256 }; 2257 2258 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2259 .halt_reg = 0x1813c, 2260 .halt_check = BRANCH_HALT_VOTED, 2261 .clkr = { 2262 .enable_reg = 0x52008, 2263 .enable_mask = BIT(23), 2264 .hw.init = &(struct clk_init_data){ 2265 .name = "gcc_qupv3_wrap1_s1_clk", 2266 .parent_hws = (const struct clk_hw*[]){ 2267 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2268 }, 2269 .num_parents = 1, 2270 .flags = CLK_SET_RATE_PARENT, 2271 .ops = &clk_branch2_ops, 2272 }, 2273 }, 2274 }; 2275 2276 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2277 .halt_reg = 0x1826c, 2278 .halt_check = BRANCH_HALT_VOTED, 2279 .clkr = { 2280 .enable_reg = 0x52008, 2281 .enable_mask = BIT(24), 2282 .hw.init = &(struct clk_init_data){ 2283 .name = "gcc_qupv3_wrap1_s2_clk", 2284 .parent_hws = (const struct clk_hw*[]){ 2285 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2286 }, 2287 .num_parents = 1, 2288 .flags = CLK_SET_RATE_PARENT, 2289 .ops = &clk_branch2_ops, 2290 }, 2291 }, 2292 }; 2293 2294 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2295 .halt_reg = 0x1839c, 2296 .halt_check = BRANCH_HALT_VOTED, 2297 .clkr = { 2298 .enable_reg = 0x52008, 2299 .enable_mask = BIT(25), 2300 .hw.init = &(struct clk_init_data){ 2301 .name = "gcc_qupv3_wrap1_s3_clk", 2302 .parent_hws = (const struct clk_hw*[]){ 2303 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2304 }, 2305 .num_parents = 1, 2306 .flags = CLK_SET_RATE_PARENT, 2307 .ops = &clk_branch2_ops, 2308 }, 2309 }, 2310 }; 2311 2312 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2313 .halt_reg = 0x184cc, 2314 .halt_check = BRANCH_HALT_VOTED, 2315 .clkr = { 2316 .enable_reg = 0x52008, 2317 .enable_mask = BIT(26), 2318 .hw.init = &(struct clk_init_data){ 2319 .name = "gcc_qupv3_wrap1_s4_clk", 2320 .parent_hws = (const struct clk_hw*[]){ 2321 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2322 }, 2323 .num_parents = 1, 2324 .flags = CLK_SET_RATE_PARENT, 2325 .ops = &clk_branch2_ops, 2326 }, 2327 }, 2328 }; 2329 2330 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2331 .halt_reg = 0x185fc, 2332 .halt_check = BRANCH_HALT_VOTED, 2333 .clkr = { 2334 .enable_reg = 0x52008, 2335 .enable_mask = BIT(27), 2336 .hw.init = &(struct clk_init_data){ 2337 .name = "gcc_qupv3_wrap1_s5_clk", 2338 .parent_hws = (const struct clk_hw*[]){ 2339 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2340 }, 2341 .num_parents = 1, 2342 .flags = CLK_SET_RATE_PARENT, 2343 .ops = &clk_branch2_ops, 2344 }, 2345 }, 2346 }; 2347 2348 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 2349 .halt_reg = 0x1872c, 2350 .halt_check = BRANCH_HALT_VOTED, 2351 .clkr = { 2352 .enable_reg = 0x52000, 2353 .enable_mask = BIT(13), 2354 .hw.init = &(struct clk_init_data){ 2355 .name = "gcc_qupv3_wrap1_s6_clk", 2356 .parent_hws = (const struct clk_hw*[]){ 2357 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 2358 }, 2359 .num_parents = 1, 2360 .flags = CLK_SET_RATE_PARENT, 2361 .ops = &clk_branch2_ops, 2362 }, 2363 }, 2364 }; 2365 2366 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 2367 .halt_reg = 0x1885c, 2368 .halt_check = BRANCH_HALT_VOTED, 2369 .clkr = { 2370 .enable_reg = 0x52000, 2371 .enable_mask = BIT(14), 2372 .hw.init = &(struct clk_init_data){ 2373 .name = "gcc_qupv3_wrap1_s7_clk", 2374 .parent_hws = (const struct clk_hw*[]){ 2375 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 2376 }, 2377 .num_parents = 1, 2378 .flags = CLK_SET_RATE_PARENT, 2379 .ops = &clk_branch2_ops, 2380 }, 2381 }, 2382 }; 2383 2384 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2385 .halt_reg = 0x17004, 2386 .halt_check = BRANCH_HALT_VOTED, 2387 .hwcg_reg = 0x17004, 2388 .hwcg_bit = 1, 2389 .clkr = { 2390 .enable_reg = 0x52008, 2391 .enable_mask = BIT(6), 2392 .hw.init = &(struct clk_init_data){ 2393 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2394 .ops = &clk_branch2_ops, 2395 }, 2396 }, 2397 }; 2398 2399 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2400 .halt_reg = 0x17008, 2401 .halt_check = BRANCH_HALT_VOTED, 2402 .hwcg_reg = 0x17008, 2403 .hwcg_bit = 1, 2404 .clkr = { 2405 .enable_reg = 0x52008, 2406 .enable_mask = BIT(7), 2407 .hw.init = &(struct clk_init_data){ 2408 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2409 .ops = &clk_branch2_ops, 2410 }, 2411 }, 2412 }; 2413 2414 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2415 .halt_reg = 0x18004, 2416 .halt_check = BRANCH_HALT_VOTED, 2417 .hwcg_reg = 0x18004, 2418 .hwcg_bit = 1, 2419 .clkr = { 2420 .enable_reg = 0x52008, 2421 .enable_mask = BIT(20), 2422 .hw.init = &(struct clk_init_data){ 2423 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2424 .ops = &clk_branch2_ops, 2425 }, 2426 }, 2427 }; 2428 2429 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2430 .halt_reg = 0x18008, 2431 .halt_check = BRANCH_HALT_VOTED, 2432 .hwcg_reg = 0x18008, 2433 .hwcg_bit = 1, 2434 .clkr = { 2435 .enable_reg = 0x52008, 2436 .enable_mask = BIT(21), 2437 .hw.init = &(struct clk_init_data){ 2438 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2439 .ops = &clk_branch2_ops, 2440 }, 2441 }, 2442 }; 2443 2444 static struct clk_branch gcc_sdcc1_ahb_clk = { 2445 .halt_reg = 0x75004, 2446 .halt_check = BRANCH_HALT, 2447 .clkr = { 2448 .enable_reg = 0x75004, 2449 .enable_mask = BIT(0), 2450 .hw.init = &(struct clk_init_data){ 2451 .name = "gcc_sdcc1_ahb_clk", 2452 .ops = &clk_branch2_ops, 2453 }, 2454 }, 2455 }; 2456 2457 static struct clk_branch gcc_sdcc1_apps_clk = { 2458 .halt_reg = 0x75008, 2459 .halt_check = BRANCH_HALT, 2460 .clkr = { 2461 .enable_reg = 0x75008, 2462 .enable_mask = BIT(0), 2463 .hw.init = &(struct clk_init_data){ 2464 .name = "gcc_sdcc1_apps_clk", 2465 .parent_hws = (const struct clk_hw*[]){ 2466 &gcc_sdcc1_apps_clk_src.clkr.hw, 2467 }, 2468 .num_parents = 1, 2469 .flags = CLK_SET_RATE_PARENT, 2470 .ops = &clk_branch2_ops, 2471 }, 2472 }, 2473 }; 2474 2475 static struct clk_branch gcc_sdcc1_ice_core_clk = { 2476 .halt_reg = 0x75024, 2477 .halt_check = BRANCH_HALT_VOTED, 2478 .hwcg_reg = 0x75024, 2479 .hwcg_bit = 1, 2480 .clkr = { 2481 .enable_reg = 0x75024, 2482 .enable_mask = BIT(0), 2483 .hw.init = &(struct clk_init_data){ 2484 .name = "gcc_sdcc1_ice_core_clk", 2485 .parent_hws = (const struct clk_hw*[]){ 2486 &gcc_sdcc1_ice_core_clk_src.clkr.hw, 2487 }, 2488 .num_parents = 1, 2489 .flags = CLK_SET_RATE_PARENT, 2490 .ops = &clk_branch2_ops, 2491 }, 2492 }, 2493 }; 2494 2495 static struct clk_branch gcc_sdcc2_ahb_clk = { 2496 .halt_reg = 0x14008, 2497 .halt_check = BRANCH_HALT, 2498 .clkr = { 2499 .enable_reg = 0x14008, 2500 .enable_mask = BIT(0), 2501 .hw.init = &(struct clk_init_data){ 2502 .name = "gcc_sdcc2_ahb_clk", 2503 .ops = &clk_branch2_ops, 2504 }, 2505 }, 2506 }; 2507 2508 static struct clk_branch gcc_sdcc2_apps_clk = { 2509 .halt_reg = 0x14004, 2510 .halt_check = BRANCH_HALT, 2511 .clkr = { 2512 .enable_reg = 0x14004, 2513 .enable_mask = BIT(0), 2514 .hw.init = &(struct clk_init_data){ 2515 .name = "gcc_sdcc2_apps_clk", 2516 .parent_hws = (const struct clk_hw*[]){ 2517 &gcc_sdcc2_apps_clk_src.clkr.hw, 2518 }, 2519 .num_parents = 1, 2520 .flags = CLK_SET_RATE_PARENT, 2521 .ops = &clk_branch2_ops, 2522 }, 2523 }, 2524 }; 2525 2526 static struct clk_branch gcc_sdcc4_ahb_clk = { 2527 .halt_reg = 0x16008, 2528 .halt_check = BRANCH_HALT, 2529 .clkr = { 2530 .enable_reg = 0x16008, 2531 .enable_mask = BIT(0), 2532 .hw.init = &(struct clk_init_data){ 2533 .name = "gcc_sdcc4_ahb_clk", 2534 .ops = &clk_branch2_ops, 2535 }, 2536 }, 2537 }; 2538 2539 static struct clk_branch gcc_sdcc4_apps_clk = { 2540 .halt_reg = 0x16004, 2541 .halt_check = BRANCH_HALT, 2542 .clkr = { 2543 .enable_reg = 0x16004, 2544 .enable_mask = BIT(0), 2545 .hw.init = &(struct clk_init_data){ 2546 .name = "gcc_sdcc4_apps_clk", 2547 .parent_hws = (const struct clk_hw*[]){ 2548 &gcc_sdcc4_apps_clk_src.clkr.hw, 2549 }, 2550 .num_parents = 1, 2551 .flags = CLK_SET_RATE_PARENT, 2552 .ops = &clk_branch2_ops, 2553 }, 2554 }, 2555 }; 2556 2557 static struct clk_branch gcc_throttle_pcie_ahb_clk = { 2558 .halt_reg = 0x9001c, 2559 .halt_check = BRANCH_HALT, 2560 .clkr = { 2561 .enable_reg = 0x9001c, 2562 .enable_mask = BIT(0), 2563 .hw.init = &(struct clk_init_data){ 2564 .name = "gcc_throttle_pcie_ahb_clk", 2565 .ops = &clk_branch2_ops, 2566 }, 2567 }, 2568 }; 2569 2570 static struct clk_branch gcc_titan_nrt_throttle_core_clk = { 2571 .halt_reg = 0x26024, 2572 .halt_check = BRANCH_HALT_SKIP, 2573 .hwcg_reg = 0x26024, 2574 .hwcg_bit = 1, 2575 .clkr = { 2576 .enable_reg = 0x26024, 2577 .enable_mask = BIT(0), 2578 .hw.init = &(struct clk_init_data){ 2579 .name = "gcc_titan_nrt_throttle_core_clk", 2580 .ops = &clk_branch2_ops, 2581 }, 2582 }, 2583 }; 2584 2585 static struct clk_branch gcc_titan_rt_throttle_core_clk = { 2586 .halt_reg = 0x26018, 2587 .halt_check = BRANCH_HALT_SKIP, 2588 .hwcg_reg = 0x26018, 2589 .hwcg_bit = 1, 2590 .clkr = { 2591 .enable_reg = 0x26018, 2592 .enable_mask = BIT(0), 2593 .hw.init = &(struct clk_init_data){ 2594 .name = "gcc_titan_rt_throttle_core_clk", 2595 .ops = &clk_branch2_ops, 2596 }, 2597 }, 2598 }; 2599 2600 static struct clk_branch gcc_ufs_1_clkref_en = { 2601 .halt_reg = 0x8c000, 2602 .halt_check = BRANCH_HALT, 2603 .clkr = { 2604 .enable_reg = 0x8c000, 2605 .enable_mask = BIT(0), 2606 .hw.init = &(struct clk_init_data){ 2607 .name = "gcc_ufs_1_clkref_en", 2608 .ops = &clk_branch2_ops, 2609 }, 2610 }, 2611 }; 2612 2613 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2614 .halt_reg = 0x77018, 2615 .halt_check = BRANCH_HALT_VOTED, 2616 .hwcg_reg = 0x77018, 2617 .hwcg_bit = 1, 2618 .clkr = { 2619 .enable_reg = 0x77018, 2620 .enable_mask = BIT(0), 2621 .hw.init = &(struct clk_init_data){ 2622 .name = "gcc_ufs_phy_ahb_clk", 2623 .ops = &clk_branch2_ops, 2624 }, 2625 }, 2626 }; 2627 2628 static struct clk_branch gcc_ufs_phy_axi_clk = { 2629 .halt_reg = 0x77010, 2630 .halt_check = BRANCH_HALT_VOTED, 2631 .hwcg_reg = 0x77010, 2632 .hwcg_bit = 1, 2633 .clkr = { 2634 .enable_reg = 0x77010, 2635 .enable_mask = BIT(0), 2636 .hw.init = &(struct clk_init_data){ 2637 .name = "gcc_ufs_phy_axi_clk", 2638 .parent_hws = (const struct clk_hw*[]){ 2639 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2640 }, 2641 .num_parents = 1, 2642 .flags = CLK_SET_RATE_PARENT, 2643 .ops = &clk_branch2_ops, 2644 }, 2645 }, 2646 }; 2647 2648 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2649 .halt_reg = 0x77064, 2650 .halt_check = BRANCH_HALT_VOTED, 2651 .hwcg_reg = 0x77064, 2652 .hwcg_bit = 1, 2653 .clkr = { 2654 .enable_reg = 0x77064, 2655 .enable_mask = BIT(0), 2656 .hw.init = &(struct clk_init_data){ 2657 .name = "gcc_ufs_phy_ice_core_clk", 2658 .parent_hws = (const struct clk_hw*[]){ 2659 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2660 }, 2661 .num_parents = 1, 2662 .flags = CLK_SET_RATE_PARENT, 2663 .ops = &clk_branch2_ops, 2664 }, 2665 }, 2666 }; 2667 2668 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2669 .halt_reg = 0x7709c, 2670 .halt_check = BRANCH_HALT_VOTED, 2671 .hwcg_reg = 0x7709c, 2672 .hwcg_bit = 1, 2673 .clkr = { 2674 .enable_reg = 0x7709c, 2675 .enable_mask = BIT(0), 2676 .hw.init = &(struct clk_init_data){ 2677 .name = "gcc_ufs_phy_phy_aux_clk", 2678 .parent_hws = (const struct clk_hw*[]){ 2679 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2680 }, 2681 .num_parents = 1, 2682 .flags = CLK_SET_RATE_PARENT, 2683 .ops = &clk_branch2_ops, 2684 }, 2685 }, 2686 }; 2687 2688 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2689 .halt_reg = 0x77020, 2690 .halt_check = BRANCH_HALT_DELAY, 2691 .clkr = { 2692 .enable_reg = 0x77020, 2693 .enable_mask = BIT(0), 2694 .hw.init = &(struct clk_init_data){ 2695 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2696 .parent_hws = (const struct clk_hw*[]){ 2697 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 2698 }, 2699 .num_parents = 1, 2700 .flags = CLK_SET_RATE_PARENT, 2701 .ops = &clk_branch2_ops, 2702 }, 2703 }, 2704 }; 2705 2706 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2707 .halt_reg = 0x770b8, 2708 .halt_check = BRANCH_HALT_DELAY, 2709 .clkr = { 2710 .enable_reg = 0x770b8, 2711 .enable_mask = BIT(0), 2712 .hw.init = &(struct clk_init_data){ 2713 .name = "gcc_ufs_phy_rx_symbol_1_clk", 2714 .parent_hws = (const struct clk_hw*[]){ 2715 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 2716 }, 2717 .num_parents = 1, 2718 .flags = CLK_SET_RATE_PARENT, 2719 .ops = &clk_branch2_ops, 2720 }, 2721 }, 2722 }; 2723 2724 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2725 .halt_reg = 0x7701c, 2726 .halt_check = BRANCH_HALT_DELAY, 2727 .clkr = { 2728 .enable_reg = 0x7701c, 2729 .enable_mask = BIT(0), 2730 .hw.init = &(struct clk_init_data){ 2731 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2732 .parent_hws = (const struct clk_hw*[]){ 2733 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 2734 }, 2735 .num_parents = 1, 2736 .flags = CLK_SET_RATE_PARENT, 2737 .ops = &clk_branch2_ops, 2738 }, 2739 }, 2740 }; 2741 2742 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2743 .halt_reg = 0x7705c, 2744 .halt_check = BRANCH_HALT_VOTED, 2745 .hwcg_reg = 0x7705c, 2746 .hwcg_bit = 1, 2747 .clkr = { 2748 .enable_reg = 0x7705c, 2749 .enable_mask = BIT(0), 2750 .hw.init = &(struct clk_init_data){ 2751 .name = "gcc_ufs_phy_unipro_core_clk", 2752 .parent_hws = (const struct clk_hw*[]){ 2753 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2754 }, 2755 .num_parents = 1, 2756 .flags = CLK_SET_RATE_PARENT, 2757 .ops = &clk_branch2_ops, 2758 }, 2759 }, 2760 }; 2761 2762 static struct clk_branch gcc_usb30_prim_master_clk = { 2763 .halt_reg = 0xf010, 2764 .halt_check = BRANCH_HALT, 2765 .clkr = { 2766 .enable_reg = 0xf010, 2767 .enable_mask = BIT(0), 2768 .hw.init = &(struct clk_init_data){ 2769 .name = "gcc_usb30_prim_master_clk", 2770 .parent_hws = (const struct clk_hw*[]){ 2771 &gcc_usb30_prim_master_clk_src.clkr.hw, 2772 }, 2773 .num_parents = 1, 2774 .flags = CLK_SET_RATE_PARENT, 2775 .ops = &clk_branch2_ops, 2776 }, 2777 }, 2778 }; 2779 2780 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2781 .halt_reg = 0xf01c, 2782 .halt_check = BRANCH_HALT, 2783 .clkr = { 2784 .enable_reg = 0xf01c, 2785 .enable_mask = BIT(0), 2786 .hw.init = &(struct clk_init_data){ 2787 .name = "gcc_usb30_prim_mock_utmi_clk", 2788 .parent_data = &(const struct clk_parent_data){ 2789 .hw = 2790 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2791 }, 2792 .num_parents = 1, 2793 .flags = CLK_SET_RATE_PARENT, 2794 .ops = &clk_branch2_ops, 2795 }, 2796 }, 2797 }; 2798 2799 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2800 .halt_reg = 0xf018, 2801 .halt_check = BRANCH_HALT, 2802 .clkr = { 2803 .enable_reg = 0xf018, 2804 .enable_mask = BIT(0), 2805 .hw.init = &(struct clk_init_data){ 2806 .name = "gcc_usb30_prim_sleep_clk", 2807 .ops = &clk_branch2_ops, 2808 }, 2809 }, 2810 }; 2811 2812 static struct clk_branch gcc_usb30_sec_master_clk = { 2813 .halt_reg = 0x9e010, 2814 .halt_check = BRANCH_HALT, 2815 .clkr = { 2816 .enable_reg = 0x9e010, 2817 .enable_mask = BIT(0), 2818 .hw.init = &(struct clk_init_data){ 2819 .name = "gcc_usb30_sec_master_clk", 2820 .parent_hws = (const struct clk_hw*[]){ 2821 &gcc_usb30_sec_master_clk_src.clkr.hw, 2822 }, 2823 .num_parents = 1, 2824 .flags = CLK_SET_RATE_PARENT, 2825 .ops = &clk_branch2_ops, 2826 }, 2827 }, 2828 }; 2829 2830 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { 2831 .halt_reg = 0x9e01c, 2832 .halt_check = BRANCH_HALT, 2833 .clkr = { 2834 .enable_reg = 0x9e01c, 2835 .enable_mask = BIT(0), 2836 .hw.init = &(struct clk_init_data){ 2837 .name = "gcc_usb30_sec_mock_utmi_clk", 2838 .parent_data = &(const struct clk_parent_data){ 2839 .hw = 2840 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw, 2841 }, 2842 .num_parents = 1, 2843 .flags = CLK_SET_RATE_PARENT, 2844 .ops = &clk_branch2_ops, 2845 }, 2846 }, 2847 }; 2848 2849 static struct clk_branch gcc_usb30_sec_sleep_clk = { 2850 .halt_reg = 0x9e018, 2851 .halt_check = BRANCH_HALT, 2852 .clkr = { 2853 .enable_reg = 0x9e018, 2854 .enable_mask = BIT(0), 2855 .hw.init = &(struct clk_init_data){ 2856 .name = "gcc_usb30_sec_sleep_clk", 2857 .ops = &clk_branch2_ops, 2858 }, 2859 }, 2860 }; 2861 2862 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2863 .halt_reg = 0xf054, 2864 .halt_check = BRANCH_HALT, 2865 .clkr = { 2866 .enable_reg = 0xf054, 2867 .enable_mask = BIT(0), 2868 .hw.init = &(struct clk_init_data){ 2869 .name = "gcc_usb3_prim_phy_aux_clk", 2870 .parent_hws = (const struct clk_hw*[]){ 2871 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2872 }, 2873 .num_parents = 1, 2874 .flags = CLK_SET_RATE_PARENT, 2875 .ops = &clk_branch2_ops, 2876 }, 2877 }, 2878 }; 2879 2880 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2881 .halt_reg = 0xf058, 2882 .halt_check = BRANCH_HALT, 2883 .clkr = { 2884 .enable_reg = 0xf058, 2885 .enable_mask = BIT(0), 2886 .hw.init = &(struct clk_init_data){ 2887 .name = "gcc_usb3_prim_phy_com_aux_clk", 2888 .parent_hws = (const struct clk_hw*[]){ 2889 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2890 }, 2891 .num_parents = 1, 2892 .flags = CLK_SET_RATE_PARENT, 2893 .ops = &clk_branch2_ops, 2894 }, 2895 }, 2896 }; 2897 2898 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2899 .halt_reg = 0xf05c, 2900 .halt_check = BRANCH_HALT_DELAY, 2901 .hwcg_reg = 0xf05c, 2902 .hwcg_bit = 1, 2903 .clkr = { 2904 .enable_reg = 0xf05c, 2905 .enable_mask = BIT(0), 2906 .hw.init = &(struct clk_init_data){ 2907 .name = "gcc_usb3_prim_phy_pipe_clk", 2908 .parent_hws = (const struct clk_hw*[]){ 2909 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 2910 }, 2911 .num_parents = 1, 2912 .flags = CLK_SET_RATE_PARENT, 2913 .ops = &clk_branch2_ops, 2914 }, 2915 }, 2916 }; 2917 2918 static struct clk_branch gcc_cfg_noc_lpass_clk = { 2919 .halt_reg = 0x47020, 2920 .halt_check = BRANCH_HALT, 2921 .clkr = { 2922 .enable_reg = 0x47020, 2923 .enable_mask = BIT(0), 2924 .hw.init = &(struct clk_init_data){ 2925 .name = "gcc_cfg_noc_lpass_clk", 2926 .ops = &clk_branch2_ops, 2927 }, 2928 }, 2929 }; 2930 static struct clk_branch gcc_mss_cfg_ahb_clk = { 2931 .halt_reg = 0x8a000, 2932 .halt_check = BRANCH_HALT, 2933 .clkr = { 2934 .enable_reg = 0x8a000, 2935 .enable_mask = BIT(0), 2936 .hw.init = &(struct clk_init_data){ 2937 .name = "gcc_mss_cfg_ahb_clk", 2938 .ops = &clk_branch2_ops, 2939 }, 2940 }, 2941 }; 2942 2943 static struct clk_branch gcc_mss_offline_axi_clk = { 2944 .halt_reg = 0x8a004, 2945 .halt_check = BRANCH_HALT_DELAY, 2946 .clkr = { 2947 .enable_reg = 0x8a004, 2948 .enable_mask = BIT(0), 2949 .hw.init = &(struct clk_init_data){ 2950 .name = "gcc_mss_offline_axi_clk", 2951 .ops = &clk_branch2_ops, 2952 }, 2953 }, 2954 }; 2955 2956 static struct clk_branch gcc_mss_snoc_axi_clk = { 2957 .halt_reg = 0x8a154, 2958 .halt_check = BRANCH_HALT_DELAY, 2959 .clkr = { 2960 .enable_reg = 0x8a154, 2961 .enable_mask = BIT(0), 2962 .hw.init = &(struct clk_init_data){ 2963 .name = "gcc_mss_snoc_axi_clk", 2964 .ops = &clk_branch2_ops, 2965 }, 2966 }, 2967 }; 2968 2969 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = { 2970 .halt_reg = 0x8a158, 2971 .halt_check = BRANCH_HALT, 2972 .clkr = { 2973 .enable_reg = 0x8a158, 2974 .enable_mask = BIT(0), 2975 .hw.init = &(struct clk_init_data){ 2976 .name = "gcc_mss_q6_memnoc_axi_clk", 2977 .ops = &clk_branch2_ops, 2978 }, 2979 }, 2980 }; 2981 2982 static struct clk_regmap_mux gcc_mss_q6ss_boot_clk_src = { 2983 .reg = 0x8a2a4, 2984 .shift = 0, 2985 .width = 1, 2986 .parent_map = gcc_parent_map_15, 2987 .clkr = { 2988 .hw.init = &(struct clk_init_data){ 2989 .name = "gcc_mss_q6ss_boot_clk_src", 2990 .parent_data = gcc_parent_data_15, 2991 .num_parents = ARRAY_SIZE(gcc_parent_data_15), 2992 .ops = &clk_regmap_mux_closest_ops, 2993 }, 2994 }, 2995 }; 2996 2997 static struct clk_branch gcc_usb3_sec_phy_aux_clk = { 2998 .halt_reg = 0x9e054, 2999 .halt_check = BRANCH_HALT, 3000 .clkr = { 3001 .enable_reg = 0x9e054, 3002 .enable_mask = BIT(0), 3003 .hw.init = &(struct clk_init_data){ 3004 .name = "gcc_usb3_sec_phy_aux_clk", 3005 .parent_hws = (const struct clk_hw*[]){ 3006 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 3007 }, 3008 .num_parents = 1, 3009 .flags = CLK_SET_RATE_PARENT, 3010 .ops = &clk_branch2_ops, 3011 }, 3012 }, 3013 }; 3014 3015 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { 3016 .halt_reg = 0x9e058, 3017 .halt_check = BRANCH_HALT, 3018 .clkr = { 3019 .enable_reg = 0x9e058, 3020 .enable_mask = BIT(0), 3021 .hw.init = &(struct clk_init_data){ 3022 .name = "gcc_usb3_sec_phy_com_aux_clk", 3023 .parent_hws = (const struct clk_hw*[]){ 3024 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 3025 }, 3026 .num_parents = 1, 3027 .flags = CLK_SET_RATE_PARENT, 3028 .ops = &clk_branch2_ops, 3029 }, 3030 }, 3031 }; 3032 3033 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { 3034 .halt_reg = 0x9e05c, 3035 .halt_check = BRANCH_HALT_SKIP, 3036 .hwcg_reg = 0x9e05c, 3037 .hwcg_bit = 1, 3038 .clkr = { 3039 .enable_reg = 0x9e05c, 3040 .enable_mask = BIT(0), 3041 .hw.init = &(struct clk_init_data){ 3042 .name = "gcc_usb3_sec_phy_pipe_clk", 3043 .parent_hws = (const struct clk_hw*[]){ 3044 &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw, 3045 }, 3046 .num_parents = 1, 3047 .flags = CLK_SET_RATE_PARENT, 3048 .ops = &clk_branch2_ops, 3049 }, 3050 }, 3051 }; 3052 3053 static struct clk_branch gcc_video_axi0_clk = { 3054 .halt_reg = 0x2800c, 3055 .halt_check = BRANCH_HALT_SKIP, 3056 .hwcg_reg = 0x2800c, 3057 .hwcg_bit = 1, 3058 .clkr = { 3059 .enable_reg = 0x2800c, 3060 .enable_mask = BIT(0), 3061 .hw.init = &(struct clk_init_data){ 3062 .name = "gcc_video_axi0_clk", 3063 .ops = &clk_branch2_ops, 3064 }, 3065 }, 3066 }; 3067 3068 static struct clk_branch gcc_video_mvp_throttle_core_clk = { 3069 .halt_reg = 0x28010, 3070 .halt_check = BRANCH_HALT_SKIP, 3071 .hwcg_reg = 0x28010, 3072 .hwcg_bit = 1, 3073 .clkr = { 3074 .enable_reg = 0x28010, 3075 .enable_mask = BIT(0), 3076 .hw.init = &(struct clk_init_data){ 3077 .name = "gcc_video_mvp_throttle_core_clk", 3078 .ops = &clk_branch2_ops, 3079 }, 3080 }, 3081 }; 3082 3083 static struct clk_branch gcc_wpss_ahb_clk = { 3084 .halt_reg = 0x9d154, 3085 .halt_check = BRANCH_HALT, 3086 .clkr = { 3087 .enable_reg = 0x9d154, 3088 .enable_mask = BIT(0), 3089 .hw.init = &(struct clk_init_data){ 3090 .name = "gcc_wpss_ahb_clk", 3091 .ops = &clk_branch2_ops, 3092 }, 3093 }, 3094 }; 3095 3096 static struct clk_branch gcc_wpss_ahb_bdg_mst_clk = { 3097 .halt_reg = 0x9d158, 3098 .halt_check = BRANCH_HALT, 3099 .clkr = { 3100 .enable_reg = 0x9d158, 3101 .enable_mask = BIT(0), 3102 .hw.init = &(struct clk_init_data){ 3103 .name = "gcc_wpss_ahb_bdg_mst_clk", 3104 .ops = &clk_branch2_ops, 3105 }, 3106 }, 3107 }; 3108 3109 static struct clk_branch gcc_wpss_rscp_clk = { 3110 .halt_reg = 0x9d16c, 3111 .halt_check = BRANCH_HALT, 3112 .clkr = { 3113 .enable_reg = 0x9d16c, 3114 .enable_mask = BIT(0), 3115 .hw.init = &(struct clk_init_data){ 3116 .name = "gcc_wpss_rscp_clk", 3117 .ops = &clk_branch2_ops, 3118 }, 3119 }, 3120 }; 3121 3122 static struct gdsc gcc_pcie_0_gdsc = { 3123 .gdscr = 0x6b004, 3124 .pd = { 3125 .name = "gcc_pcie_0_gdsc", 3126 }, 3127 .pwrsts = PWRSTS_OFF_ON, 3128 .flags = VOTABLE, 3129 }; 3130 3131 static struct gdsc gcc_pcie_1_gdsc = { 3132 .gdscr = 0x8d004, 3133 .pd = { 3134 .name = "gcc_pcie_1_gdsc", 3135 }, 3136 .pwrsts = PWRSTS_OFF_ON, 3137 .flags = VOTABLE, 3138 }; 3139 3140 static struct gdsc gcc_ufs_phy_gdsc = { 3141 .gdscr = 0x77004, 3142 .pd = { 3143 .name = "gcc_ufs_phy_gdsc", 3144 }, 3145 .pwrsts = PWRSTS_OFF_ON, 3146 .flags = VOTABLE, 3147 }; 3148 3149 static struct gdsc gcc_usb30_prim_gdsc = { 3150 .gdscr = 0xf004, 3151 .pd = { 3152 .name = "gcc_usb30_prim_gdsc", 3153 }, 3154 .pwrsts = PWRSTS_OFF_ON, 3155 .flags = VOTABLE, 3156 }; 3157 3158 static struct gdsc gcc_usb30_sec_gdsc = { 3159 .gdscr = 0x9e004, 3160 .pd = { 3161 .name = "gcc_usb30_sec_gdsc", 3162 }, 3163 .pwrsts = PWRSTS_OFF_ON, 3164 .flags = VOTABLE, 3165 }; 3166 3167 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { 3168 .gdscr = 0x7d050, 3169 .pd = { 3170 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", 3171 }, 3172 .pwrsts = PWRSTS_OFF_ON, 3173 .flags = VOTABLE, 3174 }; 3175 3176 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = { 3177 .gdscr = 0x7d058, 3178 .pd = { 3179 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", 3180 }, 3181 .pwrsts = PWRSTS_OFF_ON, 3182 .flags = VOTABLE, 3183 }; 3184 3185 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = { 3186 .gdscr = 0x7d054, 3187 .pd = { 3188 .name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc", 3189 }, 3190 .pwrsts = PWRSTS_OFF_ON, 3191 .flags = VOTABLE, 3192 }; 3193 3194 static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { 3195 .gdscr = 0x7d05c, 3196 .pd = { 3197 .name = "hlos1_vote_turing_mmu_tbu0_gdsc", 3198 }, 3199 .pwrsts = PWRSTS_OFF_ON, 3200 .flags = VOTABLE, 3201 }; 3202 3203 static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = { 3204 .gdscr = 0x7d060, 3205 .pd = { 3206 .name = "hlos1_vote_turing_mmu_tbu1_gdsc", 3207 }, 3208 .pwrsts = PWRSTS_OFF_ON, 3209 .flags = VOTABLE, 3210 }; 3211 3212 static struct clk_regmap *gcc_sc7280_clocks[] = { 3213 [GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr, 3214 [GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr, 3215 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 3216 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 3217 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, 3218 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 3219 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 3220 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3221 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, 3222 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 3223 [GCC_DDRSS_PCIE_SF_CLK] = &gcc_ddrss_pcie_sf_clk.clkr, 3224 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 3225 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3226 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, 3227 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3228 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3229 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3230 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3231 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3232 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3233 [GCC_GPLL0] = &gcc_gpll0.clkr, 3234 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 3235 [GCC_GPLL0_OUT_ODD] = &gcc_gpll0_out_odd.clkr, 3236 [GCC_GPLL1] = &gcc_gpll1.clkr, 3237 [GCC_GPLL10] = &gcc_gpll10.clkr, 3238 [GCC_GPLL4] = &gcc_gpll4.clkr, 3239 [GCC_GPLL9] = &gcc_gpll9.clkr, 3240 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3241 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3242 [GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr, 3243 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3244 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3245 [GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr, 3246 [GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr, 3247 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3248 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 3249 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3250 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3251 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 3252 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3253 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 3254 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3255 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 3256 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 3257 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 3258 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 3259 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 3260 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 3261 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 3262 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr, 3263 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 3264 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 3265 [GCC_PCIE_THROTTLE_CORE_CLK] = &gcc_pcie_throttle_core_clk.clkr, 3266 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3267 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3268 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3269 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3270 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3271 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3272 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3273 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3274 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, 3275 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, 3276 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, 3277 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 3278 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 3279 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3280 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3281 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3282 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3283 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3284 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3285 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3286 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3287 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3288 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3289 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3290 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3291 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 3292 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 3293 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 3294 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 3295 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3296 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3297 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3298 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3299 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3300 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3301 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3302 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3303 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3304 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3305 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3306 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3307 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3308 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3309 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 3310 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 3311 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 3312 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 3313 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3314 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3315 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3316 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3317 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3318 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3319 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 3320 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 3321 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 3322 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3323 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3324 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3325 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3326 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3327 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 3328 [GCC_THROTTLE_PCIE_AHB_CLK] = &gcc_throttle_pcie_ahb_clk.clkr, 3329 [GCC_TITAN_NRT_THROTTLE_CORE_CLK] = 3330 &gcc_titan_nrt_throttle_core_clk.clkr, 3331 [GCC_TITAN_RT_THROTTLE_CORE_CLK] = &gcc_titan_rt_throttle_core_clk.clkr, 3332 [GCC_UFS_1_CLKREF_EN] = &gcc_ufs_1_clkref_en.clkr, 3333 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3334 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3335 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3336 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3337 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3338 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3339 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3340 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3341 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = 3342 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 3343 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3344 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = 3345 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 3346 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3347 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = 3348 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 3349 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3350 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 3351 &gcc_ufs_phy_unipro_core_clk_src.clkr, 3352 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3353 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3354 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3355 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 3356 &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3357 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = 3358 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3359 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3360 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, 3361 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, 3362 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, 3363 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = 3364 &gcc_usb30_sec_mock_utmi_clk_src.clkr, 3365 [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = 3366 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr, 3367 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, 3368 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3369 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3370 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3371 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3372 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 3373 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, 3374 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, 3375 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, 3376 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, 3377 [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr, 3378 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3379 [GCC_VIDEO_MVP_THROTTLE_CORE_CLK] = 3380 &gcc_video_mvp_throttle_core_clk.clkr, 3381 [GCC_CFG_NOC_LPASS_CLK] = &gcc_cfg_noc_lpass_clk.clkr, 3382 [GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC] = &gcc_mss_gpll0_main_div_clk_src.clkr, 3383 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 3384 [GCC_MSS_OFFLINE_AXI_CLK] = &gcc_mss_offline_axi_clk.clkr, 3385 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, 3386 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr, 3387 [GCC_MSS_Q6SS_BOOT_CLK_SRC] = &gcc_mss_q6ss_boot_clk_src.clkr, 3388 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, 3389 [GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK] = 3390 &gcc_aggre_noc_pcie_center_sf_axi_clk.clkr, 3391 [GCC_PCIE_CLKREF_EN] = &gcc_pcie_clkref_en.clkr, 3392 [GCC_EDP_CLKREF_EN] = &gcc_edp_clkref_en.clkr, 3393 [GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr, 3394 [GCC_WPSS_AHB_CLK] = &gcc_wpss_ahb_clk.clkr, 3395 [GCC_WPSS_AHB_BDG_MST_CLK] = &gcc_wpss_ahb_bdg_mst_clk.clkr, 3396 [GCC_WPSS_RSCP_CLK] = &gcc_wpss_rscp_clk.clkr, 3397 }; 3398 3399 static struct gdsc *gcc_sc7280_gdscs[] = { 3400 [GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc, 3401 [GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc, 3402 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, 3403 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 3404 [GCC_USB30_SEC_GDSC] = &gcc_usb30_sec_gdsc, 3405 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, 3406 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, 3407 [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc, 3408 [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc, 3409 [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, 3410 }; 3411 3412 static const struct qcom_reset_map gcc_sc7280_resets[] = { 3413 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3414 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3415 [GCC_PCIE_1_BCR] = { 0x8d000 }, 3416 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 3417 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3418 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3419 [GCC_SDCC1_BCR] = { 0x75000 }, 3420 [GCC_SDCC2_BCR] = { 0x14000 }, 3421 [GCC_SDCC4_BCR] = { 0x16000 }, 3422 [GCC_UFS_PHY_BCR] = { 0x77000 }, 3423 [GCC_USB30_PRIM_BCR] = { 0xf000 }, 3424 [GCC_USB30_SEC_BCR] = { 0x9e000 }, 3425 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 3426 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 3427 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3428 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 3429 }; 3430 3431 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3432 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3433 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3434 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3435 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3436 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3437 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3438 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 3439 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 3440 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3441 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3442 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 3443 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3444 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3445 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3446 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 3447 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 3448 }; 3449 3450 static const struct regmap_config gcc_sc7280_regmap_config = { 3451 .reg_bits = 32, 3452 .reg_stride = 4, 3453 .val_bits = 32, 3454 .max_register = 0x9f128, 3455 .fast_io = true, 3456 }; 3457 3458 static const struct qcom_cc_desc gcc_sc7280_desc = { 3459 .config = &gcc_sc7280_regmap_config, 3460 .clks = gcc_sc7280_clocks, 3461 .num_clks = ARRAY_SIZE(gcc_sc7280_clocks), 3462 .resets = gcc_sc7280_resets, 3463 .num_resets = ARRAY_SIZE(gcc_sc7280_resets), 3464 .gdscs = gcc_sc7280_gdscs, 3465 .num_gdscs = ARRAY_SIZE(gcc_sc7280_gdscs), 3466 }; 3467 3468 static const struct of_device_id gcc_sc7280_match_table[] = { 3469 { .compatible = "qcom,gcc-sc7280" }, 3470 { } 3471 }; 3472 MODULE_DEVICE_TABLE(of, gcc_sc7280_match_table); 3473 3474 static int gcc_sc7280_probe(struct platform_device *pdev) 3475 { 3476 struct regmap *regmap; 3477 int ret; 3478 3479 regmap = qcom_cc_map(pdev, &gcc_sc7280_desc); 3480 if (IS_ERR(regmap)) 3481 return PTR_ERR(regmap); 3482 3483 /* 3484 * Keep the clocks always-ON 3485 * GCC_CAMERA_AHB_CLK/XO_CLK, GCC_DISP_AHB_CLK/XO_CLK 3486 * GCC_VIDEO_AHB_CLK/XO_CLK, GCC_GPU_CFG_AHB_CLK 3487 */ 3488 regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); 3489 regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); 3490 regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); 3491 regmap_update_bits(regmap, 0x2701C, BIT(0), BIT(0)); 3492 regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); 3493 regmap_update_bits(regmap, 0x28014, BIT(0), BIT(0)); 3494 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 3495 3496 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3497 ARRAY_SIZE(gcc_dfs_clocks)); 3498 if (ret) 3499 return ret; 3500 3501 return qcom_cc_really_probe(pdev, &gcc_sc7280_desc, regmap); 3502 } 3503 3504 static struct platform_driver gcc_sc7280_driver = { 3505 .probe = gcc_sc7280_probe, 3506 .driver = { 3507 .name = "gcc-sc7280", 3508 .of_match_table = gcc_sc7280_match_table, 3509 }, 3510 }; 3511 3512 static int __init gcc_sc7280_init(void) 3513 { 3514 return platform_driver_register(&gcc_sc7280_driver); 3515 } 3516 subsys_initcall(gcc_sc7280_init); 3517 3518 static void __exit gcc_sc7280_exit(void) 3519 { 3520 platform_driver_unregister(&gcc_sc7280_driver); 3521 } 3522 module_exit(gcc_sc7280_exit); 3523 3524 MODULE_DESCRIPTION("QTI GCC SC7280 Driver"); 3525 MODULE_LICENSE("GPL v2"); 3526