1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/err.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/regmap.h> 13 14 #include <dt-bindings/clock/qcom,gcc-sc7180.h> 15 16 #include "clk-alpha-pll.h" 17 #include "clk-branch.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "common.h" 21 #include "gdsc.h" 22 #include "reset.h" 23 24 enum { 25 P_BI_TCXO, 26 P_CORE_BI_PLL_TEST_SE, 27 P_GPLL0_OUT_EVEN, 28 P_GPLL0_OUT_MAIN, 29 P_GPLL1_OUT_MAIN, 30 P_GPLL4_OUT_MAIN, 31 P_GPLL6_OUT_MAIN, 32 P_GPLL7_OUT_MAIN, 33 P_SLEEP_CLK, 34 }; 35 36 static struct clk_alpha_pll gpll0 = { 37 .offset = 0x0, 38 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 39 .clkr = { 40 .enable_reg = 0x52010, 41 .enable_mask = BIT(0), 42 .hw.init = &(struct clk_init_data){ 43 .name = "gpll0", 44 .parent_data = &(const struct clk_parent_data){ 45 .fw_name = "bi_tcxo", 46 .name = "bi_tcxo", 47 }, 48 .num_parents = 1, 49 .ops = &clk_alpha_pll_fixed_fabia_ops, 50 }, 51 }, 52 }; 53 54 static const struct clk_div_table post_div_table_gpll0_out_even[] = { 55 { 0x1, 2 }, 56 { } 57 }; 58 59 static struct clk_alpha_pll_postdiv gpll0_out_even = { 60 .offset = 0x0, 61 .post_div_shift = 8, 62 .post_div_table = post_div_table_gpll0_out_even, 63 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even), 64 .width = 4, 65 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 66 .clkr.hw.init = &(struct clk_init_data){ 67 .name = "gpll0_out_even", 68 .parent_data = &(const struct clk_parent_data){ 69 .hw = &gpll0.clkr.hw, 70 }, 71 .num_parents = 1, 72 .ops = &clk_alpha_pll_postdiv_fabia_ops, 73 }, 74 }; 75 76 static struct clk_fixed_factor gcc_pll0_main_div_cdiv = { 77 .mult = 1, 78 .div = 2, 79 .hw.init = &(struct clk_init_data){ 80 .name = "gcc_pll0_main_div_cdiv", 81 .parent_data = &(const struct clk_parent_data){ 82 .hw = &gpll0.clkr.hw, 83 }, 84 .num_parents = 1, 85 .ops = &clk_fixed_factor_ops, 86 }, 87 }; 88 89 static struct clk_alpha_pll gpll1 = { 90 .offset = 0x01000, 91 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 92 .clkr = { 93 .enable_reg = 0x52010, 94 .enable_mask = BIT(1), 95 .hw.init = &(struct clk_init_data){ 96 .name = "gpll1", 97 .parent_data = &(const struct clk_parent_data){ 98 .fw_name = "bi_tcxo", 99 .name = "bi_tcxo", 100 }, 101 .num_parents = 1, 102 .ops = &clk_alpha_pll_fixed_fabia_ops, 103 }, 104 }, 105 }; 106 107 static struct clk_alpha_pll gpll4 = { 108 .offset = 0x76000, 109 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 110 .clkr = { 111 .enable_reg = 0x52010, 112 .enable_mask = BIT(4), 113 .hw.init = &(struct clk_init_data){ 114 .name = "gpll4", 115 .parent_data = &(const struct clk_parent_data){ 116 .fw_name = "bi_tcxo", 117 .name = "bi_tcxo", 118 }, 119 .num_parents = 1, 120 .ops = &clk_alpha_pll_fixed_fabia_ops, 121 }, 122 }, 123 }; 124 125 static struct clk_alpha_pll gpll6 = { 126 .offset = 0x13000, 127 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 128 .clkr = { 129 .enable_reg = 0x52010, 130 .enable_mask = BIT(6), 131 .hw.init = &(struct clk_init_data){ 132 .name = "gpll6", 133 .parent_data = &(const struct clk_parent_data){ 134 .fw_name = "bi_tcxo", 135 .name = "bi_tcxo", 136 }, 137 .num_parents = 1, 138 .ops = &clk_alpha_pll_fixed_fabia_ops, 139 }, 140 }, 141 }; 142 143 static struct clk_alpha_pll gpll7 = { 144 .offset = 0x27000, 145 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 146 .clkr = { 147 .enable_reg = 0x52010, 148 .enable_mask = BIT(7), 149 .hw.init = &(struct clk_init_data){ 150 .name = "gpll7", 151 .parent_data = &(const struct clk_parent_data){ 152 .fw_name = "bi_tcxo", 153 .name = "bi_tcxo", 154 }, 155 .num_parents = 1, 156 .ops = &clk_alpha_pll_fixed_fabia_ops, 157 }, 158 }, 159 }; 160 161 static const struct parent_map gcc_parent_map_0[] = { 162 { P_BI_TCXO, 0 }, 163 { P_GPLL0_OUT_MAIN, 1 }, 164 { P_GPLL0_OUT_EVEN, 6 }, 165 { P_CORE_BI_PLL_TEST_SE, 7 }, 166 }; 167 168 static const struct clk_parent_data gcc_parent_data_0[] = { 169 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 170 { .hw = &gpll0.clkr.hw }, 171 { .hw = &gpll0_out_even.clkr.hw }, 172 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 173 }; 174 175 static const struct clk_parent_data gcc_parent_data_0_ao[] = { 176 { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" }, 177 { .hw = &gpll0.clkr.hw }, 178 { .hw = &gpll0_out_even.clkr.hw }, 179 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 180 }; 181 182 static const struct parent_map gcc_parent_map_1[] = { 183 { P_BI_TCXO, 0 }, 184 { P_GPLL0_OUT_MAIN, 1 }, 185 { P_GPLL6_OUT_MAIN, 2 }, 186 { P_GPLL0_OUT_EVEN, 6 }, 187 { P_CORE_BI_PLL_TEST_SE, 7 }, 188 }; 189 190 static const struct clk_parent_data gcc_parent_data_1[] = { 191 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 192 { .hw = &gpll0.clkr.hw }, 193 { .hw = &gpll6.clkr.hw }, 194 { .hw = &gpll0_out_even.clkr.hw }, 195 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 196 }; 197 198 static const struct parent_map gcc_parent_map_2[] = { 199 { P_BI_TCXO, 0 }, 200 { P_GPLL0_OUT_MAIN, 1 }, 201 { P_GPLL1_OUT_MAIN, 4 }, 202 { P_GPLL4_OUT_MAIN, 5 }, 203 { P_GPLL0_OUT_EVEN, 6 }, 204 { P_CORE_BI_PLL_TEST_SE, 7 }, 205 }; 206 207 static const struct clk_parent_data gcc_parent_data_2[] = { 208 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 209 { .hw = &gpll0.clkr.hw }, 210 { .hw = &gpll1.clkr.hw }, 211 { .hw = &gpll4.clkr.hw }, 212 { .hw = &gpll0_out_even.clkr.hw }, 213 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 214 }; 215 216 static const struct parent_map gcc_parent_map_3[] = { 217 { P_BI_TCXO, 0 }, 218 { P_GPLL0_OUT_MAIN, 1 }, 219 { P_CORE_BI_PLL_TEST_SE, 7 }, 220 }; 221 222 static const struct clk_parent_data gcc_parent_data_3[] = { 223 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 224 { .hw = &gpll0.clkr.hw }, 225 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 226 }; 227 228 static const struct parent_map gcc_parent_map_4[] = { 229 { P_BI_TCXO, 0 }, 230 { P_GPLL0_OUT_MAIN, 1 }, 231 { P_SLEEP_CLK, 5 }, 232 { P_GPLL0_OUT_EVEN, 6 }, 233 { P_CORE_BI_PLL_TEST_SE, 7 }, 234 }; 235 236 static const struct clk_parent_data gcc_parent_data_4[] = { 237 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 238 { .hw = &gpll0.clkr.hw }, 239 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 240 { .hw = &gpll0_out_even.clkr.hw }, 241 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 242 }; 243 244 static const struct parent_map gcc_parent_map_5[] = { 245 { P_BI_TCXO, 0 }, 246 { P_GPLL0_OUT_MAIN, 1 }, 247 { P_GPLL7_OUT_MAIN, 3 }, 248 { P_GPLL0_OUT_EVEN, 6 }, 249 { P_CORE_BI_PLL_TEST_SE, 7 }, 250 }; 251 252 static const struct clk_parent_data gcc_parent_data_5[] = { 253 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 254 { .hw = &gpll0.clkr.hw }, 255 { .hw = &gpll7.clkr.hw }, 256 { .hw = &gpll0_out_even.clkr.hw }, 257 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 258 }; 259 260 static const struct parent_map gcc_parent_map_6[] = { 261 { P_BI_TCXO, 0 }, 262 { P_GPLL0_OUT_MAIN, 1 }, 263 { P_SLEEP_CLK, 5 }, 264 { P_CORE_BI_PLL_TEST_SE, 7 }, 265 }; 266 267 static const struct clk_parent_data gcc_parent_data_6[] = { 268 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 269 { .hw = &gpll0.clkr.hw }, 270 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 271 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 272 }; 273 274 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { 275 F(19200000, P_BI_TCXO, 1, 0, 0), 276 { } 277 }; 278 279 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 280 .cmd_rcgr = 0x48014, 281 .mnd_width = 0, 282 .hid_width = 5, 283 .parent_map = gcc_parent_map_0, 284 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, 285 .clkr.hw.init = &(struct clk_init_data){ 286 .name = "gcc_cpuss_ahb_clk_src", 287 .parent_data = gcc_parent_data_0_ao, 288 .num_parents = 4, 289 .flags = CLK_SET_RATE_PARENT, 290 .ops = &clk_rcg2_ops, 291 }, 292 }; 293 294 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 295 F(19200000, P_BI_TCXO, 1, 0, 0), 296 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 297 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 298 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 299 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0), 300 { } 301 }; 302 303 static struct clk_rcg2 gcc_gp1_clk_src = { 304 .cmd_rcgr = 0x64004, 305 .mnd_width = 8, 306 .hid_width = 5, 307 .parent_map = gcc_parent_map_4, 308 .freq_tbl = ftbl_gcc_gp1_clk_src, 309 .clkr.hw.init = &(struct clk_init_data){ 310 .name = "gcc_gp1_clk_src", 311 .parent_data = gcc_parent_data_4, 312 .num_parents = 5, 313 .ops = &clk_rcg2_ops, 314 }, 315 }; 316 317 static struct clk_rcg2 gcc_gp2_clk_src = { 318 .cmd_rcgr = 0x65004, 319 .mnd_width = 8, 320 .hid_width = 5, 321 .parent_map = gcc_parent_map_4, 322 .freq_tbl = ftbl_gcc_gp1_clk_src, 323 .clkr.hw.init = &(struct clk_init_data){ 324 .name = "gcc_gp2_clk_src", 325 .parent_data = gcc_parent_data_4, 326 .num_parents = 5, 327 .ops = &clk_rcg2_ops, 328 }, 329 }; 330 331 static struct clk_rcg2 gcc_gp3_clk_src = { 332 .cmd_rcgr = 0x66004, 333 .mnd_width = 8, 334 .hid_width = 5, 335 .parent_map = gcc_parent_map_4, 336 .freq_tbl = ftbl_gcc_gp1_clk_src, 337 .clkr.hw.init = &(struct clk_init_data){ 338 .name = "gcc_gp3_clk_src", 339 .parent_data = gcc_parent_data_4, 340 .num_parents = 5, 341 .ops = &clk_rcg2_ops, 342 }, 343 }; 344 345 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 346 F(19200000, P_BI_TCXO, 1, 0, 0), 347 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), 348 { } 349 }; 350 351 static struct clk_rcg2 gcc_pdm2_clk_src = { 352 .cmd_rcgr = 0x33010, 353 .mnd_width = 0, 354 .hid_width = 5, 355 .parent_map = gcc_parent_map_0, 356 .freq_tbl = ftbl_gcc_pdm2_clk_src, 357 .clkr.hw.init = &(struct clk_init_data){ 358 .name = "gcc_pdm2_clk_src", 359 .parent_data = gcc_parent_data_0, 360 .num_parents = 4, 361 .ops = &clk_rcg2_ops, 362 }, 363 }; 364 365 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { 366 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 367 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 368 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 369 { } 370 }; 371 372 static struct clk_rcg2 gcc_qspi_core_clk_src = { 373 .cmd_rcgr = 0x4b00c, 374 .mnd_width = 0, 375 .hid_width = 5, 376 .parent_map = gcc_parent_map_2, 377 .freq_tbl = ftbl_gcc_qspi_core_clk_src, 378 .clkr.hw.init = &(struct clk_init_data){ 379 .name = "gcc_qspi_core_clk_src", 380 .parent_data = gcc_parent_data_2, 381 .num_parents = 6, 382 .ops = &clk_rcg2_ops, 383 }, 384 }; 385 386 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 387 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 388 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 389 F(19200000, P_BI_TCXO, 1, 0, 0), 390 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 391 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 392 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 393 F(51200000, P_GPLL6_OUT_MAIN, 7.5, 0, 0), 394 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 395 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 396 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 397 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 398 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 399 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), 400 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), 401 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), 402 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), 403 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0), 404 { } 405 }; 406 407 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 408 .name = "gcc_qupv3_wrap0_s0_clk_src", 409 .parent_data = gcc_parent_data_1, 410 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 411 .ops = &clk_rcg2_ops, 412 }; 413 414 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 415 .cmd_rcgr = 0x17034, 416 .mnd_width = 16, 417 .hid_width = 5, 418 .parent_map = gcc_parent_map_1, 419 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 420 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 421 }; 422 423 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 424 .name = "gcc_qupv3_wrap0_s1_clk_src", 425 .parent_data = gcc_parent_data_1, 426 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 427 .ops = &clk_rcg2_ops, 428 }; 429 430 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 431 .cmd_rcgr = 0x17164, 432 .mnd_width = 16, 433 .hid_width = 5, 434 .parent_map = gcc_parent_map_1, 435 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 436 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 437 }; 438 439 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 440 .name = "gcc_qupv3_wrap0_s2_clk_src", 441 .parent_data = gcc_parent_data_1, 442 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 443 .ops = &clk_rcg2_ops, 444 }; 445 446 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 447 .cmd_rcgr = 0x17294, 448 .mnd_width = 16, 449 .hid_width = 5, 450 .parent_map = gcc_parent_map_1, 451 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 452 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 453 }; 454 455 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 456 .name = "gcc_qupv3_wrap0_s3_clk_src", 457 .parent_data = gcc_parent_data_1, 458 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 459 .ops = &clk_rcg2_ops, 460 }; 461 462 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 463 .cmd_rcgr = 0x173c4, 464 .mnd_width = 16, 465 .hid_width = 5, 466 .parent_map = gcc_parent_map_1, 467 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 468 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 469 }; 470 471 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 472 .name = "gcc_qupv3_wrap0_s4_clk_src", 473 .parent_data = gcc_parent_data_1, 474 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 475 .ops = &clk_rcg2_ops, 476 }; 477 478 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 479 .cmd_rcgr = 0x174f4, 480 .mnd_width = 16, 481 .hid_width = 5, 482 .parent_map = gcc_parent_map_1, 483 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 484 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 485 }; 486 487 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 488 .name = "gcc_qupv3_wrap0_s5_clk_src", 489 .parent_data = gcc_parent_data_1, 490 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 491 .ops = &clk_rcg2_ops, 492 }; 493 494 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 495 .cmd_rcgr = 0x17624, 496 .mnd_width = 16, 497 .hid_width = 5, 498 .parent_map = gcc_parent_map_1, 499 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 500 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 501 }; 502 503 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 504 .name = "gcc_qupv3_wrap1_s0_clk_src", 505 .parent_data = gcc_parent_data_1, 506 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 507 .ops = &clk_rcg2_ops, 508 }; 509 510 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 511 .cmd_rcgr = 0x18018, 512 .mnd_width = 16, 513 .hid_width = 5, 514 .parent_map = gcc_parent_map_1, 515 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 516 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 517 }; 518 519 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 520 .name = "gcc_qupv3_wrap1_s1_clk_src", 521 .parent_data = gcc_parent_data_1, 522 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 523 .ops = &clk_rcg2_ops, 524 }; 525 526 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 527 .cmd_rcgr = 0x18148, 528 .mnd_width = 16, 529 .hid_width = 5, 530 .parent_map = gcc_parent_map_1, 531 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 532 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 533 }; 534 535 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 536 .name = "gcc_qupv3_wrap1_s2_clk_src", 537 .parent_data = gcc_parent_data_1, 538 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 539 .ops = &clk_rcg2_ops, 540 }; 541 542 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 543 .cmd_rcgr = 0x18278, 544 .mnd_width = 16, 545 .hid_width = 5, 546 .parent_map = gcc_parent_map_1, 547 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 548 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 549 }; 550 551 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 552 .name = "gcc_qupv3_wrap1_s3_clk_src", 553 .parent_data = gcc_parent_data_1, 554 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 555 .ops = &clk_rcg2_ops, 556 }; 557 558 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 559 .cmd_rcgr = 0x183a8, 560 .mnd_width = 16, 561 .hid_width = 5, 562 .parent_map = gcc_parent_map_1, 563 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 564 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 565 }; 566 567 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 568 .name = "gcc_qupv3_wrap1_s4_clk_src", 569 .parent_data = gcc_parent_data_1, 570 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 571 .ops = &clk_rcg2_ops, 572 }; 573 574 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 575 .cmd_rcgr = 0x184d8, 576 .mnd_width = 16, 577 .hid_width = 5, 578 .parent_map = gcc_parent_map_1, 579 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 580 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 581 }; 582 583 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 584 .name = "gcc_qupv3_wrap1_s5_clk_src", 585 .parent_data = gcc_parent_data_1, 586 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 587 .ops = &clk_rcg2_ops, 588 }; 589 590 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 591 .cmd_rcgr = 0x18608, 592 .mnd_width = 16, 593 .hid_width = 5, 594 .parent_map = gcc_parent_map_1, 595 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 596 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 597 }; 598 599 600 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 601 F(144000, P_BI_TCXO, 16, 3, 25), 602 F(400000, P_BI_TCXO, 12, 1, 4), 603 F(19200000, P_BI_TCXO, 1, 0, 0), 604 F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), 605 F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), 606 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 607 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 608 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 609 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 610 { } 611 }; 612 613 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 614 .cmd_rcgr = 0x12028, 615 .mnd_width = 8, 616 .hid_width = 5, 617 .parent_map = gcc_parent_map_1, 618 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 619 .clkr.hw.init = &(struct clk_init_data){ 620 .name = "gcc_sdcc1_apps_clk_src", 621 .parent_data = gcc_parent_data_1, 622 .num_parents = 5, 623 .ops = &clk_rcg2_ops, 624 }, 625 }; 626 627 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 628 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 629 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 630 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 631 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 632 { } 633 }; 634 635 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 636 .cmd_rcgr = 0x12010, 637 .mnd_width = 0, 638 .hid_width = 5, 639 .parent_map = gcc_parent_map_0, 640 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 641 .clkr.hw.init = &(struct clk_init_data){ 642 .name = "gcc_sdcc1_ice_core_clk_src", 643 .parent_data = gcc_parent_data_0, 644 .num_parents = 4, 645 .ops = &clk_rcg2_floor_ops, 646 }, 647 }; 648 649 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 650 F(400000, P_BI_TCXO, 12, 1, 4), 651 F(9600000, P_BI_TCXO, 2, 0, 0), 652 F(19200000, P_BI_TCXO, 1, 0, 0), 653 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 654 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 655 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 656 F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0), 657 { } 658 }; 659 660 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 661 .cmd_rcgr = 0x1400c, 662 .mnd_width = 8, 663 .hid_width = 5, 664 .parent_map = gcc_parent_map_5, 665 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 666 .clkr.hw.init = &(struct clk_init_data){ 667 .name = "gcc_sdcc2_apps_clk_src", 668 .parent_data = gcc_parent_data_5, 669 .num_parents = 5, 670 .ops = &clk_rcg2_floor_ops, 671 }, 672 }; 673 674 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 675 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 676 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 677 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 678 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 679 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 680 { } 681 }; 682 683 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 684 .cmd_rcgr = 0x77020, 685 .mnd_width = 8, 686 .hid_width = 5, 687 .parent_map = gcc_parent_map_0, 688 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 689 .clkr.hw.init = &(struct clk_init_data){ 690 .name = "gcc_ufs_phy_axi_clk_src", 691 .parent_data = gcc_parent_data_0, 692 .num_parents = 4, 693 .ops = &clk_rcg2_ops, 694 }, 695 }; 696 697 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 698 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 699 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 700 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 701 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 702 { } 703 }; 704 705 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 706 .cmd_rcgr = 0x77048, 707 .mnd_width = 0, 708 .hid_width = 5, 709 .parent_map = gcc_parent_map_0, 710 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 711 .clkr.hw.init = &(struct clk_init_data){ 712 .name = "gcc_ufs_phy_ice_core_clk_src", 713 .parent_data = gcc_parent_data_0, 714 .num_parents = 4, 715 .ops = &clk_rcg2_ops, 716 }, 717 }; 718 719 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 720 F(9600000, P_BI_TCXO, 2, 0, 0), 721 F(19200000, P_BI_TCXO, 1, 0, 0), 722 { } 723 }; 724 725 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 726 .cmd_rcgr = 0x77098, 727 .mnd_width = 0, 728 .hid_width = 5, 729 .parent_map = gcc_parent_map_3, 730 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 731 .clkr.hw.init = &(struct clk_init_data){ 732 .name = "gcc_ufs_phy_phy_aux_clk_src", 733 .parent_data = gcc_parent_data_3, 734 .num_parents = 3, 735 .ops = &clk_rcg2_ops, 736 }, 737 }; 738 739 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 740 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 741 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 742 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 743 { } 744 }; 745 746 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 747 .cmd_rcgr = 0x77060, 748 .mnd_width = 0, 749 .hid_width = 5, 750 .parent_map = gcc_parent_map_0, 751 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 752 .clkr.hw.init = &(struct clk_init_data){ 753 .name = "gcc_ufs_phy_unipro_core_clk_src", 754 .parent_data = gcc_parent_data_0, 755 .num_parents = 4, 756 .ops = &clk_rcg2_ops, 757 }, 758 }; 759 760 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 761 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), 762 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 763 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 764 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 765 { } 766 }; 767 768 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 769 .cmd_rcgr = 0xf01c, 770 .mnd_width = 8, 771 .hid_width = 5, 772 .parent_map = gcc_parent_map_0, 773 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 774 .clkr.hw.init = &(struct clk_init_data){ 775 .name = "gcc_usb30_prim_master_clk_src", 776 .parent_data = gcc_parent_data_0, 777 .num_parents = 4, 778 .ops = &clk_rcg2_ops, 779 }, 780 }; 781 782 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 783 F(19200000, P_BI_TCXO, 1, 0, 0), 784 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), 785 { } 786 }; 787 788 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 789 .cmd_rcgr = 0xf034, 790 .mnd_width = 0, 791 .hid_width = 5, 792 .parent_map = gcc_parent_map_0, 793 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 794 .clkr.hw.init = &(struct clk_init_data){ 795 .name = "gcc_usb30_prim_mock_utmi_clk_src", 796 .parent_data = gcc_parent_data_0, 797 .num_parents = 4, 798 .ops = &clk_rcg2_ops, 799 }, 800 }; 801 802 static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = { 803 F(19200000, P_BI_TCXO, 1, 0, 0), 804 { } 805 }; 806 807 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 808 .cmd_rcgr = 0xf060, 809 .mnd_width = 0, 810 .hid_width = 5, 811 .parent_map = gcc_parent_map_6, 812 .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src, 813 .clkr.hw.init = &(struct clk_init_data){ 814 .name = "gcc_usb3_prim_phy_aux_clk_src", 815 .parent_data = gcc_parent_data_6, 816 .num_parents = 4, 817 .ops = &clk_rcg2_ops, 818 }, 819 }; 820 821 static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = { 822 F(4800000, P_BI_TCXO, 4, 0, 0), 823 F(19200000, P_BI_TCXO, 1, 0, 0), 824 { } 825 }; 826 827 static struct clk_rcg2 gcc_sec_ctrl_clk_src = { 828 .cmd_rcgr = 0x3d030, 829 .mnd_width = 0, 830 .hid_width = 5, 831 .parent_map = gcc_parent_map_3, 832 .freq_tbl = ftbl_gcc_sec_ctrl_clk_src, 833 .clkr.hw.init = &(struct clk_init_data){ 834 .name = "gcc_sec_ctrl_clk_src", 835 .parent_data = gcc_parent_data_3, 836 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 837 .ops = &clk_rcg2_ops, 838 }, 839 }; 840 841 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 842 .halt_reg = 0x82024, 843 .halt_check = BRANCH_HALT_DELAY, 844 .hwcg_reg = 0x82024, 845 .hwcg_bit = 1, 846 .clkr = { 847 .enable_reg = 0x82024, 848 .enable_mask = BIT(0), 849 .hw.init = &(struct clk_init_data){ 850 .name = "gcc_aggre_ufs_phy_axi_clk", 851 .parent_data = &(const struct clk_parent_data){ 852 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 853 }, 854 .num_parents = 1, 855 .flags = CLK_SET_RATE_PARENT, 856 .ops = &clk_branch2_ops, 857 }, 858 }, 859 }; 860 861 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 862 .halt_reg = 0x8201c, 863 .halt_check = BRANCH_HALT, 864 .clkr = { 865 .enable_reg = 0x8201c, 866 .enable_mask = BIT(0), 867 .hw.init = &(struct clk_init_data){ 868 .name = "gcc_aggre_usb3_prim_axi_clk", 869 .parent_data = &(const struct clk_parent_data){ 870 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 871 }, 872 .num_parents = 1, 873 .flags = CLK_SET_RATE_PARENT, 874 .ops = &clk_branch2_ops, 875 }, 876 }, 877 }; 878 879 static struct clk_branch gcc_boot_rom_ahb_clk = { 880 .halt_reg = 0x38004, 881 .halt_check = BRANCH_HALT_VOTED, 882 .hwcg_reg = 0x38004, 883 .hwcg_bit = 1, 884 .clkr = { 885 .enable_reg = 0x52000, 886 .enable_mask = BIT(10), 887 .hw.init = &(struct clk_init_data){ 888 .name = "gcc_boot_rom_ahb_clk", 889 .ops = &clk_branch2_ops, 890 }, 891 }, 892 }; 893 894 static struct clk_branch gcc_camera_hf_axi_clk = { 895 .halt_reg = 0xb020, 896 .halt_check = BRANCH_HALT, 897 .clkr = { 898 .enable_reg = 0xb020, 899 .enable_mask = BIT(0), 900 .hw.init = &(struct clk_init_data){ 901 .name = "gcc_camera_hf_axi_clk", 902 .ops = &clk_branch2_ops, 903 }, 904 }, 905 }; 906 907 static struct clk_branch gcc_camera_throttle_hf_axi_clk = { 908 .halt_reg = 0xb080, 909 .halt_check = BRANCH_HALT, 910 .hwcg_reg = 0xb080, 911 .hwcg_bit = 1, 912 .clkr = { 913 .enable_reg = 0xb080, 914 .enable_mask = BIT(0), 915 .hw.init = &(struct clk_init_data){ 916 .name = "gcc_camera_throttle_hf_axi_clk", 917 .ops = &clk_branch2_ops, 918 }, 919 }, 920 }; 921 922 static struct clk_branch gcc_camera_xo_clk = { 923 .halt_reg = 0xb02c, 924 .halt_check = BRANCH_HALT, 925 .clkr = { 926 .enable_reg = 0xb02c, 927 .enable_mask = BIT(0), 928 .hw.init = &(struct clk_init_data){ 929 .name = "gcc_camera_xo_clk", 930 .ops = &clk_branch2_ops, 931 }, 932 }, 933 }; 934 935 static struct clk_branch gcc_ce1_ahb_clk = { 936 .halt_reg = 0x4100c, 937 .halt_check = BRANCH_HALT_VOTED, 938 .hwcg_reg = 0x4100c, 939 .hwcg_bit = 1, 940 .clkr = { 941 .enable_reg = 0x52000, 942 .enable_mask = BIT(3), 943 .hw.init = &(struct clk_init_data){ 944 .name = "gcc_ce1_ahb_clk", 945 .ops = &clk_branch2_ops, 946 }, 947 }, 948 }; 949 950 static struct clk_branch gcc_ce1_axi_clk = { 951 .halt_reg = 0x41008, 952 .halt_check = BRANCH_HALT_VOTED, 953 .clkr = { 954 .enable_reg = 0x52000, 955 .enable_mask = BIT(4), 956 .hw.init = &(struct clk_init_data){ 957 .name = "gcc_ce1_axi_clk", 958 .ops = &clk_branch2_ops, 959 }, 960 }, 961 }; 962 963 static struct clk_branch gcc_ce1_clk = { 964 .halt_reg = 0x41004, 965 .halt_check = BRANCH_HALT_VOTED, 966 .clkr = { 967 .enable_reg = 0x52000, 968 .enable_mask = BIT(5), 969 .hw.init = &(struct clk_init_data){ 970 .name = "gcc_ce1_clk", 971 .ops = &clk_branch2_ops, 972 }, 973 }, 974 }; 975 976 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 977 .halt_reg = 0x502c, 978 .halt_check = BRANCH_HALT, 979 .clkr = { 980 .enable_reg = 0x502c, 981 .enable_mask = BIT(0), 982 .hw.init = &(struct clk_init_data){ 983 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 984 .parent_data = &(const struct clk_parent_data){ 985 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 986 }, 987 .num_parents = 1, 988 .flags = CLK_SET_RATE_PARENT, 989 .ops = &clk_branch2_ops, 990 }, 991 }, 992 }; 993 994 /* For CPUSS functionality the AHB clock needs to be left enabled */ 995 static struct clk_branch gcc_cpuss_ahb_clk = { 996 .halt_reg = 0x48000, 997 .halt_check = BRANCH_HALT_VOTED, 998 .clkr = { 999 .enable_reg = 0x52000, 1000 .enable_mask = BIT(21), 1001 .hw.init = &(struct clk_init_data){ 1002 .name = "gcc_cpuss_ahb_clk", 1003 .parent_data = &(const struct clk_parent_data){ 1004 .hw = &gcc_cpuss_ahb_clk_src.clkr.hw, 1005 }, 1006 .num_parents = 1, 1007 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 1008 .ops = &clk_branch2_ops, 1009 }, 1010 }, 1011 }; 1012 1013 static struct clk_branch gcc_cpuss_rbcpr_clk = { 1014 .halt_reg = 0x48008, 1015 .halt_check = BRANCH_HALT, 1016 .clkr = { 1017 .enable_reg = 0x48008, 1018 .enable_mask = BIT(0), 1019 .hw.init = &(struct clk_init_data){ 1020 .name = "gcc_cpuss_rbcpr_clk", 1021 .ops = &clk_branch2_ops, 1022 }, 1023 }, 1024 }; 1025 1026 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1027 .halt_reg = 0x4452c, 1028 .halt_check = BRANCH_VOTED, 1029 .clkr = { 1030 .enable_reg = 0x4452c, 1031 .enable_mask = BIT(0), 1032 .hw.init = &(struct clk_init_data){ 1033 .name = "gcc_ddrss_gpu_axi_clk", 1034 .ops = &clk_branch2_ops, 1035 }, 1036 }, 1037 }; 1038 1039 static struct clk_branch gcc_disp_gpll0_clk_src = { 1040 .halt_check = BRANCH_HALT_DELAY, 1041 .clkr = { 1042 .enable_reg = 0x52000, 1043 .enable_mask = BIT(18), 1044 .hw.init = &(struct clk_init_data){ 1045 .name = "gcc_disp_gpll0_clk_src", 1046 .parent_data = &(const struct clk_parent_data){ 1047 .hw = &gpll0.clkr.hw, 1048 }, 1049 .num_parents = 1, 1050 .ops = &clk_branch2_aon_ops, 1051 }, 1052 }, 1053 }; 1054 1055 static struct clk_branch gcc_disp_gpll0_div_clk_src = { 1056 .halt_check = BRANCH_HALT_DELAY, 1057 .clkr = { 1058 .enable_reg = 0x52000, 1059 .enable_mask = BIT(19), 1060 .hw.init = &(struct clk_init_data){ 1061 .name = "gcc_disp_gpll0_div_clk_src", 1062 .parent_data = &(const struct clk_parent_data){ 1063 .hw = &gcc_pll0_main_div_cdiv.hw, 1064 }, 1065 .num_parents = 1, 1066 .ops = &clk_branch2_ops, 1067 }, 1068 }, 1069 }; 1070 1071 static struct clk_branch gcc_disp_hf_axi_clk = { 1072 .halt_reg = 0xb024, 1073 .halt_check = BRANCH_HALT, 1074 .clkr = { 1075 .enable_reg = 0xb024, 1076 .enable_mask = BIT(0), 1077 .hw.init = &(struct clk_init_data){ 1078 .name = "gcc_disp_hf_axi_clk", 1079 .ops = &clk_branch2_ops, 1080 }, 1081 }, 1082 }; 1083 1084 static struct clk_branch gcc_disp_throttle_hf_axi_clk = { 1085 .halt_reg = 0xb084, 1086 .halt_check = BRANCH_HALT, 1087 .hwcg_reg = 0xb084, 1088 .hwcg_bit = 1, 1089 .clkr = { 1090 .enable_reg = 0xb084, 1091 .enable_mask = BIT(0), 1092 .hw.init = &(struct clk_init_data){ 1093 .name = "gcc_disp_throttle_hf_axi_clk", 1094 .ops = &clk_branch2_ops, 1095 }, 1096 }, 1097 }; 1098 1099 static struct clk_branch gcc_disp_xo_clk = { 1100 .halt_reg = 0xb030, 1101 .halt_check = BRANCH_HALT, 1102 .clkr = { 1103 .enable_reg = 0xb030, 1104 .enable_mask = BIT(0), 1105 .hw.init = &(struct clk_init_data){ 1106 .name = "gcc_disp_xo_clk", 1107 .ops = &clk_branch2_ops, 1108 }, 1109 }, 1110 }; 1111 1112 static struct clk_branch gcc_gp1_clk = { 1113 .halt_reg = 0x64000, 1114 .halt_check = BRANCH_HALT, 1115 .clkr = { 1116 .enable_reg = 0x64000, 1117 .enable_mask = BIT(0), 1118 .hw.init = &(struct clk_init_data){ 1119 .name = "gcc_gp1_clk", 1120 .parent_data = &(const struct clk_parent_data){ 1121 .hw = &gcc_gp1_clk_src.clkr.hw, 1122 }, 1123 .num_parents = 1, 1124 .flags = CLK_SET_RATE_PARENT, 1125 .ops = &clk_branch2_ops, 1126 }, 1127 }, 1128 }; 1129 1130 static struct clk_branch gcc_gp2_clk = { 1131 .halt_reg = 0x65000, 1132 .halt_check = BRANCH_HALT, 1133 .clkr = { 1134 .enable_reg = 0x65000, 1135 .enable_mask = BIT(0), 1136 .hw.init = &(struct clk_init_data){ 1137 .name = "gcc_gp2_clk", 1138 .parent_data = &(const struct clk_parent_data){ 1139 .hw = &gcc_gp2_clk_src.clkr.hw, 1140 }, 1141 .num_parents = 1, 1142 .flags = CLK_SET_RATE_PARENT, 1143 .ops = &clk_branch2_ops, 1144 }, 1145 }, 1146 }; 1147 1148 static struct clk_branch gcc_gp3_clk = { 1149 .halt_reg = 0x66000, 1150 .halt_check = BRANCH_HALT, 1151 .clkr = { 1152 .enable_reg = 0x66000, 1153 .enable_mask = BIT(0), 1154 .hw.init = &(struct clk_init_data){ 1155 .name = "gcc_gp3_clk", 1156 .parent_data = &(const struct clk_parent_data){ 1157 .hw = &gcc_gp3_clk_src.clkr.hw, 1158 }, 1159 .num_parents = 1, 1160 .flags = CLK_SET_RATE_PARENT, 1161 .ops = &clk_branch2_ops, 1162 }, 1163 }, 1164 }; 1165 1166 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1167 .halt_check = BRANCH_HALT_DELAY, 1168 .clkr = { 1169 .enable_reg = 0x52000, 1170 .enable_mask = BIT(15), 1171 .hw.init = &(struct clk_init_data){ 1172 .name = "gcc_gpu_gpll0_clk_src", 1173 .parent_data = &(const struct clk_parent_data){ 1174 .hw = &gpll0.clkr.hw, 1175 }, 1176 .num_parents = 1, 1177 .ops = &clk_branch2_ops, 1178 }, 1179 }, 1180 }; 1181 1182 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1183 .halt_check = BRANCH_HALT_DELAY, 1184 .clkr = { 1185 .enable_reg = 0x52000, 1186 .enable_mask = BIT(16), 1187 .hw.init = &(struct clk_init_data){ 1188 .name = "gcc_gpu_gpll0_div_clk_src", 1189 .parent_data = &(const struct clk_parent_data){ 1190 .hw = &gcc_pll0_main_div_cdiv.hw, 1191 }, 1192 .num_parents = 1, 1193 .ops = &clk_branch2_ops, 1194 }, 1195 }, 1196 }; 1197 1198 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1199 .halt_reg = 0x7100c, 1200 .halt_check = BRANCH_VOTED, 1201 .clkr = { 1202 .enable_reg = 0x7100c, 1203 .enable_mask = BIT(0), 1204 .hw.init = &(struct clk_init_data){ 1205 .name = "gcc_gpu_memnoc_gfx_clk", 1206 .ops = &clk_branch2_ops, 1207 }, 1208 }, 1209 }; 1210 1211 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1212 .halt_reg = 0x71018, 1213 .halt_check = BRANCH_HALT, 1214 .clkr = { 1215 .enable_reg = 0x71018, 1216 .enable_mask = BIT(0), 1217 .hw.init = &(struct clk_init_data){ 1218 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1219 .ops = &clk_branch2_ops, 1220 }, 1221 }, 1222 }; 1223 1224 static struct clk_branch gcc_npu_axi_clk = { 1225 .halt_reg = 0x4d008, 1226 .halt_check = BRANCH_HALT, 1227 .clkr = { 1228 .enable_reg = 0x4d008, 1229 .enable_mask = BIT(0), 1230 .hw.init = &(struct clk_init_data){ 1231 .name = "gcc_npu_axi_clk", 1232 .ops = &clk_branch2_ops, 1233 }, 1234 }, 1235 }; 1236 1237 static struct clk_branch gcc_npu_bwmon_axi_clk = { 1238 .halt_reg = 0x73008, 1239 .halt_check = BRANCH_HALT, 1240 .clkr = { 1241 .enable_reg = 0x73008, 1242 .enable_mask = BIT(0), 1243 .hw.init = &(struct clk_init_data){ 1244 .name = "gcc_npu_bwmon_axi_clk", 1245 .ops = &clk_branch2_ops, 1246 }, 1247 }, 1248 }; 1249 1250 static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = { 1251 .halt_reg = 0x73018, 1252 .halt_check = BRANCH_HALT, 1253 .clkr = { 1254 .enable_reg = 0x73018, 1255 .enable_mask = BIT(0), 1256 .hw.init = &(struct clk_init_data){ 1257 .name = "gcc_npu_bwmon_dma_cfg_ahb_clk", 1258 .ops = &clk_branch2_ops, 1259 }, 1260 }, 1261 }; 1262 1263 static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = { 1264 .halt_reg = 0x7301c, 1265 .halt_check = BRANCH_HALT, 1266 .clkr = { 1267 .enable_reg = 0x7301c, 1268 .enable_mask = BIT(0), 1269 .hw.init = &(struct clk_init_data){ 1270 .name = "gcc_npu_bwmon_dsp_cfg_ahb_clk", 1271 .ops = &clk_branch2_ops, 1272 }, 1273 }, 1274 }; 1275 1276 static struct clk_branch gcc_npu_cfg_ahb_clk = { 1277 .halt_reg = 0x4d004, 1278 .halt_check = BRANCH_HALT, 1279 .hwcg_reg = 0x4d004, 1280 .hwcg_bit = 1, 1281 .clkr = { 1282 .enable_reg = 0x4d004, 1283 .enable_mask = BIT(0), 1284 .hw.init = &(struct clk_init_data){ 1285 .name = "gcc_npu_cfg_ahb_clk", 1286 .ops = &clk_branch2_ops, 1287 }, 1288 }, 1289 }; 1290 1291 static struct clk_branch gcc_npu_dma_clk = { 1292 .halt_reg = 0x4d1a0, 1293 .halt_check = BRANCH_HALT, 1294 .hwcg_reg = 0x4d1a0, 1295 .hwcg_bit = 1, 1296 .clkr = { 1297 .enable_reg = 0x4d1a0, 1298 .enable_mask = BIT(0), 1299 .hw.init = &(struct clk_init_data){ 1300 .name = "gcc_npu_dma_clk", 1301 .ops = &clk_branch2_ops, 1302 }, 1303 }, 1304 }; 1305 1306 static struct clk_branch gcc_npu_gpll0_clk_src = { 1307 .halt_check = BRANCH_HALT_DELAY, 1308 .clkr = { 1309 .enable_reg = 0x52000, 1310 .enable_mask = BIT(25), 1311 .hw.init = &(struct clk_init_data){ 1312 .name = "gcc_npu_gpll0_clk_src", 1313 .parent_data = &(const struct clk_parent_data){ 1314 .hw = &gpll0.clkr.hw, 1315 }, 1316 .num_parents = 1, 1317 .ops = &clk_branch2_ops, 1318 }, 1319 }, 1320 }; 1321 1322 static struct clk_branch gcc_npu_gpll0_div_clk_src = { 1323 .halt_check = BRANCH_HALT_DELAY, 1324 .clkr = { 1325 .enable_reg = 0x52000, 1326 .enable_mask = BIT(26), 1327 .hw.init = &(struct clk_init_data){ 1328 .name = "gcc_npu_gpll0_div_clk_src", 1329 .parent_data = &(const struct clk_parent_data){ 1330 .hw = &gcc_pll0_main_div_cdiv.hw, 1331 }, 1332 .num_parents = 1, 1333 .flags = CLK_SET_RATE_PARENT, 1334 .ops = &clk_branch2_ops, 1335 }, 1336 }, 1337 }; 1338 1339 static struct clk_branch gcc_pdm2_clk = { 1340 .halt_reg = 0x3300c, 1341 .halt_check = BRANCH_HALT, 1342 .clkr = { 1343 .enable_reg = 0x3300c, 1344 .enable_mask = BIT(0), 1345 .hw.init = &(struct clk_init_data){ 1346 .name = "gcc_pdm2_clk", 1347 .parent_data = &(const struct clk_parent_data){ 1348 .hw = &gcc_pdm2_clk_src.clkr.hw, 1349 }, 1350 .num_parents = 1, 1351 .flags = CLK_SET_RATE_PARENT, 1352 .ops = &clk_branch2_ops, 1353 }, 1354 }, 1355 }; 1356 1357 static struct clk_branch gcc_pdm_ahb_clk = { 1358 .halt_reg = 0x33004, 1359 .halt_check = BRANCH_HALT, 1360 .hwcg_reg = 0x33004, 1361 .hwcg_bit = 1, 1362 .clkr = { 1363 .enable_reg = 0x33004, 1364 .enable_mask = BIT(0), 1365 .hw.init = &(struct clk_init_data){ 1366 .name = "gcc_pdm_ahb_clk", 1367 .ops = &clk_branch2_ops, 1368 }, 1369 }, 1370 }; 1371 1372 static struct clk_branch gcc_pdm_xo4_clk = { 1373 .halt_reg = 0x33008, 1374 .halt_check = BRANCH_HALT, 1375 .clkr = { 1376 .enable_reg = 0x33008, 1377 .enable_mask = BIT(0), 1378 .hw.init = &(struct clk_init_data){ 1379 .name = "gcc_pdm_xo4_clk", 1380 .ops = &clk_branch2_ops, 1381 }, 1382 }, 1383 }; 1384 1385 static struct clk_branch gcc_prng_ahb_clk = { 1386 .halt_reg = 0x34004, 1387 .halt_check = BRANCH_HALT_VOTED, 1388 .hwcg_reg = 0x34004, 1389 .hwcg_bit = 1, 1390 .clkr = { 1391 .enable_reg = 0x52000, 1392 .enable_mask = BIT(13), 1393 .hw.init = &(struct clk_init_data){ 1394 .name = "gcc_prng_ahb_clk", 1395 .ops = &clk_branch2_ops, 1396 }, 1397 }, 1398 }; 1399 1400 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { 1401 .halt_reg = 0x4b004, 1402 .halt_check = BRANCH_HALT, 1403 .hwcg_reg = 0x4b004, 1404 .hwcg_bit = 1, 1405 .clkr = { 1406 .enable_reg = 0x4b004, 1407 .enable_mask = BIT(0), 1408 .hw.init = &(struct clk_init_data){ 1409 .name = "gcc_qspi_cnoc_periph_ahb_clk", 1410 .ops = &clk_branch2_ops, 1411 }, 1412 }, 1413 }; 1414 1415 static struct clk_branch gcc_qspi_core_clk = { 1416 .halt_reg = 0x4b008, 1417 .halt_check = BRANCH_HALT, 1418 .clkr = { 1419 .enable_reg = 0x4b008, 1420 .enable_mask = BIT(0), 1421 .hw.init = &(struct clk_init_data){ 1422 .name = "gcc_qspi_core_clk", 1423 .parent_data = &(const struct clk_parent_data){ 1424 .hw = &gcc_qspi_core_clk_src.clkr.hw, 1425 }, 1426 .num_parents = 1, 1427 .flags = CLK_SET_RATE_PARENT, 1428 .ops = &clk_branch2_ops, 1429 }, 1430 }, 1431 }; 1432 1433 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 1434 .halt_reg = 0x17014, 1435 .halt_check = BRANCH_HALT_VOTED, 1436 .clkr = { 1437 .enable_reg = 0x52008, 1438 .enable_mask = BIT(9), 1439 .hw.init = &(struct clk_init_data){ 1440 .name = "gcc_qupv3_wrap0_core_2x_clk", 1441 .ops = &clk_branch2_ops, 1442 }, 1443 }, 1444 }; 1445 1446 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 1447 .halt_reg = 0x1700c, 1448 .halt_check = BRANCH_HALT_VOTED, 1449 .clkr = { 1450 .enable_reg = 0x52008, 1451 .enable_mask = BIT(8), 1452 .hw.init = &(struct clk_init_data){ 1453 .name = "gcc_qupv3_wrap0_core_clk", 1454 .ops = &clk_branch2_ops, 1455 }, 1456 }, 1457 }; 1458 1459 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 1460 .halt_reg = 0x17030, 1461 .halt_check = BRANCH_HALT_VOTED, 1462 .clkr = { 1463 .enable_reg = 0x52008, 1464 .enable_mask = BIT(10), 1465 .hw.init = &(struct clk_init_data){ 1466 .name = "gcc_qupv3_wrap0_s0_clk", 1467 .parent_data = &(const struct clk_parent_data){ 1468 .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 1469 }, 1470 .num_parents = 1, 1471 .flags = CLK_SET_RATE_PARENT, 1472 .ops = &clk_branch2_ops, 1473 }, 1474 }, 1475 }; 1476 1477 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 1478 .halt_reg = 0x17160, 1479 .halt_check = BRANCH_HALT_VOTED, 1480 .clkr = { 1481 .enable_reg = 0x52008, 1482 .enable_mask = BIT(11), 1483 .hw.init = &(struct clk_init_data){ 1484 .name = "gcc_qupv3_wrap0_s1_clk", 1485 .parent_data = &(const struct clk_parent_data){ 1486 .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 1487 }, 1488 .num_parents = 1, 1489 .flags = CLK_SET_RATE_PARENT, 1490 .ops = &clk_branch2_ops, 1491 }, 1492 }, 1493 }; 1494 1495 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 1496 .halt_reg = 0x17290, 1497 .halt_check = BRANCH_HALT_VOTED, 1498 .clkr = { 1499 .enable_reg = 0x52008, 1500 .enable_mask = BIT(12), 1501 .hw.init = &(struct clk_init_data){ 1502 .name = "gcc_qupv3_wrap0_s2_clk", 1503 .parent_data = &(const struct clk_parent_data){ 1504 .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 1505 }, 1506 .num_parents = 1, 1507 .flags = CLK_SET_RATE_PARENT, 1508 .ops = &clk_branch2_ops, 1509 }, 1510 }, 1511 }; 1512 1513 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 1514 .halt_reg = 0x173c0, 1515 .halt_check = BRANCH_HALT_VOTED, 1516 .clkr = { 1517 .enable_reg = 0x52008, 1518 .enable_mask = BIT(13), 1519 .hw.init = &(struct clk_init_data){ 1520 .name = "gcc_qupv3_wrap0_s3_clk", 1521 .parent_data = &(const struct clk_parent_data){ 1522 .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 1523 }, 1524 .num_parents = 1, 1525 .flags = CLK_SET_RATE_PARENT, 1526 .ops = &clk_branch2_ops, 1527 }, 1528 }, 1529 }; 1530 1531 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 1532 .halt_reg = 0x174f0, 1533 .halt_check = BRANCH_HALT_VOTED, 1534 .clkr = { 1535 .enable_reg = 0x52008, 1536 .enable_mask = BIT(14), 1537 .hw.init = &(struct clk_init_data){ 1538 .name = "gcc_qupv3_wrap0_s4_clk", 1539 .parent_data = &(const struct clk_parent_data){ 1540 .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 1541 }, 1542 .num_parents = 1, 1543 .flags = CLK_SET_RATE_PARENT, 1544 .ops = &clk_branch2_ops, 1545 }, 1546 }, 1547 }; 1548 1549 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 1550 .halt_reg = 0x17620, 1551 .halt_check = BRANCH_HALT_VOTED, 1552 .clkr = { 1553 .enable_reg = 0x52008, 1554 .enable_mask = BIT(15), 1555 .hw.init = &(struct clk_init_data){ 1556 .name = "gcc_qupv3_wrap0_s5_clk", 1557 .parent_data = &(const struct clk_parent_data){ 1558 .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 1559 }, 1560 .num_parents = 1, 1561 .flags = CLK_SET_RATE_PARENT, 1562 .ops = &clk_branch2_ops, 1563 }, 1564 }, 1565 }; 1566 1567 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 1568 .halt_reg = 0x18004, 1569 .halt_check = BRANCH_HALT_VOTED, 1570 .clkr = { 1571 .enable_reg = 0x52008, 1572 .enable_mask = BIT(18), 1573 .hw.init = &(struct clk_init_data){ 1574 .name = "gcc_qupv3_wrap1_core_2x_clk", 1575 .ops = &clk_branch2_ops, 1576 }, 1577 }, 1578 }; 1579 1580 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 1581 .halt_reg = 0x18008, 1582 .halt_check = BRANCH_HALT_VOTED, 1583 .clkr = { 1584 .enable_reg = 0x52008, 1585 .enable_mask = BIT(19), 1586 .hw.init = &(struct clk_init_data){ 1587 .name = "gcc_qupv3_wrap1_core_clk", 1588 .ops = &clk_branch2_ops, 1589 }, 1590 }, 1591 }; 1592 1593 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 1594 .halt_reg = 0x18014, 1595 .halt_check = BRANCH_HALT_VOTED, 1596 .clkr = { 1597 .enable_reg = 0x52008, 1598 .enable_mask = BIT(22), 1599 .hw.init = &(struct clk_init_data){ 1600 .name = "gcc_qupv3_wrap1_s0_clk", 1601 .parent_data = &(const struct clk_parent_data){ 1602 .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 1603 }, 1604 .num_parents = 1, 1605 .flags = CLK_SET_RATE_PARENT, 1606 .ops = &clk_branch2_ops, 1607 }, 1608 }, 1609 }; 1610 1611 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 1612 .halt_reg = 0x18144, 1613 .halt_check = BRANCH_HALT_VOTED, 1614 .clkr = { 1615 .enable_reg = 0x52008, 1616 .enable_mask = BIT(23), 1617 .hw.init = &(struct clk_init_data){ 1618 .name = "gcc_qupv3_wrap1_s1_clk", 1619 .parent_data = &(const struct clk_parent_data){ 1620 .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 1621 }, 1622 .num_parents = 1, 1623 .flags = CLK_SET_RATE_PARENT, 1624 .ops = &clk_branch2_ops, 1625 }, 1626 }, 1627 }; 1628 1629 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 1630 .halt_reg = 0x18274, 1631 .halt_check = BRANCH_HALT_VOTED, 1632 .clkr = { 1633 .enable_reg = 0x52008, 1634 .enable_mask = BIT(24), 1635 .hw.init = &(struct clk_init_data){ 1636 .name = "gcc_qupv3_wrap1_s2_clk", 1637 .parent_data = &(const struct clk_parent_data){ 1638 .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 1639 }, 1640 .num_parents = 1, 1641 .flags = CLK_SET_RATE_PARENT, 1642 .ops = &clk_branch2_ops, 1643 }, 1644 }, 1645 }; 1646 1647 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 1648 .halt_reg = 0x183a4, 1649 .halt_check = BRANCH_HALT_VOTED, 1650 .clkr = { 1651 .enable_reg = 0x52008, 1652 .enable_mask = BIT(25), 1653 .hw.init = &(struct clk_init_data){ 1654 .name = "gcc_qupv3_wrap1_s3_clk", 1655 .parent_data = &(const struct clk_parent_data){ 1656 .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 1657 }, 1658 .num_parents = 1, 1659 .flags = CLK_SET_RATE_PARENT, 1660 .ops = &clk_branch2_ops, 1661 }, 1662 }, 1663 }; 1664 1665 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 1666 .halt_reg = 0x184d4, 1667 .halt_check = BRANCH_HALT_VOTED, 1668 .clkr = { 1669 .enable_reg = 0x52008, 1670 .enable_mask = BIT(26), 1671 .hw.init = &(struct clk_init_data){ 1672 .name = "gcc_qupv3_wrap1_s4_clk", 1673 .parent_data = &(const struct clk_parent_data){ 1674 .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 1675 }, 1676 .num_parents = 1, 1677 .flags = CLK_SET_RATE_PARENT, 1678 .ops = &clk_branch2_ops, 1679 }, 1680 }, 1681 }; 1682 1683 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 1684 .halt_reg = 0x18604, 1685 .halt_check = BRANCH_HALT_VOTED, 1686 .clkr = { 1687 .enable_reg = 0x52008, 1688 .enable_mask = BIT(27), 1689 .hw.init = &(struct clk_init_data){ 1690 .name = "gcc_qupv3_wrap1_s5_clk", 1691 .parent_data = &(const struct clk_parent_data){ 1692 .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 1693 }, 1694 .num_parents = 1, 1695 .flags = CLK_SET_RATE_PARENT, 1696 .ops = &clk_branch2_ops, 1697 }, 1698 }, 1699 }; 1700 1701 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 1702 .halt_reg = 0x17004, 1703 .halt_check = BRANCH_HALT_VOTED, 1704 .clkr = { 1705 .enable_reg = 0x52008, 1706 .enable_mask = BIT(6), 1707 .hw.init = &(struct clk_init_data){ 1708 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 1709 .ops = &clk_branch2_ops, 1710 }, 1711 }, 1712 }; 1713 1714 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 1715 .halt_reg = 0x17008, 1716 .halt_check = BRANCH_HALT_VOTED, 1717 .hwcg_reg = 0x17008, 1718 .hwcg_bit = 1, 1719 .clkr = { 1720 .enable_reg = 0x52008, 1721 .enable_mask = BIT(7), 1722 .hw.init = &(struct clk_init_data){ 1723 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 1724 .ops = &clk_branch2_ops, 1725 }, 1726 }, 1727 }; 1728 1729 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 1730 .halt_reg = 0x1800c, 1731 .halt_check = BRANCH_HALT_VOTED, 1732 .clkr = { 1733 .enable_reg = 0x52008, 1734 .enable_mask = BIT(20), 1735 .hw.init = &(struct clk_init_data){ 1736 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 1737 .ops = &clk_branch2_ops, 1738 }, 1739 }, 1740 }; 1741 1742 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 1743 .halt_reg = 0x18010, 1744 .halt_check = BRANCH_HALT_VOTED, 1745 .hwcg_reg = 0x18010, 1746 .hwcg_bit = 1, 1747 .clkr = { 1748 .enable_reg = 0x52008, 1749 .enable_mask = BIT(21), 1750 .hw.init = &(struct clk_init_data){ 1751 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 1752 .ops = &clk_branch2_ops, 1753 }, 1754 }, 1755 }; 1756 1757 static struct clk_branch gcc_sdcc1_ahb_clk = { 1758 .halt_reg = 0x12008, 1759 .halt_check = BRANCH_HALT, 1760 .clkr = { 1761 .enable_reg = 0x12008, 1762 .enable_mask = BIT(0), 1763 .hw.init = &(struct clk_init_data){ 1764 .name = "gcc_sdcc1_ahb_clk", 1765 .ops = &clk_branch2_ops, 1766 }, 1767 }, 1768 }; 1769 1770 static struct clk_branch gcc_sdcc1_apps_clk = { 1771 .halt_reg = 0x1200c, 1772 .halt_check = BRANCH_HALT, 1773 .clkr = { 1774 .enable_reg = 0x1200c, 1775 .enable_mask = BIT(0), 1776 .hw.init = &(struct clk_init_data){ 1777 .name = "gcc_sdcc1_apps_clk", 1778 .parent_data = &(const struct clk_parent_data){ 1779 .hw = &gcc_sdcc1_apps_clk_src.clkr.hw, 1780 }, 1781 .num_parents = 1, 1782 .flags = CLK_SET_RATE_PARENT, 1783 .ops = &clk_branch2_ops, 1784 }, 1785 }, 1786 }; 1787 1788 static struct clk_branch gcc_sdcc1_ice_core_clk = { 1789 .halt_reg = 0x12040, 1790 .halt_check = BRANCH_HALT, 1791 .clkr = { 1792 .enable_reg = 0x12040, 1793 .enable_mask = BIT(0), 1794 .hw.init = &(struct clk_init_data){ 1795 .name = "gcc_sdcc1_ice_core_clk", 1796 .parent_data = &(const struct clk_parent_data){ 1797 .hw = &gcc_sdcc1_ice_core_clk_src.clkr.hw, 1798 }, 1799 .num_parents = 1, 1800 .flags = CLK_SET_RATE_PARENT, 1801 .ops = &clk_branch2_ops, 1802 }, 1803 }, 1804 }; 1805 1806 static struct clk_branch gcc_sdcc2_ahb_clk = { 1807 .halt_reg = 0x14008, 1808 .halt_check = BRANCH_HALT, 1809 .clkr = { 1810 .enable_reg = 0x14008, 1811 .enable_mask = BIT(0), 1812 .hw.init = &(struct clk_init_data){ 1813 .name = "gcc_sdcc2_ahb_clk", 1814 .ops = &clk_branch2_ops, 1815 }, 1816 }, 1817 }; 1818 1819 static struct clk_branch gcc_sdcc2_apps_clk = { 1820 .halt_reg = 0x14004, 1821 .halt_check = BRANCH_HALT, 1822 .clkr = { 1823 .enable_reg = 0x14004, 1824 .enable_mask = BIT(0), 1825 .hw.init = &(struct clk_init_data){ 1826 .name = "gcc_sdcc2_apps_clk", 1827 .parent_data = &(const struct clk_parent_data){ 1828 .hw = &gcc_sdcc2_apps_clk_src.clkr.hw, 1829 }, 1830 .num_parents = 1, 1831 .flags = CLK_SET_RATE_PARENT, 1832 .ops = &clk_branch2_ops, 1833 }, 1834 }, 1835 }; 1836 1837 /* For CPUSS functionality the SYS NOC clock needs to be left enabled */ 1838 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 1839 .halt_reg = 0x4144, 1840 .halt_check = BRANCH_HALT_VOTED, 1841 .clkr = { 1842 .enable_reg = 0x52000, 1843 .enable_mask = BIT(0), 1844 .hw.init = &(struct clk_init_data){ 1845 .name = "gcc_sys_noc_cpuss_ahb_clk", 1846 .parent_data = &(const struct clk_parent_data){ 1847 .hw = &gcc_cpuss_ahb_clk_src.clkr.hw, 1848 }, 1849 .num_parents = 1, 1850 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 1851 .ops = &clk_branch2_ops, 1852 }, 1853 }, 1854 }; 1855 1856 static struct clk_branch gcc_ufs_mem_clkref_clk = { 1857 .halt_reg = 0x8c000, 1858 .halt_check = BRANCH_HALT, 1859 .clkr = { 1860 .enable_reg = 0x8c000, 1861 .enable_mask = BIT(0), 1862 .hw.init = &(struct clk_init_data){ 1863 .name = "gcc_ufs_mem_clkref_clk", 1864 .ops = &clk_branch2_ops, 1865 }, 1866 }, 1867 }; 1868 1869 static struct clk_branch gcc_ufs_phy_ahb_clk = { 1870 .halt_reg = 0x77014, 1871 .halt_check = BRANCH_HALT, 1872 .hwcg_reg = 0x77014, 1873 .hwcg_bit = 1, 1874 .clkr = { 1875 .enable_reg = 0x77014, 1876 .enable_mask = BIT(0), 1877 .hw.init = &(struct clk_init_data){ 1878 .name = "gcc_ufs_phy_ahb_clk", 1879 .ops = &clk_branch2_ops, 1880 }, 1881 }, 1882 }; 1883 1884 static struct clk_branch gcc_ufs_phy_axi_clk = { 1885 .halt_reg = 0x77038, 1886 .halt_check = BRANCH_HALT, 1887 .hwcg_reg = 0x77038, 1888 .hwcg_bit = 1, 1889 .clkr = { 1890 .enable_reg = 0x77038, 1891 .enable_mask = BIT(0), 1892 .hw.init = &(struct clk_init_data){ 1893 .name = "gcc_ufs_phy_axi_clk", 1894 .parent_data = &(const struct clk_parent_data){ 1895 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 1896 }, 1897 .num_parents = 1, 1898 .flags = CLK_SET_RATE_PARENT, 1899 .ops = &clk_branch2_ops, 1900 }, 1901 }, 1902 }; 1903 1904 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 1905 .halt_reg = 0x77090, 1906 .halt_check = BRANCH_HALT, 1907 .hwcg_reg = 0x77090, 1908 .hwcg_bit = 1, 1909 .clkr = { 1910 .enable_reg = 0x77090, 1911 .enable_mask = BIT(0), 1912 .hw.init = &(struct clk_init_data){ 1913 .name = "gcc_ufs_phy_ice_core_clk", 1914 .parent_data = &(const struct clk_parent_data){ 1915 .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 1916 }, 1917 .num_parents = 1, 1918 .flags = CLK_SET_RATE_PARENT, 1919 .ops = &clk_branch2_ops, 1920 }, 1921 }, 1922 }; 1923 1924 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 1925 .halt_reg = 0x77094, 1926 .halt_check = BRANCH_HALT, 1927 .hwcg_reg = 0x77094, 1928 .hwcg_bit = 1, 1929 .clkr = { 1930 .enable_reg = 0x77094, 1931 .enable_mask = BIT(0), 1932 .hw.init = &(struct clk_init_data){ 1933 .name = "gcc_ufs_phy_phy_aux_clk", 1934 .parent_data = &(const struct clk_parent_data){ 1935 .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 1936 }, 1937 .num_parents = 1, 1938 .flags = CLK_SET_RATE_PARENT, 1939 .ops = &clk_branch2_ops, 1940 }, 1941 }, 1942 }; 1943 1944 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 1945 .halt_reg = 0x7701c, 1946 .halt_check = BRANCH_HALT_SKIP, 1947 .clkr = { 1948 .enable_reg = 0x7701c, 1949 .enable_mask = BIT(0), 1950 .hw.init = &(struct clk_init_data){ 1951 .name = "gcc_ufs_phy_rx_symbol_0_clk", 1952 .ops = &clk_branch2_ops, 1953 }, 1954 }, 1955 }; 1956 1957 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 1958 .halt_reg = 0x77018, 1959 .halt_check = BRANCH_HALT_SKIP, 1960 .clkr = { 1961 .enable_reg = 0x77018, 1962 .enable_mask = BIT(0), 1963 .hw.init = &(struct clk_init_data){ 1964 .name = "gcc_ufs_phy_tx_symbol_0_clk", 1965 .ops = &clk_branch2_ops, 1966 }, 1967 }, 1968 }; 1969 1970 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 1971 .halt_reg = 0x7708c, 1972 .halt_check = BRANCH_HALT, 1973 .hwcg_reg = 0x7708c, 1974 .hwcg_bit = 1, 1975 .clkr = { 1976 .enable_reg = 0x7708c, 1977 .enable_mask = BIT(0), 1978 .hw.init = &(struct clk_init_data){ 1979 .name = "gcc_ufs_phy_unipro_core_clk", 1980 .parent_data = &(const struct clk_parent_data){ 1981 .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 1982 }, 1983 .num_parents = 1, 1984 .flags = CLK_SET_RATE_PARENT, 1985 .ops = &clk_branch2_ops, 1986 }, 1987 }, 1988 }; 1989 1990 static struct clk_branch gcc_usb30_prim_master_clk = { 1991 .halt_reg = 0xf010, 1992 .halt_check = BRANCH_HALT, 1993 .clkr = { 1994 .enable_reg = 0xf010, 1995 .enable_mask = BIT(0), 1996 .hw.init = &(struct clk_init_data){ 1997 .name = "gcc_usb30_prim_master_clk", 1998 .parent_data = &(const struct clk_parent_data){ 1999 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 2000 }, 2001 .num_parents = 1, 2002 .flags = CLK_SET_RATE_PARENT, 2003 .ops = &clk_branch2_ops, 2004 }, 2005 }, 2006 }; 2007 2008 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2009 .halt_reg = 0xf018, 2010 .halt_check = BRANCH_HALT, 2011 .clkr = { 2012 .enable_reg = 0xf018, 2013 .enable_mask = BIT(0), 2014 .hw.init = &(struct clk_init_data){ 2015 .name = "gcc_usb30_prim_mock_utmi_clk", 2016 .parent_data = &(const struct clk_parent_data){ 2017 .hw = 2018 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 2019 }, 2020 .num_parents = 1, 2021 .flags = CLK_SET_RATE_PARENT, 2022 .ops = &clk_branch2_ops, 2023 }, 2024 }, 2025 }; 2026 2027 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2028 .halt_reg = 0xf014, 2029 .halt_check = BRANCH_HALT, 2030 .clkr = { 2031 .enable_reg = 0xf014, 2032 .enable_mask = BIT(0), 2033 .hw.init = &(struct clk_init_data){ 2034 .name = "gcc_usb30_prim_sleep_clk", 2035 .ops = &clk_branch2_ops, 2036 }, 2037 }, 2038 }; 2039 2040 static struct clk_branch gcc_usb3_prim_clkref_clk = { 2041 .halt_reg = 0x8c010, 2042 .halt_check = BRANCH_HALT, 2043 .clkr = { 2044 .enable_reg = 0x8c010, 2045 .enable_mask = BIT(0), 2046 .hw.init = &(struct clk_init_data){ 2047 .name = "gcc_usb3_prim_clkref_clk", 2048 .ops = &clk_branch2_ops, 2049 }, 2050 }, 2051 }; 2052 2053 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2054 .halt_reg = 0xf050, 2055 .halt_check = BRANCH_HALT, 2056 .clkr = { 2057 .enable_reg = 0xf050, 2058 .enable_mask = BIT(0), 2059 .hw.init = &(struct clk_init_data){ 2060 .name = "gcc_usb3_prim_phy_aux_clk", 2061 .parent_data = &(const struct clk_parent_data){ 2062 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2063 }, 2064 .num_parents = 1, 2065 .flags = CLK_SET_RATE_PARENT, 2066 .ops = &clk_branch2_ops, 2067 }, 2068 }, 2069 }; 2070 2071 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2072 .halt_reg = 0xf054, 2073 .halt_check = BRANCH_HALT, 2074 .clkr = { 2075 .enable_reg = 0xf054, 2076 .enable_mask = BIT(0), 2077 .hw.init = &(struct clk_init_data){ 2078 .name = "gcc_usb3_prim_phy_com_aux_clk", 2079 .parent_data = &(const struct clk_parent_data){ 2080 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2081 }, 2082 .num_parents = 1, 2083 .flags = CLK_SET_RATE_PARENT, 2084 .ops = &clk_branch2_ops, 2085 }, 2086 }, 2087 }; 2088 2089 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2090 .halt_reg = 0xf058, 2091 .halt_check = BRANCH_HALT_SKIP, 2092 .clkr = { 2093 .enable_reg = 0xf058, 2094 .enable_mask = BIT(0), 2095 .hw.init = &(struct clk_init_data){ 2096 .name = "gcc_usb3_prim_phy_pipe_clk", 2097 .ops = &clk_branch2_ops, 2098 }, 2099 }, 2100 }; 2101 2102 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 2103 .halt_reg = 0x6a004, 2104 .halt_check = BRANCH_HALT, 2105 .hwcg_reg = 0x6a004, 2106 .hwcg_bit = 1, 2107 .clkr = { 2108 .enable_reg = 0x6a004, 2109 .enable_mask = BIT(0), 2110 .hw.init = &(struct clk_init_data){ 2111 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2112 .ops = &clk_branch2_ops, 2113 }, 2114 }, 2115 }; 2116 2117 static struct clk_branch gcc_video_axi_clk = { 2118 .halt_reg = 0xb01c, 2119 .halt_check = BRANCH_HALT, 2120 .clkr = { 2121 .enable_reg = 0xb01c, 2122 .enable_mask = BIT(0), 2123 .hw.init = &(struct clk_init_data){ 2124 .name = "gcc_video_axi_clk", 2125 .ops = &clk_branch2_ops, 2126 }, 2127 }, 2128 }; 2129 2130 static struct clk_branch gcc_video_gpll0_div_clk_src = { 2131 .halt_check = BRANCH_HALT_DELAY, 2132 .clkr = { 2133 .enable_reg = 0x52000, 2134 .enable_mask = BIT(20), 2135 .hw.init = &(struct clk_init_data){ 2136 .name = "gcc_video_gpll0_div_clk_src", 2137 .parent_data = &(const struct clk_parent_data){ 2138 .hw = &gcc_pll0_main_div_cdiv.hw, 2139 }, 2140 .num_parents = 1, 2141 .flags = CLK_SET_RATE_PARENT, 2142 .ops = &clk_branch2_ops, 2143 }, 2144 }, 2145 }; 2146 2147 static struct clk_branch gcc_video_throttle_axi_clk = { 2148 .halt_reg = 0xb07c, 2149 .halt_check = BRANCH_HALT, 2150 .hwcg_reg = 0xb07c, 2151 .hwcg_bit = 1, 2152 .clkr = { 2153 .enable_reg = 0xb07c, 2154 .enable_mask = BIT(0), 2155 .hw.init = &(struct clk_init_data){ 2156 .name = "gcc_video_throttle_axi_clk", 2157 .ops = &clk_branch2_ops, 2158 }, 2159 }, 2160 }; 2161 2162 static struct clk_branch gcc_video_xo_clk = { 2163 .halt_reg = 0xb028, 2164 .halt_check = BRANCH_HALT, 2165 .clkr = { 2166 .enable_reg = 0xb028, 2167 .enable_mask = BIT(0), 2168 .hw.init = &(struct clk_init_data){ 2169 .name = "gcc_video_xo_clk", 2170 .ops = &clk_branch2_ops, 2171 }, 2172 }, 2173 }; 2174 2175 static struct clk_branch gcc_mss_cfg_ahb_clk = { 2176 .halt_reg = 0x8a000, 2177 .halt_check = BRANCH_HALT, 2178 .clkr = { 2179 .enable_reg = 0x8a000, 2180 .enable_mask = BIT(0), 2181 .hw.init = &(struct clk_init_data){ 2182 .name = "gcc_mss_cfg_ahb_clk", 2183 .ops = &clk_branch2_ops, 2184 }, 2185 }, 2186 }; 2187 2188 static struct clk_branch gcc_mss_mfab_axis_clk = { 2189 .halt_reg = 0x8a004, 2190 .halt_check = BRANCH_HALT_VOTED, 2191 .clkr = { 2192 .enable_reg = 0x8a004, 2193 .enable_mask = BIT(0), 2194 .hw.init = &(struct clk_init_data){ 2195 .name = "gcc_mss_mfab_axis_clk", 2196 .ops = &clk_branch2_ops, 2197 }, 2198 }, 2199 }; 2200 2201 static struct clk_branch gcc_mss_nav_axi_clk = { 2202 .halt_reg = 0x8a00c, 2203 .halt_check = BRANCH_HALT_VOTED, 2204 .clkr = { 2205 .enable_reg = 0x8a00c, 2206 .enable_mask = BIT(0), 2207 .hw.init = &(struct clk_init_data){ 2208 .name = "gcc_mss_nav_axi_clk", 2209 .ops = &clk_branch2_ops, 2210 }, 2211 }, 2212 }; 2213 2214 static struct clk_branch gcc_mss_snoc_axi_clk = { 2215 .halt_reg = 0x8a150, 2216 .halt_check = BRANCH_HALT, 2217 .clkr = { 2218 .enable_reg = 0x8a150, 2219 .enable_mask = BIT(0), 2220 .hw.init = &(struct clk_init_data){ 2221 .name = "gcc_mss_snoc_axi_clk", 2222 .ops = &clk_branch2_ops, 2223 }, 2224 }, 2225 }; 2226 2227 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = { 2228 .halt_reg = 0x8a154, 2229 .halt_check = BRANCH_HALT, 2230 .clkr = { 2231 .enable_reg = 0x8a154, 2232 .enable_mask = BIT(0), 2233 .hw.init = &(struct clk_init_data){ 2234 .name = "gcc_mss_q6_memnoc_axi_clk", 2235 .ops = &clk_branch2_ops, 2236 }, 2237 }, 2238 }; 2239 2240 static struct clk_branch gcc_lpass_cfg_noc_sway_clk = { 2241 .halt_reg = 0x47018, 2242 .halt_check = BRANCH_HALT_DELAY, 2243 .clkr = { 2244 .enable_reg = 0x47018, 2245 .enable_mask = BIT(0), 2246 .hw.init = &(struct clk_init_data){ 2247 .name = "gcc_lpass_cfg_noc_sway_clk", 2248 .ops = &clk_branch2_ops, 2249 }, 2250 }, 2251 }; 2252 2253 static struct gdsc ufs_phy_gdsc = { 2254 .gdscr = 0x77004, 2255 .pd = { 2256 .name = "ufs_phy_gdsc", 2257 }, 2258 .pwrsts = PWRSTS_OFF_ON, 2259 }; 2260 2261 static struct gdsc usb30_prim_gdsc = { 2262 .gdscr = 0x0f004, 2263 .pd = { 2264 .name = "usb30_prim_gdsc", 2265 }, 2266 .pwrsts = PWRSTS_OFF_ON, 2267 }; 2268 2269 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { 2270 .gdscr = 0x7d040, 2271 .pd = { 2272 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", 2273 }, 2274 .pwrsts = PWRSTS_OFF_ON, 2275 .flags = VOTABLE, 2276 }; 2277 2278 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = { 2279 .gdscr = 0x7d044, 2280 .pd = { 2281 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc", 2282 }, 2283 .pwrsts = PWRSTS_OFF_ON, 2284 .flags = VOTABLE, 2285 }; 2286 2287 static struct gdsc *gcc_sc7180_gdscs[] = { 2288 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 2289 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 2290 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = 2291 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, 2292 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = 2293 &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc, 2294 }; 2295 2296 2297 static struct clk_hw *gcc_sc7180_hws[] = { 2298 [GCC_GPLL0_MAIN_DIV_CDIV] = &gcc_pll0_main_div_cdiv.hw, 2299 }; 2300 2301 static struct clk_regmap *gcc_sc7180_clocks[] = { 2302 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 2303 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 2304 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2305 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 2306 [GCC_CAMERA_THROTTLE_HF_AXI_CLK] = &gcc_camera_throttle_hf_axi_clk.clkr, 2307 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 2308 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, 2309 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, 2310 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, 2311 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2312 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, 2313 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, 2314 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, 2315 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 2316 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 2317 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 2318 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 2319 [GCC_DISP_THROTTLE_HF_AXI_CLK] = &gcc_disp_throttle_hf_axi_clk.clkr, 2320 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 2321 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2322 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2323 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2324 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2325 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2326 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2327 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 2328 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 2329 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 2330 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 2331 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, 2332 [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr, 2333 [GCC_NPU_BWMON_DMA_CFG_AHB_CLK] = &gcc_npu_bwmon_dma_cfg_ahb_clk.clkr, 2334 [GCC_NPU_BWMON_DSP_CFG_AHB_CLK] = &gcc_npu_bwmon_dsp_cfg_ahb_clk.clkr, 2335 [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr, 2336 [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr, 2337 [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr, 2338 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr, 2339 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2340 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 2341 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2342 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2343 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2344 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, 2345 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, 2346 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, 2347 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 2348 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 2349 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 2350 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 2351 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 2352 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 2353 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 2354 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 2355 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 2356 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 2357 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 2358 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 2359 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 2360 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 2361 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 2362 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 2363 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 2364 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 2365 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 2366 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 2367 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 2368 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 2369 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 2370 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 2371 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 2372 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 2373 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 2374 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 2375 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 2376 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 2377 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 2378 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 2379 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2380 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2381 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 2382 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 2383 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 2384 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2385 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2386 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 2387 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 2388 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, 2389 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 2390 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 2391 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 2392 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 2393 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 2394 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 2395 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 2396 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 2397 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 2398 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 2399 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 2400 &gcc_ufs_phy_unipro_core_clk_src.clkr, 2401 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 2402 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 2403 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 2404 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 2405 &gcc_usb30_prim_mock_utmi_clk_src.clkr, 2406 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 2407 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 2408 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 2409 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 2410 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 2411 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 2412 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 2413 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr, 2414 [GCC_VIDEO_GPLL0_DIV_CLK_SRC] = &gcc_video_gpll0_div_clk_src.clkr, 2415 [GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr, 2416 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 2417 [GPLL0] = &gpll0.clkr, 2418 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 2419 [GPLL6] = &gpll6.clkr, 2420 [GPLL7] = &gpll7.clkr, 2421 [GPLL4] = &gpll4.clkr, 2422 [GPLL1] = &gpll1.clkr, 2423 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 2424 [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr, 2425 [GCC_MSS_NAV_AXI_CLK] = &gcc_mss_nav_axi_clk.clkr, 2426 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr, 2427 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, 2428 [GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr, 2429 [GCC_LPASS_CFG_NOC_SWAY_CLK] = &gcc_lpass_cfg_noc_sway_clk.clkr, 2430 }; 2431 2432 static const struct qcom_reset_map gcc_sc7180_resets[] = { 2433 [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 }, 2434 [GCC_QUSB2PHY_SEC_BCR] = { 0x26004 }, 2435 [GCC_UFS_PHY_BCR] = { 0x77000 }, 2436 [GCC_USB30_PRIM_BCR] = { 0xf000 }, 2437 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 2438 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 2439 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 2440 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 2441 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 2442 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 2443 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 2444 }; 2445 2446 static struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 2447 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 2448 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 2449 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 2450 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 2451 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 2452 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 2453 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 2454 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 2455 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 2456 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 2457 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 2458 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 2459 }; 2460 2461 static const struct regmap_config gcc_sc7180_regmap_config = { 2462 .reg_bits = 32, 2463 .reg_stride = 4, 2464 .val_bits = 32, 2465 .max_register = 0x18208c, 2466 .fast_io = true, 2467 }; 2468 2469 static const struct qcom_cc_desc gcc_sc7180_desc = { 2470 .config = &gcc_sc7180_regmap_config, 2471 .clk_hws = gcc_sc7180_hws, 2472 .num_clk_hws = ARRAY_SIZE(gcc_sc7180_hws), 2473 .clks = gcc_sc7180_clocks, 2474 .num_clks = ARRAY_SIZE(gcc_sc7180_clocks), 2475 .resets = gcc_sc7180_resets, 2476 .num_resets = ARRAY_SIZE(gcc_sc7180_resets), 2477 .gdscs = gcc_sc7180_gdscs, 2478 .num_gdscs = ARRAY_SIZE(gcc_sc7180_gdscs), 2479 }; 2480 2481 static const struct of_device_id gcc_sc7180_match_table[] = { 2482 { .compatible = "qcom,gcc-sc7180" }, 2483 { } 2484 }; 2485 MODULE_DEVICE_TABLE(of, gcc_sc7180_match_table); 2486 2487 static int gcc_sc7180_probe(struct platform_device *pdev) 2488 { 2489 struct regmap *regmap; 2490 int ret; 2491 2492 regmap = qcom_cc_map(pdev, &gcc_sc7180_desc); 2493 if (IS_ERR(regmap)) 2494 return PTR_ERR(regmap); 2495 2496 /* 2497 * Disable the GPLL0 active input to MM blocks, NPU 2498 * and GPU via MISC registers. 2499 */ 2500 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); 2501 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); 2502 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 2503 2504 /* 2505 * Keep the clocks always-ON 2506 * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, 2507 * GCC_DISP_AHB_CLK, GCC_GPU_CFG_AHB_CLK 2508 */ 2509 regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); 2510 regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); 2511 regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); 2512 regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); 2513 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 2514 2515 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 2516 ARRAY_SIZE(gcc_dfs_clocks)); 2517 if (ret) 2518 return ret; 2519 2520 return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap); 2521 } 2522 2523 static struct platform_driver gcc_sc7180_driver = { 2524 .probe = gcc_sc7180_probe, 2525 .driver = { 2526 .name = "gcc-sc7180", 2527 .of_match_table = gcc_sc7180_match_table, 2528 }, 2529 }; 2530 2531 static int __init gcc_sc7180_init(void) 2532 { 2533 return platform_driver_register(&gcc_sc7180_driver); 2534 } 2535 core_initcall(gcc_sc7180_init); 2536 2537 static void __exit gcc_sc7180_exit(void) 2538 { 2539 platform_driver_unregister(&gcc_sc7180_driver); 2540 } 2541 module_exit(gcc_sc7180_exit); 2542 2543 MODULE_DESCRIPTION("QTI GCC SC7180 Driver"); 2544 MODULE_LICENSE("GPL v2"); 2545