1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2023, Linaro Limited 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/err.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 16 #include <dt-bindings/clock/qcom,sa8775p-gcc.h> 17 18 #include "clk-alpha-pll.h" 19 #include "clk-branch.h" 20 #include "clk-rcg.h" 21 #include "clk-regmap.h" 22 #include "clk-regmap-divider.h" 23 #include "clk-regmap-mux.h" 24 #include "clk-regmap-phy-mux.h" 25 #include "common.h" 26 #include "gdsc.h" 27 #include "reset.h" 28 29 /* Need to match the order of clocks in DT binding */ 30 enum { 31 DT_BI_TCXO, 32 DT_SLEEP_CLK, 33 DT_UFS_PHY_RX_SYMBOL_0_CLK, 34 DT_UFS_PHY_RX_SYMBOL_1_CLK, 35 DT_UFS_PHY_TX_SYMBOL_0_CLK, 36 DT_UFS_CARD_RX_SYMBOL_0_CLK, 37 DT_UFS_CARD_RX_SYMBOL_1_CLK, 38 DT_UFS_CARD_TX_SYMBOL_0_CLK, 39 DT_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK, 40 DT_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK, 41 DT_PCIE_0_PIPE_CLK, 42 DT_PCIE_1_PIPE_CLK, 43 DT_PCIE_PHY_AUX_CLK, 44 DT_RXC0_REF_CLK, 45 DT_RXC1_REF_CLK, 46 }; 47 48 enum { 49 P_BI_TCXO, 50 P_GCC_GPLL0_OUT_EVEN, 51 P_GCC_GPLL0_OUT_MAIN, 52 P_GCC_GPLL1_OUT_MAIN, 53 P_GCC_GPLL4_OUT_MAIN, 54 P_GCC_GPLL5_OUT_MAIN, 55 P_GCC_GPLL7_OUT_MAIN, 56 P_GCC_GPLL9_OUT_MAIN, 57 P_PCIE_0_PIPE_CLK, 58 P_PCIE_1_PIPE_CLK, 59 P_PCIE_PHY_AUX_CLK, 60 P_RXC0_REF_CLK, 61 P_RXC1_REF_CLK, 62 P_SLEEP_CLK, 63 P_UFS_CARD_RX_SYMBOL_0_CLK, 64 P_UFS_CARD_RX_SYMBOL_1_CLK, 65 P_UFS_CARD_TX_SYMBOL_0_CLK, 66 P_UFS_PHY_RX_SYMBOL_0_CLK, 67 P_UFS_PHY_RX_SYMBOL_1_CLK, 68 P_UFS_PHY_TX_SYMBOL_0_CLK, 69 P_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK, 70 P_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK, 71 }; 72 73 static const struct clk_parent_data gcc_parent_data_tcxo = { .index = DT_BI_TCXO }; 74 75 static struct clk_alpha_pll gcc_gpll0 = { 76 .offset = 0x0, 77 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 78 .clkr = { 79 .enable_reg = 0x4b028, 80 .enable_mask = BIT(0), 81 .hw.init = &(const struct clk_init_data){ 82 .name = "gcc_gpll0", 83 .parent_data = &gcc_parent_data_tcxo, 84 .num_parents = 1, 85 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 86 }, 87 }, 88 }; 89 90 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 91 { 0x1, 2 }, 92 { } 93 }; 94 95 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 96 .offset = 0x0, 97 .post_div_shift = 10, 98 .post_div_table = post_div_table_gcc_gpll0_out_even, 99 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 100 .width = 4, 101 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 102 .clkr.hw.init = &(const struct clk_init_data){ 103 .name = "gcc_gpll0_out_even", 104 .parent_hws = (const struct clk_hw*[]){ 105 &gcc_gpll0.clkr.hw, 106 }, 107 .num_parents = 1, 108 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 109 }, 110 }; 111 112 static struct clk_alpha_pll gcc_gpll1 = { 113 .offset = 0x1000, 114 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 115 .clkr = { 116 .enable_reg = 0x4b028, 117 .enable_mask = BIT(1), 118 .hw.init = &(const struct clk_init_data){ 119 .name = "gcc_gpll1", 120 .parent_data = &gcc_parent_data_tcxo, 121 .num_parents = 1, 122 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 123 }, 124 }, 125 }; 126 127 static struct clk_alpha_pll gcc_gpll4 = { 128 .offset = 0x4000, 129 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 130 .clkr = { 131 .enable_reg = 0x4b028, 132 .enable_mask = BIT(4), 133 .hw.init = &(const struct clk_init_data){ 134 .name = "gcc_gpll4", 135 .parent_data = &gcc_parent_data_tcxo, 136 .num_parents = 1, 137 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 138 }, 139 }, 140 }; 141 142 static struct clk_alpha_pll gcc_gpll5 = { 143 .offset = 0x5000, 144 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 145 .clkr = { 146 .enable_reg = 0x4b028, 147 .enable_mask = BIT(5), 148 .hw.init = &(const struct clk_init_data){ 149 .name = "gcc_gpll5", 150 .parent_data = &gcc_parent_data_tcxo, 151 .num_parents = 1, 152 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 153 }, 154 }, 155 }; 156 157 static struct clk_alpha_pll gcc_gpll7 = { 158 .offset = 0x7000, 159 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 160 .clkr = { 161 .enable_reg = 0x4b028, 162 .enable_mask = BIT(7), 163 .hw.init = &(const struct clk_init_data){ 164 .name = "gcc_gpll7", 165 .parent_data = &gcc_parent_data_tcxo, 166 .num_parents = 1, 167 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 168 }, 169 }, 170 }; 171 172 static struct clk_alpha_pll gcc_gpll9 = { 173 .offset = 0x9000, 174 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 175 .clkr = { 176 .enable_reg = 0x4b028, 177 .enable_mask = BIT(9), 178 .hw.init = &(const struct clk_init_data){ 179 .name = "gcc_gpll9", 180 .parent_data = &gcc_parent_data_tcxo, 181 .num_parents = 1, 182 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 183 }, 184 }, 185 }; 186 187 static const struct parent_map gcc_parent_map_0[] = { 188 { P_BI_TCXO, 0 }, 189 { P_GCC_GPLL0_OUT_MAIN, 1 }, 190 { P_GCC_GPLL0_OUT_EVEN, 6 }, 191 }; 192 193 static const struct clk_parent_data gcc_parent_data_0[] = { 194 { .index = DT_BI_TCXO }, 195 { .hw = &gcc_gpll0.clkr.hw }, 196 { .hw = &gcc_gpll0_out_even.clkr.hw }, 197 }; 198 199 static const struct parent_map gcc_parent_map_1[] = { 200 { P_BI_TCXO, 0 }, 201 { P_GCC_GPLL0_OUT_MAIN, 1 }, 202 { P_GCC_GPLL4_OUT_MAIN, 5 }, 203 { P_GCC_GPLL0_OUT_EVEN, 6 }, 204 }; 205 206 static const struct clk_parent_data gcc_parent_data_1[] = { 207 { .index = DT_BI_TCXO }, 208 { .hw = &gcc_gpll0.clkr.hw }, 209 { .hw = &gcc_gpll4.clkr.hw }, 210 { .hw = &gcc_gpll0_out_even.clkr.hw }, 211 }; 212 213 static const struct parent_map gcc_parent_map_2[] = { 214 { P_BI_TCXO, 0 }, 215 { P_GCC_GPLL0_OUT_MAIN, 1 }, 216 { P_SLEEP_CLK, 5 }, 217 { P_GCC_GPLL0_OUT_EVEN, 6 }, 218 }; 219 220 static const struct clk_parent_data gcc_parent_data_2[] = { 221 { .index = DT_BI_TCXO }, 222 { .hw = &gcc_gpll0.clkr.hw }, 223 { .index = DT_SLEEP_CLK }, 224 { .hw = &gcc_gpll0_out_even.clkr.hw }, 225 }; 226 227 static const struct parent_map gcc_parent_map_3[] = { 228 { P_BI_TCXO, 0 }, 229 { P_SLEEP_CLK, 5 }, 230 }; 231 232 static const struct clk_parent_data gcc_parent_data_3[] = { 233 { .index = DT_BI_TCXO }, 234 { .index = DT_SLEEP_CLK }, 235 }; 236 237 static const struct parent_map gcc_parent_map_4[] = { 238 { P_BI_TCXO, 0 }, 239 { P_GCC_GPLL0_OUT_MAIN, 1 }, 240 { P_GCC_GPLL1_OUT_MAIN, 4 }, 241 { P_GCC_GPLL4_OUT_MAIN, 5 }, 242 { P_GCC_GPLL0_OUT_EVEN, 6 }, 243 }; 244 245 static const struct clk_parent_data gcc_parent_data_4[] = { 246 { .index = DT_BI_TCXO }, 247 { .hw = &gcc_gpll0.clkr.hw }, 248 { .hw = &gcc_gpll1.clkr.hw }, 249 { .hw = &gcc_gpll4.clkr.hw }, 250 { .hw = &gcc_gpll0_out_even.clkr.hw }, 251 }; 252 253 static const struct parent_map gcc_parent_map_5[] = { 254 { P_BI_TCXO, 0 }, 255 }; 256 257 static const struct clk_parent_data gcc_parent_data_5[] = { 258 { .index = DT_BI_TCXO }, 259 }; 260 261 static const struct parent_map gcc_parent_map_6[] = { 262 { P_BI_TCXO, 0 }, 263 { P_GCC_GPLL7_OUT_MAIN, 2 }, 264 { P_GCC_GPLL4_OUT_MAIN, 5 }, 265 { P_GCC_GPLL0_OUT_EVEN, 6 }, 266 }; 267 268 static const struct clk_parent_data gcc_parent_data_6[] = { 269 { .index = DT_BI_TCXO }, 270 { .hw = &gcc_gpll7.clkr.hw }, 271 { .hw = &gcc_gpll4.clkr.hw }, 272 { .hw = &gcc_gpll0_out_even.clkr.hw }, 273 }; 274 275 static const struct parent_map gcc_parent_map_7[] = { 276 { P_BI_TCXO, 0 }, 277 { P_GCC_GPLL7_OUT_MAIN, 2 }, 278 { P_RXC0_REF_CLK, 3 }, 279 { P_GCC_GPLL0_OUT_EVEN, 6 }, 280 }; 281 282 static const struct clk_parent_data gcc_parent_data_7[] = { 283 { .index = DT_BI_TCXO }, 284 { .hw = &gcc_gpll7.clkr.hw }, 285 { .index = DT_RXC0_REF_CLK }, 286 { .hw = &gcc_gpll0_out_even.clkr.hw }, 287 }; 288 289 static const struct parent_map gcc_parent_map_8[] = { 290 { P_BI_TCXO, 0 }, 291 { P_GCC_GPLL7_OUT_MAIN, 2 }, 292 { P_RXC1_REF_CLK, 3 }, 293 { P_GCC_GPLL0_OUT_EVEN, 6 }, 294 }; 295 296 static const struct clk_parent_data gcc_parent_data_8[] = { 297 { .index = DT_BI_TCXO }, 298 { .hw = &gcc_gpll7.clkr.hw }, 299 { .index = DT_RXC1_REF_CLK }, 300 { .hw = &gcc_gpll0_out_even.clkr.hw }, 301 }; 302 303 static const struct parent_map gcc_parent_map_9[] = { 304 { P_PCIE_PHY_AUX_CLK, 1 }, 305 { P_BI_TCXO, 2 }, 306 }; 307 308 static const struct clk_parent_data gcc_parent_data_9[] = { 309 { .index = DT_PCIE_PHY_AUX_CLK }, 310 { .index = DT_BI_TCXO }, 311 }; 312 313 static const struct parent_map gcc_parent_map_11[] = { 314 { P_PCIE_PHY_AUX_CLK, 1 }, 315 { P_BI_TCXO, 2 }, 316 }; 317 318 static const struct clk_parent_data gcc_parent_data_11[] = { 319 { .index = DT_PCIE_PHY_AUX_CLK }, 320 { .index = DT_BI_TCXO }, 321 }; 322 323 static const struct parent_map gcc_parent_map_13[] = { 324 { P_BI_TCXO, 0 }, 325 { P_GCC_GPLL0_OUT_MAIN, 1 }, 326 { P_GCC_GPLL9_OUT_MAIN, 2 }, 327 { P_GCC_GPLL4_OUT_MAIN, 5 }, 328 { P_GCC_GPLL0_OUT_EVEN, 6 }, 329 }; 330 331 static const struct clk_parent_data gcc_parent_data_13[] = { 332 { .index = DT_BI_TCXO }, 333 { .hw = &gcc_gpll0.clkr.hw }, 334 { .hw = &gcc_gpll9.clkr.hw }, 335 { .hw = &gcc_gpll4.clkr.hw }, 336 { .hw = &gcc_gpll0_out_even.clkr.hw }, 337 }; 338 339 static const struct parent_map gcc_parent_map_14[] = { 340 { P_BI_TCXO, 0 }, 341 { P_GCC_GPLL0_OUT_MAIN, 1 }, 342 }; 343 344 static const struct clk_parent_data gcc_parent_data_14[] = { 345 { .index = DT_BI_TCXO }, 346 { .hw = &gcc_gpll0.clkr.hw }, 347 }; 348 349 static const struct parent_map gcc_parent_map_15[] = { 350 { P_BI_TCXO, 0 }, 351 { P_GCC_GPLL7_OUT_MAIN, 2 }, 352 { P_GCC_GPLL5_OUT_MAIN, 3 }, 353 { P_GCC_GPLL4_OUT_MAIN, 5 }, 354 { P_GCC_GPLL0_OUT_EVEN, 6 }, 355 }; 356 357 static const struct clk_parent_data gcc_parent_data_15[] = { 358 { .index = DT_BI_TCXO }, 359 { .hw = &gcc_gpll7.clkr.hw }, 360 { .hw = &gcc_gpll5.clkr.hw }, 361 { .hw = &gcc_gpll4.clkr.hw }, 362 { .hw = &gcc_gpll0_out_even.clkr.hw }, 363 }; 364 365 static const struct parent_map gcc_parent_map_16[] = { 366 { P_UFS_CARD_RX_SYMBOL_0_CLK, 0 }, 367 { P_BI_TCXO, 2 }, 368 }; 369 370 static const struct clk_parent_data gcc_parent_data_16[] = { 371 { .index = DT_UFS_CARD_RX_SYMBOL_0_CLK }, 372 { .index = DT_BI_TCXO }, 373 }; 374 375 static const struct parent_map gcc_parent_map_17[] = { 376 { P_UFS_CARD_RX_SYMBOL_1_CLK, 0 }, 377 { P_BI_TCXO, 2 }, 378 }; 379 380 static const struct clk_parent_data gcc_parent_data_17[] = { 381 { .index = DT_UFS_CARD_RX_SYMBOL_1_CLK }, 382 { .index = DT_BI_TCXO }, 383 }; 384 385 static const struct parent_map gcc_parent_map_18[] = { 386 { P_UFS_CARD_TX_SYMBOL_0_CLK, 0 }, 387 { P_BI_TCXO, 2 }, 388 }; 389 390 static const struct clk_parent_data gcc_parent_data_18[] = { 391 { .index = DT_UFS_CARD_TX_SYMBOL_0_CLK }, 392 { .index = DT_BI_TCXO }, 393 }; 394 395 static const struct parent_map gcc_parent_map_19[] = { 396 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, 397 { P_BI_TCXO, 2 }, 398 }; 399 400 static const struct clk_parent_data gcc_parent_data_19[] = { 401 { .index = DT_UFS_PHY_RX_SYMBOL_0_CLK }, 402 { .index = DT_BI_TCXO }, 403 }; 404 405 static const struct parent_map gcc_parent_map_20[] = { 406 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, 407 { P_BI_TCXO, 2 }, 408 }; 409 410 static const struct clk_parent_data gcc_parent_data_20[] = { 411 { .index = DT_UFS_PHY_RX_SYMBOL_1_CLK }, 412 { .index = DT_BI_TCXO }, 413 }; 414 415 static const struct parent_map gcc_parent_map_21[] = { 416 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, 417 { P_BI_TCXO, 2 }, 418 }; 419 420 static const struct clk_parent_data gcc_parent_data_21[] = { 421 { .index = DT_UFS_PHY_TX_SYMBOL_0_CLK }, 422 { .index = DT_BI_TCXO }, 423 }; 424 425 static const struct parent_map gcc_parent_map_22[] = { 426 { P_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK, 0 }, 427 { P_BI_TCXO, 2 }, 428 }; 429 430 static const struct clk_parent_data gcc_parent_data_22[] = { 431 { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK }, 432 { .index = DT_BI_TCXO }, 433 }; 434 435 static const struct parent_map gcc_parent_map_23[] = { 436 { P_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK, 0 }, 437 { P_BI_TCXO, 2 }, 438 }; 439 440 static const struct clk_parent_data gcc_parent_data_23[] = { 441 { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK }, 442 { .index = DT_BI_TCXO }, 443 }; 444 445 static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = { 446 .reg = 0xa9074, 447 .shift = 0, 448 .width = 2, 449 .parent_map = gcc_parent_map_9, 450 .clkr = { 451 .hw.init = &(const struct clk_init_data){ 452 .name = "gcc_pcie_0_phy_aux_clk_src", 453 .parent_data = gcc_parent_data_9, 454 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 455 .ops = &clk_regmap_mux_closest_ops, 456 }, 457 }, 458 }; 459 460 static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { 461 .reg = 0xa906c, 462 .clkr = { 463 .hw.init = &(const struct clk_init_data){ 464 .name = "gcc_pcie_0_pipe_clk_src", 465 .parent_data = &(const struct clk_parent_data){ 466 .index = DT_PCIE_0_PIPE_CLK, 467 }, 468 .num_parents = 1, 469 .ops = &clk_regmap_phy_mux_ops, 470 }, 471 }, 472 }; 473 474 static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = { 475 .reg = 0x77074, 476 .shift = 0, 477 .width = 2, 478 .parent_map = gcc_parent_map_11, 479 .clkr = { 480 .hw.init = &(const struct clk_init_data){ 481 .name = "gcc_pcie_1_phy_aux_clk_src", 482 .parent_data = gcc_parent_data_11, 483 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 484 .ops = &clk_regmap_mux_closest_ops, 485 }, 486 }, 487 }; 488 489 static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = { 490 .reg = 0x7706c, 491 .clkr = { 492 .hw.init = &(const struct clk_init_data){ 493 .name = "gcc_pcie_1_pipe_clk_src", 494 .parent_data = &(const struct clk_parent_data) { 495 .index = DT_PCIE_1_PIPE_CLK, 496 }, 497 .num_parents = 1, 498 .ops = &clk_regmap_phy_mux_ops, 499 }, 500 }, 501 }; 502 503 static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src = { 504 .reg = 0x81060, 505 .shift = 0, 506 .width = 2, 507 .parent_map = gcc_parent_map_16, 508 .clkr = { 509 .hw.init = &(const struct clk_init_data){ 510 .name = "gcc_ufs_card_rx_symbol_0_clk_src", 511 .parent_data = gcc_parent_data_16, 512 .num_parents = ARRAY_SIZE(gcc_parent_data_16), 513 .ops = &clk_regmap_mux_closest_ops, 514 }, 515 }, 516 }; 517 518 static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src = { 519 .reg = 0x810d0, 520 .shift = 0, 521 .width = 2, 522 .parent_map = gcc_parent_map_17, 523 .clkr = { 524 .hw.init = &(const struct clk_init_data){ 525 .name = "gcc_ufs_card_rx_symbol_1_clk_src", 526 .parent_data = gcc_parent_data_17, 527 .num_parents = ARRAY_SIZE(gcc_parent_data_17), 528 .ops = &clk_regmap_mux_closest_ops, 529 }, 530 }, 531 }; 532 533 static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src = { 534 .reg = 0x81050, 535 .shift = 0, 536 .width = 2, 537 .parent_map = gcc_parent_map_18, 538 .clkr = { 539 .hw.init = &(const struct clk_init_data){ 540 .name = "gcc_ufs_card_tx_symbol_0_clk_src", 541 .parent_data = gcc_parent_data_18, 542 .num_parents = ARRAY_SIZE(gcc_parent_data_18), 543 .ops = &clk_regmap_mux_closest_ops, 544 }, 545 }, 546 }; 547 548 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 549 .reg = 0x83060, 550 .shift = 0, 551 .width = 2, 552 .parent_map = gcc_parent_map_19, 553 .clkr = { 554 .hw.init = &(const struct clk_init_data){ 555 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 556 .parent_data = gcc_parent_data_19, 557 .num_parents = ARRAY_SIZE(gcc_parent_data_19), 558 .ops = &clk_regmap_mux_closest_ops, 559 }, 560 }, 561 }; 562 563 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 564 .reg = 0x830d0, 565 .shift = 0, 566 .width = 2, 567 .parent_map = gcc_parent_map_20, 568 .clkr = { 569 .hw.init = &(const struct clk_init_data){ 570 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 571 .parent_data = gcc_parent_data_20, 572 .num_parents = ARRAY_SIZE(gcc_parent_data_20), 573 .ops = &clk_regmap_mux_closest_ops, 574 }, 575 }, 576 }; 577 578 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 579 .reg = 0x83050, 580 .shift = 0, 581 .width = 2, 582 .parent_map = gcc_parent_map_21, 583 .clkr = { 584 .hw.init = &(const struct clk_init_data){ 585 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 586 .parent_data = gcc_parent_data_21, 587 .num_parents = ARRAY_SIZE(gcc_parent_data_21), 588 .ops = &clk_regmap_mux_closest_ops, 589 }, 590 }, 591 }; 592 593 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 594 .reg = 0x1b068, 595 .shift = 0, 596 .width = 2, 597 .parent_map = gcc_parent_map_22, 598 .clkr = { 599 .hw.init = &(const struct clk_init_data){ 600 .name = "gcc_usb3_prim_phy_pipe_clk_src", 601 .parent_data = gcc_parent_data_22, 602 .num_parents = ARRAY_SIZE(gcc_parent_data_22), 603 .ops = &clk_regmap_mux_closest_ops, 604 }, 605 }, 606 }; 607 608 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = { 609 .reg = 0x2f068, 610 .shift = 0, 611 .width = 2, 612 .parent_map = gcc_parent_map_23, 613 .clkr = { 614 .hw.init = &(const struct clk_init_data){ 615 .name = "gcc_usb3_sec_phy_pipe_clk_src", 616 .parent_data = gcc_parent_data_23, 617 .num_parents = ARRAY_SIZE(gcc_parent_data_23), 618 .ops = &clk_regmap_mux_closest_ops, 619 }, 620 }, 621 }; 622 623 static const struct freq_tbl ftbl_gcc_emac0_phy_aux_clk_src[] = { 624 F(19200000, P_BI_TCXO, 1, 0, 0), 625 { } 626 }; 627 628 static struct clk_rcg2 gcc_emac0_phy_aux_clk_src = { 629 .cmd_rcgr = 0xb6028, 630 .mnd_width = 0, 631 .hid_width = 5, 632 .parent_map = gcc_parent_map_3, 633 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 634 .clkr.hw.init = &(const struct clk_init_data){ 635 .name = "gcc_emac0_phy_aux_clk_src", 636 .parent_data = gcc_parent_data_3, 637 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 638 .ops = &clk_rcg2_shared_ops, 639 }, 640 }; 641 642 static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] = { 643 F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0), 644 F(230400000, P_GCC_GPLL4_OUT_MAIN, 3.5, 0, 0), 645 { } 646 }; 647 648 static struct clk_rcg2 gcc_emac0_ptp_clk_src = { 649 .cmd_rcgr = 0xb6060, 650 .mnd_width = 16, 651 .hid_width = 5, 652 .parent_map = gcc_parent_map_6, 653 .freq_tbl = ftbl_gcc_emac0_ptp_clk_src, 654 .clkr.hw.init = &(const struct clk_init_data){ 655 .name = "gcc_emac0_ptp_clk_src", 656 .parent_data = gcc_parent_data_6, 657 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 658 .ops = &clk_rcg2_shared_ops, 659 }, 660 }; 661 662 static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] = { 663 F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0), 664 F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0), 665 { } 666 }; 667 668 static struct clk_rcg2 gcc_emac0_rgmii_clk_src = { 669 .cmd_rcgr = 0xb6048, 670 .mnd_width = 16, 671 .hid_width = 5, 672 .parent_map = gcc_parent_map_7, 673 .freq_tbl = ftbl_gcc_emac0_rgmii_clk_src, 674 .clkr.hw.init = &(const struct clk_init_data){ 675 .name = "gcc_emac0_rgmii_clk_src", 676 .parent_data = gcc_parent_data_7, 677 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 678 .ops = &clk_rcg2_shared_ops, 679 }, 680 }; 681 682 static struct clk_rcg2 gcc_emac1_phy_aux_clk_src = { 683 .cmd_rcgr = 0xb4028, 684 .mnd_width = 0, 685 .hid_width = 5, 686 .parent_map = gcc_parent_map_3, 687 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 688 .clkr.hw.init = &(const struct clk_init_data){ 689 .name = "gcc_emac1_phy_aux_clk_src", 690 .parent_data = gcc_parent_data_3, 691 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 692 .ops = &clk_rcg2_shared_ops, 693 }, 694 }; 695 696 static struct clk_rcg2 gcc_emac1_ptp_clk_src = { 697 .cmd_rcgr = 0xb4060, 698 .mnd_width = 16, 699 .hid_width = 5, 700 .parent_map = gcc_parent_map_6, 701 .freq_tbl = ftbl_gcc_emac0_ptp_clk_src, 702 .clkr.hw.init = &(const struct clk_init_data){ 703 .name = "gcc_emac1_ptp_clk_src", 704 .parent_data = gcc_parent_data_6, 705 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 706 .ops = &clk_rcg2_shared_ops, 707 }, 708 }; 709 710 static struct clk_rcg2 gcc_emac1_rgmii_clk_src = { 711 .cmd_rcgr = 0xb4048, 712 .mnd_width = 16, 713 .hid_width = 5, 714 .parent_map = gcc_parent_map_8, 715 .freq_tbl = ftbl_gcc_emac0_rgmii_clk_src, 716 .clkr.hw.init = &(const struct clk_init_data){ 717 .name = "gcc_emac1_rgmii_clk_src", 718 .parent_data = gcc_parent_data_8, 719 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 720 .ops = &clk_rcg2_shared_ops, 721 }, 722 }; 723 724 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 725 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 726 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 727 { } 728 }; 729 730 static struct clk_rcg2 gcc_gp1_clk_src = { 731 .cmd_rcgr = 0x70004, 732 .mnd_width = 16, 733 .hid_width = 5, 734 .parent_map = gcc_parent_map_2, 735 .freq_tbl = ftbl_gcc_gp1_clk_src, 736 .clkr.hw.init = &(const struct clk_init_data){ 737 .name = "gcc_gp1_clk_src", 738 .parent_data = gcc_parent_data_2, 739 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 740 .ops = &clk_rcg2_shared_ops, 741 }, 742 }; 743 744 static struct clk_rcg2 gcc_gp2_clk_src = { 745 .cmd_rcgr = 0x71004, 746 .mnd_width = 16, 747 .hid_width = 5, 748 .parent_map = gcc_parent_map_2, 749 .freq_tbl = ftbl_gcc_gp1_clk_src, 750 .clkr.hw.init = &(const struct clk_init_data){ 751 .name = "gcc_gp2_clk_src", 752 .parent_data = gcc_parent_data_2, 753 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 754 .ops = &clk_rcg2_shared_ops, 755 }, 756 }; 757 758 static struct clk_rcg2 gcc_gp3_clk_src = { 759 .cmd_rcgr = 0x62004, 760 .mnd_width = 16, 761 .hid_width = 5, 762 .parent_map = gcc_parent_map_2, 763 .freq_tbl = ftbl_gcc_gp1_clk_src, 764 .clkr.hw.init = &(const struct clk_init_data){ 765 .name = "gcc_gp3_clk_src", 766 .parent_data = gcc_parent_data_2, 767 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 768 .ops = &clk_rcg2_shared_ops, 769 }, 770 }; 771 772 static struct clk_rcg2 gcc_gp4_clk_src = { 773 .cmd_rcgr = 0x1e004, 774 .mnd_width = 16, 775 .hid_width = 5, 776 .parent_map = gcc_parent_map_2, 777 .freq_tbl = ftbl_gcc_gp1_clk_src, 778 .clkr.hw.init = &(const struct clk_init_data){ 779 .name = "gcc_gp4_clk_src", 780 .parent_data = gcc_parent_data_2, 781 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 782 .ops = &clk_rcg2_shared_ops, 783 }, 784 }; 785 786 static struct clk_rcg2 gcc_gp5_clk_src = { 787 .cmd_rcgr = 0x1f004, 788 .mnd_width = 16, 789 .hid_width = 5, 790 .parent_map = gcc_parent_map_2, 791 .freq_tbl = ftbl_gcc_gp1_clk_src, 792 .clkr.hw.init = &(const struct clk_init_data){ 793 .name = "gcc_gp5_clk_src", 794 .parent_data = gcc_parent_data_2, 795 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 796 .ops = &clk_rcg2_shared_ops, 797 }, 798 }; 799 800 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 801 .cmd_rcgr = 0xa9078, 802 .mnd_width = 16, 803 .hid_width = 5, 804 .parent_map = gcc_parent_map_3, 805 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 806 .clkr.hw.init = &(const struct clk_init_data){ 807 .name = "gcc_pcie_0_aux_clk_src", 808 .parent_data = gcc_parent_data_3, 809 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 810 .ops = &clk_rcg2_shared_ops, 811 }, 812 }; 813 814 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 815 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 816 { } 817 }; 818 819 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 820 .cmd_rcgr = 0xa9054, 821 .mnd_width = 0, 822 .hid_width = 5, 823 .parent_map = gcc_parent_map_0, 824 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 825 .clkr.hw.init = &(const struct clk_init_data){ 826 .name = "gcc_pcie_0_phy_rchng_clk_src", 827 .parent_data = gcc_parent_data_0, 828 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 829 .ops = &clk_rcg2_shared_ops, 830 }, 831 }; 832 833 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 834 .cmd_rcgr = 0x77078, 835 .mnd_width = 16, 836 .hid_width = 5, 837 .parent_map = gcc_parent_map_3, 838 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 839 .clkr.hw.init = &(const struct clk_init_data){ 840 .name = "gcc_pcie_1_aux_clk_src", 841 .parent_data = gcc_parent_data_3, 842 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 843 .ops = &clk_rcg2_shared_ops, 844 }, 845 }; 846 847 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 848 .cmd_rcgr = 0x77054, 849 .mnd_width = 0, 850 .hid_width = 5, 851 .parent_map = gcc_parent_map_0, 852 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 853 .clkr.hw.init = &(const struct clk_init_data){ 854 .name = "gcc_pcie_1_phy_rchng_clk_src", 855 .parent_data = gcc_parent_data_0, 856 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 857 .ops = &clk_rcg2_shared_ops, 858 }, 859 }; 860 861 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 862 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 863 { } 864 }; 865 866 static struct clk_rcg2 gcc_pdm2_clk_src = { 867 .cmd_rcgr = 0x3f010, 868 .mnd_width = 0, 869 .hid_width = 5, 870 .parent_map = gcc_parent_map_0, 871 .freq_tbl = ftbl_gcc_pdm2_clk_src, 872 .clkr.hw.init = &(const struct clk_init_data){ 873 .name = "gcc_pdm2_clk_src", 874 .parent_data = gcc_parent_data_0, 875 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 876 .ops = &clk_rcg2_shared_ops, 877 }, 878 }; 879 880 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 881 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 882 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 883 F(19200000, P_BI_TCXO, 1, 0, 0), 884 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 885 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 886 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 887 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 888 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 889 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 890 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 891 { } 892 }; 893 894 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 895 .name = "gcc_qupv3_wrap0_s0_clk_src", 896 .parent_data = gcc_parent_data_0, 897 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 898 .ops = &clk_rcg2_shared_ops, 899 }; 900 901 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 902 .cmd_rcgr = 0x23154, 903 .mnd_width = 16, 904 .hid_width = 5, 905 .parent_map = gcc_parent_map_0, 906 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 907 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 908 }; 909 910 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 911 .name = "gcc_qupv3_wrap0_s1_clk_src", 912 .parent_data = gcc_parent_data_0, 913 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 914 .ops = &clk_rcg2_shared_ops, 915 }; 916 917 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 918 .cmd_rcgr = 0x23288, 919 .mnd_width = 16, 920 .hid_width = 5, 921 .parent_map = gcc_parent_map_0, 922 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 923 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 924 }; 925 926 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = { 927 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 928 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 929 F(19200000, P_BI_TCXO, 1, 0, 0), 930 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 931 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 932 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 933 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 934 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 935 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 936 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 937 { } 938 }; 939 940 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 941 .name = "gcc_qupv3_wrap0_s2_clk_src", 942 .parent_data = gcc_parent_data_0, 943 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 944 .ops = &clk_rcg2_shared_ops, 945 }; 946 947 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 948 .cmd_rcgr = 0x233bc, 949 .mnd_width = 16, 950 .hid_width = 5, 951 .parent_map = gcc_parent_map_0, 952 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 953 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 954 }; 955 956 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 957 .name = "gcc_qupv3_wrap0_s3_clk_src", 958 .parent_data = gcc_parent_data_0, 959 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 960 .ops = &clk_rcg2_shared_ops, 961 }; 962 963 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 964 .cmd_rcgr = 0x234f0, 965 .mnd_width = 16, 966 .hid_width = 5, 967 .parent_map = gcc_parent_map_0, 968 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 969 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 970 }; 971 972 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 973 .name = "gcc_qupv3_wrap0_s4_clk_src", 974 .parent_data = gcc_parent_data_1, 975 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 976 .ops = &clk_rcg2_shared_ops, 977 }; 978 979 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 980 .cmd_rcgr = 0x23624, 981 .mnd_width = 16, 982 .hid_width = 5, 983 .parent_map = gcc_parent_map_1, 984 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 985 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 986 }; 987 988 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 989 .name = "gcc_qupv3_wrap0_s5_clk_src", 990 .parent_data = gcc_parent_data_0, 991 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 992 .ops = &clk_rcg2_shared_ops, 993 }; 994 995 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 996 .cmd_rcgr = 0x23758, 997 .mnd_width = 16, 998 .hid_width = 5, 999 .parent_map = gcc_parent_map_0, 1000 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1001 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 1002 }; 1003 1004 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 1005 .name = "gcc_qupv3_wrap0_s6_clk_src", 1006 .parent_data = gcc_parent_data_0, 1007 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1008 .ops = &clk_rcg2_shared_ops, 1009 }; 1010 1011 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 1012 .cmd_rcgr = 0x2388c, 1013 .mnd_width = 16, 1014 .hid_width = 5, 1015 .parent_map = gcc_parent_map_0, 1016 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1017 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 1018 }; 1019 1020 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 1021 .name = "gcc_qupv3_wrap1_s0_clk_src", 1022 .parent_data = gcc_parent_data_0, 1023 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1024 .ops = &clk_rcg2_shared_ops, 1025 }; 1026 1027 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 1028 .cmd_rcgr = 0x24154, 1029 .mnd_width = 16, 1030 .hid_width = 5, 1031 .parent_map = gcc_parent_map_0, 1032 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1033 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 1034 }; 1035 1036 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 1037 .name = "gcc_qupv3_wrap1_s1_clk_src", 1038 .parent_data = gcc_parent_data_0, 1039 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1040 .ops = &clk_rcg2_shared_ops, 1041 }; 1042 1043 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 1044 .cmd_rcgr = 0x24288, 1045 .mnd_width = 16, 1046 .hid_width = 5, 1047 .parent_map = gcc_parent_map_0, 1048 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1049 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 1050 }; 1051 1052 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 1053 .name = "gcc_qupv3_wrap1_s2_clk_src", 1054 .parent_data = gcc_parent_data_0, 1055 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1056 .ops = &clk_rcg2_shared_ops, 1057 }; 1058 1059 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 1060 .cmd_rcgr = 0x243bc, 1061 .mnd_width = 16, 1062 .hid_width = 5, 1063 .parent_map = gcc_parent_map_0, 1064 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1065 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 1066 }; 1067 1068 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 1069 .name = "gcc_qupv3_wrap1_s3_clk_src", 1070 .parent_data = gcc_parent_data_0, 1071 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1072 .ops = &clk_rcg2_shared_ops, 1073 }; 1074 1075 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 1076 .cmd_rcgr = 0x244f0, 1077 .mnd_width = 16, 1078 .hid_width = 5, 1079 .parent_map = gcc_parent_map_0, 1080 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1081 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 1082 }; 1083 1084 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 1085 .name = "gcc_qupv3_wrap1_s4_clk_src", 1086 .parent_data = gcc_parent_data_1, 1087 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1088 .ops = &clk_rcg2_shared_ops, 1089 }; 1090 1091 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 1092 .cmd_rcgr = 0x24624, 1093 .mnd_width = 16, 1094 .hid_width = 5, 1095 .parent_map = gcc_parent_map_1, 1096 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1097 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 1098 }; 1099 1100 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 1101 .name = "gcc_qupv3_wrap1_s5_clk_src", 1102 .parent_data = gcc_parent_data_0, 1103 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1104 .ops = &clk_rcg2_shared_ops, 1105 }; 1106 1107 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 1108 .cmd_rcgr = 0x24758, 1109 .mnd_width = 16, 1110 .hid_width = 5, 1111 .parent_map = gcc_parent_map_0, 1112 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1113 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 1114 }; 1115 1116 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 1117 .name = "gcc_qupv3_wrap1_s6_clk_src", 1118 .parent_data = gcc_parent_data_0, 1119 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1120 .ops = &clk_rcg2_shared_ops, 1121 }; 1122 1123 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 1124 .cmd_rcgr = 0x2488c, 1125 .mnd_width = 16, 1126 .hid_width = 5, 1127 .parent_map = gcc_parent_map_0, 1128 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1129 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 1130 }; 1131 1132 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 1133 .name = "gcc_qupv3_wrap2_s0_clk_src", 1134 .parent_data = gcc_parent_data_1, 1135 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1136 .ops = &clk_rcg2_shared_ops, 1137 }; 1138 1139 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 1140 .cmd_rcgr = 0x2a154, 1141 .mnd_width = 16, 1142 .hid_width = 5, 1143 .parent_map = gcc_parent_map_1, 1144 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1145 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 1146 }; 1147 1148 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 1149 .name = "gcc_qupv3_wrap2_s1_clk_src", 1150 .parent_data = gcc_parent_data_1, 1151 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1152 .ops = &clk_rcg2_shared_ops, 1153 }; 1154 1155 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 1156 .cmd_rcgr = 0x2a288, 1157 .mnd_width = 16, 1158 .hid_width = 5, 1159 .parent_map = gcc_parent_map_1, 1160 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1161 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 1162 }; 1163 1164 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 1165 .name = "gcc_qupv3_wrap2_s2_clk_src", 1166 .parent_data = gcc_parent_data_1, 1167 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1168 .ops = &clk_rcg2_shared_ops, 1169 }; 1170 1171 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 1172 .cmd_rcgr = 0x2a3bc, 1173 .mnd_width = 16, 1174 .hid_width = 5, 1175 .parent_map = gcc_parent_map_1, 1176 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1177 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 1178 }; 1179 1180 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 1181 .name = "gcc_qupv3_wrap2_s3_clk_src", 1182 .parent_data = gcc_parent_data_1, 1183 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1184 .ops = &clk_rcg2_shared_ops, 1185 }; 1186 1187 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 1188 .cmd_rcgr = 0x2a4f0, 1189 .mnd_width = 16, 1190 .hid_width = 5, 1191 .parent_map = gcc_parent_map_1, 1192 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1193 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 1194 }; 1195 1196 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 1197 .name = "gcc_qupv3_wrap2_s4_clk_src", 1198 .parent_data = gcc_parent_data_1, 1199 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1200 .ops = &clk_rcg2_shared_ops, 1201 }; 1202 1203 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 1204 .cmd_rcgr = 0x2a624, 1205 .mnd_width = 16, 1206 .hid_width = 5, 1207 .parent_map = gcc_parent_map_1, 1208 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1209 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 1210 }; 1211 1212 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 1213 .name = "gcc_qupv3_wrap2_s5_clk_src", 1214 .parent_data = gcc_parent_data_1, 1215 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1216 .ops = &clk_rcg2_shared_ops, 1217 }; 1218 1219 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 1220 .cmd_rcgr = 0x2a758, 1221 .mnd_width = 16, 1222 .hid_width = 5, 1223 .parent_map = gcc_parent_map_1, 1224 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1225 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 1226 }; 1227 1228 static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { 1229 .name = "gcc_qupv3_wrap2_s6_clk_src", 1230 .parent_data = gcc_parent_data_1, 1231 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1232 .ops = &clk_rcg2_shared_ops, 1233 }; 1234 1235 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { 1236 .cmd_rcgr = 0x2a88c, 1237 .mnd_width = 16, 1238 .hid_width = 5, 1239 .parent_map = gcc_parent_map_1, 1240 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1241 .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init, 1242 }; 1243 1244 static const struct freq_tbl ftbl_gcc_qupv3_wrap3_s0_clk_src[] = { 1245 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 1246 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 1247 F(19200000, P_BI_TCXO, 1, 0, 0), 1248 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 1249 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 1250 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 1251 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 1252 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1253 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 1254 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 1255 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 1256 F(403200000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1257 { } 1258 }; 1259 1260 static struct clk_init_data gcc_qupv3_wrap3_s0_clk_src_init = { 1261 .name = "gcc_qupv3_wrap3_s0_clk_src", 1262 .parent_data = gcc_parent_data_4, 1263 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1264 .ops = &clk_rcg2_shared_ops, 1265 }; 1266 1267 static struct clk_rcg2 gcc_qupv3_wrap3_s0_clk_src = { 1268 .cmd_rcgr = 0xc4154, 1269 .mnd_width = 16, 1270 .hid_width = 5, 1271 .parent_map = gcc_parent_map_4, 1272 .freq_tbl = ftbl_gcc_qupv3_wrap3_s0_clk_src, 1273 .clkr.hw.init = &gcc_qupv3_wrap3_s0_clk_src_init, 1274 }; 1275 1276 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 1277 F(144000, P_BI_TCXO, 16, 3, 25), 1278 F(400000, P_BI_TCXO, 12, 1, 4), 1279 F(19200000, P_BI_TCXO, 1, 0, 0), 1280 F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3), 1281 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1282 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 1283 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1284 F(192000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 1285 F(384000000, P_GCC_GPLL9_OUT_MAIN, 2, 0, 0), 1286 { } 1287 }; 1288 1289 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 1290 .cmd_rcgr = 0x20014, 1291 .mnd_width = 8, 1292 .hid_width = 5, 1293 .parent_map = gcc_parent_map_13, 1294 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 1295 .clkr.hw.init = &(const struct clk_init_data){ 1296 .name = "gcc_sdcc1_apps_clk_src", 1297 .parent_data = gcc_parent_data_13, 1298 .num_parents = ARRAY_SIZE(gcc_parent_data_13), 1299 .ops = &clk_rcg2_floor_ops, 1300 }, 1301 }; 1302 1303 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 1304 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 1305 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 1306 { } 1307 }; 1308 1309 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 1310 .cmd_rcgr = 0x2002c, 1311 .mnd_width = 0, 1312 .hid_width = 5, 1313 .parent_map = gcc_parent_map_14, 1314 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 1315 .clkr.hw.init = &(const struct clk_init_data){ 1316 .name = "gcc_sdcc1_ice_core_clk_src", 1317 .parent_data = gcc_parent_data_14, 1318 .num_parents = ARRAY_SIZE(gcc_parent_data_14), 1319 .ops = &clk_rcg2_floor_ops, 1320 }, 1321 }; 1322 1323 static const struct freq_tbl ftbl_gcc_tscss_cntr_clk_src[] = { 1324 F(15625000, P_GCC_GPLL7_OUT_MAIN, 16, 1, 4), 1325 { } 1326 }; 1327 1328 static struct clk_rcg2 gcc_tscss_cntr_clk_src = { 1329 .cmd_rcgr = 0x21008, 1330 .mnd_width = 16, 1331 .hid_width = 5, 1332 .parent_map = gcc_parent_map_15, 1333 .freq_tbl = ftbl_gcc_tscss_cntr_clk_src, 1334 .clkr.hw.init = &(const struct clk_init_data){ 1335 .name = "gcc_tscss_cntr_clk_src", 1336 .parent_data = gcc_parent_data_15, 1337 .num_parents = ARRAY_SIZE(gcc_parent_data_15), 1338 .ops = &clk_rcg2_shared_ops, 1339 }, 1340 }; 1341 1342 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { 1343 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1344 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1345 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 1346 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 1347 F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0), 1348 { } 1349 }; 1350 1351 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { 1352 .cmd_rcgr = 0x8102c, 1353 .mnd_width = 8, 1354 .hid_width = 5, 1355 .parent_map = gcc_parent_map_0, 1356 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, 1357 .clkr.hw.init = &(const struct clk_init_data){ 1358 .name = "gcc_ufs_card_axi_clk_src", 1359 .parent_data = gcc_parent_data_0, 1360 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1361 .ops = &clk_rcg2_shared_ops, 1362 }, 1363 }; 1364 1365 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { 1366 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1367 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 1368 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 1369 F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0), 1370 { } 1371 }; 1372 1373 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { 1374 .cmd_rcgr = 0x81074, 1375 .mnd_width = 0, 1376 .hid_width = 5, 1377 .parent_map = gcc_parent_map_0, 1378 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 1379 .clkr.hw.init = &(const struct clk_init_data){ 1380 .name = "gcc_ufs_card_ice_core_clk_src", 1381 .parent_data = gcc_parent_data_0, 1382 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1383 .ops = &clk_rcg2_shared_ops, 1384 }, 1385 }; 1386 1387 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { 1388 .cmd_rcgr = 0x810a8, 1389 .mnd_width = 0, 1390 .hid_width = 5, 1391 .parent_map = gcc_parent_map_5, 1392 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 1393 .clkr.hw.init = &(const struct clk_init_data){ 1394 .name = "gcc_ufs_card_phy_aux_clk_src", 1395 .parent_data = gcc_parent_data_5, 1396 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1397 .ops = &clk_rcg2_shared_ops, 1398 }, 1399 }; 1400 1401 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { 1402 .cmd_rcgr = 0x8108c, 1403 .mnd_width = 0, 1404 .hid_width = 5, 1405 .parent_map = gcc_parent_map_0, 1406 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 1407 .clkr.hw.init = &(const struct clk_init_data){ 1408 .name = "gcc_ufs_card_unipro_core_clk_src", 1409 .parent_data = gcc_parent_data_0, 1410 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1411 .ops = &clk_rcg2_shared_ops, 1412 }, 1413 }; 1414 1415 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1416 .cmd_rcgr = 0x8302c, 1417 .mnd_width = 8, 1418 .hid_width = 5, 1419 .parent_map = gcc_parent_map_0, 1420 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, 1421 .clkr.hw.init = &(const struct clk_init_data){ 1422 .name = "gcc_ufs_phy_axi_clk_src", 1423 .parent_data = gcc_parent_data_0, 1424 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1425 .ops = &clk_rcg2_shared_ops, 1426 }, 1427 }; 1428 1429 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1430 .cmd_rcgr = 0x83074, 1431 .mnd_width = 0, 1432 .hid_width = 5, 1433 .parent_map = gcc_parent_map_0, 1434 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 1435 .clkr.hw.init = &(const struct clk_init_data){ 1436 .name = "gcc_ufs_phy_ice_core_clk_src", 1437 .parent_data = gcc_parent_data_0, 1438 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1439 .ops = &clk_rcg2_shared_ops, 1440 }, 1441 }; 1442 1443 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1444 .cmd_rcgr = 0x830a8, 1445 .mnd_width = 0, 1446 .hid_width = 5, 1447 .parent_map = gcc_parent_map_5, 1448 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 1449 .clkr.hw.init = &(const struct clk_init_data){ 1450 .name = "gcc_ufs_phy_phy_aux_clk_src", 1451 .parent_data = gcc_parent_data_5, 1452 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1453 .ops = &clk_rcg2_shared_ops, 1454 }, 1455 }; 1456 1457 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1458 .cmd_rcgr = 0x8308c, 1459 .mnd_width = 0, 1460 .hid_width = 5, 1461 .parent_map = gcc_parent_map_0, 1462 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 1463 .clkr.hw.init = &(const struct clk_init_data){ 1464 .name = "gcc_ufs_phy_unipro_core_clk_src", 1465 .parent_data = gcc_parent_data_0, 1466 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1467 .ops = &clk_rcg2_shared_ops, 1468 }, 1469 }; 1470 1471 static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = { 1472 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 1473 { } 1474 }; 1475 1476 static struct clk_rcg2 gcc_usb20_master_clk_src = { 1477 .cmd_rcgr = 0x1c028, 1478 .mnd_width = 8, 1479 .hid_width = 5, 1480 .parent_map = gcc_parent_map_0, 1481 .freq_tbl = ftbl_gcc_usb20_master_clk_src, 1482 .clkr.hw.init = &(const struct clk_init_data){ 1483 .name = "gcc_usb20_master_clk_src", 1484 .parent_data = gcc_parent_data_0, 1485 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1486 .ops = &clk_rcg2_shared_ops, 1487 }, 1488 }; 1489 1490 static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = { 1491 .cmd_rcgr = 0x1c040, 1492 .mnd_width = 0, 1493 .hid_width = 5, 1494 .parent_map = gcc_parent_map_0, 1495 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 1496 .clkr.hw.init = &(const struct clk_init_data){ 1497 .name = "gcc_usb20_mock_utmi_clk_src", 1498 .parent_data = gcc_parent_data_0, 1499 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1500 .ops = &clk_rcg2_shared_ops, 1501 }, 1502 }; 1503 1504 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1505 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1506 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1507 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1508 { } 1509 }; 1510 1511 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1512 .cmd_rcgr = 0x1b028, 1513 .mnd_width = 8, 1514 .hid_width = 5, 1515 .parent_map = gcc_parent_map_0, 1516 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1517 .clkr.hw.init = &(const struct clk_init_data){ 1518 .name = "gcc_usb30_prim_master_clk_src", 1519 .parent_data = gcc_parent_data_0, 1520 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1521 .ops = &clk_rcg2_shared_ops, 1522 }, 1523 }; 1524 1525 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1526 .cmd_rcgr = 0x1b040, 1527 .mnd_width = 0, 1528 .hid_width = 5, 1529 .parent_map = gcc_parent_map_0, 1530 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 1531 .clkr.hw.init = &(const struct clk_init_data){ 1532 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1533 .parent_data = gcc_parent_data_0, 1534 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1535 .ops = &clk_rcg2_shared_ops, 1536 }, 1537 }; 1538 1539 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { 1540 .cmd_rcgr = 0x2f028, 1541 .mnd_width = 8, 1542 .hid_width = 5, 1543 .parent_map = gcc_parent_map_0, 1544 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1545 .clkr.hw.init = &(const struct clk_init_data){ 1546 .name = "gcc_usb30_sec_master_clk_src", 1547 .parent_data = gcc_parent_data_0, 1548 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1549 .ops = &clk_rcg2_shared_ops, 1550 }, 1551 }; 1552 1553 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { 1554 .cmd_rcgr = 0x2f040, 1555 .mnd_width = 0, 1556 .hid_width = 5, 1557 .parent_map = gcc_parent_map_0, 1558 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 1559 .clkr.hw.init = &(const struct clk_init_data){ 1560 .name = "gcc_usb30_sec_mock_utmi_clk_src", 1561 .parent_data = gcc_parent_data_0, 1562 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1563 .ops = &clk_rcg2_shared_ops, 1564 }, 1565 }; 1566 1567 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1568 .cmd_rcgr = 0x1b06c, 1569 .mnd_width = 0, 1570 .hid_width = 5, 1571 .parent_map = gcc_parent_map_3, 1572 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 1573 .clkr.hw.init = &(const struct clk_init_data){ 1574 .name = "gcc_usb3_prim_phy_aux_clk_src", 1575 .parent_data = gcc_parent_data_3, 1576 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1577 .ops = &clk_rcg2_shared_ops, 1578 }, 1579 }; 1580 1581 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { 1582 .cmd_rcgr = 0x2f06c, 1583 .mnd_width = 0, 1584 .hid_width = 5, 1585 .parent_map = gcc_parent_map_3, 1586 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 1587 .clkr.hw.init = &(const struct clk_init_data){ 1588 .name = "gcc_usb3_sec_phy_aux_clk_src", 1589 .parent_data = gcc_parent_data_3, 1590 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1591 .ops = &clk_rcg2_shared_ops, 1592 }, 1593 }; 1594 1595 static struct clk_regmap_div gcc_pcie_0_pipe_div_clk_src = { 1596 .reg = 0xa9070, 1597 .shift = 0, 1598 .width = 4, 1599 .clkr.hw.init = &(const struct clk_init_data) { 1600 .name = "gcc_pcie_0_pipe_div_clk_src", 1601 .parent_hws = (const struct clk_hw*[]){ 1602 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1603 }, 1604 .num_parents = 1, 1605 .flags = CLK_SET_RATE_PARENT, 1606 .ops = &clk_regmap_div_ro_ops, 1607 }, 1608 }; 1609 1610 static struct clk_regmap_div gcc_pcie_1_pipe_div_clk_src = { 1611 .reg = 0x77070, 1612 .shift = 0, 1613 .width = 4, 1614 .clkr.hw.init = &(const struct clk_init_data) { 1615 .name = "gcc_pcie_1_pipe_div_clk_src", 1616 .parent_hws = (const struct clk_hw*[]){ 1617 &gcc_pcie_1_pipe_clk_src.clkr.hw, 1618 }, 1619 .num_parents = 1, 1620 .flags = CLK_SET_RATE_PARENT, 1621 .ops = &clk_regmap_div_ro_ops, 1622 }, 1623 }; 1624 1625 static struct clk_regmap_div gcc_qupv3_wrap3_s0_div_clk_src = { 1626 .reg = 0xc4284, 1627 .shift = 0, 1628 .width = 4, 1629 .clkr.hw.init = &(const struct clk_init_data) { 1630 .name = "gcc_qupv3_wrap3_s0_div_clk_src", 1631 .parent_hws = (const struct clk_hw*[]){ 1632 &gcc_qupv3_wrap3_s0_clk_src.clkr.hw, 1633 }, 1634 .num_parents = 1, 1635 .flags = CLK_SET_RATE_PARENT, 1636 .ops = &clk_regmap_div_ro_ops, 1637 }, 1638 }; 1639 1640 static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = { 1641 .reg = 0x1c058, 1642 .shift = 0, 1643 .width = 4, 1644 .clkr.hw.init = &(const struct clk_init_data) { 1645 .name = "gcc_usb20_mock_utmi_postdiv_clk_src", 1646 .parent_hws = (const struct clk_hw*[]){ 1647 &gcc_usb20_mock_utmi_clk_src.clkr.hw, 1648 }, 1649 .num_parents = 1, 1650 .flags = CLK_SET_RATE_PARENT, 1651 .ops = &clk_regmap_div_ro_ops, 1652 }, 1653 }; 1654 1655 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1656 .reg = 0x1b058, 1657 .shift = 0, 1658 .width = 4, 1659 .clkr.hw.init = &(const struct clk_init_data) { 1660 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1661 .parent_hws = (const struct clk_hw*[]){ 1662 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1663 }, 1664 .num_parents = 1, 1665 .flags = CLK_SET_RATE_PARENT, 1666 .ops = &clk_regmap_div_ro_ops, 1667 }, 1668 }; 1669 1670 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = { 1671 .reg = 0x2f058, 1672 .shift = 0, 1673 .width = 4, 1674 .clkr.hw.init = &(const struct clk_init_data) { 1675 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src", 1676 .parent_hws = (const struct clk_hw*[]){ 1677 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, 1678 }, 1679 .num_parents = 1, 1680 .flags = CLK_SET_RATE_PARENT, 1681 .ops = &clk_regmap_div_ro_ops, 1682 }, 1683 }; 1684 1685 static struct clk_branch gcc_aggre_noc_qupv3_axi_clk = { 1686 .halt_reg = 0x8e200, 1687 .halt_check = BRANCH_HALT_VOTED, 1688 .hwcg_reg = 0x8e200, 1689 .hwcg_bit = 1, 1690 .clkr = { 1691 .enable_reg = 0x4b000, 1692 .enable_mask = BIT(28), 1693 .hw.init = &(const struct clk_init_data){ 1694 .name = "gcc_aggre_noc_qupv3_axi_clk", 1695 .ops = &clk_branch2_ops, 1696 }, 1697 }, 1698 }; 1699 1700 static struct clk_branch gcc_aggre_ufs_card_axi_clk = { 1701 .halt_reg = 0x810d4, 1702 .halt_check = BRANCH_HALT_VOTED, 1703 .hwcg_reg = 0x810d4, 1704 .hwcg_bit = 1, 1705 .clkr = { 1706 .enable_reg = 0x810d4, 1707 .enable_mask = BIT(0), 1708 .hw.init = &(const struct clk_init_data){ 1709 .name = "gcc_aggre_ufs_card_axi_clk", 1710 .parent_hws = (const struct clk_hw*[]){ 1711 &gcc_ufs_card_axi_clk_src.clkr.hw, 1712 }, 1713 .num_parents = 1, 1714 .flags = CLK_SET_RATE_PARENT, 1715 .ops = &clk_branch2_ops, 1716 }, 1717 }, 1718 }; 1719 1720 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1721 .halt_reg = 0x830d4, 1722 .halt_check = BRANCH_HALT_VOTED, 1723 .hwcg_reg = 0x830d4, 1724 .hwcg_bit = 1, 1725 .clkr = { 1726 .enable_reg = 0x830d4, 1727 .enable_mask = BIT(0), 1728 .hw.init = &(const struct clk_init_data){ 1729 .name = "gcc_aggre_ufs_phy_axi_clk", 1730 .parent_hws = (const struct clk_hw*[]){ 1731 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1732 }, 1733 .num_parents = 1, 1734 .flags = CLK_SET_RATE_PARENT, 1735 .ops = &clk_branch2_ops, 1736 }, 1737 }, 1738 }; 1739 1740 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { 1741 .halt_reg = 0x830d4, 1742 .halt_check = BRANCH_HALT_VOTED, 1743 .hwcg_reg = 0x830d4, 1744 .hwcg_bit = 1, 1745 .clkr = { 1746 .enable_reg = 0x830d4, 1747 .enable_mask = BIT(1), 1748 .hw.init = &(const struct clk_init_data){ 1749 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", 1750 .parent_hws = (const struct clk_hw*[]){ 1751 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1752 }, 1753 .num_parents = 1, 1754 .flags = CLK_SET_RATE_PARENT, 1755 .ops = &clk_branch2_ops, 1756 }, 1757 }, 1758 }; 1759 1760 static struct clk_branch gcc_aggre_usb2_prim_axi_clk = { 1761 .halt_reg = 0x1c05c, 1762 .halt_check = BRANCH_HALT_VOTED, 1763 .hwcg_reg = 0x1c05c, 1764 .hwcg_bit = 1, 1765 .clkr = { 1766 .enable_reg = 0x1c05c, 1767 .enable_mask = BIT(0), 1768 .hw.init = &(const struct clk_init_data){ 1769 .name = "gcc_aggre_usb2_prim_axi_clk", 1770 .parent_hws = (const struct clk_hw*[]){ 1771 &gcc_usb20_master_clk_src.clkr.hw, 1772 }, 1773 .num_parents = 1, 1774 .flags = CLK_SET_RATE_PARENT, 1775 .ops = &clk_branch2_ops, 1776 }, 1777 }, 1778 }; 1779 1780 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1781 .halt_reg = 0x1b084, 1782 .halt_check = BRANCH_HALT_VOTED, 1783 .hwcg_reg = 0x1b084, 1784 .hwcg_bit = 1, 1785 .clkr = { 1786 .enable_reg = 0x1b084, 1787 .enable_mask = BIT(0), 1788 .hw.init = &(const struct clk_init_data){ 1789 .name = "gcc_aggre_usb3_prim_axi_clk", 1790 .parent_hws = (const struct clk_hw*[]){ 1791 &gcc_usb30_prim_master_clk_src.clkr.hw, 1792 }, 1793 .num_parents = 1, 1794 .flags = CLK_SET_RATE_PARENT, 1795 .ops = &clk_branch2_ops, 1796 }, 1797 }, 1798 }; 1799 1800 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { 1801 .halt_reg = 0x2f088, 1802 .halt_check = BRANCH_HALT_VOTED, 1803 .hwcg_reg = 0x2f088, 1804 .hwcg_bit = 1, 1805 .clkr = { 1806 .enable_reg = 0x2f088, 1807 .enable_mask = BIT(0), 1808 .hw.init = &(const struct clk_init_data){ 1809 .name = "gcc_aggre_usb3_sec_axi_clk", 1810 .parent_hws = (const struct clk_hw*[]){ 1811 &gcc_usb30_sec_master_clk_src.clkr.hw, 1812 }, 1813 .num_parents = 1, 1814 .flags = CLK_SET_RATE_PARENT, 1815 .ops = &clk_branch2_ops, 1816 }, 1817 }, 1818 }; 1819 1820 static struct clk_branch gcc_ahb2phy0_clk = { 1821 .halt_reg = 0x76004, 1822 .halt_check = BRANCH_HALT_VOTED, 1823 .hwcg_reg = 0x76004, 1824 .hwcg_bit = 1, 1825 .clkr = { 1826 .enable_reg = 0x76004, 1827 .enable_mask = BIT(0), 1828 .hw.init = &(const struct clk_init_data){ 1829 .name = "gcc_ahb2phy0_clk", 1830 .ops = &clk_branch2_ops, 1831 }, 1832 }, 1833 }; 1834 1835 static struct clk_branch gcc_ahb2phy2_clk = { 1836 .halt_reg = 0x76008, 1837 .halt_check = BRANCH_HALT_VOTED, 1838 .hwcg_reg = 0x76008, 1839 .hwcg_bit = 1, 1840 .clkr = { 1841 .enable_reg = 0x76008, 1842 .enable_mask = BIT(0), 1843 .hw.init = &(const struct clk_init_data){ 1844 .name = "gcc_ahb2phy2_clk", 1845 .ops = &clk_branch2_ops, 1846 }, 1847 }, 1848 }; 1849 1850 static struct clk_branch gcc_ahb2phy3_clk = { 1851 .halt_reg = 0x7600c, 1852 .halt_check = BRANCH_HALT_VOTED, 1853 .hwcg_reg = 0x7600c, 1854 .hwcg_bit = 1, 1855 .clkr = { 1856 .enable_reg = 0x7600c, 1857 .enable_mask = BIT(0), 1858 .hw.init = &(const struct clk_init_data){ 1859 .name = "gcc_ahb2phy3_clk", 1860 .ops = &clk_branch2_ops, 1861 }, 1862 }, 1863 }; 1864 1865 static struct clk_branch gcc_boot_rom_ahb_clk = { 1866 .halt_reg = 0x44004, 1867 .halt_check = BRANCH_HALT_VOTED, 1868 .hwcg_reg = 0x44004, 1869 .hwcg_bit = 1, 1870 .clkr = { 1871 .enable_reg = 0x4b000, 1872 .enable_mask = BIT(10), 1873 .hw.init = &(const struct clk_init_data){ 1874 .name = "gcc_boot_rom_ahb_clk", 1875 .ops = &clk_branch2_ops, 1876 }, 1877 }, 1878 }; 1879 1880 static struct clk_branch gcc_camera_hf_axi_clk = { 1881 .halt_reg = 0x32010, 1882 .halt_check = BRANCH_HALT_SKIP, 1883 .hwcg_reg = 0x32010, 1884 .hwcg_bit = 1, 1885 .clkr = { 1886 .enable_reg = 0x32010, 1887 .enable_mask = BIT(0), 1888 .hw.init = &(const struct clk_init_data){ 1889 .name = "gcc_camera_hf_axi_clk", 1890 .ops = &clk_branch2_ops, 1891 }, 1892 }, 1893 }; 1894 1895 static struct clk_branch gcc_camera_sf_axi_clk = { 1896 .halt_reg = 0x32018, 1897 .halt_check = BRANCH_HALT_SKIP, 1898 .hwcg_reg = 0x32018, 1899 .hwcg_bit = 1, 1900 .clkr = { 1901 .enable_reg = 0x32018, 1902 .enable_mask = BIT(0), 1903 .hw.init = &(const struct clk_init_data){ 1904 .name = "gcc_camera_sf_axi_clk", 1905 .ops = &clk_branch2_ops, 1906 }, 1907 }, 1908 }; 1909 1910 static struct clk_branch gcc_camera_throttle_xo_clk = { 1911 .halt_reg = 0x32024, 1912 .halt_check = BRANCH_HALT, 1913 .clkr = { 1914 .enable_reg = 0x32024, 1915 .enable_mask = BIT(0), 1916 .hw.init = &(const struct clk_init_data){ 1917 .name = "gcc_camera_throttle_xo_clk", 1918 .ops = &clk_branch2_ops, 1919 }, 1920 }, 1921 }; 1922 1923 static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = { 1924 .halt_reg = 0x1c060, 1925 .halt_check = BRANCH_HALT_VOTED, 1926 .hwcg_reg = 0x1c060, 1927 .hwcg_bit = 1, 1928 .clkr = { 1929 .enable_reg = 0x1c060, 1930 .enable_mask = BIT(0), 1931 .hw.init = &(const struct clk_init_data){ 1932 .name = "gcc_cfg_noc_usb2_prim_axi_clk", 1933 .parent_hws = (const struct clk_hw*[]){ 1934 &gcc_usb20_master_clk_src.clkr.hw, 1935 }, 1936 .num_parents = 1, 1937 .flags = CLK_SET_RATE_PARENT, 1938 .ops = &clk_branch2_ops, 1939 }, 1940 }, 1941 }; 1942 1943 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1944 .halt_reg = 0x1b088, 1945 .halt_check = BRANCH_HALT_VOTED, 1946 .hwcg_reg = 0x1b088, 1947 .hwcg_bit = 1, 1948 .clkr = { 1949 .enable_reg = 0x1b088, 1950 .enable_mask = BIT(0), 1951 .hw.init = &(const struct clk_init_data){ 1952 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1953 .parent_hws = (const struct clk_hw*[]){ 1954 &gcc_usb30_prim_master_clk_src.clkr.hw, 1955 }, 1956 .num_parents = 1, 1957 .flags = CLK_SET_RATE_PARENT, 1958 .ops = &clk_branch2_ops, 1959 }, 1960 }, 1961 }; 1962 1963 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { 1964 .halt_reg = 0x2f084, 1965 .halt_check = BRANCH_HALT_VOTED, 1966 .hwcg_reg = 0x2f084, 1967 .hwcg_bit = 1, 1968 .clkr = { 1969 .enable_reg = 0x2f084, 1970 .enable_mask = BIT(0), 1971 .hw.init = &(const struct clk_init_data){ 1972 .name = "gcc_cfg_noc_usb3_sec_axi_clk", 1973 .parent_hws = (const struct clk_hw*[]){ 1974 &gcc_usb30_sec_master_clk_src.clkr.hw, 1975 }, 1976 .num_parents = 1, 1977 .flags = CLK_SET_RATE_PARENT, 1978 .ops = &clk_branch2_ops, 1979 }, 1980 }, 1981 }; 1982 1983 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1984 .halt_reg = 0x7d164, 1985 .halt_check = BRANCH_HALT_VOTED, 1986 .hwcg_reg = 0x7d164, 1987 .hwcg_bit = 1, 1988 .clkr = { 1989 .enable_reg = 0x7d164, 1990 .enable_mask = BIT(0), 1991 .hw.init = &(const struct clk_init_data){ 1992 .name = "gcc_ddrss_gpu_axi_clk", 1993 .ops = &clk_branch2_aon_ops, 1994 }, 1995 }, 1996 }; 1997 1998 static struct clk_branch gcc_disp1_hf_axi_clk = { 1999 .halt_reg = 0xc7010, 2000 .halt_check = BRANCH_HALT_VOTED, 2001 .hwcg_reg = 0xc7010, 2002 .hwcg_bit = 1, 2003 .clkr = { 2004 .enable_reg = 0xc7010, 2005 .enable_mask = BIT(0), 2006 .hw.init = &(const struct clk_init_data){ 2007 .name = "gcc_disp1_hf_axi_clk", 2008 .ops = &clk_branch2_ops, 2009 }, 2010 }, 2011 }; 2012 2013 static struct clk_branch gcc_disp_hf_axi_clk = { 2014 .halt_reg = 0x33010, 2015 .halt_check = BRANCH_HALT_VOTED, 2016 .hwcg_reg = 0x33010, 2017 .hwcg_bit = 1, 2018 .clkr = { 2019 .enable_reg = 0x33010, 2020 .enable_mask = BIT(0), 2021 .hw.init = &(const struct clk_init_data){ 2022 .name = "gcc_disp_hf_axi_clk", 2023 .ops = &clk_branch2_ops, 2024 }, 2025 }, 2026 }; 2027 2028 static struct clk_branch gcc_edp_ref_clkref_en = { 2029 .halt_reg = 0x97448, 2030 .halt_check = BRANCH_HALT_DELAY, 2031 .clkr = { 2032 .enable_reg = 0x97448, 2033 .enable_mask = BIT(0), 2034 .hw.init = &(const struct clk_init_data){ 2035 .name = "gcc_edp_ref_clkref_en", 2036 .ops = &clk_branch2_ops, 2037 }, 2038 }, 2039 }; 2040 2041 static struct clk_branch gcc_emac0_axi_clk = { 2042 .halt_reg = 0xb6018, 2043 .halt_check = BRANCH_HALT_VOTED, 2044 .hwcg_reg = 0xb6018, 2045 .hwcg_bit = 1, 2046 .clkr = { 2047 .enable_reg = 0xb6018, 2048 .enable_mask = BIT(0), 2049 .hw.init = &(const struct clk_init_data){ 2050 .name = "gcc_emac0_axi_clk", 2051 .ops = &clk_branch2_ops, 2052 }, 2053 }, 2054 }; 2055 2056 static struct clk_branch gcc_emac0_phy_aux_clk = { 2057 .halt_reg = 0xb6024, 2058 .halt_check = BRANCH_HALT, 2059 .clkr = { 2060 .enable_reg = 0xb6024, 2061 .enable_mask = BIT(0), 2062 .hw.init = &(const struct clk_init_data){ 2063 .name = "gcc_emac0_phy_aux_clk", 2064 .parent_hws = (const struct clk_hw*[]){ 2065 &gcc_emac0_phy_aux_clk_src.clkr.hw, 2066 }, 2067 .num_parents = 1, 2068 .flags = CLK_SET_RATE_PARENT, 2069 .ops = &clk_branch2_ops, 2070 }, 2071 }, 2072 }; 2073 2074 static struct clk_branch gcc_emac0_ptp_clk = { 2075 .halt_reg = 0xb6040, 2076 .halt_check = BRANCH_HALT, 2077 .clkr = { 2078 .enable_reg = 0xb6040, 2079 .enable_mask = BIT(0), 2080 .hw.init = &(const struct clk_init_data){ 2081 .name = "gcc_emac0_ptp_clk", 2082 .parent_hws = (const struct clk_hw*[]){ 2083 &gcc_emac0_ptp_clk_src.clkr.hw, 2084 }, 2085 .num_parents = 1, 2086 .flags = CLK_SET_RATE_PARENT, 2087 .ops = &clk_branch2_ops, 2088 }, 2089 }, 2090 }; 2091 2092 static struct clk_branch gcc_emac0_rgmii_clk = { 2093 .halt_reg = 0xb6044, 2094 .halt_check = BRANCH_HALT, 2095 .clkr = { 2096 .enable_reg = 0xb6044, 2097 .enable_mask = BIT(0), 2098 .hw.init = &(const struct clk_init_data){ 2099 .name = "gcc_emac0_rgmii_clk", 2100 .parent_hws = (const struct clk_hw*[]){ 2101 &gcc_emac0_rgmii_clk_src.clkr.hw, 2102 }, 2103 .num_parents = 1, 2104 .flags = CLK_SET_RATE_PARENT, 2105 .ops = &clk_branch2_ops, 2106 }, 2107 }, 2108 }; 2109 2110 static struct clk_branch gcc_emac0_slv_ahb_clk = { 2111 .halt_reg = 0xb6020, 2112 .halt_check = BRANCH_HALT_VOTED, 2113 .hwcg_reg = 0xb6020, 2114 .hwcg_bit = 1, 2115 .clkr = { 2116 .enable_reg = 0xb6020, 2117 .enable_mask = BIT(0), 2118 .hw.init = &(const struct clk_init_data){ 2119 .name = "gcc_emac0_slv_ahb_clk", 2120 .ops = &clk_branch2_ops, 2121 }, 2122 }, 2123 }; 2124 2125 static struct clk_branch gcc_emac1_axi_clk = { 2126 .halt_reg = 0xb4018, 2127 .halt_check = BRANCH_HALT_VOTED, 2128 .hwcg_reg = 0xb4018, 2129 .hwcg_bit = 1, 2130 .clkr = { 2131 .enable_reg = 0xb4018, 2132 .enable_mask = BIT(0), 2133 .hw.init = &(const struct clk_init_data){ 2134 .name = "gcc_emac1_axi_clk", 2135 .ops = &clk_branch2_ops, 2136 }, 2137 }, 2138 }; 2139 2140 static struct clk_branch gcc_emac1_phy_aux_clk = { 2141 .halt_reg = 0xb4024, 2142 .halt_check = BRANCH_HALT, 2143 .clkr = { 2144 .enable_reg = 0xb4024, 2145 .enable_mask = BIT(0), 2146 .hw.init = &(const struct clk_init_data){ 2147 .name = "gcc_emac1_phy_aux_clk", 2148 .parent_hws = (const struct clk_hw*[]){ 2149 &gcc_emac1_phy_aux_clk_src.clkr.hw, 2150 }, 2151 .num_parents = 1, 2152 .flags = CLK_SET_RATE_PARENT, 2153 .ops = &clk_branch2_ops, 2154 }, 2155 }, 2156 }; 2157 2158 static struct clk_branch gcc_emac1_ptp_clk = { 2159 .halt_reg = 0xb4040, 2160 .halt_check = BRANCH_HALT, 2161 .clkr = { 2162 .enable_reg = 0xb4040, 2163 .enable_mask = BIT(0), 2164 .hw.init = &(const struct clk_init_data){ 2165 .name = "gcc_emac1_ptp_clk", 2166 .parent_hws = (const struct clk_hw*[]){ 2167 &gcc_emac1_ptp_clk_src.clkr.hw, 2168 }, 2169 .num_parents = 1, 2170 .flags = CLK_SET_RATE_PARENT, 2171 .ops = &clk_branch2_ops, 2172 }, 2173 }, 2174 }; 2175 2176 static struct clk_branch gcc_emac1_rgmii_clk = { 2177 .halt_reg = 0xb4044, 2178 .halt_check = BRANCH_HALT, 2179 .clkr = { 2180 .enable_reg = 0xb4044, 2181 .enable_mask = BIT(0), 2182 .hw.init = &(const struct clk_init_data){ 2183 .name = "gcc_emac1_rgmii_clk", 2184 .parent_hws = (const struct clk_hw*[]){ 2185 &gcc_emac1_rgmii_clk_src.clkr.hw, 2186 }, 2187 .num_parents = 1, 2188 .flags = CLK_SET_RATE_PARENT, 2189 .ops = &clk_branch2_ops, 2190 }, 2191 }, 2192 }; 2193 2194 static struct clk_branch gcc_emac1_slv_ahb_clk = { 2195 .halt_reg = 0xb4020, 2196 .halt_check = BRANCH_HALT_VOTED, 2197 .hwcg_reg = 0xb4020, 2198 .hwcg_bit = 1, 2199 .clkr = { 2200 .enable_reg = 0xb4020, 2201 .enable_mask = BIT(0), 2202 .hw.init = &(const struct clk_init_data){ 2203 .name = "gcc_emac1_slv_ahb_clk", 2204 .ops = &clk_branch2_ops, 2205 }, 2206 }, 2207 }; 2208 2209 static struct clk_branch gcc_gp1_clk = { 2210 .halt_reg = 0x70000, 2211 .halt_check = BRANCH_HALT, 2212 .clkr = { 2213 .enable_reg = 0x70000, 2214 .enable_mask = BIT(0), 2215 .hw.init = &(const struct clk_init_data){ 2216 .name = "gcc_gp1_clk", 2217 .parent_hws = (const struct clk_hw*[]){ 2218 &gcc_gp1_clk_src.clkr.hw, 2219 }, 2220 .num_parents = 1, 2221 .flags = CLK_SET_RATE_PARENT, 2222 .ops = &clk_branch2_ops, 2223 }, 2224 }, 2225 }; 2226 2227 static struct clk_branch gcc_gp2_clk = { 2228 .halt_reg = 0x71000, 2229 .halt_check = BRANCH_HALT, 2230 .clkr = { 2231 .enable_reg = 0x71000, 2232 .enable_mask = BIT(0), 2233 .hw.init = &(const struct clk_init_data){ 2234 .name = "gcc_gp2_clk", 2235 .parent_hws = (const struct clk_hw*[]){ 2236 &gcc_gp2_clk_src.clkr.hw, 2237 }, 2238 .num_parents = 1, 2239 .flags = CLK_SET_RATE_PARENT, 2240 .ops = &clk_branch2_ops, 2241 }, 2242 }, 2243 }; 2244 2245 static struct clk_branch gcc_gp3_clk = { 2246 .halt_reg = 0x62000, 2247 .halt_check = BRANCH_HALT, 2248 .clkr = { 2249 .enable_reg = 0x62000, 2250 .enable_mask = BIT(0), 2251 .hw.init = &(const struct clk_init_data){ 2252 .name = "gcc_gp3_clk", 2253 .parent_hws = (const struct clk_hw*[]){ 2254 &gcc_gp3_clk_src.clkr.hw, 2255 }, 2256 .num_parents = 1, 2257 .flags = CLK_SET_RATE_PARENT, 2258 .ops = &clk_branch2_ops, 2259 }, 2260 }, 2261 }; 2262 2263 static struct clk_branch gcc_gp4_clk = { 2264 .halt_reg = 0x1e000, 2265 .halt_check = BRANCH_HALT, 2266 .clkr = { 2267 .enable_reg = 0x1e000, 2268 .enable_mask = BIT(0), 2269 .hw.init = &(const struct clk_init_data){ 2270 .name = "gcc_gp4_clk", 2271 .parent_hws = (const struct clk_hw*[]){ 2272 &gcc_gp4_clk_src.clkr.hw, 2273 }, 2274 .num_parents = 1, 2275 .flags = CLK_SET_RATE_PARENT, 2276 .ops = &clk_branch2_ops, 2277 }, 2278 }, 2279 }; 2280 2281 static struct clk_branch gcc_gp5_clk = { 2282 .halt_reg = 0x1f000, 2283 .halt_check = BRANCH_HALT, 2284 .clkr = { 2285 .enable_reg = 0x1f000, 2286 .enable_mask = BIT(0), 2287 .hw.init = &(const struct clk_init_data){ 2288 .name = "gcc_gp5_clk", 2289 .parent_hws = (const struct clk_hw*[]){ 2290 &gcc_gp5_clk_src.clkr.hw, 2291 }, 2292 .num_parents = 1, 2293 .flags = CLK_SET_RATE_PARENT, 2294 .ops = &clk_branch2_ops, 2295 }, 2296 }, 2297 }; 2298 2299 static struct clk_branch gcc_gpu_gpll0_clk_src = { 2300 .halt_check = BRANCH_HALT_DELAY, 2301 .clkr = { 2302 .enable_reg = 0x4b000, 2303 .enable_mask = BIT(15), 2304 .hw.init = &(const struct clk_init_data){ 2305 .name = "gcc_gpu_gpll0_clk_src", 2306 .parent_hws = (const struct clk_hw*[]){ 2307 &gcc_gpll0.clkr.hw, 2308 }, 2309 .num_parents = 1, 2310 .flags = CLK_SET_RATE_PARENT, 2311 .ops = &clk_branch2_ops, 2312 }, 2313 }, 2314 }; 2315 2316 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 2317 .halt_check = BRANCH_HALT_DELAY, 2318 .clkr = { 2319 .enable_reg = 0x4b000, 2320 .enable_mask = BIT(16), 2321 .hw.init = &(const struct clk_init_data){ 2322 .name = "gcc_gpu_gpll0_div_clk_src", 2323 .parent_hws = (const struct clk_hw*[]){ 2324 &gcc_gpll0_out_even.clkr.hw, 2325 }, 2326 .num_parents = 1, 2327 .flags = CLK_SET_RATE_PARENT, 2328 .ops = &clk_branch2_ops, 2329 }, 2330 }, 2331 }; 2332 2333 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 2334 .halt_reg = 0x7d010, 2335 .halt_check = BRANCH_HALT_VOTED, 2336 .hwcg_reg = 0x7d010, 2337 .hwcg_bit = 1, 2338 .clkr = { 2339 .enable_reg = 0x7d010, 2340 .enable_mask = BIT(0), 2341 .hw.init = &(const struct clk_init_data){ 2342 .name = "gcc_gpu_memnoc_gfx_clk", 2343 .ops = &clk_branch2_aon_ops, 2344 }, 2345 }, 2346 }; 2347 2348 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2349 .halt_reg = 0x7d01c, 2350 .halt_check = BRANCH_HALT_DELAY, 2351 .clkr = { 2352 .enable_reg = 0x7d01c, 2353 .enable_mask = BIT(0), 2354 .hw.init = &(const struct clk_init_data){ 2355 .name = "gcc_gpu_snoc_dvm_gfx_clk", 2356 .ops = &clk_branch2_aon_ops, 2357 }, 2358 }, 2359 }; 2360 2361 static struct clk_branch gcc_gpu_tcu_throttle_ahb_clk = { 2362 .halt_reg = 0x7d008, 2363 .halt_check = BRANCH_HALT_VOTED, 2364 .hwcg_reg = 0x7d008, 2365 .hwcg_bit = 1, 2366 .clkr = { 2367 .enable_reg = 0x7d008, 2368 .enable_mask = BIT(0), 2369 .hw.init = &(const struct clk_init_data){ 2370 .name = "gcc_gpu_tcu_throttle_ahb_clk", 2371 .ops = &clk_branch2_ops, 2372 }, 2373 }, 2374 }; 2375 2376 static struct clk_branch gcc_gpu_tcu_throttle_clk = { 2377 .halt_reg = 0x7d014, 2378 .halt_check = BRANCH_HALT_VOTED, 2379 .hwcg_reg = 0x7d014, 2380 .hwcg_bit = 1, 2381 .clkr = { 2382 .enable_reg = 0x7d014, 2383 .enable_mask = BIT(0), 2384 .hw.init = &(const struct clk_init_data){ 2385 .name = "gcc_gpu_tcu_throttle_clk", 2386 .ops = &clk_branch2_ops, 2387 }, 2388 }, 2389 }; 2390 2391 static struct clk_branch gcc_pcie_0_aux_clk = { 2392 .halt_reg = 0xa9038, 2393 .halt_check = BRANCH_HALT_VOTED, 2394 .clkr = { 2395 .enable_reg = 0x4b010, 2396 .enable_mask = BIT(16), 2397 .hw.init = &(const struct clk_init_data){ 2398 .name = "gcc_pcie_0_aux_clk", 2399 .parent_hws = (const struct clk_hw*[]){ 2400 &gcc_pcie_0_aux_clk_src.clkr.hw, 2401 }, 2402 .num_parents = 1, 2403 .flags = CLK_SET_RATE_PARENT, 2404 .ops = &clk_branch2_ops, 2405 }, 2406 }, 2407 }; 2408 2409 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 2410 .halt_reg = 0xa902c, 2411 .halt_check = BRANCH_HALT_VOTED, 2412 .hwcg_reg = 0xa902c, 2413 .hwcg_bit = 1, 2414 .clkr = { 2415 .enable_reg = 0x4b010, 2416 .enable_mask = BIT(12), 2417 .hw.init = &(const struct clk_init_data){ 2418 .name = "gcc_pcie_0_cfg_ahb_clk", 2419 .ops = &clk_branch2_ops, 2420 }, 2421 }, 2422 }; 2423 2424 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 2425 .halt_reg = 0xa9024, 2426 .halt_check = BRANCH_HALT_VOTED, 2427 .clkr = { 2428 .enable_reg = 0x4b010, 2429 .enable_mask = BIT(11), 2430 .hw.init = &(const struct clk_init_data){ 2431 .name = "gcc_pcie_0_mstr_axi_clk", 2432 .ops = &clk_branch2_ops, 2433 }, 2434 }, 2435 }; 2436 2437 static struct clk_branch gcc_pcie_0_phy_aux_clk = { 2438 .halt_reg = 0xa9030, 2439 .halt_check = BRANCH_HALT_VOTED, 2440 .clkr = { 2441 .enable_reg = 0x4b010, 2442 .enable_mask = BIT(13), 2443 .hw.init = &(const struct clk_init_data){ 2444 .name = "gcc_pcie_0_phy_aux_clk", 2445 .parent_hws = (const struct clk_hw*[]){ 2446 &gcc_pcie_0_phy_aux_clk_src.clkr.hw, 2447 }, 2448 .num_parents = 1, 2449 .flags = CLK_SET_RATE_PARENT, 2450 .ops = &clk_branch2_ops, 2451 }, 2452 }, 2453 }; 2454 2455 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 2456 .halt_reg = 0xa9050, 2457 .halt_check = BRANCH_HALT_VOTED, 2458 .clkr = { 2459 .enable_reg = 0x4b010, 2460 .enable_mask = BIT(15), 2461 .hw.init = &(const struct clk_init_data){ 2462 .name = "gcc_pcie_0_phy_rchng_clk", 2463 .parent_hws = (const struct clk_hw*[]){ 2464 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 2465 }, 2466 .num_parents = 1, 2467 .flags = CLK_SET_RATE_PARENT, 2468 .ops = &clk_branch2_ops, 2469 }, 2470 }, 2471 }; 2472 2473 static struct clk_branch gcc_pcie_0_pipe_clk = { 2474 .halt_reg = 0xa9040, 2475 .halt_check = BRANCH_HALT_SKIP, 2476 .clkr = { 2477 .enable_reg = 0x4b010, 2478 .enable_mask = BIT(14), 2479 .hw.init = &(const struct clk_init_data){ 2480 .name = "gcc_pcie_0_pipe_clk", 2481 .parent_hws = (const struct clk_hw*[]){ 2482 &gcc_pcie_0_pipe_clk_src.clkr.hw, 2483 }, 2484 .num_parents = 1, 2485 .flags = CLK_SET_RATE_PARENT, 2486 .ops = &clk_branch2_ops, 2487 }, 2488 }, 2489 }; 2490 2491 static struct clk_branch gcc_pcie_0_pipediv2_clk = { 2492 .halt_reg = 0xa9048, 2493 .halt_check = BRANCH_HALT_SKIP, 2494 .clkr = { 2495 .enable_reg = 0x4b018, 2496 .enable_mask = BIT(22), 2497 .hw.init = &(const struct clk_init_data){ 2498 .name = "gcc_pcie_0_pipediv2_clk", 2499 .parent_hws = (const struct clk_hw*[]){ 2500 &gcc_pcie_0_pipe_div_clk_src.clkr.hw, 2501 }, 2502 .num_parents = 1, 2503 .flags = CLK_SET_RATE_PARENT, 2504 .ops = &clk_branch2_ops, 2505 }, 2506 }, 2507 }; 2508 2509 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 2510 .halt_reg = 0xa901c, 2511 .halt_check = BRANCH_HALT_VOTED, 2512 .clkr = { 2513 .enable_reg = 0x4b010, 2514 .enable_mask = BIT(10), 2515 .hw.init = &(const struct clk_init_data){ 2516 .name = "gcc_pcie_0_slv_axi_clk", 2517 .ops = &clk_branch2_ops, 2518 }, 2519 }, 2520 }; 2521 2522 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 2523 .halt_reg = 0xa9018, 2524 .halt_check = BRANCH_HALT_VOTED, 2525 .clkr = { 2526 .enable_reg = 0x4b018, 2527 .enable_mask = BIT(12), 2528 .hw.init = &(const struct clk_init_data){ 2529 .name = "gcc_pcie_0_slv_q2a_axi_clk", 2530 .ops = &clk_branch2_ops, 2531 }, 2532 }, 2533 }; 2534 2535 static struct clk_branch gcc_pcie_1_aux_clk = { 2536 .halt_reg = 0x77038, 2537 .halt_check = BRANCH_HALT_VOTED, 2538 .clkr = { 2539 .enable_reg = 0x4b000, 2540 .enable_mask = BIT(31), 2541 .hw.init = &(const struct clk_init_data){ 2542 .name = "gcc_pcie_1_aux_clk", 2543 .parent_hws = (const struct clk_hw*[]){ 2544 &gcc_pcie_1_aux_clk_src.clkr.hw, 2545 }, 2546 .num_parents = 1, 2547 .flags = CLK_SET_RATE_PARENT, 2548 .ops = &clk_branch2_ops, 2549 }, 2550 }, 2551 }; 2552 2553 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 2554 .halt_reg = 0x7702c, 2555 .halt_check = BRANCH_HALT_VOTED, 2556 .hwcg_reg = 0x7702c, 2557 .hwcg_bit = 1, 2558 .clkr = { 2559 .enable_reg = 0x4b008, 2560 .enable_mask = BIT(2), 2561 .hw.init = &(const struct clk_init_data){ 2562 .name = "gcc_pcie_1_cfg_ahb_clk", 2563 .ops = &clk_branch2_ops, 2564 }, 2565 }, 2566 }; 2567 2568 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 2569 .halt_reg = 0x77024, 2570 .halt_check = BRANCH_HALT_VOTED, 2571 .clkr = { 2572 .enable_reg = 0x4b008, 2573 .enable_mask = BIT(1), 2574 .hw.init = &(const struct clk_init_data){ 2575 .name = "gcc_pcie_1_mstr_axi_clk", 2576 .ops = &clk_branch2_ops, 2577 }, 2578 }, 2579 }; 2580 2581 static struct clk_branch gcc_pcie_1_phy_aux_clk = { 2582 .halt_reg = 0x77030, 2583 .halt_check = BRANCH_HALT_VOTED, 2584 .clkr = { 2585 .enable_reg = 0x4b008, 2586 .enable_mask = BIT(3), 2587 .hw.init = &(const struct clk_init_data){ 2588 .name = "gcc_pcie_1_phy_aux_clk", 2589 .parent_hws = (const struct clk_hw*[]){ 2590 &gcc_pcie_1_phy_aux_clk_src.clkr.hw, 2591 }, 2592 .num_parents = 1, 2593 .flags = CLK_SET_RATE_PARENT, 2594 .ops = &clk_branch2_ops, 2595 }, 2596 }, 2597 }; 2598 2599 static struct clk_branch gcc_pcie_1_phy_rchng_clk = { 2600 .halt_reg = 0x77050, 2601 .halt_check = BRANCH_HALT_VOTED, 2602 .clkr = { 2603 .enable_reg = 0x4b000, 2604 .enable_mask = BIT(22), 2605 .hw.init = &(const struct clk_init_data){ 2606 .name = "gcc_pcie_1_phy_rchng_clk", 2607 .parent_hws = (const struct clk_hw*[]){ 2608 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 2609 }, 2610 .num_parents = 1, 2611 .flags = CLK_SET_RATE_PARENT, 2612 .ops = &clk_branch2_ops, 2613 }, 2614 }, 2615 }; 2616 2617 static struct clk_branch gcc_pcie_1_pipe_clk = { 2618 .halt_reg = 0x77040, 2619 .halt_check = BRANCH_HALT_SKIP, 2620 .clkr = { 2621 .enable_reg = 0x4b008, 2622 .enable_mask = BIT(4), 2623 .hw.init = &(const struct clk_init_data){ 2624 .name = "gcc_pcie_1_pipe_clk", 2625 .parent_hws = (const struct clk_hw*[]){ 2626 &gcc_pcie_1_pipe_clk_src.clkr.hw, 2627 }, 2628 .num_parents = 1, 2629 .flags = CLK_SET_RATE_PARENT, 2630 .ops = &clk_branch2_ops, 2631 }, 2632 }, 2633 }; 2634 2635 static struct clk_branch gcc_pcie_1_pipediv2_clk = { 2636 .halt_reg = 0x77048, 2637 .halt_check = BRANCH_HALT_SKIP, 2638 .clkr = { 2639 .enable_reg = 0x4b018, 2640 .enable_mask = BIT(16), 2641 .hw.init = &(const struct clk_init_data){ 2642 .name = "gcc_pcie_1_pipediv2_clk", 2643 .parent_hws = (const struct clk_hw*[]){ 2644 &gcc_pcie_1_pipe_div_clk_src.clkr.hw, 2645 }, 2646 .num_parents = 1, 2647 .flags = CLK_SET_RATE_PARENT, 2648 .ops = &clk_branch2_ops, 2649 }, 2650 }, 2651 }; 2652 2653 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 2654 .halt_reg = 0x7701c, 2655 .halt_check = BRANCH_HALT_VOTED, 2656 .clkr = { 2657 .enable_reg = 0x4b008, 2658 .enable_mask = BIT(0), 2659 .hw.init = &(const struct clk_init_data){ 2660 .name = "gcc_pcie_1_slv_axi_clk", 2661 .ops = &clk_branch2_ops, 2662 }, 2663 }, 2664 }; 2665 2666 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 2667 .halt_reg = 0x77018, 2668 .halt_check = BRANCH_HALT_VOTED, 2669 .clkr = { 2670 .enable_reg = 0x4b008, 2671 .enable_mask = BIT(5), 2672 .hw.init = &(const struct clk_init_data){ 2673 .name = "gcc_pcie_1_slv_q2a_axi_clk", 2674 .ops = &clk_branch2_ops, 2675 }, 2676 }, 2677 }; 2678 2679 static struct clk_branch gcc_pcie_clkref_en = { 2680 .halt_reg = 0x9746c, 2681 .halt_check = BRANCH_HALT_DELAY, 2682 .clkr = { 2683 .enable_reg = 0x9746c, 2684 .enable_mask = BIT(0), 2685 .hw.init = &(const struct clk_init_data){ 2686 .name = "gcc_pcie_clkref_en", 2687 .ops = &clk_branch2_ops, 2688 }, 2689 }, 2690 }; 2691 2692 static struct clk_branch gcc_pcie_throttle_cfg_clk = { 2693 .halt_reg = 0xb2034, 2694 .halt_check = BRANCH_HALT_VOTED, 2695 .clkr = { 2696 .enable_reg = 0x4b020, 2697 .enable_mask = BIT(15), 2698 .hw.init = &(const struct clk_init_data){ 2699 .name = "gcc_pcie_throttle_cfg_clk", 2700 .ops = &clk_branch2_ops, 2701 }, 2702 }, 2703 }; 2704 2705 static struct clk_branch gcc_pdm2_clk = { 2706 .halt_reg = 0x3f00c, 2707 .halt_check = BRANCH_HALT, 2708 .clkr = { 2709 .enable_reg = 0x3f00c, 2710 .enable_mask = BIT(0), 2711 .hw.init = &(const struct clk_init_data){ 2712 .name = "gcc_pdm2_clk", 2713 .parent_hws = (const struct clk_hw*[]){ 2714 &gcc_pdm2_clk_src.clkr.hw, 2715 }, 2716 .num_parents = 1, 2717 .flags = CLK_SET_RATE_PARENT, 2718 .ops = &clk_branch2_ops, 2719 }, 2720 }, 2721 }; 2722 2723 static struct clk_branch gcc_pdm_ahb_clk = { 2724 .halt_reg = 0x3f004, 2725 .halt_check = BRANCH_HALT_VOTED, 2726 .hwcg_reg = 0x3f004, 2727 .hwcg_bit = 1, 2728 .clkr = { 2729 .enable_reg = 0x3f004, 2730 .enable_mask = BIT(0), 2731 .hw.init = &(const struct clk_init_data){ 2732 .name = "gcc_pdm_ahb_clk", 2733 .ops = &clk_branch2_ops, 2734 }, 2735 }, 2736 }; 2737 2738 static struct clk_branch gcc_pdm_xo4_clk = { 2739 .halt_reg = 0x3f008, 2740 .halt_check = BRANCH_HALT, 2741 .clkr = { 2742 .enable_reg = 0x3f008, 2743 .enable_mask = BIT(0), 2744 .hw.init = &(const struct clk_init_data){ 2745 .name = "gcc_pdm_xo4_clk", 2746 .ops = &clk_branch2_ops, 2747 }, 2748 }, 2749 }; 2750 2751 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2752 .halt_reg = 0x32008, 2753 .halt_check = BRANCH_HALT_VOTED, 2754 .hwcg_reg = 0x32008, 2755 .hwcg_bit = 1, 2756 .clkr = { 2757 .enable_reg = 0x32008, 2758 .enable_mask = BIT(0), 2759 .hw.init = &(const struct clk_init_data){ 2760 .name = "gcc_qmip_camera_nrt_ahb_clk", 2761 .ops = &clk_branch2_ops, 2762 }, 2763 }, 2764 }; 2765 2766 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2767 .halt_reg = 0x3200c, 2768 .halt_check = BRANCH_HALT_VOTED, 2769 .hwcg_reg = 0x3200c, 2770 .hwcg_bit = 1, 2771 .clkr = { 2772 .enable_reg = 0x3200c, 2773 .enable_mask = BIT(0), 2774 .hw.init = &(const struct clk_init_data){ 2775 .name = "gcc_qmip_camera_rt_ahb_clk", 2776 .ops = &clk_branch2_ops, 2777 }, 2778 }, 2779 }; 2780 2781 static struct clk_branch gcc_qmip_disp1_ahb_clk = { 2782 .halt_reg = 0xc7008, 2783 .halt_check = BRANCH_HALT_VOTED, 2784 .hwcg_reg = 0xc7008, 2785 .hwcg_bit = 1, 2786 .clkr = { 2787 .enable_reg = 0xc7008, 2788 .enable_mask = BIT(0), 2789 .hw.init = &(const struct clk_init_data){ 2790 .name = "gcc_qmip_disp1_ahb_clk", 2791 .ops = &clk_branch2_ops, 2792 }, 2793 }, 2794 }; 2795 2796 static struct clk_branch gcc_qmip_disp1_rot_ahb_clk = { 2797 .halt_reg = 0xc700c, 2798 .halt_check = BRANCH_HALT_VOTED, 2799 .clkr = { 2800 .enable_reg = 0xc700c, 2801 .enable_mask = BIT(0), 2802 .hw.init = &(const struct clk_init_data){ 2803 .name = "gcc_qmip_disp1_rot_ahb_clk", 2804 .ops = &clk_branch2_ops, 2805 }, 2806 }, 2807 }; 2808 2809 static struct clk_branch gcc_qmip_disp_ahb_clk = { 2810 .halt_reg = 0x33008, 2811 .halt_check = BRANCH_HALT_VOTED, 2812 .hwcg_reg = 0x33008, 2813 .hwcg_bit = 1, 2814 .clkr = { 2815 .enable_reg = 0x33008, 2816 .enable_mask = BIT(0), 2817 .hw.init = &(const struct clk_init_data){ 2818 .name = "gcc_qmip_disp_ahb_clk", 2819 .ops = &clk_branch2_ops, 2820 }, 2821 }, 2822 }; 2823 2824 static struct clk_branch gcc_qmip_disp_rot_ahb_clk = { 2825 .halt_reg = 0x3300c, 2826 .halt_check = BRANCH_HALT_VOTED, 2827 .clkr = { 2828 .enable_reg = 0x3300c, 2829 .enable_mask = BIT(0), 2830 .hw.init = &(const struct clk_init_data){ 2831 .name = "gcc_qmip_disp_rot_ahb_clk", 2832 .ops = &clk_branch2_ops, 2833 }, 2834 }, 2835 }; 2836 2837 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 2838 .halt_reg = 0x34008, 2839 .halt_check = BRANCH_HALT_VOTED, 2840 .hwcg_reg = 0x34008, 2841 .hwcg_bit = 1, 2842 .clkr = { 2843 .enable_reg = 0x34008, 2844 .enable_mask = BIT(0), 2845 .hw.init = &(const struct clk_init_data){ 2846 .name = "gcc_qmip_video_cvp_ahb_clk", 2847 .ops = &clk_branch2_ops, 2848 }, 2849 }, 2850 }; 2851 2852 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2853 .halt_reg = 0x3400c, 2854 .halt_check = BRANCH_HALT_VOTED, 2855 .hwcg_reg = 0x3400c, 2856 .hwcg_bit = 1, 2857 .clkr = { 2858 .enable_reg = 0x3400c, 2859 .enable_mask = BIT(0), 2860 .hw.init = &(const struct clk_init_data){ 2861 .name = "gcc_qmip_video_vcodec_ahb_clk", 2862 .ops = &clk_branch2_ops, 2863 }, 2864 }, 2865 }; 2866 2867 static struct clk_branch gcc_qmip_video_vcpu_ahb_clk = { 2868 .halt_reg = 0x34010, 2869 .halt_check = BRANCH_HALT_VOTED, 2870 .hwcg_reg = 0x34010, 2871 .hwcg_bit = 1, 2872 .clkr = { 2873 .enable_reg = 0x34010, 2874 .enable_mask = BIT(0), 2875 .hw.init = &(const struct clk_init_data){ 2876 .name = "gcc_qmip_video_vcpu_ahb_clk", 2877 .ops = &clk_branch2_ops, 2878 }, 2879 }, 2880 }; 2881 2882 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2883 .halt_reg = 0x23018, 2884 .halt_check = BRANCH_HALT_VOTED, 2885 .clkr = { 2886 .enable_reg = 0x4b008, 2887 .enable_mask = BIT(9), 2888 .hw.init = &(const struct clk_init_data){ 2889 .name = "gcc_qupv3_wrap0_core_2x_clk", 2890 .ops = &clk_branch2_ops, 2891 }, 2892 }, 2893 }; 2894 2895 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2896 .halt_reg = 0x2300c, 2897 .halt_check = BRANCH_HALT_VOTED, 2898 .clkr = { 2899 .enable_reg = 0x4b008, 2900 .enable_mask = BIT(8), 2901 .hw.init = &(const struct clk_init_data){ 2902 .name = "gcc_qupv3_wrap0_core_clk", 2903 .ops = &clk_branch2_ops, 2904 }, 2905 }, 2906 }; 2907 2908 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2909 .halt_reg = 0x2314c, 2910 .halt_check = BRANCH_HALT_VOTED, 2911 .clkr = { 2912 .enable_reg = 0x4b008, 2913 .enable_mask = BIT(10), 2914 .hw.init = &(const struct clk_init_data){ 2915 .name = "gcc_qupv3_wrap0_s0_clk", 2916 .parent_hws = (const struct clk_hw*[]){ 2917 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 2918 }, 2919 .num_parents = 1, 2920 .flags = CLK_SET_RATE_PARENT, 2921 .ops = &clk_branch2_ops, 2922 }, 2923 }, 2924 }; 2925 2926 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2927 .halt_reg = 0x23280, 2928 .halt_check = BRANCH_HALT_VOTED, 2929 .clkr = { 2930 .enable_reg = 0x4b008, 2931 .enable_mask = BIT(11), 2932 .hw.init = &(const struct clk_init_data){ 2933 .name = "gcc_qupv3_wrap0_s1_clk", 2934 .parent_hws = (const struct clk_hw*[]){ 2935 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 2936 }, 2937 .num_parents = 1, 2938 .flags = CLK_SET_RATE_PARENT, 2939 .ops = &clk_branch2_ops, 2940 }, 2941 }, 2942 }; 2943 2944 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2945 .halt_reg = 0x233b4, 2946 .halt_check = BRANCH_HALT_VOTED, 2947 .clkr = { 2948 .enable_reg = 0x4b008, 2949 .enable_mask = BIT(12), 2950 .hw.init = &(const struct clk_init_data){ 2951 .name = "gcc_qupv3_wrap0_s2_clk", 2952 .parent_hws = (const struct clk_hw*[]){ 2953 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2954 }, 2955 .num_parents = 1, 2956 .flags = CLK_SET_RATE_PARENT, 2957 .ops = &clk_branch2_ops, 2958 }, 2959 }, 2960 }; 2961 2962 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2963 .halt_reg = 0x234e8, 2964 .halt_check = BRANCH_HALT_VOTED, 2965 .clkr = { 2966 .enable_reg = 0x4b008, 2967 .enable_mask = BIT(13), 2968 .hw.init = &(const struct clk_init_data){ 2969 .name = "gcc_qupv3_wrap0_s3_clk", 2970 .parent_hws = (const struct clk_hw*[]){ 2971 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2972 }, 2973 .num_parents = 1, 2974 .flags = CLK_SET_RATE_PARENT, 2975 .ops = &clk_branch2_ops, 2976 }, 2977 }, 2978 }; 2979 2980 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2981 .halt_reg = 0x2361c, 2982 .halt_check = BRANCH_HALT_VOTED, 2983 .clkr = { 2984 .enable_reg = 0x4b008, 2985 .enable_mask = BIT(14), 2986 .hw.init = &(const struct clk_init_data){ 2987 .name = "gcc_qupv3_wrap0_s4_clk", 2988 .parent_hws = (const struct clk_hw*[]){ 2989 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2990 }, 2991 .num_parents = 1, 2992 .flags = CLK_SET_RATE_PARENT, 2993 .ops = &clk_branch2_ops, 2994 }, 2995 }, 2996 }; 2997 2998 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2999 .halt_reg = 0x23750, 3000 .halt_check = BRANCH_HALT_VOTED, 3001 .clkr = { 3002 .enable_reg = 0x4b008, 3003 .enable_mask = BIT(15), 3004 .hw.init = &(const struct clk_init_data){ 3005 .name = "gcc_qupv3_wrap0_s5_clk", 3006 .parent_hws = (const struct clk_hw*[]){ 3007 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 3008 }, 3009 .num_parents = 1, 3010 .flags = CLK_SET_RATE_PARENT, 3011 .ops = &clk_branch2_ops, 3012 }, 3013 }, 3014 }; 3015 3016 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 3017 .halt_reg = 0x23884, 3018 .halt_check = BRANCH_HALT_VOTED, 3019 .clkr = { 3020 .enable_reg = 0x4b008, 3021 .enable_mask = BIT(16), 3022 .hw.init = &(const struct clk_init_data){ 3023 .name = "gcc_qupv3_wrap0_s6_clk", 3024 .parent_hws = (const struct clk_hw*[]){ 3025 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 3026 }, 3027 .num_parents = 1, 3028 .flags = CLK_SET_RATE_PARENT, 3029 .ops = &clk_branch2_ops, 3030 }, 3031 }, 3032 }; 3033 3034 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 3035 .halt_reg = 0x24018, 3036 .halt_check = BRANCH_HALT_VOTED, 3037 .clkr = { 3038 .enable_reg = 0x4b008, 3039 .enable_mask = BIT(18), 3040 .hw.init = &(const struct clk_init_data){ 3041 .name = "gcc_qupv3_wrap1_core_2x_clk", 3042 .ops = &clk_branch2_ops, 3043 }, 3044 }, 3045 }; 3046 3047 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 3048 .halt_reg = 0x2400c, 3049 .halt_check = BRANCH_HALT_VOTED, 3050 .clkr = { 3051 .enable_reg = 0x4b008, 3052 .enable_mask = BIT(19), 3053 .hw.init = &(const struct clk_init_data){ 3054 .name = "gcc_qupv3_wrap1_core_clk", 3055 .ops = &clk_branch2_ops, 3056 }, 3057 }, 3058 }; 3059 3060 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 3061 .halt_reg = 0x2414c, 3062 .halt_check = BRANCH_HALT_VOTED, 3063 .clkr = { 3064 .enable_reg = 0x4b008, 3065 .enable_mask = BIT(22), 3066 .hw.init = &(const struct clk_init_data){ 3067 .name = "gcc_qupv3_wrap1_s0_clk", 3068 .parent_hws = (const struct clk_hw*[]){ 3069 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 3070 }, 3071 .num_parents = 1, 3072 .flags = CLK_SET_RATE_PARENT, 3073 .ops = &clk_branch2_ops, 3074 }, 3075 }, 3076 }; 3077 3078 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 3079 .halt_reg = 0x24280, 3080 .halt_check = BRANCH_HALT_VOTED, 3081 .clkr = { 3082 .enable_reg = 0x4b008, 3083 .enable_mask = BIT(23), 3084 .hw.init = &(const struct clk_init_data){ 3085 .name = "gcc_qupv3_wrap1_s1_clk", 3086 .parent_hws = (const struct clk_hw*[]){ 3087 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 3088 }, 3089 .num_parents = 1, 3090 .flags = CLK_SET_RATE_PARENT, 3091 .ops = &clk_branch2_ops, 3092 }, 3093 }, 3094 }; 3095 3096 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 3097 .halt_reg = 0x243b4, 3098 .halt_check = BRANCH_HALT_VOTED, 3099 .clkr = { 3100 .enable_reg = 0x4b008, 3101 .enable_mask = BIT(24), 3102 .hw.init = &(const struct clk_init_data){ 3103 .name = "gcc_qupv3_wrap1_s2_clk", 3104 .parent_hws = (const struct clk_hw*[]){ 3105 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 3106 }, 3107 .num_parents = 1, 3108 .flags = CLK_SET_RATE_PARENT, 3109 .ops = &clk_branch2_ops, 3110 }, 3111 }, 3112 }; 3113 3114 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 3115 .halt_reg = 0x244e8, 3116 .halt_check = BRANCH_HALT_VOTED, 3117 .clkr = { 3118 .enable_reg = 0x4b008, 3119 .enable_mask = BIT(25), 3120 .hw.init = &(const struct clk_init_data){ 3121 .name = "gcc_qupv3_wrap1_s3_clk", 3122 .parent_hws = (const struct clk_hw*[]){ 3123 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 3124 }, 3125 .num_parents = 1, 3126 .flags = CLK_SET_RATE_PARENT, 3127 .ops = &clk_branch2_ops, 3128 }, 3129 }, 3130 }; 3131 3132 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 3133 .halt_reg = 0x2461c, 3134 .halt_check = BRANCH_HALT_VOTED, 3135 .clkr = { 3136 .enable_reg = 0x4b008, 3137 .enable_mask = BIT(26), 3138 .hw.init = &(const struct clk_init_data){ 3139 .name = "gcc_qupv3_wrap1_s4_clk", 3140 .parent_hws = (const struct clk_hw*[]){ 3141 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 3142 }, 3143 .num_parents = 1, 3144 .flags = CLK_SET_RATE_PARENT, 3145 .ops = &clk_branch2_ops, 3146 }, 3147 }, 3148 }; 3149 3150 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 3151 .halt_reg = 0x24750, 3152 .halt_check = BRANCH_HALT_VOTED, 3153 .clkr = { 3154 .enable_reg = 0x4b008, 3155 .enable_mask = BIT(27), 3156 .hw.init = &(const struct clk_init_data){ 3157 .name = "gcc_qupv3_wrap1_s5_clk", 3158 .parent_hws = (const struct clk_hw*[]){ 3159 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 3160 }, 3161 .num_parents = 1, 3162 .flags = CLK_SET_RATE_PARENT, 3163 .ops = &clk_branch2_ops, 3164 }, 3165 }, 3166 }; 3167 3168 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 3169 .halt_reg = 0x24884, 3170 .halt_check = BRANCH_HALT_VOTED, 3171 .clkr = { 3172 .enable_reg = 0x4b018, 3173 .enable_mask = BIT(27), 3174 .hw.init = &(const struct clk_init_data){ 3175 .name = "gcc_qupv3_wrap1_s6_clk", 3176 .parent_hws = (const struct clk_hw*[]){ 3177 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 3178 }, 3179 .num_parents = 1, 3180 .flags = CLK_SET_RATE_PARENT, 3181 .ops = &clk_branch2_ops, 3182 }, 3183 }, 3184 }; 3185 3186 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 3187 .halt_reg = 0x2a018, 3188 .halt_check = BRANCH_HALT_VOTED, 3189 .clkr = { 3190 .enable_reg = 0x4b010, 3191 .enable_mask = BIT(3), 3192 .hw.init = &(const struct clk_init_data){ 3193 .name = "gcc_qupv3_wrap2_core_2x_clk", 3194 .ops = &clk_branch2_ops, 3195 }, 3196 }, 3197 }; 3198 3199 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 3200 .halt_reg = 0x2a00c, 3201 .halt_check = BRANCH_HALT_VOTED, 3202 .clkr = { 3203 .enable_reg = 0x4b010, 3204 .enable_mask = BIT(0), 3205 .hw.init = &(const struct clk_init_data){ 3206 .name = "gcc_qupv3_wrap2_core_clk", 3207 .ops = &clk_branch2_ops, 3208 }, 3209 }, 3210 }; 3211 3212 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 3213 .halt_reg = 0x2a14c, 3214 .halt_check = BRANCH_HALT_VOTED, 3215 .clkr = { 3216 .enable_reg = 0x4b010, 3217 .enable_mask = BIT(4), 3218 .hw.init = &(const struct clk_init_data){ 3219 .name = "gcc_qupv3_wrap2_s0_clk", 3220 .parent_hws = (const struct clk_hw*[]){ 3221 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 3222 }, 3223 .num_parents = 1, 3224 .flags = CLK_SET_RATE_PARENT, 3225 .ops = &clk_branch2_ops, 3226 }, 3227 }, 3228 }; 3229 3230 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 3231 .halt_reg = 0x2a280, 3232 .halt_check = BRANCH_HALT_VOTED, 3233 .clkr = { 3234 .enable_reg = 0x4b010, 3235 .enable_mask = BIT(5), 3236 .hw.init = &(const struct clk_init_data){ 3237 .name = "gcc_qupv3_wrap2_s1_clk", 3238 .parent_hws = (const struct clk_hw*[]){ 3239 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 3240 }, 3241 .num_parents = 1, 3242 .flags = CLK_SET_RATE_PARENT, 3243 .ops = &clk_branch2_ops, 3244 }, 3245 }, 3246 }; 3247 3248 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 3249 .halt_reg = 0x2a3b4, 3250 .halt_check = BRANCH_HALT_VOTED, 3251 .clkr = { 3252 .enable_reg = 0x4b010, 3253 .enable_mask = BIT(6), 3254 .hw.init = &(const struct clk_init_data){ 3255 .name = "gcc_qupv3_wrap2_s2_clk", 3256 .parent_hws = (const struct clk_hw*[]){ 3257 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 3258 }, 3259 .num_parents = 1, 3260 .flags = CLK_SET_RATE_PARENT, 3261 .ops = &clk_branch2_ops, 3262 }, 3263 }, 3264 }; 3265 3266 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 3267 .halt_reg = 0x2a4e8, 3268 .halt_check = BRANCH_HALT_VOTED, 3269 .clkr = { 3270 .enable_reg = 0x4b010, 3271 .enable_mask = BIT(7), 3272 .hw.init = &(const struct clk_init_data){ 3273 .name = "gcc_qupv3_wrap2_s3_clk", 3274 .parent_hws = (const struct clk_hw*[]){ 3275 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 3276 }, 3277 .num_parents = 1, 3278 .flags = CLK_SET_RATE_PARENT, 3279 .ops = &clk_branch2_ops, 3280 }, 3281 }, 3282 }; 3283 3284 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 3285 .halt_reg = 0x2a61c, 3286 .halt_check = BRANCH_HALT_VOTED, 3287 .clkr = { 3288 .enable_reg = 0x4b010, 3289 .enable_mask = BIT(8), 3290 .hw.init = &(const struct clk_init_data){ 3291 .name = "gcc_qupv3_wrap2_s4_clk", 3292 .parent_hws = (const struct clk_hw*[]){ 3293 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 3294 }, 3295 .num_parents = 1, 3296 .flags = CLK_SET_RATE_PARENT, 3297 .ops = &clk_branch2_ops, 3298 }, 3299 }, 3300 }; 3301 3302 static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 3303 .halt_reg = 0x2a750, 3304 .halt_check = BRANCH_HALT_VOTED, 3305 .clkr = { 3306 .enable_reg = 0x4b010, 3307 .enable_mask = BIT(9), 3308 .hw.init = &(const struct clk_init_data){ 3309 .name = "gcc_qupv3_wrap2_s5_clk", 3310 .parent_hws = (const struct clk_hw*[]){ 3311 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 3312 }, 3313 .num_parents = 1, 3314 .flags = CLK_SET_RATE_PARENT, 3315 .ops = &clk_branch2_ops, 3316 }, 3317 }, 3318 }; 3319 3320 static struct clk_branch gcc_qupv3_wrap2_s6_clk = { 3321 .halt_reg = 0x2a884, 3322 .halt_check = BRANCH_HALT_VOTED, 3323 .clkr = { 3324 .enable_reg = 0x4b018, 3325 .enable_mask = BIT(29), 3326 .hw.init = &(const struct clk_init_data){ 3327 .name = "gcc_qupv3_wrap2_s6_clk", 3328 .parent_hws = (const struct clk_hw*[]){ 3329 &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, 3330 }, 3331 .num_parents = 1, 3332 .flags = CLK_SET_RATE_PARENT, 3333 .ops = &clk_branch2_ops, 3334 }, 3335 }, 3336 }; 3337 3338 static struct clk_branch gcc_qupv3_wrap3_core_2x_clk = { 3339 .halt_reg = 0xc4018, 3340 .halt_check = BRANCH_HALT_VOTED, 3341 .clkr = { 3342 .enable_reg = 0x4b000, 3343 .enable_mask = BIT(24), 3344 .hw.init = &(const struct clk_init_data){ 3345 .name = "gcc_qupv3_wrap3_core_2x_clk", 3346 .ops = &clk_branch2_ops, 3347 }, 3348 }, 3349 }; 3350 3351 static struct clk_branch gcc_qupv3_wrap3_core_clk = { 3352 .halt_reg = 0xc400c, 3353 .halt_check = BRANCH_HALT_VOTED, 3354 .clkr = { 3355 .enable_reg = 0x4b000, 3356 .enable_mask = BIT(23), 3357 .hw.init = &(const struct clk_init_data){ 3358 .name = "gcc_qupv3_wrap3_core_clk", 3359 .ops = &clk_branch2_ops, 3360 }, 3361 }, 3362 }; 3363 3364 static struct clk_branch gcc_qupv3_wrap3_qspi_clk = { 3365 .halt_reg = 0xc4280, 3366 .halt_check = BRANCH_HALT_VOTED, 3367 .clkr = { 3368 .enable_reg = 0x4b000, 3369 .enable_mask = BIT(26), 3370 .hw.init = &(const struct clk_init_data){ 3371 .name = "gcc_qupv3_wrap3_qspi_clk", 3372 .parent_hws = (const struct clk_hw*[]){ 3373 &gcc_qupv3_wrap3_s0_clk_src.clkr.hw, 3374 }, 3375 .num_parents = 1, 3376 .flags = CLK_SET_RATE_PARENT, 3377 .ops = &clk_branch2_ops, 3378 }, 3379 }, 3380 }; 3381 3382 static struct clk_branch gcc_qupv3_wrap3_s0_clk = { 3383 .halt_reg = 0xc414c, 3384 .halt_check = BRANCH_HALT_VOTED, 3385 .clkr = { 3386 .enable_reg = 0x4b000, 3387 .enable_mask = BIT(25), 3388 .hw.init = &(const struct clk_init_data){ 3389 .name = "gcc_qupv3_wrap3_s0_clk", 3390 .parent_hws = (const struct clk_hw*[]){ 3391 &gcc_qupv3_wrap3_s0_div_clk_src.clkr.hw, 3392 }, 3393 .num_parents = 1, 3394 .flags = CLK_SET_RATE_PARENT, 3395 .ops = &clk_branch2_ops, 3396 }, 3397 }, 3398 }; 3399 3400 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 3401 .halt_reg = 0x23004, 3402 .halt_check = BRANCH_HALT_VOTED, 3403 .hwcg_reg = 0x23004, 3404 .hwcg_bit = 1, 3405 .clkr = { 3406 .enable_reg = 0x4b008, 3407 .enable_mask = BIT(6), 3408 .hw.init = &(const struct clk_init_data){ 3409 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 3410 .ops = &clk_branch2_ops, 3411 }, 3412 }, 3413 }; 3414 3415 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 3416 .halt_reg = 0x23008, 3417 .halt_check = BRANCH_HALT_VOTED, 3418 .hwcg_reg = 0x23008, 3419 .hwcg_bit = 1, 3420 .clkr = { 3421 .enable_reg = 0x4b008, 3422 .enable_mask = BIT(7), 3423 .hw.init = &(const struct clk_init_data){ 3424 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 3425 .ops = &clk_branch2_ops, 3426 }, 3427 }, 3428 }; 3429 3430 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 3431 .halt_reg = 0x24004, 3432 .halt_check = BRANCH_HALT_VOTED, 3433 .hwcg_reg = 0x24004, 3434 .hwcg_bit = 1, 3435 .clkr = { 3436 .enable_reg = 0x4b008, 3437 .enable_mask = BIT(20), 3438 .hw.init = &(const struct clk_init_data){ 3439 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 3440 .ops = &clk_branch2_ops, 3441 }, 3442 }, 3443 }; 3444 3445 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 3446 .halt_reg = 0x24008, 3447 .halt_check = BRANCH_HALT_VOTED, 3448 .hwcg_reg = 0x24008, 3449 .hwcg_bit = 1, 3450 .clkr = { 3451 .enable_reg = 0x4b008, 3452 .enable_mask = BIT(21), 3453 .hw.init = &(const struct clk_init_data){ 3454 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 3455 .ops = &clk_branch2_ops, 3456 }, 3457 }, 3458 }; 3459 3460 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 3461 .halt_reg = 0x2a004, 3462 .halt_check = BRANCH_HALT_VOTED, 3463 .hwcg_reg = 0x2a004, 3464 .hwcg_bit = 1, 3465 .clkr = { 3466 .enable_reg = 0x4b010, 3467 .enable_mask = BIT(2), 3468 .hw.init = &(const struct clk_init_data){ 3469 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 3470 .ops = &clk_branch2_ops, 3471 }, 3472 }, 3473 }; 3474 3475 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 3476 .halt_reg = 0x2a008, 3477 .halt_check = BRANCH_HALT_VOTED, 3478 .hwcg_reg = 0x2a008, 3479 .hwcg_bit = 1, 3480 .clkr = { 3481 .enable_reg = 0x4b010, 3482 .enable_mask = BIT(1), 3483 .hw.init = &(const struct clk_init_data){ 3484 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 3485 .ops = &clk_branch2_ops, 3486 }, 3487 }, 3488 }; 3489 3490 static struct clk_branch gcc_qupv3_wrap_3_m_ahb_clk = { 3491 .halt_reg = 0xc4004, 3492 .halt_check = BRANCH_HALT_VOTED, 3493 .hwcg_reg = 0xc4004, 3494 .hwcg_bit = 1, 3495 .clkr = { 3496 .enable_reg = 0x4b000, 3497 .enable_mask = BIT(27), 3498 .hw.init = &(const struct clk_init_data){ 3499 .name = "gcc_qupv3_wrap_3_m_ahb_clk", 3500 .ops = &clk_branch2_ops, 3501 }, 3502 }, 3503 }; 3504 3505 static struct clk_branch gcc_qupv3_wrap_3_s_ahb_clk = { 3506 .halt_reg = 0xc4008, 3507 .halt_check = BRANCH_HALT_VOTED, 3508 .hwcg_reg = 0xc4008, 3509 .hwcg_bit = 1, 3510 .clkr = { 3511 .enable_reg = 0x4b000, 3512 .enable_mask = BIT(20), 3513 .hw.init = &(const struct clk_init_data){ 3514 .name = "gcc_qupv3_wrap_3_s_ahb_clk", 3515 .ops = &clk_branch2_ops, 3516 }, 3517 }, 3518 }; 3519 3520 static struct clk_branch gcc_sdcc1_ahb_clk = { 3521 .halt_reg = 0x2000c, 3522 .halt_check = BRANCH_HALT, 3523 .clkr = { 3524 .enable_reg = 0x2000c, 3525 .enable_mask = BIT(0), 3526 .hw.init = &(const struct clk_init_data){ 3527 .name = "gcc_sdcc1_ahb_clk", 3528 .ops = &clk_branch2_ops, 3529 }, 3530 }, 3531 }; 3532 3533 static struct clk_branch gcc_sdcc1_apps_clk = { 3534 .halt_reg = 0x20004, 3535 .halt_check = BRANCH_HALT, 3536 .clkr = { 3537 .enable_reg = 0x20004, 3538 .enable_mask = BIT(0), 3539 .hw.init = &(const struct clk_init_data){ 3540 .name = "gcc_sdcc1_apps_clk", 3541 .parent_hws = (const struct clk_hw*[]){ 3542 &gcc_sdcc1_apps_clk_src.clkr.hw, 3543 }, 3544 .num_parents = 1, 3545 .flags = CLK_SET_RATE_PARENT, 3546 .ops = &clk_branch2_ops, 3547 }, 3548 }, 3549 }; 3550 3551 static struct clk_branch gcc_sdcc1_ice_core_clk = { 3552 .halt_reg = 0x20044, 3553 .halt_check = BRANCH_HALT_VOTED, 3554 .hwcg_reg = 0x20044, 3555 .hwcg_bit = 1, 3556 .clkr = { 3557 .enable_reg = 0x20044, 3558 .enable_mask = BIT(0), 3559 .hw.init = &(const struct clk_init_data){ 3560 .name = "gcc_sdcc1_ice_core_clk", 3561 .parent_hws = (const struct clk_hw*[]){ 3562 &gcc_sdcc1_ice_core_clk_src.clkr.hw, 3563 }, 3564 .num_parents = 1, 3565 .flags = CLK_SET_RATE_PARENT, 3566 .ops = &clk_branch2_ops, 3567 }, 3568 }, 3569 }; 3570 3571 static struct clk_branch gcc_sgmi_clkref_en = { 3572 .halt_reg = 0x9c034, 3573 .halt_check = BRANCH_HALT_DELAY, 3574 .clkr = { 3575 .enable_reg = 0x9c034, 3576 .enable_mask = BIT(0), 3577 .hw.init = &(const struct clk_init_data){ 3578 .name = "gcc_sgmi_clkref_en", 3579 .ops = &clk_branch2_ops, 3580 }, 3581 }, 3582 }; 3583 3584 static struct clk_branch gcc_tscss_ahb_clk = { 3585 .halt_reg = 0x21024, 3586 .halt_check = BRANCH_HALT, 3587 .clkr = { 3588 .enable_reg = 0x21024, 3589 .enable_mask = BIT(0), 3590 .hw.init = &(const struct clk_init_data){ 3591 .name = "gcc_tscss_ahb_clk", 3592 .ops = &clk_branch2_ops, 3593 }, 3594 }, 3595 }; 3596 3597 static struct clk_branch gcc_tscss_etu_clk = { 3598 .halt_reg = 0x21020, 3599 .halt_check = BRANCH_HALT, 3600 .clkr = { 3601 .enable_reg = 0x21020, 3602 .enable_mask = BIT(0), 3603 .hw.init = &(const struct clk_init_data){ 3604 .name = "gcc_tscss_etu_clk", 3605 .ops = &clk_branch2_ops, 3606 }, 3607 }, 3608 }; 3609 3610 static struct clk_branch gcc_tscss_global_cntr_clk = { 3611 .halt_reg = 0x21004, 3612 .halt_check = BRANCH_HALT_VOTED, 3613 .clkr = { 3614 .enable_reg = 0x21004, 3615 .enable_mask = BIT(0), 3616 .hw.init = &(const struct clk_init_data){ 3617 .name = "gcc_tscss_global_cntr_clk", 3618 .parent_hws = (const struct clk_hw*[]){ 3619 &gcc_tscss_cntr_clk_src.clkr.hw, 3620 }, 3621 .num_parents = 1, 3622 .flags = CLK_SET_RATE_PARENT, 3623 .ops = &clk_branch2_ops, 3624 }, 3625 }, 3626 }; 3627 3628 static struct clk_branch gcc_ufs_card_ahb_clk = { 3629 .halt_reg = 0x81020, 3630 .halt_check = BRANCH_HALT_VOTED, 3631 .hwcg_reg = 0x81020, 3632 .hwcg_bit = 1, 3633 .clkr = { 3634 .enable_reg = 0x81020, 3635 .enable_mask = BIT(0), 3636 .hw.init = &(const struct clk_init_data){ 3637 .name = "gcc_ufs_card_ahb_clk", 3638 .ops = &clk_branch2_ops, 3639 }, 3640 }, 3641 }; 3642 3643 static struct clk_branch gcc_ufs_card_axi_clk = { 3644 .halt_reg = 0x81018, 3645 .halt_check = BRANCH_HALT_VOTED, 3646 .hwcg_reg = 0x81018, 3647 .hwcg_bit = 1, 3648 .clkr = { 3649 .enable_reg = 0x81018, 3650 .enable_mask = BIT(0), 3651 .hw.init = &(const struct clk_init_data){ 3652 .name = "gcc_ufs_card_axi_clk", 3653 .parent_hws = (const struct clk_hw*[]){ 3654 &gcc_ufs_card_axi_clk_src.clkr.hw, 3655 }, 3656 .num_parents = 1, 3657 .flags = CLK_SET_RATE_PARENT, 3658 .ops = &clk_branch2_ops, 3659 }, 3660 }, 3661 }; 3662 3663 static struct clk_branch gcc_ufs_card_ice_core_clk = { 3664 .halt_reg = 0x8106c, 3665 .halt_check = BRANCH_HALT_VOTED, 3666 .hwcg_reg = 0x8106c, 3667 .hwcg_bit = 1, 3668 .clkr = { 3669 .enable_reg = 0x8106c, 3670 .enable_mask = BIT(0), 3671 .hw.init = &(const struct clk_init_data){ 3672 .name = "gcc_ufs_card_ice_core_clk", 3673 .parent_hws = (const struct clk_hw*[]){ 3674 &gcc_ufs_card_ice_core_clk_src.clkr.hw, 3675 }, 3676 .num_parents = 1, 3677 .flags = CLK_SET_RATE_PARENT, 3678 .ops = &clk_branch2_ops, 3679 }, 3680 }, 3681 }; 3682 3683 static struct clk_branch gcc_ufs_card_phy_aux_clk = { 3684 .halt_reg = 0x810a4, 3685 .halt_check = BRANCH_HALT_VOTED, 3686 .hwcg_reg = 0x810a4, 3687 .hwcg_bit = 1, 3688 .clkr = { 3689 .enable_reg = 0x810a4, 3690 .enable_mask = BIT(0), 3691 .hw.init = &(const struct clk_init_data){ 3692 .name = "gcc_ufs_card_phy_aux_clk", 3693 .parent_hws = (const struct clk_hw*[]){ 3694 &gcc_ufs_card_phy_aux_clk_src.clkr.hw, 3695 }, 3696 .num_parents = 1, 3697 .flags = CLK_SET_RATE_PARENT, 3698 .ops = &clk_branch2_ops, 3699 }, 3700 }, 3701 }; 3702 3703 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { 3704 .halt_reg = 0x81028, 3705 .halt_check = BRANCH_HALT_DELAY, 3706 .clkr = { 3707 .enable_reg = 0x81028, 3708 .enable_mask = BIT(0), 3709 .hw.init = &(const struct clk_init_data){ 3710 .name = "gcc_ufs_card_rx_symbol_0_clk", 3711 .parent_hws = (const struct clk_hw*[]){ 3712 &gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw, 3713 }, 3714 .num_parents = 1, 3715 .flags = CLK_SET_RATE_PARENT, 3716 .ops = &clk_branch2_ops, 3717 }, 3718 }, 3719 }; 3720 3721 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { 3722 .halt_reg = 0x810c0, 3723 .halt_check = BRANCH_HALT_DELAY, 3724 .clkr = { 3725 .enable_reg = 0x810c0, 3726 .enable_mask = BIT(0), 3727 .hw.init = &(const struct clk_init_data){ 3728 .name = "gcc_ufs_card_rx_symbol_1_clk", 3729 .parent_hws = (const struct clk_hw*[]){ 3730 &gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw, 3731 }, 3732 .num_parents = 1, 3733 .flags = CLK_SET_RATE_PARENT, 3734 .ops = &clk_branch2_ops, 3735 }, 3736 }, 3737 }; 3738 3739 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { 3740 .halt_reg = 0x81024, 3741 .halt_check = BRANCH_HALT_DELAY, 3742 .clkr = { 3743 .enable_reg = 0x81024, 3744 .enable_mask = BIT(0), 3745 .hw.init = &(const struct clk_init_data){ 3746 .name = "gcc_ufs_card_tx_symbol_0_clk", 3747 .parent_hws = (const struct clk_hw*[]){ 3748 &gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw, 3749 }, 3750 .num_parents = 1, 3751 .flags = CLK_SET_RATE_PARENT, 3752 .ops = &clk_branch2_ops, 3753 }, 3754 }, 3755 }; 3756 3757 static struct clk_branch gcc_ufs_card_unipro_core_clk = { 3758 .halt_reg = 0x81064, 3759 .halt_check = BRANCH_HALT_VOTED, 3760 .hwcg_reg = 0x81064, 3761 .hwcg_bit = 1, 3762 .clkr = { 3763 .enable_reg = 0x81064, 3764 .enable_mask = BIT(0), 3765 .hw.init = &(const struct clk_init_data){ 3766 .name = "gcc_ufs_card_unipro_core_clk", 3767 .parent_hws = (const struct clk_hw*[]){ 3768 &gcc_ufs_card_unipro_core_clk_src.clkr.hw, 3769 }, 3770 .num_parents = 1, 3771 .flags = CLK_SET_RATE_PARENT, 3772 .ops = &clk_branch2_ops, 3773 }, 3774 }, 3775 }; 3776 3777 static struct clk_branch gcc_ufs_phy_ahb_clk = { 3778 .halt_reg = 0x83020, 3779 .halt_check = BRANCH_HALT_VOTED, 3780 .hwcg_reg = 0x83020, 3781 .hwcg_bit = 1, 3782 .clkr = { 3783 .enable_reg = 0x83020, 3784 .enable_mask = BIT(0), 3785 .hw.init = &(const struct clk_init_data){ 3786 .name = "gcc_ufs_phy_ahb_clk", 3787 .ops = &clk_branch2_ops, 3788 }, 3789 }, 3790 }; 3791 3792 static struct clk_branch gcc_ufs_phy_axi_clk = { 3793 .halt_reg = 0x83018, 3794 .halt_check = BRANCH_HALT_VOTED, 3795 .hwcg_reg = 0x83018, 3796 .hwcg_bit = 1, 3797 .clkr = { 3798 .enable_reg = 0x83018, 3799 .enable_mask = BIT(0), 3800 .hw.init = &(const struct clk_init_data){ 3801 .name = "gcc_ufs_phy_axi_clk", 3802 .parent_hws = (const struct clk_hw*[]){ 3803 &gcc_ufs_phy_axi_clk_src.clkr.hw, 3804 }, 3805 .num_parents = 1, 3806 .flags = CLK_SET_RATE_PARENT, 3807 .ops = &clk_branch2_ops, 3808 }, 3809 }, 3810 }; 3811 3812 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { 3813 .halt_reg = 0x83018, 3814 .halt_check = BRANCH_HALT_VOTED, 3815 .hwcg_reg = 0x83018, 3816 .hwcg_bit = 1, 3817 .clkr = { 3818 .enable_reg = 0x83018, 3819 .enable_mask = BIT(1), 3820 .hw.init = &(const struct clk_init_data){ 3821 .name = "gcc_ufs_phy_axi_hw_ctl_clk", 3822 .parent_hws = (const struct clk_hw*[]){ 3823 &gcc_ufs_phy_axi_clk_src.clkr.hw, 3824 }, 3825 .num_parents = 1, 3826 .flags = CLK_SET_RATE_PARENT, 3827 .ops = &clk_branch2_ops, 3828 }, 3829 }, 3830 }; 3831 3832 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 3833 .halt_reg = 0x8306c, 3834 .halt_check = BRANCH_HALT_VOTED, 3835 .hwcg_reg = 0x8306c, 3836 .hwcg_bit = 1, 3837 .clkr = { 3838 .enable_reg = 0x8306c, 3839 .enable_mask = BIT(0), 3840 .hw.init = &(const struct clk_init_data){ 3841 .name = "gcc_ufs_phy_ice_core_clk", 3842 .parent_hws = (const struct clk_hw*[]){ 3843 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 3844 }, 3845 .num_parents = 1, 3846 .flags = CLK_SET_RATE_PARENT, 3847 .ops = &clk_branch2_ops, 3848 }, 3849 }, 3850 }; 3851 3852 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { 3853 .halt_reg = 0x8306c, 3854 .halt_check = BRANCH_HALT_VOTED, 3855 .hwcg_reg = 0x8306c, 3856 .hwcg_bit = 1, 3857 .clkr = { 3858 .enable_reg = 0x8306c, 3859 .enable_mask = BIT(1), 3860 .hw.init = &(const struct clk_init_data){ 3861 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", 3862 .parent_hws = (const struct clk_hw*[]){ 3863 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 3864 }, 3865 .num_parents = 1, 3866 .flags = CLK_SET_RATE_PARENT, 3867 .ops = &clk_branch2_ops, 3868 }, 3869 }, 3870 }; 3871 3872 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 3873 .halt_reg = 0x830a4, 3874 .halt_check = BRANCH_HALT_VOTED, 3875 .hwcg_reg = 0x830a4, 3876 .hwcg_bit = 1, 3877 .clkr = { 3878 .enable_reg = 0x830a4, 3879 .enable_mask = BIT(0), 3880 .hw.init = &(const struct clk_init_data){ 3881 .name = "gcc_ufs_phy_phy_aux_clk", 3882 .parent_hws = (const struct clk_hw*[]){ 3883 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 3884 }, 3885 .num_parents = 1, 3886 .flags = CLK_SET_RATE_PARENT, 3887 .ops = &clk_branch2_ops, 3888 }, 3889 }, 3890 }; 3891 3892 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { 3893 .halt_reg = 0x830a4, 3894 .halt_check = BRANCH_HALT_VOTED, 3895 .hwcg_reg = 0x830a4, 3896 .hwcg_bit = 1, 3897 .clkr = { 3898 .enable_reg = 0x830a4, 3899 .enable_mask = BIT(1), 3900 .hw.init = &(const struct clk_init_data){ 3901 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", 3902 .parent_hws = (const struct clk_hw*[]){ 3903 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 3904 }, 3905 .num_parents = 1, 3906 .flags = CLK_SET_RATE_PARENT, 3907 .ops = &clk_branch2_ops, 3908 }, 3909 }, 3910 }; 3911 3912 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 3913 .halt_reg = 0x83028, 3914 .halt_check = BRANCH_HALT_DELAY, 3915 .clkr = { 3916 .enable_reg = 0x83028, 3917 .enable_mask = BIT(0), 3918 .hw.init = &(const struct clk_init_data){ 3919 .name = "gcc_ufs_phy_rx_symbol_0_clk", 3920 .parent_hws = (const struct clk_hw*[]){ 3921 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 3922 }, 3923 .num_parents = 1, 3924 .flags = CLK_SET_RATE_PARENT, 3925 .ops = &clk_branch2_ops, 3926 }, 3927 }, 3928 }; 3929 3930 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 3931 .halt_reg = 0x830c0, 3932 .halt_check = BRANCH_HALT_DELAY, 3933 .clkr = { 3934 .enable_reg = 0x830c0, 3935 .enable_mask = BIT(0), 3936 .hw.init = &(const struct clk_init_data){ 3937 .name = "gcc_ufs_phy_rx_symbol_1_clk", 3938 .parent_hws = (const struct clk_hw*[]){ 3939 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 3940 }, 3941 .num_parents = 1, 3942 .flags = CLK_SET_RATE_PARENT, 3943 .ops = &clk_branch2_ops, 3944 }, 3945 }, 3946 }; 3947 3948 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 3949 .halt_reg = 0x83024, 3950 .halt_check = BRANCH_HALT_DELAY, 3951 .clkr = { 3952 .enable_reg = 0x83024, 3953 .enable_mask = BIT(0), 3954 .hw.init = &(const struct clk_init_data){ 3955 .name = "gcc_ufs_phy_tx_symbol_0_clk", 3956 .parent_hws = (const struct clk_hw*[]){ 3957 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 3958 }, 3959 .num_parents = 1, 3960 .flags = CLK_SET_RATE_PARENT, 3961 .ops = &clk_branch2_ops, 3962 }, 3963 }, 3964 }; 3965 3966 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 3967 .halt_reg = 0x83064, 3968 .halt_check = BRANCH_HALT_VOTED, 3969 .hwcg_reg = 0x83064, 3970 .hwcg_bit = 1, 3971 .clkr = { 3972 .enable_reg = 0x83064, 3973 .enable_mask = BIT(0), 3974 .hw.init = &(const struct clk_init_data){ 3975 .name = "gcc_ufs_phy_unipro_core_clk", 3976 .parent_hws = (const struct clk_hw*[]){ 3977 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 3978 }, 3979 .num_parents = 1, 3980 .flags = CLK_SET_RATE_PARENT, 3981 .ops = &clk_branch2_ops, 3982 }, 3983 }, 3984 }; 3985 3986 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { 3987 .halt_reg = 0x83064, 3988 .halt_check = BRANCH_HALT_VOTED, 3989 .hwcg_reg = 0x83064, 3990 .hwcg_bit = 1, 3991 .clkr = { 3992 .enable_reg = 0x83064, 3993 .enable_mask = BIT(1), 3994 .hw.init = &(const struct clk_init_data){ 3995 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", 3996 .parent_hws = (const struct clk_hw*[]){ 3997 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 3998 }, 3999 .num_parents = 1, 4000 .flags = CLK_SET_RATE_PARENT, 4001 .ops = &clk_branch2_ops, 4002 }, 4003 }, 4004 }; 4005 4006 static struct clk_branch gcc_usb20_master_clk = { 4007 .halt_reg = 0x1c018, 4008 .halt_check = BRANCH_HALT, 4009 .clkr = { 4010 .enable_reg = 0x1c018, 4011 .enable_mask = BIT(0), 4012 .hw.init = &(const struct clk_init_data){ 4013 .name = "gcc_usb20_master_clk", 4014 .parent_hws = (const struct clk_hw*[]){ 4015 &gcc_usb20_master_clk_src.clkr.hw, 4016 }, 4017 .num_parents = 1, 4018 .flags = CLK_SET_RATE_PARENT, 4019 .ops = &clk_branch2_ops, 4020 }, 4021 }, 4022 }; 4023 4024 static struct clk_branch gcc_usb20_mock_utmi_clk = { 4025 .halt_reg = 0x1c024, 4026 .halt_check = BRANCH_HALT, 4027 .clkr = { 4028 .enable_reg = 0x1c024, 4029 .enable_mask = BIT(0), 4030 .hw.init = &(const struct clk_init_data){ 4031 .name = "gcc_usb20_mock_utmi_clk", 4032 .parent_hws = (const struct clk_hw*[]){ 4033 &gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw, 4034 }, 4035 .num_parents = 1, 4036 .flags = CLK_SET_RATE_PARENT, 4037 .ops = &clk_branch2_ops, 4038 }, 4039 }, 4040 }; 4041 4042 static struct clk_branch gcc_usb20_sleep_clk = { 4043 .halt_reg = 0x1c020, 4044 .halt_check = BRANCH_HALT, 4045 .clkr = { 4046 .enable_reg = 0x1c020, 4047 .enable_mask = BIT(0), 4048 .hw.init = &(const struct clk_init_data){ 4049 .name = "gcc_usb20_sleep_clk", 4050 .ops = &clk_branch2_ops, 4051 }, 4052 }, 4053 }; 4054 4055 static struct clk_branch gcc_usb30_prim_master_clk = { 4056 .halt_reg = 0x1b018, 4057 .halt_check = BRANCH_HALT, 4058 .clkr = { 4059 .enable_reg = 0x1b018, 4060 .enable_mask = BIT(0), 4061 .hw.init = &(const struct clk_init_data){ 4062 .name = "gcc_usb30_prim_master_clk", 4063 .parent_hws = (const struct clk_hw*[]){ 4064 &gcc_usb30_prim_master_clk_src.clkr.hw, 4065 }, 4066 .num_parents = 1, 4067 .flags = CLK_SET_RATE_PARENT, 4068 .ops = &clk_branch2_ops, 4069 }, 4070 }, 4071 }; 4072 4073 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 4074 .halt_reg = 0x1b024, 4075 .halt_check = BRANCH_HALT, 4076 .clkr = { 4077 .enable_reg = 0x1b024, 4078 .enable_mask = BIT(0), 4079 .hw.init = &(const struct clk_init_data){ 4080 .name = "gcc_usb30_prim_mock_utmi_clk", 4081 .parent_hws = (const struct clk_hw*[]){ 4082 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 4083 }, 4084 .num_parents = 1, 4085 .flags = CLK_SET_RATE_PARENT, 4086 .ops = &clk_branch2_ops, 4087 }, 4088 }, 4089 }; 4090 4091 static struct clk_branch gcc_usb30_prim_sleep_clk = { 4092 .halt_reg = 0x1b020, 4093 .halt_check = BRANCH_HALT, 4094 .clkr = { 4095 .enable_reg = 0x1b020, 4096 .enable_mask = BIT(0), 4097 .hw.init = &(const struct clk_init_data){ 4098 .name = "gcc_usb30_prim_sleep_clk", 4099 .ops = &clk_branch2_ops, 4100 }, 4101 }, 4102 }; 4103 4104 static struct clk_branch gcc_usb30_sec_master_clk = { 4105 .halt_reg = 0x2f018, 4106 .halt_check = BRANCH_HALT, 4107 .clkr = { 4108 .enable_reg = 0x2f018, 4109 .enable_mask = BIT(0), 4110 .hw.init = &(const struct clk_init_data){ 4111 .name = "gcc_usb30_sec_master_clk", 4112 .parent_hws = (const struct clk_hw*[]){ 4113 &gcc_usb30_sec_master_clk_src.clkr.hw, 4114 }, 4115 .num_parents = 1, 4116 .flags = CLK_SET_RATE_PARENT, 4117 .ops = &clk_branch2_ops, 4118 }, 4119 }, 4120 }; 4121 4122 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { 4123 .halt_reg = 0x2f024, 4124 .halt_check = BRANCH_HALT, 4125 .clkr = { 4126 .enable_reg = 0x2f024, 4127 .enable_mask = BIT(0), 4128 .hw.init = &(const struct clk_init_data){ 4129 .name = "gcc_usb30_sec_mock_utmi_clk", 4130 .parent_hws = (const struct clk_hw*[]){ 4131 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw, 4132 }, 4133 .num_parents = 1, 4134 .flags = CLK_SET_RATE_PARENT, 4135 .ops = &clk_branch2_ops, 4136 }, 4137 }, 4138 }; 4139 4140 static struct clk_branch gcc_usb30_sec_sleep_clk = { 4141 .halt_reg = 0x2f020, 4142 .halt_check = BRANCH_HALT, 4143 .clkr = { 4144 .enable_reg = 0x2f020, 4145 .enable_mask = BIT(0), 4146 .hw.init = &(const struct clk_init_data){ 4147 .name = "gcc_usb30_sec_sleep_clk", 4148 .ops = &clk_branch2_ops, 4149 }, 4150 }, 4151 }; 4152 4153 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 4154 .halt_reg = 0x1b05c, 4155 .halt_check = BRANCH_HALT, 4156 .clkr = { 4157 .enable_reg = 0x1b05c, 4158 .enable_mask = BIT(0), 4159 .hw.init = &(const struct clk_init_data){ 4160 .name = "gcc_usb3_prim_phy_aux_clk", 4161 .parent_hws = (const struct clk_hw*[]){ 4162 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 4163 }, 4164 .num_parents = 1, 4165 .flags = CLK_SET_RATE_PARENT, 4166 .ops = &clk_branch2_ops, 4167 }, 4168 }, 4169 }; 4170 4171 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 4172 .halt_reg = 0x1b060, 4173 .halt_check = BRANCH_HALT, 4174 .clkr = { 4175 .enable_reg = 0x1b060, 4176 .enable_mask = BIT(0), 4177 .hw.init = &(const struct clk_init_data){ 4178 .name = "gcc_usb3_prim_phy_com_aux_clk", 4179 .parent_hws = (const struct clk_hw*[]){ 4180 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 4181 }, 4182 .num_parents = 1, 4183 .flags = CLK_SET_RATE_PARENT, 4184 .ops = &clk_branch2_ops, 4185 }, 4186 }, 4187 }; 4188 4189 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 4190 .halt_reg = 0x1b064, 4191 .halt_check = BRANCH_HALT_DELAY, 4192 .hwcg_reg = 0x1b064, 4193 .hwcg_bit = 1, 4194 .clkr = { 4195 .enable_reg = 0x1b064, 4196 .enable_mask = BIT(0), 4197 .hw.init = &(const struct clk_init_data){ 4198 .name = "gcc_usb3_prim_phy_pipe_clk", 4199 .parent_hws = (const struct clk_hw*[]){ 4200 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 4201 }, 4202 .num_parents = 1, 4203 .flags = CLK_SET_RATE_PARENT, 4204 .ops = &clk_branch2_ops, 4205 }, 4206 }, 4207 }; 4208 4209 static struct clk_branch gcc_usb3_sec_phy_aux_clk = { 4210 .halt_reg = 0x2f05c, 4211 .halt_check = BRANCH_HALT, 4212 .clkr = { 4213 .enable_reg = 0x2f05c, 4214 .enable_mask = BIT(0), 4215 .hw.init = &(const struct clk_init_data){ 4216 .name = "gcc_usb3_sec_phy_aux_clk", 4217 .parent_hws = (const struct clk_hw*[]){ 4218 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 4219 }, 4220 .num_parents = 1, 4221 .flags = CLK_SET_RATE_PARENT, 4222 .ops = &clk_branch2_ops, 4223 }, 4224 }, 4225 }; 4226 4227 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { 4228 .halt_reg = 0x2f060, 4229 .halt_check = BRANCH_HALT, 4230 .clkr = { 4231 .enable_reg = 0x2f060, 4232 .enable_mask = BIT(0), 4233 .hw.init = &(const struct clk_init_data){ 4234 .name = "gcc_usb3_sec_phy_com_aux_clk", 4235 .parent_hws = (const struct clk_hw*[]){ 4236 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 4237 }, 4238 .num_parents = 1, 4239 .flags = CLK_SET_RATE_PARENT, 4240 .ops = &clk_branch2_ops, 4241 }, 4242 }, 4243 }; 4244 4245 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { 4246 .halt_reg = 0x2f064, 4247 .halt_check = BRANCH_HALT_DELAY, 4248 .clkr = { 4249 .enable_reg = 0x2f064, 4250 .enable_mask = BIT(0), 4251 .hw.init = &(const struct clk_init_data){ 4252 .name = "gcc_usb3_sec_phy_pipe_clk", 4253 .parent_hws = (const struct clk_hw*[]){ 4254 &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw, 4255 }, 4256 .num_parents = 1, 4257 .flags = CLK_SET_RATE_PARENT, 4258 .ops = &clk_branch2_ops, 4259 }, 4260 }, 4261 }; 4262 4263 static struct clk_branch gcc_usb_clkref_en = { 4264 .halt_reg = 0x97468, 4265 .halt_check = BRANCH_HALT_DELAY, 4266 .clkr = { 4267 .enable_reg = 0x97468, 4268 .enable_mask = BIT(0), 4269 .hw.init = &(const struct clk_init_data){ 4270 .name = "gcc_usb_clkref_en", 4271 .ops = &clk_branch2_ops, 4272 }, 4273 }, 4274 }; 4275 4276 static struct clk_branch gcc_video_axi0_clk = { 4277 .halt_reg = 0x34014, 4278 .halt_check = BRANCH_HALT_VOTED, 4279 .hwcg_reg = 0x34014, 4280 .hwcg_bit = 1, 4281 .clkr = { 4282 .enable_reg = 0x34014, 4283 .enable_mask = BIT(0), 4284 .hw.init = &(const struct clk_init_data){ 4285 .name = "gcc_video_axi0_clk", 4286 .ops = &clk_branch2_ops, 4287 }, 4288 }, 4289 }; 4290 4291 static struct clk_branch gcc_video_axi1_clk = { 4292 .halt_reg = 0x3401c, 4293 .halt_check = BRANCH_HALT_VOTED, 4294 .hwcg_reg = 0x3401c, 4295 .hwcg_bit = 1, 4296 .clkr = { 4297 .enable_reg = 0x3401c, 4298 .enable_mask = BIT(0), 4299 .hw.init = &(const struct clk_init_data){ 4300 .name = "gcc_video_axi1_clk", 4301 .ops = &clk_branch2_ops, 4302 }, 4303 }, 4304 }; 4305 4306 static struct gdsc pcie_0_gdsc = { 4307 .gdscr = 0xa9004, 4308 .collapse_ctrl = 0x4b104, 4309 .collapse_mask = BIT(0), 4310 .en_rest_wait_val = 0x2, 4311 .en_few_wait_val = 0x2, 4312 .clk_dis_wait_val = 0xf, 4313 .pd = { 4314 .name = "pcie_0_gdsc", 4315 }, 4316 .pwrsts = PWRSTS_OFF_ON, 4317 .flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4318 }; 4319 4320 static struct gdsc pcie_1_gdsc = { 4321 .gdscr = 0x77004, 4322 .collapse_ctrl = 0x4b104, 4323 .collapse_mask = BIT(1), 4324 .en_rest_wait_val = 0x2, 4325 .en_few_wait_val = 0x2, 4326 .clk_dis_wait_val = 0xf, 4327 .pd = { 4328 .name = "pcie_1_gdsc", 4329 }, 4330 .pwrsts = PWRSTS_OFF_ON, 4331 .flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4332 }; 4333 4334 static struct gdsc ufs_card_gdsc = { 4335 .gdscr = 0x81004, 4336 .en_rest_wait_val = 0x2, 4337 .en_few_wait_val = 0x2, 4338 .clk_dis_wait_val = 0xf, 4339 .pd = { 4340 .name = "ufs_card_gdsc", 4341 }, 4342 .pwrsts = PWRSTS_OFF_ON, 4343 .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4344 }; 4345 4346 static struct gdsc ufs_phy_gdsc = { 4347 .gdscr = 0x83004, 4348 .en_rest_wait_val = 0x2, 4349 .en_few_wait_val = 0x2, 4350 .clk_dis_wait_val = 0xf, 4351 .pd = { 4352 .name = "ufs_phy_gdsc", 4353 }, 4354 .pwrsts = PWRSTS_OFF_ON, 4355 .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4356 }; 4357 4358 static struct gdsc usb20_prim_gdsc = { 4359 .gdscr = 0x1c004, 4360 .en_rest_wait_val = 0x2, 4361 .en_few_wait_val = 0x2, 4362 .clk_dis_wait_val = 0xf, 4363 .pd = { 4364 .name = "usb20_prim_gdsc", 4365 }, 4366 .pwrsts = PWRSTS_OFF_ON, 4367 .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4368 }; 4369 4370 static struct gdsc usb30_prim_gdsc = { 4371 .gdscr = 0x1b004, 4372 .en_rest_wait_val = 0x2, 4373 .en_few_wait_val = 0x2, 4374 .clk_dis_wait_val = 0xf, 4375 .pd = { 4376 .name = "usb30_prim_gdsc", 4377 }, 4378 .pwrsts = PWRSTS_OFF_ON, 4379 .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4380 }; 4381 4382 static struct gdsc usb30_sec_gdsc = { 4383 .gdscr = 0x2f004, 4384 .en_rest_wait_val = 0x2, 4385 .en_few_wait_val = 0x2, 4386 .clk_dis_wait_val = 0xf, 4387 .pd = { 4388 .name = "usb30_sec_gdsc", 4389 }, 4390 .pwrsts = PWRSTS_OFF_ON, 4391 .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4392 }; 4393 4394 static struct gdsc emac0_gdsc = { 4395 .gdscr = 0xb6004, 4396 .en_rest_wait_val = 0x2, 4397 .en_few_wait_val = 0x2, 4398 .clk_dis_wait_val = 0xf, 4399 .pd = { 4400 .name = "emac0_gdsc", 4401 }, 4402 .pwrsts = PWRSTS_OFF_ON, 4403 .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4404 }; 4405 4406 static struct gdsc emac1_gdsc = { 4407 .gdscr = 0xb4004, 4408 .en_rest_wait_val = 0x2, 4409 .en_few_wait_val = 0x2, 4410 .clk_dis_wait_val = 0xf, 4411 .pd = { 4412 .name = "emac1_gdsc", 4413 }, 4414 .pwrsts = PWRSTS_OFF_ON, 4415 .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4416 }; 4417 4418 static struct clk_regmap *gcc_sa8775p_clocks[] = { 4419 [GCC_AGGRE_NOC_QUPV3_AXI_CLK] = &gcc_aggre_noc_qupv3_axi_clk.clkr, 4420 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, 4421 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 4422 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, 4423 [GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr, 4424 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 4425 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, 4426 [GCC_AHB2PHY0_CLK] = &gcc_ahb2phy0_clk.clkr, 4427 [GCC_AHB2PHY2_CLK] = &gcc_ahb2phy2_clk.clkr, 4428 [GCC_AHB2PHY3_CLK] = &gcc_ahb2phy3_clk.clkr, 4429 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 4430 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 4431 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 4432 [GCC_CAMERA_THROTTLE_XO_CLK] = &gcc_camera_throttle_xo_clk.clkr, 4433 [GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &gcc_cfg_noc_usb2_prim_axi_clk.clkr, 4434 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 4435 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, 4436 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 4437 [GCC_DISP1_HF_AXI_CLK] = &gcc_disp1_hf_axi_clk.clkr, 4438 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 4439 [GCC_EDP_REF_CLKREF_EN] = &gcc_edp_ref_clkref_en.clkr, 4440 [GCC_EMAC0_AXI_CLK] = &gcc_emac0_axi_clk.clkr, 4441 [GCC_EMAC0_PHY_AUX_CLK] = &gcc_emac0_phy_aux_clk.clkr, 4442 [GCC_EMAC0_PHY_AUX_CLK_SRC] = &gcc_emac0_phy_aux_clk_src.clkr, 4443 [GCC_EMAC0_PTP_CLK] = &gcc_emac0_ptp_clk.clkr, 4444 [GCC_EMAC0_PTP_CLK_SRC] = &gcc_emac0_ptp_clk_src.clkr, 4445 [GCC_EMAC0_RGMII_CLK] = &gcc_emac0_rgmii_clk.clkr, 4446 [GCC_EMAC0_RGMII_CLK_SRC] = &gcc_emac0_rgmii_clk_src.clkr, 4447 [GCC_EMAC0_SLV_AHB_CLK] = &gcc_emac0_slv_ahb_clk.clkr, 4448 [GCC_EMAC1_AXI_CLK] = &gcc_emac1_axi_clk.clkr, 4449 [GCC_EMAC1_PHY_AUX_CLK] = &gcc_emac1_phy_aux_clk.clkr, 4450 [GCC_EMAC1_PHY_AUX_CLK_SRC] = &gcc_emac1_phy_aux_clk_src.clkr, 4451 [GCC_EMAC1_PTP_CLK] = &gcc_emac1_ptp_clk.clkr, 4452 [GCC_EMAC1_PTP_CLK_SRC] = &gcc_emac1_ptp_clk_src.clkr, 4453 [GCC_EMAC1_RGMII_CLK] = &gcc_emac1_rgmii_clk.clkr, 4454 [GCC_EMAC1_RGMII_CLK_SRC] = &gcc_emac1_rgmii_clk_src.clkr, 4455 [GCC_EMAC1_SLV_AHB_CLK] = &gcc_emac1_slv_ahb_clk.clkr, 4456 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 4457 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 4458 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 4459 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 4460 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 4461 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 4462 [GCC_GP4_CLK] = &gcc_gp4_clk.clkr, 4463 [GCC_GP4_CLK_SRC] = &gcc_gp4_clk_src.clkr, 4464 [GCC_GP5_CLK] = &gcc_gp5_clk.clkr, 4465 [GCC_GP5_CLK_SRC] = &gcc_gp5_clk_src.clkr, 4466 [GCC_GPLL0] = &gcc_gpll0.clkr, 4467 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 4468 [GCC_GPLL1] = &gcc_gpll1.clkr, 4469 [GCC_GPLL4] = &gcc_gpll4.clkr, 4470 [GCC_GPLL5] = &gcc_gpll5.clkr, 4471 [GCC_GPLL7] = &gcc_gpll7.clkr, 4472 [GCC_GPLL9] = &gcc_gpll9.clkr, 4473 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 4474 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 4475 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 4476 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 4477 [GCC_GPU_TCU_THROTTLE_AHB_CLK] = &gcc_gpu_tcu_throttle_ahb_clk.clkr, 4478 [GCC_GPU_TCU_THROTTLE_CLK] = &gcc_gpu_tcu_throttle_clk.clkr, 4479 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 4480 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 4481 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 4482 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 4483 [GCC_PCIE_0_PHY_AUX_CLK] = &gcc_pcie_0_phy_aux_clk.clkr, 4484 [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, 4485 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 4486 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 4487 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 4488 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 4489 [GCC_PCIE_0_PIPE_DIV_CLK_SRC] = &gcc_pcie_0_pipe_div_clk_src.clkr, 4490 [GCC_PCIE_0_PIPEDIV2_CLK] = &gcc_pcie_0_pipediv2_clk.clkr, 4491 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 4492 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 4493 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 4494 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 4495 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 4496 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 4497 [GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr, 4498 [GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr, 4499 [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr, 4500 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 4501 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 4502 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr, 4503 [GCC_PCIE_1_PIPE_DIV_CLK_SRC] = &gcc_pcie_1_pipe_div_clk_src.clkr, 4504 [GCC_PCIE_1_PIPEDIV2_CLK] = &gcc_pcie_1_pipediv2_clk.clkr, 4505 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 4506 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 4507 [GCC_PCIE_CLKREF_EN] = &gcc_pcie_clkref_en.clkr, 4508 [GCC_PCIE_THROTTLE_CFG_CLK] = &gcc_pcie_throttle_cfg_clk.clkr, 4509 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 4510 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 4511 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 4512 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 4513 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 4514 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 4515 [GCC_QMIP_DISP1_AHB_CLK] = &gcc_qmip_disp1_ahb_clk.clkr, 4516 [GCC_QMIP_DISP1_ROT_AHB_CLK] = &gcc_qmip_disp1_rot_ahb_clk.clkr, 4517 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 4518 [GCC_QMIP_DISP_ROT_AHB_CLK] = &gcc_qmip_disp_rot_ahb_clk.clkr, 4519 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 4520 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 4521 [GCC_QMIP_VIDEO_VCPU_AHB_CLK] = &gcc_qmip_video_vcpu_ahb_clk.clkr, 4522 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 4523 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 4524 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 4525 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 4526 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 4527 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 4528 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 4529 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 4530 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 4531 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 4532 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 4533 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 4534 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 4535 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 4536 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 4537 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 4538 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 4539 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 4540 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 4541 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 4542 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 4543 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 4544 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 4545 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 4546 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 4547 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 4548 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 4549 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 4550 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 4551 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 4552 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 4553 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 4554 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 4555 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 4556 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 4557 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 4558 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 4559 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 4560 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 4561 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 4562 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 4563 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 4564 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 4565 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 4566 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 4567 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 4568 [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr, 4569 [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr, 4570 [GCC_QUPV3_WRAP3_CORE_2X_CLK] = &gcc_qupv3_wrap3_core_2x_clk.clkr, 4571 [GCC_QUPV3_WRAP3_CORE_CLK] = &gcc_qupv3_wrap3_core_clk.clkr, 4572 [GCC_QUPV3_WRAP3_QSPI_CLK] = &gcc_qupv3_wrap3_qspi_clk.clkr, 4573 [GCC_QUPV3_WRAP3_S0_CLK] = &gcc_qupv3_wrap3_s0_clk.clkr, 4574 [GCC_QUPV3_WRAP3_S0_CLK_SRC] = &gcc_qupv3_wrap3_s0_clk_src.clkr, 4575 [GCC_QUPV3_WRAP3_S0_DIV_CLK_SRC] = &gcc_qupv3_wrap3_s0_div_clk_src.clkr, 4576 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 4577 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 4578 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 4579 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 4580 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 4581 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 4582 [GCC_QUPV3_WRAP_3_M_AHB_CLK] = &gcc_qupv3_wrap_3_m_ahb_clk.clkr, 4583 [GCC_QUPV3_WRAP_3_S_AHB_CLK] = &gcc_qupv3_wrap_3_s_ahb_clk.clkr, 4584 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 4585 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 4586 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 4587 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 4588 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 4589 [GCC_SGMI_CLKREF_EN] = &gcc_sgmi_clkref_en.clkr, 4590 [GCC_TSCSS_AHB_CLK] = &gcc_tscss_ahb_clk.clkr, 4591 [GCC_TSCSS_CNTR_CLK_SRC] = &gcc_tscss_cntr_clk_src.clkr, 4592 [GCC_TSCSS_ETU_CLK] = &gcc_tscss_etu_clk.clkr, 4593 [GCC_TSCSS_GLOBAL_CNTR_CLK] = &gcc_tscss_global_cntr_clk.clkr, 4594 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, 4595 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, 4596 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, 4597 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, 4598 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, 4599 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, 4600 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, 4601 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, 4602 [GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_rx_symbol_0_clk_src.clkr, 4603 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, 4604 [GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_card_rx_symbol_1_clk_src.clkr, 4605 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, 4606 [GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_tx_symbol_0_clk_src.clkr, 4607 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, 4608 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr, 4609 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 4610 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 4611 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 4612 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, 4613 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 4614 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 4615 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, 4616 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 4617 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 4618 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, 4619 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 4620 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 4621 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 4622 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 4623 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 4624 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 4625 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 4626 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 4627 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, 4628 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr, 4629 [GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr, 4630 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr, 4631 [GCC_USB20_MOCK_UTMI_CLK_SRC] = &gcc_usb20_mock_utmi_clk_src.clkr, 4632 [GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb20_mock_utmi_postdiv_clk_src.clkr, 4633 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr, 4634 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 4635 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 4636 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 4637 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 4638 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 4639 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 4640 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, 4641 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, 4642 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, 4643 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr, 4644 [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr, 4645 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, 4646 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 4647 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 4648 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 4649 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 4650 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 4651 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, 4652 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, 4653 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, 4654 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, 4655 [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr, 4656 [GCC_USB_CLKREF_EN] = &gcc_usb_clkref_en.clkr, 4657 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 4658 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 4659 }; 4660 4661 static const struct qcom_reset_map gcc_sa8775p_resets[] = { 4662 [GCC_CAMERA_BCR] = { 0x32000 }, 4663 [GCC_DISPLAY1_BCR] = { 0xc7000 }, 4664 [GCC_DISPLAY_BCR] = { 0x33000 }, 4665 [GCC_EMAC0_BCR] = { 0xb6000 }, 4666 [GCC_EMAC1_BCR] = { 0xb4000 }, 4667 [GCC_GPU_BCR] = { 0x7d000 }, 4668 [GCC_MMSS_BCR] = { 0x17000 }, 4669 [GCC_PCIE_0_BCR] = { 0xa9000 }, 4670 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0xbf000 }, 4671 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xbf008 }, 4672 [GCC_PCIE_0_PHY_BCR] = { 0xad144 }, 4673 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xbf00c }, 4674 [GCC_PCIE_1_BCR] = { 0x77000 }, 4675 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0xae084 }, 4676 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0xae090 }, 4677 [GCC_PCIE_1_PHY_BCR] = { 0xae08c }, 4678 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0xae094 }, 4679 [GCC_PDM_BCR] = { 0x3f000 }, 4680 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x23000 }, 4681 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x24000 }, 4682 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x2a000 }, 4683 [GCC_QUPV3_WRAPPER_3_BCR] = { 0xc4000 }, 4684 [GCC_SDCC1_BCR] = { 0x20000 }, 4685 [GCC_TSCSS_BCR] = { 0x21000 }, 4686 [GCC_UFS_CARD_BCR] = { 0x81000 }, 4687 [GCC_UFS_PHY_BCR] = { 0x83000 }, 4688 [GCC_USB20_PRIM_BCR] = { 0x1c000 }, 4689 [GCC_USB2_PHY_PRIM_BCR] = { 0x5c028 }, 4690 [GCC_USB2_PHY_SEC_BCR] = { 0x5c02c }, 4691 [GCC_USB30_PRIM_BCR] = { 0x1b000 }, 4692 [GCC_USB30_SEC_BCR] = { 0x2f000 }, 4693 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x5c008 }, 4694 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x5c014 }, 4695 [GCC_USB3_PHY_PRIM_BCR] = { 0x5c000 }, 4696 [GCC_USB3_PHY_SEC_BCR] = { 0x5c00c }, 4697 [GCC_USB3_PHY_TERT_BCR] = { 0x5c030 }, 4698 [GCC_USB3_UNIPHY_MP0_BCR] = { 0x5c018 }, 4699 [GCC_USB3_UNIPHY_MP1_BCR] = { 0x5c01c }, 4700 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x5c004 }, 4701 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x5c010 }, 4702 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5c020 }, 4703 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x5c024 }, 4704 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x76000 }, 4705 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x34014, 2 }, 4706 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x3401c, 2 }, 4707 [GCC_VIDEO_BCR] = { 0x34000 }, 4708 }; 4709 4710 static struct gdsc *gcc_sa8775p_gdscs[] = { 4711 [PCIE_0_GDSC] = &pcie_0_gdsc, 4712 [PCIE_1_GDSC] = &pcie_1_gdsc, 4713 [UFS_CARD_GDSC] = &ufs_card_gdsc, 4714 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 4715 [USB20_PRIM_GDSC] = &usb20_prim_gdsc, 4716 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 4717 [USB30_SEC_GDSC] = &usb30_sec_gdsc, 4718 [EMAC0_GDSC] = &emac0_gdsc, 4719 [EMAC1_GDSC] = &emac1_gdsc, 4720 }; 4721 4722 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 4723 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 4724 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 4725 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 4726 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 4727 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 4728 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 4729 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 4730 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 4731 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 4732 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 4733 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 4734 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 4735 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 4736 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 4737 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 4738 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 4739 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 4740 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 4741 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 4742 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 4743 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src), 4744 DEFINE_RCG_DFS(gcc_qupv3_wrap3_s0_clk_src), 4745 }; 4746 4747 static const struct regmap_config gcc_sa8775p_regmap_config = { 4748 .reg_bits = 32, 4749 .reg_stride = 4, 4750 .val_bits = 32, 4751 .max_register = 0xc7018, 4752 .fast_io = true, 4753 }; 4754 4755 static const struct qcom_cc_desc gcc_sa8775p_desc = { 4756 .config = &gcc_sa8775p_regmap_config, 4757 .clks = gcc_sa8775p_clocks, 4758 .num_clks = ARRAY_SIZE(gcc_sa8775p_clocks), 4759 .resets = gcc_sa8775p_resets, 4760 .num_resets = ARRAY_SIZE(gcc_sa8775p_resets), 4761 .gdscs = gcc_sa8775p_gdscs, 4762 .num_gdscs = ARRAY_SIZE(gcc_sa8775p_gdscs), 4763 }; 4764 4765 static const struct of_device_id gcc_sa8775p_match_table[] = { 4766 { .compatible = "qcom,sa8775p-gcc" }, 4767 { } 4768 }; 4769 MODULE_DEVICE_TABLE(of, gcc_sa8775p_match_table); 4770 4771 static int gcc_sa8775p_probe(struct platform_device *pdev) 4772 { 4773 struct regmap *regmap; 4774 int ret; 4775 4776 regmap = qcom_cc_map(pdev, &gcc_sa8775p_desc); 4777 if (IS_ERR(regmap)) 4778 return PTR_ERR(regmap); 4779 4780 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 4781 ARRAY_SIZE(gcc_dfs_clocks)); 4782 if (ret) 4783 return ret; 4784 4785 /* 4786 * Keep the clocks always-ON 4787 * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP1_AHB_CLK, 4788 * GCC_DISP1_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK, 4789 * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK. 4790 */ 4791 regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); 4792 regmap_update_bits(regmap, 0x32020, BIT(0), BIT(0)); 4793 regmap_update_bits(regmap, 0xc7004, BIT(0), BIT(0)); 4794 regmap_update_bits(regmap, 0xc7018, BIT(0), BIT(0)); 4795 regmap_update_bits(regmap, 0x33004, BIT(0), BIT(0)); 4796 regmap_update_bits(regmap, 0x33018, BIT(0), BIT(0)); 4797 regmap_update_bits(regmap, 0x7d004, BIT(0), BIT(0)); 4798 regmap_update_bits(regmap, 0x34004, BIT(0), BIT(0)); 4799 regmap_update_bits(regmap, 0x34024, BIT(0), BIT(0)); 4800 4801 return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap); 4802 } 4803 4804 static struct platform_driver gcc_sa8775p_driver = { 4805 .probe = gcc_sa8775p_probe, 4806 .driver = { 4807 .name = "sa8775p-gcc", 4808 .of_match_table = gcc_sa8775p_match_table, 4809 }, 4810 }; 4811 4812 static int __init gcc_sa8775p_init(void) 4813 { 4814 return platform_driver_register(&gcc_sa8775p_driver); 4815 } 4816 core_initcall(gcc_sa8775p_init); 4817 4818 static void __exit gcc_sa8775p_exit(void) 4819 { 4820 platform_driver_unregister(&gcc_sa8775p_driver); 4821 } 4822 module_exit(gcc_sa8775p_exit); 4823 4824 MODULE_DESCRIPTION("Qualcomm SA8775P GCC driver"); 4825 MODULE_LICENSE("GPL"); 4826