1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/of.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,qdu1000-gcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "clk-regmap-divider.h" 19 #include "clk-regmap-mux.h" 20 #include "clk-regmap-phy-mux.h" 21 #include "reset.h" 22 23 enum { 24 P_BI_TCXO, 25 P_GCC_GPLL0_OUT_EVEN, 26 P_GCC_GPLL0_OUT_MAIN, 27 P_GCC_GPLL1_OUT_MAIN, 28 P_GCC_GPLL2_OUT_MAIN, 29 P_GCC_GPLL3_OUT_MAIN, 30 P_GCC_GPLL4_OUT_MAIN, 31 P_GCC_GPLL5_OUT_MAIN, 32 P_GCC_GPLL6_OUT_MAIN, 33 P_GCC_GPLL7_OUT_MAIN, 34 P_GCC_GPLL8_OUT_MAIN, 35 P_PCIE_0_PHY_AUX_CLK, 36 P_PCIE_0_PIPE_CLK, 37 P_SLEEP_CLK, 38 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 39 }; 40 41 enum { 42 DT_TCXO_IDX, 43 DT_SLEEP_CLK_IDX, 44 DT_PCIE_0_PIPE_CLK_IDX, 45 DT_PCIE_0_PHY_AUX_CLK_IDX, 46 DT_USB3_PHY_WRAPPER_PIPE_CLK_IDX, 47 }; 48 49 static struct clk_alpha_pll gcc_gpll0 = { 50 .offset = 0x0, 51 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 52 .clkr = { 53 .enable_reg = 0x62018, 54 .enable_mask = BIT(0), 55 .hw.init = &(const struct clk_init_data) { 56 .name = "gcc_gpll0", 57 .parent_data = &(const struct clk_parent_data) { 58 .index = DT_TCXO_IDX, 59 }, 60 .num_parents = 1, 61 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 62 }, 63 }, 64 }; 65 66 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 67 { 0x1, 2 } 68 }; 69 70 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 71 .offset = 0x0, 72 .post_div_shift = 10, 73 .post_div_table = post_div_table_gcc_gpll0_out_even, 74 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 75 .width = 4, 76 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 77 .clkr.hw.init = &(const struct clk_init_data) { 78 .name = "gcc_gpll0_out_even", 79 .parent_hws = (const struct clk_hw*[]) { 80 &gcc_gpll0.clkr.hw, 81 }, 82 .num_parents = 1, 83 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 84 }, 85 }; 86 87 static struct clk_alpha_pll gcc_gpll1 = { 88 .offset = 0x1000, 89 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 90 .clkr = { 91 .enable_reg = 0x62018, 92 .enable_mask = BIT(1), 93 .hw.init = &(const struct clk_init_data) { 94 .name = "gcc_gpll1", 95 .parent_data = &(const struct clk_parent_data) { 96 .index = DT_TCXO_IDX, 97 }, 98 .num_parents = 1, 99 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 100 }, 101 }, 102 }; 103 104 static struct clk_alpha_pll_postdiv gcc_gpll1_out_even = { 105 .offset = 0x1000, 106 .post_div_shift = 10, 107 .post_div_table = post_div_table_gcc_gpll0_out_even, 108 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 109 .width = 4, 110 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 111 .clkr.hw.init = &(const struct clk_init_data) { 112 .name = "gcc_gpll1_out_even", 113 .parent_hws = (const struct clk_hw*[]) { 114 &gcc_gpll1.clkr.hw, 115 }, 116 .num_parents = 1, 117 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 118 }, 119 }; 120 121 static struct clk_alpha_pll gcc_gpll2 = { 122 .offset = 0x2000, 123 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 124 .clkr = { 125 .enable_reg = 0x62018, 126 .enable_mask = BIT(2), 127 .hw.init = &(const struct clk_init_data) { 128 .name = "gcc_gpll2", 129 .parent_data = &(const struct clk_parent_data) { 130 .index = DT_TCXO_IDX, 131 }, 132 .num_parents = 1, 133 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 134 }, 135 }, 136 }; 137 138 static struct clk_alpha_pll_postdiv gcc_gpll2_out_even = { 139 .offset = 0x2000, 140 .post_div_shift = 10, 141 .post_div_table = post_div_table_gcc_gpll0_out_even, 142 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 143 .width = 4, 144 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 145 .clkr.hw.init = &(const struct clk_init_data) { 146 .name = "gcc_gpll2_out_even", 147 .parent_hws = (const struct clk_hw*[]) { 148 &gcc_gpll2.clkr.hw, 149 }, 150 .num_parents = 1, 151 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 152 }, 153 }; 154 155 static struct clk_alpha_pll gcc_gpll3 = { 156 .offset = 0x3000, 157 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 158 .clkr = { 159 .enable_reg = 0x62018, 160 .enable_mask = BIT(3), 161 .hw.init = &(const struct clk_init_data) { 162 .name = "gcc_gpll3", 163 .parent_data = &(const struct clk_parent_data) { 164 .index = DT_TCXO_IDX, 165 }, 166 .num_parents = 1, 167 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 168 }, 169 }, 170 }; 171 172 static struct clk_alpha_pll gcc_gpll4 = { 173 .offset = 0x4000, 174 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 175 .clkr = { 176 .enable_reg = 0x62018, 177 .enable_mask = BIT(4), 178 .hw.init = &(const struct clk_init_data) { 179 .name = "gcc_gpll4", 180 .parent_data = &(const struct clk_parent_data) { 181 .index = DT_TCXO_IDX, 182 }, 183 .num_parents = 1, 184 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 185 }, 186 }, 187 }; 188 189 static struct clk_alpha_pll gcc_gpll5 = { 190 .offset = 0x5000, 191 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 192 .clkr = { 193 .enable_reg = 0x62018, 194 .enable_mask = BIT(5), 195 .hw.init = &(const struct clk_init_data) { 196 .name = "gcc_gpll5", 197 .parent_data = &(const struct clk_parent_data) { 198 .index = DT_TCXO_IDX, 199 }, 200 .num_parents = 1, 201 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 202 }, 203 }, 204 }; 205 206 static struct clk_alpha_pll_postdiv gcc_gpll5_out_even = { 207 .offset = 0x5000, 208 .post_div_shift = 10, 209 .post_div_table = post_div_table_gcc_gpll0_out_even, 210 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 211 .width = 4, 212 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 213 .clkr.hw.init = &(const struct clk_init_data) { 214 .name = "gcc_gpll5_out_even", 215 .parent_hws = (const struct clk_hw*[]) { 216 &gcc_gpll5.clkr.hw, 217 }, 218 .num_parents = 1, 219 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 220 }, 221 }; 222 223 static struct clk_alpha_pll gcc_gpll6 = { 224 .offset = 0x6000, 225 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 226 .clkr = { 227 .enable_reg = 0x62018, 228 .enable_mask = BIT(6), 229 .hw.init = &(const struct clk_init_data) { 230 .name = "gcc_gpll6", 231 .parent_data = &(const struct clk_parent_data) { 232 .index = DT_TCXO_IDX, 233 }, 234 .num_parents = 1, 235 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 236 }, 237 }, 238 }; 239 240 static struct clk_alpha_pll gcc_gpll7 = { 241 .offset = 0x7000, 242 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 243 .clkr = { 244 .enable_reg = 0x62018, 245 .enable_mask = BIT(7), 246 .hw.init = &(const struct clk_init_data) { 247 .name = "gcc_gpll7", 248 .parent_data = &(const struct clk_parent_data) { 249 .index = DT_TCXO_IDX, 250 }, 251 .num_parents = 1, 252 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 253 }, 254 }, 255 }; 256 257 static struct clk_alpha_pll gcc_gpll8 = { 258 .offset = 0x8000, 259 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 260 .clkr = { 261 .enable_reg = 0x62018, 262 .enable_mask = BIT(8), 263 .hw.init = &(const struct clk_init_data) { 264 .name = "gcc_gpll8", 265 .parent_data = &(const struct clk_parent_data) { 266 .index = DT_TCXO_IDX, 267 }, 268 .num_parents = 1, 269 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 270 }, 271 }, 272 }; 273 274 static const struct parent_map gcc_parent_map_0[] = { 275 { P_BI_TCXO, 0 }, 276 { P_GCC_GPLL0_OUT_MAIN, 1 }, 277 { P_GCC_GPLL0_OUT_EVEN, 6 }, 278 }; 279 280 static const struct clk_parent_data gcc_parent_data_0[] = { 281 { .index = DT_TCXO_IDX }, 282 { .hw = &gcc_gpll0.clkr.hw }, 283 { .hw = &gcc_gpll0_out_even.clkr.hw }, 284 }; 285 286 static const struct parent_map gcc_parent_map_1[] = { 287 { P_BI_TCXO, 0 }, 288 { P_GCC_GPLL0_OUT_MAIN, 1 }, 289 { P_SLEEP_CLK, 5 }, 290 { P_GCC_GPLL0_OUT_EVEN, 6 }, 291 }; 292 293 static const struct clk_parent_data gcc_parent_data_1[] = { 294 { .index = DT_TCXO_IDX }, 295 { .hw = &gcc_gpll0.clkr.hw }, 296 { .index = DT_SLEEP_CLK_IDX }, 297 { .hw = &gcc_gpll0_out_even.clkr.hw }, 298 }; 299 300 static const struct parent_map gcc_parent_map_2[] = { 301 { P_BI_TCXO, 0 }, 302 { P_GCC_GPLL0_OUT_MAIN, 1 }, 303 { P_GCC_GPLL5_OUT_MAIN, 3 }, 304 { P_GCC_GPLL4_OUT_MAIN, 5 }, 305 }; 306 307 static const struct clk_parent_data gcc_parent_data_2[] = { 308 { .index = DT_TCXO_IDX }, 309 { .hw = &gcc_gpll0.clkr.hw }, 310 { .hw = &gcc_gpll5.clkr.hw }, 311 { .hw = &gcc_gpll4.clkr.hw }, 312 }; 313 314 static const struct parent_map gcc_parent_map_3[] = { 315 { P_BI_TCXO, 0 }, 316 { P_SLEEP_CLK, 5 }, 317 }; 318 319 static const struct clk_parent_data gcc_parent_data_3[] = { 320 { .index = DT_TCXO_IDX }, 321 { .index = DT_SLEEP_CLK_IDX }, 322 }; 323 324 static const struct parent_map gcc_parent_map_4[] = { 325 { P_BI_TCXO, 0 }, 326 { P_GCC_GPLL0_OUT_MAIN, 1 }, 327 { P_GCC_GPLL2_OUT_MAIN, 2 }, 328 { P_GCC_GPLL5_OUT_MAIN, 3 }, 329 { P_GCC_GPLL1_OUT_MAIN, 4 }, 330 { P_GCC_GPLL4_OUT_MAIN, 5 }, 331 { P_GCC_GPLL3_OUT_MAIN, 6 }, 332 }; 333 334 static const struct clk_parent_data gcc_parent_data_4[] = { 335 { .index = DT_TCXO_IDX }, 336 { .hw = &gcc_gpll0.clkr.hw }, 337 { .hw = &gcc_gpll2.clkr.hw }, 338 { .hw = &gcc_gpll5.clkr.hw }, 339 { .hw = &gcc_gpll1.clkr.hw }, 340 { .hw = &gcc_gpll4.clkr.hw }, 341 { .hw = &gcc_gpll3.clkr.hw }, 342 }; 343 344 static const struct parent_map gcc_parent_map_5[] = { 345 { P_BI_TCXO, 0 }, 346 { P_GCC_GPLL0_OUT_MAIN, 1 }, 347 { P_GCC_GPLL2_OUT_MAIN, 2 }, 348 { P_GCC_GPLL6_OUT_MAIN, 3 }, 349 { P_GCC_GPLL1_OUT_MAIN, 4 }, 350 { P_GCC_GPLL4_OUT_MAIN, 5 }, 351 { P_GCC_GPLL3_OUT_MAIN, 6 }, 352 }; 353 354 static const struct clk_parent_data gcc_parent_data_5[] = { 355 { .index = DT_TCXO_IDX }, 356 { .hw = &gcc_gpll0.clkr.hw }, 357 { .hw = &gcc_gpll2.clkr.hw }, 358 { .hw = &gcc_gpll6.clkr.hw }, 359 { .hw = &gcc_gpll1.clkr.hw }, 360 { .hw = &gcc_gpll4.clkr.hw }, 361 { .hw = &gcc_gpll3.clkr.hw }, 362 }; 363 364 static const struct parent_map gcc_parent_map_6[] = { 365 { P_PCIE_0_PHY_AUX_CLK, 0 }, 366 { P_BI_TCXO, 2 }, 367 }; 368 369 static const struct clk_parent_data gcc_parent_data_6[] = { 370 { .index = DT_PCIE_0_PHY_AUX_CLK_IDX }, 371 { .index = DT_TCXO_IDX }, 372 }; 373 374 static const struct parent_map gcc_parent_map_7[] = { 375 { P_PCIE_0_PIPE_CLK, 0 }, 376 { P_BI_TCXO, 2 }, 377 }; 378 379 static const struct clk_parent_data gcc_parent_data_7[] = { 380 { .index = DT_PCIE_0_PIPE_CLK_IDX }, 381 { .index = DT_TCXO_IDX }, 382 }; 383 384 static const struct parent_map gcc_parent_map_8[] = { 385 { P_BI_TCXO, 0 }, 386 { P_GCC_GPLL0_OUT_MAIN, 1 }, 387 { P_GCC_GPLL8_OUT_MAIN, 2 }, 388 { P_GCC_GPLL5_OUT_MAIN, 3 }, 389 { P_GCC_GPLL4_OUT_MAIN, 5 }, 390 }; 391 392 static const struct clk_parent_data gcc_parent_data_8[] = { 393 { .index = DT_TCXO_IDX }, 394 { .hw = &gcc_gpll0.clkr.hw }, 395 { .hw = &gcc_gpll8.clkr.hw }, 396 { .hw = &gcc_gpll5.clkr.hw }, 397 { .hw = &gcc_gpll4.clkr.hw }, 398 }; 399 400 static const struct parent_map gcc_parent_map_9[] = { 401 { P_BI_TCXO, 0 }, 402 { P_GCC_GPLL0_OUT_MAIN, 1 }, 403 { P_GCC_GPLL2_OUT_MAIN, 2 }, 404 { P_GCC_GPLL5_OUT_MAIN, 3 }, 405 { P_GCC_GPLL7_OUT_MAIN, 4 }, 406 { P_GCC_GPLL4_OUT_MAIN, 5 }, 407 }; 408 409 static const struct clk_parent_data gcc_parent_data_9[] = { 410 { .index = DT_TCXO_IDX }, 411 { .hw = &gcc_gpll0.clkr.hw }, 412 { .hw = &gcc_gpll2.clkr.hw }, 413 { .hw = &gcc_gpll5.clkr.hw }, 414 { .hw = &gcc_gpll7.clkr.hw }, 415 { .hw = &gcc_gpll4.clkr.hw }, 416 }; 417 418 static const struct parent_map gcc_parent_map_10[] = { 419 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 420 { P_BI_TCXO, 2 }, 421 }; 422 423 static const struct clk_parent_data gcc_parent_data_10[] = { 424 { .index = DT_USB3_PHY_WRAPPER_PIPE_CLK_IDX }, 425 { .index = DT_TCXO_IDX }, 426 }; 427 428 static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = { 429 .reg = 0x9d080, 430 .shift = 0, 431 .width = 2, 432 .parent_map = gcc_parent_map_6, 433 .clkr = { 434 .hw.init = &(const struct clk_init_data) { 435 .name = "gcc_pcie_0_phy_aux_clk_src", 436 .parent_data = gcc_parent_data_6, 437 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 438 .ops = &clk_regmap_mux_closest_ops, 439 }, 440 }, 441 }; 442 443 static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { 444 .reg = 0x9d064, 445 .shift = 0, 446 .width = 2, 447 .parent_map = gcc_parent_map_7, 448 .clkr = { 449 .hw.init = &(const struct clk_init_data) { 450 .name = "gcc_pcie_0_pipe_clk_src", 451 .parent_data = gcc_parent_data_7, 452 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 453 .ops = &clk_regmap_phy_mux_ops, 454 }, 455 }, 456 }; 457 458 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 459 .reg = 0x4906c, 460 .shift = 0, 461 .width = 2, 462 .parent_map = gcc_parent_map_10, 463 .clkr = { 464 .hw.init = &(const struct clk_init_data) { 465 .name = "gcc_usb3_prim_phy_pipe_clk_src", 466 .parent_data = gcc_parent_data_10, 467 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 468 .ops = &clk_regmap_mux_closest_ops, 469 }, 470 }, 471 }; 472 473 static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_dma_clk_src[] = { 474 F(466500000, P_GCC_GPLL5_OUT_MAIN, 2, 0, 0), 475 F(500000000, P_GCC_GPLL2_OUT_MAIN, 2, 0, 0), 476 { } 477 }; 478 479 static struct clk_rcg2 gcc_aggre_noc_ecpri_dma_clk_src = { 480 .cmd_rcgr = 0x92020, 481 .mnd_width = 0, 482 .hid_width = 5, 483 .parent_map = gcc_parent_map_4, 484 .freq_tbl = ftbl_gcc_aggre_noc_ecpri_dma_clk_src, 485 .clkr.hw.init = &(const struct clk_init_data) { 486 .name = "gcc_aggre_noc_ecpri_dma_clk_src", 487 .parent_data = gcc_parent_data_4, 488 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 489 .ops = &clk_rcg2_ops, 490 }, 491 }; 492 493 static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_gsi_clk_src[] = { 494 F(250000000, P_GCC_GPLL2_OUT_MAIN, 4, 0, 0), 495 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 496 { } 497 }; 498 499 static struct clk_rcg2 gcc_aggre_noc_ecpri_gsi_clk_src = { 500 .cmd_rcgr = 0x92038, 501 .mnd_width = 0, 502 .hid_width = 5, 503 .parent_map = gcc_parent_map_5, 504 .freq_tbl = ftbl_gcc_aggre_noc_ecpri_gsi_clk_src, 505 .clkr.hw.init = &(const struct clk_init_data) { 506 .name = "gcc_aggre_noc_ecpri_gsi_clk_src", 507 .parent_data = gcc_parent_data_5, 508 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 509 .ops = &clk_rcg2_ops, 510 }, 511 }; 512 513 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 514 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 515 { } 516 }; 517 518 static struct clk_rcg2 gcc_gp1_clk_src = { 519 .cmd_rcgr = 0x74004, 520 .mnd_width = 16, 521 .hid_width = 5, 522 .parent_map = gcc_parent_map_1, 523 .freq_tbl = ftbl_gcc_gp1_clk_src, 524 .clkr.hw.init = &(const struct clk_init_data) { 525 .name = "gcc_gp1_clk_src", 526 .parent_data = gcc_parent_data_1, 527 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 528 .ops = &clk_rcg2_ops, 529 }, 530 }; 531 532 static struct clk_rcg2 gcc_gp2_clk_src = { 533 .cmd_rcgr = 0x75004, 534 .mnd_width = 16, 535 .hid_width = 5, 536 .parent_map = gcc_parent_map_1, 537 .freq_tbl = ftbl_gcc_gp1_clk_src, 538 .clkr.hw.init = &(const struct clk_init_data) { 539 .name = "gcc_gp2_clk_src", 540 .parent_data = gcc_parent_data_1, 541 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 542 .ops = &clk_rcg2_ops, 543 }, 544 }; 545 546 static struct clk_rcg2 gcc_gp3_clk_src = { 547 .cmd_rcgr = 0x76004, 548 .mnd_width = 16, 549 .hid_width = 5, 550 .parent_map = gcc_parent_map_1, 551 .freq_tbl = ftbl_gcc_gp1_clk_src, 552 .clkr.hw.init = &(const struct clk_init_data) { 553 .name = "gcc_gp3_clk_src", 554 .parent_data = gcc_parent_data_1, 555 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 556 .ops = &clk_rcg2_ops, 557 }, 558 }; 559 560 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 561 F(19200000, P_BI_TCXO, 1, 0, 0), 562 { } 563 }; 564 565 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 566 .cmd_rcgr = 0x9d068, 567 .mnd_width = 16, 568 .hid_width = 5, 569 .parent_map = gcc_parent_map_3, 570 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 571 .clkr.hw.init = &(const struct clk_init_data) { 572 .name = "gcc_pcie_0_aux_clk_src", 573 .parent_data = gcc_parent_data_3, 574 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 575 .ops = &clk_rcg2_ops, 576 }, 577 }; 578 579 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 580 F(19200000, P_BI_TCXO, 1, 0, 0), 581 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 582 { } 583 }; 584 585 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 586 .cmd_rcgr = 0x9d04c, 587 .mnd_width = 0, 588 .hid_width = 5, 589 .parent_map = gcc_parent_map_0, 590 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 591 .clkr.hw.init = &(const struct clk_init_data) { 592 .name = "gcc_pcie_0_phy_rchng_clk_src", 593 .parent_data = gcc_parent_data_0, 594 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 595 .ops = &clk_rcg2_ops, 596 }, 597 }; 598 599 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 600 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 601 { } 602 }; 603 604 static struct clk_rcg2 gcc_pdm2_clk_src = { 605 .cmd_rcgr = 0x43010, 606 .mnd_width = 0, 607 .hid_width = 5, 608 .parent_map = gcc_parent_map_0, 609 .freq_tbl = ftbl_gcc_pdm2_clk_src, 610 .clkr.hw.init = &(const struct clk_init_data) { 611 .name = "gcc_pdm2_clk_src", 612 .parent_data = gcc_parent_data_0, 613 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 614 .ops = &clk_rcg2_ops, 615 }, 616 }; 617 618 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 619 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 620 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 621 F(19200000, P_BI_TCXO, 1, 0, 0), 622 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 623 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 624 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 625 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 626 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 627 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 628 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 629 { } 630 }; 631 632 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 633 .name = "gcc_qupv3_wrap0_s0_clk_src", 634 .parent_data = gcc_parent_data_0, 635 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 636 .ops = &clk_rcg2_ops, 637 }; 638 639 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 640 .cmd_rcgr = 0x27154, 641 .mnd_width = 16, 642 .hid_width = 5, 643 .parent_map = gcc_parent_map_0, 644 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 645 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 646 }; 647 648 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 649 .name = "gcc_qupv3_wrap0_s1_clk_src", 650 .parent_data = gcc_parent_data_0, 651 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 652 .ops = &clk_rcg2_ops, 653 }; 654 655 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 656 .cmd_rcgr = 0x27288, 657 .mnd_width = 16, 658 .hid_width = 5, 659 .parent_map = gcc_parent_map_0, 660 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 661 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 662 }; 663 664 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 665 .name = "gcc_qupv3_wrap0_s2_clk_src", 666 .parent_data = gcc_parent_data_0, 667 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 668 .ops = &clk_rcg2_ops, 669 }; 670 671 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 672 .cmd_rcgr = 0x273bc, 673 .mnd_width = 16, 674 .hid_width = 5, 675 .parent_map = gcc_parent_map_0, 676 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 677 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 678 }; 679 680 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 681 .name = "gcc_qupv3_wrap0_s3_clk_src", 682 .parent_data = gcc_parent_data_0, 683 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 684 .ops = &clk_rcg2_ops, 685 }; 686 687 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 688 .cmd_rcgr = 0x274f0, 689 .mnd_width = 16, 690 .hid_width = 5, 691 .parent_map = gcc_parent_map_0, 692 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 693 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 694 }; 695 696 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 697 .name = "gcc_qupv3_wrap0_s4_clk_src", 698 .parent_data = gcc_parent_data_0, 699 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 700 .ops = &clk_rcg2_ops, 701 }; 702 703 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 704 .cmd_rcgr = 0x27624, 705 .mnd_width = 16, 706 .hid_width = 5, 707 .parent_map = gcc_parent_map_0, 708 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 709 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 710 }; 711 712 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] = { 713 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 714 { } 715 }; 716 717 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 718 .name = "gcc_qupv3_wrap0_s5_clk_src", 719 .parent_data = gcc_parent_data_0, 720 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 721 .ops = &clk_rcg2_ops, 722 }; 723 724 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 725 .cmd_rcgr = 0x27758, 726 .mnd_width = 16, 727 .hid_width = 5, 728 .parent_map = gcc_parent_map_0, 729 .freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src, 730 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 731 }; 732 733 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 734 .name = "gcc_qupv3_wrap0_s6_clk_src", 735 .parent_data = gcc_parent_data_0, 736 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 737 .ops = &clk_rcg2_ops, 738 }; 739 740 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 741 .cmd_rcgr = 0x2788c, 742 .mnd_width = 16, 743 .hid_width = 5, 744 .parent_map = gcc_parent_map_0, 745 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 746 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 747 }; 748 749 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 750 .name = "gcc_qupv3_wrap0_s7_clk_src", 751 .parent_data = gcc_parent_data_0, 752 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 753 .ops = &clk_rcg2_ops, 754 }; 755 756 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 757 .cmd_rcgr = 0x279c0, 758 .mnd_width = 16, 759 .hid_width = 5, 760 .parent_map = gcc_parent_map_0, 761 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 762 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 763 }; 764 765 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 766 .name = "gcc_qupv3_wrap1_s0_clk_src", 767 .parent_data = gcc_parent_data_0, 768 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 769 .ops = &clk_rcg2_ops, 770 }; 771 772 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 773 .cmd_rcgr = 0x28154, 774 .mnd_width = 16, 775 .hid_width = 5, 776 .parent_map = gcc_parent_map_0, 777 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 778 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 779 }; 780 781 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 782 .name = "gcc_qupv3_wrap1_s1_clk_src", 783 .parent_data = gcc_parent_data_0, 784 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 785 .ops = &clk_rcg2_ops, 786 }; 787 788 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 789 .cmd_rcgr = 0x28288, 790 .mnd_width = 16, 791 .hid_width = 5, 792 .parent_map = gcc_parent_map_0, 793 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 794 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 795 }; 796 797 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 798 .name = "gcc_qupv3_wrap1_s2_clk_src", 799 .parent_data = gcc_parent_data_0, 800 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 801 .ops = &clk_rcg2_ops, 802 }; 803 804 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 805 .cmd_rcgr = 0x283bc, 806 .mnd_width = 16, 807 .hid_width = 5, 808 .parent_map = gcc_parent_map_0, 809 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 810 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 811 }; 812 813 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 814 .name = "gcc_qupv3_wrap1_s3_clk_src", 815 .parent_data = gcc_parent_data_0, 816 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 817 .ops = &clk_rcg2_ops, 818 }; 819 820 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 821 .cmd_rcgr = 0x284f0, 822 .mnd_width = 16, 823 .hid_width = 5, 824 .parent_map = gcc_parent_map_0, 825 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 826 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 827 }; 828 829 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 830 .name = "gcc_qupv3_wrap1_s4_clk_src", 831 .parent_data = gcc_parent_data_0, 832 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 833 .ops = &clk_rcg2_ops, 834 }; 835 836 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 837 .cmd_rcgr = 0x28624, 838 .mnd_width = 16, 839 .hid_width = 5, 840 .parent_map = gcc_parent_map_0, 841 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 842 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 843 }; 844 845 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 846 .name = "gcc_qupv3_wrap1_s5_clk_src", 847 .parent_data = gcc_parent_data_0, 848 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 849 .ops = &clk_rcg2_ops, 850 }; 851 852 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 853 .cmd_rcgr = 0x28758, 854 .mnd_width = 16, 855 .hid_width = 5, 856 .parent_map = gcc_parent_map_0, 857 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 858 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 859 }; 860 861 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 862 .name = "gcc_qupv3_wrap1_s6_clk_src", 863 .parent_data = gcc_parent_data_0, 864 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 865 .ops = &clk_rcg2_ops, 866 }; 867 868 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 869 .cmd_rcgr = 0x2888c, 870 .mnd_width = 16, 871 .hid_width = 5, 872 .parent_map = gcc_parent_map_0, 873 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 874 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 875 }; 876 877 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 878 .name = "gcc_qupv3_wrap1_s7_clk_src", 879 .parent_data = gcc_parent_data_0, 880 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 881 .ops = &clk_rcg2_ops, 882 }; 883 884 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 885 .cmd_rcgr = 0x289c0, 886 .mnd_width = 16, 887 .hid_width = 5, 888 .parent_map = gcc_parent_map_0, 889 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 890 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 891 }; 892 893 static const struct freq_tbl ftbl_gcc_sdcc5_apps_clk_src[] = { 894 F(144000, P_BI_TCXO, 16, 3, 25), 895 F(400000, P_BI_TCXO, 12, 1, 4), 896 F(19200000, P_BI_TCXO, 1, 0, 0), 897 F(20000000, P_GCC_GPLL0_OUT_MAIN, 10, 1, 3), 898 F(25000000, P_GCC_GPLL0_OUT_MAIN, 12, 1, 2), 899 F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0), 900 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 901 F(192000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0), 902 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 903 F(384000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0), 904 { } 905 }; 906 907 static struct clk_rcg2 gcc_sdcc5_apps_clk_src = { 908 .cmd_rcgr = 0x3b034, 909 .mnd_width = 8, 910 .hid_width = 5, 911 .parent_map = gcc_parent_map_8, 912 .freq_tbl = ftbl_gcc_sdcc5_apps_clk_src, 913 .clkr.hw.init = &(const struct clk_init_data) { 914 .name = "gcc_sdcc5_apps_clk_src", 915 .parent_data = gcc_parent_data_8, 916 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 917 .ops = &clk_rcg2_ops, 918 }, 919 }; 920 921 static const struct freq_tbl ftbl_gcc_sdcc5_ice_core_clk_src[] = { 922 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 923 { } 924 }; 925 926 static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src = { 927 .cmd_rcgr = 0x3b01c, 928 .mnd_width = 0, 929 .hid_width = 5, 930 .parent_map = gcc_parent_map_2, 931 .freq_tbl = ftbl_gcc_sdcc5_ice_core_clk_src, 932 .clkr.hw.init = &(const struct clk_init_data) { 933 .name = "gcc_sdcc5_ice_core_clk_src", 934 .parent_data = gcc_parent_data_2, 935 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 936 .ops = &clk_rcg2_ops, 937 }, 938 }; 939 940 static struct clk_rcg2 gcc_sm_bus_xo_clk_src = { 941 .cmd_rcgr = 0x5b00c, 942 .mnd_width = 0, 943 .hid_width = 5, 944 .parent_map = gcc_parent_map_2, 945 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 946 .clkr.hw.init = &(const struct clk_init_data) { 947 .name = "gcc_sm_bus_xo_clk_src", 948 .parent_data = gcc_parent_data_2, 949 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 950 .ops = &clk_rcg2_ops, 951 }, 952 }; 953 954 static const struct freq_tbl ftbl_gcc_tsc_clk_src[] = { 955 F(500000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0), 956 { } 957 }; 958 959 static struct clk_rcg2 gcc_tsc_clk_src = { 960 .cmd_rcgr = 0x57010, 961 .mnd_width = 0, 962 .hid_width = 5, 963 .parent_map = gcc_parent_map_9, 964 .freq_tbl = ftbl_gcc_tsc_clk_src, 965 .clkr.hw.init = &(const struct clk_init_data) { 966 .name = "gcc_tsc_clk_src", 967 .parent_data = gcc_parent_data_9, 968 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 969 .ops = &clk_rcg2_ops, 970 }, 971 }; 972 973 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 974 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 975 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 976 { } 977 }; 978 979 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 980 .cmd_rcgr = 0x49028, 981 .mnd_width = 8, 982 .hid_width = 5, 983 .parent_map = gcc_parent_map_0, 984 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 985 .clkr.hw.init = &(const struct clk_init_data) { 986 .name = "gcc_usb30_prim_master_clk_src", 987 .parent_data = gcc_parent_data_0, 988 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 989 .ops = &clk_rcg2_ops, 990 }, 991 }; 992 993 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 994 .cmd_rcgr = 0x49044, 995 .mnd_width = 0, 996 .hid_width = 5, 997 .parent_map = gcc_parent_map_0, 998 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 999 .clkr.hw.init = &(const struct clk_init_data) { 1000 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1001 .parent_data = gcc_parent_data_0, 1002 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1003 .ops = &clk_rcg2_ops, 1004 }, 1005 }; 1006 1007 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1008 .cmd_rcgr = 0x49070, 1009 .mnd_width = 0, 1010 .hid_width = 5, 1011 .parent_map = gcc_parent_map_3, 1012 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1013 .clkr.hw.init = &(const struct clk_init_data) { 1014 .name = "gcc_usb3_prim_phy_aux_clk_src", 1015 .parent_data = gcc_parent_data_3, 1016 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1017 .ops = &clk_rcg2_ops, 1018 }, 1019 }; 1020 1021 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1022 .reg = 0x4905c, 1023 .shift = 0, 1024 .width = 4, 1025 .clkr.hw.init = &(const struct clk_init_data) { 1026 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1027 .parent_hws = (const struct clk_hw*[]) { 1028 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1029 }, 1030 .num_parents = 1, 1031 .flags = CLK_SET_RATE_PARENT, 1032 .ops = &clk_regmap_div_ro_ops, 1033 }, 1034 }; 1035 1036 static struct clk_branch gcc_aggre_noc_ecpri_dma_clk = { 1037 .halt_reg = 0x92008, 1038 .halt_check = BRANCH_HALT_VOTED, 1039 .hwcg_reg = 0x92008, 1040 .hwcg_bit = 1, 1041 .clkr = { 1042 .enable_reg = 0x92008, 1043 .enable_mask = BIT(0), 1044 .hw.init = &(const struct clk_init_data) { 1045 .name = "gcc_aggre_noc_ecpri_dma_clk", 1046 .parent_hws = (const struct clk_hw*[]) { 1047 &gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw, 1048 }, 1049 .num_parents = 1, 1050 .flags = CLK_SET_RATE_PARENT, 1051 .ops = &clk_branch2_ops, 1052 }, 1053 }, 1054 }; 1055 1056 static struct clk_branch gcc_aggre_noc_ecpri_gsi_clk = { 1057 .halt_reg = 0x9201c, 1058 .halt_check = BRANCH_HALT_VOTED, 1059 .hwcg_reg = 0x9201c, 1060 .hwcg_bit = 1, 1061 .clkr = { 1062 .enable_reg = 0x9201c, 1063 .enable_mask = BIT(0), 1064 .hw.init = &(const struct clk_init_data) { 1065 .name = "gcc_aggre_noc_ecpri_gsi_clk", 1066 .parent_hws = (const struct clk_hw*[]) { 1067 &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, 1068 }, 1069 .num_parents = 1, 1070 .flags = CLK_SET_RATE_PARENT, 1071 .ops = &clk_branch2_ops, 1072 }, 1073 }, 1074 }; 1075 1076 static struct clk_branch gcc_boot_rom_ahb_clk = { 1077 .halt_reg = 0x48004, 1078 .halt_check = BRANCH_HALT_VOTED, 1079 .hwcg_reg = 0x48004, 1080 .hwcg_bit = 1, 1081 .clkr = { 1082 .enable_reg = 0x62000, 1083 .enable_mask = BIT(10), 1084 .hw.init = &(const struct clk_init_data) { 1085 .name = "gcc_boot_rom_ahb_clk", 1086 .ops = &clk_branch2_ops, 1087 }, 1088 }, 1089 }; 1090 1091 static struct clk_branch gcc_cfg_noc_ecpri_cc_ahb_clk = { 1092 .halt_reg = 0x3e004, 1093 .halt_check = BRANCH_HALT_VOTED, 1094 .hwcg_reg = 0x3e004, 1095 .hwcg_bit = 1, 1096 .clkr = { 1097 .enable_reg = 0x3e004, 1098 .enable_mask = BIT(0), 1099 .hw.init = &(const struct clk_init_data) { 1100 .name = "gcc_cfg_noc_ecpri_cc_ahb_clk", 1101 .ops = &clk_branch2_ops, 1102 }, 1103 }, 1104 }; 1105 1106 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1107 .halt_reg = 0x8401c, 1108 .halt_check = BRANCH_HALT_VOTED, 1109 .hwcg_reg = 0x8401c, 1110 .hwcg_bit = 1, 1111 .clkr = { 1112 .enable_reg = 0x8401c, 1113 .enable_mask = BIT(0), 1114 .hw.init = &(const struct clk_init_data) { 1115 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1116 .parent_hws = (const struct clk_hw*[]) { 1117 &gcc_usb30_prim_master_clk_src.clkr.hw, 1118 }, 1119 .num_parents = 1, 1120 .flags = CLK_SET_RATE_PARENT, 1121 .ops = &clk_branch2_ops, 1122 }, 1123 }, 1124 }; 1125 1126 static struct clk_branch gcc_ddrss_ecpri_dma_clk = { 1127 .halt_reg = 0x54030, 1128 .halt_check = BRANCH_HALT_VOTED, 1129 .hwcg_reg = 0x54030, 1130 .hwcg_bit = 1, 1131 .clkr = { 1132 .enable_reg = 0x54030, 1133 .enable_mask = BIT(0), 1134 .hw.init = &(const struct clk_init_data) { 1135 .name = "gcc_ddrss_ecpri_dma_clk", 1136 .parent_hws = (const struct clk_hw*[]) { 1137 &gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw, 1138 }, 1139 .num_parents = 1, 1140 .flags = CLK_SET_RATE_PARENT, 1141 .ops = &clk_branch2_aon_ops, 1142 }, 1143 }, 1144 }; 1145 1146 static struct clk_branch gcc_ecpri_ahb_clk = { 1147 .halt_reg = 0x3a008, 1148 .halt_check = BRANCH_HALT_VOTED, 1149 .hwcg_reg = 0x3a008, 1150 .hwcg_bit = 1, 1151 .clkr = { 1152 .enable_reg = 0x3a008, 1153 .enable_mask = BIT(0), 1154 .hw.init = &(const struct clk_init_data) { 1155 .name = "gcc_ecpri_ahb_clk", 1156 .ops = &clk_branch2_ops, 1157 }, 1158 }, 1159 }; 1160 1161 static struct clk_branch gcc_ecpri_cc_gpll0_clk_src = { 1162 .halt_check = BRANCH_HALT_DELAY, 1163 .clkr = { 1164 .enable_reg = 0x62010, 1165 .enable_mask = BIT(0), 1166 .hw.init = &(const struct clk_init_data) { 1167 .name = "gcc_ecpri_cc_gpll0_clk_src", 1168 .parent_hws = (const struct clk_hw*[]) { 1169 &gcc_gpll0.clkr.hw, 1170 }, 1171 .num_parents = 1, 1172 .flags = CLK_SET_RATE_PARENT, 1173 .ops = &clk_branch2_ops, 1174 }, 1175 }, 1176 }; 1177 1178 static struct clk_branch gcc_ecpri_cc_gpll1_even_clk_src = { 1179 .halt_check = BRANCH_HALT_DELAY, 1180 .clkr = { 1181 .enable_reg = 0x62010, 1182 .enable_mask = BIT(1), 1183 .hw.init = &(const struct clk_init_data) { 1184 .name = "gcc_ecpri_cc_gpll1_even_clk_src", 1185 .parent_hws = (const struct clk_hw*[]) { 1186 &gcc_gpll1_out_even.clkr.hw, 1187 }, 1188 .num_parents = 1, 1189 .flags = CLK_SET_RATE_PARENT, 1190 .ops = &clk_branch2_ops, 1191 }, 1192 }, 1193 }; 1194 1195 static struct clk_branch gcc_ecpri_cc_gpll2_even_clk_src = { 1196 .halt_check = BRANCH_HALT_DELAY, 1197 .clkr = { 1198 .enable_reg = 0x62010, 1199 .enable_mask = BIT(2), 1200 .hw.init = &(const struct clk_init_data) { 1201 .name = "gcc_ecpri_cc_gpll2_even_clk_src", 1202 .parent_hws = (const struct clk_hw*[]) { 1203 &gcc_gpll2_out_even.clkr.hw, 1204 }, 1205 .num_parents = 1, 1206 .flags = CLK_SET_RATE_PARENT, 1207 .ops = &clk_branch2_ops, 1208 }, 1209 }, 1210 }; 1211 1212 static struct clk_branch gcc_ecpri_cc_gpll3_clk_src = { 1213 .halt_check = BRANCH_HALT_DELAY, 1214 .clkr = { 1215 .enable_reg = 0x62010, 1216 .enable_mask = BIT(3), 1217 .hw.init = &(const struct clk_init_data) { 1218 .name = "gcc_ecpri_cc_gpll3_clk_src", 1219 .parent_hws = (const struct clk_hw*[]) { 1220 &gcc_gpll3.clkr.hw, 1221 }, 1222 .num_parents = 1, 1223 .flags = CLK_SET_RATE_PARENT, 1224 .ops = &clk_branch2_ops, 1225 }, 1226 }, 1227 }; 1228 1229 static struct clk_branch gcc_ecpri_cc_gpll4_clk_src = { 1230 .halt_check = BRANCH_HALT_DELAY, 1231 .clkr = { 1232 .enable_reg = 0x62010, 1233 .enable_mask = BIT(4), 1234 .hw.init = &(const struct clk_init_data) { 1235 .name = "gcc_ecpri_cc_gpll4_clk_src", 1236 .parent_hws = (const struct clk_hw*[]) { 1237 &gcc_gpll4.clkr.hw, 1238 }, 1239 .num_parents = 1, 1240 .flags = CLK_SET_RATE_PARENT, 1241 .ops = &clk_branch2_ops, 1242 }, 1243 }, 1244 }; 1245 1246 static struct clk_branch gcc_ecpri_cc_gpll5_even_clk_src = { 1247 .halt_check = BRANCH_HALT_DELAY, 1248 .clkr = { 1249 .enable_reg = 0x62010, 1250 .enable_mask = BIT(5), 1251 .hw.init = &(const struct clk_init_data) { 1252 .name = "gcc_ecpri_cc_gpll5_even_clk_src", 1253 .parent_hws = (const struct clk_hw*[]) { 1254 &gcc_gpll5_out_even.clkr.hw, 1255 }, 1256 .num_parents = 1, 1257 .flags = CLK_SET_RATE_PARENT, 1258 .ops = &clk_branch2_ops, 1259 }, 1260 }, 1261 }; 1262 1263 static struct clk_branch gcc_ecpri_xo_clk = { 1264 .halt_reg = 0x3a004, 1265 .halt_check = BRANCH_HALT, 1266 .clkr = { 1267 .enable_reg = 0x3a004, 1268 .enable_mask = BIT(0), 1269 .hw.init = &(const struct clk_init_data) { 1270 .name = "gcc_ecpri_xo_clk", 1271 .ops = &clk_branch2_ops, 1272 }, 1273 }, 1274 }; 1275 1276 static struct clk_branch gcc_eth_100g_c2c_hm_apb_clk = { 1277 .halt_reg = 0x39010, 1278 .halt_check = BRANCH_HALT, 1279 .clkr = { 1280 .enable_reg = 0x39010, 1281 .enable_mask = BIT(0), 1282 .hw.init = &(const struct clk_init_data) { 1283 .name = "gcc_eth_100g_c2c_hm_apb_clk", 1284 .ops = &clk_branch2_ops, 1285 }, 1286 }, 1287 }; 1288 1289 static struct clk_branch gcc_eth_100g_fh_hm_apb_0_clk = { 1290 .halt_reg = 0x39004, 1291 .halt_check = BRANCH_HALT, 1292 .clkr = { 1293 .enable_reg = 0x39004, 1294 .enable_mask = BIT(0), 1295 .hw.init = &(const struct clk_init_data) { 1296 .name = "gcc_eth_100g_fh_hm_apb_0_clk", 1297 .ops = &clk_branch2_ops, 1298 }, 1299 }, 1300 }; 1301 1302 static struct clk_branch gcc_eth_100g_fh_hm_apb_1_clk = { 1303 .halt_reg = 0x39008, 1304 .halt_check = BRANCH_HALT, 1305 .clkr = { 1306 .enable_reg = 0x39008, 1307 .enable_mask = BIT(0), 1308 .hw.init = &(const struct clk_init_data) { 1309 .name = "gcc_eth_100g_fh_hm_apb_1_clk", 1310 .ops = &clk_branch2_ops, 1311 }, 1312 }, 1313 }; 1314 1315 static struct clk_branch gcc_eth_100g_fh_hm_apb_2_clk = { 1316 .halt_reg = 0x3900c, 1317 .halt_check = BRANCH_HALT, 1318 .clkr = { 1319 .enable_reg = 0x3900c, 1320 .enable_mask = BIT(0), 1321 .hw.init = &(const struct clk_init_data) { 1322 .name = "gcc_eth_100g_fh_hm_apb_2_clk", 1323 .ops = &clk_branch2_ops, 1324 }, 1325 }, 1326 }; 1327 1328 static struct clk_branch gcc_eth_dbg_c2c_hm_apb_clk = { 1329 .halt_reg = 0x39014, 1330 .halt_check = BRANCH_HALT, 1331 .clkr = { 1332 .enable_reg = 0x39014, 1333 .enable_mask = BIT(0), 1334 .hw.init = &(const struct clk_init_data) { 1335 .name = "gcc_eth_dbg_c2c_hm_apb_clk", 1336 .ops = &clk_branch2_ops, 1337 }, 1338 }, 1339 }; 1340 1341 static struct clk_branch gcc_eth_dbg_snoc_axi_clk = { 1342 .halt_reg = 0x3901c, 1343 .halt_check = BRANCH_HALT_VOTED, 1344 .hwcg_reg = 0x3901c, 1345 .hwcg_bit = 1, 1346 .clkr = { 1347 .enable_reg = 0x3901c, 1348 .enable_mask = BIT(0), 1349 .hw.init = &(const struct clk_init_data) { 1350 .name = "gcc_eth_dbg_snoc_axi_clk", 1351 .ops = &clk_branch2_ops, 1352 }, 1353 }, 1354 }; 1355 1356 static struct clk_branch gcc_gemnoc_pcie_qx_clk = { 1357 .halt_reg = 0x5402c, 1358 .halt_check = BRANCH_HALT_VOTED, 1359 .hwcg_reg = 0x5402c, 1360 .hwcg_bit = 1, 1361 .clkr = { 1362 .enable_reg = 0x62008, 1363 .enable_mask = BIT(0), 1364 .hw.init = &(const struct clk_init_data) { 1365 .name = "gcc_gemnoc_pcie_qx_clk", 1366 .ops = &clk_branch2_aon_ops, 1367 }, 1368 }, 1369 }; 1370 1371 static struct clk_branch gcc_gp1_clk = { 1372 .halt_reg = 0x74000, 1373 .halt_check = BRANCH_HALT, 1374 .clkr = { 1375 .enable_reg = 0x74000, 1376 .enable_mask = BIT(0), 1377 .hw.init = &(const struct clk_init_data) { 1378 .name = "gcc_gp1_clk", 1379 .parent_hws = (const struct clk_hw*[]) { 1380 &gcc_gp1_clk_src.clkr.hw, 1381 }, 1382 .num_parents = 1, 1383 .flags = CLK_SET_RATE_PARENT, 1384 .ops = &clk_branch2_ops, 1385 }, 1386 }, 1387 }; 1388 1389 static struct clk_branch gcc_gp2_clk = { 1390 .halt_reg = 0x75000, 1391 .halt_check = BRANCH_HALT, 1392 .clkr = { 1393 .enable_reg = 0x75000, 1394 .enable_mask = BIT(0), 1395 .hw.init = &(const struct clk_init_data) { 1396 .name = "gcc_gp2_clk", 1397 .parent_hws = (const struct clk_hw*[]) { 1398 &gcc_gp2_clk_src.clkr.hw, 1399 }, 1400 .num_parents = 1, 1401 .flags = CLK_SET_RATE_PARENT, 1402 .ops = &clk_branch2_ops, 1403 }, 1404 }, 1405 }; 1406 1407 static struct clk_branch gcc_gp3_clk = { 1408 .halt_reg = 0x76000, 1409 .halt_check = BRANCH_HALT, 1410 .clkr = { 1411 .enable_reg = 0x76000, 1412 .enable_mask = BIT(0), 1413 .hw.init = &(const struct clk_init_data) { 1414 .name = "gcc_gp3_clk", 1415 .parent_hws = (const struct clk_hw*[]) { 1416 &gcc_gp3_clk_src.clkr.hw, 1417 }, 1418 .num_parents = 1, 1419 .flags = CLK_SET_RATE_PARENT, 1420 .ops = &clk_branch2_ops, 1421 }, 1422 }, 1423 }; 1424 1425 static struct clk_branch gcc_pcie_0_aux_clk = { 1426 .halt_reg = 0x9d030, 1427 .halt_check = BRANCH_HALT_VOTED, 1428 .hwcg_reg = 0x9d030, 1429 .hwcg_bit = 1, 1430 .clkr = { 1431 .enable_reg = 0x62000, 1432 .enable_mask = BIT(29), 1433 .hw.init = &(const struct clk_init_data) { 1434 .name = "gcc_pcie_0_aux_clk", 1435 .parent_hws = (const struct clk_hw*[]) { 1436 &gcc_pcie_0_aux_clk_src.clkr.hw, 1437 }, 1438 .num_parents = 1, 1439 .flags = CLK_SET_RATE_PARENT, 1440 .ops = &clk_branch2_ops, 1441 }, 1442 }, 1443 }; 1444 1445 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1446 .halt_reg = 0x9d02c, 1447 .halt_check = BRANCH_HALT_VOTED, 1448 .hwcg_reg = 0x9d02c, 1449 .hwcg_bit = 1, 1450 .clkr = { 1451 .enable_reg = 0x62000, 1452 .enable_mask = BIT(28), 1453 .hw.init = &(const struct clk_init_data) { 1454 .name = "gcc_pcie_0_cfg_ahb_clk", 1455 .ops = &clk_branch2_ops, 1456 }, 1457 }, 1458 }; 1459 1460 static struct clk_branch gcc_pcie_0_clkref_en = { 1461 .halt_reg = 0x9c004, 1462 .halt_bit = 31, 1463 .halt_check = BRANCH_HALT_ENABLE, 1464 .clkr = { 1465 .enable_reg = 0x9c004, 1466 .enable_mask = BIT(0), 1467 .hw.init = &(const struct clk_init_data) { 1468 .name = "gcc_pcie_0_clkref_en", 1469 .ops = &clk_branch_ops, 1470 }, 1471 }, 1472 }; 1473 1474 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1475 .halt_reg = 0x9d024, 1476 .halt_check = BRANCH_HALT_SKIP, 1477 .hwcg_reg = 0x9d024, 1478 .hwcg_bit = 1, 1479 .clkr = { 1480 .enable_reg = 0x62000, 1481 .enable_mask = BIT(27), 1482 .hw.init = &(const struct clk_init_data) { 1483 .name = "gcc_pcie_0_mstr_axi_clk", 1484 .ops = &clk_branch2_ops, 1485 }, 1486 }, 1487 }; 1488 1489 static struct clk_branch gcc_pcie_0_phy_aux_clk = { 1490 .halt_reg = 0x9d038, 1491 .halt_check = BRANCH_HALT_VOTED, 1492 .hwcg_reg = 0x9d038, 1493 .hwcg_bit = 1, 1494 .clkr = { 1495 .enable_reg = 0x62000, 1496 .enable_mask = BIT(24), 1497 .hw.init = &(const struct clk_init_data) { 1498 .name = "gcc_pcie_0_phy_aux_clk", 1499 .parent_hws = (const struct clk_hw*[]) { 1500 &gcc_pcie_0_phy_aux_clk_src.clkr.hw, 1501 }, 1502 .num_parents = 1, 1503 .flags = CLK_SET_RATE_PARENT, 1504 .ops = &clk_branch2_ops, 1505 }, 1506 }, 1507 }; 1508 1509 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 1510 .halt_reg = 0x9d048, 1511 .halt_check = BRANCH_HALT_VOTED, 1512 .hwcg_reg = 0x9d048, 1513 .hwcg_bit = 1, 1514 .clkr = { 1515 .enable_reg = 0x62000, 1516 .enable_mask = BIT(23), 1517 .hw.init = &(const struct clk_init_data) { 1518 .name = "gcc_pcie_0_phy_rchng_clk", 1519 .parent_hws = (const struct clk_hw*[]) { 1520 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1521 }, 1522 .num_parents = 1, 1523 .flags = CLK_SET_RATE_PARENT, 1524 .ops = &clk_branch2_ops, 1525 }, 1526 }, 1527 }; 1528 1529 static struct clk_branch gcc_pcie_0_pipe_clk = { 1530 .halt_reg = 0x9d040, 1531 .halt_check = BRANCH_HALT_VOTED, 1532 .hwcg_reg = 0x9d040, 1533 .hwcg_bit = 1, 1534 .clkr = { 1535 .enable_reg = 0x62000, 1536 .enable_mask = BIT(30), 1537 .hw.init = &(const struct clk_init_data) { 1538 .name = "gcc_pcie_0_pipe_clk", 1539 .parent_hws = (const struct clk_hw*[]) { 1540 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1541 }, 1542 .num_parents = 1, 1543 .flags = CLK_SET_RATE_PARENT, 1544 .ops = &clk_branch2_ops, 1545 }, 1546 }, 1547 }; 1548 1549 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1550 .halt_reg = 0x9d01c, 1551 .halt_check = BRANCH_HALT_VOTED, 1552 .hwcg_reg = 0x9d01c, 1553 .hwcg_bit = 1, 1554 .clkr = { 1555 .enable_reg = 0x62000, 1556 .enable_mask = BIT(26), 1557 .hw.init = &(const struct clk_init_data) { 1558 .name = "gcc_pcie_0_slv_axi_clk", 1559 .ops = &clk_branch2_ops, 1560 }, 1561 }, 1562 }; 1563 1564 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1565 .halt_reg = 0x9d018, 1566 .halt_check = BRANCH_HALT_VOTED, 1567 .hwcg_reg = 0x9d018, 1568 .hwcg_bit = 1, 1569 .clkr = { 1570 .enable_reg = 0x62000, 1571 .enable_mask = BIT(25), 1572 .hw.init = &(const struct clk_init_data) { 1573 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1574 .ops = &clk_branch2_ops, 1575 }, 1576 }, 1577 }; 1578 1579 static struct clk_branch gcc_pdm2_clk = { 1580 .halt_reg = 0x4300c, 1581 .halt_check = BRANCH_HALT, 1582 .clkr = { 1583 .enable_reg = 0x4300c, 1584 .enable_mask = BIT(0), 1585 .hw.init = &(const struct clk_init_data) { 1586 .name = "gcc_pdm2_clk", 1587 .parent_hws = (const struct clk_hw*[]) { 1588 &gcc_pdm2_clk_src.clkr.hw, 1589 }, 1590 .num_parents = 1, 1591 .flags = CLK_SET_RATE_PARENT, 1592 .ops = &clk_branch2_ops, 1593 }, 1594 }, 1595 }; 1596 1597 static struct clk_branch gcc_pdm_ahb_clk = { 1598 .halt_reg = 0x43004, 1599 .halt_check = BRANCH_HALT_VOTED, 1600 .hwcg_reg = 0x43004, 1601 .hwcg_bit = 1, 1602 .clkr = { 1603 .enable_reg = 0x43004, 1604 .enable_mask = BIT(0), 1605 .hw.init = &(const struct clk_init_data) { 1606 .name = "gcc_pdm_ahb_clk", 1607 .ops = &clk_branch2_ops, 1608 }, 1609 }, 1610 }; 1611 1612 static struct clk_branch gcc_pdm_xo4_clk = { 1613 .halt_reg = 0x43008, 1614 .halt_check = BRANCH_HALT, 1615 .clkr = { 1616 .enable_reg = 0x43008, 1617 .enable_mask = BIT(0), 1618 .hw.init = &(const struct clk_init_data) { 1619 .name = "gcc_pdm_xo4_clk", 1620 .ops = &clk_branch2_ops, 1621 }, 1622 }, 1623 }; 1624 1625 static struct clk_branch gcc_qmip_anoc_pcie_clk = { 1626 .halt_reg = 0x84044, 1627 .halt_check = BRANCH_HALT_VOTED, 1628 .hwcg_reg = 0x84044, 1629 .hwcg_bit = 1, 1630 .clkr = { 1631 .enable_reg = 0x84044, 1632 .enable_mask = BIT(0), 1633 .hw.init = &(const struct clk_init_data) { 1634 .name = "gcc_qmip_anoc_pcie_clk", 1635 .ops = &clk_branch2_ops, 1636 }, 1637 }, 1638 }; 1639 1640 static struct clk_branch gcc_qmip_ecpri_dma0_clk = { 1641 .halt_reg = 0x84038, 1642 .halt_check = BRANCH_HALT_VOTED, 1643 .hwcg_reg = 0x84038, 1644 .hwcg_bit = 1, 1645 .clkr = { 1646 .enable_reg = 0x84038, 1647 .enable_mask = BIT(0), 1648 .hw.init = &(const struct clk_init_data) { 1649 .name = "gcc_qmip_ecpri_dma0_clk", 1650 .ops = &clk_branch2_ops, 1651 }, 1652 }, 1653 }; 1654 1655 static struct clk_branch gcc_qmip_ecpri_dma1_clk = { 1656 .halt_reg = 0x8403c, 1657 .halt_check = BRANCH_HALT_VOTED, 1658 .hwcg_reg = 0x8403c, 1659 .hwcg_bit = 1, 1660 .clkr = { 1661 .enable_reg = 0x8403c, 1662 .enable_mask = BIT(0), 1663 .hw.init = &(const struct clk_init_data) { 1664 .name = "gcc_qmip_ecpri_dma1_clk", 1665 .ops = &clk_branch2_ops, 1666 }, 1667 }, 1668 }; 1669 1670 static struct clk_branch gcc_qmip_ecpri_gsi_clk = { 1671 .halt_reg = 0x84040, 1672 .halt_check = BRANCH_HALT_VOTED, 1673 .hwcg_reg = 0x84040, 1674 .hwcg_bit = 1, 1675 .clkr = { 1676 .enable_reg = 0x84040, 1677 .enable_mask = BIT(0), 1678 .hw.init = &(const struct clk_init_data) { 1679 .name = "gcc_qmip_ecpri_gsi_clk", 1680 .ops = &clk_branch2_ops, 1681 }, 1682 }, 1683 }; 1684 1685 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 1686 .halt_reg = 0x27018, 1687 .halt_check = BRANCH_HALT_VOTED, 1688 .clkr = { 1689 .enable_reg = 0x62008, 1690 .enable_mask = BIT(9), 1691 .hw.init = &(const struct clk_init_data) { 1692 .name = "gcc_qupv3_wrap0_core_2x_clk", 1693 .ops = &clk_branch2_ops, 1694 }, 1695 }, 1696 }; 1697 1698 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 1699 .halt_reg = 0x2700c, 1700 .halt_check = BRANCH_HALT_VOTED, 1701 .clkr = { 1702 .enable_reg = 0x62008, 1703 .enable_mask = BIT(8), 1704 .hw.init = &(const struct clk_init_data) { 1705 .name = "gcc_qupv3_wrap0_core_clk", 1706 .ops = &clk_branch2_ops, 1707 }, 1708 }, 1709 }; 1710 1711 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 1712 .halt_reg = 0x2714c, 1713 .halt_check = BRANCH_HALT_VOTED, 1714 .clkr = { 1715 .enable_reg = 0x62008, 1716 .enable_mask = BIT(10), 1717 .hw.init = &(const struct clk_init_data) { 1718 .name = "gcc_qupv3_wrap0_s0_clk", 1719 .parent_hws = (const struct clk_hw*[]) { 1720 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 1721 }, 1722 .num_parents = 1, 1723 .flags = CLK_SET_RATE_PARENT, 1724 .ops = &clk_branch2_ops, 1725 }, 1726 }, 1727 }; 1728 1729 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 1730 .halt_reg = 0x27280, 1731 .halt_check = BRANCH_HALT_VOTED, 1732 .clkr = { 1733 .enable_reg = 0x62008, 1734 .enable_mask = BIT(11), 1735 .hw.init = &(const struct clk_init_data) { 1736 .name = "gcc_qupv3_wrap0_s1_clk", 1737 .parent_hws = (const struct clk_hw*[]) { 1738 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 1739 }, 1740 .num_parents = 1, 1741 .flags = CLK_SET_RATE_PARENT, 1742 .ops = &clk_branch2_ops, 1743 }, 1744 }, 1745 }; 1746 1747 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 1748 .halt_reg = 0x273b4, 1749 .halt_check = BRANCH_HALT_VOTED, 1750 .clkr = { 1751 .enable_reg = 0x62008, 1752 .enable_mask = BIT(12), 1753 .hw.init = &(const struct clk_init_data) { 1754 .name = "gcc_qupv3_wrap0_s2_clk", 1755 .parent_hws = (const struct clk_hw*[]) { 1756 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 1757 }, 1758 .num_parents = 1, 1759 .flags = CLK_SET_RATE_PARENT, 1760 .ops = &clk_branch2_ops, 1761 }, 1762 }, 1763 }; 1764 1765 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 1766 .halt_reg = 0x274e8, 1767 .halt_check = BRANCH_HALT_VOTED, 1768 .clkr = { 1769 .enable_reg = 0x62008, 1770 .enable_mask = BIT(13), 1771 .hw.init = &(const struct clk_init_data) { 1772 .name = "gcc_qupv3_wrap0_s3_clk", 1773 .parent_hws = (const struct clk_hw*[]) { 1774 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 1775 }, 1776 .num_parents = 1, 1777 .flags = CLK_SET_RATE_PARENT, 1778 .ops = &clk_branch2_ops, 1779 }, 1780 }, 1781 }; 1782 1783 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 1784 .halt_reg = 0x2761c, 1785 .halt_check = BRANCH_HALT_VOTED, 1786 .clkr = { 1787 .enable_reg = 0x62008, 1788 .enable_mask = BIT(14), 1789 .hw.init = &(const struct clk_init_data) { 1790 .name = "gcc_qupv3_wrap0_s4_clk", 1791 .parent_hws = (const struct clk_hw*[]) { 1792 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 1793 }, 1794 .num_parents = 1, 1795 .flags = CLK_SET_RATE_PARENT, 1796 .ops = &clk_branch2_ops, 1797 }, 1798 }, 1799 }; 1800 1801 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 1802 .halt_reg = 0x27750, 1803 .halt_check = BRANCH_HALT_VOTED, 1804 .clkr = { 1805 .enable_reg = 0x62008, 1806 .enable_mask = BIT(15), 1807 .hw.init = &(const struct clk_init_data) { 1808 .name = "gcc_qupv3_wrap0_s5_clk", 1809 .parent_hws = (const struct clk_hw*[]) { 1810 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 1811 }, 1812 .num_parents = 1, 1813 .flags = CLK_SET_RATE_PARENT, 1814 .ops = &clk_branch2_ops, 1815 }, 1816 }, 1817 }; 1818 1819 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 1820 .halt_reg = 0x27884, 1821 .halt_check = BRANCH_HALT_VOTED, 1822 .clkr = { 1823 .enable_reg = 0x62008, 1824 .enable_mask = BIT(16), 1825 .hw.init = &(const struct clk_init_data) { 1826 .name = "gcc_qupv3_wrap0_s6_clk", 1827 .parent_hws = (const struct clk_hw*[]) { 1828 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 1829 }, 1830 .num_parents = 1, 1831 .flags = CLK_SET_RATE_PARENT, 1832 .ops = &clk_branch2_ops, 1833 }, 1834 }, 1835 }; 1836 1837 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 1838 .halt_reg = 0x279b8, 1839 .halt_check = BRANCH_HALT_VOTED, 1840 .clkr = { 1841 .enable_reg = 0x62008, 1842 .enable_mask = BIT(17), 1843 .hw.init = &(const struct clk_init_data) { 1844 .name = "gcc_qupv3_wrap0_s7_clk", 1845 .parent_hws = (const struct clk_hw*[]) { 1846 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 1847 }, 1848 .num_parents = 1, 1849 .flags = CLK_SET_RATE_PARENT, 1850 .ops = &clk_branch2_ops, 1851 }, 1852 }, 1853 }; 1854 1855 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 1856 .halt_reg = 0x28018, 1857 .halt_check = BRANCH_HALT_VOTED, 1858 .clkr = { 1859 .enable_reg = 0x62008, 1860 .enable_mask = BIT(18), 1861 .hw.init = &(const struct clk_init_data) { 1862 .name = "gcc_qupv3_wrap1_core_2x_clk", 1863 .ops = &clk_branch2_ops, 1864 }, 1865 }, 1866 }; 1867 1868 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 1869 .halt_reg = 0x2800c, 1870 .halt_check = BRANCH_HALT_VOTED, 1871 .clkr = { 1872 .enable_reg = 0x62008, 1873 .enable_mask = BIT(19), 1874 .hw.init = &(const struct clk_init_data) { 1875 .name = "gcc_qupv3_wrap1_core_clk", 1876 .ops = &clk_branch2_ops, 1877 }, 1878 }, 1879 }; 1880 1881 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 1882 .halt_reg = 0x2814c, 1883 .halt_check = BRANCH_HALT_VOTED, 1884 .clkr = { 1885 .enable_reg = 0x62008, 1886 .enable_mask = BIT(22), 1887 .hw.init = &(const struct clk_init_data) { 1888 .name = "gcc_qupv3_wrap1_s0_clk", 1889 .parent_hws = (const struct clk_hw*[]) { 1890 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 1891 }, 1892 .num_parents = 1, 1893 .flags = CLK_SET_RATE_PARENT, 1894 .ops = &clk_branch2_ops, 1895 }, 1896 }, 1897 }; 1898 1899 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 1900 .halt_reg = 0x28280, 1901 .halt_check = BRANCH_HALT_VOTED, 1902 .clkr = { 1903 .enable_reg = 0x62008, 1904 .enable_mask = BIT(23), 1905 .hw.init = &(const struct clk_init_data) { 1906 .name = "gcc_qupv3_wrap1_s1_clk", 1907 .parent_hws = (const struct clk_hw*[]) { 1908 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 1909 }, 1910 .num_parents = 1, 1911 .flags = CLK_SET_RATE_PARENT, 1912 .ops = &clk_branch2_ops, 1913 }, 1914 }, 1915 }; 1916 1917 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 1918 .halt_reg = 0x283b4, 1919 .halt_check = BRANCH_HALT_VOTED, 1920 .clkr = { 1921 .enable_reg = 0x62008, 1922 .enable_mask = BIT(24), 1923 .hw.init = &(const struct clk_init_data) { 1924 .name = "gcc_qupv3_wrap1_s2_clk", 1925 .parent_hws = (const struct clk_hw*[]) { 1926 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 1927 }, 1928 .num_parents = 1, 1929 .flags = CLK_SET_RATE_PARENT, 1930 .ops = &clk_branch2_ops, 1931 }, 1932 }, 1933 }; 1934 1935 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 1936 .halt_reg = 0x284e8, 1937 .halt_check = BRANCH_HALT_VOTED, 1938 .clkr = { 1939 .enable_reg = 0x62008, 1940 .enable_mask = BIT(25), 1941 .hw.init = &(const struct clk_init_data) { 1942 .name = "gcc_qupv3_wrap1_s3_clk", 1943 .parent_hws = (const struct clk_hw*[]) { 1944 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 1945 }, 1946 .num_parents = 1, 1947 .flags = CLK_SET_RATE_PARENT, 1948 .ops = &clk_branch2_ops, 1949 }, 1950 }, 1951 }; 1952 1953 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 1954 .halt_reg = 0x2861c, 1955 .halt_check = BRANCH_HALT_VOTED, 1956 .clkr = { 1957 .enable_reg = 0x62008, 1958 .enable_mask = BIT(26), 1959 .hw.init = &(const struct clk_init_data) { 1960 .name = "gcc_qupv3_wrap1_s4_clk", 1961 .parent_hws = (const struct clk_hw*[]) { 1962 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 1963 }, 1964 .num_parents = 1, 1965 .flags = CLK_SET_RATE_PARENT, 1966 .ops = &clk_branch2_ops, 1967 }, 1968 }, 1969 }; 1970 1971 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 1972 .halt_reg = 0x28750, 1973 .halt_check = BRANCH_HALT_VOTED, 1974 .clkr = { 1975 .enable_reg = 0x62008, 1976 .enable_mask = BIT(27), 1977 .hw.init = &(const struct clk_init_data) { 1978 .name = "gcc_qupv3_wrap1_s5_clk", 1979 .parent_hws = (const struct clk_hw*[]) { 1980 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 1981 }, 1982 .num_parents = 1, 1983 .flags = CLK_SET_RATE_PARENT, 1984 .ops = &clk_branch2_ops, 1985 }, 1986 }, 1987 }; 1988 1989 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 1990 .halt_reg = 0x28884, 1991 .halt_check = BRANCH_HALT_VOTED, 1992 .clkr = { 1993 .enable_reg = 0x62008, 1994 .enable_mask = BIT(28), 1995 .hw.init = &(const struct clk_init_data) { 1996 .name = "gcc_qupv3_wrap1_s6_clk", 1997 .parent_hws = (const struct clk_hw*[]) { 1998 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 1999 }, 2000 .num_parents = 1, 2001 .flags = CLK_SET_RATE_PARENT, 2002 .ops = &clk_branch2_ops, 2003 }, 2004 }, 2005 }; 2006 2007 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 2008 .halt_reg = 0x289b8, 2009 .halt_check = BRANCH_HALT_VOTED, 2010 .clkr = { 2011 .enable_reg = 0x62008, 2012 .enable_mask = BIT(29), 2013 .hw.init = &(const struct clk_init_data) { 2014 .name = "gcc_qupv3_wrap1_s7_clk", 2015 .parent_hws = (const struct clk_hw*[]) { 2016 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 2017 }, 2018 .num_parents = 1, 2019 .flags = CLK_SET_RATE_PARENT, 2020 .ops = &clk_branch2_ops, 2021 }, 2022 }, 2023 }; 2024 2025 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2026 .halt_reg = 0x27004, 2027 .halt_check = BRANCH_HALT_VOTED, 2028 .hwcg_reg = 0x27004, 2029 .hwcg_bit = 1, 2030 .clkr = { 2031 .enable_reg = 0x62008, 2032 .enable_mask = BIT(6), 2033 .hw.init = &(const struct clk_init_data) { 2034 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2035 .ops = &clk_branch2_ops, 2036 }, 2037 }, 2038 }; 2039 2040 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2041 .halt_reg = 0x27008, 2042 .halt_check = BRANCH_HALT_VOTED, 2043 .hwcg_reg = 0x27008, 2044 .hwcg_bit = 1, 2045 .clkr = { 2046 .enable_reg = 0x62008, 2047 .enable_mask = BIT(7), 2048 .hw.init = &(const struct clk_init_data) { 2049 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2050 .ops = &clk_branch2_ops, 2051 }, 2052 }, 2053 }; 2054 2055 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2056 .halt_reg = 0x28004, 2057 .halt_check = BRANCH_HALT_VOTED, 2058 .hwcg_reg = 0x28004, 2059 .hwcg_bit = 1, 2060 .clkr = { 2061 .enable_reg = 0x62008, 2062 .enable_mask = BIT(20), 2063 .hw.init = &(const struct clk_init_data) { 2064 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2065 .ops = &clk_branch2_ops, 2066 }, 2067 }, 2068 }; 2069 2070 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2071 .halt_reg = 0x28008, 2072 .halt_check = BRANCH_HALT_VOTED, 2073 .hwcg_reg = 0x28008, 2074 .hwcg_bit = 1, 2075 .clkr = { 2076 .enable_reg = 0x62008, 2077 .enable_mask = BIT(21), 2078 .hw.init = &(const struct clk_init_data) { 2079 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2080 .ops = &clk_branch2_ops, 2081 }, 2082 }, 2083 }; 2084 2085 static struct clk_branch gcc_sdcc5_ahb_clk = { 2086 .halt_reg = 0x3b00c, 2087 .halt_check = BRANCH_HALT, 2088 .clkr = { 2089 .enable_reg = 0x3b00c, 2090 .enable_mask = BIT(0), 2091 .hw.init = &(const struct clk_init_data) { 2092 .name = "gcc_sdcc5_ahb_clk", 2093 .ops = &clk_branch2_ops, 2094 }, 2095 }, 2096 }; 2097 2098 static struct clk_branch gcc_sdcc5_apps_clk = { 2099 .halt_reg = 0x3b004, 2100 .halt_check = BRANCH_HALT, 2101 .clkr = { 2102 .enable_reg = 0x3b004, 2103 .enable_mask = BIT(0), 2104 .hw.init = &(const struct clk_init_data) { 2105 .name = "gcc_sdcc5_apps_clk", 2106 .parent_hws = (const struct clk_hw*[]) { 2107 &gcc_sdcc5_apps_clk_src.clkr.hw, 2108 }, 2109 .num_parents = 1, 2110 .flags = CLK_SET_RATE_PARENT, 2111 .ops = &clk_branch2_ops, 2112 }, 2113 }, 2114 }; 2115 2116 static struct clk_branch gcc_sdcc5_ice_core_clk = { 2117 .halt_reg = 0x3b010, 2118 .halt_check = BRANCH_HALT, 2119 .clkr = { 2120 .enable_reg = 0x3b010, 2121 .enable_mask = BIT(0), 2122 .hw.init = &(const struct clk_init_data) { 2123 .name = "gcc_sdcc5_ice_core_clk", 2124 .parent_hws = (const struct clk_hw*[]) { 2125 &gcc_sdcc5_ice_core_clk_src.clkr.hw, 2126 }, 2127 .num_parents = 1, 2128 .flags = CLK_SET_RATE_PARENT, 2129 .ops = &clk_branch2_ops, 2130 }, 2131 }, 2132 }; 2133 2134 static struct clk_branch gcc_sm_bus_ahb_clk = { 2135 .halt_reg = 0x5b004, 2136 .halt_check = BRANCH_HALT, 2137 .clkr = { 2138 .enable_reg = 0x5b004, 2139 .enable_mask = BIT(0), 2140 .hw.init = &(const struct clk_init_data) { 2141 .name = "gcc_sm_bus_ahb_clk", 2142 .ops = &clk_branch2_ops, 2143 }, 2144 }, 2145 }; 2146 2147 static struct clk_branch gcc_sm_bus_xo_clk = { 2148 .halt_reg = 0x5b008, 2149 .halt_check = BRANCH_HALT, 2150 .clkr = { 2151 .enable_reg = 0x5b008, 2152 .enable_mask = BIT(0), 2153 .hw.init = &(const struct clk_init_data) { 2154 .name = "gcc_sm_bus_xo_clk", 2155 .parent_hws = (const struct clk_hw*[]) { 2156 &gcc_sm_bus_xo_clk_src.clkr.hw, 2157 }, 2158 .num_parents = 1, 2159 .flags = CLK_SET_RATE_PARENT, 2160 .ops = &clk_branch2_ops, 2161 }, 2162 }, 2163 }; 2164 2165 static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_qx_clk = { 2166 .halt_reg = 0x9200c, 2167 .halt_check = BRANCH_HALT_SKIP, 2168 .hwcg_reg = 0x9200c, 2169 .hwcg_bit = 1, 2170 .clkr = { 2171 .enable_reg = 0x62000, 2172 .enable_mask = BIT(11), 2173 .hw.init = &(const struct clk_init_data) { 2174 .name = "gcc_snoc_cnoc_gemnoc_pcie_qx_clk", 2175 .ops = &clk_branch2_ops, 2176 }, 2177 }, 2178 }; 2179 2180 static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk = { 2181 .halt_reg = 0x92010, 2182 .halt_check = BRANCH_HALT_SKIP, 2183 .hwcg_reg = 0x92010, 2184 .hwcg_bit = 1, 2185 .clkr = { 2186 .enable_reg = 0x62000, 2187 .enable_mask = BIT(12), 2188 .hw.init = &(const struct clk_init_data) { 2189 .name = "gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk", 2190 .ops = &clk_branch2_ops, 2191 }, 2192 }, 2193 }; 2194 2195 static struct clk_branch gcc_snoc_cnoc_pcie_qx_clk = { 2196 .halt_reg = 0x84030, 2197 .halt_check = BRANCH_HALT, 2198 .clkr = { 2199 .enable_reg = 0x84030, 2200 .enable_mask = BIT(0), 2201 .hw.init = &(const struct clk_init_data) { 2202 .name = "gcc_snoc_cnoc_pcie_qx_clk", 2203 .ops = &clk_branch2_ops, 2204 }, 2205 }, 2206 }; 2207 2208 static struct clk_branch gcc_snoc_pcie_sf_center_qx_clk = { 2209 .halt_reg = 0x92014, 2210 .halt_check = BRANCH_HALT_SKIP, 2211 .hwcg_reg = 0x92014, 2212 .hwcg_bit = 1, 2213 .clkr = { 2214 .enable_reg = 0x62000, 2215 .enable_mask = BIT(19), 2216 .hw.init = &(const struct clk_init_data) { 2217 .name = "gcc_snoc_pcie_sf_center_qx_clk", 2218 .ops = &clk_branch2_ops, 2219 }, 2220 }, 2221 }; 2222 2223 static struct clk_branch gcc_snoc_pcie_sf_south_qx_clk = { 2224 .halt_reg = 0x92018, 2225 .halt_check = BRANCH_HALT_SKIP, 2226 .hwcg_reg = 0x92018, 2227 .hwcg_bit = 1, 2228 .clkr = { 2229 .enable_reg = 0x62000, 2230 .enable_mask = BIT(22), 2231 .hw.init = &(const struct clk_init_data) { 2232 .name = "gcc_snoc_pcie_sf_south_qx_clk", 2233 .ops = &clk_branch2_ops, 2234 }, 2235 }, 2236 }; 2237 2238 static struct clk_branch gcc_tsc_cfg_ahb_clk = { 2239 .halt_reg = 0x5700c, 2240 .halt_check = BRANCH_HALT, 2241 .clkr = { 2242 .enable_reg = 0x5700c, 2243 .enable_mask = BIT(0), 2244 .hw.init = &(const struct clk_init_data) { 2245 .name = "gcc_tsc_cfg_ahb_clk", 2246 .ops = &clk_branch2_ops, 2247 }, 2248 }, 2249 }; 2250 2251 static struct clk_branch gcc_tsc_cntr_clk = { 2252 .halt_reg = 0x57004, 2253 .halt_check = BRANCH_HALT, 2254 .clkr = { 2255 .enable_reg = 0x57004, 2256 .enable_mask = BIT(0), 2257 .hw.init = &(const struct clk_init_data) { 2258 .name = "gcc_tsc_cntr_clk", 2259 .parent_hws = (const struct clk_hw*[]) { 2260 &gcc_tsc_clk_src.clkr.hw, 2261 }, 2262 .num_parents = 1, 2263 .flags = CLK_SET_RATE_PARENT, 2264 .ops = &clk_branch2_ops, 2265 }, 2266 }, 2267 }; 2268 2269 static struct clk_branch gcc_tsc_etu_clk = { 2270 .halt_reg = 0x57008, 2271 .halt_check = BRANCH_HALT, 2272 .clkr = { 2273 .enable_reg = 0x57008, 2274 .enable_mask = BIT(0), 2275 .hw.init = &(const struct clk_init_data) { 2276 .name = "gcc_tsc_etu_clk", 2277 .parent_hws = (const struct clk_hw*[]) { 2278 &gcc_tsc_clk_src.clkr.hw, 2279 }, 2280 .num_parents = 1, 2281 .flags = CLK_SET_RATE_PARENT, 2282 .ops = &clk_branch2_ops, 2283 }, 2284 }, 2285 }; 2286 2287 static struct clk_branch gcc_usb2_clkref_en = { 2288 .halt_reg = 0x9c008, 2289 .halt_bit = 31, 2290 .halt_check = BRANCH_HALT_ENABLE, 2291 .clkr = { 2292 .enable_reg = 0x9c008, 2293 .enable_mask = BIT(0), 2294 .hw.init = &(const struct clk_init_data) { 2295 .name = "gcc_usb2_clkref_en", 2296 .ops = &clk_branch_ops, 2297 }, 2298 }, 2299 }; 2300 2301 static struct clk_branch gcc_usb30_prim_master_clk = { 2302 .halt_reg = 0x49018, 2303 .halt_check = BRANCH_HALT, 2304 .clkr = { 2305 .enable_reg = 0x49018, 2306 .enable_mask = BIT(0), 2307 .hw.init = &(const struct clk_init_data) { 2308 .name = "gcc_usb30_prim_master_clk", 2309 .parent_hws = (const struct clk_hw*[]) { 2310 &gcc_usb30_prim_master_clk_src.clkr.hw, 2311 }, 2312 .num_parents = 1, 2313 .flags = CLK_SET_RATE_PARENT, 2314 .ops = &clk_branch2_ops, 2315 }, 2316 }, 2317 }; 2318 2319 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2320 .halt_reg = 0x49024, 2321 .halt_check = BRANCH_HALT, 2322 .clkr = { 2323 .enable_reg = 0x49024, 2324 .enable_mask = BIT(0), 2325 .hw.init = &(const struct clk_init_data) { 2326 .name = "gcc_usb30_prim_mock_utmi_clk", 2327 .parent_hws = (const struct clk_hw*[]) { 2328 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2329 }, 2330 .num_parents = 1, 2331 .flags = CLK_SET_RATE_PARENT, 2332 .ops = &clk_branch2_ops, 2333 }, 2334 }, 2335 }; 2336 2337 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2338 .halt_reg = 0x49020, 2339 .halt_check = BRANCH_HALT, 2340 .clkr = { 2341 .enable_reg = 0x49020, 2342 .enable_mask = BIT(0), 2343 .hw.init = &(const struct clk_init_data) { 2344 .name = "gcc_usb30_prim_sleep_clk", 2345 .ops = &clk_branch2_ops, 2346 }, 2347 }, 2348 }; 2349 2350 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2351 .halt_reg = 0x49060, 2352 .halt_check = BRANCH_HALT, 2353 .clkr = { 2354 .enable_reg = 0x49060, 2355 .enable_mask = BIT(0), 2356 .hw.init = &(const struct clk_init_data) { 2357 .name = "gcc_usb3_prim_phy_aux_clk", 2358 .parent_hws = (const struct clk_hw*[]) { 2359 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2360 }, 2361 .num_parents = 1, 2362 .flags = CLK_SET_RATE_PARENT, 2363 .ops = &clk_branch2_ops, 2364 }, 2365 }, 2366 }; 2367 2368 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2369 .halt_reg = 0x49064, 2370 .halt_check = BRANCH_HALT, 2371 .clkr = { 2372 .enable_reg = 0x49064, 2373 .enable_mask = BIT(0), 2374 .hw.init = &(const struct clk_init_data) { 2375 .name = "gcc_usb3_prim_phy_com_aux_clk", 2376 .parent_hws = (const struct clk_hw*[]) { 2377 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2378 }, 2379 .num_parents = 1, 2380 .flags = CLK_SET_RATE_PARENT, 2381 .ops = &clk_branch2_ops, 2382 }, 2383 }, 2384 }; 2385 2386 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2387 .halt_reg = 0x49068, 2388 .halt_check = BRANCH_HALT_DELAY, 2389 .hwcg_reg = 0x49068, 2390 .hwcg_bit = 1, 2391 .clkr = { 2392 .enable_reg = 0x49068, 2393 .enable_mask = BIT(0), 2394 .hw.init = &(const struct clk_init_data) { 2395 .name = "gcc_usb3_prim_phy_pipe_clk", 2396 .parent_hws = (const struct clk_hw*[]) { 2397 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 2398 }, 2399 .num_parents = 1, 2400 .flags = CLK_SET_RATE_PARENT, 2401 .ops = &clk_branch2_ops, 2402 }, 2403 }, 2404 }; 2405 2406 static struct clk_regmap *gcc_qdu1000_clocks[] = { 2407 [GCC_AGGRE_NOC_ECPRI_DMA_CLK] = &gcc_aggre_noc_ecpri_dma_clk.clkr, 2408 [GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC] = &gcc_aggre_noc_ecpri_dma_clk_src.clkr, 2409 [GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC] = &gcc_aggre_noc_ecpri_gsi_clk_src.clkr, 2410 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2411 [GCC_CFG_NOC_ECPRI_CC_AHB_CLK] = &gcc_cfg_noc_ecpri_cc_ahb_clk.clkr, 2412 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2413 [GCC_DDRSS_ECPRI_DMA_CLK] = &gcc_ddrss_ecpri_dma_clk.clkr, 2414 [GCC_ECPRI_AHB_CLK] = &gcc_ecpri_ahb_clk.clkr, 2415 [GCC_ECPRI_CC_GPLL0_CLK_SRC] = &gcc_ecpri_cc_gpll0_clk_src.clkr, 2416 [GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll1_even_clk_src.clkr, 2417 [GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll2_even_clk_src.clkr, 2418 [GCC_ECPRI_CC_GPLL3_CLK_SRC] = &gcc_ecpri_cc_gpll3_clk_src.clkr, 2419 [GCC_ECPRI_CC_GPLL4_CLK_SRC] = &gcc_ecpri_cc_gpll4_clk_src.clkr, 2420 [GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll5_even_clk_src.clkr, 2421 [GCC_ECPRI_XO_CLK] = &gcc_ecpri_xo_clk.clkr, 2422 [GCC_ETH_DBG_SNOC_AXI_CLK] = &gcc_eth_dbg_snoc_axi_clk.clkr, 2423 [GCC_GEMNOC_PCIE_QX_CLK] = &gcc_gemnoc_pcie_qx_clk.clkr, 2424 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2425 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2426 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2427 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2428 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2429 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2430 [GCC_GPLL0] = &gcc_gpll0.clkr, 2431 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 2432 [GCC_GPLL1] = &gcc_gpll1.clkr, 2433 [GCC_GPLL2] = &gcc_gpll2.clkr, 2434 [GCC_GPLL2_OUT_EVEN] = &gcc_gpll2_out_even.clkr, 2435 [GCC_GPLL3] = &gcc_gpll3.clkr, 2436 [GCC_GPLL4] = &gcc_gpll4.clkr, 2437 [GCC_GPLL5] = &gcc_gpll5.clkr, 2438 [GCC_GPLL5_OUT_EVEN] = &gcc_gpll5_out_even.clkr, 2439 [GCC_GPLL6] = &gcc_gpll6.clkr, 2440 [GCC_GPLL7] = &gcc_gpll7.clkr, 2441 [GCC_GPLL8] = &gcc_gpll8.clkr, 2442 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2443 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 2444 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2445 [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr, 2446 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2447 [GCC_PCIE_0_PHY_AUX_CLK] = &gcc_pcie_0_phy_aux_clk.clkr, 2448 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 2449 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 2450 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2451 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2452 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 2453 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2454 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 2455 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2456 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2457 [GCC_QMIP_ANOC_PCIE_CLK] = &gcc_qmip_anoc_pcie_clk.clkr, 2458 [GCC_QMIP_ECPRI_DMA0_CLK] = &gcc_qmip_ecpri_dma0_clk.clkr, 2459 [GCC_QMIP_ECPRI_DMA1_CLK] = &gcc_qmip_ecpri_dma1_clk.clkr, 2460 [GCC_QMIP_ECPRI_GSI_CLK] = &gcc_qmip_ecpri_gsi_clk.clkr, 2461 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 2462 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 2463 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 2464 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 2465 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 2466 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 2467 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 2468 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 2469 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 2470 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 2471 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 2472 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 2473 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 2474 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 2475 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 2476 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 2477 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 2478 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 2479 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 2480 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 2481 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 2482 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 2483 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 2484 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 2485 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 2486 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 2487 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 2488 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 2489 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 2490 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 2491 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 2492 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 2493 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 2494 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 2495 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 2496 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 2497 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 2498 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 2499 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 2500 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 2501 [GCC_SDCC5_AHB_CLK] = &gcc_sdcc5_ahb_clk.clkr, 2502 [GCC_SDCC5_APPS_CLK] = &gcc_sdcc5_apps_clk.clkr, 2503 [GCC_SDCC5_APPS_CLK_SRC] = &gcc_sdcc5_apps_clk_src.clkr, 2504 [GCC_SDCC5_ICE_CORE_CLK] = &gcc_sdcc5_ice_core_clk.clkr, 2505 [GCC_SDCC5_ICE_CORE_CLK_SRC] = &gcc_sdcc5_ice_core_clk_src.clkr, 2506 [GCC_SM_BUS_AHB_CLK] = &gcc_sm_bus_ahb_clk.clkr, 2507 [GCC_SM_BUS_XO_CLK] = &gcc_sm_bus_xo_clk.clkr, 2508 [GCC_SM_BUS_XO_CLK_SRC] = &gcc_sm_bus_xo_clk_src.clkr, 2509 [GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK] = &gcc_snoc_cnoc_gemnoc_pcie_qx_clk.clkr, 2510 [GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK] = &gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk.clkr, 2511 [GCC_SNOC_CNOC_PCIE_QX_CLK] = &gcc_snoc_cnoc_pcie_qx_clk.clkr, 2512 [GCC_SNOC_PCIE_SF_CENTER_QX_CLK] = &gcc_snoc_pcie_sf_center_qx_clk.clkr, 2513 [GCC_SNOC_PCIE_SF_SOUTH_QX_CLK] = &gcc_snoc_pcie_sf_south_qx_clk.clkr, 2514 [GCC_TSC_CFG_AHB_CLK] = &gcc_tsc_cfg_ahb_clk.clkr, 2515 [GCC_TSC_CLK_SRC] = &gcc_tsc_clk_src.clkr, 2516 [GCC_TSC_CNTR_CLK] = &gcc_tsc_cntr_clk.clkr, 2517 [GCC_TSC_ETU_CLK] = &gcc_tsc_etu_clk.clkr, 2518 [GCC_USB2_CLKREF_EN] = &gcc_usb2_clkref_en.clkr, 2519 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 2520 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 2521 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 2522 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 2523 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 2524 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 2525 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 2526 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 2527 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 2528 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 2529 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 2530 [GCC_ETH_100G_C2C_HM_APB_CLK] = &gcc_eth_100g_c2c_hm_apb_clk.clkr, 2531 [GCC_ETH_100G_FH_HM_APB_0_CLK] = &gcc_eth_100g_fh_hm_apb_0_clk.clkr, 2532 [GCC_ETH_100G_FH_HM_APB_1_CLK] = &gcc_eth_100g_fh_hm_apb_1_clk.clkr, 2533 [GCC_ETH_100G_FH_HM_APB_2_CLK] = &gcc_eth_100g_fh_hm_apb_2_clk.clkr, 2534 [GCC_ETH_DBG_C2C_HM_APB_CLK] = &gcc_eth_dbg_c2c_hm_apb_clk.clkr, 2535 [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr, 2536 [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, 2537 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 2538 }; 2539 2540 static const struct qcom_reset_map gcc_qdu1000_resets[] = { 2541 [GCC_ECPRI_CC_BCR] = { 0x3e000 }, 2542 [GCC_ECPRI_SS_BCR] = { 0x3a000 }, 2543 [GCC_ETH_WRAPPER_BCR] = { 0x39000 }, 2544 [GCC_PCIE_0_BCR] = { 0x9d000 }, 2545 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x9e014 }, 2546 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x9e020 }, 2547 [GCC_PCIE_0_PHY_BCR] = { 0x7c000 }, 2548 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 }, 2549 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c }, 2550 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 }, 2551 [GCC_PDM_BCR] = { 0x43000 }, 2552 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 }, 2553 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 }, 2554 [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 }, 2555 [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 }, 2556 [GCC_SDCC5_BCR] = { 0x3b000 }, 2557 [GCC_TSC_BCR] = { 0x57000 }, 2558 [GCC_USB30_PRIM_BCR] = { 0x49000 }, 2559 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 }, 2560 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 }, 2561 [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 }, 2562 [GCC_USB3_PHY_SEC_BCR] = { 0x6000c }, 2563 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 }, 2564 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 }, 2565 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 }, 2566 }; 2567 2568 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 2569 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 2570 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 2571 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 2572 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 2573 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 2574 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 2575 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 2576 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 2577 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 2578 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 2579 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 2580 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 2581 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 2582 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 2583 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 2584 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 2585 }; 2586 2587 static const struct regmap_config gcc_qdu1000_regmap_config = { 2588 .reg_bits = 32, 2589 .reg_stride = 4, 2590 .val_bits = 32, 2591 .max_register = 0x1f41f0, 2592 .fast_io = true, 2593 }; 2594 2595 static const struct qcom_cc_desc gcc_qdu1000_desc = { 2596 .config = &gcc_qdu1000_regmap_config, 2597 .clks = gcc_qdu1000_clocks, 2598 .num_clks = ARRAY_SIZE(gcc_qdu1000_clocks), 2599 .resets = gcc_qdu1000_resets, 2600 .num_resets = ARRAY_SIZE(gcc_qdu1000_resets), 2601 }; 2602 2603 static const struct of_device_id gcc_qdu1000_match_table[] = { 2604 { .compatible = "qcom,qdu1000-gcc" }, 2605 { } 2606 }; 2607 MODULE_DEVICE_TABLE(of, gcc_qdu1000_match_table); 2608 2609 static int gcc_qdu1000_probe(struct platform_device *pdev) 2610 { 2611 struct regmap *regmap; 2612 int ret; 2613 2614 regmap = qcom_cc_map(pdev, &gcc_qdu1000_desc); 2615 if (IS_ERR(regmap)) 2616 return PTR_ERR(regmap); 2617 2618 /* Update FORCE_MEM_CORE_ON for gcc_pcie_0_mstr_axi_clk */ 2619 regmap_update_bits(regmap, 0x9d024, BIT(14), BIT(14)); 2620 2621 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 2622 ARRAY_SIZE(gcc_dfs_clocks)); 2623 if (ret) 2624 return ret; 2625 2626 ret = qcom_cc_really_probe(pdev, &gcc_qdu1000_desc, regmap); 2627 if (ret) 2628 return dev_err_probe(&pdev->dev, ret, "Failed to register GCC clocks\n"); 2629 2630 return ret; 2631 } 2632 2633 static struct platform_driver gcc_qdu1000_driver = { 2634 .probe = gcc_qdu1000_probe, 2635 .driver = { 2636 .name = "gcc-qdu1000", 2637 .of_match_table = gcc_qdu1000_match_table, 2638 }, 2639 }; 2640 2641 static int __init gcc_qdu1000_init(void) 2642 { 2643 return platform_driver_register(&gcc_qdu1000_driver); 2644 } 2645 subsys_initcall(gcc_qdu1000_init); 2646 2647 static void __exit gcc_qdu1000_exit(void) 2648 { 2649 platform_driver_unregister(&gcc_qdu1000_driver); 2650 } 2651 module_exit(gcc_qdu1000_exit); 2652 2653 MODULE_DESCRIPTION("QTI GCC QDU1000 Driver"); 2654 MODULE_LICENSE("GPL"); 2655