1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/of_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,qdu1000-gcc.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-rcg.h" 16 #include "clk-regmap.h" 17 #include "clk-regmap-divider.h" 18 #include "clk-regmap-mux.h" 19 #include "clk-regmap-phy-mux.h" 20 #include "gdsc.h" 21 #include "reset.h" 22 23 enum { 24 P_BI_TCXO, 25 P_GCC_GPLL0_OUT_EVEN, 26 P_GCC_GPLL0_OUT_MAIN, 27 P_GCC_GPLL1_OUT_MAIN, 28 P_GCC_GPLL2_OUT_MAIN, 29 P_GCC_GPLL3_OUT_MAIN, 30 P_GCC_GPLL4_OUT_MAIN, 31 P_GCC_GPLL5_OUT_MAIN, 32 P_GCC_GPLL6_OUT_MAIN, 33 P_GCC_GPLL7_OUT_MAIN, 34 P_GCC_GPLL8_OUT_MAIN, 35 P_PCIE_0_PHY_AUX_CLK, 36 P_PCIE_0_PIPE_CLK, 37 P_SLEEP_CLK, 38 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 39 }; 40 41 enum { 42 DT_TCXO_IDX, 43 DT_SLEEP_CLK_IDX, 44 DT_PCIE_0_PIPE_CLK_IDX, 45 DT_PCIE_0_PHY_AUX_CLK_IDX, 46 DT_USB3_PHY_WRAPPER_PIPE_CLK_IDX, 47 }; 48 49 static struct clk_alpha_pll gcc_gpll0 = { 50 .offset = 0x0, 51 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 52 .clkr = { 53 .enable_reg = 0x62018, 54 .enable_mask = BIT(0), 55 .hw.init = &(const struct clk_init_data) { 56 .name = "gcc_gpll0", 57 .parent_data = &(const struct clk_parent_data) { 58 .index = DT_TCXO_IDX, 59 }, 60 .num_parents = 1, 61 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 62 }, 63 }, 64 }; 65 66 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 67 { 0x1, 2 } 68 }; 69 70 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 71 .offset = 0x0, 72 .post_div_shift = 10, 73 .post_div_table = post_div_table_gcc_gpll0_out_even, 74 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 75 .width = 4, 76 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 77 .clkr.hw.init = &(const struct clk_init_data) { 78 .name = "gcc_gpll0_out_even", 79 .parent_hws = (const struct clk_hw*[]) { 80 &gcc_gpll0.clkr.hw, 81 }, 82 .num_parents = 1, 83 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 84 }, 85 }; 86 87 static struct clk_alpha_pll gcc_gpll1 = { 88 .offset = 0x1000, 89 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 90 .clkr = { 91 .enable_reg = 0x62018, 92 .enable_mask = BIT(1), 93 .hw.init = &(const struct clk_init_data) { 94 .name = "gcc_gpll1", 95 .parent_data = &(const struct clk_parent_data) { 96 .index = DT_TCXO_IDX, 97 }, 98 .num_parents = 1, 99 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 100 }, 101 }, 102 }; 103 104 static struct clk_alpha_pll_postdiv gcc_gpll1_out_even = { 105 .offset = 0x1000, 106 .post_div_shift = 10, 107 .post_div_table = post_div_table_gcc_gpll0_out_even, 108 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 109 .width = 4, 110 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 111 .clkr.hw.init = &(const struct clk_init_data) { 112 .name = "gcc_gpll1_out_even", 113 .parent_hws = (const struct clk_hw*[]) { 114 &gcc_gpll1.clkr.hw, 115 }, 116 .num_parents = 1, 117 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 118 }, 119 }; 120 121 static struct clk_alpha_pll gcc_gpll2 = { 122 .offset = 0x2000, 123 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 124 .clkr = { 125 .enable_reg = 0x62018, 126 .enable_mask = BIT(2), 127 .hw.init = &(const struct clk_init_data) { 128 .name = "gcc_gpll2", 129 .parent_data = &(const struct clk_parent_data) { 130 .index = DT_TCXO_IDX, 131 }, 132 .num_parents = 1, 133 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 134 }, 135 }, 136 }; 137 138 static struct clk_alpha_pll_postdiv gcc_gpll2_out_even = { 139 .offset = 0x2000, 140 .post_div_shift = 10, 141 .post_div_table = post_div_table_gcc_gpll0_out_even, 142 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 143 .width = 4, 144 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 145 .clkr.hw.init = &(const struct clk_init_data) { 146 .name = "gcc_gpll2_out_even", 147 .parent_hws = (const struct clk_hw*[]) { 148 &gcc_gpll2.clkr.hw, 149 }, 150 .num_parents = 1, 151 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 152 }, 153 }; 154 155 static struct clk_alpha_pll gcc_gpll3 = { 156 .offset = 0x3000, 157 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 158 .clkr = { 159 .enable_reg = 0x62018, 160 .enable_mask = BIT(3), 161 .hw.init = &(const struct clk_init_data) { 162 .name = "gcc_gpll3", 163 .parent_data = &(const struct clk_parent_data) { 164 .index = DT_TCXO_IDX, 165 }, 166 .num_parents = 1, 167 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 168 }, 169 }, 170 }; 171 172 static struct clk_alpha_pll gcc_gpll4 = { 173 .offset = 0x4000, 174 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 175 .clkr = { 176 .enable_reg = 0x62018, 177 .enable_mask = BIT(4), 178 .hw.init = &(const struct clk_init_data) { 179 .name = "gcc_gpll4", 180 .parent_data = &(const struct clk_parent_data) { 181 .index = DT_TCXO_IDX, 182 }, 183 .num_parents = 1, 184 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 185 }, 186 }, 187 }; 188 189 static struct clk_alpha_pll gcc_gpll5 = { 190 .offset = 0x5000, 191 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 192 .clkr = { 193 .enable_reg = 0x62018, 194 .enable_mask = BIT(5), 195 .hw.init = &(const struct clk_init_data) { 196 .name = "gcc_gpll5", 197 .parent_data = &(const struct clk_parent_data) { 198 .index = DT_TCXO_IDX, 199 }, 200 .num_parents = 1, 201 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 202 }, 203 }, 204 }; 205 206 static struct clk_alpha_pll_postdiv gcc_gpll5_out_even = { 207 .offset = 0x5000, 208 .post_div_shift = 10, 209 .post_div_table = post_div_table_gcc_gpll0_out_even, 210 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 211 .width = 4, 212 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 213 .clkr.hw.init = &(const struct clk_init_data) { 214 .name = "gcc_gpll5_out_even", 215 .parent_hws = (const struct clk_hw*[]) { 216 &gcc_gpll5.clkr.hw, 217 }, 218 .num_parents = 1, 219 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 220 }, 221 }; 222 223 static struct clk_alpha_pll gcc_gpll6 = { 224 .offset = 0x6000, 225 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 226 .clkr = { 227 .enable_reg = 0x62018, 228 .enable_mask = BIT(6), 229 .hw.init = &(const struct clk_init_data) { 230 .name = "gcc_gpll6", 231 .parent_data = &(const struct clk_parent_data) { 232 .index = DT_TCXO_IDX, 233 }, 234 .num_parents = 1, 235 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 236 }, 237 }, 238 }; 239 240 static struct clk_alpha_pll gcc_gpll7 = { 241 .offset = 0x7000, 242 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 243 .clkr = { 244 .enable_reg = 0x62018, 245 .enable_mask = BIT(7), 246 .hw.init = &(const struct clk_init_data) { 247 .name = "gcc_gpll7", 248 .parent_data = &(const struct clk_parent_data) { 249 .index = DT_TCXO_IDX, 250 }, 251 .num_parents = 1, 252 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 253 }, 254 }, 255 }; 256 257 static struct clk_alpha_pll gcc_gpll8 = { 258 .offset = 0x8000, 259 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 260 .clkr = { 261 .enable_reg = 0x62018, 262 .enable_mask = BIT(8), 263 .hw.init = &(const struct clk_init_data) { 264 .name = "gcc_gpll8", 265 .parent_data = &(const struct clk_parent_data) { 266 .index = DT_TCXO_IDX, 267 }, 268 .num_parents = 1, 269 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 270 }, 271 }, 272 }; 273 274 static const struct parent_map gcc_parent_map_0[] = { 275 { P_BI_TCXO, 0 }, 276 { P_GCC_GPLL0_OUT_MAIN, 1 }, 277 { P_GCC_GPLL0_OUT_EVEN, 6 }, 278 }; 279 280 static const struct clk_parent_data gcc_parent_data_0[] = { 281 { .index = DT_TCXO_IDX }, 282 { .hw = &gcc_gpll0.clkr.hw }, 283 { .hw = &gcc_gpll0_out_even.clkr.hw }, 284 }; 285 286 static const struct parent_map gcc_parent_map_1[] = { 287 { P_BI_TCXO, 0 }, 288 { P_GCC_GPLL0_OUT_MAIN, 1 }, 289 { P_SLEEP_CLK, 5 }, 290 { P_GCC_GPLL0_OUT_EVEN, 6 }, 291 }; 292 293 static const struct clk_parent_data gcc_parent_data_1[] = { 294 { .index = DT_TCXO_IDX }, 295 { .hw = &gcc_gpll0.clkr.hw }, 296 { .index = DT_SLEEP_CLK_IDX }, 297 { .hw = &gcc_gpll0_out_even.clkr.hw }, 298 }; 299 300 static const struct parent_map gcc_parent_map_2[] = { 301 { P_BI_TCXO, 0 }, 302 { P_GCC_GPLL0_OUT_MAIN, 1 }, 303 { P_GCC_GPLL5_OUT_MAIN, 3 }, 304 { P_GCC_GPLL4_OUT_MAIN, 5 }, 305 }; 306 307 static const struct clk_parent_data gcc_parent_data_2[] = { 308 { .index = DT_TCXO_IDX }, 309 { .hw = &gcc_gpll0.clkr.hw }, 310 { .hw = &gcc_gpll5.clkr.hw }, 311 { .hw = &gcc_gpll4.clkr.hw }, 312 }; 313 314 static const struct parent_map gcc_parent_map_3[] = { 315 { P_BI_TCXO, 0 }, 316 { P_SLEEP_CLK, 5 }, 317 }; 318 319 static const struct clk_parent_data gcc_parent_data_3[] = { 320 { .index = DT_TCXO_IDX }, 321 { .index = DT_SLEEP_CLK_IDX }, 322 }; 323 324 static const struct parent_map gcc_parent_map_4[] = { 325 { P_BI_TCXO, 0 }, 326 { P_GCC_GPLL0_OUT_MAIN, 1 }, 327 { P_GCC_GPLL2_OUT_MAIN, 2 }, 328 { P_GCC_GPLL5_OUT_MAIN, 3 }, 329 { P_GCC_GPLL1_OUT_MAIN, 4 }, 330 { P_GCC_GPLL4_OUT_MAIN, 5 }, 331 { P_GCC_GPLL3_OUT_MAIN, 6 }, 332 }; 333 334 static const struct clk_parent_data gcc_parent_data_4[] = { 335 { .index = DT_TCXO_IDX }, 336 { .hw = &gcc_gpll0.clkr.hw }, 337 { .hw = &gcc_gpll2.clkr.hw }, 338 { .hw = &gcc_gpll5.clkr.hw }, 339 { .hw = &gcc_gpll1.clkr.hw }, 340 { .hw = &gcc_gpll4.clkr.hw }, 341 { .hw = &gcc_gpll3.clkr.hw }, 342 }; 343 344 static const struct parent_map gcc_parent_map_5[] = { 345 { P_BI_TCXO, 0 }, 346 { P_GCC_GPLL0_OUT_MAIN, 1 }, 347 { P_GCC_GPLL2_OUT_MAIN, 2 }, 348 { P_GCC_GPLL6_OUT_MAIN, 3 }, 349 { P_GCC_GPLL1_OUT_MAIN, 4 }, 350 { P_GCC_GPLL4_OUT_MAIN, 5 }, 351 { P_GCC_GPLL3_OUT_MAIN, 6 }, 352 }; 353 354 static const struct clk_parent_data gcc_parent_data_5[] = { 355 { .index = DT_TCXO_IDX }, 356 { .hw = &gcc_gpll0.clkr.hw }, 357 { .hw = &gcc_gpll2.clkr.hw }, 358 { .hw = &gcc_gpll6.clkr.hw }, 359 { .hw = &gcc_gpll1.clkr.hw }, 360 { .hw = &gcc_gpll4.clkr.hw }, 361 { .hw = &gcc_gpll3.clkr.hw }, 362 }; 363 364 static const struct parent_map gcc_parent_map_6[] = { 365 { P_PCIE_0_PHY_AUX_CLK, 0 }, 366 { P_BI_TCXO, 2 }, 367 }; 368 369 static const struct clk_parent_data gcc_parent_data_6[] = { 370 { .index = DT_PCIE_0_PHY_AUX_CLK_IDX }, 371 { .index = DT_TCXO_IDX }, 372 }; 373 374 static const struct parent_map gcc_parent_map_8[] = { 375 { P_BI_TCXO, 0 }, 376 { P_GCC_GPLL0_OUT_MAIN, 1 }, 377 { P_GCC_GPLL8_OUT_MAIN, 2 }, 378 { P_GCC_GPLL5_OUT_MAIN, 3 }, 379 { P_GCC_GPLL4_OUT_MAIN, 5 }, 380 }; 381 382 static const struct clk_parent_data gcc_parent_data_8[] = { 383 { .index = DT_TCXO_IDX }, 384 { .hw = &gcc_gpll0.clkr.hw }, 385 { .hw = &gcc_gpll8.clkr.hw }, 386 { .hw = &gcc_gpll5.clkr.hw }, 387 { .hw = &gcc_gpll4.clkr.hw }, 388 }; 389 390 static const struct parent_map gcc_parent_map_9[] = { 391 { P_BI_TCXO, 0 }, 392 { P_GCC_GPLL0_OUT_MAIN, 1 }, 393 { P_GCC_GPLL2_OUT_MAIN, 2 }, 394 { P_GCC_GPLL5_OUT_MAIN, 3 }, 395 { P_GCC_GPLL7_OUT_MAIN, 4 }, 396 { P_GCC_GPLL4_OUT_MAIN, 5 }, 397 }; 398 399 static const struct clk_parent_data gcc_parent_data_9[] = { 400 { .index = DT_TCXO_IDX }, 401 { .hw = &gcc_gpll0.clkr.hw }, 402 { .hw = &gcc_gpll2.clkr.hw }, 403 { .hw = &gcc_gpll5.clkr.hw }, 404 { .hw = &gcc_gpll7.clkr.hw }, 405 { .hw = &gcc_gpll4.clkr.hw }, 406 }; 407 408 static const struct parent_map gcc_parent_map_10[] = { 409 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 410 { P_BI_TCXO, 2 }, 411 }; 412 413 static const struct clk_parent_data gcc_parent_data_10[] = { 414 { .index = DT_USB3_PHY_WRAPPER_PIPE_CLK_IDX }, 415 { .index = DT_TCXO_IDX }, 416 }; 417 418 static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = { 419 .reg = 0x9d080, 420 .shift = 0, 421 .width = 2, 422 .parent_map = gcc_parent_map_6, 423 .clkr = { 424 .hw.init = &(const struct clk_init_data) { 425 .name = "gcc_pcie_0_phy_aux_clk_src", 426 .parent_data = gcc_parent_data_6, 427 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 428 .ops = &clk_regmap_mux_closest_ops, 429 }, 430 }, 431 }; 432 433 static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { 434 .reg = 0x9d064, 435 .clkr = { 436 .hw.init = &(const struct clk_init_data) { 437 .name = "gcc_pcie_0_pipe_clk_src", 438 .parent_data = &(const struct clk_parent_data){ 439 .index = DT_PCIE_0_PIPE_CLK_IDX, 440 }, 441 .num_parents = 1, 442 .ops = &clk_regmap_phy_mux_ops, 443 }, 444 }, 445 }; 446 447 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 448 .reg = 0x4906c, 449 .shift = 0, 450 .width = 2, 451 .parent_map = gcc_parent_map_10, 452 .clkr = { 453 .hw.init = &(const struct clk_init_data) { 454 .name = "gcc_usb3_prim_phy_pipe_clk_src", 455 .parent_data = gcc_parent_data_10, 456 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 457 .ops = &clk_regmap_mux_closest_ops, 458 }, 459 }, 460 }; 461 462 static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_dma_clk_src[] = { 463 F(466500000, P_GCC_GPLL5_OUT_MAIN, 2, 0, 0), 464 F(500000000, P_GCC_GPLL2_OUT_MAIN, 2, 0, 0), 465 { } 466 }; 467 468 static struct clk_rcg2 gcc_aggre_noc_ecpri_dma_clk_src = { 469 .cmd_rcgr = 0x92020, 470 .mnd_width = 0, 471 .hid_width = 5, 472 .parent_map = gcc_parent_map_4, 473 .freq_tbl = ftbl_gcc_aggre_noc_ecpri_dma_clk_src, 474 .clkr.hw.init = &(const struct clk_init_data) { 475 .name = "gcc_aggre_noc_ecpri_dma_clk_src", 476 .parent_data = gcc_parent_data_4, 477 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 478 .ops = &clk_rcg2_ops, 479 }, 480 }; 481 482 static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_gsi_clk_src[] = { 483 F(250000000, P_GCC_GPLL2_OUT_MAIN, 4, 0, 0), 484 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 485 { } 486 }; 487 488 static struct clk_rcg2 gcc_aggre_noc_ecpri_gsi_clk_src = { 489 .cmd_rcgr = 0x92038, 490 .mnd_width = 0, 491 .hid_width = 5, 492 .parent_map = gcc_parent_map_5, 493 .freq_tbl = ftbl_gcc_aggre_noc_ecpri_gsi_clk_src, 494 .clkr.hw.init = &(const struct clk_init_data) { 495 .name = "gcc_aggre_noc_ecpri_gsi_clk_src", 496 .parent_data = gcc_parent_data_5, 497 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 498 .ops = &clk_rcg2_ops, 499 }, 500 }; 501 502 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 503 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 504 { } 505 }; 506 507 static struct clk_rcg2 gcc_gp1_clk_src = { 508 .cmd_rcgr = 0x74004, 509 .mnd_width = 16, 510 .hid_width = 5, 511 .parent_map = gcc_parent_map_1, 512 .freq_tbl = ftbl_gcc_gp1_clk_src, 513 .clkr.hw.init = &(const struct clk_init_data) { 514 .name = "gcc_gp1_clk_src", 515 .parent_data = gcc_parent_data_1, 516 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 517 .ops = &clk_rcg2_ops, 518 }, 519 }; 520 521 static struct clk_rcg2 gcc_gp2_clk_src = { 522 .cmd_rcgr = 0x75004, 523 .mnd_width = 16, 524 .hid_width = 5, 525 .parent_map = gcc_parent_map_1, 526 .freq_tbl = ftbl_gcc_gp1_clk_src, 527 .clkr.hw.init = &(const struct clk_init_data) { 528 .name = "gcc_gp2_clk_src", 529 .parent_data = gcc_parent_data_1, 530 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 531 .ops = &clk_rcg2_ops, 532 }, 533 }; 534 535 static struct clk_rcg2 gcc_gp3_clk_src = { 536 .cmd_rcgr = 0x76004, 537 .mnd_width = 16, 538 .hid_width = 5, 539 .parent_map = gcc_parent_map_1, 540 .freq_tbl = ftbl_gcc_gp1_clk_src, 541 .clkr.hw.init = &(const struct clk_init_data) { 542 .name = "gcc_gp3_clk_src", 543 .parent_data = gcc_parent_data_1, 544 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 545 .ops = &clk_rcg2_ops, 546 }, 547 }; 548 549 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 550 F(19200000, P_BI_TCXO, 1, 0, 0), 551 { } 552 }; 553 554 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 555 .cmd_rcgr = 0x9d068, 556 .mnd_width = 16, 557 .hid_width = 5, 558 .parent_map = gcc_parent_map_3, 559 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 560 .clkr.hw.init = &(const struct clk_init_data) { 561 .name = "gcc_pcie_0_aux_clk_src", 562 .parent_data = gcc_parent_data_3, 563 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 564 .ops = &clk_rcg2_ops, 565 }, 566 }; 567 568 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 569 F(19200000, P_BI_TCXO, 1, 0, 0), 570 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 571 { } 572 }; 573 574 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 575 .cmd_rcgr = 0x9d04c, 576 .mnd_width = 0, 577 .hid_width = 5, 578 .parent_map = gcc_parent_map_0, 579 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 580 .clkr.hw.init = &(const struct clk_init_data) { 581 .name = "gcc_pcie_0_phy_rchng_clk_src", 582 .parent_data = gcc_parent_data_0, 583 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 584 .ops = &clk_rcg2_ops, 585 }, 586 }; 587 588 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 589 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 590 { } 591 }; 592 593 static struct clk_rcg2 gcc_pdm2_clk_src = { 594 .cmd_rcgr = 0x43010, 595 .mnd_width = 0, 596 .hid_width = 5, 597 .parent_map = gcc_parent_map_0, 598 .freq_tbl = ftbl_gcc_pdm2_clk_src, 599 .clkr.hw.init = &(const struct clk_init_data) { 600 .name = "gcc_pdm2_clk_src", 601 .parent_data = gcc_parent_data_0, 602 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 603 .ops = &clk_rcg2_ops, 604 }, 605 }; 606 607 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 608 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 609 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 610 F(19200000, P_BI_TCXO, 1, 0, 0), 611 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 612 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 613 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 614 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 615 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 616 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 617 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 618 { } 619 }; 620 621 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 622 .name = "gcc_qupv3_wrap0_s0_clk_src", 623 .parent_data = gcc_parent_data_0, 624 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 625 .ops = &clk_rcg2_ops, 626 }; 627 628 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 629 .cmd_rcgr = 0x27154, 630 .mnd_width = 16, 631 .hid_width = 5, 632 .parent_map = gcc_parent_map_0, 633 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 634 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 635 }; 636 637 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 638 .name = "gcc_qupv3_wrap0_s1_clk_src", 639 .parent_data = gcc_parent_data_0, 640 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 641 .ops = &clk_rcg2_ops, 642 }; 643 644 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 645 .cmd_rcgr = 0x27288, 646 .mnd_width = 16, 647 .hid_width = 5, 648 .parent_map = gcc_parent_map_0, 649 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 650 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 651 }; 652 653 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 654 .name = "gcc_qupv3_wrap0_s2_clk_src", 655 .parent_data = gcc_parent_data_0, 656 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 657 .ops = &clk_rcg2_ops, 658 }; 659 660 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 661 .cmd_rcgr = 0x273bc, 662 .mnd_width = 16, 663 .hid_width = 5, 664 .parent_map = gcc_parent_map_0, 665 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 666 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 667 }; 668 669 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 670 .name = "gcc_qupv3_wrap0_s3_clk_src", 671 .parent_data = gcc_parent_data_0, 672 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 673 .ops = &clk_rcg2_ops, 674 }; 675 676 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 677 .cmd_rcgr = 0x274f0, 678 .mnd_width = 16, 679 .hid_width = 5, 680 .parent_map = gcc_parent_map_0, 681 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 682 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 683 }; 684 685 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 686 .name = "gcc_qupv3_wrap0_s4_clk_src", 687 .parent_data = gcc_parent_data_0, 688 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 689 .ops = &clk_rcg2_ops, 690 }; 691 692 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 693 .cmd_rcgr = 0x27624, 694 .mnd_width = 16, 695 .hid_width = 5, 696 .parent_map = gcc_parent_map_0, 697 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 698 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 699 }; 700 701 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] = { 702 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 703 { } 704 }; 705 706 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 707 .name = "gcc_qupv3_wrap0_s5_clk_src", 708 .parent_data = gcc_parent_data_0, 709 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 710 .ops = &clk_rcg2_ops, 711 }; 712 713 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 714 .cmd_rcgr = 0x27758, 715 .mnd_width = 16, 716 .hid_width = 5, 717 .parent_map = gcc_parent_map_0, 718 .freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src, 719 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 720 }; 721 722 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 723 .name = "gcc_qupv3_wrap0_s6_clk_src", 724 .parent_data = gcc_parent_data_0, 725 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 726 .ops = &clk_rcg2_ops, 727 }; 728 729 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 730 .cmd_rcgr = 0x2788c, 731 .mnd_width = 16, 732 .hid_width = 5, 733 .parent_map = gcc_parent_map_0, 734 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 735 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 736 }; 737 738 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 739 .name = "gcc_qupv3_wrap0_s7_clk_src", 740 .parent_data = gcc_parent_data_0, 741 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 742 .ops = &clk_rcg2_ops, 743 }; 744 745 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 746 .cmd_rcgr = 0x279c0, 747 .mnd_width = 16, 748 .hid_width = 5, 749 .parent_map = gcc_parent_map_0, 750 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 751 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 752 }; 753 754 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 755 .name = "gcc_qupv3_wrap1_s0_clk_src", 756 .parent_data = gcc_parent_data_0, 757 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 758 .ops = &clk_rcg2_ops, 759 }; 760 761 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 762 .cmd_rcgr = 0x28154, 763 .mnd_width = 16, 764 .hid_width = 5, 765 .parent_map = gcc_parent_map_0, 766 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 767 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 768 }; 769 770 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 771 .name = "gcc_qupv3_wrap1_s1_clk_src", 772 .parent_data = gcc_parent_data_0, 773 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 774 .ops = &clk_rcg2_ops, 775 }; 776 777 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 778 .cmd_rcgr = 0x28288, 779 .mnd_width = 16, 780 .hid_width = 5, 781 .parent_map = gcc_parent_map_0, 782 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 783 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 784 }; 785 786 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 787 .name = "gcc_qupv3_wrap1_s2_clk_src", 788 .parent_data = gcc_parent_data_0, 789 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 790 .ops = &clk_rcg2_ops, 791 }; 792 793 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 794 .cmd_rcgr = 0x283bc, 795 .mnd_width = 16, 796 .hid_width = 5, 797 .parent_map = gcc_parent_map_0, 798 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 799 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 800 }; 801 802 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 803 .name = "gcc_qupv3_wrap1_s3_clk_src", 804 .parent_data = gcc_parent_data_0, 805 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 806 .ops = &clk_rcg2_ops, 807 }; 808 809 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 810 .cmd_rcgr = 0x284f0, 811 .mnd_width = 16, 812 .hid_width = 5, 813 .parent_map = gcc_parent_map_0, 814 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 815 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 816 }; 817 818 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 819 .name = "gcc_qupv3_wrap1_s4_clk_src", 820 .parent_data = gcc_parent_data_0, 821 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 822 .ops = &clk_rcg2_ops, 823 }; 824 825 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 826 .cmd_rcgr = 0x28624, 827 .mnd_width = 16, 828 .hid_width = 5, 829 .parent_map = gcc_parent_map_0, 830 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 831 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 832 }; 833 834 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 835 .name = "gcc_qupv3_wrap1_s5_clk_src", 836 .parent_data = gcc_parent_data_0, 837 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 838 .ops = &clk_rcg2_ops, 839 }; 840 841 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 842 .cmd_rcgr = 0x28758, 843 .mnd_width = 16, 844 .hid_width = 5, 845 .parent_map = gcc_parent_map_0, 846 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 847 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 848 }; 849 850 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 851 .name = "gcc_qupv3_wrap1_s6_clk_src", 852 .parent_data = gcc_parent_data_0, 853 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 854 .ops = &clk_rcg2_ops, 855 }; 856 857 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 858 .cmd_rcgr = 0x2888c, 859 .mnd_width = 16, 860 .hid_width = 5, 861 .parent_map = gcc_parent_map_0, 862 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 863 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 864 }; 865 866 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 867 .name = "gcc_qupv3_wrap1_s7_clk_src", 868 .parent_data = gcc_parent_data_0, 869 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 870 .ops = &clk_rcg2_ops, 871 }; 872 873 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 874 .cmd_rcgr = 0x289c0, 875 .mnd_width = 16, 876 .hid_width = 5, 877 .parent_map = gcc_parent_map_0, 878 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 879 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 880 }; 881 882 static const struct freq_tbl ftbl_gcc_sdcc5_apps_clk_src[] = { 883 F(144000, P_BI_TCXO, 16, 3, 25), 884 F(400000, P_BI_TCXO, 12, 1, 4), 885 F(19200000, P_BI_TCXO, 1, 0, 0), 886 F(20000000, P_GCC_GPLL0_OUT_MAIN, 10, 1, 3), 887 F(25000000, P_GCC_GPLL0_OUT_MAIN, 12, 1, 2), 888 F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0), 889 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 890 F(192000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0), 891 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 892 F(384000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0), 893 { } 894 }; 895 896 static struct clk_rcg2 gcc_sdcc5_apps_clk_src = { 897 .cmd_rcgr = 0x3b034, 898 .mnd_width = 8, 899 .hid_width = 5, 900 .parent_map = gcc_parent_map_8, 901 .freq_tbl = ftbl_gcc_sdcc5_apps_clk_src, 902 .clkr.hw.init = &(const struct clk_init_data) { 903 .name = "gcc_sdcc5_apps_clk_src", 904 .parent_data = gcc_parent_data_8, 905 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 906 .ops = &clk_rcg2_ops, 907 }, 908 }; 909 910 static const struct freq_tbl ftbl_gcc_sdcc5_ice_core_clk_src[] = { 911 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 912 { } 913 }; 914 915 static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src = { 916 .cmd_rcgr = 0x3b01c, 917 .mnd_width = 0, 918 .hid_width = 5, 919 .parent_map = gcc_parent_map_2, 920 .freq_tbl = ftbl_gcc_sdcc5_ice_core_clk_src, 921 .clkr.hw.init = &(const struct clk_init_data) { 922 .name = "gcc_sdcc5_ice_core_clk_src", 923 .parent_data = gcc_parent_data_2, 924 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 925 .ops = &clk_rcg2_ops, 926 }, 927 }; 928 929 static struct clk_rcg2 gcc_sm_bus_xo_clk_src = { 930 .cmd_rcgr = 0x5b00c, 931 .mnd_width = 0, 932 .hid_width = 5, 933 .parent_map = gcc_parent_map_2, 934 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 935 .clkr.hw.init = &(const struct clk_init_data) { 936 .name = "gcc_sm_bus_xo_clk_src", 937 .parent_data = gcc_parent_data_2, 938 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 939 .ops = &clk_rcg2_ops, 940 }, 941 }; 942 943 static const struct freq_tbl ftbl_gcc_tsc_clk_src[] = { 944 F(500000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0), 945 { } 946 }; 947 948 static struct clk_rcg2 gcc_tsc_clk_src = { 949 .cmd_rcgr = 0x57010, 950 .mnd_width = 0, 951 .hid_width = 5, 952 .parent_map = gcc_parent_map_9, 953 .freq_tbl = ftbl_gcc_tsc_clk_src, 954 .clkr.hw.init = &(const struct clk_init_data) { 955 .name = "gcc_tsc_clk_src", 956 .parent_data = gcc_parent_data_9, 957 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 958 .ops = &clk_rcg2_ops, 959 }, 960 }; 961 962 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 963 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 964 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 965 { } 966 }; 967 968 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 969 .cmd_rcgr = 0x49028, 970 .mnd_width = 8, 971 .hid_width = 5, 972 .parent_map = gcc_parent_map_0, 973 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 974 .clkr.hw.init = &(const struct clk_init_data) { 975 .name = "gcc_usb30_prim_master_clk_src", 976 .parent_data = gcc_parent_data_0, 977 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 978 .ops = &clk_rcg2_ops, 979 }, 980 }; 981 982 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 983 .cmd_rcgr = 0x49044, 984 .mnd_width = 0, 985 .hid_width = 5, 986 .parent_map = gcc_parent_map_0, 987 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 988 .clkr.hw.init = &(const struct clk_init_data) { 989 .name = "gcc_usb30_prim_mock_utmi_clk_src", 990 .parent_data = gcc_parent_data_0, 991 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 992 .ops = &clk_rcg2_ops, 993 }, 994 }; 995 996 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 997 .cmd_rcgr = 0x49070, 998 .mnd_width = 0, 999 .hid_width = 5, 1000 .parent_map = gcc_parent_map_3, 1001 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1002 .clkr.hw.init = &(const struct clk_init_data) { 1003 .name = "gcc_usb3_prim_phy_aux_clk_src", 1004 .parent_data = gcc_parent_data_3, 1005 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1006 .ops = &clk_rcg2_ops, 1007 }, 1008 }; 1009 1010 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1011 .reg = 0x4905c, 1012 .shift = 0, 1013 .width = 4, 1014 .clkr.hw.init = &(const struct clk_init_data) { 1015 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1016 .parent_hws = (const struct clk_hw*[]) { 1017 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1018 }, 1019 .num_parents = 1, 1020 .flags = CLK_SET_RATE_PARENT, 1021 .ops = &clk_regmap_div_ro_ops, 1022 }, 1023 }; 1024 1025 static struct clk_branch gcc_aggre_noc_ecpri_dma_clk = { 1026 .halt_reg = 0x92008, 1027 .halt_check = BRANCH_HALT_VOTED, 1028 .hwcg_reg = 0x92008, 1029 .hwcg_bit = 1, 1030 .clkr = { 1031 .enable_reg = 0x92008, 1032 .enable_mask = BIT(0), 1033 .hw.init = &(const struct clk_init_data) { 1034 .name = "gcc_aggre_noc_ecpri_dma_clk", 1035 .parent_hws = (const struct clk_hw*[]) { 1036 &gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw, 1037 }, 1038 .num_parents = 1, 1039 .flags = CLK_SET_RATE_PARENT, 1040 .ops = &clk_branch2_ops, 1041 }, 1042 }, 1043 }; 1044 1045 static struct clk_branch gcc_aggre_noc_ecpri_gsi_clk = { 1046 .halt_reg = 0x9201c, 1047 .halt_check = BRANCH_HALT_VOTED, 1048 .hwcg_reg = 0x9201c, 1049 .hwcg_bit = 1, 1050 .clkr = { 1051 .enable_reg = 0x9201c, 1052 .enable_mask = BIT(0), 1053 .hw.init = &(const struct clk_init_data) { 1054 .name = "gcc_aggre_noc_ecpri_gsi_clk", 1055 .parent_hws = (const struct clk_hw*[]) { 1056 &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, 1057 }, 1058 .num_parents = 1, 1059 .flags = CLK_SET_RATE_PARENT, 1060 .ops = &clk_branch2_ops, 1061 }, 1062 }, 1063 }; 1064 1065 static struct clk_branch gcc_boot_rom_ahb_clk = { 1066 .halt_reg = 0x48004, 1067 .halt_check = BRANCH_HALT_VOTED, 1068 .hwcg_reg = 0x48004, 1069 .hwcg_bit = 1, 1070 .clkr = { 1071 .enable_reg = 0x62000, 1072 .enable_mask = BIT(10), 1073 .hw.init = &(const struct clk_init_data) { 1074 .name = "gcc_boot_rom_ahb_clk", 1075 .ops = &clk_branch2_ops, 1076 }, 1077 }, 1078 }; 1079 1080 static struct clk_branch gcc_cfg_noc_ecpri_cc_ahb_clk = { 1081 .halt_reg = 0x3e004, 1082 .halt_check = BRANCH_HALT_VOTED, 1083 .hwcg_reg = 0x3e004, 1084 .hwcg_bit = 1, 1085 .clkr = { 1086 .enable_reg = 0x3e004, 1087 .enable_mask = BIT(0), 1088 .hw.init = &(const struct clk_init_data) { 1089 .name = "gcc_cfg_noc_ecpri_cc_ahb_clk", 1090 .ops = &clk_branch2_ops, 1091 }, 1092 }, 1093 }; 1094 1095 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1096 .halt_reg = 0x8401c, 1097 .halt_check = BRANCH_HALT_VOTED, 1098 .hwcg_reg = 0x8401c, 1099 .hwcg_bit = 1, 1100 .clkr = { 1101 .enable_reg = 0x8401c, 1102 .enable_mask = BIT(0), 1103 .hw.init = &(const struct clk_init_data) { 1104 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1105 .parent_hws = (const struct clk_hw*[]) { 1106 &gcc_usb30_prim_master_clk_src.clkr.hw, 1107 }, 1108 .num_parents = 1, 1109 .flags = CLK_SET_RATE_PARENT, 1110 .ops = &clk_branch2_ops, 1111 }, 1112 }, 1113 }; 1114 1115 static struct clk_branch gcc_ddrss_ecpri_dma_clk = { 1116 .halt_reg = 0x54030, 1117 .halt_check = BRANCH_HALT_VOTED, 1118 .hwcg_reg = 0x54030, 1119 .hwcg_bit = 1, 1120 .clkr = { 1121 .enable_reg = 0x54030, 1122 .enable_mask = BIT(0), 1123 .hw.init = &(const struct clk_init_data) { 1124 .name = "gcc_ddrss_ecpri_dma_clk", 1125 .parent_hws = (const struct clk_hw*[]) { 1126 &gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw, 1127 }, 1128 .num_parents = 1, 1129 .flags = CLK_SET_RATE_PARENT, 1130 .ops = &clk_branch2_aon_ops, 1131 }, 1132 }, 1133 }; 1134 1135 static struct clk_branch gcc_ddrss_ecpri_gsi_clk = { 1136 .halt_reg = 0x54298, 1137 .halt_check = BRANCH_HALT_VOTED, 1138 .hwcg_reg = 0x54298, 1139 .hwcg_bit = 1, 1140 .clkr = { 1141 .enable_reg = 0x54298, 1142 .enable_mask = BIT(0), 1143 .hw.init = &(const struct clk_init_data) { 1144 .name = "gcc_ddrss_ecpri_gsi_clk", 1145 .parent_hws = (const struct clk_hw*[]) { 1146 &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, 1147 }, 1148 .num_parents = 1, 1149 .flags = CLK_SET_RATE_PARENT, 1150 .ops = &clk_branch2_aon_ops, 1151 }, 1152 }, 1153 }; 1154 1155 static struct clk_branch gcc_ecpri_ahb_clk = { 1156 .halt_reg = 0x3a008, 1157 .halt_check = BRANCH_HALT_VOTED, 1158 .hwcg_reg = 0x3a008, 1159 .hwcg_bit = 1, 1160 .clkr = { 1161 .enable_reg = 0x3a008, 1162 .enable_mask = BIT(0), 1163 .hw.init = &(const struct clk_init_data) { 1164 .name = "gcc_ecpri_ahb_clk", 1165 .ops = &clk_branch2_ops, 1166 }, 1167 }, 1168 }; 1169 1170 static struct clk_branch gcc_ecpri_cc_gpll0_clk_src = { 1171 .halt_check = BRANCH_HALT_DELAY, 1172 .clkr = { 1173 .enable_reg = 0x62010, 1174 .enable_mask = BIT(0), 1175 .hw.init = &(const struct clk_init_data) { 1176 .name = "gcc_ecpri_cc_gpll0_clk_src", 1177 .parent_hws = (const struct clk_hw*[]) { 1178 &gcc_gpll0.clkr.hw, 1179 }, 1180 .num_parents = 1, 1181 .flags = CLK_SET_RATE_PARENT, 1182 .ops = &clk_branch2_ops, 1183 }, 1184 }, 1185 }; 1186 1187 static struct clk_branch gcc_ecpri_cc_gpll1_even_clk_src = { 1188 .halt_check = BRANCH_HALT_DELAY, 1189 .clkr = { 1190 .enable_reg = 0x62010, 1191 .enable_mask = BIT(1), 1192 .hw.init = &(const struct clk_init_data) { 1193 .name = "gcc_ecpri_cc_gpll1_even_clk_src", 1194 .parent_hws = (const struct clk_hw*[]) { 1195 &gcc_gpll1_out_even.clkr.hw, 1196 }, 1197 .num_parents = 1, 1198 .flags = CLK_SET_RATE_PARENT, 1199 .ops = &clk_branch2_ops, 1200 }, 1201 }, 1202 }; 1203 1204 static struct clk_branch gcc_ecpri_cc_gpll2_even_clk_src = { 1205 .halt_check = BRANCH_HALT_DELAY, 1206 .clkr = { 1207 .enable_reg = 0x62010, 1208 .enable_mask = BIT(2), 1209 .hw.init = &(const struct clk_init_data) { 1210 .name = "gcc_ecpri_cc_gpll2_even_clk_src", 1211 .parent_hws = (const struct clk_hw*[]) { 1212 &gcc_gpll2_out_even.clkr.hw, 1213 }, 1214 .num_parents = 1, 1215 .flags = CLK_SET_RATE_PARENT, 1216 .ops = &clk_branch2_ops, 1217 }, 1218 }, 1219 }; 1220 1221 static struct clk_branch gcc_ecpri_cc_gpll3_clk_src = { 1222 .halt_check = BRANCH_HALT_DELAY, 1223 .clkr = { 1224 .enable_reg = 0x62010, 1225 .enable_mask = BIT(3), 1226 .hw.init = &(const struct clk_init_data) { 1227 .name = "gcc_ecpri_cc_gpll3_clk_src", 1228 .parent_hws = (const struct clk_hw*[]) { 1229 &gcc_gpll3.clkr.hw, 1230 }, 1231 .num_parents = 1, 1232 .flags = CLK_SET_RATE_PARENT, 1233 .ops = &clk_branch2_ops, 1234 }, 1235 }, 1236 }; 1237 1238 static struct clk_branch gcc_ecpri_cc_gpll4_clk_src = { 1239 .halt_check = BRANCH_HALT_DELAY, 1240 .clkr = { 1241 .enable_reg = 0x62010, 1242 .enable_mask = BIT(4), 1243 .hw.init = &(const struct clk_init_data) { 1244 .name = "gcc_ecpri_cc_gpll4_clk_src", 1245 .parent_hws = (const struct clk_hw*[]) { 1246 &gcc_gpll4.clkr.hw, 1247 }, 1248 .num_parents = 1, 1249 .flags = CLK_SET_RATE_PARENT, 1250 .ops = &clk_branch2_ops, 1251 }, 1252 }, 1253 }; 1254 1255 static struct clk_branch gcc_ecpri_cc_gpll5_even_clk_src = { 1256 .halt_check = BRANCH_HALT_DELAY, 1257 .clkr = { 1258 .enable_reg = 0x62010, 1259 .enable_mask = BIT(5), 1260 .hw.init = &(const struct clk_init_data) { 1261 .name = "gcc_ecpri_cc_gpll5_even_clk_src", 1262 .parent_hws = (const struct clk_hw*[]) { 1263 &gcc_gpll5_out_even.clkr.hw, 1264 }, 1265 .num_parents = 1, 1266 .flags = CLK_SET_RATE_PARENT, 1267 .ops = &clk_branch2_ops, 1268 }, 1269 }, 1270 }; 1271 1272 static struct clk_branch gcc_ecpri_xo_clk = { 1273 .halt_reg = 0x3a004, 1274 .halt_check = BRANCH_HALT, 1275 .clkr = { 1276 .enable_reg = 0x3a004, 1277 .enable_mask = BIT(0), 1278 .hw.init = &(const struct clk_init_data) { 1279 .name = "gcc_ecpri_xo_clk", 1280 .ops = &clk_branch2_ops, 1281 }, 1282 }, 1283 }; 1284 1285 static struct clk_branch gcc_eth_100g_c2c_hm_apb_clk = { 1286 .halt_reg = 0x39010, 1287 .halt_check = BRANCH_HALT, 1288 .clkr = { 1289 .enable_reg = 0x39010, 1290 .enable_mask = BIT(0), 1291 .hw.init = &(const struct clk_init_data) { 1292 .name = "gcc_eth_100g_c2c_hm_apb_clk", 1293 .ops = &clk_branch2_ops, 1294 }, 1295 }, 1296 }; 1297 1298 static struct clk_branch gcc_eth_100g_fh_hm_apb_0_clk = { 1299 .halt_reg = 0x39004, 1300 .halt_check = BRANCH_HALT, 1301 .clkr = { 1302 .enable_reg = 0x39004, 1303 .enable_mask = BIT(0), 1304 .hw.init = &(const struct clk_init_data) { 1305 .name = "gcc_eth_100g_fh_hm_apb_0_clk", 1306 .ops = &clk_branch2_ops, 1307 }, 1308 }, 1309 }; 1310 1311 static struct clk_branch gcc_eth_100g_fh_hm_apb_1_clk = { 1312 .halt_reg = 0x39008, 1313 .halt_check = BRANCH_HALT, 1314 .clkr = { 1315 .enable_reg = 0x39008, 1316 .enable_mask = BIT(0), 1317 .hw.init = &(const struct clk_init_data) { 1318 .name = "gcc_eth_100g_fh_hm_apb_1_clk", 1319 .ops = &clk_branch2_ops, 1320 }, 1321 }, 1322 }; 1323 1324 static struct clk_branch gcc_eth_100g_fh_hm_apb_2_clk = { 1325 .halt_reg = 0x3900c, 1326 .halt_check = BRANCH_HALT, 1327 .clkr = { 1328 .enable_reg = 0x3900c, 1329 .enable_mask = BIT(0), 1330 .hw.init = &(const struct clk_init_data) { 1331 .name = "gcc_eth_100g_fh_hm_apb_2_clk", 1332 .ops = &clk_branch2_ops, 1333 }, 1334 }, 1335 }; 1336 1337 static struct clk_branch gcc_eth_dbg_c2c_hm_apb_clk = { 1338 .halt_reg = 0x39014, 1339 .halt_check = BRANCH_HALT, 1340 .clkr = { 1341 .enable_reg = 0x39014, 1342 .enable_mask = BIT(0), 1343 .hw.init = &(const struct clk_init_data) { 1344 .name = "gcc_eth_dbg_c2c_hm_apb_clk", 1345 .ops = &clk_branch2_ops, 1346 }, 1347 }, 1348 }; 1349 1350 static struct clk_branch gcc_eth_dbg_snoc_axi_clk = { 1351 .halt_reg = 0x3901c, 1352 .halt_check = BRANCH_HALT_VOTED, 1353 .hwcg_reg = 0x3901c, 1354 .hwcg_bit = 1, 1355 .clkr = { 1356 .enable_reg = 0x3901c, 1357 .enable_mask = BIT(0), 1358 .hw.init = &(const struct clk_init_data) { 1359 .name = "gcc_eth_dbg_snoc_axi_clk", 1360 .ops = &clk_branch2_ops, 1361 }, 1362 }, 1363 }; 1364 1365 static struct clk_branch gcc_gemnoc_pcie_qx_clk = { 1366 .halt_reg = 0x5402c, 1367 .halt_check = BRANCH_HALT_VOTED, 1368 .hwcg_reg = 0x5402c, 1369 .hwcg_bit = 1, 1370 .clkr = { 1371 .enable_reg = 0x62008, 1372 .enable_mask = BIT(0), 1373 .hw.init = &(const struct clk_init_data) { 1374 .name = "gcc_gemnoc_pcie_qx_clk", 1375 .ops = &clk_branch2_aon_ops, 1376 }, 1377 }, 1378 }; 1379 1380 static struct clk_branch gcc_gp1_clk = { 1381 .halt_reg = 0x74000, 1382 .halt_check = BRANCH_HALT, 1383 .clkr = { 1384 .enable_reg = 0x74000, 1385 .enable_mask = BIT(0), 1386 .hw.init = &(const struct clk_init_data) { 1387 .name = "gcc_gp1_clk", 1388 .parent_hws = (const struct clk_hw*[]) { 1389 &gcc_gp1_clk_src.clkr.hw, 1390 }, 1391 .num_parents = 1, 1392 .flags = CLK_SET_RATE_PARENT, 1393 .ops = &clk_branch2_ops, 1394 }, 1395 }, 1396 }; 1397 1398 static struct clk_branch gcc_gp2_clk = { 1399 .halt_reg = 0x75000, 1400 .halt_check = BRANCH_HALT, 1401 .clkr = { 1402 .enable_reg = 0x75000, 1403 .enable_mask = BIT(0), 1404 .hw.init = &(const struct clk_init_data) { 1405 .name = "gcc_gp2_clk", 1406 .parent_hws = (const struct clk_hw*[]) { 1407 &gcc_gp2_clk_src.clkr.hw, 1408 }, 1409 .num_parents = 1, 1410 .flags = CLK_SET_RATE_PARENT, 1411 .ops = &clk_branch2_ops, 1412 }, 1413 }, 1414 }; 1415 1416 static struct clk_branch gcc_gp3_clk = { 1417 .halt_reg = 0x76000, 1418 .halt_check = BRANCH_HALT, 1419 .clkr = { 1420 .enable_reg = 0x76000, 1421 .enable_mask = BIT(0), 1422 .hw.init = &(const struct clk_init_data) { 1423 .name = "gcc_gp3_clk", 1424 .parent_hws = (const struct clk_hw*[]) { 1425 &gcc_gp3_clk_src.clkr.hw, 1426 }, 1427 .num_parents = 1, 1428 .flags = CLK_SET_RATE_PARENT, 1429 .ops = &clk_branch2_ops, 1430 }, 1431 }, 1432 }; 1433 1434 static struct clk_branch gcc_pcie_0_aux_clk = { 1435 .halt_reg = 0x9d030, 1436 .halt_check = BRANCH_HALT_VOTED, 1437 .hwcg_reg = 0x9d030, 1438 .hwcg_bit = 1, 1439 .clkr = { 1440 .enable_reg = 0x62000, 1441 .enable_mask = BIT(29), 1442 .hw.init = &(const struct clk_init_data) { 1443 .name = "gcc_pcie_0_aux_clk", 1444 .parent_hws = (const struct clk_hw*[]) { 1445 &gcc_pcie_0_aux_clk_src.clkr.hw, 1446 }, 1447 .num_parents = 1, 1448 .flags = CLK_SET_RATE_PARENT, 1449 .ops = &clk_branch2_ops, 1450 }, 1451 }, 1452 }; 1453 1454 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1455 .halt_reg = 0x9d02c, 1456 .halt_check = BRANCH_HALT_VOTED, 1457 .hwcg_reg = 0x9d02c, 1458 .hwcg_bit = 1, 1459 .clkr = { 1460 .enable_reg = 0x62000, 1461 .enable_mask = BIT(28), 1462 .hw.init = &(const struct clk_init_data) { 1463 .name = "gcc_pcie_0_cfg_ahb_clk", 1464 .ops = &clk_branch2_ops, 1465 }, 1466 }, 1467 }; 1468 1469 static struct clk_branch gcc_pcie_0_clkref_en = { 1470 .halt_reg = 0x9c004, 1471 .halt_check = BRANCH_HALT, 1472 .clkr = { 1473 .enable_reg = 0x9c004, 1474 .enable_mask = BIT(0), 1475 .hw.init = &(const struct clk_init_data) { 1476 .name = "gcc_pcie_0_clkref_en", 1477 .ops = &clk_branch2_ops, 1478 }, 1479 }, 1480 }; 1481 1482 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1483 .halt_reg = 0x9d024, 1484 .halt_check = BRANCH_HALT_SKIP, 1485 .hwcg_reg = 0x9d024, 1486 .hwcg_bit = 1, 1487 .clkr = { 1488 .enable_reg = 0x62000, 1489 .enable_mask = BIT(27), 1490 .hw.init = &(const struct clk_init_data) { 1491 .name = "gcc_pcie_0_mstr_axi_clk", 1492 .ops = &clk_branch2_ops, 1493 }, 1494 }, 1495 }; 1496 1497 static struct clk_branch gcc_pcie_0_phy_aux_clk = { 1498 .halt_reg = 0x9d038, 1499 .halt_check = BRANCH_HALT_VOTED, 1500 .hwcg_reg = 0x9d038, 1501 .hwcg_bit = 1, 1502 .clkr = { 1503 .enable_reg = 0x62000, 1504 .enable_mask = BIT(24), 1505 .hw.init = &(const struct clk_init_data) { 1506 .name = "gcc_pcie_0_phy_aux_clk", 1507 .parent_hws = (const struct clk_hw*[]) { 1508 &gcc_pcie_0_phy_aux_clk_src.clkr.hw, 1509 }, 1510 .num_parents = 1, 1511 .flags = CLK_SET_RATE_PARENT, 1512 .ops = &clk_branch2_ops, 1513 }, 1514 }, 1515 }; 1516 1517 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 1518 .halt_reg = 0x9d048, 1519 .halt_check = BRANCH_HALT_VOTED, 1520 .hwcg_reg = 0x9d048, 1521 .hwcg_bit = 1, 1522 .clkr = { 1523 .enable_reg = 0x62000, 1524 .enable_mask = BIT(23), 1525 .hw.init = &(const struct clk_init_data) { 1526 .name = "gcc_pcie_0_phy_rchng_clk", 1527 .parent_hws = (const struct clk_hw*[]) { 1528 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1529 }, 1530 .num_parents = 1, 1531 .flags = CLK_SET_RATE_PARENT, 1532 .ops = &clk_branch2_ops, 1533 }, 1534 }, 1535 }; 1536 1537 static struct clk_branch gcc_pcie_0_pipe_clk = { 1538 .halt_reg = 0x9d040, 1539 .halt_check = BRANCH_HALT_VOTED, 1540 .hwcg_reg = 0x9d040, 1541 .hwcg_bit = 1, 1542 .clkr = { 1543 .enable_reg = 0x62000, 1544 .enable_mask = BIT(30), 1545 .hw.init = &(const struct clk_init_data) { 1546 .name = "gcc_pcie_0_pipe_clk", 1547 .parent_hws = (const struct clk_hw*[]) { 1548 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1549 }, 1550 .num_parents = 1, 1551 .flags = CLK_SET_RATE_PARENT, 1552 .ops = &clk_branch2_ops, 1553 }, 1554 }, 1555 }; 1556 1557 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1558 .halt_reg = 0x9d01c, 1559 .halt_check = BRANCH_HALT_VOTED, 1560 .hwcg_reg = 0x9d01c, 1561 .hwcg_bit = 1, 1562 .clkr = { 1563 .enable_reg = 0x62000, 1564 .enable_mask = BIT(26), 1565 .hw.init = &(const struct clk_init_data) { 1566 .name = "gcc_pcie_0_slv_axi_clk", 1567 .ops = &clk_branch2_ops, 1568 }, 1569 }, 1570 }; 1571 1572 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1573 .halt_reg = 0x9d018, 1574 .halt_check = BRANCH_HALT_VOTED, 1575 .hwcg_reg = 0x9d018, 1576 .hwcg_bit = 1, 1577 .clkr = { 1578 .enable_reg = 0x62000, 1579 .enable_mask = BIT(25), 1580 .hw.init = &(const struct clk_init_data) { 1581 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1582 .ops = &clk_branch2_ops, 1583 }, 1584 }, 1585 }; 1586 1587 static struct clk_branch gcc_pdm2_clk = { 1588 .halt_reg = 0x4300c, 1589 .halt_check = BRANCH_HALT, 1590 .clkr = { 1591 .enable_reg = 0x4300c, 1592 .enable_mask = BIT(0), 1593 .hw.init = &(const struct clk_init_data) { 1594 .name = "gcc_pdm2_clk", 1595 .parent_hws = (const struct clk_hw*[]) { 1596 &gcc_pdm2_clk_src.clkr.hw, 1597 }, 1598 .num_parents = 1, 1599 .flags = CLK_SET_RATE_PARENT, 1600 .ops = &clk_branch2_ops, 1601 }, 1602 }, 1603 }; 1604 1605 static struct clk_branch gcc_pdm_ahb_clk = { 1606 .halt_reg = 0x43004, 1607 .halt_check = BRANCH_HALT_VOTED, 1608 .hwcg_reg = 0x43004, 1609 .hwcg_bit = 1, 1610 .clkr = { 1611 .enable_reg = 0x43004, 1612 .enable_mask = BIT(0), 1613 .hw.init = &(const struct clk_init_data) { 1614 .name = "gcc_pdm_ahb_clk", 1615 .ops = &clk_branch2_ops, 1616 }, 1617 }, 1618 }; 1619 1620 static struct clk_branch gcc_pdm_xo4_clk = { 1621 .halt_reg = 0x43008, 1622 .halt_check = BRANCH_HALT, 1623 .clkr = { 1624 .enable_reg = 0x43008, 1625 .enable_mask = BIT(0), 1626 .hw.init = &(const struct clk_init_data) { 1627 .name = "gcc_pdm_xo4_clk", 1628 .ops = &clk_branch2_ops, 1629 }, 1630 }, 1631 }; 1632 1633 static struct clk_branch gcc_qmip_anoc_pcie_clk = { 1634 .halt_reg = 0x84044, 1635 .halt_check = BRANCH_HALT_VOTED, 1636 .hwcg_reg = 0x84044, 1637 .hwcg_bit = 1, 1638 .clkr = { 1639 .enable_reg = 0x84044, 1640 .enable_mask = BIT(0), 1641 .hw.init = &(const struct clk_init_data) { 1642 .name = "gcc_qmip_anoc_pcie_clk", 1643 .ops = &clk_branch2_ops, 1644 }, 1645 }, 1646 }; 1647 1648 static struct clk_branch gcc_qmip_ecpri_dma0_clk = { 1649 .halt_reg = 0x84038, 1650 .halt_check = BRANCH_HALT_VOTED, 1651 .hwcg_reg = 0x84038, 1652 .hwcg_bit = 1, 1653 .clkr = { 1654 .enable_reg = 0x84038, 1655 .enable_mask = BIT(0), 1656 .hw.init = &(const struct clk_init_data) { 1657 .name = "gcc_qmip_ecpri_dma0_clk", 1658 .ops = &clk_branch2_ops, 1659 }, 1660 }, 1661 }; 1662 1663 static struct clk_branch gcc_qmip_ecpri_dma1_clk = { 1664 .halt_reg = 0x8403c, 1665 .halt_check = BRANCH_HALT_VOTED, 1666 .hwcg_reg = 0x8403c, 1667 .hwcg_bit = 1, 1668 .clkr = { 1669 .enable_reg = 0x8403c, 1670 .enable_mask = BIT(0), 1671 .hw.init = &(const struct clk_init_data) { 1672 .name = "gcc_qmip_ecpri_dma1_clk", 1673 .ops = &clk_branch2_ops, 1674 }, 1675 }, 1676 }; 1677 1678 static struct clk_branch gcc_qmip_ecpri_gsi_clk = { 1679 .halt_reg = 0x84040, 1680 .halt_check = BRANCH_HALT_VOTED, 1681 .hwcg_reg = 0x84040, 1682 .hwcg_bit = 1, 1683 .clkr = { 1684 .enable_reg = 0x84040, 1685 .enable_mask = BIT(0), 1686 .hw.init = &(const struct clk_init_data) { 1687 .name = "gcc_qmip_ecpri_gsi_clk", 1688 .ops = &clk_branch2_ops, 1689 }, 1690 }, 1691 }; 1692 1693 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 1694 .halt_reg = 0x27018, 1695 .halt_check = BRANCH_HALT_VOTED, 1696 .clkr = { 1697 .enable_reg = 0x62008, 1698 .enable_mask = BIT(9), 1699 .hw.init = &(const struct clk_init_data) { 1700 .name = "gcc_qupv3_wrap0_core_2x_clk", 1701 .ops = &clk_branch2_ops, 1702 }, 1703 }, 1704 }; 1705 1706 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 1707 .halt_reg = 0x2700c, 1708 .halt_check = BRANCH_HALT_VOTED, 1709 .clkr = { 1710 .enable_reg = 0x62008, 1711 .enable_mask = BIT(8), 1712 .hw.init = &(const struct clk_init_data) { 1713 .name = "gcc_qupv3_wrap0_core_clk", 1714 .ops = &clk_branch2_ops, 1715 }, 1716 }, 1717 }; 1718 1719 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 1720 .halt_reg = 0x2714c, 1721 .halt_check = BRANCH_HALT_VOTED, 1722 .clkr = { 1723 .enable_reg = 0x62008, 1724 .enable_mask = BIT(10), 1725 .hw.init = &(const struct clk_init_data) { 1726 .name = "gcc_qupv3_wrap0_s0_clk", 1727 .parent_hws = (const struct clk_hw*[]) { 1728 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 1729 }, 1730 .num_parents = 1, 1731 .flags = CLK_SET_RATE_PARENT, 1732 .ops = &clk_branch2_ops, 1733 }, 1734 }, 1735 }; 1736 1737 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 1738 .halt_reg = 0x27280, 1739 .halt_check = BRANCH_HALT_VOTED, 1740 .clkr = { 1741 .enable_reg = 0x62008, 1742 .enable_mask = BIT(11), 1743 .hw.init = &(const struct clk_init_data) { 1744 .name = "gcc_qupv3_wrap0_s1_clk", 1745 .parent_hws = (const struct clk_hw*[]) { 1746 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 1747 }, 1748 .num_parents = 1, 1749 .flags = CLK_SET_RATE_PARENT, 1750 .ops = &clk_branch2_ops, 1751 }, 1752 }, 1753 }; 1754 1755 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 1756 .halt_reg = 0x273b4, 1757 .halt_check = BRANCH_HALT_VOTED, 1758 .clkr = { 1759 .enable_reg = 0x62008, 1760 .enable_mask = BIT(12), 1761 .hw.init = &(const struct clk_init_data) { 1762 .name = "gcc_qupv3_wrap0_s2_clk", 1763 .parent_hws = (const struct clk_hw*[]) { 1764 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 1765 }, 1766 .num_parents = 1, 1767 .flags = CLK_SET_RATE_PARENT, 1768 .ops = &clk_branch2_ops, 1769 }, 1770 }, 1771 }; 1772 1773 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 1774 .halt_reg = 0x274e8, 1775 .halt_check = BRANCH_HALT_VOTED, 1776 .clkr = { 1777 .enable_reg = 0x62008, 1778 .enable_mask = BIT(13), 1779 .hw.init = &(const struct clk_init_data) { 1780 .name = "gcc_qupv3_wrap0_s3_clk", 1781 .parent_hws = (const struct clk_hw*[]) { 1782 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 1783 }, 1784 .num_parents = 1, 1785 .flags = CLK_SET_RATE_PARENT, 1786 .ops = &clk_branch2_ops, 1787 }, 1788 }, 1789 }; 1790 1791 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 1792 .halt_reg = 0x2761c, 1793 .halt_check = BRANCH_HALT_VOTED, 1794 .clkr = { 1795 .enable_reg = 0x62008, 1796 .enable_mask = BIT(14), 1797 .hw.init = &(const struct clk_init_data) { 1798 .name = "gcc_qupv3_wrap0_s4_clk", 1799 .parent_hws = (const struct clk_hw*[]) { 1800 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 1801 }, 1802 .num_parents = 1, 1803 .flags = CLK_SET_RATE_PARENT, 1804 .ops = &clk_branch2_ops, 1805 }, 1806 }, 1807 }; 1808 1809 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 1810 .halt_reg = 0x27750, 1811 .halt_check = BRANCH_HALT_VOTED, 1812 .clkr = { 1813 .enable_reg = 0x62008, 1814 .enable_mask = BIT(15), 1815 .hw.init = &(const struct clk_init_data) { 1816 .name = "gcc_qupv3_wrap0_s5_clk", 1817 .parent_hws = (const struct clk_hw*[]) { 1818 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 1819 }, 1820 .num_parents = 1, 1821 .flags = CLK_SET_RATE_PARENT, 1822 .ops = &clk_branch2_ops, 1823 }, 1824 }, 1825 }; 1826 1827 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 1828 .halt_reg = 0x27884, 1829 .halt_check = BRANCH_HALT_VOTED, 1830 .clkr = { 1831 .enable_reg = 0x62008, 1832 .enable_mask = BIT(16), 1833 .hw.init = &(const struct clk_init_data) { 1834 .name = "gcc_qupv3_wrap0_s6_clk", 1835 .parent_hws = (const struct clk_hw*[]) { 1836 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 1837 }, 1838 .num_parents = 1, 1839 .flags = CLK_SET_RATE_PARENT, 1840 .ops = &clk_branch2_ops, 1841 }, 1842 }, 1843 }; 1844 1845 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 1846 .halt_reg = 0x279b8, 1847 .halt_check = BRANCH_HALT_VOTED, 1848 .clkr = { 1849 .enable_reg = 0x62008, 1850 .enable_mask = BIT(17), 1851 .hw.init = &(const struct clk_init_data) { 1852 .name = "gcc_qupv3_wrap0_s7_clk", 1853 .parent_hws = (const struct clk_hw*[]) { 1854 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 1855 }, 1856 .num_parents = 1, 1857 .flags = CLK_SET_RATE_PARENT, 1858 .ops = &clk_branch2_ops, 1859 }, 1860 }, 1861 }; 1862 1863 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 1864 .halt_reg = 0x28018, 1865 .halt_check = BRANCH_HALT_VOTED, 1866 .clkr = { 1867 .enable_reg = 0x62008, 1868 .enable_mask = BIT(18), 1869 .hw.init = &(const struct clk_init_data) { 1870 .name = "gcc_qupv3_wrap1_core_2x_clk", 1871 .ops = &clk_branch2_ops, 1872 }, 1873 }, 1874 }; 1875 1876 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 1877 .halt_reg = 0x2800c, 1878 .halt_check = BRANCH_HALT_VOTED, 1879 .clkr = { 1880 .enable_reg = 0x62008, 1881 .enable_mask = BIT(19), 1882 .hw.init = &(const struct clk_init_data) { 1883 .name = "gcc_qupv3_wrap1_core_clk", 1884 .ops = &clk_branch2_ops, 1885 }, 1886 }, 1887 }; 1888 1889 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 1890 .halt_reg = 0x2814c, 1891 .halt_check = BRANCH_HALT_VOTED, 1892 .clkr = { 1893 .enable_reg = 0x62008, 1894 .enable_mask = BIT(22), 1895 .hw.init = &(const struct clk_init_data) { 1896 .name = "gcc_qupv3_wrap1_s0_clk", 1897 .parent_hws = (const struct clk_hw*[]) { 1898 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 1899 }, 1900 .num_parents = 1, 1901 .flags = CLK_SET_RATE_PARENT, 1902 .ops = &clk_branch2_ops, 1903 }, 1904 }, 1905 }; 1906 1907 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 1908 .halt_reg = 0x28280, 1909 .halt_check = BRANCH_HALT_VOTED, 1910 .clkr = { 1911 .enable_reg = 0x62008, 1912 .enable_mask = BIT(23), 1913 .hw.init = &(const struct clk_init_data) { 1914 .name = "gcc_qupv3_wrap1_s1_clk", 1915 .parent_hws = (const struct clk_hw*[]) { 1916 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 1917 }, 1918 .num_parents = 1, 1919 .flags = CLK_SET_RATE_PARENT, 1920 .ops = &clk_branch2_ops, 1921 }, 1922 }, 1923 }; 1924 1925 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 1926 .halt_reg = 0x283b4, 1927 .halt_check = BRANCH_HALT_VOTED, 1928 .clkr = { 1929 .enable_reg = 0x62008, 1930 .enable_mask = BIT(24), 1931 .hw.init = &(const struct clk_init_data) { 1932 .name = "gcc_qupv3_wrap1_s2_clk", 1933 .parent_hws = (const struct clk_hw*[]) { 1934 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 1935 }, 1936 .num_parents = 1, 1937 .flags = CLK_SET_RATE_PARENT, 1938 .ops = &clk_branch2_ops, 1939 }, 1940 }, 1941 }; 1942 1943 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 1944 .halt_reg = 0x284e8, 1945 .halt_check = BRANCH_HALT_VOTED, 1946 .clkr = { 1947 .enable_reg = 0x62008, 1948 .enable_mask = BIT(25), 1949 .hw.init = &(const struct clk_init_data) { 1950 .name = "gcc_qupv3_wrap1_s3_clk", 1951 .parent_hws = (const struct clk_hw*[]) { 1952 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 1953 }, 1954 .num_parents = 1, 1955 .flags = CLK_SET_RATE_PARENT, 1956 .ops = &clk_branch2_ops, 1957 }, 1958 }, 1959 }; 1960 1961 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 1962 .halt_reg = 0x2861c, 1963 .halt_check = BRANCH_HALT_VOTED, 1964 .clkr = { 1965 .enable_reg = 0x62008, 1966 .enable_mask = BIT(26), 1967 .hw.init = &(const struct clk_init_data) { 1968 .name = "gcc_qupv3_wrap1_s4_clk", 1969 .parent_hws = (const struct clk_hw*[]) { 1970 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 1971 }, 1972 .num_parents = 1, 1973 .flags = CLK_SET_RATE_PARENT, 1974 .ops = &clk_branch2_ops, 1975 }, 1976 }, 1977 }; 1978 1979 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 1980 .halt_reg = 0x28750, 1981 .halt_check = BRANCH_HALT_VOTED, 1982 .clkr = { 1983 .enable_reg = 0x62008, 1984 .enable_mask = BIT(27), 1985 .hw.init = &(const struct clk_init_data) { 1986 .name = "gcc_qupv3_wrap1_s5_clk", 1987 .parent_hws = (const struct clk_hw*[]) { 1988 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 1989 }, 1990 .num_parents = 1, 1991 .flags = CLK_SET_RATE_PARENT, 1992 .ops = &clk_branch2_ops, 1993 }, 1994 }, 1995 }; 1996 1997 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 1998 .halt_reg = 0x28884, 1999 .halt_check = BRANCH_HALT_VOTED, 2000 .clkr = { 2001 .enable_reg = 0x62008, 2002 .enable_mask = BIT(28), 2003 .hw.init = &(const struct clk_init_data) { 2004 .name = "gcc_qupv3_wrap1_s6_clk", 2005 .parent_hws = (const struct clk_hw*[]) { 2006 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 2007 }, 2008 .num_parents = 1, 2009 .flags = CLK_SET_RATE_PARENT, 2010 .ops = &clk_branch2_ops, 2011 }, 2012 }, 2013 }; 2014 2015 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 2016 .halt_reg = 0x289b8, 2017 .halt_check = BRANCH_HALT_VOTED, 2018 .clkr = { 2019 .enable_reg = 0x62008, 2020 .enable_mask = BIT(29), 2021 .hw.init = &(const struct clk_init_data) { 2022 .name = "gcc_qupv3_wrap1_s7_clk", 2023 .parent_hws = (const struct clk_hw*[]) { 2024 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 2025 }, 2026 .num_parents = 1, 2027 .flags = CLK_SET_RATE_PARENT, 2028 .ops = &clk_branch2_ops, 2029 }, 2030 }, 2031 }; 2032 2033 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2034 .halt_reg = 0x27004, 2035 .halt_check = BRANCH_HALT_VOTED, 2036 .hwcg_reg = 0x27004, 2037 .hwcg_bit = 1, 2038 .clkr = { 2039 .enable_reg = 0x62008, 2040 .enable_mask = BIT(6), 2041 .hw.init = &(const struct clk_init_data) { 2042 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2043 .ops = &clk_branch2_ops, 2044 }, 2045 }, 2046 }; 2047 2048 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2049 .halt_reg = 0x27008, 2050 .halt_check = BRANCH_HALT_VOTED, 2051 .hwcg_reg = 0x27008, 2052 .hwcg_bit = 1, 2053 .clkr = { 2054 .enable_reg = 0x62008, 2055 .enable_mask = BIT(7), 2056 .hw.init = &(const struct clk_init_data) { 2057 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2058 .ops = &clk_branch2_ops, 2059 }, 2060 }, 2061 }; 2062 2063 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2064 .halt_reg = 0x28004, 2065 .halt_check = BRANCH_HALT_VOTED, 2066 .hwcg_reg = 0x28004, 2067 .hwcg_bit = 1, 2068 .clkr = { 2069 .enable_reg = 0x62008, 2070 .enable_mask = BIT(20), 2071 .hw.init = &(const struct clk_init_data) { 2072 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2073 .ops = &clk_branch2_ops, 2074 }, 2075 }, 2076 }; 2077 2078 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2079 .halt_reg = 0x28008, 2080 .halt_check = BRANCH_HALT_VOTED, 2081 .hwcg_reg = 0x28008, 2082 .hwcg_bit = 1, 2083 .clkr = { 2084 .enable_reg = 0x62008, 2085 .enable_mask = BIT(21), 2086 .hw.init = &(const struct clk_init_data) { 2087 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2088 .ops = &clk_branch2_ops, 2089 }, 2090 }, 2091 }; 2092 2093 static struct clk_branch gcc_sdcc5_ahb_clk = { 2094 .halt_reg = 0x3b00c, 2095 .halt_check = BRANCH_HALT, 2096 .clkr = { 2097 .enable_reg = 0x3b00c, 2098 .enable_mask = BIT(0), 2099 .hw.init = &(const struct clk_init_data) { 2100 .name = "gcc_sdcc5_ahb_clk", 2101 .ops = &clk_branch2_ops, 2102 }, 2103 }, 2104 }; 2105 2106 static struct clk_branch gcc_sdcc5_apps_clk = { 2107 .halt_reg = 0x3b004, 2108 .halt_check = BRANCH_HALT, 2109 .clkr = { 2110 .enable_reg = 0x3b004, 2111 .enable_mask = BIT(0), 2112 .hw.init = &(const struct clk_init_data) { 2113 .name = "gcc_sdcc5_apps_clk", 2114 .parent_hws = (const struct clk_hw*[]) { 2115 &gcc_sdcc5_apps_clk_src.clkr.hw, 2116 }, 2117 .num_parents = 1, 2118 .flags = CLK_SET_RATE_PARENT, 2119 .ops = &clk_branch2_ops, 2120 }, 2121 }, 2122 }; 2123 2124 static struct clk_branch gcc_sdcc5_ice_core_clk = { 2125 .halt_reg = 0x3b010, 2126 .halt_check = BRANCH_HALT, 2127 .clkr = { 2128 .enable_reg = 0x3b010, 2129 .enable_mask = BIT(0), 2130 .hw.init = &(const struct clk_init_data) { 2131 .name = "gcc_sdcc5_ice_core_clk", 2132 .parent_hws = (const struct clk_hw*[]) { 2133 &gcc_sdcc5_ice_core_clk_src.clkr.hw, 2134 }, 2135 .num_parents = 1, 2136 .flags = CLK_SET_RATE_PARENT, 2137 .ops = &clk_branch2_ops, 2138 }, 2139 }, 2140 }; 2141 2142 static struct clk_branch gcc_sm_bus_ahb_clk = { 2143 .halt_reg = 0x5b004, 2144 .halt_check = BRANCH_HALT, 2145 .clkr = { 2146 .enable_reg = 0x5b004, 2147 .enable_mask = BIT(0), 2148 .hw.init = &(const struct clk_init_data) { 2149 .name = "gcc_sm_bus_ahb_clk", 2150 .ops = &clk_branch2_ops, 2151 }, 2152 }, 2153 }; 2154 2155 static struct clk_branch gcc_sm_bus_xo_clk = { 2156 .halt_reg = 0x5b008, 2157 .halt_check = BRANCH_HALT, 2158 .clkr = { 2159 .enable_reg = 0x5b008, 2160 .enable_mask = BIT(0), 2161 .hw.init = &(const struct clk_init_data) { 2162 .name = "gcc_sm_bus_xo_clk", 2163 .parent_hws = (const struct clk_hw*[]) { 2164 &gcc_sm_bus_xo_clk_src.clkr.hw, 2165 }, 2166 .num_parents = 1, 2167 .flags = CLK_SET_RATE_PARENT, 2168 .ops = &clk_branch2_ops, 2169 }, 2170 }, 2171 }; 2172 2173 static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_qx_clk = { 2174 .halt_reg = 0x9200c, 2175 .halt_check = BRANCH_HALT_SKIP, 2176 .hwcg_reg = 0x9200c, 2177 .hwcg_bit = 1, 2178 .clkr = { 2179 .enable_reg = 0x62000, 2180 .enable_mask = BIT(11), 2181 .hw.init = &(const struct clk_init_data) { 2182 .name = "gcc_snoc_cnoc_gemnoc_pcie_qx_clk", 2183 .ops = &clk_branch2_ops, 2184 }, 2185 }, 2186 }; 2187 2188 static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk = { 2189 .halt_reg = 0x92010, 2190 .halt_check = BRANCH_HALT_SKIP, 2191 .hwcg_reg = 0x92010, 2192 .hwcg_bit = 1, 2193 .clkr = { 2194 .enable_reg = 0x62000, 2195 .enable_mask = BIT(12), 2196 .hw.init = &(const struct clk_init_data) { 2197 .name = "gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk", 2198 .ops = &clk_branch2_ops, 2199 }, 2200 }, 2201 }; 2202 2203 static struct clk_branch gcc_snoc_cnoc_pcie_qx_clk = { 2204 .halt_reg = 0x84030, 2205 .halt_check = BRANCH_HALT, 2206 .clkr = { 2207 .enable_reg = 0x84030, 2208 .enable_mask = BIT(0), 2209 .hw.init = &(const struct clk_init_data) { 2210 .name = "gcc_snoc_cnoc_pcie_qx_clk", 2211 .ops = &clk_branch2_ops, 2212 }, 2213 }, 2214 }; 2215 2216 static struct clk_branch gcc_snoc_pcie_sf_center_qx_clk = { 2217 .halt_reg = 0x92014, 2218 .halt_check = BRANCH_HALT_SKIP, 2219 .hwcg_reg = 0x92014, 2220 .hwcg_bit = 1, 2221 .clkr = { 2222 .enable_reg = 0x62000, 2223 .enable_mask = BIT(19), 2224 .hw.init = &(const struct clk_init_data) { 2225 .name = "gcc_snoc_pcie_sf_center_qx_clk", 2226 .ops = &clk_branch2_ops, 2227 }, 2228 }, 2229 }; 2230 2231 static struct clk_branch gcc_snoc_pcie_sf_south_qx_clk = { 2232 .halt_reg = 0x92018, 2233 .halt_check = BRANCH_HALT_SKIP, 2234 .hwcg_reg = 0x92018, 2235 .hwcg_bit = 1, 2236 .clkr = { 2237 .enable_reg = 0x62000, 2238 .enable_mask = BIT(22), 2239 .hw.init = &(const struct clk_init_data) { 2240 .name = "gcc_snoc_pcie_sf_south_qx_clk", 2241 .ops = &clk_branch2_ops, 2242 }, 2243 }, 2244 }; 2245 2246 static struct clk_branch gcc_tsc_cfg_ahb_clk = { 2247 .halt_reg = 0x5700c, 2248 .halt_check = BRANCH_HALT, 2249 .clkr = { 2250 .enable_reg = 0x5700c, 2251 .enable_mask = BIT(0), 2252 .hw.init = &(const struct clk_init_data) { 2253 .name = "gcc_tsc_cfg_ahb_clk", 2254 .ops = &clk_branch2_ops, 2255 }, 2256 }, 2257 }; 2258 2259 static struct clk_branch gcc_tsc_cntr_clk = { 2260 .halt_reg = 0x57004, 2261 .halt_check = BRANCH_HALT, 2262 .clkr = { 2263 .enable_reg = 0x57004, 2264 .enable_mask = BIT(0), 2265 .hw.init = &(const struct clk_init_data) { 2266 .name = "gcc_tsc_cntr_clk", 2267 .parent_hws = (const struct clk_hw*[]) { 2268 &gcc_tsc_clk_src.clkr.hw, 2269 }, 2270 .num_parents = 1, 2271 .flags = CLK_SET_RATE_PARENT, 2272 .ops = &clk_branch2_ops, 2273 }, 2274 }, 2275 }; 2276 2277 static struct clk_branch gcc_tsc_etu_clk = { 2278 .halt_reg = 0x57008, 2279 .halt_check = BRANCH_HALT, 2280 .clkr = { 2281 .enable_reg = 0x57008, 2282 .enable_mask = BIT(0), 2283 .hw.init = &(const struct clk_init_data) { 2284 .name = "gcc_tsc_etu_clk", 2285 .parent_hws = (const struct clk_hw*[]) { 2286 &gcc_tsc_clk_src.clkr.hw, 2287 }, 2288 .num_parents = 1, 2289 .flags = CLK_SET_RATE_PARENT, 2290 .ops = &clk_branch2_ops, 2291 }, 2292 }, 2293 }; 2294 2295 static struct clk_branch gcc_usb2_clkref_en = { 2296 .halt_reg = 0x9c008, 2297 .halt_check = BRANCH_HALT, 2298 .clkr = { 2299 .enable_reg = 0x9c008, 2300 .enable_mask = BIT(0), 2301 .hw.init = &(const struct clk_init_data) { 2302 .name = "gcc_usb2_clkref_en", 2303 .ops = &clk_branch2_ops, 2304 }, 2305 }, 2306 }; 2307 2308 static struct clk_branch gcc_usb30_prim_master_clk = { 2309 .halt_reg = 0x49018, 2310 .halt_check = BRANCH_HALT, 2311 .clkr = { 2312 .enable_reg = 0x49018, 2313 .enable_mask = BIT(0), 2314 .hw.init = &(const struct clk_init_data) { 2315 .name = "gcc_usb30_prim_master_clk", 2316 .parent_hws = (const struct clk_hw*[]) { 2317 &gcc_usb30_prim_master_clk_src.clkr.hw, 2318 }, 2319 .num_parents = 1, 2320 .flags = CLK_SET_RATE_PARENT, 2321 .ops = &clk_branch2_ops, 2322 }, 2323 }, 2324 }; 2325 2326 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2327 .halt_reg = 0x49024, 2328 .halt_check = BRANCH_HALT, 2329 .clkr = { 2330 .enable_reg = 0x49024, 2331 .enable_mask = BIT(0), 2332 .hw.init = &(const struct clk_init_data) { 2333 .name = "gcc_usb30_prim_mock_utmi_clk", 2334 .parent_hws = (const struct clk_hw*[]) { 2335 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2336 }, 2337 .num_parents = 1, 2338 .flags = CLK_SET_RATE_PARENT, 2339 .ops = &clk_branch2_ops, 2340 }, 2341 }, 2342 }; 2343 2344 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2345 .halt_reg = 0x49020, 2346 .halt_check = BRANCH_HALT, 2347 .clkr = { 2348 .enable_reg = 0x49020, 2349 .enable_mask = BIT(0), 2350 .hw.init = &(const struct clk_init_data) { 2351 .name = "gcc_usb30_prim_sleep_clk", 2352 .ops = &clk_branch2_ops, 2353 }, 2354 }, 2355 }; 2356 2357 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2358 .halt_reg = 0x49060, 2359 .halt_check = BRANCH_HALT, 2360 .clkr = { 2361 .enable_reg = 0x49060, 2362 .enable_mask = BIT(0), 2363 .hw.init = &(const struct clk_init_data) { 2364 .name = "gcc_usb3_prim_phy_aux_clk", 2365 .parent_hws = (const struct clk_hw*[]) { 2366 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2367 }, 2368 .num_parents = 1, 2369 .flags = CLK_SET_RATE_PARENT, 2370 .ops = &clk_branch2_ops, 2371 }, 2372 }, 2373 }; 2374 2375 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2376 .halt_reg = 0x49064, 2377 .halt_check = BRANCH_HALT, 2378 .clkr = { 2379 .enable_reg = 0x49064, 2380 .enable_mask = BIT(0), 2381 .hw.init = &(const struct clk_init_data) { 2382 .name = "gcc_usb3_prim_phy_com_aux_clk", 2383 .parent_hws = (const struct clk_hw*[]) { 2384 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2385 }, 2386 .num_parents = 1, 2387 .flags = CLK_SET_RATE_PARENT, 2388 .ops = &clk_branch2_ops, 2389 }, 2390 }, 2391 }; 2392 2393 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2394 .halt_reg = 0x49068, 2395 .halt_check = BRANCH_HALT_DELAY, 2396 .hwcg_reg = 0x49068, 2397 .hwcg_bit = 1, 2398 .clkr = { 2399 .enable_reg = 0x49068, 2400 .enable_mask = BIT(0), 2401 .hw.init = &(const struct clk_init_data) { 2402 .name = "gcc_usb3_prim_phy_pipe_clk", 2403 .parent_hws = (const struct clk_hw*[]) { 2404 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 2405 }, 2406 .num_parents = 1, 2407 .flags = CLK_SET_RATE_PARENT, 2408 .ops = &clk_branch2_ops, 2409 }, 2410 }, 2411 }; 2412 2413 static struct gdsc pcie_0_gdsc = { 2414 .gdscr = 0x9d004, 2415 .en_rest_wait_val = 0x2, 2416 .en_few_wait_val = 0x2, 2417 .clk_dis_wait_val = 0xf, 2418 .pd = { 2419 .name = "gcc_pcie_0_gdsc", 2420 }, 2421 .pwrsts = PWRSTS_OFF_ON, 2422 }; 2423 2424 static struct gdsc pcie_0_phy_gdsc = { 2425 .gdscr = 0x7c004, 2426 .en_rest_wait_val = 0x2, 2427 .en_few_wait_val = 0x2, 2428 .clk_dis_wait_val = 0x2, 2429 .pd = { 2430 .name = "gcc_pcie_0_phy_gdsc", 2431 }, 2432 .pwrsts = PWRSTS_OFF_ON, 2433 }; 2434 2435 static struct gdsc usb30_prim_gdsc = { 2436 .gdscr = 0x49004, 2437 .en_rest_wait_val = 0x2, 2438 .en_few_wait_val = 0x2, 2439 .clk_dis_wait_val = 0xf, 2440 .pd = { 2441 .name = "gcc_usb30_prim_gdsc", 2442 }, 2443 .pwrsts = PWRSTS_OFF_ON, 2444 }; 2445 2446 static struct clk_regmap *gcc_qdu1000_clocks[] = { 2447 [GCC_AGGRE_NOC_ECPRI_DMA_CLK] = &gcc_aggre_noc_ecpri_dma_clk.clkr, 2448 [GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC] = &gcc_aggre_noc_ecpri_dma_clk_src.clkr, 2449 [GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC] = &gcc_aggre_noc_ecpri_gsi_clk_src.clkr, 2450 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2451 [GCC_CFG_NOC_ECPRI_CC_AHB_CLK] = &gcc_cfg_noc_ecpri_cc_ahb_clk.clkr, 2452 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2453 [GCC_DDRSS_ECPRI_DMA_CLK] = &gcc_ddrss_ecpri_dma_clk.clkr, 2454 [GCC_ECPRI_AHB_CLK] = &gcc_ecpri_ahb_clk.clkr, 2455 [GCC_ECPRI_CC_GPLL0_CLK_SRC] = &gcc_ecpri_cc_gpll0_clk_src.clkr, 2456 [GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll1_even_clk_src.clkr, 2457 [GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll2_even_clk_src.clkr, 2458 [GCC_ECPRI_CC_GPLL3_CLK_SRC] = &gcc_ecpri_cc_gpll3_clk_src.clkr, 2459 [GCC_ECPRI_CC_GPLL4_CLK_SRC] = &gcc_ecpri_cc_gpll4_clk_src.clkr, 2460 [GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll5_even_clk_src.clkr, 2461 [GCC_ECPRI_XO_CLK] = &gcc_ecpri_xo_clk.clkr, 2462 [GCC_ETH_DBG_SNOC_AXI_CLK] = &gcc_eth_dbg_snoc_axi_clk.clkr, 2463 [GCC_GEMNOC_PCIE_QX_CLK] = &gcc_gemnoc_pcie_qx_clk.clkr, 2464 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2465 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2466 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2467 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2468 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2469 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2470 [GCC_GPLL0] = &gcc_gpll0.clkr, 2471 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 2472 [GCC_GPLL1] = &gcc_gpll1.clkr, 2473 [GCC_GPLL2] = &gcc_gpll2.clkr, 2474 [GCC_GPLL2_OUT_EVEN] = &gcc_gpll2_out_even.clkr, 2475 [GCC_GPLL3] = &gcc_gpll3.clkr, 2476 [GCC_GPLL4] = &gcc_gpll4.clkr, 2477 [GCC_GPLL5] = &gcc_gpll5.clkr, 2478 [GCC_GPLL5_OUT_EVEN] = &gcc_gpll5_out_even.clkr, 2479 [GCC_GPLL6] = &gcc_gpll6.clkr, 2480 [GCC_GPLL7] = &gcc_gpll7.clkr, 2481 [GCC_GPLL8] = &gcc_gpll8.clkr, 2482 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2483 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 2484 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2485 [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr, 2486 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2487 [GCC_PCIE_0_PHY_AUX_CLK] = &gcc_pcie_0_phy_aux_clk.clkr, 2488 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 2489 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 2490 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2491 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2492 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 2493 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2494 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 2495 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2496 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2497 [GCC_QMIP_ANOC_PCIE_CLK] = &gcc_qmip_anoc_pcie_clk.clkr, 2498 [GCC_QMIP_ECPRI_DMA0_CLK] = &gcc_qmip_ecpri_dma0_clk.clkr, 2499 [GCC_QMIP_ECPRI_DMA1_CLK] = &gcc_qmip_ecpri_dma1_clk.clkr, 2500 [GCC_QMIP_ECPRI_GSI_CLK] = &gcc_qmip_ecpri_gsi_clk.clkr, 2501 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 2502 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 2503 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 2504 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 2505 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 2506 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 2507 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 2508 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 2509 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 2510 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 2511 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 2512 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 2513 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 2514 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 2515 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 2516 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 2517 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 2518 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 2519 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 2520 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 2521 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 2522 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 2523 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 2524 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 2525 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 2526 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 2527 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 2528 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 2529 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 2530 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 2531 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 2532 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 2533 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 2534 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 2535 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 2536 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 2537 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 2538 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 2539 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 2540 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 2541 [GCC_SDCC5_AHB_CLK] = &gcc_sdcc5_ahb_clk.clkr, 2542 [GCC_SDCC5_APPS_CLK] = &gcc_sdcc5_apps_clk.clkr, 2543 [GCC_SDCC5_APPS_CLK_SRC] = &gcc_sdcc5_apps_clk_src.clkr, 2544 [GCC_SDCC5_ICE_CORE_CLK] = &gcc_sdcc5_ice_core_clk.clkr, 2545 [GCC_SDCC5_ICE_CORE_CLK_SRC] = &gcc_sdcc5_ice_core_clk_src.clkr, 2546 [GCC_SM_BUS_AHB_CLK] = &gcc_sm_bus_ahb_clk.clkr, 2547 [GCC_SM_BUS_XO_CLK] = &gcc_sm_bus_xo_clk.clkr, 2548 [GCC_SM_BUS_XO_CLK_SRC] = &gcc_sm_bus_xo_clk_src.clkr, 2549 [GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK] = &gcc_snoc_cnoc_gemnoc_pcie_qx_clk.clkr, 2550 [GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK] = &gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk.clkr, 2551 [GCC_SNOC_CNOC_PCIE_QX_CLK] = &gcc_snoc_cnoc_pcie_qx_clk.clkr, 2552 [GCC_SNOC_PCIE_SF_CENTER_QX_CLK] = &gcc_snoc_pcie_sf_center_qx_clk.clkr, 2553 [GCC_SNOC_PCIE_SF_SOUTH_QX_CLK] = &gcc_snoc_pcie_sf_south_qx_clk.clkr, 2554 [GCC_TSC_CFG_AHB_CLK] = &gcc_tsc_cfg_ahb_clk.clkr, 2555 [GCC_TSC_CLK_SRC] = &gcc_tsc_clk_src.clkr, 2556 [GCC_TSC_CNTR_CLK] = &gcc_tsc_cntr_clk.clkr, 2557 [GCC_TSC_ETU_CLK] = &gcc_tsc_etu_clk.clkr, 2558 [GCC_USB2_CLKREF_EN] = &gcc_usb2_clkref_en.clkr, 2559 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 2560 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 2561 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 2562 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 2563 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 2564 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 2565 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 2566 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 2567 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 2568 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 2569 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 2570 [GCC_ETH_100G_C2C_HM_APB_CLK] = &gcc_eth_100g_c2c_hm_apb_clk.clkr, 2571 [GCC_ETH_100G_FH_HM_APB_0_CLK] = &gcc_eth_100g_fh_hm_apb_0_clk.clkr, 2572 [GCC_ETH_100G_FH_HM_APB_1_CLK] = &gcc_eth_100g_fh_hm_apb_1_clk.clkr, 2573 [GCC_ETH_100G_FH_HM_APB_2_CLK] = &gcc_eth_100g_fh_hm_apb_2_clk.clkr, 2574 [GCC_ETH_DBG_C2C_HM_APB_CLK] = &gcc_eth_dbg_c2c_hm_apb_clk.clkr, 2575 [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr, 2576 [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, 2577 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 2578 [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr, 2579 [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr, 2580 }; 2581 2582 static struct gdsc *gcc_qdu1000_gdscs[] = { 2583 [PCIE_0_GDSC] = &pcie_0_gdsc, 2584 [PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc, 2585 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 2586 }; 2587 2588 static const struct qcom_reset_map gcc_qdu1000_resets[] = { 2589 [GCC_ECPRI_CC_BCR] = { 0x3e000 }, 2590 [GCC_ECPRI_SS_BCR] = { 0x3a000 }, 2591 [GCC_ETH_WRAPPER_BCR] = { 0x39000 }, 2592 [GCC_PCIE_0_BCR] = { 0x9d000 }, 2593 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x9e014 }, 2594 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x9e020 }, 2595 [GCC_PCIE_0_PHY_BCR] = { 0x7c000 }, 2596 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 }, 2597 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c }, 2598 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 }, 2599 [GCC_PDM_BCR] = { 0x43000 }, 2600 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 }, 2601 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 }, 2602 [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 }, 2603 [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 }, 2604 [GCC_SDCC5_BCR] = { 0x3b000 }, 2605 [GCC_TSC_BCR] = { 0x57000 }, 2606 [GCC_USB30_PRIM_BCR] = { 0x49000 }, 2607 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 }, 2608 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 }, 2609 [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 }, 2610 [GCC_USB3_PHY_SEC_BCR] = { 0x6000c }, 2611 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 }, 2612 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 }, 2613 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 }, 2614 }; 2615 2616 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 2617 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 2618 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 2619 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 2620 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 2621 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 2622 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 2623 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 2624 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 2625 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 2626 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 2627 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 2628 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 2629 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 2630 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 2631 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 2632 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 2633 }; 2634 2635 static const struct regmap_config gcc_qdu1000_regmap_config = { 2636 .reg_bits = 32, 2637 .reg_stride = 4, 2638 .val_bits = 32, 2639 .max_register = 0x1f41f0, 2640 .fast_io = true, 2641 }; 2642 2643 static const struct qcom_cc_desc gcc_qdu1000_desc = { 2644 .config = &gcc_qdu1000_regmap_config, 2645 .clks = gcc_qdu1000_clocks, 2646 .num_clks = ARRAY_SIZE(gcc_qdu1000_clocks), 2647 .resets = gcc_qdu1000_resets, 2648 .num_resets = ARRAY_SIZE(gcc_qdu1000_resets), 2649 .gdscs = gcc_qdu1000_gdscs, 2650 .num_gdscs = ARRAY_SIZE(gcc_qdu1000_gdscs), 2651 }; 2652 2653 static const struct of_device_id gcc_qdu1000_match_table[] = { 2654 { .compatible = "qcom,qdu1000-gcc" }, 2655 { } 2656 }; 2657 MODULE_DEVICE_TABLE(of, gcc_qdu1000_match_table); 2658 2659 static int gcc_qdu1000_probe(struct platform_device *pdev) 2660 { 2661 struct regmap *regmap; 2662 int ret; 2663 2664 regmap = qcom_cc_map(pdev, &gcc_qdu1000_desc); 2665 if (IS_ERR(regmap)) 2666 return PTR_ERR(regmap); 2667 2668 /* Update FORCE_MEM_CORE_ON for gcc_pcie_0_mstr_axi_clk */ 2669 regmap_update_bits(regmap, 0x9d024, BIT(14), BIT(14)); 2670 2671 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 2672 ARRAY_SIZE(gcc_dfs_clocks)); 2673 if (ret) 2674 return ret; 2675 2676 ret = qcom_cc_really_probe(pdev, &gcc_qdu1000_desc, regmap); 2677 if (ret) 2678 return dev_err_probe(&pdev->dev, ret, "Failed to register GCC clocks\n"); 2679 2680 return ret; 2681 } 2682 2683 static struct platform_driver gcc_qdu1000_driver = { 2684 .probe = gcc_qdu1000_probe, 2685 .driver = { 2686 .name = "gcc-qdu1000", 2687 .of_match_table = gcc_qdu1000_match_table, 2688 }, 2689 }; 2690 2691 static int __init gcc_qdu1000_init(void) 2692 { 2693 return platform_driver_register(&gcc_qdu1000_driver); 2694 } 2695 subsys_initcall(gcc_qdu1000_init); 2696 2697 static void __exit gcc_qdu1000_exit(void) 2698 { 2699 platform_driver_unregister(&gcc_qdu1000_driver); 2700 } 2701 module_exit(gcc_qdu1000_exit); 2702 2703 MODULE_DESCRIPTION("QTI GCC QDU1000 Driver"); 2704 MODULE_LICENSE("GPL"); 2705