1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/of_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,qdu1000-gcc.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-rcg.h" 16 #include "clk-regmap.h" 17 #include "clk-regmap-divider.h" 18 #include "clk-regmap-mux.h" 19 #include "clk-regmap-phy-mux.h" 20 #include "reset.h" 21 22 enum { 23 P_BI_TCXO, 24 P_GCC_GPLL0_OUT_EVEN, 25 P_GCC_GPLL0_OUT_MAIN, 26 P_GCC_GPLL1_OUT_MAIN, 27 P_GCC_GPLL2_OUT_MAIN, 28 P_GCC_GPLL3_OUT_MAIN, 29 P_GCC_GPLL4_OUT_MAIN, 30 P_GCC_GPLL5_OUT_MAIN, 31 P_GCC_GPLL6_OUT_MAIN, 32 P_GCC_GPLL7_OUT_MAIN, 33 P_GCC_GPLL8_OUT_MAIN, 34 P_PCIE_0_PHY_AUX_CLK, 35 P_PCIE_0_PIPE_CLK, 36 P_SLEEP_CLK, 37 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 38 }; 39 40 enum { 41 DT_TCXO_IDX, 42 DT_SLEEP_CLK_IDX, 43 DT_PCIE_0_PIPE_CLK_IDX, 44 DT_PCIE_0_PHY_AUX_CLK_IDX, 45 DT_USB3_PHY_WRAPPER_PIPE_CLK_IDX, 46 }; 47 48 static struct clk_alpha_pll gcc_gpll0 = { 49 .offset = 0x0, 50 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 51 .clkr = { 52 .enable_reg = 0x62018, 53 .enable_mask = BIT(0), 54 .hw.init = &(const struct clk_init_data) { 55 .name = "gcc_gpll0", 56 .parent_data = &(const struct clk_parent_data) { 57 .index = DT_TCXO_IDX, 58 }, 59 .num_parents = 1, 60 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 61 }, 62 }, 63 }; 64 65 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 66 { 0x1, 2 } 67 }; 68 69 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 70 .offset = 0x0, 71 .post_div_shift = 10, 72 .post_div_table = post_div_table_gcc_gpll0_out_even, 73 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 74 .width = 4, 75 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 76 .clkr.hw.init = &(const struct clk_init_data) { 77 .name = "gcc_gpll0_out_even", 78 .parent_hws = (const struct clk_hw*[]) { 79 &gcc_gpll0.clkr.hw, 80 }, 81 .num_parents = 1, 82 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 83 }, 84 }; 85 86 static struct clk_alpha_pll gcc_gpll1 = { 87 .offset = 0x1000, 88 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 89 .clkr = { 90 .enable_reg = 0x62018, 91 .enable_mask = BIT(1), 92 .hw.init = &(const struct clk_init_data) { 93 .name = "gcc_gpll1", 94 .parent_data = &(const struct clk_parent_data) { 95 .index = DT_TCXO_IDX, 96 }, 97 .num_parents = 1, 98 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 99 }, 100 }, 101 }; 102 103 static struct clk_alpha_pll_postdiv gcc_gpll1_out_even = { 104 .offset = 0x1000, 105 .post_div_shift = 10, 106 .post_div_table = post_div_table_gcc_gpll0_out_even, 107 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 108 .width = 4, 109 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 110 .clkr.hw.init = &(const struct clk_init_data) { 111 .name = "gcc_gpll1_out_even", 112 .parent_hws = (const struct clk_hw*[]) { 113 &gcc_gpll1.clkr.hw, 114 }, 115 .num_parents = 1, 116 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 117 }, 118 }; 119 120 static struct clk_alpha_pll gcc_gpll2 = { 121 .offset = 0x2000, 122 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 123 .clkr = { 124 .enable_reg = 0x62018, 125 .enable_mask = BIT(2), 126 .hw.init = &(const struct clk_init_data) { 127 .name = "gcc_gpll2", 128 .parent_data = &(const struct clk_parent_data) { 129 .index = DT_TCXO_IDX, 130 }, 131 .num_parents = 1, 132 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 133 }, 134 }, 135 }; 136 137 static struct clk_alpha_pll_postdiv gcc_gpll2_out_even = { 138 .offset = 0x2000, 139 .post_div_shift = 10, 140 .post_div_table = post_div_table_gcc_gpll0_out_even, 141 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 142 .width = 4, 143 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 144 .clkr.hw.init = &(const struct clk_init_data) { 145 .name = "gcc_gpll2_out_even", 146 .parent_hws = (const struct clk_hw*[]) { 147 &gcc_gpll2.clkr.hw, 148 }, 149 .num_parents = 1, 150 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 151 }, 152 }; 153 154 static struct clk_alpha_pll gcc_gpll3 = { 155 .offset = 0x3000, 156 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 157 .clkr = { 158 .enable_reg = 0x62018, 159 .enable_mask = BIT(3), 160 .hw.init = &(const struct clk_init_data) { 161 .name = "gcc_gpll3", 162 .parent_data = &(const struct clk_parent_data) { 163 .index = DT_TCXO_IDX, 164 }, 165 .num_parents = 1, 166 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 167 }, 168 }, 169 }; 170 171 static struct clk_alpha_pll gcc_gpll4 = { 172 .offset = 0x4000, 173 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 174 .clkr = { 175 .enable_reg = 0x62018, 176 .enable_mask = BIT(4), 177 .hw.init = &(const struct clk_init_data) { 178 .name = "gcc_gpll4", 179 .parent_data = &(const struct clk_parent_data) { 180 .index = DT_TCXO_IDX, 181 }, 182 .num_parents = 1, 183 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 184 }, 185 }, 186 }; 187 188 static struct clk_alpha_pll gcc_gpll5 = { 189 .offset = 0x5000, 190 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 191 .clkr = { 192 .enable_reg = 0x62018, 193 .enable_mask = BIT(5), 194 .hw.init = &(const struct clk_init_data) { 195 .name = "gcc_gpll5", 196 .parent_data = &(const struct clk_parent_data) { 197 .index = DT_TCXO_IDX, 198 }, 199 .num_parents = 1, 200 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 201 }, 202 }, 203 }; 204 205 static struct clk_alpha_pll_postdiv gcc_gpll5_out_even = { 206 .offset = 0x5000, 207 .post_div_shift = 10, 208 .post_div_table = post_div_table_gcc_gpll0_out_even, 209 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 210 .width = 4, 211 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 212 .clkr.hw.init = &(const struct clk_init_data) { 213 .name = "gcc_gpll5_out_even", 214 .parent_hws = (const struct clk_hw*[]) { 215 &gcc_gpll5.clkr.hw, 216 }, 217 .num_parents = 1, 218 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 219 }, 220 }; 221 222 static struct clk_alpha_pll gcc_gpll6 = { 223 .offset = 0x6000, 224 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 225 .clkr = { 226 .enable_reg = 0x62018, 227 .enable_mask = BIT(6), 228 .hw.init = &(const struct clk_init_data) { 229 .name = "gcc_gpll6", 230 .parent_data = &(const struct clk_parent_data) { 231 .index = DT_TCXO_IDX, 232 }, 233 .num_parents = 1, 234 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 235 }, 236 }, 237 }; 238 239 static struct clk_alpha_pll gcc_gpll7 = { 240 .offset = 0x7000, 241 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 242 .clkr = { 243 .enable_reg = 0x62018, 244 .enable_mask = BIT(7), 245 .hw.init = &(const struct clk_init_data) { 246 .name = "gcc_gpll7", 247 .parent_data = &(const struct clk_parent_data) { 248 .index = DT_TCXO_IDX, 249 }, 250 .num_parents = 1, 251 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 252 }, 253 }, 254 }; 255 256 static struct clk_alpha_pll gcc_gpll8 = { 257 .offset = 0x8000, 258 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 259 .clkr = { 260 .enable_reg = 0x62018, 261 .enable_mask = BIT(8), 262 .hw.init = &(const struct clk_init_data) { 263 .name = "gcc_gpll8", 264 .parent_data = &(const struct clk_parent_data) { 265 .index = DT_TCXO_IDX, 266 }, 267 .num_parents = 1, 268 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 269 }, 270 }, 271 }; 272 273 static const struct parent_map gcc_parent_map_0[] = { 274 { P_BI_TCXO, 0 }, 275 { P_GCC_GPLL0_OUT_MAIN, 1 }, 276 { P_GCC_GPLL0_OUT_EVEN, 6 }, 277 }; 278 279 static const struct clk_parent_data gcc_parent_data_0[] = { 280 { .index = DT_TCXO_IDX }, 281 { .hw = &gcc_gpll0.clkr.hw }, 282 { .hw = &gcc_gpll0_out_even.clkr.hw }, 283 }; 284 285 static const struct parent_map gcc_parent_map_1[] = { 286 { P_BI_TCXO, 0 }, 287 { P_GCC_GPLL0_OUT_MAIN, 1 }, 288 { P_SLEEP_CLK, 5 }, 289 { P_GCC_GPLL0_OUT_EVEN, 6 }, 290 }; 291 292 static const struct clk_parent_data gcc_parent_data_1[] = { 293 { .index = DT_TCXO_IDX }, 294 { .hw = &gcc_gpll0.clkr.hw }, 295 { .index = DT_SLEEP_CLK_IDX }, 296 { .hw = &gcc_gpll0_out_even.clkr.hw }, 297 }; 298 299 static const struct parent_map gcc_parent_map_2[] = { 300 { P_BI_TCXO, 0 }, 301 { P_GCC_GPLL0_OUT_MAIN, 1 }, 302 { P_GCC_GPLL5_OUT_MAIN, 3 }, 303 { P_GCC_GPLL4_OUT_MAIN, 5 }, 304 }; 305 306 static const struct clk_parent_data gcc_parent_data_2[] = { 307 { .index = DT_TCXO_IDX }, 308 { .hw = &gcc_gpll0.clkr.hw }, 309 { .hw = &gcc_gpll5.clkr.hw }, 310 { .hw = &gcc_gpll4.clkr.hw }, 311 }; 312 313 static const struct parent_map gcc_parent_map_3[] = { 314 { P_BI_TCXO, 0 }, 315 { P_SLEEP_CLK, 5 }, 316 }; 317 318 static const struct clk_parent_data gcc_parent_data_3[] = { 319 { .index = DT_TCXO_IDX }, 320 { .index = DT_SLEEP_CLK_IDX }, 321 }; 322 323 static const struct parent_map gcc_parent_map_4[] = { 324 { P_BI_TCXO, 0 }, 325 { P_GCC_GPLL0_OUT_MAIN, 1 }, 326 { P_GCC_GPLL2_OUT_MAIN, 2 }, 327 { P_GCC_GPLL5_OUT_MAIN, 3 }, 328 { P_GCC_GPLL1_OUT_MAIN, 4 }, 329 { P_GCC_GPLL4_OUT_MAIN, 5 }, 330 { P_GCC_GPLL3_OUT_MAIN, 6 }, 331 }; 332 333 static const struct clk_parent_data gcc_parent_data_4[] = { 334 { .index = DT_TCXO_IDX }, 335 { .hw = &gcc_gpll0.clkr.hw }, 336 { .hw = &gcc_gpll2.clkr.hw }, 337 { .hw = &gcc_gpll5.clkr.hw }, 338 { .hw = &gcc_gpll1.clkr.hw }, 339 { .hw = &gcc_gpll4.clkr.hw }, 340 { .hw = &gcc_gpll3.clkr.hw }, 341 }; 342 343 static const struct parent_map gcc_parent_map_5[] = { 344 { P_BI_TCXO, 0 }, 345 { P_GCC_GPLL0_OUT_MAIN, 1 }, 346 { P_GCC_GPLL2_OUT_MAIN, 2 }, 347 { P_GCC_GPLL6_OUT_MAIN, 3 }, 348 { P_GCC_GPLL1_OUT_MAIN, 4 }, 349 { P_GCC_GPLL4_OUT_MAIN, 5 }, 350 { P_GCC_GPLL3_OUT_MAIN, 6 }, 351 }; 352 353 static const struct clk_parent_data gcc_parent_data_5[] = { 354 { .index = DT_TCXO_IDX }, 355 { .hw = &gcc_gpll0.clkr.hw }, 356 { .hw = &gcc_gpll2.clkr.hw }, 357 { .hw = &gcc_gpll6.clkr.hw }, 358 { .hw = &gcc_gpll1.clkr.hw }, 359 { .hw = &gcc_gpll4.clkr.hw }, 360 { .hw = &gcc_gpll3.clkr.hw }, 361 }; 362 363 static const struct parent_map gcc_parent_map_6[] = { 364 { P_PCIE_0_PHY_AUX_CLK, 0 }, 365 { P_BI_TCXO, 2 }, 366 }; 367 368 static const struct clk_parent_data gcc_parent_data_6[] = { 369 { .index = DT_PCIE_0_PHY_AUX_CLK_IDX }, 370 { .index = DT_TCXO_IDX }, 371 }; 372 373 static const struct parent_map gcc_parent_map_7[] = { 374 { P_PCIE_0_PIPE_CLK, 0 }, 375 { P_BI_TCXO, 2 }, 376 }; 377 378 static const struct clk_parent_data gcc_parent_data_7[] = { 379 { .index = DT_PCIE_0_PIPE_CLK_IDX }, 380 { .index = DT_TCXO_IDX }, 381 }; 382 383 static const struct parent_map gcc_parent_map_8[] = { 384 { P_BI_TCXO, 0 }, 385 { P_GCC_GPLL0_OUT_MAIN, 1 }, 386 { P_GCC_GPLL8_OUT_MAIN, 2 }, 387 { P_GCC_GPLL5_OUT_MAIN, 3 }, 388 { P_GCC_GPLL4_OUT_MAIN, 5 }, 389 }; 390 391 static const struct clk_parent_data gcc_parent_data_8[] = { 392 { .index = DT_TCXO_IDX }, 393 { .hw = &gcc_gpll0.clkr.hw }, 394 { .hw = &gcc_gpll8.clkr.hw }, 395 { .hw = &gcc_gpll5.clkr.hw }, 396 { .hw = &gcc_gpll4.clkr.hw }, 397 }; 398 399 static const struct parent_map gcc_parent_map_9[] = { 400 { P_BI_TCXO, 0 }, 401 { P_GCC_GPLL0_OUT_MAIN, 1 }, 402 { P_GCC_GPLL2_OUT_MAIN, 2 }, 403 { P_GCC_GPLL5_OUT_MAIN, 3 }, 404 { P_GCC_GPLL7_OUT_MAIN, 4 }, 405 { P_GCC_GPLL4_OUT_MAIN, 5 }, 406 }; 407 408 static const struct clk_parent_data gcc_parent_data_9[] = { 409 { .index = DT_TCXO_IDX }, 410 { .hw = &gcc_gpll0.clkr.hw }, 411 { .hw = &gcc_gpll2.clkr.hw }, 412 { .hw = &gcc_gpll5.clkr.hw }, 413 { .hw = &gcc_gpll7.clkr.hw }, 414 { .hw = &gcc_gpll4.clkr.hw }, 415 }; 416 417 static const struct parent_map gcc_parent_map_10[] = { 418 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 419 { P_BI_TCXO, 2 }, 420 }; 421 422 static const struct clk_parent_data gcc_parent_data_10[] = { 423 { .index = DT_USB3_PHY_WRAPPER_PIPE_CLK_IDX }, 424 { .index = DT_TCXO_IDX }, 425 }; 426 427 static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = { 428 .reg = 0x9d080, 429 .shift = 0, 430 .width = 2, 431 .parent_map = gcc_parent_map_6, 432 .clkr = { 433 .hw.init = &(const struct clk_init_data) { 434 .name = "gcc_pcie_0_phy_aux_clk_src", 435 .parent_data = gcc_parent_data_6, 436 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 437 .ops = &clk_regmap_mux_closest_ops, 438 }, 439 }, 440 }; 441 442 static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { 443 .reg = 0x9d064, 444 .shift = 0, 445 .width = 2, 446 .parent_map = gcc_parent_map_7, 447 .clkr = { 448 .hw.init = &(const struct clk_init_data) { 449 .name = "gcc_pcie_0_pipe_clk_src", 450 .parent_data = gcc_parent_data_7, 451 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 452 .ops = &clk_regmap_phy_mux_ops, 453 }, 454 }, 455 }; 456 457 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 458 .reg = 0x4906c, 459 .shift = 0, 460 .width = 2, 461 .parent_map = gcc_parent_map_10, 462 .clkr = { 463 .hw.init = &(const struct clk_init_data) { 464 .name = "gcc_usb3_prim_phy_pipe_clk_src", 465 .parent_data = gcc_parent_data_10, 466 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 467 .ops = &clk_regmap_mux_closest_ops, 468 }, 469 }, 470 }; 471 472 static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_dma_clk_src[] = { 473 F(466500000, P_GCC_GPLL5_OUT_MAIN, 2, 0, 0), 474 F(500000000, P_GCC_GPLL2_OUT_MAIN, 2, 0, 0), 475 { } 476 }; 477 478 static struct clk_rcg2 gcc_aggre_noc_ecpri_dma_clk_src = { 479 .cmd_rcgr = 0x92020, 480 .mnd_width = 0, 481 .hid_width = 5, 482 .parent_map = gcc_parent_map_4, 483 .freq_tbl = ftbl_gcc_aggre_noc_ecpri_dma_clk_src, 484 .clkr.hw.init = &(const struct clk_init_data) { 485 .name = "gcc_aggre_noc_ecpri_dma_clk_src", 486 .parent_data = gcc_parent_data_4, 487 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 488 .ops = &clk_rcg2_ops, 489 }, 490 }; 491 492 static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_gsi_clk_src[] = { 493 F(250000000, P_GCC_GPLL2_OUT_MAIN, 4, 0, 0), 494 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 495 { } 496 }; 497 498 static struct clk_rcg2 gcc_aggre_noc_ecpri_gsi_clk_src = { 499 .cmd_rcgr = 0x92038, 500 .mnd_width = 0, 501 .hid_width = 5, 502 .parent_map = gcc_parent_map_5, 503 .freq_tbl = ftbl_gcc_aggre_noc_ecpri_gsi_clk_src, 504 .clkr.hw.init = &(const struct clk_init_data) { 505 .name = "gcc_aggre_noc_ecpri_gsi_clk_src", 506 .parent_data = gcc_parent_data_5, 507 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 508 .ops = &clk_rcg2_ops, 509 }, 510 }; 511 512 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 513 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 514 { } 515 }; 516 517 static struct clk_rcg2 gcc_gp1_clk_src = { 518 .cmd_rcgr = 0x74004, 519 .mnd_width = 16, 520 .hid_width = 5, 521 .parent_map = gcc_parent_map_1, 522 .freq_tbl = ftbl_gcc_gp1_clk_src, 523 .clkr.hw.init = &(const struct clk_init_data) { 524 .name = "gcc_gp1_clk_src", 525 .parent_data = gcc_parent_data_1, 526 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 527 .ops = &clk_rcg2_ops, 528 }, 529 }; 530 531 static struct clk_rcg2 gcc_gp2_clk_src = { 532 .cmd_rcgr = 0x75004, 533 .mnd_width = 16, 534 .hid_width = 5, 535 .parent_map = gcc_parent_map_1, 536 .freq_tbl = ftbl_gcc_gp1_clk_src, 537 .clkr.hw.init = &(const struct clk_init_data) { 538 .name = "gcc_gp2_clk_src", 539 .parent_data = gcc_parent_data_1, 540 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 541 .ops = &clk_rcg2_ops, 542 }, 543 }; 544 545 static struct clk_rcg2 gcc_gp3_clk_src = { 546 .cmd_rcgr = 0x76004, 547 .mnd_width = 16, 548 .hid_width = 5, 549 .parent_map = gcc_parent_map_1, 550 .freq_tbl = ftbl_gcc_gp1_clk_src, 551 .clkr.hw.init = &(const struct clk_init_data) { 552 .name = "gcc_gp3_clk_src", 553 .parent_data = gcc_parent_data_1, 554 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 555 .ops = &clk_rcg2_ops, 556 }, 557 }; 558 559 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 560 F(19200000, P_BI_TCXO, 1, 0, 0), 561 { } 562 }; 563 564 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 565 .cmd_rcgr = 0x9d068, 566 .mnd_width = 16, 567 .hid_width = 5, 568 .parent_map = gcc_parent_map_3, 569 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 570 .clkr.hw.init = &(const struct clk_init_data) { 571 .name = "gcc_pcie_0_aux_clk_src", 572 .parent_data = gcc_parent_data_3, 573 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 574 .ops = &clk_rcg2_ops, 575 }, 576 }; 577 578 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 579 F(19200000, P_BI_TCXO, 1, 0, 0), 580 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 581 { } 582 }; 583 584 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 585 .cmd_rcgr = 0x9d04c, 586 .mnd_width = 0, 587 .hid_width = 5, 588 .parent_map = gcc_parent_map_0, 589 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 590 .clkr.hw.init = &(const struct clk_init_data) { 591 .name = "gcc_pcie_0_phy_rchng_clk_src", 592 .parent_data = gcc_parent_data_0, 593 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 594 .ops = &clk_rcg2_ops, 595 }, 596 }; 597 598 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 599 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 600 { } 601 }; 602 603 static struct clk_rcg2 gcc_pdm2_clk_src = { 604 .cmd_rcgr = 0x43010, 605 .mnd_width = 0, 606 .hid_width = 5, 607 .parent_map = gcc_parent_map_0, 608 .freq_tbl = ftbl_gcc_pdm2_clk_src, 609 .clkr.hw.init = &(const struct clk_init_data) { 610 .name = "gcc_pdm2_clk_src", 611 .parent_data = gcc_parent_data_0, 612 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 613 .ops = &clk_rcg2_ops, 614 }, 615 }; 616 617 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 618 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 619 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 620 F(19200000, P_BI_TCXO, 1, 0, 0), 621 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 622 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 623 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 624 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 625 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 626 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 627 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 628 { } 629 }; 630 631 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 632 .name = "gcc_qupv3_wrap0_s0_clk_src", 633 .parent_data = gcc_parent_data_0, 634 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 635 .ops = &clk_rcg2_ops, 636 }; 637 638 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 639 .cmd_rcgr = 0x27154, 640 .mnd_width = 16, 641 .hid_width = 5, 642 .parent_map = gcc_parent_map_0, 643 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 644 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 645 }; 646 647 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 648 .name = "gcc_qupv3_wrap0_s1_clk_src", 649 .parent_data = gcc_parent_data_0, 650 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 651 .ops = &clk_rcg2_ops, 652 }; 653 654 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 655 .cmd_rcgr = 0x27288, 656 .mnd_width = 16, 657 .hid_width = 5, 658 .parent_map = gcc_parent_map_0, 659 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 660 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 661 }; 662 663 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 664 .name = "gcc_qupv3_wrap0_s2_clk_src", 665 .parent_data = gcc_parent_data_0, 666 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 667 .ops = &clk_rcg2_ops, 668 }; 669 670 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 671 .cmd_rcgr = 0x273bc, 672 .mnd_width = 16, 673 .hid_width = 5, 674 .parent_map = gcc_parent_map_0, 675 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 676 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 677 }; 678 679 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 680 .name = "gcc_qupv3_wrap0_s3_clk_src", 681 .parent_data = gcc_parent_data_0, 682 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 683 .ops = &clk_rcg2_ops, 684 }; 685 686 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 687 .cmd_rcgr = 0x274f0, 688 .mnd_width = 16, 689 .hid_width = 5, 690 .parent_map = gcc_parent_map_0, 691 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 692 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 693 }; 694 695 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 696 .name = "gcc_qupv3_wrap0_s4_clk_src", 697 .parent_data = gcc_parent_data_0, 698 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 699 .ops = &clk_rcg2_ops, 700 }; 701 702 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 703 .cmd_rcgr = 0x27624, 704 .mnd_width = 16, 705 .hid_width = 5, 706 .parent_map = gcc_parent_map_0, 707 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 708 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 709 }; 710 711 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] = { 712 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 713 { } 714 }; 715 716 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 717 .name = "gcc_qupv3_wrap0_s5_clk_src", 718 .parent_data = gcc_parent_data_0, 719 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 720 .ops = &clk_rcg2_ops, 721 }; 722 723 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 724 .cmd_rcgr = 0x27758, 725 .mnd_width = 16, 726 .hid_width = 5, 727 .parent_map = gcc_parent_map_0, 728 .freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src, 729 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 730 }; 731 732 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 733 .name = "gcc_qupv3_wrap0_s6_clk_src", 734 .parent_data = gcc_parent_data_0, 735 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 736 .ops = &clk_rcg2_ops, 737 }; 738 739 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 740 .cmd_rcgr = 0x2788c, 741 .mnd_width = 16, 742 .hid_width = 5, 743 .parent_map = gcc_parent_map_0, 744 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 745 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 746 }; 747 748 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 749 .name = "gcc_qupv3_wrap0_s7_clk_src", 750 .parent_data = gcc_parent_data_0, 751 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 752 .ops = &clk_rcg2_ops, 753 }; 754 755 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 756 .cmd_rcgr = 0x279c0, 757 .mnd_width = 16, 758 .hid_width = 5, 759 .parent_map = gcc_parent_map_0, 760 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 761 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 762 }; 763 764 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 765 .name = "gcc_qupv3_wrap1_s0_clk_src", 766 .parent_data = gcc_parent_data_0, 767 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 768 .ops = &clk_rcg2_ops, 769 }; 770 771 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 772 .cmd_rcgr = 0x28154, 773 .mnd_width = 16, 774 .hid_width = 5, 775 .parent_map = gcc_parent_map_0, 776 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 777 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 778 }; 779 780 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 781 .name = "gcc_qupv3_wrap1_s1_clk_src", 782 .parent_data = gcc_parent_data_0, 783 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 784 .ops = &clk_rcg2_ops, 785 }; 786 787 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 788 .cmd_rcgr = 0x28288, 789 .mnd_width = 16, 790 .hid_width = 5, 791 .parent_map = gcc_parent_map_0, 792 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 793 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 794 }; 795 796 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 797 .name = "gcc_qupv3_wrap1_s2_clk_src", 798 .parent_data = gcc_parent_data_0, 799 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 800 .ops = &clk_rcg2_ops, 801 }; 802 803 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 804 .cmd_rcgr = 0x283bc, 805 .mnd_width = 16, 806 .hid_width = 5, 807 .parent_map = gcc_parent_map_0, 808 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 809 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 810 }; 811 812 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 813 .name = "gcc_qupv3_wrap1_s3_clk_src", 814 .parent_data = gcc_parent_data_0, 815 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 816 .ops = &clk_rcg2_ops, 817 }; 818 819 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 820 .cmd_rcgr = 0x284f0, 821 .mnd_width = 16, 822 .hid_width = 5, 823 .parent_map = gcc_parent_map_0, 824 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 825 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 826 }; 827 828 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 829 .name = "gcc_qupv3_wrap1_s4_clk_src", 830 .parent_data = gcc_parent_data_0, 831 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 832 .ops = &clk_rcg2_ops, 833 }; 834 835 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 836 .cmd_rcgr = 0x28624, 837 .mnd_width = 16, 838 .hid_width = 5, 839 .parent_map = gcc_parent_map_0, 840 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 841 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 842 }; 843 844 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 845 .name = "gcc_qupv3_wrap1_s5_clk_src", 846 .parent_data = gcc_parent_data_0, 847 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 848 .ops = &clk_rcg2_ops, 849 }; 850 851 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 852 .cmd_rcgr = 0x28758, 853 .mnd_width = 16, 854 .hid_width = 5, 855 .parent_map = gcc_parent_map_0, 856 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 857 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 858 }; 859 860 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 861 .name = "gcc_qupv3_wrap1_s6_clk_src", 862 .parent_data = gcc_parent_data_0, 863 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 864 .ops = &clk_rcg2_ops, 865 }; 866 867 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 868 .cmd_rcgr = 0x2888c, 869 .mnd_width = 16, 870 .hid_width = 5, 871 .parent_map = gcc_parent_map_0, 872 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 873 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 874 }; 875 876 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 877 .name = "gcc_qupv3_wrap1_s7_clk_src", 878 .parent_data = gcc_parent_data_0, 879 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 880 .ops = &clk_rcg2_ops, 881 }; 882 883 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 884 .cmd_rcgr = 0x289c0, 885 .mnd_width = 16, 886 .hid_width = 5, 887 .parent_map = gcc_parent_map_0, 888 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 889 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 890 }; 891 892 static const struct freq_tbl ftbl_gcc_sdcc5_apps_clk_src[] = { 893 F(144000, P_BI_TCXO, 16, 3, 25), 894 F(400000, P_BI_TCXO, 12, 1, 4), 895 F(19200000, P_BI_TCXO, 1, 0, 0), 896 F(20000000, P_GCC_GPLL0_OUT_MAIN, 10, 1, 3), 897 F(25000000, P_GCC_GPLL0_OUT_MAIN, 12, 1, 2), 898 F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0), 899 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 900 F(192000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0), 901 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 902 F(384000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0), 903 { } 904 }; 905 906 static struct clk_rcg2 gcc_sdcc5_apps_clk_src = { 907 .cmd_rcgr = 0x3b034, 908 .mnd_width = 8, 909 .hid_width = 5, 910 .parent_map = gcc_parent_map_8, 911 .freq_tbl = ftbl_gcc_sdcc5_apps_clk_src, 912 .clkr.hw.init = &(const struct clk_init_data) { 913 .name = "gcc_sdcc5_apps_clk_src", 914 .parent_data = gcc_parent_data_8, 915 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 916 .ops = &clk_rcg2_ops, 917 }, 918 }; 919 920 static const struct freq_tbl ftbl_gcc_sdcc5_ice_core_clk_src[] = { 921 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 922 { } 923 }; 924 925 static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src = { 926 .cmd_rcgr = 0x3b01c, 927 .mnd_width = 0, 928 .hid_width = 5, 929 .parent_map = gcc_parent_map_2, 930 .freq_tbl = ftbl_gcc_sdcc5_ice_core_clk_src, 931 .clkr.hw.init = &(const struct clk_init_data) { 932 .name = "gcc_sdcc5_ice_core_clk_src", 933 .parent_data = gcc_parent_data_2, 934 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 935 .ops = &clk_rcg2_ops, 936 }, 937 }; 938 939 static struct clk_rcg2 gcc_sm_bus_xo_clk_src = { 940 .cmd_rcgr = 0x5b00c, 941 .mnd_width = 0, 942 .hid_width = 5, 943 .parent_map = gcc_parent_map_2, 944 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 945 .clkr.hw.init = &(const struct clk_init_data) { 946 .name = "gcc_sm_bus_xo_clk_src", 947 .parent_data = gcc_parent_data_2, 948 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 949 .ops = &clk_rcg2_ops, 950 }, 951 }; 952 953 static const struct freq_tbl ftbl_gcc_tsc_clk_src[] = { 954 F(500000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0), 955 { } 956 }; 957 958 static struct clk_rcg2 gcc_tsc_clk_src = { 959 .cmd_rcgr = 0x57010, 960 .mnd_width = 0, 961 .hid_width = 5, 962 .parent_map = gcc_parent_map_9, 963 .freq_tbl = ftbl_gcc_tsc_clk_src, 964 .clkr.hw.init = &(const struct clk_init_data) { 965 .name = "gcc_tsc_clk_src", 966 .parent_data = gcc_parent_data_9, 967 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 968 .ops = &clk_rcg2_ops, 969 }, 970 }; 971 972 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 973 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 974 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 975 { } 976 }; 977 978 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 979 .cmd_rcgr = 0x49028, 980 .mnd_width = 8, 981 .hid_width = 5, 982 .parent_map = gcc_parent_map_0, 983 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 984 .clkr.hw.init = &(const struct clk_init_data) { 985 .name = "gcc_usb30_prim_master_clk_src", 986 .parent_data = gcc_parent_data_0, 987 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 988 .ops = &clk_rcg2_ops, 989 }, 990 }; 991 992 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 993 .cmd_rcgr = 0x49044, 994 .mnd_width = 0, 995 .hid_width = 5, 996 .parent_map = gcc_parent_map_0, 997 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 998 .clkr.hw.init = &(const struct clk_init_data) { 999 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1000 .parent_data = gcc_parent_data_0, 1001 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1002 .ops = &clk_rcg2_ops, 1003 }, 1004 }; 1005 1006 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1007 .cmd_rcgr = 0x49070, 1008 .mnd_width = 0, 1009 .hid_width = 5, 1010 .parent_map = gcc_parent_map_3, 1011 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1012 .clkr.hw.init = &(const struct clk_init_data) { 1013 .name = "gcc_usb3_prim_phy_aux_clk_src", 1014 .parent_data = gcc_parent_data_3, 1015 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1016 .ops = &clk_rcg2_ops, 1017 }, 1018 }; 1019 1020 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1021 .reg = 0x4905c, 1022 .shift = 0, 1023 .width = 4, 1024 .clkr.hw.init = &(const struct clk_init_data) { 1025 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1026 .parent_hws = (const struct clk_hw*[]) { 1027 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1028 }, 1029 .num_parents = 1, 1030 .flags = CLK_SET_RATE_PARENT, 1031 .ops = &clk_regmap_div_ro_ops, 1032 }, 1033 }; 1034 1035 static struct clk_branch gcc_aggre_noc_ecpri_dma_clk = { 1036 .halt_reg = 0x92008, 1037 .halt_check = BRANCH_HALT_VOTED, 1038 .hwcg_reg = 0x92008, 1039 .hwcg_bit = 1, 1040 .clkr = { 1041 .enable_reg = 0x92008, 1042 .enable_mask = BIT(0), 1043 .hw.init = &(const struct clk_init_data) { 1044 .name = "gcc_aggre_noc_ecpri_dma_clk", 1045 .parent_hws = (const struct clk_hw*[]) { 1046 &gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw, 1047 }, 1048 .num_parents = 1, 1049 .flags = CLK_SET_RATE_PARENT, 1050 .ops = &clk_branch2_ops, 1051 }, 1052 }, 1053 }; 1054 1055 static struct clk_branch gcc_aggre_noc_ecpri_gsi_clk = { 1056 .halt_reg = 0x9201c, 1057 .halt_check = BRANCH_HALT_VOTED, 1058 .hwcg_reg = 0x9201c, 1059 .hwcg_bit = 1, 1060 .clkr = { 1061 .enable_reg = 0x9201c, 1062 .enable_mask = BIT(0), 1063 .hw.init = &(const struct clk_init_data) { 1064 .name = "gcc_aggre_noc_ecpri_gsi_clk", 1065 .parent_hws = (const struct clk_hw*[]) { 1066 &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, 1067 }, 1068 .num_parents = 1, 1069 .flags = CLK_SET_RATE_PARENT, 1070 .ops = &clk_branch2_ops, 1071 }, 1072 }, 1073 }; 1074 1075 static struct clk_branch gcc_boot_rom_ahb_clk = { 1076 .halt_reg = 0x48004, 1077 .halt_check = BRANCH_HALT_VOTED, 1078 .hwcg_reg = 0x48004, 1079 .hwcg_bit = 1, 1080 .clkr = { 1081 .enable_reg = 0x62000, 1082 .enable_mask = BIT(10), 1083 .hw.init = &(const struct clk_init_data) { 1084 .name = "gcc_boot_rom_ahb_clk", 1085 .ops = &clk_branch2_ops, 1086 }, 1087 }, 1088 }; 1089 1090 static struct clk_branch gcc_cfg_noc_ecpri_cc_ahb_clk = { 1091 .halt_reg = 0x3e004, 1092 .halt_check = BRANCH_HALT_VOTED, 1093 .hwcg_reg = 0x3e004, 1094 .hwcg_bit = 1, 1095 .clkr = { 1096 .enable_reg = 0x3e004, 1097 .enable_mask = BIT(0), 1098 .hw.init = &(const struct clk_init_data) { 1099 .name = "gcc_cfg_noc_ecpri_cc_ahb_clk", 1100 .ops = &clk_branch2_ops, 1101 }, 1102 }, 1103 }; 1104 1105 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1106 .halt_reg = 0x8401c, 1107 .halt_check = BRANCH_HALT_VOTED, 1108 .hwcg_reg = 0x8401c, 1109 .hwcg_bit = 1, 1110 .clkr = { 1111 .enable_reg = 0x8401c, 1112 .enable_mask = BIT(0), 1113 .hw.init = &(const struct clk_init_data) { 1114 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1115 .parent_hws = (const struct clk_hw*[]) { 1116 &gcc_usb30_prim_master_clk_src.clkr.hw, 1117 }, 1118 .num_parents = 1, 1119 .flags = CLK_SET_RATE_PARENT, 1120 .ops = &clk_branch2_ops, 1121 }, 1122 }, 1123 }; 1124 1125 static struct clk_branch gcc_ddrss_ecpri_dma_clk = { 1126 .halt_reg = 0x54030, 1127 .halt_check = BRANCH_HALT_VOTED, 1128 .hwcg_reg = 0x54030, 1129 .hwcg_bit = 1, 1130 .clkr = { 1131 .enable_reg = 0x54030, 1132 .enable_mask = BIT(0), 1133 .hw.init = &(const struct clk_init_data) { 1134 .name = "gcc_ddrss_ecpri_dma_clk", 1135 .parent_hws = (const struct clk_hw*[]) { 1136 &gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw, 1137 }, 1138 .num_parents = 1, 1139 .flags = CLK_SET_RATE_PARENT, 1140 .ops = &clk_branch2_aon_ops, 1141 }, 1142 }, 1143 }; 1144 1145 static struct clk_branch gcc_ecpri_ahb_clk = { 1146 .halt_reg = 0x3a008, 1147 .halt_check = BRANCH_HALT_VOTED, 1148 .hwcg_reg = 0x3a008, 1149 .hwcg_bit = 1, 1150 .clkr = { 1151 .enable_reg = 0x3a008, 1152 .enable_mask = BIT(0), 1153 .hw.init = &(const struct clk_init_data) { 1154 .name = "gcc_ecpri_ahb_clk", 1155 .ops = &clk_branch2_ops, 1156 }, 1157 }, 1158 }; 1159 1160 static struct clk_branch gcc_ecpri_cc_gpll0_clk_src = { 1161 .halt_check = BRANCH_HALT_DELAY, 1162 .clkr = { 1163 .enable_reg = 0x62010, 1164 .enable_mask = BIT(0), 1165 .hw.init = &(const struct clk_init_data) { 1166 .name = "gcc_ecpri_cc_gpll0_clk_src", 1167 .parent_hws = (const struct clk_hw*[]) { 1168 &gcc_gpll0.clkr.hw, 1169 }, 1170 .num_parents = 1, 1171 .flags = CLK_SET_RATE_PARENT, 1172 .ops = &clk_branch2_ops, 1173 }, 1174 }, 1175 }; 1176 1177 static struct clk_branch gcc_ecpri_cc_gpll1_even_clk_src = { 1178 .halt_check = BRANCH_HALT_DELAY, 1179 .clkr = { 1180 .enable_reg = 0x62010, 1181 .enable_mask = BIT(1), 1182 .hw.init = &(const struct clk_init_data) { 1183 .name = "gcc_ecpri_cc_gpll1_even_clk_src", 1184 .parent_hws = (const struct clk_hw*[]) { 1185 &gcc_gpll1_out_even.clkr.hw, 1186 }, 1187 .num_parents = 1, 1188 .flags = CLK_SET_RATE_PARENT, 1189 .ops = &clk_branch2_ops, 1190 }, 1191 }, 1192 }; 1193 1194 static struct clk_branch gcc_ecpri_cc_gpll2_even_clk_src = { 1195 .halt_check = BRANCH_HALT_DELAY, 1196 .clkr = { 1197 .enable_reg = 0x62010, 1198 .enable_mask = BIT(2), 1199 .hw.init = &(const struct clk_init_data) { 1200 .name = "gcc_ecpri_cc_gpll2_even_clk_src", 1201 .parent_hws = (const struct clk_hw*[]) { 1202 &gcc_gpll2_out_even.clkr.hw, 1203 }, 1204 .num_parents = 1, 1205 .flags = CLK_SET_RATE_PARENT, 1206 .ops = &clk_branch2_ops, 1207 }, 1208 }, 1209 }; 1210 1211 static struct clk_branch gcc_ecpri_cc_gpll3_clk_src = { 1212 .halt_check = BRANCH_HALT_DELAY, 1213 .clkr = { 1214 .enable_reg = 0x62010, 1215 .enable_mask = BIT(3), 1216 .hw.init = &(const struct clk_init_data) { 1217 .name = "gcc_ecpri_cc_gpll3_clk_src", 1218 .parent_hws = (const struct clk_hw*[]) { 1219 &gcc_gpll3.clkr.hw, 1220 }, 1221 .num_parents = 1, 1222 .flags = CLK_SET_RATE_PARENT, 1223 .ops = &clk_branch2_ops, 1224 }, 1225 }, 1226 }; 1227 1228 static struct clk_branch gcc_ecpri_cc_gpll4_clk_src = { 1229 .halt_check = BRANCH_HALT_DELAY, 1230 .clkr = { 1231 .enable_reg = 0x62010, 1232 .enable_mask = BIT(4), 1233 .hw.init = &(const struct clk_init_data) { 1234 .name = "gcc_ecpri_cc_gpll4_clk_src", 1235 .parent_hws = (const struct clk_hw*[]) { 1236 &gcc_gpll4.clkr.hw, 1237 }, 1238 .num_parents = 1, 1239 .flags = CLK_SET_RATE_PARENT, 1240 .ops = &clk_branch2_ops, 1241 }, 1242 }, 1243 }; 1244 1245 static struct clk_branch gcc_ecpri_cc_gpll5_even_clk_src = { 1246 .halt_check = BRANCH_HALT_DELAY, 1247 .clkr = { 1248 .enable_reg = 0x62010, 1249 .enable_mask = BIT(5), 1250 .hw.init = &(const struct clk_init_data) { 1251 .name = "gcc_ecpri_cc_gpll5_even_clk_src", 1252 .parent_hws = (const struct clk_hw*[]) { 1253 &gcc_gpll5_out_even.clkr.hw, 1254 }, 1255 .num_parents = 1, 1256 .flags = CLK_SET_RATE_PARENT, 1257 .ops = &clk_branch2_ops, 1258 }, 1259 }, 1260 }; 1261 1262 static struct clk_branch gcc_ecpri_xo_clk = { 1263 .halt_reg = 0x3a004, 1264 .halt_check = BRANCH_HALT, 1265 .clkr = { 1266 .enable_reg = 0x3a004, 1267 .enable_mask = BIT(0), 1268 .hw.init = &(const struct clk_init_data) { 1269 .name = "gcc_ecpri_xo_clk", 1270 .ops = &clk_branch2_ops, 1271 }, 1272 }, 1273 }; 1274 1275 static struct clk_branch gcc_eth_100g_c2c_hm_apb_clk = { 1276 .halt_reg = 0x39010, 1277 .halt_check = BRANCH_HALT, 1278 .clkr = { 1279 .enable_reg = 0x39010, 1280 .enable_mask = BIT(0), 1281 .hw.init = &(const struct clk_init_data) { 1282 .name = "gcc_eth_100g_c2c_hm_apb_clk", 1283 .ops = &clk_branch2_ops, 1284 }, 1285 }, 1286 }; 1287 1288 static struct clk_branch gcc_eth_100g_fh_hm_apb_0_clk = { 1289 .halt_reg = 0x39004, 1290 .halt_check = BRANCH_HALT, 1291 .clkr = { 1292 .enable_reg = 0x39004, 1293 .enable_mask = BIT(0), 1294 .hw.init = &(const struct clk_init_data) { 1295 .name = "gcc_eth_100g_fh_hm_apb_0_clk", 1296 .ops = &clk_branch2_ops, 1297 }, 1298 }, 1299 }; 1300 1301 static struct clk_branch gcc_eth_100g_fh_hm_apb_1_clk = { 1302 .halt_reg = 0x39008, 1303 .halt_check = BRANCH_HALT, 1304 .clkr = { 1305 .enable_reg = 0x39008, 1306 .enable_mask = BIT(0), 1307 .hw.init = &(const struct clk_init_data) { 1308 .name = "gcc_eth_100g_fh_hm_apb_1_clk", 1309 .ops = &clk_branch2_ops, 1310 }, 1311 }, 1312 }; 1313 1314 static struct clk_branch gcc_eth_100g_fh_hm_apb_2_clk = { 1315 .halt_reg = 0x3900c, 1316 .halt_check = BRANCH_HALT, 1317 .clkr = { 1318 .enable_reg = 0x3900c, 1319 .enable_mask = BIT(0), 1320 .hw.init = &(const struct clk_init_data) { 1321 .name = "gcc_eth_100g_fh_hm_apb_2_clk", 1322 .ops = &clk_branch2_ops, 1323 }, 1324 }, 1325 }; 1326 1327 static struct clk_branch gcc_eth_dbg_c2c_hm_apb_clk = { 1328 .halt_reg = 0x39014, 1329 .halt_check = BRANCH_HALT, 1330 .clkr = { 1331 .enable_reg = 0x39014, 1332 .enable_mask = BIT(0), 1333 .hw.init = &(const struct clk_init_data) { 1334 .name = "gcc_eth_dbg_c2c_hm_apb_clk", 1335 .ops = &clk_branch2_ops, 1336 }, 1337 }, 1338 }; 1339 1340 static struct clk_branch gcc_eth_dbg_snoc_axi_clk = { 1341 .halt_reg = 0x3901c, 1342 .halt_check = BRANCH_HALT_VOTED, 1343 .hwcg_reg = 0x3901c, 1344 .hwcg_bit = 1, 1345 .clkr = { 1346 .enable_reg = 0x3901c, 1347 .enable_mask = BIT(0), 1348 .hw.init = &(const struct clk_init_data) { 1349 .name = "gcc_eth_dbg_snoc_axi_clk", 1350 .ops = &clk_branch2_ops, 1351 }, 1352 }, 1353 }; 1354 1355 static struct clk_branch gcc_gemnoc_pcie_qx_clk = { 1356 .halt_reg = 0x5402c, 1357 .halt_check = BRANCH_HALT_VOTED, 1358 .hwcg_reg = 0x5402c, 1359 .hwcg_bit = 1, 1360 .clkr = { 1361 .enable_reg = 0x62008, 1362 .enable_mask = BIT(0), 1363 .hw.init = &(const struct clk_init_data) { 1364 .name = "gcc_gemnoc_pcie_qx_clk", 1365 .ops = &clk_branch2_aon_ops, 1366 }, 1367 }, 1368 }; 1369 1370 static struct clk_branch gcc_gp1_clk = { 1371 .halt_reg = 0x74000, 1372 .halt_check = BRANCH_HALT, 1373 .clkr = { 1374 .enable_reg = 0x74000, 1375 .enable_mask = BIT(0), 1376 .hw.init = &(const struct clk_init_data) { 1377 .name = "gcc_gp1_clk", 1378 .parent_hws = (const struct clk_hw*[]) { 1379 &gcc_gp1_clk_src.clkr.hw, 1380 }, 1381 .num_parents = 1, 1382 .flags = CLK_SET_RATE_PARENT, 1383 .ops = &clk_branch2_ops, 1384 }, 1385 }, 1386 }; 1387 1388 static struct clk_branch gcc_gp2_clk = { 1389 .halt_reg = 0x75000, 1390 .halt_check = BRANCH_HALT, 1391 .clkr = { 1392 .enable_reg = 0x75000, 1393 .enable_mask = BIT(0), 1394 .hw.init = &(const struct clk_init_data) { 1395 .name = "gcc_gp2_clk", 1396 .parent_hws = (const struct clk_hw*[]) { 1397 &gcc_gp2_clk_src.clkr.hw, 1398 }, 1399 .num_parents = 1, 1400 .flags = CLK_SET_RATE_PARENT, 1401 .ops = &clk_branch2_ops, 1402 }, 1403 }, 1404 }; 1405 1406 static struct clk_branch gcc_gp3_clk = { 1407 .halt_reg = 0x76000, 1408 .halt_check = BRANCH_HALT, 1409 .clkr = { 1410 .enable_reg = 0x76000, 1411 .enable_mask = BIT(0), 1412 .hw.init = &(const struct clk_init_data) { 1413 .name = "gcc_gp3_clk", 1414 .parent_hws = (const struct clk_hw*[]) { 1415 &gcc_gp3_clk_src.clkr.hw, 1416 }, 1417 .num_parents = 1, 1418 .flags = CLK_SET_RATE_PARENT, 1419 .ops = &clk_branch2_ops, 1420 }, 1421 }, 1422 }; 1423 1424 static struct clk_branch gcc_pcie_0_aux_clk = { 1425 .halt_reg = 0x9d030, 1426 .halt_check = BRANCH_HALT_VOTED, 1427 .hwcg_reg = 0x9d030, 1428 .hwcg_bit = 1, 1429 .clkr = { 1430 .enable_reg = 0x62000, 1431 .enable_mask = BIT(29), 1432 .hw.init = &(const struct clk_init_data) { 1433 .name = "gcc_pcie_0_aux_clk", 1434 .parent_hws = (const struct clk_hw*[]) { 1435 &gcc_pcie_0_aux_clk_src.clkr.hw, 1436 }, 1437 .num_parents = 1, 1438 .flags = CLK_SET_RATE_PARENT, 1439 .ops = &clk_branch2_ops, 1440 }, 1441 }, 1442 }; 1443 1444 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1445 .halt_reg = 0x9d02c, 1446 .halt_check = BRANCH_HALT_VOTED, 1447 .hwcg_reg = 0x9d02c, 1448 .hwcg_bit = 1, 1449 .clkr = { 1450 .enable_reg = 0x62000, 1451 .enable_mask = BIT(28), 1452 .hw.init = &(const struct clk_init_data) { 1453 .name = "gcc_pcie_0_cfg_ahb_clk", 1454 .ops = &clk_branch2_ops, 1455 }, 1456 }, 1457 }; 1458 1459 static struct clk_branch gcc_pcie_0_clkref_en = { 1460 .halt_reg = 0x9c004, 1461 .halt_bit = 31, 1462 .halt_check = BRANCH_HALT_ENABLE, 1463 .clkr = { 1464 .enable_reg = 0x9c004, 1465 .enable_mask = BIT(0), 1466 .hw.init = &(const struct clk_init_data) { 1467 .name = "gcc_pcie_0_clkref_en", 1468 .ops = &clk_branch_ops, 1469 }, 1470 }, 1471 }; 1472 1473 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1474 .halt_reg = 0x9d024, 1475 .halt_check = BRANCH_HALT_SKIP, 1476 .hwcg_reg = 0x9d024, 1477 .hwcg_bit = 1, 1478 .clkr = { 1479 .enable_reg = 0x62000, 1480 .enable_mask = BIT(27), 1481 .hw.init = &(const struct clk_init_data) { 1482 .name = "gcc_pcie_0_mstr_axi_clk", 1483 .ops = &clk_branch2_ops, 1484 }, 1485 }, 1486 }; 1487 1488 static struct clk_branch gcc_pcie_0_phy_aux_clk = { 1489 .halt_reg = 0x9d038, 1490 .halt_check = BRANCH_HALT_VOTED, 1491 .hwcg_reg = 0x9d038, 1492 .hwcg_bit = 1, 1493 .clkr = { 1494 .enable_reg = 0x62000, 1495 .enable_mask = BIT(24), 1496 .hw.init = &(const struct clk_init_data) { 1497 .name = "gcc_pcie_0_phy_aux_clk", 1498 .parent_hws = (const struct clk_hw*[]) { 1499 &gcc_pcie_0_phy_aux_clk_src.clkr.hw, 1500 }, 1501 .num_parents = 1, 1502 .flags = CLK_SET_RATE_PARENT, 1503 .ops = &clk_branch2_ops, 1504 }, 1505 }, 1506 }; 1507 1508 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 1509 .halt_reg = 0x9d048, 1510 .halt_check = BRANCH_HALT_VOTED, 1511 .hwcg_reg = 0x9d048, 1512 .hwcg_bit = 1, 1513 .clkr = { 1514 .enable_reg = 0x62000, 1515 .enable_mask = BIT(23), 1516 .hw.init = &(const struct clk_init_data) { 1517 .name = "gcc_pcie_0_phy_rchng_clk", 1518 .parent_hws = (const struct clk_hw*[]) { 1519 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1520 }, 1521 .num_parents = 1, 1522 .flags = CLK_SET_RATE_PARENT, 1523 .ops = &clk_branch2_ops, 1524 }, 1525 }, 1526 }; 1527 1528 static struct clk_branch gcc_pcie_0_pipe_clk = { 1529 .halt_reg = 0x9d040, 1530 .halt_check = BRANCH_HALT_VOTED, 1531 .hwcg_reg = 0x9d040, 1532 .hwcg_bit = 1, 1533 .clkr = { 1534 .enable_reg = 0x62000, 1535 .enable_mask = BIT(30), 1536 .hw.init = &(const struct clk_init_data) { 1537 .name = "gcc_pcie_0_pipe_clk", 1538 .parent_hws = (const struct clk_hw*[]) { 1539 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1540 }, 1541 .num_parents = 1, 1542 .flags = CLK_SET_RATE_PARENT, 1543 .ops = &clk_branch2_ops, 1544 }, 1545 }, 1546 }; 1547 1548 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1549 .halt_reg = 0x9d01c, 1550 .halt_check = BRANCH_HALT_VOTED, 1551 .hwcg_reg = 0x9d01c, 1552 .hwcg_bit = 1, 1553 .clkr = { 1554 .enable_reg = 0x62000, 1555 .enable_mask = BIT(26), 1556 .hw.init = &(const struct clk_init_data) { 1557 .name = "gcc_pcie_0_slv_axi_clk", 1558 .ops = &clk_branch2_ops, 1559 }, 1560 }, 1561 }; 1562 1563 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1564 .halt_reg = 0x9d018, 1565 .halt_check = BRANCH_HALT_VOTED, 1566 .hwcg_reg = 0x9d018, 1567 .hwcg_bit = 1, 1568 .clkr = { 1569 .enable_reg = 0x62000, 1570 .enable_mask = BIT(25), 1571 .hw.init = &(const struct clk_init_data) { 1572 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1573 .ops = &clk_branch2_ops, 1574 }, 1575 }, 1576 }; 1577 1578 static struct clk_branch gcc_pdm2_clk = { 1579 .halt_reg = 0x4300c, 1580 .halt_check = BRANCH_HALT, 1581 .clkr = { 1582 .enable_reg = 0x4300c, 1583 .enable_mask = BIT(0), 1584 .hw.init = &(const struct clk_init_data) { 1585 .name = "gcc_pdm2_clk", 1586 .parent_hws = (const struct clk_hw*[]) { 1587 &gcc_pdm2_clk_src.clkr.hw, 1588 }, 1589 .num_parents = 1, 1590 .flags = CLK_SET_RATE_PARENT, 1591 .ops = &clk_branch2_ops, 1592 }, 1593 }, 1594 }; 1595 1596 static struct clk_branch gcc_pdm_ahb_clk = { 1597 .halt_reg = 0x43004, 1598 .halt_check = BRANCH_HALT_VOTED, 1599 .hwcg_reg = 0x43004, 1600 .hwcg_bit = 1, 1601 .clkr = { 1602 .enable_reg = 0x43004, 1603 .enable_mask = BIT(0), 1604 .hw.init = &(const struct clk_init_data) { 1605 .name = "gcc_pdm_ahb_clk", 1606 .ops = &clk_branch2_ops, 1607 }, 1608 }, 1609 }; 1610 1611 static struct clk_branch gcc_pdm_xo4_clk = { 1612 .halt_reg = 0x43008, 1613 .halt_check = BRANCH_HALT, 1614 .clkr = { 1615 .enable_reg = 0x43008, 1616 .enable_mask = BIT(0), 1617 .hw.init = &(const struct clk_init_data) { 1618 .name = "gcc_pdm_xo4_clk", 1619 .ops = &clk_branch2_ops, 1620 }, 1621 }, 1622 }; 1623 1624 static struct clk_branch gcc_qmip_anoc_pcie_clk = { 1625 .halt_reg = 0x84044, 1626 .halt_check = BRANCH_HALT_VOTED, 1627 .hwcg_reg = 0x84044, 1628 .hwcg_bit = 1, 1629 .clkr = { 1630 .enable_reg = 0x84044, 1631 .enable_mask = BIT(0), 1632 .hw.init = &(const struct clk_init_data) { 1633 .name = "gcc_qmip_anoc_pcie_clk", 1634 .ops = &clk_branch2_ops, 1635 }, 1636 }, 1637 }; 1638 1639 static struct clk_branch gcc_qmip_ecpri_dma0_clk = { 1640 .halt_reg = 0x84038, 1641 .halt_check = BRANCH_HALT_VOTED, 1642 .hwcg_reg = 0x84038, 1643 .hwcg_bit = 1, 1644 .clkr = { 1645 .enable_reg = 0x84038, 1646 .enable_mask = BIT(0), 1647 .hw.init = &(const struct clk_init_data) { 1648 .name = "gcc_qmip_ecpri_dma0_clk", 1649 .ops = &clk_branch2_ops, 1650 }, 1651 }, 1652 }; 1653 1654 static struct clk_branch gcc_qmip_ecpri_dma1_clk = { 1655 .halt_reg = 0x8403c, 1656 .halt_check = BRANCH_HALT_VOTED, 1657 .hwcg_reg = 0x8403c, 1658 .hwcg_bit = 1, 1659 .clkr = { 1660 .enable_reg = 0x8403c, 1661 .enable_mask = BIT(0), 1662 .hw.init = &(const struct clk_init_data) { 1663 .name = "gcc_qmip_ecpri_dma1_clk", 1664 .ops = &clk_branch2_ops, 1665 }, 1666 }, 1667 }; 1668 1669 static struct clk_branch gcc_qmip_ecpri_gsi_clk = { 1670 .halt_reg = 0x84040, 1671 .halt_check = BRANCH_HALT_VOTED, 1672 .hwcg_reg = 0x84040, 1673 .hwcg_bit = 1, 1674 .clkr = { 1675 .enable_reg = 0x84040, 1676 .enable_mask = BIT(0), 1677 .hw.init = &(const struct clk_init_data) { 1678 .name = "gcc_qmip_ecpri_gsi_clk", 1679 .ops = &clk_branch2_ops, 1680 }, 1681 }, 1682 }; 1683 1684 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 1685 .halt_reg = 0x27018, 1686 .halt_check = BRANCH_HALT_VOTED, 1687 .clkr = { 1688 .enable_reg = 0x62008, 1689 .enable_mask = BIT(9), 1690 .hw.init = &(const struct clk_init_data) { 1691 .name = "gcc_qupv3_wrap0_core_2x_clk", 1692 .ops = &clk_branch2_ops, 1693 }, 1694 }, 1695 }; 1696 1697 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 1698 .halt_reg = 0x2700c, 1699 .halt_check = BRANCH_HALT_VOTED, 1700 .clkr = { 1701 .enable_reg = 0x62008, 1702 .enable_mask = BIT(8), 1703 .hw.init = &(const struct clk_init_data) { 1704 .name = "gcc_qupv3_wrap0_core_clk", 1705 .ops = &clk_branch2_ops, 1706 }, 1707 }, 1708 }; 1709 1710 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 1711 .halt_reg = 0x2714c, 1712 .halt_check = BRANCH_HALT_VOTED, 1713 .clkr = { 1714 .enable_reg = 0x62008, 1715 .enable_mask = BIT(10), 1716 .hw.init = &(const struct clk_init_data) { 1717 .name = "gcc_qupv3_wrap0_s0_clk", 1718 .parent_hws = (const struct clk_hw*[]) { 1719 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 1720 }, 1721 .num_parents = 1, 1722 .flags = CLK_SET_RATE_PARENT, 1723 .ops = &clk_branch2_ops, 1724 }, 1725 }, 1726 }; 1727 1728 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 1729 .halt_reg = 0x27280, 1730 .halt_check = BRANCH_HALT_VOTED, 1731 .clkr = { 1732 .enable_reg = 0x62008, 1733 .enable_mask = BIT(11), 1734 .hw.init = &(const struct clk_init_data) { 1735 .name = "gcc_qupv3_wrap0_s1_clk", 1736 .parent_hws = (const struct clk_hw*[]) { 1737 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 1738 }, 1739 .num_parents = 1, 1740 .flags = CLK_SET_RATE_PARENT, 1741 .ops = &clk_branch2_ops, 1742 }, 1743 }, 1744 }; 1745 1746 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 1747 .halt_reg = 0x273b4, 1748 .halt_check = BRANCH_HALT_VOTED, 1749 .clkr = { 1750 .enable_reg = 0x62008, 1751 .enable_mask = BIT(12), 1752 .hw.init = &(const struct clk_init_data) { 1753 .name = "gcc_qupv3_wrap0_s2_clk", 1754 .parent_hws = (const struct clk_hw*[]) { 1755 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 1756 }, 1757 .num_parents = 1, 1758 .flags = CLK_SET_RATE_PARENT, 1759 .ops = &clk_branch2_ops, 1760 }, 1761 }, 1762 }; 1763 1764 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 1765 .halt_reg = 0x274e8, 1766 .halt_check = BRANCH_HALT_VOTED, 1767 .clkr = { 1768 .enable_reg = 0x62008, 1769 .enable_mask = BIT(13), 1770 .hw.init = &(const struct clk_init_data) { 1771 .name = "gcc_qupv3_wrap0_s3_clk", 1772 .parent_hws = (const struct clk_hw*[]) { 1773 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 1774 }, 1775 .num_parents = 1, 1776 .flags = CLK_SET_RATE_PARENT, 1777 .ops = &clk_branch2_ops, 1778 }, 1779 }, 1780 }; 1781 1782 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 1783 .halt_reg = 0x2761c, 1784 .halt_check = BRANCH_HALT_VOTED, 1785 .clkr = { 1786 .enable_reg = 0x62008, 1787 .enable_mask = BIT(14), 1788 .hw.init = &(const struct clk_init_data) { 1789 .name = "gcc_qupv3_wrap0_s4_clk", 1790 .parent_hws = (const struct clk_hw*[]) { 1791 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 1792 }, 1793 .num_parents = 1, 1794 .flags = CLK_SET_RATE_PARENT, 1795 .ops = &clk_branch2_ops, 1796 }, 1797 }, 1798 }; 1799 1800 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 1801 .halt_reg = 0x27750, 1802 .halt_check = BRANCH_HALT_VOTED, 1803 .clkr = { 1804 .enable_reg = 0x62008, 1805 .enable_mask = BIT(15), 1806 .hw.init = &(const struct clk_init_data) { 1807 .name = "gcc_qupv3_wrap0_s5_clk", 1808 .parent_hws = (const struct clk_hw*[]) { 1809 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 1810 }, 1811 .num_parents = 1, 1812 .flags = CLK_SET_RATE_PARENT, 1813 .ops = &clk_branch2_ops, 1814 }, 1815 }, 1816 }; 1817 1818 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 1819 .halt_reg = 0x27884, 1820 .halt_check = BRANCH_HALT_VOTED, 1821 .clkr = { 1822 .enable_reg = 0x62008, 1823 .enable_mask = BIT(16), 1824 .hw.init = &(const struct clk_init_data) { 1825 .name = "gcc_qupv3_wrap0_s6_clk", 1826 .parent_hws = (const struct clk_hw*[]) { 1827 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 1828 }, 1829 .num_parents = 1, 1830 .flags = CLK_SET_RATE_PARENT, 1831 .ops = &clk_branch2_ops, 1832 }, 1833 }, 1834 }; 1835 1836 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 1837 .halt_reg = 0x279b8, 1838 .halt_check = BRANCH_HALT_VOTED, 1839 .clkr = { 1840 .enable_reg = 0x62008, 1841 .enable_mask = BIT(17), 1842 .hw.init = &(const struct clk_init_data) { 1843 .name = "gcc_qupv3_wrap0_s7_clk", 1844 .parent_hws = (const struct clk_hw*[]) { 1845 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 1846 }, 1847 .num_parents = 1, 1848 .flags = CLK_SET_RATE_PARENT, 1849 .ops = &clk_branch2_ops, 1850 }, 1851 }, 1852 }; 1853 1854 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 1855 .halt_reg = 0x28018, 1856 .halt_check = BRANCH_HALT_VOTED, 1857 .clkr = { 1858 .enable_reg = 0x62008, 1859 .enable_mask = BIT(18), 1860 .hw.init = &(const struct clk_init_data) { 1861 .name = "gcc_qupv3_wrap1_core_2x_clk", 1862 .ops = &clk_branch2_ops, 1863 }, 1864 }, 1865 }; 1866 1867 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 1868 .halt_reg = 0x2800c, 1869 .halt_check = BRANCH_HALT_VOTED, 1870 .clkr = { 1871 .enable_reg = 0x62008, 1872 .enable_mask = BIT(19), 1873 .hw.init = &(const struct clk_init_data) { 1874 .name = "gcc_qupv3_wrap1_core_clk", 1875 .ops = &clk_branch2_ops, 1876 }, 1877 }, 1878 }; 1879 1880 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 1881 .halt_reg = 0x2814c, 1882 .halt_check = BRANCH_HALT_VOTED, 1883 .clkr = { 1884 .enable_reg = 0x62008, 1885 .enable_mask = BIT(22), 1886 .hw.init = &(const struct clk_init_data) { 1887 .name = "gcc_qupv3_wrap1_s0_clk", 1888 .parent_hws = (const struct clk_hw*[]) { 1889 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 1890 }, 1891 .num_parents = 1, 1892 .flags = CLK_SET_RATE_PARENT, 1893 .ops = &clk_branch2_ops, 1894 }, 1895 }, 1896 }; 1897 1898 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 1899 .halt_reg = 0x28280, 1900 .halt_check = BRANCH_HALT_VOTED, 1901 .clkr = { 1902 .enable_reg = 0x62008, 1903 .enable_mask = BIT(23), 1904 .hw.init = &(const struct clk_init_data) { 1905 .name = "gcc_qupv3_wrap1_s1_clk", 1906 .parent_hws = (const struct clk_hw*[]) { 1907 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 1908 }, 1909 .num_parents = 1, 1910 .flags = CLK_SET_RATE_PARENT, 1911 .ops = &clk_branch2_ops, 1912 }, 1913 }, 1914 }; 1915 1916 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 1917 .halt_reg = 0x283b4, 1918 .halt_check = BRANCH_HALT_VOTED, 1919 .clkr = { 1920 .enable_reg = 0x62008, 1921 .enable_mask = BIT(24), 1922 .hw.init = &(const struct clk_init_data) { 1923 .name = "gcc_qupv3_wrap1_s2_clk", 1924 .parent_hws = (const struct clk_hw*[]) { 1925 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 1926 }, 1927 .num_parents = 1, 1928 .flags = CLK_SET_RATE_PARENT, 1929 .ops = &clk_branch2_ops, 1930 }, 1931 }, 1932 }; 1933 1934 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 1935 .halt_reg = 0x284e8, 1936 .halt_check = BRANCH_HALT_VOTED, 1937 .clkr = { 1938 .enable_reg = 0x62008, 1939 .enable_mask = BIT(25), 1940 .hw.init = &(const struct clk_init_data) { 1941 .name = "gcc_qupv3_wrap1_s3_clk", 1942 .parent_hws = (const struct clk_hw*[]) { 1943 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 1944 }, 1945 .num_parents = 1, 1946 .flags = CLK_SET_RATE_PARENT, 1947 .ops = &clk_branch2_ops, 1948 }, 1949 }, 1950 }; 1951 1952 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 1953 .halt_reg = 0x2861c, 1954 .halt_check = BRANCH_HALT_VOTED, 1955 .clkr = { 1956 .enable_reg = 0x62008, 1957 .enable_mask = BIT(26), 1958 .hw.init = &(const struct clk_init_data) { 1959 .name = "gcc_qupv3_wrap1_s4_clk", 1960 .parent_hws = (const struct clk_hw*[]) { 1961 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 1962 }, 1963 .num_parents = 1, 1964 .flags = CLK_SET_RATE_PARENT, 1965 .ops = &clk_branch2_ops, 1966 }, 1967 }, 1968 }; 1969 1970 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 1971 .halt_reg = 0x28750, 1972 .halt_check = BRANCH_HALT_VOTED, 1973 .clkr = { 1974 .enable_reg = 0x62008, 1975 .enable_mask = BIT(27), 1976 .hw.init = &(const struct clk_init_data) { 1977 .name = "gcc_qupv3_wrap1_s5_clk", 1978 .parent_hws = (const struct clk_hw*[]) { 1979 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 1980 }, 1981 .num_parents = 1, 1982 .flags = CLK_SET_RATE_PARENT, 1983 .ops = &clk_branch2_ops, 1984 }, 1985 }, 1986 }; 1987 1988 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 1989 .halt_reg = 0x28884, 1990 .halt_check = BRANCH_HALT_VOTED, 1991 .clkr = { 1992 .enable_reg = 0x62008, 1993 .enable_mask = BIT(28), 1994 .hw.init = &(const struct clk_init_data) { 1995 .name = "gcc_qupv3_wrap1_s6_clk", 1996 .parent_hws = (const struct clk_hw*[]) { 1997 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 1998 }, 1999 .num_parents = 1, 2000 .flags = CLK_SET_RATE_PARENT, 2001 .ops = &clk_branch2_ops, 2002 }, 2003 }, 2004 }; 2005 2006 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 2007 .halt_reg = 0x289b8, 2008 .halt_check = BRANCH_HALT_VOTED, 2009 .clkr = { 2010 .enable_reg = 0x62008, 2011 .enable_mask = BIT(29), 2012 .hw.init = &(const struct clk_init_data) { 2013 .name = "gcc_qupv3_wrap1_s7_clk", 2014 .parent_hws = (const struct clk_hw*[]) { 2015 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 2016 }, 2017 .num_parents = 1, 2018 .flags = CLK_SET_RATE_PARENT, 2019 .ops = &clk_branch2_ops, 2020 }, 2021 }, 2022 }; 2023 2024 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2025 .halt_reg = 0x27004, 2026 .halt_check = BRANCH_HALT_VOTED, 2027 .hwcg_reg = 0x27004, 2028 .hwcg_bit = 1, 2029 .clkr = { 2030 .enable_reg = 0x62008, 2031 .enable_mask = BIT(6), 2032 .hw.init = &(const struct clk_init_data) { 2033 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2034 .ops = &clk_branch2_ops, 2035 }, 2036 }, 2037 }; 2038 2039 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2040 .halt_reg = 0x27008, 2041 .halt_check = BRANCH_HALT_VOTED, 2042 .hwcg_reg = 0x27008, 2043 .hwcg_bit = 1, 2044 .clkr = { 2045 .enable_reg = 0x62008, 2046 .enable_mask = BIT(7), 2047 .hw.init = &(const struct clk_init_data) { 2048 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2049 .ops = &clk_branch2_ops, 2050 }, 2051 }, 2052 }; 2053 2054 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2055 .halt_reg = 0x28004, 2056 .halt_check = BRANCH_HALT_VOTED, 2057 .hwcg_reg = 0x28004, 2058 .hwcg_bit = 1, 2059 .clkr = { 2060 .enable_reg = 0x62008, 2061 .enable_mask = BIT(20), 2062 .hw.init = &(const struct clk_init_data) { 2063 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2064 .ops = &clk_branch2_ops, 2065 }, 2066 }, 2067 }; 2068 2069 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2070 .halt_reg = 0x28008, 2071 .halt_check = BRANCH_HALT_VOTED, 2072 .hwcg_reg = 0x28008, 2073 .hwcg_bit = 1, 2074 .clkr = { 2075 .enable_reg = 0x62008, 2076 .enable_mask = BIT(21), 2077 .hw.init = &(const struct clk_init_data) { 2078 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2079 .ops = &clk_branch2_ops, 2080 }, 2081 }, 2082 }; 2083 2084 static struct clk_branch gcc_sdcc5_ahb_clk = { 2085 .halt_reg = 0x3b00c, 2086 .halt_check = BRANCH_HALT, 2087 .clkr = { 2088 .enable_reg = 0x3b00c, 2089 .enable_mask = BIT(0), 2090 .hw.init = &(const struct clk_init_data) { 2091 .name = "gcc_sdcc5_ahb_clk", 2092 .ops = &clk_branch2_ops, 2093 }, 2094 }, 2095 }; 2096 2097 static struct clk_branch gcc_sdcc5_apps_clk = { 2098 .halt_reg = 0x3b004, 2099 .halt_check = BRANCH_HALT, 2100 .clkr = { 2101 .enable_reg = 0x3b004, 2102 .enable_mask = BIT(0), 2103 .hw.init = &(const struct clk_init_data) { 2104 .name = "gcc_sdcc5_apps_clk", 2105 .parent_hws = (const struct clk_hw*[]) { 2106 &gcc_sdcc5_apps_clk_src.clkr.hw, 2107 }, 2108 .num_parents = 1, 2109 .flags = CLK_SET_RATE_PARENT, 2110 .ops = &clk_branch2_ops, 2111 }, 2112 }, 2113 }; 2114 2115 static struct clk_branch gcc_sdcc5_ice_core_clk = { 2116 .halt_reg = 0x3b010, 2117 .halt_check = BRANCH_HALT, 2118 .clkr = { 2119 .enable_reg = 0x3b010, 2120 .enable_mask = BIT(0), 2121 .hw.init = &(const struct clk_init_data) { 2122 .name = "gcc_sdcc5_ice_core_clk", 2123 .parent_hws = (const struct clk_hw*[]) { 2124 &gcc_sdcc5_ice_core_clk_src.clkr.hw, 2125 }, 2126 .num_parents = 1, 2127 .flags = CLK_SET_RATE_PARENT, 2128 .ops = &clk_branch2_ops, 2129 }, 2130 }, 2131 }; 2132 2133 static struct clk_branch gcc_sm_bus_ahb_clk = { 2134 .halt_reg = 0x5b004, 2135 .halt_check = BRANCH_HALT, 2136 .clkr = { 2137 .enable_reg = 0x5b004, 2138 .enable_mask = BIT(0), 2139 .hw.init = &(const struct clk_init_data) { 2140 .name = "gcc_sm_bus_ahb_clk", 2141 .ops = &clk_branch2_ops, 2142 }, 2143 }, 2144 }; 2145 2146 static struct clk_branch gcc_sm_bus_xo_clk = { 2147 .halt_reg = 0x5b008, 2148 .halt_check = BRANCH_HALT, 2149 .clkr = { 2150 .enable_reg = 0x5b008, 2151 .enable_mask = BIT(0), 2152 .hw.init = &(const struct clk_init_data) { 2153 .name = "gcc_sm_bus_xo_clk", 2154 .parent_hws = (const struct clk_hw*[]) { 2155 &gcc_sm_bus_xo_clk_src.clkr.hw, 2156 }, 2157 .num_parents = 1, 2158 .flags = CLK_SET_RATE_PARENT, 2159 .ops = &clk_branch2_ops, 2160 }, 2161 }, 2162 }; 2163 2164 static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_qx_clk = { 2165 .halt_reg = 0x9200c, 2166 .halt_check = BRANCH_HALT_SKIP, 2167 .hwcg_reg = 0x9200c, 2168 .hwcg_bit = 1, 2169 .clkr = { 2170 .enable_reg = 0x62000, 2171 .enable_mask = BIT(11), 2172 .hw.init = &(const struct clk_init_data) { 2173 .name = "gcc_snoc_cnoc_gemnoc_pcie_qx_clk", 2174 .ops = &clk_branch2_ops, 2175 }, 2176 }, 2177 }; 2178 2179 static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk = { 2180 .halt_reg = 0x92010, 2181 .halt_check = BRANCH_HALT_SKIP, 2182 .hwcg_reg = 0x92010, 2183 .hwcg_bit = 1, 2184 .clkr = { 2185 .enable_reg = 0x62000, 2186 .enable_mask = BIT(12), 2187 .hw.init = &(const struct clk_init_data) { 2188 .name = "gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk", 2189 .ops = &clk_branch2_ops, 2190 }, 2191 }, 2192 }; 2193 2194 static struct clk_branch gcc_snoc_cnoc_pcie_qx_clk = { 2195 .halt_reg = 0x84030, 2196 .halt_check = BRANCH_HALT, 2197 .clkr = { 2198 .enable_reg = 0x84030, 2199 .enable_mask = BIT(0), 2200 .hw.init = &(const struct clk_init_data) { 2201 .name = "gcc_snoc_cnoc_pcie_qx_clk", 2202 .ops = &clk_branch2_ops, 2203 }, 2204 }, 2205 }; 2206 2207 static struct clk_branch gcc_snoc_pcie_sf_center_qx_clk = { 2208 .halt_reg = 0x92014, 2209 .halt_check = BRANCH_HALT_SKIP, 2210 .hwcg_reg = 0x92014, 2211 .hwcg_bit = 1, 2212 .clkr = { 2213 .enable_reg = 0x62000, 2214 .enable_mask = BIT(19), 2215 .hw.init = &(const struct clk_init_data) { 2216 .name = "gcc_snoc_pcie_sf_center_qx_clk", 2217 .ops = &clk_branch2_ops, 2218 }, 2219 }, 2220 }; 2221 2222 static struct clk_branch gcc_snoc_pcie_sf_south_qx_clk = { 2223 .halt_reg = 0x92018, 2224 .halt_check = BRANCH_HALT_SKIP, 2225 .hwcg_reg = 0x92018, 2226 .hwcg_bit = 1, 2227 .clkr = { 2228 .enable_reg = 0x62000, 2229 .enable_mask = BIT(22), 2230 .hw.init = &(const struct clk_init_data) { 2231 .name = "gcc_snoc_pcie_sf_south_qx_clk", 2232 .ops = &clk_branch2_ops, 2233 }, 2234 }, 2235 }; 2236 2237 static struct clk_branch gcc_tsc_cfg_ahb_clk = { 2238 .halt_reg = 0x5700c, 2239 .halt_check = BRANCH_HALT, 2240 .clkr = { 2241 .enable_reg = 0x5700c, 2242 .enable_mask = BIT(0), 2243 .hw.init = &(const struct clk_init_data) { 2244 .name = "gcc_tsc_cfg_ahb_clk", 2245 .ops = &clk_branch2_ops, 2246 }, 2247 }, 2248 }; 2249 2250 static struct clk_branch gcc_tsc_cntr_clk = { 2251 .halt_reg = 0x57004, 2252 .halt_check = BRANCH_HALT, 2253 .clkr = { 2254 .enable_reg = 0x57004, 2255 .enable_mask = BIT(0), 2256 .hw.init = &(const struct clk_init_data) { 2257 .name = "gcc_tsc_cntr_clk", 2258 .parent_hws = (const struct clk_hw*[]) { 2259 &gcc_tsc_clk_src.clkr.hw, 2260 }, 2261 .num_parents = 1, 2262 .flags = CLK_SET_RATE_PARENT, 2263 .ops = &clk_branch2_ops, 2264 }, 2265 }, 2266 }; 2267 2268 static struct clk_branch gcc_tsc_etu_clk = { 2269 .halt_reg = 0x57008, 2270 .halt_check = BRANCH_HALT, 2271 .clkr = { 2272 .enable_reg = 0x57008, 2273 .enable_mask = BIT(0), 2274 .hw.init = &(const struct clk_init_data) { 2275 .name = "gcc_tsc_etu_clk", 2276 .parent_hws = (const struct clk_hw*[]) { 2277 &gcc_tsc_clk_src.clkr.hw, 2278 }, 2279 .num_parents = 1, 2280 .flags = CLK_SET_RATE_PARENT, 2281 .ops = &clk_branch2_ops, 2282 }, 2283 }, 2284 }; 2285 2286 static struct clk_branch gcc_usb2_clkref_en = { 2287 .halt_reg = 0x9c008, 2288 .halt_bit = 31, 2289 .halt_check = BRANCH_HALT_ENABLE, 2290 .clkr = { 2291 .enable_reg = 0x9c008, 2292 .enable_mask = BIT(0), 2293 .hw.init = &(const struct clk_init_data) { 2294 .name = "gcc_usb2_clkref_en", 2295 .ops = &clk_branch_ops, 2296 }, 2297 }, 2298 }; 2299 2300 static struct clk_branch gcc_usb30_prim_master_clk = { 2301 .halt_reg = 0x49018, 2302 .halt_check = BRANCH_HALT, 2303 .clkr = { 2304 .enable_reg = 0x49018, 2305 .enable_mask = BIT(0), 2306 .hw.init = &(const struct clk_init_data) { 2307 .name = "gcc_usb30_prim_master_clk", 2308 .parent_hws = (const struct clk_hw*[]) { 2309 &gcc_usb30_prim_master_clk_src.clkr.hw, 2310 }, 2311 .num_parents = 1, 2312 .flags = CLK_SET_RATE_PARENT, 2313 .ops = &clk_branch2_ops, 2314 }, 2315 }, 2316 }; 2317 2318 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2319 .halt_reg = 0x49024, 2320 .halt_check = BRANCH_HALT, 2321 .clkr = { 2322 .enable_reg = 0x49024, 2323 .enable_mask = BIT(0), 2324 .hw.init = &(const struct clk_init_data) { 2325 .name = "gcc_usb30_prim_mock_utmi_clk", 2326 .parent_hws = (const struct clk_hw*[]) { 2327 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2328 }, 2329 .num_parents = 1, 2330 .flags = CLK_SET_RATE_PARENT, 2331 .ops = &clk_branch2_ops, 2332 }, 2333 }, 2334 }; 2335 2336 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2337 .halt_reg = 0x49020, 2338 .halt_check = BRANCH_HALT, 2339 .clkr = { 2340 .enable_reg = 0x49020, 2341 .enable_mask = BIT(0), 2342 .hw.init = &(const struct clk_init_data) { 2343 .name = "gcc_usb30_prim_sleep_clk", 2344 .ops = &clk_branch2_ops, 2345 }, 2346 }, 2347 }; 2348 2349 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2350 .halt_reg = 0x49060, 2351 .halt_check = BRANCH_HALT, 2352 .clkr = { 2353 .enable_reg = 0x49060, 2354 .enable_mask = BIT(0), 2355 .hw.init = &(const struct clk_init_data) { 2356 .name = "gcc_usb3_prim_phy_aux_clk", 2357 .parent_hws = (const struct clk_hw*[]) { 2358 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2359 }, 2360 .num_parents = 1, 2361 .flags = CLK_SET_RATE_PARENT, 2362 .ops = &clk_branch2_ops, 2363 }, 2364 }, 2365 }; 2366 2367 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2368 .halt_reg = 0x49064, 2369 .halt_check = BRANCH_HALT, 2370 .clkr = { 2371 .enable_reg = 0x49064, 2372 .enable_mask = BIT(0), 2373 .hw.init = &(const struct clk_init_data) { 2374 .name = "gcc_usb3_prim_phy_com_aux_clk", 2375 .parent_hws = (const struct clk_hw*[]) { 2376 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2377 }, 2378 .num_parents = 1, 2379 .flags = CLK_SET_RATE_PARENT, 2380 .ops = &clk_branch2_ops, 2381 }, 2382 }, 2383 }; 2384 2385 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2386 .halt_reg = 0x49068, 2387 .halt_check = BRANCH_HALT_DELAY, 2388 .hwcg_reg = 0x49068, 2389 .hwcg_bit = 1, 2390 .clkr = { 2391 .enable_reg = 0x49068, 2392 .enable_mask = BIT(0), 2393 .hw.init = &(const struct clk_init_data) { 2394 .name = "gcc_usb3_prim_phy_pipe_clk", 2395 .parent_hws = (const struct clk_hw*[]) { 2396 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 2397 }, 2398 .num_parents = 1, 2399 .flags = CLK_SET_RATE_PARENT, 2400 .ops = &clk_branch2_ops, 2401 }, 2402 }, 2403 }; 2404 2405 static struct clk_regmap *gcc_qdu1000_clocks[] = { 2406 [GCC_AGGRE_NOC_ECPRI_DMA_CLK] = &gcc_aggre_noc_ecpri_dma_clk.clkr, 2407 [GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC] = &gcc_aggre_noc_ecpri_dma_clk_src.clkr, 2408 [GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC] = &gcc_aggre_noc_ecpri_gsi_clk_src.clkr, 2409 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2410 [GCC_CFG_NOC_ECPRI_CC_AHB_CLK] = &gcc_cfg_noc_ecpri_cc_ahb_clk.clkr, 2411 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2412 [GCC_DDRSS_ECPRI_DMA_CLK] = &gcc_ddrss_ecpri_dma_clk.clkr, 2413 [GCC_ECPRI_AHB_CLK] = &gcc_ecpri_ahb_clk.clkr, 2414 [GCC_ECPRI_CC_GPLL0_CLK_SRC] = &gcc_ecpri_cc_gpll0_clk_src.clkr, 2415 [GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll1_even_clk_src.clkr, 2416 [GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll2_even_clk_src.clkr, 2417 [GCC_ECPRI_CC_GPLL3_CLK_SRC] = &gcc_ecpri_cc_gpll3_clk_src.clkr, 2418 [GCC_ECPRI_CC_GPLL4_CLK_SRC] = &gcc_ecpri_cc_gpll4_clk_src.clkr, 2419 [GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll5_even_clk_src.clkr, 2420 [GCC_ECPRI_XO_CLK] = &gcc_ecpri_xo_clk.clkr, 2421 [GCC_ETH_DBG_SNOC_AXI_CLK] = &gcc_eth_dbg_snoc_axi_clk.clkr, 2422 [GCC_GEMNOC_PCIE_QX_CLK] = &gcc_gemnoc_pcie_qx_clk.clkr, 2423 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2424 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2425 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2426 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2427 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2428 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2429 [GCC_GPLL0] = &gcc_gpll0.clkr, 2430 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 2431 [GCC_GPLL1] = &gcc_gpll1.clkr, 2432 [GCC_GPLL2] = &gcc_gpll2.clkr, 2433 [GCC_GPLL2_OUT_EVEN] = &gcc_gpll2_out_even.clkr, 2434 [GCC_GPLL3] = &gcc_gpll3.clkr, 2435 [GCC_GPLL4] = &gcc_gpll4.clkr, 2436 [GCC_GPLL5] = &gcc_gpll5.clkr, 2437 [GCC_GPLL5_OUT_EVEN] = &gcc_gpll5_out_even.clkr, 2438 [GCC_GPLL6] = &gcc_gpll6.clkr, 2439 [GCC_GPLL7] = &gcc_gpll7.clkr, 2440 [GCC_GPLL8] = &gcc_gpll8.clkr, 2441 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2442 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 2443 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2444 [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr, 2445 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2446 [GCC_PCIE_0_PHY_AUX_CLK] = &gcc_pcie_0_phy_aux_clk.clkr, 2447 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 2448 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 2449 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2450 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2451 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 2452 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2453 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 2454 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2455 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2456 [GCC_QMIP_ANOC_PCIE_CLK] = &gcc_qmip_anoc_pcie_clk.clkr, 2457 [GCC_QMIP_ECPRI_DMA0_CLK] = &gcc_qmip_ecpri_dma0_clk.clkr, 2458 [GCC_QMIP_ECPRI_DMA1_CLK] = &gcc_qmip_ecpri_dma1_clk.clkr, 2459 [GCC_QMIP_ECPRI_GSI_CLK] = &gcc_qmip_ecpri_gsi_clk.clkr, 2460 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 2461 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 2462 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 2463 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 2464 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 2465 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 2466 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 2467 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 2468 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 2469 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 2470 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 2471 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 2472 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 2473 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 2474 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 2475 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 2476 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 2477 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 2478 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 2479 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 2480 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 2481 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 2482 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 2483 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 2484 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 2485 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 2486 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 2487 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 2488 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 2489 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 2490 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 2491 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 2492 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 2493 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 2494 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 2495 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 2496 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 2497 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 2498 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 2499 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 2500 [GCC_SDCC5_AHB_CLK] = &gcc_sdcc5_ahb_clk.clkr, 2501 [GCC_SDCC5_APPS_CLK] = &gcc_sdcc5_apps_clk.clkr, 2502 [GCC_SDCC5_APPS_CLK_SRC] = &gcc_sdcc5_apps_clk_src.clkr, 2503 [GCC_SDCC5_ICE_CORE_CLK] = &gcc_sdcc5_ice_core_clk.clkr, 2504 [GCC_SDCC5_ICE_CORE_CLK_SRC] = &gcc_sdcc5_ice_core_clk_src.clkr, 2505 [GCC_SM_BUS_AHB_CLK] = &gcc_sm_bus_ahb_clk.clkr, 2506 [GCC_SM_BUS_XO_CLK] = &gcc_sm_bus_xo_clk.clkr, 2507 [GCC_SM_BUS_XO_CLK_SRC] = &gcc_sm_bus_xo_clk_src.clkr, 2508 [GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK] = &gcc_snoc_cnoc_gemnoc_pcie_qx_clk.clkr, 2509 [GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK] = &gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk.clkr, 2510 [GCC_SNOC_CNOC_PCIE_QX_CLK] = &gcc_snoc_cnoc_pcie_qx_clk.clkr, 2511 [GCC_SNOC_PCIE_SF_CENTER_QX_CLK] = &gcc_snoc_pcie_sf_center_qx_clk.clkr, 2512 [GCC_SNOC_PCIE_SF_SOUTH_QX_CLK] = &gcc_snoc_pcie_sf_south_qx_clk.clkr, 2513 [GCC_TSC_CFG_AHB_CLK] = &gcc_tsc_cfg_ahb_clk.clkr, 2514 [GCC_TSC_CLK_SRC] = &gcc_tsc_clk_src.clkr, 2515 [GCC_TSC_CNTR_CLK] = &gcc_tsc_cntr_clk.clkr, 2516 [GCC_TSC_ETU_CLK] = &gcc_tsc_etu_clk.clkr, 2517 [GCC_USB2_CLKREF_EN] = &gcc_usb2_clkref_en.clkr, 2518 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 2519 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 2520 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 2521 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 2522 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 2523 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 2524 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 2525 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 2526 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 2527 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 2528 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 2529 [GCC_ETH_100G_C2C_HM_APB_CLK] = &gcc_eth_100g_c2c_hm_apb_clk.clkr, 2530 [GCC_ETH_100G_FH_HM_APB_0_CLK] = &gcc_eth_100g_fh_hm_apb_0_clk.clkr, 2531 [GCC_ETH_100G_FH_HM_APB_1_CLK] = &gcc_eth_100g_fh_hm_apb_1_clk.clkr, 2532 [GCC_ETH_100G_FH_HM_APB_2_CLK] = &gcc_eth_100g_fh_hm_apb_2_clk.clkr, 2533 [GCC_ETH_DBG_C2C_HM_APB_CLK] = &gcc_eth_dbg_c2c_hm_apb_clk.clkr, 2534 [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr, 2535 [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, 2536 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 2537 }; 2538 2539 static const struct qcom_reset_map gcc_qdu1000_resets[] = { 2540 [GCC_ECPRI_CC_BCR] = { 0x3e000 }, 2541 [GCC_ECPRI_SS_BCR] = { 0x3a000 }, 2542 [GCC_ETH_WRAPPER_BCR] = { 0x39000 }, 2543 [GCC_PCIE_0_BCR] = { 0x9d000 }, 2544 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x9e014 }, 2545 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x9e020 }, 2546 [GCC_PCIE_0_PHY_BCR] = { 0x7c000 }, 2547 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 }, 2548 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c }, 2549 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 }, 2550 [GCC_PDM_BCR] = { 0x43000 }, 2551 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 }, 2552 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 }, 2553 [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 }, 2554 [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 }, 2555 [GCC_SDCC5_BCR] = { 0x3b000 }, 2556 [GCC_TSC_BCR] = { 0x57000 }, 2557 [GCC_USB30_PRIM_BCR] = { 0x49000 }, 2558 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 }, 2559 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 }, 2560 [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 }, 2561 [GCC_USB3_PHY_SEC_BCR] = { 0x6000c }, 2562 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 }, 2563 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 }, 2564 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 }, 2565 }; 2566 2567 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 2568 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 2569 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 2570 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 2571 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 2572 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 2573 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 2574 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 2575 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 2576 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 2577 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 2578 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 2579 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 2580 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 2581 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 2582 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 2583 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 2584 }; 2585 2586 static const struct regmap_config gcc_qdu1000_regmap_config = { 2587 .reg_bits = 32, 2588 .reg_stride = 4, 2589 .val_bits = 32, 2590 .max_register = 0x1f41f0, 2591 .fast_io = true, 2592 }; 2593 2594 static const struct qcom_cc_desc gcc_qdu1000_desc = { 2595 .config = &gcc_qdu1000_regmap_config, 2596 .clks = gcc_qdu1000_clocks, 2597 .num_clks = ARRAY_SIZE(gcc_qdu1000_clocks), 2598 .resets = gcc_qdu1000_resets, 2599 .num_resets = ARRAY_SIZE(gcc_qdu1000_resets), 2600 }; 2601 2602 static const struct of_device_id gcc_qdu1000_match_table[] = { 2603 { .compatible = "qcom,qdu1000-gcc" }, 2604 { } 2605 }; 2606 MODULE_DEVICE_TABLE(of, gcc_qdu1000_match_table); 2607 2608 static int gcc_qdu1000_probe(struct platform_device *pdev) 2609 { 2610 struct regmap *regmap; 2611 int ret; 2612 2613 regmap = qcom_cc_map(pdev, &gcc_qdu1000_desc); 2614 if (IS_ERR(regmap)) 2615 return PTR_ERR(regmap); 2616 2617 /* Update FORCE_MEM_CORE_ON for gcc_pcie_0_mstr_axi_clk */ 2618 regmap_update_bits(regmap, 0x9d024, BIT(14), BIT(14)); 2619 2620 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 2621 ARRAY_SIZE(gcc_dfs_clocks)); 2622 if (ret) 2623 return ret; 2624 2625 ret = qcom_cc_really_probe(pdev, &gcc_qdu1000_desc, regmap); 2626 if (ret) 2627 return dev_err_probe(&pdev->dev, ret, "Failed to register GCC clocks\n"); 2628 2629 return ret; 2630 } 2631 2632 static struct platform_driver gcc_qdu1000_driver = { 2633 .probe = gcc_qdu1000_probe, 2634 .driver = { 2635 .name = "gcc-qdu1000", 2636 .of_match_table = gcc_qdu1000_match_table, 2637 }, 2638 }; 2639 2640 static int __init gcc_qdu1000_init(void) 2641 { 2642 return platform_driver_register(&gcc_qdu1000_driver); 2643 } 2644 subsys_initcall(gcc_qdu1000_init); 2645 2646 static void __exit gcc_qdu1000_exit(void) 2647 { 2648 platform_driver_unregister(&gcc_qdu1000_driver); 2649 } 2650 module_exit(gcc_qdu1000_exit); 2651 2652 MODULE_DESCRIPTION("QTI GCC QDU1000 Driver"); 2653 MODULE_LICENSE("GPL"); 2654