1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/of_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,qdu1000-gcc.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-rcg.h" 16 #include "clk-regmap.h" 17 #include "clk-regmap-divider.h" 18 #include "clk-regmap-mux.h" 19 #include "clk-regmap-phy-mux.h" 20 #include "reset.h" 21 22 enum { 23 P_BI_TCXO, 24 P_GCC_GPLL0_OUT_EVEN, 25 P_GCC_GPLL0_OUT_MAIN, 26 P_GCC_GPLL1_OUT_MAIN, 27 P_GCC_GPLL2_OUT_MAIN, 28 P_GCC_GPLL3_OUT_MAIN, 29 P_GCC_GPLL4_OUT_MAIN, 30 P_GCC_GPLL5_OUT_MAIN, 31 P_GCC_GPLL6_OUT_MAIN, 32 P_GCC_GPLL7_OUT_MAIN, 33 P_GCC_GPLL8_OUT_MAIN, 34 P_PCIE_0_PHY_AUX_CLK, 35 P_PCIE_0_PIPE_CLK, 36 P_SLEEP_CLK, 37 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 38 }; 39 40 enum { 41 DT_TCXO_IDX, 42 DT_SLEEP_CLK_IDX, 43 DT_PCIE_0_PIPE_CLK_IDX, 44 DT_PCIE_0_PHY_AUX_CLK_IDX, 45 DT_USB3_PHY_WRAPPER_PIPE_CLK_IDX, 46 }; 47 48 static struct clk_alpha_pll gcc_gpll0 = { 49 .offset = 0x0, 50 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 51 .clkr = { 52 .enable_reg = 0x62018, 53 .enable_mask = BIT(0), 54 .hw.init = &(const struct clk_init_data) { 55 .name = "gcc_gpll0", 56 .parent_data = &(const struct clk_parent_data) { 57 .index = DT_TCXO_IDX, 58 }, 59 .num_parents = 1, 60 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 61 }, 62 }, 63 }; 64 65 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 66 { 0x1, 2 } 67 }; 68 69 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 70 .offset = 0x0, 71 .post_div_shift = 10, 72 .post_div_table = post_div_table_gcc_gpll0_out_even, 73 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 74 .width = 4, 75 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 76 .clkr.hw.init = &(const struct clk_init_data) { 77 .name = "gcc_gpll0_out_even", 78 .parent_hws = (const struct clk_hw*[]) { 79 &gcc_gpll0.clkr.hw, 80 }, 81 .num_parents = 1, 82 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 83 }, 84 }; 85 86 static struct clk_alpha_pll gcc_gpll1 = { 87 .offset = 0x1000, 88 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 89 .clkr = { 90 .enable_reg = 0x62018, 91 .enable_mask = BIT(1), 92 .hw.init = &(const struct clk_init_data) { 93 .name = "gcc_gpll1", 94 .parent_data = &(const struct clk_parent_data) { 95 .index = DT_TCXO_IDX, 96 }, 97 .num_parents = 1, 98 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 99 }, 100 }, 101 }; 102 103 static struct clk_alpha_pll_postdiv gcc_gpll1_out_even = { 104 .offset = 0x1000, 105 .post_div_shift = 10, 106 .post_div_table = post_div_table_gcc_gpll0_out_even, 107 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 108 .width = 4, 109 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 110 .clkr.hw.init = &(const struct clk_init_data) { 111 .name = "gcc_gpll1_out_even", 112 .parent_hws = (const struct clk_hw*[]) { 113 &gcc_gpll1.clkr.hw, 114 }, 115 .num_parents = 1, 116 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 117 }, 118 }; 119 120 static struct clk_alpha_pll gcc_gpll2 = { 121 .offset = 0x2000, 122 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 123 .clkr = { 124 .enable_reg = 0x62018, 125 .enable_mask = BIT(2), 126 .hw.init = &(const struct clk_init_data) { 127 .name = "gcc_gpll2", 128 .parent_data = &(const struct clk_parent_data) { 129 .index = DT_TCXO_IDX, 130 }, 131 .num_parents = 1, 132 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 133 }, 134 }, 135 }; 136 137 static struct clk_alpha_pll_postdiv gcc_gpll2_out_even = { 138 .offset = 0x2000, 139 .post_div_shift = 10, 140 .post_div_table = post_div_table_gcc_gpll0_out_even, 141 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 142 .width = 4, 143 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 144 .clkr.hw.init = &(const struct clk_init_data) { 145 .name = "gcc_gpll2_out_even", 146 .parent_hws = (const struct clk_hw*[]) { 147 &gcc_gpll2.clkr.hw, 148 }, 149 .num_parents = 1, 150 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 151 }, 152 }; 153 154 static struct clk_alpha_pll gcc_gpll3 = { 155 .offset = 0x3000, 156 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 157 .clkr = { 158 .enable_reg = 0x62018, 159 .enable_mask = BIT(3), 160 .hw.init = &(const struct clk_init_data) { 161 .name = "gcc_gpll3", 162 .parent_data = &(const struct clk_parent_data) { 163 .index = DT_TCXO_IDX, 164 }, 165 .num_parents = 1, 166 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 167 }, 168 }, 169 }; 170 171 static struct clk_alpha_pll gcc_gpll4 = { 172 .offset = 0x4000, 173 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 174 .clkr = { 175 .enable_reg = 0x62018, 176 .enable_mask = BIT(4), 177 .hw.init = &(const struct clk_init_data) { 178 .name = "gcc_gpll4", 179 .parent_data = &(const struct clk_parent_data) { 180 .index = DT_TCXO_IDX, 181 }, 182 .num_parents = 1, 183 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 184 }, 185 }, 186 }; 187 188 static struct clk_alpha_pll gcc_gpll5 = { 189 .offset = 0x5000, 190 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 191 .clkr = { 192 .enable_reg = 0x62018, 193 .enable_mask = BIT(5), 194 .hw.init = &(const struct clk_init_data) { 195 .name = "gcc_gpll5", 196 .parent_data = &(const struct clk_parent_data) { 197 .index = DT_TCXO_IDX, 198 }, 199 .num_parents = 1, 200 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 201 }, 202 }, 203 }; 204 205 static struct clk_alpha_pll_postdiv gcc_gpll5_out_even = { 206 .offset = 0x5000, 207 .post_div_shift = 10, 208 .post_div_table = post_div_table_gcc_gpll0_out_even, 209 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 210 .width = 4, 211 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 212 .clkr.hw.init = &(const struct clk_init_data) { 213 .name = "gcc_gpll5_out_even", 214 .parent_hws = (const struct clk_hw*[]) { 215 &gcc_gpll5.clkr.hw, 216 }, 217 .num_parents = 1, 218 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 219 }, 220 }; 221 222 static struct clk_alpha_pll gcc_gpll6 = { 223 .offset = 0x6000, 224 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 225 .clkr = { 226 .enable_reg = 0x62018, 227 .enable_mask = BIT(6), 228 .hw.init = &(const struct clk_init_data) { 229 .name = "gcc_gpll6", 230 .parent_data = &(const struct clk_parent_data) { 231 .index = DT_TCXO_IDX, 232 }, 233 .num_parents = 1, 234 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 235 }, 236 }, 237 }; 238 239 static struct clk_alpha_pll gcc_gpll7 = { 240 .offset = 0x7000, 241 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 242 .clkr = { 243 .enable_reg = 0x62018, 244 .enable_mask = BIT(7), 245 .hw.init = &(const struct clk_init_data) { 246 .name = "gcc_gpll7", 247 .parent_data = &(const struct clk_parent_data) { 248 .index = DT_TCXO_IDX, 249 }, 250 .num_parents = 1, 251 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 252 }, 253 }, 254 }; 255 256 static struct clk_alpha_pll gcc_gpll8 = { 257 .offset = 0x8000, 258 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 259 .clkr = { 260 .enable_reg = 0x62018, 261 .enable_mask = BIT(8), 262 .hw.init = &(const struct clk_init_data) { 263 .name = "gcc_gpll8", 264 .parent_data = &(const struct clk_parent_data) { 265 .index = DT_TCXO_IDX, 266 }, 267 .num_parents = 1, 268 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 269 }, 270 }, 271 }; 272 273 static const struct parent_map gcc_parent_map_0[] = { 274 { P_BI_TCXO, 0 }, 275 { P_GCC_GPLL0_OUT_MAIN, 1 }, 276 { P_GCC_GPLL0_OUT_EVEN, 6 }, 277 }; 278 279 static const struct clk_parent_data gcc_parent_data_0[] = { 280 { .index = DT_TCXO_IDX }, 281 { .hw = &gcc_gpll0.clkr.hw }, 282 { .hw = &gcc_gpll0_out_even.clkr.hw }, 283 }; 284 285 static const struct parent_map gcc_parent_map_1[] = { 286 { P_BI_TCXO, 0 }, 287 { P_GCC_GPLL0_OUT_MAIN, 1 }, 288 { P_SLEEP_CLK, 5 }, 289 { P_GCC_GPLL0_OUT_EVEN, 6 }, 290 }; 291 292 static const struct clk_parent_data gcc_parent_data_1[] = { 293 { .index = DT_TCXO_IDX }, 294 { .hw = &gcc_gpll0.clkr.hw }, 295 { .index = DT_SLEEP_CLK_IDX }, 296 { .hw = &gcc_gpll0_out_even.clkr.hw }, 297 }; 298 299 static const struct parent_map gcc_parent_map_2[] = { 300 { P_BI_TCXO, 0 }, 301 { P_GCC_GPLL0_OUT_MAIN, 1 }, 302 { P_GCC_GPLL5_OUT_MAIN, 3 }, 303 { P_GCC_GPLL4_OUT_MAIN, 5 }, 304 }; 305 306 static const struct clk_parent_data gcc_parent_data_2[] = { 307 { .index = DT_TCXO_IDX }, 308 { .hw = &gcc_gpll0.clkr.hw }, 309 { .hw = &gcc_gpll5.clkr.hw }, 310 { .hw = &gcc_gpll4.clkr.hw }, 311 }; 312 313 static const struct parent_map gcc_parent_map_3[] = { 314 { P_BI_TCXO, 0 }, 315 { P_SLEEP_CLK, 5 }, 316 }; 317 318 static const struct clk_parent_data gcc_parent_data_3[] = { 319 { .index = DT_TCXO_IDX }, 320 { .index = DT_SLEEP_CLK_IDX }, 321 }; 322 323 static const struct parent_map gcc_parent_map_4[] = { 324 { P_BI_TCXO, 0 }, 325 { P_GCC_GPLL0_OUT_MAIN, 1 }, 326 { P_GCC_GPLL2_OUT_MAIN, 2 }, 327 { P_GCC_GPLL5_OUT_MAIN, 3 }, 328 { P_GCC_GPLL1_OUT_MAIN, 4 }, 329 { P_GCC_GPLL4_OUT_MAIN, 5 }, 330 { P_GCC_GPLL3_OUT_MAIN, 6 }, 331 }; 332 333 static const struct clk_parent_data gcc_parent_data_4[] = { 334 { .index = DT_TCXO_IDX }, 335 { .hw = &gcc_gpll0.clkr.hw }, 336 { .hw = &gcc_gpll2.clkr.hw }, 337 { .hw = &gcc_gpll5.clkr.hw }, 338 { .hw = &gcc_gpll1.clkr.hw }, 339 { .hw = &gcc_gpll4.clkr.hw }, 340 { .hw = &gcc_gpll3.clkr.hw }, 341 }; 342 343 static const struct parent_map gcc_parent_map_5[] = { 344 { P_BI_TCXO, 0 }, 345 { P_GCC_GPLL0_OUT_MAIN, 1 }, 346 { P_GCC_GPLL2_OUT_MAIN, 2 }, 347 { P_GCC_GPLL6_OUT_MAIN, 3 }, 348 { P_GCC_GPLL1_OUT_MAIN, 4 }, 349 { P_GCC_GPLL4_OUT_MAIN, 5 }, 350 { P_GCC_GPLL3_OUT_MAIN, 6 }, 351 }; 352 353 static const struct clk_parent_data gcc_parent_data_5[] = { 354 { .index = DT_TCXO_IDX }, 355 { .hw = &gcc_gpll0.clkr.hw }, 356 { .hw = &gcc_gpll2.clkr.hw }, 357 { .hw = &gcc_gpll6.clkr.hw }, 358 { .hw = &gcc_gpll1.clkr.hw }, 359 { .hw = &gcc_gpll4.clkr.hw }, 360 { .hw = &gcc_gpll3.clkr.hw }, 361 }; 362 363 static const struct parent_map gcc_parent_map_6[] = { 364 { P_PCIE_0_PHY_AUX_CLK, 0 }, 365 { P_BI_TCXO, 2 }, 366 }; 367 368 static const struct clk_parent_data gcc_parent_data_6[] = { 369 { .index = DT_PCIE_0_PHY_AUX_CLK_IDX }, 370 { .index = DT_TCXO_IDX }, 371 }; 372 373 static const struct parent_map gcc_parent_map_8[] = { 374 { P_BI_TCXO, 0 }, 375 { P_GCC_GPLL0_OUT_MAIN, 1 }, 376 { P_GCC_GPLL8_OUT_MAIN, 2 }, 377 { P_GCC_GPLL5_OUT_MAIN, 3 }, 378 { P_GCC_GPLL4_OUT_MAIN, 5 }, 379 }; 380 381 static const struct clk_parent_data gcc_parent_data_8[] = { 382 { .index = DT_TCXO_IDX }, 383 { .hw = &gcc_gpll0.clkr.hw }, 384 { .hw = &gcc_gpll8.clkr.hw }, 385 { .hw = &gcc_gpll5.clkr.hw }, 386 { .hw = &gcc_gpll4.clkr.hw }, 387 }; 388 389 static const struct parent_map gcc_parent_map_9[] = { 390 { P_BI_TCXO, 0 }, 391 { P_GCC_GPLL0_OUT_MAIN, 1 }, 392 { P_GCC_GPLL2_OUT_MAIN, 2 }, 393 { P_GCC_GPLL5_OUT_MAIN, 3 }, 394 { P_GCC_GPLL7_OUT_MAIN, 4 }, 395 { P_GCC_GPLL4_OUT_MAIN, 5 }, 396 }; 397 398 static const struct clk_parent_data gcc_parent_data_9[] = { 399 { .index = DT_TCXO_IDX }, 400 { .hw = &gcc_gpll0.clkr.hw }, 401 { .hw = &gcc_gpll2.clkr.hw }, 402 { .hw = &gcc_gpll5.clkr.hw }, 403 { .hw = &gcc_gpll7.clkr.hw }, 404 { .hw = &gcc_gpll4.clkr.hw }, 405 }; 406 407 static const struct parent_map gcc_parent_map_10[] = { 408 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 409 { P_BI_TCXO, 2 }, 410 }; 411 412 static const struct clk_parent_data gcc_parent_data_10[] = { 413 { .index = DT_USB3_PHY_WRAPPER_PIPE_CLK_IDX }, 414 { .index = DT_TCXO_IDX }, 415 }; 416 417 static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = { 418 .reg = 0x9d080, 419 .shift = 0, 420 .width = 2, 421 .parent_map = gcc_parent_map_6, 422 .clkr = { 423 .hw.init = &(const struct clk_init_data) { 424 .name = "gcc_pcie_0_phy_aux_clk_src", 425 .parent_data = gcc_parent_data_6, 426 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 427 .ops = &clk_regmap_mux_closest_ops, 428 }, 429 }, 430 }; 431 432 static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { 433 .reg = 0x9d064, 434 .clkr = { 435 .hw.init = &(const struct clk_init_data) { 436 .name = "gcc_pcie_0_pipe_clk_src", 437 .parent_data = &(const struct clk_parent_data){ 438 .index = DT_PCIE_0_PIPE_CLK_IDX, 439 }, 440 .num_parents = 1, 441 .ops = &clk_regmap_phy_mux_ops, 442 }, 443 }, 444 }; 445 446 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 447 .reg = 0x4906c, 448 .shift = 0, 449 .width = 2, 450 .parent_map = gcc_parent_map_10, 451 .clkr = { 452 .hw.init = &(const struct clk_init_data) { 453 .name = "gcc_usb3_prim_phy_pipe_clk_src", 454 .parent_data = gcc_parent_data_10, 455 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 456 .ops = &clk_regmap_mux_closest_ops, 457 }, 458 }, 459 }; 460 461 static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_dma_clk_src[] = { 462 F(466500000, P_GCC_GPLL5_OUT_MAIN, 2, 0, 0), 463 F(500000000, P_GCC_GPLL2_OUT_MAIN, 2, 0, 0), 464 { } 465 }; 466 467 static struct clk_rcg2 gcc_aggre_noc_ecpri_dma_clk_src = { 468 .cmd_rcgr = 0x92020, 469 .mnd_width = 0, 470 .hid_width = 5, 471 .parent_map = gcc_parent_map_4, 472 .freq_tbl = ftbl_gcc_aggre_noc_ecpri_dma_clk_src, 473 .clkr.hw.init = &(const struct clk_init_data) { 474 .name = "gcc_aggre_noc_ecpri_dma_clk_src", 475 .parent_data = gcc_parent_data_4, 476 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 477 .ops = &clk_rcg2_ops, 478 }, 479 }; 480 481 static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_gsi_clk_src[] = { 482 F(250000000, P_GCC_GPLL2_OUT_MAIN, 4, 0, 0), 483 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 484 { } 485 }; 486 487 static struct clk_rcg2 gcc_aggre_noc_ecpri_gsi_clk_src = { 488 .cmd_rcgr = 0x92038, 489 .mnd_width = 0, 490 .hid_width = 5, 491 .parent_map = gcc_parent_map_5, 492 .freq_tbl = ftbl_gcc_aggre_noc_ecpri_gsi_clk_src, 493 .clkr.hw.init = &(const struct clk_init_data) { 494 .name = "gcc_aggre_noc_ecpri_gsi_clk_src", 495 .parent_data = gcc_parent_data_5, 496 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 497 .ops = &clk_rcg2_ops, 498 }, 499 }; 500 501 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 502 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 503 { } 504 }; 505 506 static struct clk_rcg2 gcc_gp1_clk_src = { 507 .cmd_rcgr = 0x74004, 508 .mnd_width = 16, 509 .hid_width = 5, 510 .parent_map = gcc_parent_map_1, 511 .freq_tbl = ftbl_gcc_gp1_clk_src, 512 .clkr.hw.init = &(const struct clk_init_data) { 513 .name = "gcc_gp1_clk_src", 514 .parent_data = gcc_parent_data_1, 515 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 516 .ops = &clk_rcg2_ops, 517 }, 518 }; 519 520 static struct clk_rcg2 gcc_gp2_clk_src = { 521 .cmd_rcgr = 0x75004, 522 .mnd_width = 16, 523 .hid_width = 5, 524 .parent_map = gcc_parent_map_1, 525 .freq_tbl = ftbl_gcc_gp1_clk_src, 526 .clkr.hw.init = &(const struct clk_init_data) { 527 .name = "gcc_gp2_clk_src", 528 .parent_data = gcc_parent_data_1, 529 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 530 .ops = &clk_rcg2_ops, 531 }, 532 }; 533 534 static struct clk_rcg2 gcc_gp3_clk_src = { 535 .cmd_rcgr = 0x76004, 536 .mnd_width = 16, 537 .hid_width = 5, 538 .parent_map = gcc_parent_map_1, 539 .freq_tbl = ftbl_gcc_gp1_clk_src, 540 .clkr.hw.init = &(const struct clk_init_data) { 541 .name = "gcc_gp3_clk_src", 542 .parent_data = gcc_parent_data_1, 543 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 544 .ops = &clk_rcg2_ops, 545 }, 546 }; 547 548 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 549 F(19200000, P_BI_TCXO, 1, 0, 0), 550 { } 551 }; 552 553 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 554 .cmd_rcgr = 0x9d068, 555 .mnd_width = 16, 556 .hid_width = 5, 557 .parent_map = gcc_parent_map_3, 558 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 559 .clkr.hw.init = &(const struct clk_init_data) { 560 .name = "gcc_pcie_0_aux_clk_src", 561 .parent_data = gcc_parent_data_3, 562 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 563 .ops = &clk_rcg2_ops, 564 }, 565 }; 566 567 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 568 F(19200000, P_BI_TCXO, 1, 0, 0), 569 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 570 { } 571 }; 572 573 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 574 .cmd_rcgr = 0x9d04c, 575 .mnd_width = 0, 576 .hid_width = 5, 577 .parent_map = gcc_parent_map_0, 578 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 579 .clkr.hw.init = &(const struct clk_init_data) { 580 .name = "gcc_pcie_0_phy_rchng_clk_src", 581 .parent_data = gcc_parent_data_0, 582 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 583 .ops = &clk_rcg2_ops, 584 }, 585 }; 586 587 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 588 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 589 { } 590 }; 591 592 static struct clk_rcg2 gcc_pdm2_clk_src = { 593 .cmd_rcgr = 0x43010, 594 .mnd_width = 0, 595 .hid_width = 5, 596 .parent_map = gcc_parent_map_0, 597 .freq_tbl = ftbl_gcc_pdm2_clk_src, 598 .clkr.hw.init = &(const struct clk_init_data) { 599 .name = "gcc_pdm2_clk_src", 600 .parent_data = gcc_parent_data_0, 601 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 602 .ops = &clk_rcg2_ops, 603 }, 604 }; 605 606 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 607 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 608 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 609 F(19200000, P_BI_TCXO, 1, 0, 0), 610 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 611 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 612 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 613 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 614 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 615 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 616 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 617 { } 618 }; 619 620 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 621 .name = "gcc_qupv3_wrap0_s0_clk_src", 622 .parent_data = gcc_parent_data_0, 623 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 624 .ops = &clk_rcg2_ops, 625 }; 626 627 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 628 .cmd_rcgr = 0x27154, 629 .mnd_width = 16, 630 .hid_width = 5, 631 .parent_map = gcc_parent_map_0, 632 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 633 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 634 }; 635 636 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 637 .name = "gcc_qupv3_wrap0_s1_clk_src", 638 .parent_data = gcc_parent_data_0, 639 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 640 .ops = &clk_rcg2_ops, 641 }; 642 643 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 644 .cmd_rcgr = 0x27288, 645 .mnd_width = 16, 646 .hid_width = 5, 647 .parent_map = gcc_parent_map_0, 648 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 649 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 650 }; 651 652 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 653 .name = "gcc_qupv3_wrap0_s2_clk_src", 654 .parent_data = gcc_parent_data_0, 655 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 656 .ops = &clk_rcg2_ops, 657 }; 658 659 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 660 .cmd_rcgr = 0x273bc, 661 .mnd_width = 16, 662 .hid_width = 5, 663 .parent_map = gcc_parent_map_0, 664 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 665 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 666 }; 667 668 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 669 .name = "gcc_qupv3_wrap0_s3_clk_src", 670 .parent_data = gcc_parent_data_0, 671 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 672 .ops = &clk_rcg2_ops, 673 }; 674 675 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 676 .cmd_rcgr = 0x274f0, 677 .mnd_width = 16, 678 .hid_width = 5, 679 .parent_map = gcc_parent_map_0, 680 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 681 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 682 }; 683 684 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 685 .name = "gcc_qupv3_wrap0_s4_clk_src", 686 .parent_data = gcc_parent_data_0, 687 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 688 .ops = &clk_rcg2_ops, 689 }; 690 691 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 692 .cmd_rcgr = 0x27624, 693 .mnd_width = 16, 694 .hid_width = 5, 695 .parent_map = gcc_parent_map_0, 696 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 697 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 698 }; 699 700 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] = { 701 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 702 { } 703 }; 704 705 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 706 .name = "gcc_qupv3_wrap0_s5_clk_src", 707 .parent_data = gcc_parent_data_0, 708 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 709 .ops = &clk_rcg2_ops, 710 }; 711 712 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 713 .cmd_rcgr = 0x27758, 714 .mnd_width = 16, 715 .hid_width = 5, 716 .parent_map = gcc_parent_map_0, 717 .freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src, 718 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 719 }; 720 721 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 722 .name = "gcc_qupv3_wrap0_s6_clk_src", 723 .parent_data = gcc_parent_data_0, 724 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 725 .ops = &clk_rcg2_ops, 726 }; 727 728 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 729 .cmd_rcgr = 0x2788c, 730 .mnd_width = 16, 731 .hid_width = 5, 732 .parent_map = gcc_parent_map_0, 733 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 734 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 735 }; 736 737 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 738 .name = "gcc_qupv3_wrap0_s7_clk_src", 739 .parent_data = gcc_parent_data_0, 740 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 741 .ops = &clk_rcg2_ops, 742 }; 743 744 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 745 .cmd_rcgr = 0x279c0, 746 .mnd_width = 16, 747 .hid_width = 5, 748 .parent_map = gcc_parent_map_0, 749 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 750 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 751 }; 752 753 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 754 .name = "gcc_qupv3_wrap1_s0_clk_src", 755 .parent_data = gcc_parent_data_0, 756 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 757 .ops = &clk_rcg2_ops, 758 }; 759 760 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 761 .cmd_rcgr = 0x28154, 762 .mnd_width = 16, 763 .hid_width = 5, 764 .parent_map = gcc_parent_map_0, 765 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 766 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 767 }; 768 769 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 770 .name = "gcc_qupv3_wrap1_s1_clk_src", 771 .parent_data = gcc_parent_data_0, 772 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 773 .ops = &clk_rcg2_ops, 774 }; 775 776 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 777 .cmd_rcgr = 0x28288, 778 .mnd_width = 16, 779 .hid_width = 5, 780 .parent_map = gcc_parent_map_0, 781 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 782 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 783 }; 784 785 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 786 .name = "gcc_qupv3_wrap1_s2_clk_src", 787 .parent_data = gcc_parent_data_0, 788 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 789 .ops = &clk_rcg2_ops, 790 }; 791 792 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 793 .cmd_rcgr = 0x283bc, 794 .mnd_width = 16, 795 .hid_width = 5, 796 .parent_map = gcc_parent_map_0, 797 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 798 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 799 }; 800 801 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 802 .name = "gcc_qupv3_wrap1_s3_clk_src", 803 .parent_data = gcc_parent_data_0, 804 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 805 .ops = &clk_rcg2_ops, 806 }; 807 808 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 809 .cmd_rcgr = 0x284f0, 810 .mnd_width = 16, 811 .hid_width = 5, 812 .parent_map = gcc_parent_map_0, 813 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 814 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 815 }; 816 817 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 818 .name = "gcc_qupv3_wrap1_s4_clk_src", 819 .parent_data = gcc_parent_data_0, 820 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 821 .ops = &clk_rcg2_ops, 822 }; 823 824 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 825 .cmd_rcgr = 0x28624, 826 .mnd_width = 16, 827 .hid_width = 5, 828 .parent_map = gcc_parent_map_0, 829 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 830 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 831 }; 832 833 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 834 .name = "gcc_qupv3_wrap1_s5_clk_src", 835 .parent_data = gcc_parent_data_0, 836 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 837 .ops = &clk_rcg2_ops, 838 }; 839 840 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 841 .cmd_rcgr = 0x28758, 842 .mnd_width = 16, 843 .hid_width = 5, 844 .parent_map = gcc_parent_map_0, 845 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 846 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 847 }; 848 849 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 850 .name = "gcc_qupv3_wrap1_s6_clk_src", 851 .parent_data = gcc_parent_data_0, 852 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 853 .ops = &clk_rcg2_ops, 854 }; 855 856 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 857 .cmd_rcgr = 0x2888c, 858 .mnd_width = 16, 859 .hid_width = 5, 860 .parent_map = gcc_parent_map_0, 861 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 862 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 863 }; 864 865 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 866 .name = "gcc_qupv3_wrap1_s7_clk_src", 867 .parent_data = gcc_parent_data_0, 868 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 869 .ops = &clk_rcg2_ops, 870 }; 871 872 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 873 .cmd_rcgr = 0x289c0, 874 .mnd_width = 16, 875 .hid_width = 5, 876 .parent_map = gcc_parent_map_0, 877 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 878 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 879 }; 880 881 static const struct freq_tbl ftbl_gcc_sdcc5_apps_clk_src[] = { 882 F(144000, P_BI_TCXO, 16, 3, 25), 883 F(400000, P_BI_TCXO, 12, 1, 4), 884 F(19200000, P_BI_TCXO, 1, 0, 0), 885 F(20000000, P_GCC_GPLL0_OUT_MAIN, 10, 1, 3), 886 F(25000000, P_GCC_GPLL0_OUT_MAIN, 12, 1, 2), 887 F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0), 888 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 889 F(192000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0), 890 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 891 F(384000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0), 892 { } 893 }; 894 895 static struct clk_rcg2 gcc_sdcc5_apps_clk_src = { 896 .cmd_rcgr = 0x3b034, 897 .mnd_width = 8, 898 .hid_width = 5, 899 .parent_map = gcc_parent_map_8, 900 .freq_tbl = ftbl_gcc_sdcc5_apps_clk_src, 901 .clkr.hw.init = &(const struct clk_init_data) { 902 .name = "gcc_sdcc5_apps_clk_src", 903 .parent_data = gcc_parent_data_8, 904 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 905 .ops = &clk_rcg2_ops, 906 }, 907 }; 908 909 static const struct freq_tbl ftbl_gcc_sdcc5_ice_core_clk_src[] = { 910 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 911 { } 912 }; 913 914 static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src = { 915 .cmd_rcgr = 0x3b01c, 916 .mnd_width = 0, 917 .hid_width = 5, 918 .parent_map = gcc_parent_map_2, 919 .freq_tbl = ftbl_gcc_sdcc5_ice_core_clk_src, 920 .clkr.hw.init = &(const struct clk_init_data) { 921 .name = "gcc_sdcc5_ice_core_clk_src", 922 .parent_data = gcc_parent_data_2, 923 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 924 .ops = &clk_rcg2_ops, 925 }, 926 }; 927 928 static struct clk_rcg2 gcc_sm_bus_xo_clk_src = { 929 .cmd_rcgr = 0x5b00c, 930 .mnd_width = 0, 931 .hid_width = 5, 932 .parent_map = gcc_parent_map_2, 933 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 934 .clkr.hw.init = &(const struct clk_init_data) { 935 .name = "gcc_sm_bus_xo_clk_src", 936 .parent_data = gcc_parent_data_2, 937 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 938 .ops = &clk_rcg2_ops, 939 }, 940 }; 941 942 static const struct freq_tbl ftbl_gcc_tsc_clk_src[] = { 943 F(500000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0), 944 { } 945 }; 946 947 static struct clk_rcg2 gcc_tsc_clk_src = { 948 .cmd_rcgr = 0x57010, 949 .mnd_width = 0, 950 .hid_width = 5, 951 .parent_map = gcc_parent_map_9, 952 .freq_tbl = ftbl_gcc_tsc_clk_src, 953 .clkr.hw.init = &(const struct clk_init_data) { 954 .name = "gcc_tsc_clk_src", 955 .parent_data = gcc_parent_data_9, 956 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 957 .ops = &clk_rcg2_ops, 958 }, 959 }; 960 961 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 962 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 963 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 964 { } 965 }; 966 967 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 968 .cmd_rcgr = 0x49028, 969 .mnd_width = 8, 970 .hid_width = 5, 971 .parent_map = gcc_parent_map_0, 972 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 973 .clkr.hw.init = &(const struct clk_init_data) { 974 .name = "gcc_usb30_prim_master_clk_src", 975 .parent_data = gcc_parent_data_0, 976 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 977 .ops = &clk_rcg2_ops, 978 }, 979 }; 980 981 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 982 .cmd_rcgr = 0x49044, 983 .mnd_width = 0, 984 .hid_width = 5, 985 .parent_map = gcc_parent_map_0, 986 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 987 .clkr.hw.init = &(const struct clk_init_data) { 988 .name = "gcc_usb30_prim_mock_utmi_clk_src", 989 .parent_data = gcc_parent_data_0, 990 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 991 .ops = &clk_rcg2_ops, 992 }, 993 }; 994 995 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 996 .cmd_rcgr = 0x49070, 997 .mnd_width = 0, 998 .hid_width = 5, 999 .parent_map = gcc_parent_map_3, 1000 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1001 .clkr.hw.init = &(const struct clk_init_data) { 1002 .name = "gcc_usb3_prim_phy_aux_clk_src", 1003 .parent_data = gcc_parent_data_3, 1004 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1005 .ops = &clk_rcg2_ops, 1006 }, 1007 }; 1008 1009 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1010 .reg = 0x4905c, 1011 .shift = 0, 1012 .width = 4, 1013 .clkr.hw.init = &(const struct clk_init_data) { 1014 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1015 .parent_hws = (const struct clk_hw*[]) { 1016 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1017 }, 1018 .num_parents = 1, 1019 .flags = CLK_SET_RATE_PARENT, 1020 .ops = &clk_regmap_div_ro_ops, 1021 }, 1022 }; 1023 1024 static struct clk_branch gcc_aggre_noc_ecpri_dma_clk = { 1025 .halt_reg = 0x92008, 1026 .halt_check = BRANCH_HALT_VOTED, 1027 .hwcg_reg = 0x92008, 1028 .hwcg_bit = 1, 1029 .clkr = { 1030 .enable_reg = 0x92008, 1031 .enable_mask = BIT(0), 1032 .hw.init = &(const struct clk_init_data) { 1033 .name = "gcc_aggre_noc_ecpri_dma_clk", 1034 .parent_hws = (const struct clk_hw*[]) { 1035 &gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw, 1036 }, 1037 .num_parents = 1, 1038 .flags = CLK_SET_RATE_PARENT, 1039 .ops = &clk_branch2_ops, 1040 }, 1041 }, 1042 }; 1043 1044 static struct clk_branch gcc_aggre_noc_ecpri_gsi_clk = { 1045 .halt_reg = 0x9201c, 1046 .halt_check = BRANCH_HALT_VOTED, 1047 .hwcg_reg = 0x9201c, 1048 .hwcg_bit = 1, 1049 .clkr = { 1050 .enable_reg = 0x9201c, 1051 .enable_mask = BIT(0), 1052 .hw.init = &(const struct clk_init_data) { 1053 .name = "gcc_aggre_noc_ecpri_gsi_clk", 1054 .parent_hws = (const struct clk_hw*[]) { 1055 &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, 1056 }, 1057 .num_parents = 1, 1058 .flags = CLK_SET_RATE_PARENT, 1059 .ops = &clk_branch2_ops, 1060 }, 1061 }, 1062 }; 1063 1064 static struct clk_branch gcc_boot_rom_ahb_clk = { 1065 .halt_reg = 0x48004, 1066 .halt_check = BRANCH_HALT_VOTED, 1067 .hwcg_reg = 0x48004, 1068 .hwcg_bit = 1, 1069 .clkr = { 1070 .enable_reg = 0x62000, 1071 .enable_mask = BIT(10), 1072 .hw.init = &(const struct clk_init_data) { 1073 .name = "gcc_boot_rom_ahb_clk", 1074 .ops = &clk_branch2_ops, 1075 }, 1076 }, 1077 }; 1078 1079 static struct clk_branch gcc_cfg_noc_ecpri_cc_ahb_clk = { 1080 .halt_reg = 0x3e004, 1081 .halt_check = BRANCH_HALT_VOTED, 1082 .hwcg_reg = 0x3e004, 1083 .hwcg_bit = 1, 1084 .clkr = { 1085 .enable_reg = 0x3e004, 1086 .enable_mask = BIT(0), 1087 .hw.init = &(const struct clk_init_data) { 1088 .name = "gcc_cfg_noc_ecpri_cc_ahb_clk", 1089 .ops = &clk_branch2_ops, 1090 }, 1091 }, 1092 }; 1093 1094 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1095 .halt_reg = 0x8401c, 1096 .halt_check = BRANCH_HALT_VOTED, 1097 .hwcg_reg = 0x8401c, 1098 .hwcg_bit = 1, 1099 .clkr = { 1100 .enable_reg = 0x8401c, 1101 .enable_mask = BIT(0), 1102 .hw.init = &(const struct clk_init_data) { 1103 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1104 .parent_hws = (const struct clk_hw*[]) { 1105 &gcc_usb30_prim_master_clk_src.clkr.hw, 1106 }, 1107 .num_parents = 1, 1108 .flags = CLK_SET_RATE_PARENT, 1109 .ops = &clk_branch2_ops, 1110 }, 1111 }, 1112 }; 1113 1114 static struct clk_branch gcc_ddrss_ecpri_dma_clk = { 1115 .halt_reg = 0x54030, 1116 .halt_check = BRANCH_HALT_VOTED, 1117 .hwcg_reg = 0x54030, 1118 .hwcg_bit = 1, 1119 .clkr = { 1120 .enable_reg = 0x54030, 1121 .enable_mask = BIT(0), 1122 .hw.init = &(const struct clk_init_data) { 1123 .name = "gcc_ddrss_ecpri_dma_clk", 1124 .parent_hws = (const struct clk_hw*[]) { 1125 &gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw, 1126 }, 1127 .num_parents = 1, 1128 .flags = CLK_SET_RATE_PARENT, 1129 .ops = &clk_branch2_aon_ops, 1130 }, 1131 }, 1132 }; 1133 1134 static struct clk_branch gcc_ddrss_ecpri_gsi_clk = { 1135 .halt_reg = 0x54298, 1136 .halt_check = BRANCH_HALT_VOTED, 1137 .hwcg_reg = 0x54298, 1138 .hwcg_bit = 1, 1139 .clkr = { 1140 .enable_reg = 0x54298, 1141 .enable_mask = BIT(0), 1142 .hw.init = &(const struct clk_init_data) { 1143 .name = "gcc_ddrss_ecpri_gsi_clk", 1144 .parent_hws = (const struct clk_hw*[]) { 1145 &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, 1146 }, 1147 .num_parents = 1, 1148 .flags = CLK_SET_RATE_PARENT, 1149 .ops = &clk_branch2_aon_ops, 1150 }, 1151 }, 1152 }; 1153 1154 static struct clk_branch gcc_ecpri_ahb_clk = { 1155 .halt_reg = 0x3a008, 1156 .halt_check = BRANCH_HALT_VOTED, 1157 .hwcg_reg = 0x3a008, 1158 .hwcg_bit = 1, 1159 .clkr = { 1160 .enable_reg = 0x3a008, 1161 .enable_mask = BIT(0), 1162 .hw.init = &(const struct clk_init_data) { 1163 .name = "gcc_ecpri_ahb_clk", 1164 .ops = &clk_branch2_ops, 1165 }, 1166 }, 1167 }; 1168 1169 static struct clk_branch gcc_ecpri_cc_gpll0_clk_src = { 1170 .halt_check = BRANCH_HALT_DELAY, 1171 .clkr = { 1172 .enable_reg = 0x62010, 1173 .enable_mask = BIT(0), 1174 .hw.init = &(const struct clk_init_data) { 1175 .name = "gcc_ecpri_cc_gpll0_clk_src", 1176 .parent_hws = (const struct clk_hw*[]) { 1177 &gcc_gpll0.clkr.hw, 1178 }, 1179 .num_parents = 1, 1180 .flags = CLK_SET_RATE_PARENT, 1181 .ops = &clk_branch2_ops, 1182 }, 1183 }, 1184 }; 1185 1186 static struct clk_branch gcc_ecpri_cc_gpll1_even_clk_src = { 1187 .halt_check = BRANCH_HALT_DELAY, 1188 .clkr = { 1189 .enable_reg = 0x62010, 1190 .enable_mask = BIT(1), 1191 .hw.init = &(const struct clk_init_data) { 1192 .name = "gcc_ecpri_cc_gpll1_even_clk_src", 1193 .parent_hws = (const struct clk_hw*[]) { 1194 &gcc_gpll1_out_even.clkr.hw, 1195 }, 1196 .num_parents = 1, 1197 .flags = CLK_SET_RATE_PARENT, 1198 .ops = &clk_branch2_ops, 1199 }, 1200 }, 1201 }; 1202 1203 static struct clk_branch gcc_ecpri_cc_gpll2_even_clk_src = { 1204 .halt_check = BRANCH_HALT_DELAY, 1205 .clkr = { 1206 .enable_reg = 0x62010, 1207 .enable_mask = BIT(2), 1208 .hw.init = &(const struct clk_init_data) { 1209 .name = "gcc_ecpri_cc_gpll2_even_clk_src", 1210 .parent_hws = (const struct clk_hw*[]) { 1211 &gcc_gpll2_out_even.clkr.hw, 1212 }, 1213 .num_parents = 1, 1214 .flags = CLK_SET_RATE_PARENT, 1215 .ops = &clk_branch2_ops, 1216 }, 1217 }, 1218 }; 1219 1220 static struct clk_branch gcc_ecpri_cc_gpll3_clk_src = { 1221 .halt_check = BRANCH_HALT_DELAY, 1222 .clkr = { 1223 .enable_reg = 0x62010, 1224 .enable_mask = BIT(3), 1225 .hw.init = &(const struct clk_init_data) { 1226 .name = "gcc_ecpri_cc_gpll3_clk_src", 1227 .parent_hws = (const struct clk_hw*[]) { 1228 &gcc_gpll3.clkr.hw, 1229 }, 1230 .num_parents = 1, 1231 .flags = CLK_SET_RATE_PARENT, 1232 .ops = &clk_branch2_ops, 1233 }, 1234 }, 1235 }; 1236 1237 static struct clk_branch gcc_ecpri_cc_gpll4_clk_src = { 1238 .halt_check = BRANCH_HALT_DELAY, 1239 .clkr = { 1240 .enable_reg = 0x62010, 1241 .enable_mask = BIT(4), 1242 .hw.init = &(const struct clk_init_data) { 1243 .name = "gcc_ecpri_cc_gpll4_clk_src", 1244 .parent_hws = (const struct clk_hw*[]) { 1245 &gcc_gpll4.clkr.hw, 1246 }, 1247 .num_parents = 1, 1248 .flags = CLK_SET_RATE_PARENT, 1249 .ops = &clk_branch2_ops, 1250 }, 1251 }, 1252 }; 1253 1254 static struct clk_branch gcc_ecpri_cc_gpll5_even_clk_src = { 1255 .halt_check = BRANCH_HALT_DELAY, 1256 .clkr = { 1257 .enable_reg = 0x62010, 1258 .enable_mask = BIT(5), 1259 .hw.init = &(const struct clk_init_data) { 1260 .name = "gcc_ecpri_cc_gpll5_even_clk_src", 1261 .parent_hws = (const struct clk_hw*[]) { 1262 &gcc_gpll5_out_even.clkr.hw, 1263 }, 1264 .num_parents = 1, 1265 .flags = CLK_SET_RATE_PARENT, 1266 .ops = &clk_branch2_ops, 1267 }, 1268 }, 1269 }; 1270 1271 static struct clk_branch gcc_ecpri_xo_clk = { 1272 .halt_reg = 0x3a004, 1273 .halt_check = BRANCH_HALT, 1274 .clkr = { 1275 .enable_reg = 0x3a004, 1276 .enable_mask = BIT(0), 1277 .hw.init = &(const struct clk_init_data) { 1278 .name = "gcc_ecpri_xo_clk", 1279 .ops = &clk_branch2_ops, 1280 }, 1281 }, 1282 }; 1283 1284 static struct clk_branch gcc_eth_100g_c2c_hm_apb_clk = { 1285 .halt_reg = 0x39010, 1286 .halt_check = BRANCH_HALT, 1287 .clkr = { 1288 .enable_reg = 0x39010, 1289 .enable_mask = BIT(0), 1290 .hw.init = &(const struct clk_init_data) { 1291 .name = "gcc_eth_100g_c2c_hm_apb_clk", 1292 .ops = &clk_branch2_ops, 1293 }, 1294 }, 1295 }; 1296 1297 static struct clk_branch gcc_eth_100g_fh_hm_apb_0_clk = { 1298 .halt_reg = 0x39004, 1299 .halt_check = BRANCH_HALT, 1300 .clkr = { 1301 .enable_reg = 0x39004, 1302 .enable_mask = BIT(0), 1303 .hw.init = &(const struct clk_init_data) { 1304 .name = "gcc_eth_100g_fh_hm_apb_0_clk", 1305 .ops = &clk_branch2_ops, 1306 }, 1307 }, 1308 }; 1309 1310 static struct clk_branch gcc_eth_100g_fh_hm_apb_1_clk = { 1311 .halt_reg = 0x39008, 1312 .halt_check = BRANCH_HALT, 1313 .clkr = { 1314 .enable_reg = 0x39008, 1315 .enable_mask = BIT(0), 1316 .hw.init = &(const struct clk_init_data) { 1317 .name = "gcc_eth_100g_fh_hm_apb_1_clk", 1318 .ops = &clk_branch2_ops, 1319 }, 1320 }, 1321 }; 1322 1323 static struct clk_branch gcc_eth_100g_fh_hm_apb_2_clk = { 1324 .halt_reg = 0x3900c, 1325 .halt_check = BRANCH_HALT, 1326 .clkr = { 1327 .enable_reg = 0x3900c, 1328 .enable_mask = BIT(0), 1329 .hw.init = &(const struct clk_init_data) { 1330 .name = "gcc_eth_100g_fh_hm_apb_2_clk", 1331 .ops = &clk_branch2_ops, 1332 }, 1333 }, 1334 }; 1335 1336 static struct clk_branch gcc_eth_dbg_c2c_hm_apb_clk = { 1337 .halt_reg = 0x39014, 1338 .halt_check = BRANCH_HALT, 1339 .clkr = { 1340 .enable_reg = 0x39014, 1341 .enable_mask = BIT(0), 1342 .hw.init = &(const struct clk_init_data) { 1343 .name = "gcc_eth_dbg_c2c_hm_apb_clk", 1344 .ops = &clk_branch2_ops, 1345 }, 1346 }, 1347 }; 1348 1349 static struct clk_branch gcc_eth_dbg_snoc_axi_clk = { 1350 .halt_reg = 0x3901c, 1351 .halt_check = BRANCH_HALT_VOTED, 1352 .hwcg_reg = 0x3901c, 1353 .hwcg_bit = 1, 1354 .clkr = { 1355 .enable_reg = 0x3901c, 1356 .enable_mask = BIT(0), 1357 .hw.init = &(const struct clk_init_data) { 1358 .name = "gcc_eth_dbg_snoc_axi_clk", 1359 .ops = &clk_branch2_ops, 1360 }, 1361 }, 1362 }; 1363 1364 static struct clk_branch gcc_gemnoc_pcie_qx_clk = { 1365 .halt_reg = 0x5402c, 1366 .halt_check = BRANCH_HALT_VOTED, 1367 .hwcg_reg = 0x5402c, 1368 .hwcg_bit = 1, 1369 .clkr = { 1370 .enable_reg = 0x62008, 1371 .enable_mask = BIT(0), 1372 .hw.init = &(const struct clk_init_data) { 1373 .name = "gcc_gemnoc_pcie_qx_clk", 1374 .ops = &clk_branch2_aon_ops, 1375 }, 1376 }, 1377 }; 1378 1379 static struct clk_branch gcc_gp1_clk = { 1380 .halt_reg = 0x74000, 1381 .halt_check = BRANCH_HALT, 1382 .clkr = { 1383 .enable_reg = 0x74000, 1384 .enable_mask = BIT(0), 1385 .hw.init = &(const struct clk_init_data) { 1386 .name = "gcc_gp1_clk", 1387 .parent_hws = (const struct clk_hw*[]) { 1388 &gcc_gp1_clk_src.clkr.hw, 1389 }, 1390 .num_parents = 1, 1391 .flags = CLK_SET_RATE_PARENT, 1392 .ops = &clk_branch2_ops, 1393 }, 1394 }, 1395 }; 1396 1397 static struct clk_branch gcc_gp2_clk = { 1398 .halt_reg = 0x75000, 1399 .halt_check = BRANCH_HALT, 1400 .clkr = { 1401 .enable_reg = 0x75000, 1402 .enable_mask = BIT(0), 1403 .hw.init = &(const struct clk_init_data) { 1404 .name = "gcc_gp2_clk", 1405 .parent_hws = (const struct clk_hw*[]) { 1406 &gcc_gp2_clk_src.clkr.hw, 1407 }, 1408 .num_parents = 1, 1409 .flags = CLK_SET_RATE_PARENT, 1410 .ops = &clk_branch2_ops, 1411 }, 1412 }, 1413 }; 1414 1415 static struct clk_branch gcc_gp3_clk = { 1416 .halt_reg = 0x76000, 1417 .halt_check = BRANCH_HALT, 1418 .clkr = { 1419 .enable_reg = 0x76000, 1420 .enable_mask = BIT(0), 1421 .hw.init = &(const struct clk_init_data) { 1422 .name = "gcc_gp3_clk", 1423 .parent_hws = (const struct clk_hw*[]) { 1424 &gcc_gp3_clk_src.clkr.hw, 1425 }, 1426 .num_parents = 1, 1427 .flags = CLK_SET_RATE_PARENT, 1428 .ops = &clk_branch2_ops, 1429 }, 1430 }, 1431 }; 1432 1433 static struct clk_branch gcc_pcie_0_aux_clk = { 1434 .halt_reg = 0x9d030, 1435 .halt_check = BRANCH_HALT_VOTED, 1436 .hwcg_reg = 0x9d030, 1437 .hwcg_bit = 1, 1438 .clkr = { 1439 .enable_reg = 0x62000, 1440 .enable_mask = BIT(29), 1441 .hw.init = &(const struct clk_init_data) { 1442 .name = "gcc_pcie_0_aux_clk", 1443 .parent_hws = (const struct clk_hw*[]) { 1444 &gcc_pcie_0_aux_clk_src.clkr.hw, 1445 }, 1446 .num_parents = 1, 1447 .flags = CLK_SET_RATE_PARENT, 1448 .ops = &clk_branch2_ops, 1449 }, 1450 }, 1451 }; 1452 1453 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1454 .halt_reg = 0x9d02c, 1455 .halt_check = BRANCH_HALT_VOTED, 1456 .hwcg_reg = 0x9d02c, 1457 .hwcg_bit = 1, 1458 .clkr = { 1459 .enable_reg = 0x62000, 1460 .enable_mask = BIT(28), 1461 .hw.init = &(const struct clk_init_data) { 1462 .name = "gcc_pcie_0_cfg_ahb_clk", 1463 .ops = &clk_branch2_ops, 1464 }, 1465 }, 1466 }; 1467 1468 static struct clk_branch gcc_pcie_0_clkref_en = { 1469 .halt_reg = 0x9c004, 1470 .halt_check = BRANCH_HALT, 1471 .clkr = { 1472 .enable_reg = 0x9c004, 1473 .enable_mask = BIT(0), 1474 .hw.init = &(const struct clk_init_data) { 1475 .name = "gcc_pcie_0_clkref_en", 1476 .ops = &clk_branch2_ops, 1477 }, 1478 }, 1479 }; 1480 1481 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1482 .halt_reg = 0x9d024, 1483 .halt_check = BRANCH_HALT_SKIP, 1484 .hwcg_reg = 0x9d024, 1485 .hwcg_bit = 1, 1486 .clkr = { 1487 .enable_reg = 0x62000, 1488 .enable_mask = BIT(27), 1489 .hw.init = &(const struct clk_init_data) { 1490 .name = "gcc_pcie_0_mstr_axi_clk", 1491 .ops = &clk_branch2_ops, 1492 }, 1493 }, 1494 }; 1495 1496 static struct clk_branch gcc_pcie_0_phy_aux_clk = { 1497 .halt_reg = 0x9d038, 1498 .halt_check = BRANCH_HALT_VOTED, 1499 .hwcg_reg = 0x9d038, 1500 .hwcg_bit = 1, 1501 .clkr = { 1502 .enable_reg = 0x62000, 1503 .enable_mask = BIT(24), 1504 .hw.init = &(const struct clk_init_data) { 1505 .name = "gcc_pcie_0_phy_aux_clk", 1506 .parent_hws = (const struct clk_hw*[]) { 1507 &gcc_pcie_0_phy_aux_clk_src.clkr.hw, 1508 }, 1509 .num_parents = 1, 1510 .flags = CLK_SET_RATE_PARENT, 1511 .ops = &clk_branch2_ops, 1512 }, 1513 }, 1514 }; 1515 1516 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 1517 .halt_reg = 0x9d048, 1518 .halt_check = BRANCH_HALT_VOTED, 1519 .hwcg_reg = 0x9d048, 1520 .hwcg_bit = 1, 1521 .clkr = { 1522 .enable_reg = 0x62000, 1523 .enable_mask = BIT(23), 1524 .hw.init = &(const struct clk_init_data) { 1525 .name = "gcc_pcie_0_phy_rchng_clk", 1526 .parent_hws = (const struct clk_hw*[]) { 1527 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1528 }, 1529 .num_parents = 1, 1530 .flags = CLK_SET_RATE_PARENT, 1531 .ops = &clk_branch2_ops, 1532 }, 1533 }, 1534 }; 1535 1536 static struct clk_branch gcc_pcie_0_pipe_clk = { 1537 .halt_reg = 0x9d040, 1538 .halt_check = BRANCH_HALT_VOTED, 1539 .hwcg_reg = 0x9d040, 1540 .hwcg_bit = 1, 1541 .clkr = { 1542 .enable_reg = 0x62000, 1543 .enable_mask = BIT(30), 1544 .hw.init = &(const struct clk_init_data) { 1545 .name = "gcc_pcie_0_pipe_clk", 1546 .parent_hws = (const struct clk_hw*[]) { 1547 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1548 }, 1549 .num_parents = 1, 1550 .flags = CLK_SET_RATE_PARENT, 1551 .ops = &clk_branch2_ops, 1552 }, 1553 }, 1554 }; 1555 1556 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1557 .halt_reg = 0x9d01c, 1558 .halt_check = BRANCH_HALT_VOTED, 1559 .hwcg_reg = 0x9d01c, 1560 .hwcg_bit = 1, 1561 .clkr = { 1562 .enable_reg = 0x62000, 1563 .enable_mask = BIT(26), 1564 .hw.init = &(const struct clk_init_data) { 1565 .name = "gcc_pcie_0_slv_axi_clk", 1566 .ops = &clk_branch2_ops, 1567 }, 1568 }, 1569 }; 1570 1571 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1572 .halt_reg = 0x9d018, 1573 .halt_check = BRANCH_HALT_VOTED, 1574 .hwcg_reg = 0x9d018, 1575 .hwcg_bit = 1, 1576 .clkr = { 1577 .enable_reg = 0x62000, 1578 .enable_mask = BIT(25), 1579 .hw.init = &(const struct clk_init_data) { 1580 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1581 .ops = &clk_branch2_ops, 1582 }, 1583 }, 1584 }; 1585 1586 static struct clk_branch gcc_pdm2_clk = { 1587 .halt_reg = 0x4300c, 1588 .halt_check = BRANCH_HALT, 1589 .clkr = { 1590 .enable_reg = 0x4300c, 1591 .enable_mask = BIT(0), 1592 .hw.init = &(const struct clk_init_data) { 1593 .name = "gcc_pdm2_clk", 1594 .parent_hws = (const struct clk_hw*[]) { 1595 &gcc_pdm2_clk_src.clkr.hw, 1596 }, 1597 .num_parents = 1, 1598 .flags = CLK_SET_RATE_PARENT, 1599 .ops = &clk_branch2_ops, 1600 }, 1601 }, 1602 }; 1603 1604 static struct clk_branch gcc_pdm_ahb_clk = { 1605 .halt_reg = 0x43004, 1606 .halt_check = BRANCH_HALT_VOTED, 1607 .hwcg_reg = 0x43004, 1608 .hwcg_bit = 1, 1609 .clkr = { 1610 .enable_reg = 0x43004, 1611 .enable_mask = BIT(0), 1612 .hw.init = &(const struct clk_init_data) { 1613 .name = "gcc_pdm_ahb_clk", 1614 .ops = &clk_branch2_ops, 1615 }, 1616 }, 1617 }; 1618 1619 static struct clk_branch gcc_pdm_xo4_clk = { 1620 .halt_reg = 0x43008, 1621 .halt_check = BRANCH_HALT, 1622 .clkr = { 1623 .enable_reg = 0x43008, 1624 .enable_mask = BIT(0), 1625 .hw.init = &(const struct clk_init_data) { 1626 .name = "gcc_pdm_xo4_clk", 1627 .ops = &clk_branch2_ops, 1628 }, 1629 }, 1630 }; 1631 1632 static struct clk_branch gcc_qmip_anoc_pcie_clk = { 1633 .halt_reg = 0x84044, 1634 .halt_check = BRANCH_HALT_VOTED, 1635 .hwcg_reg = 0x84044, 1636 .hwcg_bit = 1, 1637 .clkr = { 1638 .enable_reg = 0x84044, 1639 .enable_mask = BIT(0), 1640 .hw.init = &(const struct clk_init_data) { 1641 .name = "gcc_qmip_anoc_pcie_clk", 1642 .ops = &clk_branch2_ops, 1643 }, 1644 }, 1645 }; 1646 1647 static struct clk_branch gcc_qmip_ecpri_dma0_clk = { 1648 .halt_reg = 0x84038, 1649 .halt_check = BRANCH_HALT_VOTED, 1650 .hwcg_reg = 0x84038, 1651 .hwcg_bit = 1, 1652 .clkr = { 1653 .enable_reg = 0x84038, 1654 .enable_mask = BIT(0), 1655 .hw.init = &(const struct clk_init_data) { 1656 .name = "gcc_qmip_ecpri_dma0_clk", 1657 .ops = &clk_branch2_ops, 1658 }, 1659 }, 1660 }; 1661 1662 static struct clk_branch gcc_qmip_ecpri_dma1_clk = { 1663 .halt_reg = 0x8403c, 1664 .halt_check = BRANCH_HALT_VOTED, 1665 .hwcg_reg = 0x8403c, 1666 .hwcg_bit = 1, 1667 .clkr = { 1668 .enable_reg = 0x8403c, 1669 .enable_mask = BIT(0), 1670 .hw.init = &(const struct clk_init_data) { 1671 .name = "gcc_qmip_ecpri_dma1_clk", 1672 .ops = &clk_branch2_ops, 1673 }, 1674 }, 1675 }; 1676 1677 static struct clk_branch gcc_qmip_ecpri_gsi_clk = { 1678 .halt_reg = 0x84040, 1679 .halt_check = BRANCH_HALT_VOTED, 1680 .hwcg_reg = 0x84040, 1681 .hwcg_bit = 1, 1682 .clkr = { 1683 .enable_reg = 0x84040, 1684 .enable_mask = BIT(0), 1685 .hw.init = &(const struct clk_init_data) { 1686 .name = "gcc_qmip_ecpri_gsi_clk", 1687 .ops = &clk_branch2_ops, 1688 }, 1689 }, 1690 }; 1691 1692 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 1693 .halt_reg = 0x27018, 1694 .halt_check = BRANCH_HALT_VOTED, 1695 .clkr = { 1696 .enable_reg = 0x62008, 1697 .enable_mask = BIT(9), 1698 .hw.init = &(const struct clk_init_data) { 1699 .name = "gcc_qupv3_wrap0_core_2x_clk", 1700 .ops = &clk_branch2_ops, 1701 }, 1702 }, 1703 }; 1704 1705 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 1706 .halt_reg = 0x2700c, 1707 .halt_check = BRANCH_HALT_VOTED, 1708 .clkr = { 1709 .enable_reg = 0x62008, 1710 .enable_mask = BIT(8), 1711 .hw.init = &(const struct clk_init_data) { 1712 .name = "gcc_qupv3_wrap0_core_clk", 1713 .ops = &clk_branch2_ops, 1714 }, 1715 }, 1716 }; 1717 1718 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 1719 .halt_reg = 0x2714c, 1720 .halt_check = BRANCH_HALT_VOTED, 1721 .clkr = { 1722 .enable_reg = 0x62008, 1723 .enable_mask = BIT(10), 1724 .hw.init = &(const struct clk_init_data) { 1725 .name = "gcc_qupv3_wrap0_s0_clk", 1726 .parent_hws = (const struct clk_hw*[]) { 1727 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 1728 }, 1729 .num_parents = 1, 1730 .flags = CLK_SET_RATE_PARENT, 1731 .ops = &clk_branch2_ops, 1732 }, 1733 }, 1734 }; 1735 1736 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 1737 .halt_reg = 0x27280, 1738 .halt_check = BRANCH_HALT_VOTED, 1739 .clkr = { 1740 .enable_reg = 0x62008, 1741 .enable_mask = BIT(11), 1742 .hw.init = &(const struct clk_init_data) { 1743 .name = "gcc_qupv3_wrap0_s1_clk", 1744 .parent_hws = (const struct clk_hw*[]) { 1745 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 1746 }, 1747 .num_parents = 1, 1748 .flags = CLK_SET_RATE_PARENT, 1749 .ops = &clk_branch2_ops, 1750 }, 1751 }, 1752 }; 1753 1754 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 1755 .halt_reg = 0x273b4, 1756 .halt_check = BRANCH_HALT_VOTED, 1757 .clkr = { 1758 .enable_reg = 0x62008, 1759 .enable_mask = BIT(12), 1760 .hw.init = &(const struct clk_init_data) { 1761 .name = "gcc_qupv3_wrap0_s2_clk", 1762 .parent_hws = (const struct clk_hw*[]) { 1763 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 1764 }, 1765 .num_parents = 1, 1766 .flags = CLK_SET_RATE_PARENT, 1767 .ops = &clk_branch2_ops, 1768 }, 1769 }, 1770 }; 1771 1772 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 1773 .halt_reg = 0x274e8, 1774 .halt_check = BRANCH_HALT_VOTED, 1775 .clkr = { 1776 .enable_reg = 0x62008, 1777 .enable_mask = BIT(13), 1778 .hw.init = &(const struct clk_init_data) { 1779 .name = "gcc_qupv3_wrap0_s3_clk", 1780 .parent_hws = (const struct clk_hw*[]) { 1781 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 1782 }, 1783 .num_parents = 1, 1784 .flags = CLK_SET_RATE_PARENT, 1785 .ops = &clk_branch2_ops, 1786 }, 1787 }, 1788 }; 1789 1790 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 1791 .halt_reg = 0x2761c, 1792 .halt_check = BRANCH_HALT_VOTED, 1793 .clkr = { 1794 .enable_reg = 0x62008, 1795 .enable_mask = BIT(14), 1796 .hw.init = &(const struct clk_init_data) { 1797 .name = "gcc_qupv3_wrap0_s4_clk", 1798 .parent_hws = (const struct clk_hw*[]) { 1799 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 1800 }, 1801 .num_parents = 1, 1802 .flags = CLK_SET_RATE_PARENT, 1803 .ops = &clk_branch2_ops, 1804 }, 1805 }, 1806 }; 1807 1808 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 1809 .halt_reg = 0x27750, 1810 .halt_check = BRANCH_HALT_VOTED, 1811 .clkr = { 1812 .enable_reg = 0x62008, 1813 .enable_mask = BIT(15), 1814 .hw.init = &(const struct clk_init_data) { 1815 .name = "gcc_qupv3_wrap0_s5_clk", 1816 .parent_hws = (const struct clk_hw*[]) { 1817 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 1818 }, 1819 .num_parents = 1, 1820 .flags = CLK_SET_RATE_PARENT, 1821 .ops = &clk_branch2_ops, 1822 }, 1823 }, 1824 }; 1825 1826 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 1827 .halt_reg = 0x27884, 1828 .halt_check = BRANCH_HALT_VOTED, 1829 .clkr = { 1830 .enable_reg = 0x62008, 1831 .enable_mask = BIT(16), 1832 .hw.init = &(const struct clk_init_data) { 1833 .name = "gcc_qupv3_wrap0_s6_clk", 1834 .parent_hws = (const struct clk_hw*[]) { 1835 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 1836 }, 1837 .num_parents = 1, 1838 .flags = CLK_SET_RATE_PARENT, 1839 .ops = &clk_branch2_ops, 1840 }, 1841 }, 1842 }; 1843 1844 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 1845 .halt_reg = 0x279b8, 1846 .halt_check = BRANCH_HALT_VOTED, 1847 .clkr = { 1848 .enable_reg = 0x62008, 1849 .enable_mask = BIT(17), 1850 .hw.init = &(const struct clk_init_data) { 1851 .name = "gcc_qupv3_wrap0_s7_clk", 1852 .parent_hws = (const struct clk_hw*[]) { 1853 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 1854 }, 1855 .num_parents = 1, 1856 .flags = CLK_SET_RATE_PARENT, 1857 .ops = &clk_branch2_ops, 1858 }, 1859 }, 1860 }; 1861 1862 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 1863 .halt_reg = 0x28018, 1864 .halt_check = BRANCH_HALT_VOTED, 1865 .clkr = { 1866 .enable_reg = 0x62008, 1867 .enable_mask = BIT(18), 1868 .hw.init = &(const struct clk_init_data) { 1869 .name = "gcc_qupv3_wrap1_core_2x_clk", 1870 .ops = &clk_branch2_ops, 1871 }, 1872 }, 1873 }; 1874 1875 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 1876 .halt_reg = 0x2800c, 1877 .halt_check = BRANCH_HALT_VOTED, 1878 .clkr = { 1879 .enable_reg = 0x62008, 1880 .enable_mask = BIT(19), 1881 .hw.init = &(const struct clk_init_data) { 1882 .name = "gcc_qupv3_wrap1_core_clk", 1883 .ops = &clk_branch2_ops, 1884 }, 1885 }, 1886 }; 1887 1888 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 1889 .halt_reg = 0x2814c, 1890 .halt_check = BRANCH_HALT_VOTED, 1891 .clkr = { 1892 .enable_reg = 0x62008, 1893 .enable_mask = BIT(22), 1894 .hw.init = &(const struct clk_init_data) { 1895 .name = "gcc_qupv3_wrap1_s0_clk", 1896 .parent_hws = (const struct clk_hw*[]) { 1897 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 1898 }, 1899 .num_parents = 1, 1900 .flags = CLK_SET_RATE_PARENT, 1901 .ops = &clk_branch2_ops, 1902 }, 1903 }, 1904 }; 1905 1906 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 1907 .halt_reg = 0x28280, 1908 .halt_check = BRANCH_HALT_VOTED, 1909 .clkr = { 1910 .enable_reg = 0x62008, 1911 .enable_mask = BIT(23), 1912 .hw.init = &(const struct clk_init_data) { 1913 .name = "gcc_qupv3_wrap1_s1_clk", 1914 .parent_hws = (const struct clk_hw*[]) { 1915 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 1916 }, 1917 .num_parents = 1, 1918 .flags = CLK_SET_RATE_PARENT, 1919 .ops = &clk_branch2_ops, 1920 }, 1921 }, 1922 }; 1923 1924 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 1925 .halt_reg = 0x283b4, 1926 .halt_check = BRANCH_HALT_VOTED, 1927 .clkr = { 1928 .enable_reg = 0x62008, 1929 .enable_mask = BIT(24), 1930 .hw.init = &(const struct clk_init_data) { 1931 .name = "gcc_qupv3_wrap1_s2_clk", 1932 .parent_hws = (const struct clk_hw*[]) { 1933 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 1934 }, 1935 .num_parents = 1, 1936 .flags = CLK_SET_RATE_PARENT, 1937 .ops = &clk_branch2_ops, 1938 }, 1939 }, 1940 }; 1941 1942 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 1943 .halt_reg = 0x284e8, 1944 .halt_check = BRANCH_HALT_VOTED, 1945 .clkr = { 1946 .enable_reg = 0x62008, 1947 .enable_mask = BIT(25), 1948 .hw.init = &(const struct clk_init_data) { 1949 .name = "gcc_qupv3_wrap1_s3_clk", 1950 .parent_hws = (const struct clk_hw*[]) { 1951 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 1952 }, 1953 .num_parents = 1, 1954 .flags = CLK_SET_RATE_PARENT, 1955 .ops = &clk_branch2_ops, 1956 }, 1957 }, 1958 }; 1959 1960 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 1961 .halt_reg = 0x2861c, 1962 .halt_check = BRANCH_HALT_VOTED, 1963 .clkr = { 1964 .enable_reg = 0x62008, 1965 .enable_mask = BIT(26), 1966 .hw.init = &(const struct clk_init_data) { 1967 .name = "gcc_qupv3_wrap1_s4_clk", 1968 .parent_hws = (const struct clk_hw*[]) { 1969 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 1970 }, 1971 .num_parents = 1, 1972 .flags = CLK_SET_RATE_PARENT, 1973 .ops = &clk_branch2_ops, 1974 }, 1975 }, 1976 }; 1977 1978 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 1979 .halt_reg = 0x28750, 1980 .halt_check = BRANCH_HALT_VOTED, 1981 .clkr = { 1982 .enable_reg = 0x62008, 1983 .enable_mask = BIT(27), 1984 .hw.init = &(const struct clk_init_data) { 1985 .name = "gcc_qupv3_wrap1_s5_clk", 1986 .parent_hws = (const struct clk_hw*[]) { 1987 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 1988 }, 1989 .num_parents = 1, 1990 .flags = CLK_SET_RATE_PARENT, 1991 .ops = &clk_branch2_ops, 1992 }, 1993 }, 1994 }; 1995 1996 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 1997 .halt_reg = 0x28884, 1998 .halt_check = BRANCH_HALT_VOTED, 1999 .clkr = { 2000 .enable_reg = 0x62008, 2001 .enable_mask = BIT(28), 2002 .hw.init = &(const struct clk_init_data) { 2003 .name = "gcc_qupv3_wrap1_s6_clk", 2004 .parent_hws = (const struct clk_hw*[]) { 2005 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 2006 }, 2007 .num_parents = 1, 2008 .flags = CLK_SET_RATE_PARENT, 2009 .ops = &clk_branch2_ops, 2010 }, 2011 }, 2012 }; 2013 2014 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 2015 .halt_reg = 0x289b8, 2016 .halt_check = BRANCH_HALT_VOTED, 2017 .clkr = { 2018 .enable_reg = 0x62008, 2019 .enable_mask = BIT(29), 2020 .hw.init = &(const struct clk_init_data) { 2021 .name = "gcc_qupv3_wrap1_s7_clk", 2022 .parent_hws = (const struct clk_hw*[]) { 2023 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 2024 }, 2025 .num_parents = 1, 2026 .flags = CLK_SET_RATE_PARENT, 2027 .ops = &clk_branch2_ops, 2028 }, 2029 }, 2030 }; 2031 2032 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2033 .halt_reg = 0x27004, 2034 .halt_check = BRANCH_HALT_VOTED, 2035 .hwcg_reg = 0x27004, 2036 .hwcg_bit = 1, 2037 .clkr = { 2038 .enable_reg = 0x62008, 2039 .enable_mask = BIT(6), 2040 .hw.init = &(const struct clk_init_data) { 2041 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2042 .ops = &clk_branch2_ops, 2043 }, 2044 }, 2045 }; 2046 2047 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2048 .halt_reg = 0x27008, 2049 .halt_check = BRANCH_HALT_VOTED, 2050 .hwcg_reg = 0x27008, 2051 .hwcg_bit = 1, 2052 .clkr = { 2053 .enable_reg = 0x62008, 2054 .enable_mask = BIT(7), 2055 .hw.init = &(const struct clk_init_data) { 2056 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2057 .ops = &clk_branch2_ops, 2058 }, 2059 }, 2060 }; 2061 2062 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2063 .halt_reg = 0x28004, 2064 .halt_check = BRANCH_HALT_VOTED, 2065 .hwcg_reg = 0x28004, 2066 .hwcg_bit = 1, 2067 .clkr = { 2068 .enable_reg = 0x62008, 2069 .enable_mask = BIT(20), 2070 .hw.init = &(const struct clk_init_data) { 2071 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2072 .ops = &clk_branch2_ops, 2073 }, 2074 }, 2075 }; 2076 2077 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2078 .halt_reg = 0x28008, 2079 .halt_check = BRANCH_HALT_VOTED, 2080 .hwcg_reg = 0x28008, 2081 .hwcg_bit = 1, 2082 .clkr = { 2083 .enable_reg = 0x62008, 2084 .enable_mask = BIT(21), 2085 .hw.init = &(const struct clk_init_data) { 2086 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2087 .ops = &clk_branch2_ops, 2088 }, 2089 }, 2090 }; 2091 2092 static struct clk_branch gcc_sdcc5_ahb_clk = { 2093 .halt_reg = 0x3b00c, 2094 .halt_check = BRANCH_HALT, 2095 .clkr = { 2096 .enable_reg = 0x3b00c, 2097 .enable_mask = BIT(0), 2098 .hw.init = &(const struct clk_init_data) { 2099 .name = "gcc_sdcc5_ahb_clk", 2100 .ops = &clk_branch2_ops, 2101 }, 2102 }, 2103 }; 2104 2105 static struct clk_branch gcc_sdcc5_apps_clk = { 2106 .halt_reg = 0x3b004, 2107 .halt_check = BRANCH_HALT, 2108 .clkr = { 2109 .enable_reg = 0x3b004, 2110 .enable_mask = BIT(0), 2111 .hw.init = &(const struct clk_init_data) { 2112 .name = "gcc_sdcc5_apps_clk", 2113 .parent_hws = (const struct clk_hw*[]) { 2114 &gcc_sdcc5_apps_clk_src.clkr.hw, 2115 }, 2116 .num_parents = 1, 2117 .flags = CLK_SET_RATE_PARENT, 2118 .ops = &clk_branch2_ops, 2119 }, 2120 }, 2121 }; 2122 2123 static struct clk_branch gcc_sdcc5_ice_core_clk = { 2124 .halt_reg = 0x3b010, 2125 .halt_check = BRANCH_HALT, 2126 .clkr = { 2127 .enable_reg = 0x3b010, 2128 .enable_mask = BIT(0), 2129 .hw.init = &(const struct clk_init_data) { 2130 .name = "gcc_sdcc5_ice_core_clk", 2131 .parent_hws = (const struct clk_hw*[]) { 2132 &gcc_sdcc5_ice_core_clk_src.clkr.hw, 2133 }, 2134 .num_parents = 1, 2135 .flags = CLK_SET_RATE_PARENT, 2136 .ops = &clk_branch2_ops, 2137 }, 2138 }, 2139 }; 2140 2141 static struct clk_branch gcc_sm_bus_ahb_clk = { 2142 .halt_reg = 0x5b004, 2143 .halt_check = BRANCH_HALT, 2144 .clkr = { 2145 .enable_reg = 0x5b004, 2146 .enable_mask = BIT(0), 2147 .hw.init = &(const struct clk_init_data) { 2148 .name = "gcc_sm_bus_ahb_clk", 2149 .ops = &clk_branch2_ops, 2150 }, 2151 }, 2152 }; 2153 2154 static struct clk_branch gcc_sm_bus_xo_clk = { 2155 .halt_reg = 0x5b008, 2156 .halt_check = BRANCH_HALT, 2157 .clkr = { 2158 .enable_reg = 0x5b008, 2159 .enable_mask = BIT(0), 2160 .hw.init = &(const struct clk_init_data) { 2161 .name = "gcc_sm_bus_xo_clk", 2162 .parent_hws = (const struct clk_hw*[]) { 2163 &gcc_sm_bus_xo_clk_src.clkr.hw, 2164 }, 2165 .num_parents = 1, 2166 .flags = CLK_SET_RATE_PARENT, 2167 .ops = &clk_branch2_ops, 2168 }, 2169 }, 2170 }; 2171 2172 static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_qx_clk = { 2173 .halt_reg = 0x9200c, 2174 .halt_check = BRANCH_HALT_SKIP, 2175 .hwcg_reg = 0x9200c, 2176 .hwcg_bit = 1, 2177 .clkr = { 2178 .enable_reg = 0x62000, 2179 .enable_mask = BIT(11), 2180 .hw.init = &(const struct clk_init_data) { 2181 .name = "gcc_snoc_cnoc_gemnoc_pcie_qx_clk", 2182 .ops = &clk_branch2_ops, 2183 }, 2184 }, 2185 }; 2186 2187 static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk = { 2188 .halt_reg = 0x92010, 2189 .halt_check = BRANCH_HALT_SKIP, 2190 .hwcg_reg = 0x92010, 2191 .hwcg_bit = 1, 2192 .clkr = { 2193 .enable_reg = 0x62000, 2194 .enable_mask = BIT(12), 2195 .hw.init = &(const struct clk_init_data) { 2196 .name = "gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk", 2197 .ops = &clk_branch2_ops, 2198 }, 2199 }, 2200 }; 2201 2202 static struct clk_branch gcc_snoc_cnoc_pcie_qx_clk = { 2203 .halt_reg = 0x84030, 2204 .halt_check = BRANCH_HALT, 2205 .clkr = { 2206 .enable_reg = 0x84030, 2207 .enable_mask = BIT(0), 2208 .hw.init = &(const struct clk_init_data) { 2209 .name = "gcc_snoc_cnoc_pcie_qx_clk", 2210 .ops = &clk_branch2_ops, 2211 }, 2212 }, 2213 }; 2214 2215 static struct clk_branch gcc_snoc_pcie_sf_center_qx_clk = { 2216 .halt_reg = 0x92014, 2217 .halt_check = BRANCH_HALT_SKIP, 2218 .hwcg_reg = 0x92014, 2219 .hwcg_bit = 1, 2220 .clkr = { 2221 .enable_reg = 0x62000, 2222 .enable_mask = BIT(19), 2223 .hw.init = &(const struct clk_init_data) { 2224 .name = "gcc_snoc_pcie_sf_center_qx_clk", 2225 .ops = &clk_branch2_ops, 2226 }, 2227 }, 2228 }; 2229 2230 static struct clk_branch gcc_snoc_pcie_sf_south_qx_clk = { 2231 .halt_reg = 0x92018, 2232 .halt_check = BRANCH_HALT_SKIP, 2233 .hwcg_reg = 0x92018, 2234 .hwcg_bit = 1, 2235 .clkr = { 2236 .enable_reg = 0x62000, 2237 .enable_mask = BIT(22), 2238 .hw.init = &(const struct clk_init_data) { 2239 .name = "gcc_snoc_pcie_sf_south_qx_clk", 2240 .ops = &clk_branch2_ops, 2241 }, 2242 }, 2243 }; 2244 2245 static struct clk_branch gcc_tsc_cfg_ahb_clk = { 2246 .halt_reg = 0x5700c, 2247 .halt_check = BRANCH_HALT, 2248 .clkr = { 2249 .enable_reg = 0x5700c, 2250 .enable_mask = BIT(0), 2251 .hw.init = &(const struct clk_init_data) { 2252 .name = "gcc_tsc_cfg_ahb_clk", 2253 .ops = &clk_branch2_ops, 2254 }, 2255 }, 2256 }; 2257 2258 static struct clk_branch gcc_tsc_cntr_clk = { 2259 .halt_reg = 0x57004, 2260 .halt_check = BRANCH_HALT, 2261 .clkr = { 2262 .enable_reg = 0x57004, 2263 .enable_mask = BIT(0), 2264 .hw.init = &(const struct clk_init_data) { 2265 .name = "gcc_tsc_cntr_clk", 2266 .parent_hws = (const struct clk_hw*[]) { 2267 &gcc_tsc_clk_src.clkr.hw, 2268 }, 2269 .num_parents = 1, 2270 .flags = CLK_SET_RATE_PARENT, 2271 .ops = &clk_branch2_ops, 2272 }, 2273 }, 2274 }; 2275 2276 static struct clk_branch gcc_tsc_etu_clk = { 2277 .halt_reg = 0x57008, 2278 .halt_check = BRANCH_HALT, 2279 .clkr = { 2280 .enable_reg = 0x57008, 2281 .enable_mask = BIT(0), 2282 .hw.init = &(const struct clk_init_data) { 2283 .name = "gcc_tsc_etu_clk", 2284 .parent_hws = (const struct clk_hw*[]) { 2285 &gcc_tsc_clk_src.clkr.hw, 2286 }, 2287 .num_parents = 1, 2288 .flags = CLK_SET_RATE_PARENT, 2289 .ops = &clk_branch2_ops, 2290 }, 2291 }, 2292 }; 2293 2294 static struct clk_branch gcc_usb2_clkref_en = { 2295 .halt_reg = 0x9c008, 2296 .halt_check = BRANCH_HALT, 2297 .clkr = { 2298 .enable_reg = 0x9c008, 2299 .enable_mask = BIT(0), 2300 .hw.init = &(const struct clk_init_data) { 2301 .name = "gcc_usb2_clkref_en", 2302 .ops = &clk_branch2_ops, 2303 }, 2304 }, 2305 }; 2306 2307 static struct clk_branch gcc_usb30_prim_master_clk = { 2308 .halt_reg = 0x49018, 2309 .halt_check = BRANCH_HALT, 2310 .clkr = { 2311 .enable_reg = 0x49018, 2312 .enable_mask = BIT(0), 2313 .hw.init = &(const struct clk_init_data) { 2314 .name = "gcc_usb30_prim_master_clk", 2315 .parent_hws = (const struct clk_hw*[]) { 2316 &gcc_usb30_prim_master_clk_src.clkr.hw, 2317 }, 2318 .num_parents = 1, 2319 .flags = CLK_SET_RATE_PARENT, 2320 .ops = &clk_branch2_ops, 2321 }, 2322 }, 2323 }; 2324 2325 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2326 .halt_reg = 0x49024, 2327 .halt_check = BRANCH_HALT, 2328 .clkr = { 2329 .enable_reg = 0x49024, 2330 .enable_mask = BIT(0), 2331 .hw.init = &(const struct clk_init_data) { 2332 .name = "gcc_usb30_prim_mock_utmi_clk", 2333 .parent_hws = (const struct clk_hw*[]) { 2334 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2335 }, 2336 .num_parents = 1, 2337 .flags = CLK_SET_RATE_PARENT, 2338 .ops = &clk_branch2_ops, 2339 }, 2340 }, 2341 }; 2342 2343 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2344 .halt_reg = 0x49020, 2345 .halt_check = BRANCH_HALT, 2346 .clkr = { 2347 .enable_reg = 0x49020, 2348 .enable_mask = BIT(0), 2349 .hw.init = &(const struct clk_init_data) { 2350 .name = "gcc_usb30_prim_sleep_clk", 2351 .ops = &clk_branch2_ops, 2352 }, 2353 }, 2354 }; 2355 2356 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2357 .halt_reg = 0x49060, 2358 .halt_check = BRANCH_HALT, 2359 .clkr = { 2360 .enable_reg = 0x49060, 2361 .enable_mask = BIT(0), 2362 .hw.init = &(const struct clk_init_data) { 2363 .name = "gcc_usb3_prim_phy_aux_clk", 2364 .parent_hws = (const struct clk_hw*[]) { 2365 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2366 }, 2367 .num_parents = 1, 2368 .flags = CLK_SET_RATE_PARENT, 2369 .ops = &clk_branch2_ops, 2370 }, 2371 }, 2372 }; 2373 2374 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2375 .halt_reg = 0x49064, 2376 .halt_check = BRANCH_HALT, 2377 .clkr = { 2378 .enable_reg = 0x49064, 2379 .enable_mask = BIT(0), 2380 .hw.init = &(const struct clk_init_data) { 2381 .name = "gcc_usb3_prim_phy_com_aux_clk", 2382 .parent_hws = (const struct clk_hw*[]) { 2383 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2384 }, 2385 .num_parents = 1, 2386 .flags = CLK_SET_RATE_PARENT, 2387 .ops = &clk_branch2_ops, 2388 }, 2389 }, 2390 }; 2391 2392 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2393 .halt_reg = 0x49068, 2394 .halt_check = BRANCH_HALT_DELAY, 2395 .hwcg_reg = 0x49068, 2396 .hwcg_bit = 1, 2397 .clkr = { 2398 .enable_reg = 0x49068, 2399 .enable_mask = BIT(0), 2400 .hw.init = &(const struct clk_init_data) { 2401 .name = "gcc_usb3_prim_phy_pipe_clk", 2402 .parent_hws = (const struct clk_hw*[]) { 2403 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 2404 }, 2405 .num_parents = 1, 2406 .flags = CLK_SET_RATE_PARENT, 2407 .ops = &clk_branch2_ops, 2408 }, 2409 }, 2410 }; 2411 2412 static struct clk_regmap *gcc_qdu1000_clocks[] = { 2413 [GCC_AGGRE_NOC_ECPRI_DMA_CLK] = &gcc_aggre_noc_ecpri_dma_clk.clkr, 2414 [GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC] = &gcc_aggre_noc_ecpri_dma_clk_src.clkr, 2415 [GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC] = &gcc_aggre_noc_ecpri_gsi_clk_src.clkr, 2416 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2417 [GCC_CFG_NOC_ECPRI_CC_AHB_CLK] = &gcc_cfg_noc_ecpri_cc_ahb_clk.clkr, 2418 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2419 [GCC_DDRSS_ECPRI_DMA_CLK] = &gcc_ddrss_ecpri_dma_clk.clkr, 2420 [GCC_ECPRI_AHB_CLK] = &gcc_ecpri_ahb_clk.clkr, 2421 [GCC_ECPRI_CC_GPLL0_CLK_SRC] = &gcc_ecpri_cc_gpll0_clk_src.clkr, 2422 [GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll1_even_clk_src.clkr, 2423 [GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll2_even_clk_src.clkr, 2424 [GCC_ECPRI_CC_GPLL3_CLK_SRC] = &gcc_ecpri_cc_gpll3_clk_src.clkr, 2425 [GCC_ECPRI_CC_GPLL4_CLK_SRC] = &gcc_ecpri_cc_gpll4_clk_src.clkr, 2426 [GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll5_even_clk_src.clkr, 2427 [GCC_ECPRI_XO_CLK] = &gcc_ecpri_xo_clk.clkr, 2428 [GCC_ETH_DBG_SNOC_AXI_CLK] = &gcc_eth_dbg_snoc_axi_clk.clkr, 2429 [GCC_GEMNOC_PCIE_QX_CLK] = &gcc_gemnoc_pcie_qx_clk.clkr, 2430 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2431 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2432 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2433 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2434 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2435 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2436 [GCC_GPLL0] = &gcc_gpll0.clkr, 2437 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 2438 [GCC_GPLL1] = &gcc_gpll1.clkr, 2439 [GCC_GPLL2] = &gcc_gpll2.clkr, 2440 [GCC_GPLL2_OUT_EVEN] = &gcc_gpll2_out_even.clkr, 2441 [GCC_GPLL3] = &gcc_gpll3.clkr, 2442 [GCC_GPLL4] = &gcc_gpll4.clkr, 2443 [GCC_GPLL5] = &gcc_gpll5.clkr, 2444 [GCC_GPLL5_OUT_EVEN] = &gcc_gpll5_out_even.clkr, 2445 [GCC_GPLL6] = &gcc_gpll6.clkr, 2446 [GCC_GPLL7] = &gcc_gpll7.clkr, 2447 [GCC_GPLL8] = &gcc_gpll8.clkr, 2448 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2449 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 2450 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2451 [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr, 2452 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2453 [GCC_PCIE_0_PHY_AUX_CLK] = &gcc_pcie_0_phy_aux_clk.clkr, 2454 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 2455 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 2456 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2457 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2458 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 2459 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2460 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 2461 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2462 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2463 [GCC_QMIP_ANOC_PCIE_CLK] = &gcc_qmip_anoc_pcie_clk.clkr, 2464 [GCC_QMIP_ECPRI_DMA0_CLK] = &gcc_qmip_ecpri_dma0_clk.clkr, 2465 [GCC_QMIP_ECPRI_DMA1_CLK] = &gcc_qmip_ecpri_dma1_clk.clkr, 2466 [GCC_QMIP_ECPRI_GSI_CLK] = &gcc_qmip_ecpri_gsi_clk.clkr, 2467 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 2468 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 2469 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 2470 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 2471 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 2472 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 2473 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 2474 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 2475 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 2476 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 2477 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 2478 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 2479 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 2480 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 2481 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 2482 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 2483 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 2484 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 2485 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 2486 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 2487 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 2488 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 2489 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 2490 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 2491 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 2492 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 2493 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 2494 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 2495 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 2496 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 2497 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 2498 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 2499 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 2500 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 2501 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 2502 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 2503 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 2504 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 2505 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 2506 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 2507 [GCC_SDCC5_AHB_CLK] = &gcc_sdcc5_ahb_clk.clkr, 2508 [GCC_SDCC5_APPS_CLK] = &gcc_sdcc5_apps_clk.clkr, 2509 [GCC_SDCC5_APPS_CLK_SRC] = &gcc_sdcc5_apps_clk_src.clkr, 2510 [GCC_SDCC5_ICE_CORE_CLK] = &gcc_sdcc5_ice_core_clk.clkr, 2511 [GCC_SDCC5_ICE_CORE_CLK_SRC] = &gcc_sdcc5_ice_core_clk_src.clkr, 2512 [GCC_SM_BUS_AHB_CLK] = &gcc_sm_bus_ahb_clk.clkr, 2513 [GCC_SM_BUS_XO_CLK] = &gcc_sm_bus_xo_clk.clkr, 2514 [GCC_SM_BUS_XO_CLK_SRC] = &gcc_sm_bus_xo_clk_src.clkr, 2515 [GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK] = &gcc_snoc_cnoc_gemnoc_pcie_qx_clk.clkr, 2516 [GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK] = &gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk.clkr, 2517 [GCC_SNOC_CNOC_PCIE_QX_CLK] = &gcc_snoc_cnoc_pcie_qx_clk.clkr, 2518 [GCC_SNOC_PCIE_SF_CENTER_QX_CLK] = &gcc_snoc_pcie_sf_center_qx_clk.clkr, 2519 [GCC_SNOC_PCIE_SF_SOUTH_QX_CLK] = &gcc_snoc_pcie_sf_south_qx_clk.clkr, 2520 [GCC_TSC_CFG_AHB_CLK] = &gcc_tsc_cfg_ahb_clk.clkr, 2521 [GCC_TSC_CLK_SRC] = &gcc_tsc_clk_src.clkr, 2522 [GCC_TSC_CNTR_CLK] = &gcc_tsc_cntr_clk.clkr, 2523 [GCC_TSC_ETU_CLK] = &gcc_tsc_etu_clk.clkr, 2524 [GCC_USB2_CLKREF_EN] = &gcc_usb2_clkref_en.clkr, 2525 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 2526 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 2527 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 2528 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 2529 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 2530 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 2531 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 2532 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 2533 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 2534 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 2535 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 2536 [GCC_ETH_100G_C2C_HM_APB_CLK] = &gcc_eth_100g_c2c_hm_apb_clk.clkr, 2537 [GCC_ETH_100G_FH_HM_APB_0_CLK] = &gcc_eth_100g_fh_hm_apb_0_clk.clkr, 2538 [GCC_ETH_100G_FH_HM_APB_1_CLK] = &gcc_eth_100g_fh_hm_apb_1_clk.clkr, 2539 [GCC_ETH_100G_FH_HM_APB_2_CLK] = &gcc_eth_100g_fh_hm_apb_2_clk.clkr, 2540 [GCC_ETH_DBG_C2C_HM_APB_CLK] = &gcc_eth_dbg_c2c_hm_apb_clk.clkr, 2541 [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr, 2542 [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, 2543 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 2544 [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr, 2545 [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr, 2546 }; 2547 2548 static const struct qcom_reset_map gcc_qdu1000_resets[] = { 2549 [GCC_ECPRI_CC_BCR] = { 0x3e000 }, 2550 [GCC_ECPRI_SS_BCR] = { 0x3a000 }, 2551 [GCC_ETH_WRAPPER_BCR] = { 0x39000 }, 2552 [GCC_PCIE_0_BCR] = { 0x9d000 }, 2553 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x9e014 }, 2554 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x9e020 }, 2555 [GCC_PCIE_0_PHY_BCR] = { 0x7c000 }, 2556 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 }, 2557 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c }, 2558 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 }, 2559 [GCC_PDM_BCR] = { 0x43000 }, 2560 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 }, 2561 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 }, 2562 [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 }, 2563 [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 }, 2564 [GCC_SDCC5_BCR] = { 0x3b000 }, 2565 [GCC_TSC_BCR] = { 0x57000 }, 2566 [GCC_USB30_PRIM_BCR] = { 0x49000 }, 2567 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 }, 2568 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 }, 2569 [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 }, 2570 [GCC_USB3_PHY_SEC_BCR] = { 0x6000c }, 2571 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 }, 2572 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 }, 2573 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 }, 2574 }; 2575 2576 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 2577 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 2578 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 2579 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 2580 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 2581 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 2582 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 2583 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 2584 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 2585 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 2586 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 2587 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 2588 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 2589 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 2590 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 2591 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 2592 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 2593 }; 2594 2595 static const struct regmap_config gcc_qdu1000_regmap_config = { 2596 .reg_bits = 32, 2597 .reg_stride = 4, 2598 .val_bits = 32, 2599 .max_register = 0x1f41f0, 2600 .fast_io = true, 2601 }; 2602 2603 static const struct qcom_cc_desc gcc_qdu1000_desc = { 2604 .config = &gcc_qdu1000_regmap_config, 2605 .clks = gcc_qdu1000_clocks, 2606 .num_clks = ARRAY_SIZE(gcc_qdu1000_clocks), 2607 .resets = gcc_qdu1000_resets, 2608 .num_resets = ARRAY_SIZE(gcc_qdu1000_resets), 2609 }; 2610 2611 static const struct of_device_id gcc_qdu1000_match_table[] = { 2612 { .compatible = "qcom,qdu1000-gcc" }, 2613 { } 2614 }; 2615 MODULE_DEVICE_TABLE(of, gcc_qdu1000_match_table); 2616 2617 static int gcc_qdu1000_probe(struct platform_device *pdev) 2618 { 2619 struct regmap *regmap; 2620 int ret; 2621 2622 regmap = qcom_cc_map(pdev, &gcc_qdu1000_desc); 2623 if (IS_ERR(regmap)) 2624 return PTR_ERR(regmap); 2625 2626 /* Update FORCE_MEM_CORE_ON for gcc_pcie_0_mstr_axi_clk */ 2627 regmap_update_bits(regmap, 0x9d024, BIT(14), BIT(14)); 2628 2629 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 2630 ARRAY_SIZE(gcc_dfs_clocks)); 2631 if (ret) 2632 return ret; 2633 2634 ret = qcom_cc_really_probe(pdev, &gcc_qdu1000_desc, regmap); 2635 if (ret) 2636 return dev_err_probe(&pdev->dev, ret, "Failed to register GCC clocks\n"); 2637 2638 return ret; 2639 } 2640 2641 static struct platform_driver gcc_qdu1000_driver = { 2642 .probe = gcc_qdu1000_probe, 2643 .driver = { 2644 .name = "gcc-qdu1000", 2645 .of_match_table = gcc_qdu1000_match_table, 2646 }, 2647 }; 2648 2649 static int __init gcc_qdu1000_init(void) 2650 { 2651 return platform_driver_register(&gcc_qdu1000_driver); 2652 } 2653 subsys_initcall(gcc_qdu1000_init); 2654 2655 static void __exit gcc_qdu1000_exit(void) 2656 { 2657 platform_driver_unregister(&gcc_qdu1000_driver); 2658 } 2659 module_exit(gcc_qdu1000_exit); 2660 2661 MODULE_DESCRIPTION("QTI GCC QDU1000 Driver"); 2662 MODULE_LICENSE("GPL"); 2663