1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/of_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,qdu1000-gcc.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-rcg.h" 16 #include "clk-regmap.h" 17 #include "clk-regmap-divider.h" 18 #include "clk-regmap-mux.h" 19 #include "clk-regmap-phy-mux.h" 20 #include "reset.h" 21 22 enum { 23 P_BI_TCXO, 24 P_GCC_GPLL0_OUT_EVEN, 25 P_GCC_GPLL0_OUT_MAIN, 26 P_GCC_GPLL1_OUT_MAIN, 27 P_GCC_GPLL2_OUT_MAIN, 28 P_GCC_GPLL3_OUT_MAIN, 29 P_GCC_GPLL4_OUT_MAIN, 30 P_GCC_GPLL5_OUT_MAIN, 31 P_GCC_GPLL6_OUT_MAIN, 32 P_GCC_GPLL7_OUT_MAIN, 33 P_GCC_GPLL8_OUT_MAIN, 34 P_PCIE_0_PHY_AUX_CLK, 35 P_PCIE_0_PIPE_CLK, 36 P_SLEEP_CLK, 37 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 38 }; 39 40 enum { 41 DT_TCXO_IDX, 42 DT_SLEEP_CLK_IDX, 43 DT_PCIE_0_PIPE_CLK_IDX, 44 DT_PCIE_0_PHY_AUX_CLK_IDX, 45 DT_USB3_PHY_WRAPPER_PIPE_CLK_IDX, 46 }; 47 48 static struct clk_alpha_pll gcc_gpll0 = { 49 .offset = 0x0, 50 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 51 .clkr = { 52 .enable_reg = 0x62018, 53 .enable_mask = BIT(0), 54 .hw.init = &(const struct clk_init_data) { 55 .name = "gcc_gpll0", 56 .parent_data = &(const struct clk_parent_data) { 57 .index = DT_TCXO_IDX, 58 }, 59 .num_parents = 1, 60 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 61 }, 62 }, 63 }; 64 65 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 66 { 0x1, 2 } 67 }; 68 69 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 70 .offset = 0x0, 71 .post_div_shift = 10, 72 .post_div_table = post_div_table_gcc_gpll0_out_even, 73 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 74 .width = 4, 75 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 76 .clkr.hw.init = &(const struct clk_init_data) { 77 .name = "gcc_gpll0_out_even", 78 .parent_hws = (const struct clk_hw*[]) { 79 &gcc_gpll0.clkr.hw, 80 }, 81 .num_parents = 1, 82 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 83 }, 84 }; 85 86 static struct clk_alpha_pll gcc_gpll1 = { 87 .offset = 0x1000, 88 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 89 .clkr = { 90 .enable_reg = 0x62018, 91 .enable_mask = BIT(1), 92 .hw.init = &(const struct clk_init_data) { 93 .name = "gcc_gpll1", 94 .parent_data = &(const struct clk_parent_data) { 95 .index = DT_TCXO_IDX, 96 }, 97 .num_parents = 1, 98 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 99 }, 100 }, 101 }; 102 103 static struct clk_alpha_pll_postdiv gcc_gpll1_out_even = { 104 .offset = 0x1000, 105 .post_div_shift = 10, 106 .post_div_table = post_div_table_gcc_gpll0_out_even, 107 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 108 .width = 4, 109 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 110 .clkr.hw.init = &(const struct clk_init_data) { 111 .name = "gcc_gpll1_out_even", 112 .parent_hws = (const struct clk_hw*[]) { 113 &gcc_gpll1.clkr.hw, 114 }, 115 .num_parents = 1, 116 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 117 }, 118 }; 119 120 static struct clk_alpha_pll gcc_gpll2 = { 121 .offset = 0x2000, 122 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 123 .clkr = { 124 .enable_reg = 0x62018, 125 .enable_mask = BIT(2), 126 .hw.init = &(const struct clk_init_data) { 127 .name = "gcc_gpll2", 128 .parent_data = &(const struct clk_parent_data) { 129 .index = DT_TCXO_IDX, 130 }, 131 .num_parents = 1, 132 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 133 }, 134 }, 135 }; 136 137 static struct clk_alpha_pll_postdiv gcc_gpll2_out_even = { 138 .offset = 0x2000, 139 .post_div_shift = 10, 140 .post_div_table = post_div_table_gcc_gpll0_out_even, 141 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 142 .width = 4, 143 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 144 .clkr.hw.init = &(const struct clk_init_data) { 145 .name = "gcc_gpll2_out_even", 146 .parent_hws = (const struct clk_hw*[]) { 147 &gcc_gpll2.clkr.hw, 148 }, 149 .num_parents = 1, 150 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 151 }, 152 }; 153 154 static struct clk_alpha_pll gcc_gpll3 = { 155 .offset = 0x3000, 156 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 157 .clkr = { 158 .enable_reg = 0x62018, 159 .enable_mask = BIT(3), 160 .hw.init = &(const struct clk_init_data) { 161 .name = "gcc_gpll3", 162 .parent_data = &(const struct clk_parent_data) { 163 .index = DT_TCXO_IDX, 164 }, 165 .num_parents = 1, 166 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 167 }, 168 }, 169 }; 170 171 static struct clk_alpha_pll gcc_gpll4 = { 172 .offset = 0x4000, 173 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 174 .clkr = { 175 .enable_reg = 0x62018, 176 .enable_mask = BIT(4), 177 .hw.init = &(const struct clk_init_data) { 178 .name = "gcc_gpll4", 179 .parent_data = &(const struct clk_parent_data) { 180 .index = DT_TCXO_IDX, 181 }, 182 .num_parents = 1, 183 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 184 }, 185 }, 186 }; 187 188 static struct clk_alpha_pll gcc_gpll5 = { 189 .offset = 0x5000, 190 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 191 .clkr = { 192 .enable_reg = 0x62018, 193 .enable_mask = BIT(5), 194 .hw.init = &(const struct clk_init_data) { 195 .name = "gcc_gpll5", 196 .parent_data = &(const struct clk_parent_data) { 197 .index = DT_TCXO_IDX, 198 }, 199 .num_parents = 1, 200 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 201 }, 202 }, 203 }; 204 205 static struct clk_alpha_pll_postdiv gcc_gpll5_out_even = { 206 .offset = 0x5000, 207 .post_div_shift = 10, 208 .post_div_table = post_div_table_gcc_gpll0_out_even, 209 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 210 .width = 4, 211 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 212 .clkr.hw.init = &(const struct clk_init_data) { 213 .name = "gcc_gpll5_out_even", 214 .parent_hws = (const struct clk_hw*[]) { 215 &gcc_gpll5.clkr.hw, 216 }, 217 .num_parents = 1, 218 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 219 }, 220 }; 221 222 static struct clk_alpha_pll gcc_gpll6 = { 223 .offset = 0x6000, 224 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 225 .clkr = { 226 .enable_reg = 0x62018, 227 .enable_mask = BIT(6), 228 .hw.init = &(const struct clk_init_data) { 229 .name = "gcc_gpll6", 230 .parent_data = &(const struct clk_parent_data) { 231 .index = DT_TCXO_IDX, 232 }, 233 .num_parents = 1, 234 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 235 }, 236 }, 237 }; 238 239 static struct clk_alpha_pll gcc_gpll7 = { 240 .offset = 0x7000, 241 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 242 .clkr = { 243 .enable_reg = 0x62018, 244 .enable_mask = BIT(7), 245 .hw.init = &(const struct clk_init_data) { 246 .name = "gcc_gpll7", 247 .parent_data = &(const struct clk_parent_data) { 248 .index = DT_TCXO_IDX, 249 }, 250 .num_parents = 1, 251 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 252 }, 253 }, 254 }; 255 256 static struct clk_alpha_pll gcc_gpll8 = { 257 .offset = 0x8000, 258 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 259 .clkr = { 260 .enable_reg = 0x62018, 261 .enable_mask = BIT(8), 262 .hw.init = &(const struct clk_init_data) { 263 .name = "gcc_gpll8", 264 .parent_data = &(const struct clk_parent_data) { 265 .index = DT_TCXO_IDX, 266 }, 267 .num_parents = 1, 268 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 269 }, 270 }, 271 }; 272 273 static const struct parent_map gcc_parent_map_0[] = { 274 { P_BI_TCXO, 0 }, 275 { P_GCC_GPLL0_OUT_MAIN, 1 }, 276 { P_GCC_GPLL0_OUT_EVEN, 6 }, 277 }; 278 279 static const struct clk_parent_data gcc_parent_data_0[] = { 280 { .index = DT_TCXO_IDX }, 281 { .hw = &gcc_gpll0.clkr.hw }, 282 { .hw = &gcc_gpll0_out_even.clkr.hw }, 283 }; 284 285 static const struct parent_map gcc_parent_map_1[] = { 286 { P_BI_TCXO, 0 }, 287 { P_GCC_GPLL0_OUT_MAIN, 1 }, 288 { P_SLEEP_CLK, 5 }, 289 { P_GCC_GPLL0_OUT_EVEN, 6 }, 290 }; 291 292 static const struct clk_parent_data gcc_parent_data_1[] = { 293 { .index = DT_TCXO_IDX }, 294 { .hw = &gcc_gpll0.clkr.hw }, 295 { .index = DT_SLEEP_CLK_IDX }, 296 { .hw = &gcc_gpll0_out_even.clkr.hw }, 297 }; 298 299 static const struct parent_map gcc_parent_map_2[] = { 300 { P_BI_TCXO, 0 }, 301 { P_GCC_GPLL0_OUT_MAIN, 1 }, 302 { P_GCC_GPLL5_OUT_MAIN, 3 }, 303 { P_GCC_GPLL4_OUT_MAIN, 5 }, 304 }; 305 306 static const struct clk_parent_data gcc_parent_data_2[] = { 307 { .index = DT_TCXO_IDX }, 308 { .hw = &gcc_gpll0.clkr.hw }, 309 { .hw = &gcc_gpll5.clkr.hw }, 310 { .hw = &gcc_gpll4.clkr.hw }, 311 }; 312 313 static const struct parent_map gcc_parent_map_3[] = { 314 { P_BI_TCXO, 0 }, 315 { P_SLEEP_CLK, 5 }, 316 }; 317 318 static const struct clk_parent_data gcc_parent_data_3[] = { 319 { .index = DT_TCXO_IDX }, 320 { .index = DT_SLEEP_CLK_IDX }, 321 }; 322 323 static const struct parent_map gcc_parent_map_4[] = { 324 { P_BI_TCXO, 0 }, 325 { P_GCC_GPLL0_OUT_MAIN, 1 }, 326 { P_GCC_GPLL2_OUT_MAIN, 2 }, 327 { P_GCC_GPLL5_OUT_MAIN, 3 }, 328 { P_GCC_GPLL1_OUT_MAIN, 4 }, 329 { P_GCC_GPLL4_OUT_MAIN, 5 }, 330 { P_GCC_GPLL3_OUT_MAIN, 6 }, 331 }; 332 333 static const struct clk_parent_data gcc_parent_data_4[] = { 334 { .index = DT_TCXO_IDX }, 335 { .hw = &gcc_gpll0.clkr.hw }, 336 { .hw = &gcc_gpll2.clkr.hw }, 337 { .hw = &gcc_gpll5.clkr.hw }, 338 { .hw = &gcc_gpll1.clkr.hw }, 339 { .hw = &gcc_gpll4.clkr.hw }, 340 { .hw = &gcc_gpll3.clkr.hw }, 341 }; 342 343 static const struct parent_map gcc_parent_map_5[] = { 344 { P_BI_TCXO, 0 }, 345 { P_GCC_GPLL0_OUT_MAIN, 1 }, 346 { P_GCC_GPLL2_OUT_MAIN, 2 }, 347 { P_GCC_GPLL6_OUT_MAIN, 3 }, 348 { P_GCC_GPLL1_OUT_MAIN, 4 }, 349 { P_GCC_GPLL4_OUT_MAIN, 5 }, 350 { P_GCC_GPLL3_OUT_MAIN, 6 }, 351 }; 352 353 static const struct clk_parent_data gcc_parent_data_5[] = { 354 { .index = DT_TCXO_IDX }, 355 { .hw = &gcc_gpll0.clkr.hw }, 356 { .hw = &gcc_gpll2.clkr.hw }, 357 { .hw = &gcc_gpll6.clkr.hw }, 358 { .hw = &gcc_gpll1.clkr.hw }, 359 { .hw = &gcc_gpll4.clkr.hw }, 360 { .hw = &gcc_gpll3.clkr.hw }, 361 }; 362 363 static const struct parent_map gcc_parent_map_6[] = { 364 { P_PCIE_0_PHY_AUX_CLK, 0 }, 365 { P_BI_TCXO, 2 }, 366 }; 367 368 static const struct clk_parent_data gcc_parent_data_6[] = { 369 { .index = DT_PCIE_0_PHY_AUX_CLK_IDX }, 370 { .index = DT_TCXO_IDX }, 371 }; 372 373 static const struct parent_map gcc_parent_map_8[] = { 374 { P_BI_TCXO, 0 }, 375 { P_GCC_GPLL0_OUT_MAIN, 1 }, 376 { P_GCC_GPLL8_OUT_MAIN, 2 }, 377 { P_GCC_GPLL5_OUT_MAIN, 3 }, 378 { P_GCC_GPLL4_OUT_MAIN, 5 }, 379 }; 380 381 static const struct clk_parent_data gcc_parent_data_8[] = { 382 { .index = DT_TCXO_IDX }, 383 { .hw = &gcc_gpll0.clkr.hw }, 384 { .hw = &gcc_gpll8.clkr.hw }, 385 { .hw = &gcc_gpll5.clkr.hw }, 386 { .hw = &gcc_gpll4.clkr.hw }, 387 }; 388 389 static const struct parent_map gcc_parent_map_9[] = { 390 { P_BI_TCXO, 0 }, 391 { P_GCC_GPLL0_OUT_MAIN, 1 }, 392 { P_GCC_GPLL2_OUT_MAIN, 2 }, 393 { P_GCC_GPLL5_OUT_MAIN, 3 }, 394 { P_GCC_GPLL7_OUT_MAIN, 4 }, 395 { P_GCC_GPLL4_OUT_MAIN, 5 }, 396 }; 397 398 static const struct clk_parent_data gcc_parent_data_9[] = { 399 { .index = DT_TCXO_IDX }, 400 { .hw = &gcc_gpll0.clkr.hw }, 401 { .hw = &gcc_gpll2.clkr.hw }, 402 { .hw = &gcc_gpll5.clkr.hw }, 403 { .hw = &gcc_gpll7.clkr.hw }, 404 { .hw = &gcc_gpll4.clkr.hw }, 405 }; 406 407 static const struct parent_map gcc_parent_map_10[] = { 408 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 409 { P_BI_TCXO, 2 }, 410 }; 411 412 static const struct clk_parent_data gcc_parent_data_10[] = { 413 { .index = DT_USB3_PHY_WRAPPER_PIPE_CLK_IDX }, 414 { .index = DT_TCXO_IDX }, 415 }; 416 417 static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = { 418 .reg = 0x9d080, 419 .shift = 0, 420 .width = 2, 421 .parent_map = gcc_parent_map_6, 422 .clkr = { 423 .hw.init = &(const struct clk_init_data) { 424 .name = "gcc_pcie_0_phy_aux_clk_src", 425 .parent_data = gcc_parent_data_6, 426 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 427 .ops = &clk_regmap_mux_closest_ops, 428 }, 429 }, 430 }; 431 432 static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { 433 .reg = 0x9d064, 434 .clkr = { 435 .hw.init = &(const struct clk_init_data) { 436 .name = "gcc_pcie_0_pipe_clk_src", 437 .parent_data = &(const struct clk_parent_data){ 438 .index = DT_PCIE_0_PIPE_CLK_IDX, 439 }, 440 .num_parents = 1, 441 .ops = &clk_regmap_phy_mux_ops, 442 }, 443 }, 444 }; 445 446 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 447 .reg = 0x4906c, 448 .shift = 0, 449 .width = 2, 450 .parent_map = gcc_parent_map_10, 451 .clkr = { 452 .hw.init = &(const struct clk_init_data) { 453 .name = "gcc_usb3_prim_phy_pipe_clk_src", 454 .parent_data = gcc_parent_data_10, 455 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 456 .ops = &clk_regmap_mux_closest_ops, 457 }, 458 }, 459 }; 460 461 static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_dma_clk_src[] = { 462 F(466500000, P_GCC_GPLL5_OUT_MAIN, 2, 0, 0), 463 F(500000000, P_GCC_GPLL2_OUT_MAIN, 2, 0, 0), 464 { } 465 }; 466 467 static struct clk_rcg2 gcc_aggre_noc_ecpri_dma_clk_src = { 468 .cmd_rcgr = 0x92020, 469 .mnd_width = 0, 470 .hid_width = 5, 471 .parent_map = gcc_parent_map_4, 472 .freq_tbl = ftbl_gcc_aggre_noc_ecpri_dma_clk_src, 473 .clkr.hw.init = &(const struct clk_init_data) { 474 .name = "gcc_aggre_noc_ecpri_dma_clk_src", 475 .parent_data = gcc_parent_data_4, 476 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 477 .ops = &clk_rcg2_ops, 478 }, 479 }; 480 481 static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_gsi_clk_src[] = { 482 F(250000000, P_GCC_GPLL2_OUT_MAIN, 4, 0, 0), 483 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 484 { } 485 }; 486 487 static struct clk_rcg2 gcc_aggre_noc_ecpri_gsi_clk_src = { 488 .cmd_rcgr = 0x92038, 489 .mnd_width = 0, 490 .hid_width = 5, 491 .parent_map = gcc_parent_map_5, 492 .freq_tbl = ftbl_gcc_aggre_noc_ecpri_gsi_clk_src, 493 .clkr.hw.init = &(const struct clk_init_data) { 494 .name = "gcc_aggre_noc_ecpri_gsi_clk_src", 495 .parent_data = gcc_parent_data_5, 496 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 497 .ops = &clk_rcg2_ops, 498 }, 499 }; 500 501 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 502 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 503 { } 504 }; 505 506 static struct clk_rcg2 gcc_gp1_clk_src = { 507 .cmd_rcgr = 0x74004, 508 .mnd_width = 16, 509 .hid_width = 5, 510 .parent_map = gcc_parent_map_1, 511 .freq_tbl = ftbl_gcc_gp1_clk_src, 512 .clkr.hw.init = &(const struct clk_init_data) { 513 .name = "gcc_gp1_clk_src", 514 .parent_data = gcc_parent_data_1, 515 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 516 .ops = &clk_rcg2_ops, 517 }, 518 }; 519 520 static struct clk_rcg2 gcc_gp2_clk_src = { 521 .cmd_rcgr = 0x75004, 522 .mnd_width = 16, 523 .hid_width = 5, 524 .parent_map = gcc_parent_map_1, 525 .freq_tbl = ftbl_gcc_gp1_clk_src, 526 .clkr.hw.init = &(const struct clk_init_data) { 527 .name = "gcc_gp2_clk_src", 528 .parent_data = gcc_parent_data_1, 529 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 530 .ops = &clk_rcg2_ops, 531 }, 532 }; 533 534 static struct clk_rcg2 gcc_gp3_clk_src = { 535 .cmd_rcgr = 0x76004, 536 .mnd_width = 16, 537 .hid_width = 5, 538 .parent_map = gcc_parent_map_1, 539 .freq_tbl = ftbl_gcc_gp1_clk_src, 540 .clkr.hw.init = &(const struct clk_init_data) { 541 .name = "gcc_gp3_clk_src", 542 .parent_data = gcc_parent_data_1, 543 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 544 .ops = &clk_rcg2_ops, 545 }, 546 }; 547 548 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 549 F(19200000, P_BI_TCXO, 1, 0, 0), 550 { } 551 }; 552 553 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 554 .cmd_rcgr = 0x9d068, 555 .mnd_width = 16, 556 .hid_width = 5, 557 .parent_map = gcc_parent_map_3, 558 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 559 .clkr.hw.init = &(const struct clk_init_data) { 560 .name = "gcc_pcie_0_aux_clk_src", 561 .parent_data = gcc_parent_data_3, 562 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 563 .ops = &clk_rcg2_ops, 564 }, 565 }; 566 567 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 568 F(19200000, P_BI_TCXO, 1, 0, 0), 569 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 570 { } 571 }; 572 573 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 574 .cmd_rcgr = 0x9d04c, 575 .mnd_width = 0, 576 .hid_width = 5, 577 .parent_map = gcc_parent_map_0, 578 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 579 .clkr.hw.init = &(const struct clk_init_data) { 580 .name = "gcc_pcie_0_phy_rchng_clk_src", 581 .parent_data = gcc_parent_data_0, 582 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 583 .ops = &clk_rcg2_ops, 584 }, 585 }; 586 587 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 588 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 589 { } 590 }; 591 592 static struct clk_rcg2 gcc_pdm2_clk_src = { 593 .cmd_rcgr = 0x43010, 594 .mnd_width = 0, 595 .hid_width = 5, 596 .parent_map = gcc_parent_map_0, 597 .freq_tbl = ftbl_gcc_pdm2_clk_src, 598 .clkr.hw.init = &(const struct clk_init_data) { 599 .name = "gcc_pdm2_clk_src", 600 .parent_data = gcc_parent_data_0, 601 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 602 .ops = &clk_rcg2_ops, 603 }, 604 }; 605 606 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 607 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 608 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 609 F(19200000, P_BI_TCXO, 1, 0, 0), 610 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 611 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 612 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 613 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 614 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 615 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 616 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 617 { } 618 }; 619 620 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 621 .name = "gcc_qupv3_wrap0_s0_clk_src", 622 .parent_data = gcc_parent_data_0, 623 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 624 .ops = &clk_rcg2_ops, 625 }; 626 627 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 628 .cmd_rcgr = 0x27154, 629 .mnd_width = 16, 630 .hid_width = 5, 631 .parent_map = gcc_parent_map_0, 632 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 633 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 634 }; 635 636 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 637 .name = "gcc_qupv3_wrap0_s1_clk_src", 638 .parent_data = gcc_parent_data_0, 639 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 640 .ops = &clk_rcg2_ops, 641 }; 642 643 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 644 .cmd_rcgr = 0x27288, 645 .mnd_width = 16, 646 .hid_width = 5, 647 .parent_map = gcc_parent_map_0, 648 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 649 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 650 }; 651 652 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 653 .name = "gcc_qupv3_wrap0_s2_clk_src", 654 .parent_data = gcc_parent_data_0, 655 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 656 .ops = &clk_rcg2_ops, 657 }; 658 659 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 660 .cmd_rcgr = 0x273bc, 661 .mnd_width = 16, 662 .hid_width = 5, 663 .parent_map = gcc_parent_map_0, 664 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 665 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 666 }; 667 668 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 669 .name = "gcc_qupv3_wrap0_s3_clk_src", 670 .parent_data = gcc_parent_data_0, 671 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 672 .ops = &clk_rcg2_ops, 673 }; 674 675 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 676 .cmd_rcgr = 0x274f0, 677 .mnd_width = 16, 678 .hid_width = 5, 679 .parent_map = gcc_parent_map_0, 680 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 681 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 682 }; 683 684 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 685 .name = "gcc_qupv3_wrap0_s4_clk_src", 686 .parent_data = gcc_parent_data_0, 687 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 688 .ops = &clk_rcg2_ops, 689 }; 690 691 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 692 .cmd_rcgr = 0x27624, 693 .mnd_width = 16, 694 .hid_width = 5, 695 .parent_map = gcc_parent_map_0, 696 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 697 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 698 }; 699 700 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] = { 701 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 702 { } 703 }; 704 705 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 706 .name = "gcc_qupv3_wrap0_s5_clk_src", 707 .parent_data = gcc_parent_data_0, 708 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 709 .ops = &clk_rcg2_ops, 710 }; 711 712 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 713 .cmd_rcgr = 0x27758, 714 .mnd_width = 16, 715 .hid_width = 5, 716 .parent_map = gcc_parent_map_0, 717 .freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src, 718 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 719 }; 720 721 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 722 .name = "gcc_qupv3_wrap0_s6_clk_src", 723 .parent_data = gcc_parent_data_0, 724 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 725 .ops = &clk_rcg2_ops, 726 }; 727 728 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 729 .cmd_rcgr = 0x2788c, 730 .mnd_width = 16, 731 .hid_width = 5, 732 .parent_map = gcc_parent_map_0, 733 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 734 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 735 }; 736 737 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 738 .name = "gcc_qupv3_wrap0_s7_clk_src", 739 .parent_data = gcc_parent_data_0, 740 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 741 .ops = &clk_rcg2_ops, 742 }; 743 744 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 745 .cmd_rcgr = 0x279c0, 746 .mnd_width = 16, 747 .hid_width = 5, 748 .parent_map = gcc_parent_map_0, 749 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 750 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 751 }; 752 753 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 754 .name = "gcc_qupv3_wrap1_s0_clk_src", 755 .parent_data = gcc_parent_data_0, 756 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 757 .ops = &clk_rcg2_ops, 758 }; 759 760 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 761 .cmd_rcgr = 0x28154, 762 .mnd_width = 16, 763 .hid_width = 5, 764 .parent_map = gcc_parent_map_0, 765 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 766 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 767 }; 768 769 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 770 .name = "gcc_qupv3_wrap1_s1_clk_src", 771 .parent_data = gcc_parent_data_0, 772 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 773 .ops = &clk_rcg2_ops, 774 }; 775 776 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 777 .cmd_rcgr = 0x28288, 778 .mnd_width = 16, 779 .hid_width = 5, 780 .parent_map = gcc_parent_map_0, 781 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 782 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 783 }; 784 785 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 786 .name = "gcc_qupv3_wrap1_s2_clk_src", 787 .parent_data = gcc_parent_data_0, 788 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 789 .ops = &clk_rcg2_ops, 790 }; 791 792 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 793 .cmd_rcgr = 0x283bc, 794 .mnd_width = 16, 795 .hid_width = 5, 796 .parent_map = gcc_parent_map_0, 797 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 798 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 799 }; 800 801 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 802 .name = "gcc_qupv3_wrap1_s3_clk_src", 803 .parent_data = gcc_parent_data_0, 804 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 805 .ops = &clk_rcg2_ops, 806 }; 807 808 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 809 .cmd_rcgr = 0x284f0, 810 .mnd_width = 16, 811 .hid_width = 5, 812 .parent_map = gcc_parent_map_0, 813 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 814 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 815 }; 816 817 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 818 .name = "gcc_qupv3_wrap1_s4_clk_src", 819 .parent_data = gcc_parent_data_0, 820 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 821 .ops = &clk_rcg2_ops, 822 }; 823 824 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 825 .cmd_rcgr = 0x28624, 826 .mnd_width = 16, 827 .hid_width = 5, 828 .parent_map = gcc_parent_map_0, 829 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 830 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 831 }; 832 833 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 834 .name = "gcc_qupv3_wrap1_s5_clk_src", 835 .parent_data = gcc_parent_data_0, 836 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 837 .ops = &clk_rcg2_ops, 838 }; 839 840 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 841 .cmd_rcgr = 0x28758, 842 .mnd_width = 16, 843 .hid_width = 5, 844 .parent_map = gcc_parent_map_0, 845 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 846 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 847 }; 848 849 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 850 .name = "gcc_qupv3_wrap1_s6_clk_src", 851 .parent_data = gcc_parent_data_0, 852 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 853 .ops = &clk_rcg2_ops, 854 }; 855 856 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 857 .cmd_rcgr = 0x2888c, 858 .mnd_width = 16, 859 .hid_width = 5, 860 .parent_map = gcc_parent_map_0, 861 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 862 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 863 }; 864 865 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 866 .name = "gcc_qupv3_wrap1_s7_clk_src", 867 .parent_data = gcc_parent_data_0, 868 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 869 .ops = &clk_rcg2_ops, 870 }; 871 872 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 873 .cmd_rcgr = 0x289c0, 874 .mnd_width = 16, 875 .hid_width = 5, 876 .parent_map = gcc_parent_map_0, 877 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 878 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 879 }; 880 881 static const struct freq_tbl ftbl_gcc_sdcc5_apps_clk_src[] = { 882 F(144000, P_BI_TCXO, 16, 3, 25), 883 F(400000, P_BI_TCXO, 12, 1, 4), 884 F(19200000, P_BI_TCXO, 1, 0, 0), 885 F(20000000, P_GCC_GPLL0_OUT_MAIN, 10, 1, 3), 886 F(25000000, P_GCC_GPLL0_OUT_MAIN, 12, 1, 2), 887 F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0), 888 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 889 F(192000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0), 890 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 891 F(384000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0), 892 { } 893 }; 894 895 static struct clk_rcg2 gcc_sdcc5_apps_clk_src = { 896 .cmd_rcgr = 0x3b034, 897 .mnd_width = 8, 898 .hid_width = 5, 899 .parent_map = gcc_parent_map_8, 900 .freq_tbl = ftbl_gcc_sdcc5_apps_clk_src, 901 .clkr.hw.init = &(const struct clk_init_data) { 902 .name = "gcc_sdcc5_apps_clk_src", 903 .parent_data = gcc_parent_data_8, 904 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 905 .ops = &clk_rcg2_ops, 906 }, 907 }; 908 909 static const struct freq_tbl ftbl_gcc_sdcc5_ice_core_clk_src[] = { 910 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 911 { } 912 }; 913 914 static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src = { 915 .cmd_rcgr = 0x3b01c, 916 .mnd_width = 0, 917 .hid_width = 5, 918 .parent_map = gcc_parent_map_2, 919 .freq_tbl = ftbl_gcc_sdcc5_ice_core_clk_src, 920 .clkr.hw.init = &(const struct clk_init_data) { 921 .name = "gcc_sdcc5_ice_core_clk_src", 922 .parent_data = gcc_parent_data_2, 923 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 924 .ops = &clk_rcg2_ops, 925 }, 926 }; 927 928 static struct clk_rcg2 gcc_sm_bus_xo_clk_src = { 929 .cmd_rcgr = 0x5b00c, 930 .mnd_width = 0, 931 .hid_width = 5, 932 .parent_map = gcc_parent_map_2, 933 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 934 .clkr.hw.init = &(const struct clk_init_data) { 935 .name = "gcc_sm_bus_xo_clk_src", 936 .parent_data = gcc_parent_data_2, 937 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 938 .ops = &clk_rcg2_ops, 939 }, 940 }; 941 942 static const struct freq_tbl ftbl_gcc_tsc_clk_src[] = { 943 F(500000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0), 944 { } 945 }; 946 947 static struct clk_rcg2 gcc_tsc_clk_src = { 948 .cmd_rcgr = 0x57010, 949 .mnd_width = 0, 950 .hid_width = 5, 951 .parent_map = gcc_parent_map_9, 952 .freq_tbl = ftbl_gcc_tsc_clk_src, 953 .clkr.hw.init = &(const struct clk_init_data) { 954 .name = "gcc_tsc_clk_src", 955 .parent_data = gcc_parent_data_9, 956 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 957 .ops = &clk_rcg2_ops, 958 }, 959 }; 960 961 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 962 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 963 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 964 { } 965 }; 966 967 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 968 .cmd_rcgr = 0x49028, 969 .mnd_width = 8, 970 .hid_width = 5, 971 .parent_map = gcc_parent_map_0, 972 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 973 .clkr.hw.init = &(const struct clk_init_data) { 974 .name = "gcc_usb30_prim_master_clk_src", 975 .parent_data = gcc_parent_data_0, 976 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 977 .ops = &clk_rcg2_ops, 978 }, 979 }; 980 981 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 982 .cmd_rcgr = 0x49044, 983 .mnd_width = 0, 984 .hid_width = 5, 985 .parent_map = gcc_parent_map_0, 986 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 987 .clkr.hw.init = &(const struct clk_init_data) { 988 .name = "gcc_usb30_prim_mock_utmi_clk_src", 989 .parent_data = gcc_parent_data_0, 990 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 991 .ops = &clk_rcg2_ops, 992 }, 993 }; 994 995 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 996 .cmd_rcgr = 0x49070, 997 .mnd_width = 0, 998 .hid_width = 5, 999 .parent_map = gcc_parent_map_3, 1000 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1001 .clkr.hw.init = &(const struct clk_init_data) { 1002 .name = "gcc_usb3_prim_phy_aux_clk_src", 1003 .parent_data = gcc_parent_data_3, 1004 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1005 .ops = &clk_rcg2_ops, 1006 }, 1007 }; 1008 1009 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1010 .reg = 0x4905c, 1011 .shift = 0, 1012 .width = 4, 1013 .clkr.hw.init = &(const struct clk_init_data) { 1014 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1015 .parent_hws = (const struct clk_hw*[]) { 1016 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1017 }, 1018 .num_parents = 1, 1019 .flags = CLK_SET_RATE_PARENT, 1020 .ops = &clk_regmap_div_ro_ops, 1021 }, 1022 }; 1023 1024 static struct clk_branch gcc_aggre_noc_ecpri_dma_clk = { 1025 .halt_reg = 0x92008, 1026 .halt_check = BRANCH_HALT_VOTED, 1027 .hwcg_reg = 0x92008, 1028 .hwcg_bit = 1, 1029 .clkr = { 1030 .enable_reg = 0x92008, 1031 .enable_mask = BIT(0), 1032 .hw.init = &(const struct clk_init_data) { 1033 .name = "gcc_aggre_noc_ecpri_dma_clk", 1034 .parent_hws = (const struct clk_hw*[]) { 1035 &gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw, 1036 }, 1037 .num_parents = 1, 1038 .flags = CLK_SET_RATE_PARENT, 1039 .ops = &clk_branch2_ops, 1040 }, 1041 }, 1042 }; 1043 1044 static struct clk_branch gcc_aggre_noc_ecpri_gsi_clk = { 1045 .halt_reg = 0x9201c, 1046 .halt_check = BRANCH_HALT_VOTED, 1047 .hwcg_reg = 0x9201c, 1048 .hwcg_bit = 1, 1049 .clkr = { 1050 .enable_reg = 0x9201c, 1051 .enable_mask = BIT(0), 1052 .hw.init = &(const struct clk_init_data) { 1053 .name = "gcc_aggre_noc_ecpri_gsi_clk", 1054 .parent_hws = (const struct clk_hw*[]) { 1055 &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, 1056 }, 1057 .num_parents = 1, 1058 .flags = CLK_SET_RATE_PARENT, 1059 .ops = &clk_branch2_ops, 1060 }, 1061 }, 1062 }; 1063 1064 static struct clk_branch gcc_boot_rom_ahb_clk = { 1065 .halt_reg = 0x48004, 1066 .halt_check = BRANCH_HALT_VOTED, 1067 .hwcg_reg = 0x48004, 1068 .hwcg_bit = 1, 1069 .clkr = { 1070 .enable_reg = 0x62000, 1071 .enable_mask = BIT(10), 1072 .hw.init = &(const struct clk_init_data) { 1073 .name = "gcc_boot_rom_ahb_clk", 1074 .ops = &clk_branch2_ops, 1075 }, 1076 }, 1077 }; 1078 1079 static struct clk_branch gcc_cfg_noc_ecpri_cc_ahb_clk = { 1080 .halt_reg = 0x3e004, 1081 .halt_check = BRANCH_HALT_VOTED, 1082 .hwcg_reg = 0x3e004, 1083 .hwcg_bit = 1, 1084 .clkr = { 1085 .enable_reg = 0x3e004, 1086 .enable_mask = BIT(0), 1087 .hw.init = &(const struct clk_init_data) { 1088 .name = "gcc_cfg_noc_ecpri_cc_ahb_clk", 1089 .ops = &clk_branch2_ops, 1090 }, 1091 }, 1092 }; 1093 1094 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1095 .halt_reg = 0x8401c, 1096 .halt_check = BRANCH_HALT_VOTED, 1097 .hwcg_reg = 0x8401c, 1098 .hwcg_bit = 1, 1099 .clkr = { 1100 .enable_reg = 0x8401c, 1101 .enable_mask = BIT(0), 1102 .hw.init = &(const struct clk_init_data) { 1103 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1104 .parent_hws = (const struct clk_hw*[]) { 1105 &gcc_usb30_prim_master_clk_src.clkr.hw, 1106 }, 1107 .num_parents = 1, 1108 .flags = CLK_SET_RATE_PARENT, 1109 .ops = &clk_branch2_ops, 1110 }, 1111 }, 1112 }; 1113 1114 static struct clk_branch gcc_ddrss_ecpri_dma_clk = { 1115 .halt_reg = 0x54030, 1116 .halt_check = BRANCH_HALT_VOTED, 1117 .hwcg_reg = 0x54030, 1118 .hwcg_bit = 1, 1119 .clkr = { 1120 .enable_reg = 0x54030, 1121 .enable_mask = BIT(0), 1122 .hw.init = &(const struct clk_init_data) { 1123 .name = "gcc_ddrss_ecpri_dma_clk", 1124 .parent_hws = (const struct clk_hw*[]) { 1125 &gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw, 1126 }, 1127 .num_parents = 1, 1128 .flags = CLK_SET_RATE_PARENT, 1129 .ops = &clk_branch2_aon_ops, 1130 }, 1131 }, 1132 }; 1133 1134 static struct clk_branch gcc_ecpri_ahb_clk = { 1135 .halt_reg = 0x3a008, 1136 .halt_check = BRANCH_HALT_VOTED, 1137 .hwcg_reg = 0x3a008, 1138 .hwcg_bit = 1, 1139 .clkr = { 1140 .enable_reg = 0x3a008, 1141 .enable_mask = BIT(0), 1142 .hw.init = &(const struct clk_init_data) { 1143 .name = "gcc_ecpri_ahb_clk", 1144 .ops = &clk_branch2_ops, 1145 }, 1146 }, 1147 }; 1148 1149 static struct clk_branch gcc_ecpri_cc_gpll0_clk_src = { 1150 .halt_check = BRANCH_HALT_DELAY, 1151 .clkr = { 1152 .enable_reg = 0x62010, 1153 .enable_mask = BIT(0), 1154 .hw.init = &(const struct clk_init_data) { 1155 .name = "gcc_ecpri_cc_gpll0_clk_src", 1156 .parent_hws = (const struct clk_hw*[]) { 1157 &gcc_gpll0.clkr.hw, 1158 }, 1159 .num_parents = 1, 1160 .flags = CLK_SET_RATE_PARENT, 1161 .ops = &clk_branch2_ops, 1162 }, 1163 }, 1164 }; 1165 1166 static struct clk_branch gcc_ecpri_cc_gpll1_even_clk_src = { 1167 .halt_check = BRANCH_HALT_DELAY, 1168 .clkr = { 1169 .enable_reg = 0x62010, 1170 .enable_mask = BIT(1), 1171 .hw.init = &(const struct clk_init_data) { 1172 .name = "gcc_ecpri_cc_gpll1_even_clk_src", 1173 .parent_hws = (const struct clk_hw*[]) { 1174 &gcc_gpll1_out_even.clkr.hw, 1175 }, 1176 .num_parents = 1, 1177 .flags = CLK_SET_RATE_PARENT, 1178 .ops = &clk_branch2_ops, 1179 }, 1180 }, 1181 }; 1182 1183 static struct clk_branch gcc_ecpri_cc_gpll2_even_clk_src = { 1184 .halt_check = BRANCH_HALT_DELAY, 1185 .clkr = { 1186 .enable_reg = 0x62010, 1187 .enable_mask = BIT(2), 1188 .hw.init = &(const struct clk_init_data) { 1189 .name = "gcc_ecpri_cc_gpll2_even_clk_src", 1190 .parent_hws = (const struct clk_hw*[]) { 1191 &gcc_gpll2_out_even.clkr.hw, 1192 }, 1193 .num_parents = 1, 1194 .flags = CLK_SET_RATE_PARENT, 1195 .ops = &clk_branch2_ops, 1196 }, 1197 }, 1198 }; 1199 1200 static struct clk_branch gcc_ecpri_cc_gpll3_clk_src = { 1201 .halt_check = BRANCH_HALT_DELAY, 1202 .clkr = { 1203 .enable_reg = 0x62010, 1204 .enable_mask = BIT(3), 1205 .hw.init = &(const struct clk_init_data) { 1206 .name = "gcc_ecpri_cc_gpll3_clk_src", 1207 .parent_hws = (const struct clk_hw*[]) { 1208 &gcc_gpll3.clkr.hw, 1209 }, 1210 .num_parents = 1, 1211 .flags = CLK_SET_RATE_PARENT, 1212 .ops = &clk_branch2_ops, 1213 }, 1214 }, 1215 }; 1216 1217 static struct clk_branch gcc_ecpri_cc_gpll4_clk_src = { 1218 .halt_check = BRANCH_HALT_DELAY, 1219 .clkr = { 1220 .enable_reg = 0x62010, 1221 .enable_mask = BIT(4), 1222 .hw.init = &(const struct clk_init_data) { 1223 .name = "gcc_ecpri_cc_gpll4_clk_src", 1224 .parent_hws = (const struct clk_hw*[]) { 1225 &gcc_gpll4.clkr.hw, 1226 }, 1227 .num_parents = 1, 1228 .flags = CLK_SET_RATE_PARENT, 1229 .ops = &clk_branch2_ops, 1230 }, 1231 }, 1232 }; 1233 1234 static struct clk_branch gcc_ecpri_cc_gpll5_even_clk_src = { 1235 .halt_check = BRANCH_HALT_DELAY, 1236 .clkr = { 1237 .enable_reg = 0x62010, 1238 .enable_mask = BIT(5), 1239 .hw.init = &(const struct clk_init_data) { 1240 .name = "gcc_ecpri_cc_gpll5_even_clk_src", 1241 .parent_hws = (const struct clk_hw*[]) { 1242 &gcc_gpll5_out_even.clkr.hw, 1243 }, 1244 .num_parents = 1, 1245 .flags = CLK_SET_RATE_PARENT, 1246 .ops = &clk_branch2_ops, 1247 }, 1248 }, 1249 }; 1250 1251 static struct clk_branch gcc_ecpri_xo_clk = { 1252 .halt_reg = 0x3a004, 1253 .halt_check = BRANCH_HALT, 1254 .clkr = { 1255 .enable_reg = 0x3a004, 1256 .enable_mask = BIT(0), 1257 .hw.init = &(const struct clk_init_data) { 1258 .name = "gcc_ecpri_xo_clk", 1259 .ops = &clk_branch2_ops, 1260 }, 1261 }, 1262 }; 1263 1264 static struct clk_branch gcc_eth_100g_c2c_hm_apb_clk = { 1265 .halt_reg = 0x39010, 1266 .halt_check = BRANCH_HALT, 1267 .clkr = { 1268 .enable_reg = 0x39010, 1269 .enable_mask = BIT(0), 1270 .hw.init = &(const struct clk_init_data) { 1271 .name = "gcc_eth_100g_c2c_hm_apb_clk", 1272 .ops = &clk_branch2_ops, 1273 }, 1274 }, 1275 }; 1276 1277 static struct clk_branch gcc_eth_100g_fh_hm_apb_0_clk = { 1278 .halt_reg = 0x39004, 1279 .halt_check = BRANCH_HALT, 1280 .clkr = { 1281 .enable_reg = 0x39004, 1282 .enable_mask = BIT(0), 1283 .hw.init = &(const struct clk_init_data) { 1284 .name = "gcc_eth_100g_fh_hm_apb_0_clk", 1285 .ops = &clk_branch2_ops, 1286 }, 1287 }, 1288 }; 1289 1290 static struct clk_branch gcc_eth_100g_fh_hm_apb_1_clk = { 1291 .halt_reg = 0x39008, 1292 .halt_check = BRANCH_HALT, 1293 .clkr = { 1294 .enable_reg = 0x39008, 1295 .enable_mask = BIT(0), 1296 .hw.init = &(const struct clk_init_data) { 1297 .name = "gcc_eth_100g_fh_hm_apb_1_clk", 1298 .ops = &clk_branch2_ops, 1299 }, 1300 }, 1301 }; 1302 1303 static struct clk_branch gcc_eth_100g_fh_hm_apb_2_clk = { 1304 .halt_reg = 0x3900c, 1305 .halt_check = BRANCH_HALT, 1306 .clkr = { 1307 .enable_reg = 0x3900c, 1308 .enable_mask = BIT(0), 1309 .hw.init = &(const struct clk_init_data) { 1310 .name = "gcc_eth_100g_fh_hm_apb_2_clk", 1311 .ops = &clk_branch2_ops, 1312 }, 1313 }, 1314 }; 1315 1316 static struct clk_branch gcc_eth_dbg_c2c_hm_apb_clk = { 1317 .halt_reg = 0x39014, 1318 .halt_check = BRANCH_HALT, 1319 .clkr = { 1320 .enable_reg = 0x39014, 1321 .enable_mask = BIT(0), 1322 .hw.init = &(const struct clk_init_data) { 1323 .name = "gcc_eth_dbg_c2c_hm_apb_clk", 1324 .ops = &clk_branch2_ops, 1325 }, 1326 }, 1327 }; 1328 1329 static struct clk_branch gcc_eth_dbg_snoc_axi_clk = { 1330 .halt_reg = 0x3901c, 1331 .halt_check = BRANCH_HALT_VOTED, 1332 .hwcg_reg = 0x3901c, 1333 .hwcg_bit = 1, 1334 .clkr = { 1335 .enable_reg = 0x3901c, 1336 .enable_mask = BIT(0), 1337 .hw.init = &(const struct clk_init_data) { 1338 .name = "gcc_eth_dbg_snoc_axi_clk", 1339 .ops = &clk_branch2_ops, 1340 }, 1341 }, 1342 }; 1343 1344 static struct clk_branch gcc_gemnoc_pcie_qx_clk = { 1345 .halt_reg = 0x5402c, 1346 .halt_check = BRANCH_HALT_VOTED, 1347 .hwcg_reg = 0x5402c, 1348 .hwcg_bit = 1, 1349 .clkr = { 1350 .enable_reg = 0x62008, 1351 .enable_mask = BIT(0), 1352 .hw.init = &(const struct clk_init_data) { 1353 .name = "gcc_gemnoc_pcie_qx_clk", 1354 .ops = &clk_branch2_aon_ops, 1355 }, 1356 }, 1357 }; 1358 1359 static struct clk_branch gcc_gp1_clk = { 1360 .halt_reg = 0x74000, 1361 .halt_check = BRANCH_HALT, 1362 .clkr = { 1363 .enable_reg = 0x74000, 1364 .enable_mask = BIT(0), 1365 .hw.init = &(const struct clk_init_data) { 1366 .name = "gcc_gp1_clk", 1367 .parent_hws = (const struct clk_hw*[]) { 1368 &gcc_gp1_clk_src.clkr.hw, 1369 }, 1370 .num_parents = 1, 1371 .flags = CLK_SET_RATE_PARENT, 1372 .ops = &clk_branch2_ops, 1373 }, 1374 }, 1375 }; 1376 1377 static struct clk_branch gcc_gp2_clk = { 1378 .halt_reg = 0x75000, 1379 .halt_check = BRANCH_HALT, 1380 .clkr = { 1381 .enable_reg = 0x75000, 1382 .enable_mask = BIT(0), 1383 .hw.init = &(const struct clk_init_data) { 1384 .name = "gcc_gp2_clk", 1385 .parent_hws = (const struct clk_hw*[]) { 1386 &gcc_gp2_clk_src.clkr.hw, 1387 }, 1388 .num_parents = 1, 1389 .flags = CLK_SET_RATE_PARENT, 1390 .ops = &clk_branch2_ops, 1391 }, 1392 }, 1393 }; 1394 1395 static struct clk_branch gcc_gp3_clk = { 1396 .halt_reg = 0x76000, 1397 .halt_check = BRANCH_HALT, 1398 .clkr = { 1399 .enable_reg = 0x76000, 1400 .enable_mask = BIT(0), 1401 .hw.init = &(const struct clk_init_data) { 1402 .name = "gcc_gp3_clk", 1403 .parent_hws = (const struct clk_hw*[]) { 1404 &gcc_gp3_clk_src.clkr.hw, 1405 }, 1406 .num_parents = 1, 1407 .flags = CLK_SET_RATE_PARENT, 1408 .ops = &clk_branch2_ops, 1409 }, 1410 }, 1411 }; 1412 1413 static struct clk_branch gcc_pcie_0_aux_clk = { 1414 .halt_reg = 0x9d030, 1415 .halt_check = BRANCH_HALT_VOTED, 1416 .hwcg_reg = 0x9d030, 1417 .hwcg_bit = 1, 1418 .clkr = { 1419 .enable_reg = 0x62000, 1420 .enable_mask = BIT(29), 1421 .hw.init = &(const struct clk_init_data) { 1422 .name = "gcc_pcie_0_aux_clk", 1423 .parent_hws = (const struct clk_hw*[]) { 1424 &gcc_pcie_0_aux_clk_src.clkr.hw, 1425 }, 1426 .num_parents = 1, 1427 .flags = CLK_SET_RATE_PARENT, 1428 .ops = &clk_branch2_ops, 1429 }, 1430 }, 1431 }; 1432 1433 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1434 .halt_reg = 0x9d02c, 1435 .halt_check = BRANCH_HALT_VOTED, 1436 .hwcg_reg = 0x9d02c, 1437 .hwcg_bit = 1, 1438 .clkr = { 1439 .enable_reg = 0x62000, 1440 .enable_mask = BIT(28), 1441 .hw.init = &(const struct clk_init_data) { 1442 .name = "gcc_pcie_0_cfg_ahb_clk", 1443 .ops = &clk_branch2_ops, 1444 }, 1445 }, 1446 }; 1447 1448 static struct clk_branch gcc_pcie_0_clkref_en = { 1449 .halt_reg = 0x9c004, 1450 .halt_check = BRANCH_HALT, 1451 .clkr = { 1452 .enable_reg = 0x9c004, 1453 .enable_mask = BIT(0), 1454 .hw.init = &(const struct clk_init_data) { 1455 .name = "gcc_pcie_0_clkref_en", 1456 .ops = &clk_branch2_ops, 1457 }, 1458 }, 1459 }; 1460 1461 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1462 .halt_reg = 0x9d024, 1463 .halt_check = BRANCH_HALT_SKIP, 1464 .hwcg_reg = 0x9d024, 1465 .hwcg_bit = 1, 1466 .clkr = { 1467 .enable_reg = 0x62000, 1468 .enable_mask = BIT(27), 1469 .hw.init = &(const struct clk_init_data) { 1470 .name = "gcc_pcie_0_mstr_axi_clk", 1471 .ops = &clk_branch2_ops, 1472 }, 1473 }, 1474 }; 1475 1476 static struct clk_branch gcc_pcie_0_phy_aux_clk = { 1477 .halt_reg = 0x9d038, 1478 .halt_check = BRANCH_HALT_VOTED, 1479 .hwcg_reg = 0x9d038, 1480 .hwcg_bit = 1, 1481 .clkr = { 1482 .enable_reg = 0x62000, 1483 .enable_mask = BIT(24), 1484 .hw.init = &(const struct clk_init_data) { 1485 .name = "gcc_pcie_0_phy_aux_clk", 1486 .parent_hws = (const struct clk_hw*[]) { 1487 &gcc_pcie_0_phy_aux_clk_src.clkr.hw, 1488 }, 1489 .num_parents = 1, 1490 .flags = CLK_SET_RATE_PARENT, 1491 .ops = &clk_branch2_ops, 1492 }, 1493 }, 1494 }; 1495 1496 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 1497 .halt_reg = 0x9d048, 1498 .halt_check = BRANCH_HALT_VOTED, 1499 .hwcg_reg = 0x9d048, 1500 .hwcg_bit = 1, 1501 .clkr = { 1502 .enable_reg = 0x62000, 1503 .enable_mask = BIT(23), 1504 .hw.init = &(const struct clk_init_data) { 1505 .name = "gcc_pcie_0_phy_rchng_clk", 1506 .parent_hws = (const struct clk_hw*[]) { 1507 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1508 }, 1509 .num_parents = 1, 1510 .flags = CLK_SET_RATE_PARENT, 1511 .ops = &clk_branch2_ops, 1512 }, 1513 }, 1514 }; 1515 1516 static struct clk_branch gcc_pcie_0_pipe_clk = { 1517 .halt_reg = 0x9d040, 1518 .halt_check = BRANCH_HALT_VOTED, 1519 .hwcg_reg = 0x9d040, 1520 .hwcg_bit = 1, 1521 .clkr = { 1522 .enable_reg = 0x62000, 1523 .enable_mask = BIT(30), 1524 .hw.init = &(const struct clk_init_data) { 1525 .name = "gcc_pcie_0_pipe_clk", 1526 .parent_hws = (const struct clk_hw*[]) { 1527 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1528 }, 1529 .num_parents = 1, 1530 .flags = CLK_SET_RATE_PARENT, 1531 .ops = &clk_branch2_ops, 1532 }, 1533 }, 1534 }; 1535 1536 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1537 .halt_reg = 0x9d01c, 1538 .halt_check = BRANCH_HALT_VOTED, 1539 .hwcg_reg = 0x9d01c, 1540 .hwcg_bit = 1, 1541 .clkr = { 1542 .enable_reg = 0x62000, 1543 .enable_mask = BIT(26), 1544 .hw.init = &(const struct clk_init_data) { 1545 .name = "gcc_pcie_0_slv_axi_clk", 1546 .ops = &clk_branch2_ops, 1547 }, 1548 }, 1549 }; 1550 1551 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1552 .halt_reg = 0x9d018, 1553 .halt_check = BRANCH_HALT_VOTED, 1554 .hwcg_reg = 0x9d018, 1555 .hwcg_bit = 1, 1556 .clkr = { 1557 .enable_reg = 0x62000, 1558 .enable_mask = BIT(25), 1559 .hw.init = &(const struct clk_init_data) { 1560 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1561 .ops = &clk_branch2_ops, 1562 }, 1563 }, 1564 }; 1565 1566 static struct clk_branch gcc_pdm2_clk = { 1567 .halt_reg = 0x4300c, 1568 .halt_check = BRANCH_HALT, 1569 .clkr = { 1570 .enable_reg = 0x4300c, 1571 .enable_mask = BIT(0), 1572 .hw.init = &(const struct clk_init_data) { 1573 .name = "gcc_pdm2_clk", 1574 .parent_hws = (const struct clk_hw*[]) { 1575 &gcc_pdm2_clk_src.clkr.hw, 1576 }, 1577 .num_parents = 1, 1578 .flags = CLK_SET_RATE_PARENT, 1579 .ops = &clk_branch2_ops, 1580 }, 1581 }, 1582 }; 1583 1584 static struct clk_branch gcc_pdm_ahb_clk = { 1585 .halt_reg = 0x43004, 1586 .halt_check = BRANCH_HALT_VOTED, 1587 .hwcg_reg = 0x43004, 1588 .hwcg_bit = 1, 1589 .clkr = { 1590 .enable_reg = 0x43004, 1591 .enable_mask = BIT(0), 1592 .hw.init = &(const struct clk_init_data) { 1593 .name = "gcc_pdm_ahb_clk", 1594 .ops = &clk_branch2_ops, 1595 }, 1596 }, 1597 }; 1598 1599 static struct clk_branch gcc_pdm_xo4_clk = { 1600 .halt_reg = 0x43008, 1601 .halt_check = BRANCH_HALT, 1602 .clkr = { 1603 .enable_reg = 0x43008, 1604 .enable_mask = BIT(0), 1605 .hw.init = &(const struct clk_init_data) { 1606 .name = "gcc_pdm_xo4_clk", 1607 .ops = &clk_branch2_ops, 1608 }, 1609 }, 1610 }; 1611 1612 static struct clk_branch gcc_qmip_anoc_pcie_clk = { 1613 .halt_reg = 0x84044, 1614 .halt_check = BRANCH_HALT_VOTED, 1615 .hwcg_reg = 0x84044, 1616 .hwcg_bit = 1, 1617 .clkr = { 1618 .enable_reg = 0x84044, 1619 .enable_mask = BIT(0), 1620 .hw.init = &(const struct clk_init_data) { 1621 .name = "gcc_qmip_anoc_pcie_clk", 1622 .ops = &clk_branch2_ops, 1623 }, 1624 }, 1625 }; 1626 1627 static struct clk_branch gcc_qmip_ecpri_dma0_clk = { 1628 .halt_reg = 0x84038, 1629 .halt_check = BRANCH_HALT_VOTED, 1630 .hwcg_reg = 0x84038, 1631 .hwcg_bit = 1, 1632 .clkr = { 1633 .enable_reg = 0x84038, 1634 .enable_mask = BIT(0), 1635 .hw.init = &(const struct clk_init_data) { 1636 .name = "gcc_qmip_ecpri_dma0_clk", 1637 .ops = &clk_branch2_ops, 1638 }, 1639 }, 1640 }; 1641 1642 static struct clk_branch gcc_qmip_ecpri_dma1_clk = { 1643 .halt_reg = 0x8403c, 1644 .halt_check = BRANCH_HALT_VOTED, 1645 .hwcg_reg = 0x8403c, 1646 .hwcg_bit = 1, 1647 .clkr = { 1648 .enable_reg = 0x8403c, 1649 .enable_mask = BIT(0), 1650 .hw.init = &(const struct clk_init_data) { 1651 .name = "gcc_qmip_ecpri_dma1_clk", 1652 .ops = &clk_branch2_ops, 1653 }, 1654 }, 1655 }; 1656 1657 static struct clk_branch gcc_qmip_ecpri_gsi_clk = { 1658 .halt_reg = 0x84040, 1659 .halt_check = BRANCH_HALT_VOTED, 1660 .hwcg_reg = 0x84040, 1661 .hwcg_bit = 1, 1662 .clkr = { 1663 .enable_reg = 0x84040, 1664 .enable_mask = BIT(0), 1665 .hw.init = &(const struct clk_init_data) { 1666 .name = "gcc_qmip_ecpri_gsi_clk", 1667 .ops = &clk_branch2_ops, 1668 }, 1669 }, 1670 }; 1671 1672 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 1673 .halt_reg = 0x27018, 1674 .halt_check = BRANCH_HALT_VOTED, 1675 .clkr = { 1676 .enable_reg = 0x62008, 1677 .enable_mask = BIT(9), 1678 .hw.init = &(const struct clk_init_data) { 1679 .name = "gcc_qupv3_wrap0_core_2x_clk", 1680 .ops = &clk_branch2_ops, 1681 }, 1682 }, 1683 }; 1684 1685 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 1686 .halt_reg = 0x2700c, 1687 .halt_check = BRANCH_HALT_VOTED, 1688 .clkr = { 1689 .enable_reg = 0x62008, 1690 .enable_mask = BIT(8), 1691 .hw.init = &(const struct clk_init_data) { 1692 .name = "gcc_qupv3_wrap0_core_clk", 1693 .ops = &clk_branch2_ops, 1694 }, 1695 }, 1696 }; 1697 1698 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 1699 .halt_reg = 0x2714c, 1700 .halt_check = BRANCH_HALT_VOTED, 1701 .clkr = { 1702 .enable_reg = 0x62008, 1703 .enable_mask = BIT(10), 1704 .hw.init = &(const struct clk_init_data) { 1705 .name = "gcc_qupv3_wrap0_s0_clk", 1706 .parent_hws = (const struct clk_hw*[]) { 1707 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 1708 }, 1709 .num_parents = 1, 1710 .flags = CLK_SET_RATE_PARENT, 1711 .ops = &clk_branch2_ops, 1712 }, 1713 }, 1714 }; 1715 1716 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 1717 .halt_reg = 0x27280, 1718 .halt_check = BRANCH_HALT_VOTED, 1719 .clkr = { 1720 .enable_reg = 0x62008, 1721 .enable_mask = BIT(11), 1722 .hw.init = &(const struct clk_init_data) { 1723 .name = "gcc_qupv3_wrap0_s1_clk", 1724 .parent_hws = (const struct clk_hw*[]) { 1725 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 1726 }, 1727 .num_parents = 1, 1728 .flags = CLK_SET_RATE_PARENT, 1729 .ops = &clk_branch2_ops, 1730 }, 1731 }, 1732 }; 1733 1734 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 1735 .halt_reg = 0x273b4, 1736 .halt_check = BRANCH_HALT_VOTED, 1737 .clkr = { 1738 .enable_reg = 0x62008, 1739 .enable_mask = BIT(12), 1740 .hw.init = &(const struct clk_init_data) { 1741 .name = "gcc_qupv3_wrap0_s2_clk", 1742 .parent_hws = (const struct clk_hw*[]) { 1743 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 1744 }, 1745 .num_parents = 1, 1746 .flags = CLK_SET_RATE_PARENT, 1747 .ops = &clk_branch2_ops, 1748 }, 1749 }, 1750 }; 1751 1752 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 1753 .halt_reg = 0x274e8, 1754 .halt_check = BRANCH_HALT_VOTED, 1755 .clkr = { 1756 .enable_reg = 0x62008, 1757 .enable_mask = BIT(13), 1758 .hw.init = &(const struct clk_init_data) { 1759 .name = "gcc_qupv3_wrap0_s3_clk", 1760 .parent_hws = (const struct clk_hw*[]) { 1761 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 1762 }, 1763 .num_parents = 1, 1764 .flags = CLK_SET_RATE_PARENT, 1765 .ops = &clk_branch2_ops, 1766 }, 1767 }, 1768 }; 1769 1770 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 1771 .halt_reg = 0x2761c, 1772 .halt_check = BRANCH_HALT_VOTED, 1773 .clkr = { 1774 .enable_reg = 0x62008, 1775 .enable_mask = BIT(14), 1776 .hw.init = &(const struct clk_init_data) { 1777 .name = "gcc_qupv3_wrap0_s4_clk", 1778 .parent_hws = (const struct clk_hw*[]) { 1779 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 1780 }, 1781 .num_parents = 1, 1782 .flags = CLK_SET_RATE_PARENT, 1783 .ops = &clk_branch2_ops, 1784 }, 1785 }, 1786 }; 1787 1788 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 1789 .halt_reg = 0x27750, 1790 .halt_check = BRANCH_HALT_VOTED, 1791 .clkr = { 1792 .enable_reg = 0x62008, 1793 .enable_mask = BIT(15), 1794 .hw.init = &(const struct clk_init_data) { 1795 .name = "gcc_qupv3_wrap0_s5_clk", 1796 .parent_hws = (const struct clk_hw*[]) { 1797 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 1798 }, 1799 .num_parents = 1, 1800 .flags = CLK_SET_RATE_PARENT, 1801 .ops = &clk_branch2_ops, 1802 }, 1803 }, 1804 }; 1805 1806 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 1807 .halt_reg = 0x27884, 1808 .halt_check = BRANCH_HALT_VOTED, 1809 .clkr = { 1810 .enable_reg = 0x62008, 1811 .enable_mask = BIT(16), 1812 .hw.init = &(const struct clk_init_data) { 1813 .name = "gcc_qupv3_wrap0_s6_clk", 1814 .parent_hws = (const struct clk_hw*[]) { 1815 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 1816 }, 1817 .num_parents = 1, 1818 .flags = CLK_SET_RATE_PARENT, 1819 .ops = &clk_branch2_ops, 1820 }, 1821 }, 1822 }; 1823 1824 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 1825 .halt_reg = 0x279b8, 1826 .halt_check = BRANCH_HALT_VOTED, 1827 .clkr = { 1828 .enable_reg = 0x62008, 1829 .enable_mask = BIT(17), 1830 .hw.init = &(const struct clk_init_data) { 1831 .name = "gcc_qupv3_wrap0_s7_clk", 1832 .parent_hws = (const struct clk_hw*[]) { 1833 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 1834 }, 1835 .num_parents = 1, 1836 .flags = CLK_SET_RATE_PARENT, 1837 .ops = &clk_branch2_ops, 1838 }, 1839 }, 1840 }; 1841 1842 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 1843 .halt_reg = 0x28018, 1844 .halt_check = BRANCH_HALT_VOTED, 1845 .clkr = { 1846 .enable_reg = 0x62008, 1847 .enable_mask = BIT(18), 1848 .hw.init = &(const struct clk_init_data) { 1849 .name = "gcc_qupv3_wrap1_core_2x_clk", 1850 .ops = &clk_branch2_ops, 1851 }, 1852 }, 1853 }; 1854 1855 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 1856 .halt_reg = 0x2800c, 1857 .halt_check = BRANCH_HALT_VOTED, 1858 .clkr = { 1859 .enable_reg = 0x62008, 1860 .enable_mask = BIT(19), 1861 .hw.init = &(const struct clk_init_data) { 1862 .name = "gcc_qupv3_wrap1_core_clk", 1863 .ops = &clk_branch2_ops, 1864 }, 1865 }, 1866 }; 1867 1868 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 1869 .halt_reg = 0x2814c, 1870 .halt_check = BRANCH_HALT_VOTED, 1871 .clkr = { 1872 .enable_reg = 0x62008, 1873 .enable_mask = BIT(22), 1874 .hw.init = &(const struct clk_init_data) { 1875 .name = "gcc_qupv3_wrap1_s0_clk", 1876 .parent_hws = (const struct clk_hw*[]) { 1877 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 1878 }, 1879 .num_parents = 1, 1880 .flags = CLK_SET_RATE_PARENT, 1881 .ops = &clk_branch2_ops, 1882 }, 1883 }, 1884 }; 1885 1886 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 1887 .halt_reg = 0x28280, 1888 .halt_check = BRANCH_HALT_VOTED, 1889 .clkr = { 1890 .enable_reg = 0x62008, 1891 .enable_mask = BIT(23), 1892 .hw.init = &(const struct clk_init_data) { 1893 .name = "gcc_qupv3_wrap1_s1_clk", 1894 .parent_hws = (const struct clk_hw*[]) { 1895 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 1896 }, 1897 .num_parents = 1, 1898 .flags = CLK_SET_RATE_PARENT, 1899 .ops = &clk_branch2_ops, 1900 }, 1901 }, 1902 }; 1903 1904 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 1905 .halt_reg = 0x283b4, 1906 .halt_check = BRANCH_HALT_VOTED, 1907 .clkr = { 1908 .enable_reg = 0x62008, 1909 .enable_mask = BIT(24), 1910 .hw.init = &(const struct clk_init_data) { 1911 .name = "gcc_qupv3_wrap1_s2_clk", 1912 .parent_hws = (const struct clk_hw*[]) { 1913 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 1914 }, 1915 .num_parents = 1, 1916 .flags = CLK_SET_RATE_PARENT, 1917 .ops = &clk_branch2_ops, 1918 }, 1919 }, 1920 }; 1921 1922 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 1923 .halt_reg = 0x284e8, 1924 .halt_check = BRANCH_HALT_VOTED, 1925 .clkr = { 1926 .enable_reg = 0x62008, 1927 .enable_mask = BIT(25), 1928 .hw.init = &(const struct clk_init_data) { 1929 .name = "gcc_qupv3_wrap1_s3_clk", 1930 .parent_hws = (const struct clk_hw*[]) { 1931 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 1932 }, 1933 .num_parents = 1, 1934 .flags = CLK_SET_RATE_PARENT, 1935 .ops = &clk_branch2_ops, 1936 }, 1937 }, 1938 }; 1939 1940 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 1941 .halt_reg = 0x2861c, 1942 .halt_check = BRANCH_HALT_VOTED, 1943 .clkr = { 1944 .enable_reg = 0x62008, 1945 .enable_mask = BIT(26), 1946 .hw.init = &(const struct clk_init_data) { 1947 .name = "gcc_qupv3_wrap1_s4_clk", 1948 .parent_hws = (const struct clk_hw*[]) { 1949 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 1950 }, 1951 .num_parents = 1, 1952 .flags = CLK_SET_RATE_PARENT, 1953 .ops = &clk_branch2_ops, 1954 }, 1955 }, 1956 }; 1957 1958 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 1959 .halt_reg = 0x28750, 1960 .halt_check = BRANCH_HALT_VOTED, 1961 .clkr = { 1962 .enable_reg = 0x62008, 1963 .enable_mask = BIT(27), 1964 .hw.init = &(const struct clk_init_data) { 1965 .name = "gcc_qupv3_wrap1_s5_clk", 1966 .parent_hws = (const struct clk_hw*[]) { 1967 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 1968 }, 1969 .num_parents = 1, 1970 .flags = CLK_SET_RATE_PARENT, 1971 .ops = &clk_branch2_ops, 1972 }, 1973 }, 1974 }; 1975 1976 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 1977 .halt_reg = 0x28884, 1978 .halt_check = BRANCH_HALT_VOTED, 1979 .clkr = { 1980 .enable_reg = 0x62008, 1981 .enable_mask = BIT(28), 1982 .hw.init = &(const struct clk_init_data) { 1983 .name = "gcc_qupv3_wrap1_s6_clk", 1984 .parent_hws = (const struct clk_hw*[]) { 1985 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 1986 }, 1987 .num_parents = 1, 1988 .flags = CLK_SET_RATE_PARENT, 1989 .ops = &clk_branch2_ops, 1990 }, 1991 }, 1992 }; 1993 1994 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 1995 .halt_reg = 0x289b8, 1996 .halt_check = BRANCH_HALT_VOTED, 1997 .clkr = { 1998 .enable_reg = 0x62008, 1999 .enable_mask = BIT(29), 2000 .hw.init = &(const struct clk_init_data) { 2001 .name = "gcc_qupv3_wrap1_s7_clk", 2002 .parent_hws = (const struct clk_hw*[]) { 2003 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 2004 }, 2005 .num_parents = 1, 2006 .flags = CLK_SET_RATE_PARENT, 2007 .ops = &clk_branch2_ops, 2008 }, 2009 }, 2010 }; 2011 2012 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2013 .halt_reg = 0x27004, 2014 .halt_check = BRANCH_HALT_VOTED, 2015 .hwcg_reg = 0x27004, 2016 .hwcg_bit = 1, 2017 .clkr = { 2018 .enable_reg = 0x62008, 2019 .enable_mask = BIT(6), 2020 .hw.init = &(const struct clk_init_data) { 2021 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2022 .ops = &clk_branch2_ops, 2023 }, 2024 }, 2025 }; 2026 2027 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2028 .halt_reg = 0x27008, 2029 .halt_check = BRANCH_HALT_VOTED, 2030 .hwcg_reg = 0x27008, 2031 .hwcg_bit = 1, 2032 .clkr = { 2033 .enable_reg = 0x62008, 2034 .enable_mask = BIT(7), 2035 .hw.init = &(const struct clk_init_data) { 2036 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2037 .ops = &clk_branch2_ops, 2038 }, 2039 }, 2040 }; 2041 2042 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2043 .halt_reg = 0x28004, 2044 .halt_check = BRANCH_HALT_VOTED, 2045 .hwcg_reg = 0x28004, 2046 .hwcg_bit = 1, 2047 .clkr = { 2048 .enable_reg = 0x62008, 2049 .enable_mask = BIT(20), 2050 .hw.init = &(const struct clk_init_data) { 2051 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2052 .ops = &clk_branch2_ops, 2053 }, 2054 }, 2055 }; 2056 2057 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2058 .halt_reg = 0x28008, 2059 .halt_check = BRANCH_HALT_VOTED, 2060 .hwcg_reg = 0x28008, 2061 .hwcg_bit = 1, 2062 .clkr = { 2063 .enable_reg = 0x62008, 2064 .enable_mask = BIT(21), 2065 .hw.init = &(const struct clk_init_data) { 2066 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2067 .ops = &clk_branch2_ops, 2068 }, 2069 }, 2070 }; 2071 2072 static struct clk_branch gcc_sdcc5_ahb_clk = { 2073 .halt_reg = 0x3b00c, 2074 .halt_check = BRANCH_HALT, 2075 .clkr = { 2076 .enable_reg = 0x3b00c, 2077 .enable_mask = BIT(0), 2078 .hw.init = &(const struct clk_init_data) { 2079 .name = "gcc_sdcc5_ahb_clk", 2080 .ops = &clk_branch2_ops, 2081 }, 2082 }, 2083 }; 2084 2085 static struct clk_branch gcc_sdcc5_apps_clk = { 2086 .halt_reg = 0x3b004, 2087 .halt_check = BRANCH_HALT, 2088 .clkr = { 2089 .enable_reg = 0x3b004, 2090 .enable_mask = BIT(0), 2091 .hw.init = &(const struct clk_init_data) { 2092 .name = "gcc_sdcc5_apps_clk", 2093 .parent_hws = (const struct clk_hw*[]) { 2094 &gcc_sdcc5_apps_clk_src.clkr.hw, 2095 }, 2096 .num_parents = 1, 2097 .flags = CLK_SET_RATE_PARENT, 2098 .ops = &clk_branch2_ops, 2099 }, 2100 }, 2101 }; 2102 2103 static struct clk_branch gcc_sdcc5_ice_core_clk = { 2104 .halt_reg = 0x3b010, 2105 .halt_check = BRANCH_HALT, 2106 .clkr = { 2107 .enable_reg = 0x3b010, 2108 .enable_mask = BIT(0), 2109 .hw.init = &(const struct clk_init_data) { 2110 .name = "gcc_sdcc5_ice_core_clk", 2111 .parent_hws = (const struct clk_hw*[]) { 2112 &gcc_sdcc5_ice_core_clk_src.clkr.hw, 2113 }, 2114 .num_parents = 1, 2115 .flags = CLK_SET_RATE_PARENT, 2116 .ops = &clk_branch2_ops, 2117 }, 2118 }, 2119 }; 2120 2121 static struct clk_branch gcc_sm_bus_ahb_clk = { 2122 .halt_reg = 0x5b004, 2123 .halt_check = BRANCH_HALT, 2124 .clkr = { 2125 .enable_reg = 0x5b004, 2126 .enable_mask = BIT(0), 2127 .hw.init = &(const struct clk_init_data) { 2128 .name = "gcc_sm_bus_ahb_clk", 2129 .ops = &clk_branch2_ops, 2130 }, 2131 }, 2132 }; 2133 2134 static struct clk_branch gcc_sm_bus_xo_clk = { 2135 .halt_reg = 0x5b008, 2136 .halt_check = BRANCH_HALT, 2137 .clkr = { 2138 .enable_reg = 0x5b008, 2139 .enable_mask = BIT(0), 2140 .hw.init = &(const struct clk_init_data) { 2141 .name = "gcc_sm_bus_xo_clk", 2142 .parent_hws = (const struct clk_hw*[]) { 2143 &gcc_sm_bus_xo_clk_src.clkr.hw, 2144 }, 2145 .num_parents = 1, 2146 .flags = CLK_SET_RATE_PARENT, 2147 .ops = &clk_branch2_ops, 2148 }, 2149 }, 2150 }; 2151 2152 static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_qx_clk = { 2153 .halt_reg = 0x9200c, 2154 .halt_check = BRANCH_HALT_SKIP, 2155 .hwcg_reg = 0x9200c, 2156 .hwcg_bit = 1, 2157 .clkr = { 2158 .enable_reg = 0x62000, 2159 .enable_mask = BIT(11), 2160 .hw.init = &(const struct clk_init_data) { 2161 .name = "gcc_snoc_cnoc_gemnoc_pcie_qx_clk", 2162 .ops = &clk_branch2_ops, 2163 }, 2164 }, 2165 }; 2166 2167 static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk = { 2168 .halt_reg = 0x92010, 2169 .halt_check = BRANCH_HALT_SKIP, 2170 .hwcg_reg = 0x92010, 2171 .hwcg_bit = 1, 2172 .clkr = { 2173 .enable_reg = 0x62000, 2174 .enable_mask = BIT(12), 2175 .hw.init = &(const struct clk_init_data) { 2176 .name = "gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk", 2177 .ops = &clk_branch2_ops, 2178 }, 2179 }, 2180 }; 2181 2182 static struct clk_branch gcc_snoc_cnoc_pcie_qx_clk = { 2183 .halt_reg = 0x84030, 2184 .halt_check = BRANCH_HALT, 2185 .clkr = { 2186 .enable_reg = 0x84030, 2187 .enable_mask = BIT(0), 2188 .hw.init = &(const struct clk_init_data) { 2189 .name = "gcc_snoc_cnoc_pcie_qx_clk", 2190 .ops = &clk_branch2_ops, 2191 }, 2192 }, 2193 }; 2194 2195 static struct clk_branch gcc_snoc_pcie_sf_center_qx_clk = { 2196 .halt_reg = 0x92014, 2197 .halt_check = BRANCH_HALT_SKIP, 2198 .hwcg_reg = 0x92014, 2199 .hwcg_bit = 1, 2200 .clkr = { 2201 .enable_reg = 0x62000, 2202 .enable_mask = BIT(19), 2203 .hw.init = &(const struct clk_init_data) { 2204 .name = "gcc_snoc_pcie_sf_center_qx_clk", 2205 .ops = &clk_branch2_ops, 2206 }, 2207 }, 2208 }; 2209 2210 static struct clk_branch gcc_snoc_pcie_sf_south_qx_clk = { 2211 .halt_reg = 0x92018, 2212 .halt_check = BRANCH_HALT_SKIP, 2213 .hwcg_reg = 0x92018, 2214 .hwcg_bit = 1, 2215 .clkr = { 2216 .enable_reg = 0x62000, 2217 .enable_mask = BIT(22), 2218 .hw.init = &(const struct clk_init_data) { 2219 .name = "gcc_snoc_pcie_sf_south_qx_clk", 2220 .ops = &clk_branch2_ops, 2221 }, 2222 }, 2223 }; 2224 2225 static struct clk_branch gcc_tsc_cfg_ahb_clk = { 2226 .halt_reg = 0x5700c, 2227 .halt_check = BRANCH_HALT, 2228 .clkr = { 2229 .enable_reg = 0x5700c, 2230 .enable_mask = BIT(0), 2231 .hw.init = &(const struct clk_init_data) { 2232 .name = "gcc_tsc_cfg_ahb_clk", 2233 .ops = &clk_branch2_ops, 2234 }, 2235 }, 2236 }; 2237 2238 static struct clk_branch gcc_tsc_cntr_clk = { 2239 .halt_reg = 0x57004, 2240 .halt_check = BRANCH_HALT, 2241 .clkr = { 2242 .enable_reg = 0x57004, 2243 .enable_mask = BIT(0), 2244 .hw.init = &(const struct clk_init_data) { 2245 .name = "gcc_tsc_cntr_clk", 2246 .parent_hws = (const struct clk_hw*[]) { 2247 &gcc_tsc_clk_src.clkr.hw, 2248 }, 2249 .num_parents = 1, 2250 .flags = CLK_SET_RATE_PARENT, 2251 .ops = &clk_branch2_ops, 2252 }, 2253 }, 2254 }; 2255 2256 static struct clk_branch gcc_tsc_etu_clk = { 2257 .halt_reg = 0x57008, 2258 .halt_check = BRANCH_HALT, 2259 .clkr = { 2260 .enable_reg = 0x57008, 2261 .enable_mask = BIT(0), 2262 .hw.init = &(const struct clk_init_data) { 2263 .name = "gcc_tsc_etu_clk", 2264 .parent_hws = (const struct clk_hw*[]) { 2265 &gcc_tsc_clk_src.clkr.hw, 2266 }, 2267 .num_parents = 1, 2268 .flags = CLK_SET_RATE_PARENT, 2269 .ops = &clk_branch2_ops, 2270 }, 2271 }, 2272 }; 2273 2274 static struct clk_branch gcc_usb2_clkref_en = { 2275 .halt_reg = 0x9c008, 2276 .halt_check = BRANCH_HALT, 2277 .clkr = { 2278 .enable_reg = 0x9c008, 2279 .enable_mask = BIT(0), 2280 .hw.init = &(const struct clk_init_data) { 2281 .name = "gcc_usb2_clkref_en", 2282 .ops = &clk_branch2_ops, 2283 }, 2284 }, 2285 }; 2286 2287 static struct clk_branch gcc_usb30_prim_master_clk = { 2288 .halt_reg = 0x49018, 2289 .halt_check = BRANCH_HALT, 2290 .clkr = { 2291 .enable_reg = 0x49018, 2292 .enable_mask = BIT(0), 2293 .hw.init = &(const struct clk_init_data) { 2294 .name = "gcc_usb30_prim_master_clk", 2295 .parent_hws = (const struct clk_hw*[]) { 2296 &gcc_usb30_prim_master_clk_src.clkr.hw, 2297 }, 2298 .num_parents = 1, 2299 .flags = CLK_SET_RATE_PARENT, 2300 .ops = &clk_branch2_ops, 2301 }, 2302 }, 2303 }; 2304 2305 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2306 .halt_reg = 0x49024, 2307 .halt_check = BRANCH_HALT, 2308 .clkr = { 2309 .enable_reg = 0x49024, 2310 .enable_mask = BIT(0), 2311 .hw.init = &(const struct clk_init_data) { 2312 .name = "gcc_usb30_prim_mock_utmi_clk", 2313 .parent_hws = (const struct clk_hw*[]) { 2314 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2315 }, 2316 .num_parents = 1, 2317 .flags = CLK_SET_RATE_PARENT, 2318 .ops = &clk_branch2_ops, 2319 }, 2320 }, 2321 }; 2322 2323 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2324 .halt_reg = 0x49020, 2325 .halt_check = BRANCH_HALT, 2326 .clkr = { 2327 .enable_reg = 0x49020, 2328 .enable_mask = BIT(0), 2329 .hw.init = &(const struct clk_init_data) { 2330 .name = "gcc_usb30_prim_sleep_clk", 2331 .ops = &clk_branch2_ops, 2332 }, 2333 }, 2334 }; 2335 2336 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2337 .halt_reg = 0x49060, 2338 .halt_check = BRANCH_HALT, 2339 .clkr = { 2340 .enable_reg = 0x49060, 2341 .enable_mask = BIT(0), 2342 .hw.init = &(const struct clk_init_data) { 2343 .name = "gcc_usb3_prim_phy_aux_clk", 2344 .parent_hws = (const struct clk_hw*[]) { 2345 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2346 }, 2347 .num_parents = 1, 2348 .flags = CLK_SET_RATE_PARENT, 2349 .ops = &clk_branch2_ops, 2350 }, 2351 }, 2352 }; 2353 2354 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2355 .halt_reg = 0x49064, 2356 .halt_check = BRANCH_HALT, 2357 .clkr = { 2358 .enable_reg = 0x49064, 2359 .enable_mask = BIT(0), 2360 .hw.init = &(const struct clk_init_data) { 2361 .name = "gcc_usb3_prim_phy_com_aux_clk", 2362 .parent_hws = (const struct clk_hw*[]) { 2363 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2364 }, 2365 .num_parents = 1, 2366 .flags = CLK_SET_RATE_PARENT, 2367 .ops = &clk_branch2_ops, 2368 }, 2369 }, 2370 }; 2371 2372 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2373 .halt_reg = 0x49068, 2374 .halt_check = BRANCH_HALT_DELAY, 2375 .hwcg_reg = 0x49068, 2376 .hwcg_bit = 1, 2377 .clkr = { 2378 .enable_reg = 0x49068, 2379 .enable_mask = BIT(0), 2380 .hw.init = &(const struct clk_init_data) { 2381 .name = "gcc_usb3_prim_phy_pipe_clk", 2382 .parent_hws = (const struct clk_hw*[]) { 2383 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 2384 }, 2385 .num_parents = 1, 2386 .flags = CLK_SET_RATE_PARENT, 2387 .ops = &clk_branch2_ops, 2388 }, 2389 }, 2390 }; 2391 2392 static struct clk_regmap *gcc_qdu1000_clocks[] = { 2393 [GCC_AGGRE_NOC_ECPRI_DMA_CLK] = &gcc_aggre_noc_ecpri_dma_clk.clkr, 2394 [GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC] = &gcc_aggre_noc_ecpri_dma_clk_src.clkr, 2395 [GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC] = &gcc_aggre_noc_ecpri_gsi_clk_src.clkr, 2396 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2397 [GCC_CFG_NOC_ECPRI_CC_AHB_CLK] = &gcc_cfg_noc_ecpri_cc_ahb_clk.clkr, 2398 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2399 [GCC_DDRSS_ECPRI_DMA_CLK] = &gcc_ddrss_ecpri_dma_clk.clkr, 2400 [GCC_ECPRI_AHB_CLK] = &gcc_ecpri_ahb_clk.clkr, 2401 [GCC_ECPRI_CC_GPLL0_CLK_SRC] = &gcc_ecpri_cc_gpll0_clk_src.clkr, 2402 [GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll1_even_clk_src.clkr, 2403 [GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll2_even_clk_src.clkr, 2404 [GCC_ECPRI_CC_GPLL3_CLK_SRC] = &gcc_ecpri_cc_gpll3_clk_src.clkr, 2405 [GCC_ECPRI_CC_GPLL4_CLK_SRC] = &gcc_ecpri_cc_gpll4_clk_src.clkr, 2406 [GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll5_even_clk_src.clkr, 2407 [GCC_ECPRI_XO_CLK] = &gcc_ecpri_xo_clk.clkr, 2408 [GCC_ETH_DBG_SNOC_AXI_CLK] = &gcc_eth_dbg_snoc_axi_clk.clkr, 2409 [GCC_GEMNOC_PCIE_QX_CLK] = &gcc_gemnoc_pcie_qx_clk.clkr, 2410 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2411 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2412 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2413 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2414 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2415 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2416 [GCC_GPLL0] = &gcc_gpll0.clkr, 2417 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 2418 [GCC_GPLL1] = &gcc_gpll1.clkr, 2419 [GCC_GPLL2] = &gcc_gpll2.clkr, 2420 [GCC_GPLL2_OUT_EVEN] = &gcc_gpll2_out_even.clkr, 2421 [GCC_GPLL3] = &gcc_gpll3.clkr, 2422 [GCC_GPLL4] = &gcc_gpll4.clkr, 2423 [GCC_GPLL5] = &gcc_gpll5.clkr, 2424 [GCC_GPLL5_OUT_EVEN] = &gcc_gpll5_out_even.clkr, 2425 [GCC_GPLL6] = &gcc_gpll6.clkr, 2426 [GCC_GPLL7] = &gcc_gpll7.clkr, 2427 [GCC_GPLL8] = &gcc_gpll8.clkr, 2428 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2429 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 2430 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2431 [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr, 2432 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2433 [GCC_PCIE_0_PHY_AUX_CLK] = &gcc_pcie_0_phy_aux_clk.clkr, 2434 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 2435 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 2436 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2437 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2438 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 2439 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2440 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 2441 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2442 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2443 [GCC_QMIP_ANOC_PCIE_CLK] = &gcc_qmip_anoc_pcie_clk.clkr, 2444 [GCC_QMIP_ECPRI_DMA0_CLK] = &gcc_qmip_ecpri_dma0_clk.clkr, 2445 [GCC_QMIP_ECPRI_DMA1_CLK] = &gcc_qmip_ecpri_dma1_clk.clkr, 2446 [GCC_QMIP_ECPRI_GSI_CLK] = &gcc_qmip_ecpri_gsi_clk.clkr, 2447 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 2448 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 2449 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 2450 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 2451 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 2452 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 2453 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 2454 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 2455 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 2456 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 2457 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 2458 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 2459 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 2460 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 2461 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 2462 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 2463 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 2464 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 2465 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 2466 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 2467 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 2468 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 2469 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 2470 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 2471 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 2472 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 2473 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 2474 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 2475 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 2476 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 2477 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 2478 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 2479 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 2480 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 2481 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 2482 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 2483 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 2484 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 2485 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 2486 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 2487 [GCC_SDCC5_AHB_CLK] = &gcc_sdcc5_ahb_clk.clkr, 2488 [GCC_SDCC5_APPS_CLK] = &gcc_sdcc5_apps_clk.clkr, 2489 [GCC_SDCC5_APPS_CLK_SRC] = &gcc_sdcc5_apps_clk_src.clkr, 2490 [GCC_SDCC5_ICE_CORE_CLK] = &gcc_sdcc5_ice_core_clk.clkr, 2491 [GCC_SDCC5_ICE_CORE_CLK_SRC] = &gcc_sdcc5_ice_core_clk_src.clkr, 2492 [GCC_SM_BUS_AHB_CLK] = &gcc_sm_bus_ahb_clk.clkr, 2493 [GCC_SM_BUS_XO_CLK] = &gcc_sm_bus_xo_clk.clkr, 2494 [GCC_SM_BUS_XO_CLK_SRC] = &gcc_sm_bus_xo_clk_src.clkr, 2495 [GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK] = &gcc_snoc_cnoc_gemnoc_pcie_qx_clk.clkr, 2496 [GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK] = &gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk.clkr, 2497 [GCC_SNOC_CNOC_PCIE_QX_CLK] = &gcc_snoc_cnoc_pcie_qx_clk.clkr, 2498 [GCC_SNOC_PCIE_SF_CENTER_QX_CLK] = &gcc_snoc_pcie_sf_center_qx_clk.clkr, 2499 [GCC_SNOC_PCIE_SF_SOUTH_QX_CLK] = &gcc_snoc_pcie_sf_south_qx_clk.clkr, 2500 [GCC_TSC_CFG_AHB_CLK] = &gcc_tsc_cfg_ahb_clk.clkr, 2501 [GCC_TSC_CLK_SRC] = &gcc_tsc_clk_src.clkr, 2502 [GCC_TSC_CNTR_CLK] = &gcc_tsc_cntr_clk.clkr, 2503 [GCC_TSC_ETU_CLK] = &gcc_tsc_etu_clk.clkr, 2504 [GCC_USB2_CLKREF_EN] = &gcc_usb2_clkref_en.clkr, 2505 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 2506 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 2507 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 2508 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 2509 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 2510 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 2511 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 2512 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 2513 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 2514 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 2515 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 2516 [GCC_ETH_100G_C2C_HM_APB_CLK] = &gcc_eth_100g_c2c_hm_apb_clk.clkr, 2517 [GCC_ETH_100G_FH_HM_APB_0_CLK] = &gcc_eth_100g_fh_hm_apb_0_clk.clkr, 2518 [GCC_ETH_100G_FH_HM_APB_1_CLK] = &gcc_eth_100g_fh_hm_apb_1_clk.clkr, 2519 [GCC_ETH_100G_FH_HM_APB_2_CLK] = &gcc_eth_100g_fh_hm_apb_2_clk.clkr, 2520 [GCC_ETH_DBG_C2C_HM_APB_CLK] = &gcc_eth_dbg_c2c_hm_apb_clk.clkr, 2521 [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr, 2522 [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, 2523 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 2524 [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr, 2525 }; 2526 2527 static const struct qcom_reset_map gcc_qdu1000_resets[] = { 2528 [GCC_ECPRI_CC_BCR] = { 0x3e000 }, 2529 [GCC_ECPRI_SS_BCR] = { 0x3a000 }, 2530 [GCC_ETH_WRAPPER_BCR] = { 0x39000 }, 2531 [GCC_PCIE_0_BCR] = { 0x9d000 }, 2532 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x9e014 }, 2533 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x9e020 }, 2534 [GCC_PCIE_0_PHY_BCR] = { 0x7c000 }, 2535 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 }, 2536 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c }, 2537 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 }, 2538 [GCC_PDM_BCR] = { 0x43000 }, 2539 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 }, 2540 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 }, 2541 [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 }, 2542 [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 }, 2543 [GCC_SDCC5_BCR] = { 0x3b000 }, 2544 [GCC_TSC_BCR] = { 0x57000 }, 2545 [GCC_USB30_PRIM_BCR] = { 0x49000 }, 2546 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 }, 2547 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 }, 2548 [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 }, 2549 [GCC_USB3_PHY_SEC_BCR] = { 0x6000c }, 2550 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 }, 2551 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 }, 2552 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 }, 2553 }; 2554 2555 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 2556 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 2557 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 2558 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 2559 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 2560 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 2561 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 2562 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 2563 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 2564 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 2565 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 2566 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 2567 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 2568 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 2569 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 2570 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 2571 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 2572 }; 2573 2574 static const struct regmap_config gcc_qdu1000_regmap_config = { 2575 .reg_bits = 32, 2576 .reg_stride = 4, 2577 .val_bits = 32, 2578 .max_register = 0x1f41f0, 2579 .fast_io = true, 2580 }; 2581 2582 static const struct qcom_cc_desc gcc_qdu1000_desc = { 2583 .config = &gcc_qdu1000_regmap_config, 2584 .clks = gcc_qdu1000_clocks, 2585 .num_clks = ARRAY_SIZE(gcc_qdu1000_clocks), 2586 .resets = gcc_qdu1000_resets, 2587 .num_resets = ARRAY_SIZE(gcc_qdu1000_resets), 2588 }; 2589 2590 static const struct of_device_id gcc_qdu1000_match_table[] = { 2591 { .compatible = "qcom,qdu1000-gcc" }, 2592 { } 2593 }; 2594 MODULE_DEVICE_TABLE(of, gcc_qdu1000_match_table); 2595 2596 static int gcc_qdu1000_probe(struct platform_device *pdev) 2597 { 2598 struct regmap *regmap; 2599 int ret; 2600 2601 regmap = qcom_cc_map(pdev, &gcc_qdu1000_desc); 2602 if (IS_ERR(regmap)) 2603 return PTR_ERR(regmap); 2604 2605 /* Update FORCE_MEM_CORE_ON for gcc_pcie_0_mstr_axi_clk */ 2606 regmap_update_bits(regmap, 0x9d024, BIT(14), BIT(14)); 2607 2608 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 2609 ARRAY_SIZE(gcc_dfs_clocks)); 2610 if (ret) 2611 return ret; 2612 2613 ret = qcom_cc_really_probe(pdev, &gcc_qdu1000_desc, regmap); 2614 if (ret) 2615 return dev_err_probe(&pdev->dev, ret, "Failed to register GCC clocks\n"); 2616 2617 return ret; 2618 } 2619 2620 static struct platform_driver gcc_qdu1000_driver = { 2621 .probe = gcc_qdu1000_probe, 2622 .driver = { 2623 .name = "gcc-qdu1000", 2624 .of_match_table = gcc_qdu1000_match_table, 2625 }, 2626 }; 2627 2628 static int __init gcc_qdu1000_init(void) 2629 { 2630 return platform_driver_register(&gcc_qdu1000_driver); 2631 } 2632 subsys_initcall(gcc_qdu1000_init); 2633 2634 static void __exit gcc_qdu1000_exit(void) 2635 { 2636 platform_driver_unregister(&gcc_qdu1000_driver); 2637 } 2638 module_exit(gcc_qdu1000_exit); 2639 2640 MODULE_DESCRIPTION("QTI GCC QDU1000 Driver"); 2641 MODULE_LICENSE("GPL"); 2642