11c9efb0bSTaniya Das // SPDX-License-Identifier: GPL-2.0-only 21c9efb0bSTaniya Das /* 3*b311f5d3SImran Shaik * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 41c9efb0bSTaniya Das */ 51c9efb0bSTaniya Das 61c9efb0bSTaniya Das #include <linux/clk-provider.h> 71c9efb0bSTaniya Das #include <linux/module.h> 81c9efb0bSTaniya Das #include <linux/of_device.h> 91c9efb0bSTaniya Das #include <linux/regmap.h> 101c9efb0bSTaniya Das 111c9efb0bSTaniya Das #include <dt-bindings/clock/qcom,qdu1000-gcc.h> 121c9efb0bSTaniya Das 131c9efb0bSTaniya Das #include "clk-alpha-pll.h" 141c9efb0bSTaniya Das #include "clk-branch.h" 151c9efb0bSTaniya Das #include "clk-rcg.h" 161c9efb0bSTaniya Das #include "clk-regmap.h" 171c9efb0bSTaniya Das #include "clk-regmap-divider.h" 181c9efb0bSTaniya Das #include "clk-regmap-mux.h" 191c9efb0bSTaniya Das #include "clk-regmap-phy-mux.h" 201c9efb0bSTaniya Das #include "reset.h" 211c9efb0bSTaniya Das 221c9efb0bSTaniya Das enum { 231c9efb0bSTaniya Das P_BI_TCXO, 241c9efb0bSTaniya Das P_GCC_GPLL0_OUT_EVEN, 251c9efb0bSTaniya Das P_GCC_GPLL0_OUT_MAIN, 261c9efb0bSTaniya Das P_GCC_GPLL1_OUT_MAIN, 271c9efb0bSTaniya Das P_GCC_GPLL2_OUT_MAIN, 281c9efb0bSTaniya Das P_GCC_GPLL3_OUT_MAIN, 291c9efb0bSTaniya Das P_GCC_GPLL4_OUT_MAIN, 301c9efb0bSTaniya Das P_GCC_GPLL5_OUT_MAIN, 311c9efb0bSTaniya Das P_GCC_GPLL6_OUT_MAIN, 321c9efb0bSTaniya Das P_GCC_GPLL7_OUT_MAIN, 331c9efb0bSTaniya Das P_GCC_GPLL8_OUT_MAIN, 341c9efb0bSTaniya Das P_PCIE_0_PHY_AUX_CLK, 351c9efb0bSTaniya Das P_PCIE_0_PIPE_CLK, 361c9efb0bSTaniya Das P_SLEEP_CLK, 371c9efb0bSTaniya Das P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 381c9efb0bSTaniya Das }; 391c9efb0bSTaniya Das 401c9efb0bSTaniya Das enum { 411c9efb0bSTaniya Das DT_TCXO_IDX, 421c9efb0bSTaniya Das DT_SLEEP_CLK_IDX, 431c9efb0bSTaniya Das DT_PCIE_0_PIPE_CLK_IDX, 441c9efb0bSTaniya Das DT_PCIE_0_PHY_AUX_CLK_IDX, 451c9efb0bSTaniya Das DT_USB3_PHY_WRAPPER_PIPE_CLK_IDX, 461c9efb0bSTaniya Das }; 471c9efb0bSTaniya Das 481c9efb0bSTaniya Das static struct clk_alpha_pll gcc_gpll0 = { 491c9efb0bSTaniya Das .offset = 0x0, 501c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 511c9efb0bSTaniya Das .clkr = { 521c9efb0bSTaniya Das .enable_reg = 0x62018, 531c9efb0bSTaniya Das .enable_mask = BIT(0), 541c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 551c9efb0bSTaniya Das .name = "gcc_gpll0", 561c9efb0bSTaniya Das .parent_data = &(const struct clk_parent_data) { 571c9efb0bSTaniya Das .index = DT_TCXO_IDX, 581c9efb0bSTaniya Das }, 591c9efb0bSTaniya Das .num_parents = 1, 601c9efb0bSTaniya Das .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 611c9efb0bSTaniya Das }, 621c9efb0bSTaniya Das }, 631c9efb0bSTaniya Das }; 641c9efb0bSTaniya Das 651c9efb0bSTaniya Das static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 661c9efb0bSTaniya Das { 0x1, 2 } 671c9efb0bSTaniya Das }; 681c9efb0bSTaniya Das 691c9efb0bSTaniya Das static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 701c9efb0bSTaniya Das .offset = 0x0, 711c9efb0bSTaniya Das .post_div_shift = 10, 721c9efb0bSTaniya Das .post_div_table = post_div_table_gcc_gpll0_out_even, 731c9efb0bSTaniya Das .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 741c9efb0bSTaniya Das .width = 4, 751c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 761c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 771c9efb0bSTaniya Das .name = "gcc_gpll0_out_even", 781c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 791c9efb0bSTaniya Das &gcc_gpll0.clkr.hw, 801c9efb0bSTaniya Das }, 811c9efb0bSTaniya Das .num_parents = 1, 821c9efb0bSTaniya Das .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 831c9efb0bSTaniya Das }, 841c9efb0bSTaniya Das }; 851c9efb0bSTaniya Das 861c9efb0bSTaniya Das static struct clk_alpha_pll gcc_gpll1 = { 871c9efb0bSTaniya Das .offset = 0x1000, 881c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 891c9efb0bSTaniya Das .clkr = { 901c9efb0bSTaniya Das .enable_reg = 0x62018, 911c9efb0bSTaniya Das .enable_mask = BIT(1), 921c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 931c9efb0bSTaniya Das .name = "gcc_gpll1", 941c9efb0bSTaniya Das .parent_data = &(const struct clk_parent_data) { 951c9efb0bSTaniya Das .index = DT_TCXO_IDX, 961c9efb0bSTaniya Das }, 971c9efb0bSTaniya Das .num_parents = 1, 981c9efb0bSTaniya Das .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 991c9efb0bSTaniya Das }, 1001c9efb0bSTaniya Das }, 1011c9efb0bSTaniya Das }; 1021c9efb0bSTaniya Das 1031c9efb0bSTaniya Das static struct clk_alpha_pll_postdiv gcc_gpll1_out_even = { 1041c9efb0bSTaniya Das .offset = 0x1000, 1051c9efb0bSTaniya Das .post_div_shift = 10, 1061c9efb0bSTaniya Das .post_div_table = post_div_table_gcc_gpll0_out_even, 1071c9efb0bSTaniya Das .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 1081c9efb0bSTaniya Das .width = 4, 1091c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 1101c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 1111c9efb0bSTaniya Das .name = "gcc_gpll1_out_even", 1121c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1131c9efb0bSTaniya Das &gcc_gpll1.clkr.hw, 1141c9efb0bSTaniya Das }, 1151c9efb0bSTaniya Das .num_parents = 1, 1161c9efb0bSTaniya Das .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 1171c9efb0bSTaniya Das }, 1181c9efb0bSTaniya Das }; 1191c9efb0bSTaniya Das 1201c9efb0bSTaniya Das static struct clk_alpha_pll gcc_gpll2 = { 1211c9efb0bSTaniya Das .offset = 0x2000, 1221c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 1231c9efb0bSTaniya Das .clkr = { 1241c9efb0bSTaniya Das .enable_reg = 0x62018, 1251c9efb0bSTaniya Das .enable_mask = BIT(2), 1261c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1271c9efb0bSTaniya Das .name = "gcc_gpll2", 1281c9efb0bSTaniya Das .parent_data = &(const struct clk_parent_data) { 1291c9efb0bSTaniya Das .index = DT_TCXO_IDX, 1301c9efb0bSTaniya Das }, 1311c9efb0bSTaniya Das .num_parents = 1, 1321c9efb0bSTaniya Das .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 1331c9efb0bSTaniya Das }, 1341c9efb0bSTaniya Das }, 1351c9efb0bSTaniya Das }; 1361c9efb0bSTaniya Das 1371c9efb0bSTaniya Das static struct clk_alpha_pll_postdiv gcc_gpll2_out_even = { 1381c9efb0bSTaniya Das .offset = 0x2000, 1391c9efb0bSTaniya Das .post_div_shift = 10, 1401c9efb0bSTaniya Das .post_div_table = post_div_table_gcc_gpll0_out_even, 1411c9efb0bSTaniya Das .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 1421c9efb0bSTaniya Das .width = 4, 1431c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 1441c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 1451c9efb0bSTaniya Das .name = "gcc_gpll2_out_even", 1461c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1471c9efb0bSTaniya Das &gcc_gpll2.clkr.hw, 1481c9efb0bSTaniya Das }, 1491c9efb0bSTaniya Das .num_parents = 1, 1501c9efb0bSTaniya Das .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 1511c9efb0bSTaniya Das }, 1521c9efb0bSTaniya Das }; 1531c9efb0bSTaniya Das 1541c9efb0bSTaniya Das static struct clk_alpha_pll gcc_gpll3 = { 1551c9efb0bSTaniya Das .offset = 0x3000, 1561c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 1571c9efb0bSTaniya Das .clkr = { 1581c9efb0bSTaniya Das .enable_reg = 0x62018, 1591c9efb0bSTaniya Das .enable_mask = BIT(3), 1601c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1611c9efb0bSTaniya Das .name = "gcc_gpll3", 1621c9efb0bSTaniya Das .parent_data = &(const struct clk_parent_data) { 1631c9efb0bSTaniya Das .index = DT_TCXO_IDX, 1641c9efb0bSTaniya Das }, 1651c9efb0bSTaniya Das .num_parents = 1, 1661c9efb0bSTaniya Das .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 1671c9efb0bSTaniya Das }, 1681c9efb0bSTaniya Das }, 1691c9efb0bSTaniya Das }; 1701c9efb0bSTaniya Das 1711c9efb0bSTaniya Das static struct clk_alpha_pll gcc_gpll4 = { 1721c9efb0bSTaniya Das .offset = 0x4000, 1731c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 1741c9efb0bSTaniya Das .clkr = { 1751c9efb0bSTaniya Das .enable_reg = 0x62018, 1761c9efb0bSTaniya Das .enable_mask = BIT(4), 1771c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1781c9efb0bSTaniya Das .name = "gcc_gpll4", 1791c9efb0bSTaniya Das .parent_data = &(const struct clk_parent_data) { 1801c9efb0bSTaniya Das .index = DT_TCXO_IDX, 1811c9efb0bSTaniya Das }, 1821c9efb0bSTaniya Das .num_parents = 1, 1831c9efb0bSTaniya Das .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 1841c9efb0bSTaniya Das }, 1851c9efb0bSTaniya Das }, 1861c9efb0bSTaniya Das }; 1871c9efb0bSTaniya Das 1881c9efb0bSTaniya Das static struct clk_alpha_pll gcc_gpll5 = { 1891c9efb0bSTaniya Das .offset = 0x5000, 1901c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 1911c9efb0bSTaniya Das .clkr = { 1921c9efb0bSTaniya Das .enable_reg = 0x62018, 1931c9efb0bSTaniya Das .enable_mask = BIT(5), 1941c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1951c9efb0bSTaniya Das .name = "gcc_gpll5", 1961c9efb0bSTaniya Das .parent_data = &(const struct clk_parent_data) { 1971c9efb0bSTaniya Das .index = DT_TCXO_IDX, 1981c9efb0bSTaniya Das }, 1991c9efb0bSTaniya Das .num_parents = 1, 2001c9efb0bSTaniya Das .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 2011c9efb0bSTaniya Das }, 2021c9efb0bSTaniya Das }, 2031c9efb0bSTaniya Das }; 2041c9efb0bSTaniya Das 2051c9efb0bSTaniya Das static struct clk_alpha_pll_postdiv gcc_gpll5_out_even = { 2061c9efb0bSTaniya Das .offset = 0x5000, 2071c9efb0bSTaniya Das .post_div_shift = 10, 2081c9efb0bSTaniya Das .post_div_table = post_div_table_gcc_gpll0_out_even, 2091c9efb0bSTaniya Das .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 2101c9efb0bSTaniya Das .width = 4, 2111c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 2121c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 2131c9efb0bSTaniya Das .name = "gcc_gpll5_out_even", 2141c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 2151c9efb0bSTaniya Das &gcc_gpll5.clkr.hw, 2161c9efb0bSTaniya Das }, 2171c9efb0bSTaniya Das .num_parents = 1, 2181c9efb0bSTaniya Das .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 2191c9efb0bSTaniya Das }, 2201c9efb0bSTaniya Das }; 2211c9efb0bSTaniya Das 2221c9efb0bSTaniya Das static struct clk_alpha_pll gcc_gpll6 = { 2231c9efb0bSTaniya Das .offset = 0x6000, 2241c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 2251c9efb0bSTaniya Das .clkr = { 2261c9efb0bSTaniya Das .enable_reg = 0x62018, 2271c9efb0bSTaniya Das .enable_mask = BIT(6), 2281c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2291c9efb0bSTaniya Das .name = "gcc_gpll6", 2301c9efb0bSTaniya Das .parent_data = &(const struct clk_parent_data) { 2311c9efb0bSTaniya Das .index = DT_TCXO_IDX, 2321c9efb0bSTaniya Das }, 2331c9efb0bSTaniya Das .num_parents = 1, 2341c9efb0bSTaniya Das .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 2351c9efb0bSTaniya Das }, 2361c9efb0bSTaniya Das }, 2371c9efb0bSTaniya Das }; 2381c9efb0bSTaniya Das 2391c9efb0bSTaniya Das static struct clk_alpha_pll gcc_gpll7 = { 2401c9efb0bSTaniya Das .offset = 0x7000, 2411c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 2421c9efb0bSTaniya Das .clkr = { 2431c9efb0bSTaniya Das .enable_reg = 0x62018, 2441c9efb0bSTaniya Das .enable_mask = BIT(7), 2451c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2461c9efb0bSTaniya Das .name = "gcc_gpll7", 2471c9efb0bSTaniya Das .parent_data = &(const struct clk_parent_data) { 2481c9efb0bSTaniya Das .index = DT_TCXO_IDX, 2491c9efb0bSTaniya Das }, 2501c9efb0bSTaniya Das .num_parents = 1, 2511c9efb0bSTaniya Das .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 2521c9efb0bSTaniya Das }, 2531c9efb0bSTaniya Das }, 2541c9efb0bSTaniya Das }; 2551c9efb0bSTaniya Das 2561c9efb0bSTaniya Das static struct clk_alpha_pll gcc_gpll8 = { 2571c9efb0bSTaniya Das .offset = 0x8000, 2581c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 2591c9efb0bSTaniya Das .clkr = { 2601c9efb0bSTaniya Das .enable_reg = 0x62018, 2611c9efb0bSTaniya Das .enable_mask = BIT(8), 2621c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2631c9efb0bSTaniya Das .name = "gcc_gpll8", 2641c9efb0bSTaniya Das .parent_data = &(const struct clk_parent_data) { 2651c9efb0bSTaniya Das .index = DT_TCXO_IDX, 2661c9efb0bSTaniya Das }, 2671c9efb0bSTaniya Das .num_parents = 1, 2681c9efb0bSTaniya Das .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 2691c9efb0bSTaniya Das }, 2701c9efb0bSTaniya Das }, 2711c9efb0bSTaniya Das }; 2721c9efb0bSTaniya Das 2731c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_0[] = { 2741c9efb0bSTaniya Das { P_BI_TCXO, 0 }, 2751c9efb0bSTaniya Das { P_GCC_GPLL0_OUT_MAIN, 1 }, 2761c9efb0bSTaniya Das { P_GCC_GPLL0_OUT_EVEN, 6 }, 2771c9efb0bSTaniya Das }; 2781c9efb0bSTaniya Das 2791c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_0[] = { 2801c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 2811c9efb0bSTaniya Das { .hw = &gcc_gpll0.clkr.hw }, 2821c9efb0bSTaniya Das { .hw = &gcc_gpll0_out_even.clkr.hw }, 2831c9efb0bSTaniya Das }; 2841c9efb0bSTaniya Das 2851c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_1[] = { 2861c9efb0bSTaniya Das { P_BI_TCXO, 0 }, 2871c9efb0bSTaniya Das { P_GCC_GPLL0_OUT_MAIN, 1 }, 2881c9efb0bSTaniya Das { P_SLEEP_CLK, 5 }, 2891c9efb0bSTaniya Das { P_GCC_GPLL0_OUT_EVEN, 6 }, 2901c9efb0bSTaniya Das }; 2911c9efb0bSTaniya Das 2921c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_1[] = { 2931c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 2941c9efb0bSTaniya Das { .hw = &gcc_gpll0.clkr.hw }, 2951c9efb0bSTaniya Das { .index = DT_SLEEP_CLK_IDX }, 2961c9efb0bSTaniya Das { .hw = &gcc_gpll0_out_even.clkr.hw }, 2971c9efb0bSTaniya Das }; 2981c9efb0bSTaniya Das 2991c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_2[] = { 3001c9efb0bSTaniya Das { P_BI_TCXO, 0 }, 3011c9efb0bSTaniya Das { P_GCC_GPLL0_OUT_MAIN, 1 }, 3021c9efb0bSTaniya Das { P_GCC_GPLL5_OUT_MAIN, 3 }, 3031c9efb0bSTaniya Das { P_GCC_GPLL4_OUT_MAIN, 5 }, 3041c9efb0bSTaniya Das }; 3051c9efb0bSTaniya Das 3061c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_2[] = { 3071c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 3081c9efb0bSTaniya Das { .hw = &gcc_gpll0.clkr.hw }, 3091c9efb0bSTaniya Das { .hw = &gcc_gpll5.clkr.hw }, 3101c9efb0bSTaniya Das { .hw = &gcc_gpll4.clkr.hw }, 3111c9efb0bSTaniya Das }; 3121c9efb0bSTaniya Das 3131c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_3[] = { 3141c9efb0bSTaniya Das { P_BI_TCXO, 0 }, 3151c9efb0bSTaniya Das { P_SLEEP_CLK, 5 }, 3161c9efb0bSTaniya Das }; 3171c9efb0bSTaniya Das 3181c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_3[] = { 3191c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 3201c9efb0bSTaniya Das { .index = DT_SLEEP_CLK_IDX }, 3211c9efb0bSTaniya Das }; 3221c9efb0bSTaniya Das 3231c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_4[] = { 3241c9efb0bSTaniya Das { P_BI_TCXO, 0 }, 3251c9efb0bSTaniya Das { P_GCC_GPLL0_OUT_MAIN, 1 }, 3261c9efb0bSTaniya Das { P_GCC_GPLL2_OUT_MAIN, 2 }, 3271c9efb0bSTaniya Das { P_GCC_GPLL5_OUT_MAIN, 3 }, 3281c9efb0bSTaniya Das { P_GCC_GPLL1_OUT_MAIN, 4 }, 3291c9efb0bSTaniya Das { P_GCC_GPLL4_OUT_MAIN, 5 }, 3301c9efb0bSTaniya Das { P_GCC_GPLL3_OUT_MAIN, 6 }, 3311c9efb0bSTaniya Das }; 3321c9efb0bSTaniya Das 3331c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_4[] = { 3341c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 3351c9efb0bSTaniya Das { .hw = &gcc_gpll0.clkr.hw }, 3361c9efb0bSTaniya Das { .hw = &gcc_gpll2.clkr.hw }, 3371c9efb0bSTaniya Das { .hw = &gcc_gpll5.clkr.hw }, 3381c9efb0bSTaniya Das { .hw = &gcc_gpll1.clkr.hw }, 3391c9efb0bSTaniya Das { .hw = &gcc_gpll4.clkr.hw }, 3401c9efb0bSTaniya Das { .hw = &gcc_gpll3.clkr.hw }, 3411c9efb0bSTaniya Das }; 3421c9efb0bSTaniya Das 3431c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_5[] = { 3441c9efb0bSTaniya Das { P_BI_TCXO, 0 }, 3451c9efb0bSTaniya Das { P_GCC_GPLL0_OUT_MAIN, 1 }, 3461c9efb0bSTaniya Das { P_GCC_GPLL2_OUT_MAIN, 2 }, 3471c9efb0bSTaniya Das { P_GCC_GPLL6_OUT_MAIN, 3 }, 3481c9efb0bSTaniya Das { P_GCC_GPLL1_OUT_MAIN, 4 }, 3491c9efb0bSTaniya Das { P_GCC_GPLL4_OUT_MAIN, 5 }, 3501c9efb0bSTaniya Das { P_GCC_GPLL3_OUT_MAIN, 6 }, 3511c9efb0bSTaniya Das }; 3521c9efb0bSTaniya Das 3531c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_5[] = { 3541c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 3551c9efb0bSTaniya Das { .hw = &gcc_gpll0.clkr.hw }, 3561c9efb0bSTaniya Das { .hw = &gcc_gpll2.clkr.hw }, 3571c9efb0bSTaniya Das { .hw = &gcc_gpll6.clkr.hw }, 3581c9efb0bSTaniya Das { .hw = &gcc_gpll1.clkr.hw }, 3591c9efb0bSTaniya Das { .hw = &gcc_gpll4.clkr.hw }, 3601c9efb0bSTaniya Das { .hw = &gcc_gpll3.clkr.hw }, 3611c9efb0bSTaniya Das }; 3621c9efb0bSTaniya Das 3631c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_6[] = { 3641c9efb0bSTaniya Das { P_PCIE_0_PHY_AUX_CLK, 0 }, 3651c9efb0bSTaniya Das { P_BI_TCXO, 2 }, 3661c9efb0bSTaniya Das }; 3671c9efb0bSTaniya Das 3681c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_6[] = { 3691c9efb0bSTaniya Das { .index = DT_PCIE_0_PHY_AUX_CLK_IDX }, 3701c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 3711c9efb0bSTaniya Das }; 3721c9efb0bSTaniya Das 3731c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_8[] = { 3741c9efb0bSTaniya Das { P_BI_TCXO, 0 }, 3751c9efb0bSTaniya Das { P_GCC_GPLL0_OUT_MAIN, 1 }, 3761c9efb0bSTaniya Das { P_GCC_GPLL8_OUT_MAIN, 2 }, 3771c9efb0bSTaniya Das { P_GCC_GPLL5_OUT_MAIN, 3 }, 3781c9efb0bSTaniya Das { P_GCC_GPLL4_OUT_MAIN, 5 }, 3791c9efb0bSTaniya Das }; 3801c9efb0bSTaniya Das 3811c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_8[] = { 3821c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 3831c9efb0bSTaniya Das { .hw = &gcc_gpll0.clkr.hw }, 3841c9efb0bSTaniya Das { .hw = &gcc_gpll8.clkr.hw }, 3851c9efb0bSTaniya Das { .hw = &gcc_gpll5.clkr.hw }, 3861c9efb0bSTaniya Das { .hw = &gcc_gpll4.clkr.hw }, 3871c9efb0bSTaniya Das }; 3881c9efb0bSTaniya Das 3891c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_9[] = { 3901c9efb0bSTaniya Das { P_BI_TCXO, 0 }, 3911c9efb0bSTaniya Das { P_GCC_GPLL0_OUT_MAIN, 1 }, 3921c9efb0bSTaniya Das { P_GCC_GPLL2_OUT_MAIN, 2 }, 3931c9efb0bSTaniya Das { P_GCC_GPLL5_OUT_MAIN, 3 }, 3941c9efb0bSTaniya Das { P_GCC_GPLL7_OUT_MAIN, 4 }, 3951c9efb0bSTaniya Das { P_GCC_GPLL4_OUT_MAIN, 5 }, 3961c9efb0bSTaniya Das }; 3971c9efb0bSTaniya Das 3981c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_9[] = { 3991c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 4001c9efb0bSTaniya Das { .hw = &gcc_gpll0.clkr.hw }, 4011c9efb0bSTaniya Das { .hw = &gcc_gpll2.clkr.hw }, 4021c9efb0bSTaniya Das { .hw = &gcc_gpll5.clkr.hw }, 4031c9efb0bSTaniya Das { .hw = &gcc_gpll7.clkr.hw }, 4041c9efb0bSTaniya Das { .hw = &gcc_gpll4.clkr.hw }, 4051c9efb0bSTaniya Das }; 4061c9efb0bSTaniya Das 4071c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_10[] = { 4081c9efb0bSTaniya Das { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 4091c9efb0bSTaniya Das { P_BI_TCXO, 2 }, 4101c9efb0bSTaniya Das }; 4111c9efb0bSTaniya Das 4121c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_10[] = { 4131c9efb0bSTaniya Das { .index = DT_USB3_PHY_WRAPPER_PIPE_CLK_IDX }, 4141c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 4151c9efb0bSTaniya Das }; 4161c9efb0bSTaniya Das 4171c9efb0bSTaniya Das static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = { 4181c9efb0bSTaniya Das .reg = 0x9d080, 4191c9efb0bSTaniya Das .shift = 0, 4201c9efb0bSTaniya Das .width = 2, 4211c9efb0bSTaniya Das .parent_map = gcc_parent_map_6, 4221c9efb0bSTaniya Das .clkr = { 4231c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 4241c9efb0bSTaniya Das .name = "gcc_pcie_0_phy_aux_clk_src", 4251c9efb0bSTaniya Das .parent_data = gcc_parent_data_6, 4261c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_6), 4271c9efb0bSTaniya Das .ops = &clk_regmap_mux_closest_ops, 4281c9efb0bSTaniya Das }, 4291c9efb0bSTaniya Das }, 4301c9efb0bSTaniya Das }; 4311c9efb0bSTaniya Das 432*b311f5d3SImran Shaik static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { 4331c9efb0bSTaniya Das .reg = 0x9d064, 4341c9efb0bSTaniya Das .clkr = { 4351c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 4361c9efb0bSTaniya Das .name = "gcc_pcie_0_pipe_clk_src", 437*b311f5d3SImran Shaik .parent_data = &(const struct clk_parent_data){ 438*b311f5d3SImran Shaik .index = DT_PCIE_0_PIPE_CLK_IDX, 439*b311f5d3SImran Shaik }, 440*b311f5d3SImran Shaik .num_parents = 1, 4411c9efb0bSTaniya Das .ops = &clk_regmap_phy_mux_ops, 4421c9efb0bSTaniya Das }, 4431c9efb0bSTaniya Das }, 4441c9efb0bSTaniya Das }; 4451c9efb0bSTaniya Das 4461c9efb0bSTaniya Das static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 4471c9efb0bSTaniya Das .reg = 0x4906c, 4481c9efb0bSTaniya Das .shift = 0, 4491c9efb0bSTaniya Das .width = 2, 4501c9efb0bSTaniya Das .parent_map = gcc_parent_map_10, 4511c9efb0bSTaniya Das .clkr = { 4521c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 4531c9efb0bSTaniya Das .name = "gcc_usb3_prim_phy_pipe_clk_src", 4541c9efb0bSTaniya Das .parent_data = gcc_parent_data_10, 4551c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_10), 4561c9efb0bSTaniya Das .ops = &clk_regmap_mux_closest_ops, 4571c9efb0bSTaniya Das }, 4581c9efb0bSTaniya Das }, 4591c9efb0bSTaniya Das }; 4601c9efb0bSTaniya Das 4611c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_dma_clk_src[] = { 4621c9efb0bSTaniya Das F(466500000, P_GCC_GPLL5_OUT_MAIN, 2, 0, 0), 4631c9efb0bSTaniya Das F(500000000, P_GCC_GPLL2_OUT_MAIN, 2, 0, 0), 4641c9efb0bSTaniya Das { } 4651c9efb0bSTaniya Das }; 4661c9efb0bSTaniya Das 4671c9efb0bSTaniya Das static struct clk_rcg2 gcc_aggre_noc_ecpri_dma_clk_src = { 4681c9efb0bSTaniya Das .cmd_rcgr = 0x92020, 4691c9efb0bSTaniya Das .mnd_width = 0, 4701c9efb0bSTaniya Das .hid_width = 5, 4711c9efb0bSTaniya Das .parent_map = gcc_parent_map_4, 4721c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_aggre_noc_ecpri_dma_clk_src, 4731c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 4741c9efb0bSTaniya Das .name = "gcc_aggre_noc_ecpri_dma_clk_src", 4751c9efb0bSTaniya Das .parent_data = gcc_parent_data_4, 4761c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_4), 4771c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 4781c9efb0bSTaniya Das }, 4791c9efb0bSTaniya Das }; 4801c9efb0bSTaniya Das 4811c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_gsi_clk_src[] = { 4821c9efb0bSTaniya Das F(250000000, P_GCC_GPLL2_OUT_MAIN, 4, 0, 0), 4831c9efb0bSTaniya Das F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 4841c9efb0bSTaniya Das { } 4851c9efb0bSTaniya Das }; 4861c9efb0bSTaniya Das 4871c9efb0bSTaniya Das static struct clk_rcg2 gcc_aggre_noc_ecpri_gsi_clk_src = { 4881c9efb0bSTaniya Das .cmd_rcgr = 0x92038, 4891c9efb0bSTaniya Das .mnd_width = 0, 4901c9efb0bSTaniya Das .hid_width = 5, 4911c9efb0bSTaniya Das .parent_map = gcc_parent_map_5, 4921c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_aggre_noc_ecpri_gsi_clk_src, 4931c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 4941c9efb0bSTaniya Das .name = "gcc_aggre_noc_ecpri_gsi_clk_src", 4951c9efb0bSTaniya Das .parent_data = gcc_parent_data_5, 4961c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_5), 4971c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 4981c9efb0bSTaniya Das }, 4991c9efb0bSTaniya Das }; 5001c9efb0bSTaniya Das 5011c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 5021c9efb0bSTaniya Das F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 5031c9efb0bSTaniya Das { } 5041c9efb0bSTaniya Das }; 5051c9efb0bSTaniya Das 5061c9efb0bSTaniya Das static struct clk_rcg2 gcc_gp1_clk_src = { 5071c9efb0bSTaniya Das .cmd_rcgr = 0x74004, 5081c9efb0bSTaniya Das .mnd_width = 16, 5091c9efb0bSTaniya Das .hid_width = 5, 5101c9efb0bSTaniya Das .parent_map = gcc_parent_map_1, 5111c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_gp1_clk_src, 5121c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 5131c9efb0bSTaniya Das .name = "gcc_gp1_clk_src", 5141c9efb0bSTaniya Das .parent_data = gcc_parent_data_1, 5151c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_1), 5161c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 5171c9efb0bSTaniya Das }, 5181c9efb0bSTaniya Das }; 5191c9efb0bSTaniya Das 5201c9efb0bSTaniya Das static struct clk_rcg2 gcc_gp2_clk_src = { 5211c9efb0bSTaniya Das .cmd_rcgr = 0x75004, 5221c9efb0bSTaniya Das .mnd_width = 16, 5231c9efb0bSTaniya Das .hid_width = 5, 5241c9efb0bSTaniya Das .parent_map = gcc_parent_map_1, 5251c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_gp1_clk_src, 5261c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 5271c9efb0bSTaniya Das .name = "gcc_gp2_clk_src", 5281c9efb0bSTaniya Das .parent_data = gcc_parent_data_1, 5291c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_1), 5301c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 5311c9efb0bSTaniya Das }, 5321c9efb0bSTaniya Das }; 5331c9efb0bSTaniya Das 5341c9efb0bSTaniya Das static struct clk_rcg2 gcc_gp3_clk_src = { 5351c9efb0bSTaniya Das .cmd_rcgr = 0x76004, 5361c9efb0bSTaniya Das .mnd_width = 16, 5371c9efb0bSTaniya Das .hid_width = 5, 5381c9efb0bSTaniya Das .parent_map = gcc_parent_map_1, 5391c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_gp1_clk_src, 5401c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 5411c9efb0bSTaniya Das .name = "gcc_gp3_clk_src", 5421c9efb0bSTaniya Das .parent_data = gcc_parent_data_1, 5431c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_1), 5441c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 5451c9efb0bSTaniya Das }, 5461c9efb0bSTaniya Das }; 5471c9efb0bSTaniya Das 5481c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 5491c9efb0bSTaniya Das F(19200000, P_BI_TCXO, 1, 0, 0), 5501c9efb0bSTaniya Das { } 5511c9efb0bSTaniya Das }; 5521c9efb0bSTaniya Das 5531c9efb0bSTaniya Das static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 5541c9efb0bSTaniya Das .cmd_rcgr = 0x9d068, 5551c9efb0bSTaniya Das .mnd_width = 16, 5561c9efb0bSTaniya Das .hid_width = 5, 5571c9efb0bSTaniya Das .parent_map = gcc_parent_map_3, 5581c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 5591c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 5601c9efb0bSTaniya Das .name = "gcc_pcie_0_aux_clk_src", 5611c9efb0bSTaniya Das .parent_data = gcc_parent_data_3, 5621c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_3), 5631c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 5641c9efb0bSTaniya Das }, 5651c9efb0bSTaniya Das }; 5661c9efb0bSTaniya Das 5671c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 5681c9efb0bSTaniya Das F(19200000, P_BI_TCXO, 1, 0, 0), 5691c9efb0bSTaniya Das F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 5701c9efb0bSTaniya Das { } 5711c9efb0bSTaniya Das }; 5721c9efb0bSTaniya Das 5731c9efb0bSTaniya Das static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 5741c9efb0bSTaniya Das .cmd_rcgr = 0x9d04c, 5751c9efb0bSTaniya Das .mnd_width = 0, 5761c9efb0bSTaniya Das .hid_width = 5, 5771c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 5781c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 5791c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 5801c9efb0bSTaniya Das .name = "gcc_pcie_0_phy_rchng_clk_src", 5811c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 5821c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 5831c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 5841c9efb0bSTaniya Das }, 5851c9efb0bSTaniya Das }; 5861c9efb0bSTaniya Das 5871c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 5881c9efb0bSTaniya Das F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 5891c9efb0bSTaniya Das { } 5901c9efb0bSTaniya Das }; 5911c9efb0bSTaniya Das 5921c9efb0bSTaniya Das static struct clk_rcg2 gcc_pdm2_clk_src = { 5931c9efb0bSTaniya Das .cmd_rcgr = 0x43010, 5941c9efb0bSTaniya Das .mnd_width = 0, 5951c9efb0bSTaniya Das .hid_width = 5, 5961c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 5971c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_pdm2_clk_src, 5981c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 5991c9efb0bSTaniya Das .name = "gcc_pdm2_clk_src", 6001c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 6011c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 6021c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 6031c9efb0bSTaniya Das }, 6041c9efb0bSTaniya Das }; 6051c9efb0bSTaniya Das 6061c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 6071c9efb0bSTaniya Das F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 6081c9efb0bSTaniya Das F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 6091c9efb0bSTaniya Das F(19200000, P_BI_TCXO, 1, 0, 0), 6101c9efb0bSTaniya Das F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 6111c9efb0bSTaniya Das F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 6121c9efb0bSTaniya Das F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 6131c9efb0bSTaniya Das F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 6141c9efb0bSTaniya Das F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 6151c9efb0bSTaniya Das F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 6161c9efb0bSTaniya Das F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 6171c9efb0bSTaniya Das { } 6181c9efb0bSTaniya Das }; 6191c9efb0bSTaniya Das 6201c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 6211c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s0_clk_src", 6221c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 6231c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 6241c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 6251c9efb0bSTaniya Das }; 6261c9efb0bSTaniya Das 6271c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 6281c9efb0bSTaniya Das .cmd_rcgr = 0x27154, 6291c9efb0bSTaniya Das .mnd_width = 16, 6301c9efb0bSTaniya Das .hid_width = 5, 6311c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 6321c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 6331c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 6341c9efb0bSTaniya Das }; 6351c9efb0bSTaniya Das 6361c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 6371c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s1_clk_src", 6381c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 6391c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 6401c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 6411c9efb0bSTaniya Das }; 6421c9efb0bSTaniya Das 6431c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 6441c9efb0bSTaniya Das .cmd_rcgr = 0x27288, 6451c9efb0bSTaniya Das .mnd_width = 16, 6461c9efb0bSTaniya Das .hid_width = 5, 6471c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 6481c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 6491c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 6501c9efb0bSTaniya Das }; 6511c9efb0bSTaniya Das 6521c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 6531c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s2_clk_src", 6541c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 6551c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 6561c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 6571c9efb0bSTaniya Das }; 6581c9efb0bSTaniya Das 6591c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 6601c9efb0bSTaniya Das .cmd_rcgr = 0x273bc, 6611c9efb0bSTaniya Das .mnd_width = 16, 6621c9efb0bSTaniya Das .hid_width = 5, 6631c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 6641c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 6651c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 6661c9efb0bSTaniya Das }; 6671c9efb0bSTaniya Das 6681c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 6691c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s3_clk_src", 6701c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 6711c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 6721c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 6731c9efb0bSTaniya Das }; 6741c9efb0bSTaniya Das 6751c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 6761c9efb0bSTaniya Das .cmd_rcgr = 0x274f0, 6771c9efb0bSTaniya Das .mnd_width = 16, 6781c9efb0bSTaniya Das .hid_width = 5, 6791c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 6801c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 6811c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 6821c9efb0bSTaniya Das }; 6831c9efb0bSTaniya Das 6841c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 6851c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s4_clk_src", 6861c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 6871c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 6881c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 6891c9efb0bSTaniya Das }; 6901c9efb0bSTaniya Das 6911c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 6921c9efb0bSTaniya Das .cmd_rcgr = 0x27624, 6931c9efb0bSTaniya Das .mnd_width = 16, 6941c9efb0bSTaniya Das .hid_width = 5, 6951c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 6961c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 6971c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 6981c9efb0bSTaniya Das }; 6991c9efb0bSTaniya Das 7001c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] = { 7011c9efb0bSTaniya Das F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 7021c9efb0bSTaniya Das { } 7031c9efb0bSTaniya Das }; 7041c9efb0bSTaniya Das 7051c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 7061c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s5_clk_src", 7071c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 7081c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 7091c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 7101c9efb0bSTaniya Das }; 7111c9efb0bSTaniya Das 7121c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 7131c9efb0bSTaniya Das .cmd_rcgr = 0x27758, 7141c9efb0bSTaniya Das .mnd_width = 16, 7151c9efb0bSTaniya Das .hid_width = 5, 7161c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 7171c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src, 7181c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 7191c9efb0bSTaniya Das }; 7201c9efb0bSTaniya Das 7211c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 7221c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s6_clk_src", 7231c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 7241c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 7251c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 7261c9efb0bSTaniya Das }; 7271c9efb0bSTaniya Das 7281c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 7291c9efb0bSTaniya Das .cmd_rcgr = 0x2788c, 7301c9efb0bSTaniya Das .mnd_width = 16, 7311c9efb0bSTaniya Das .hid_width = 5, 7321c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 7331c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 7341c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 7351c9efb0bSTaniya Das }; 7361c9efb0bSTaniya Das 7371c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 7381c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s7_clk_src", 7391c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 7401c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 7411c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 7421c9efb0bSTaniya Das }; 7431c9efb0bSTaniya Das 7441c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 7451c9efb0bSTaniya Das .cmd_rcgr = 0x279c0, 7461c9efb0bSTaniya Das .mnd_width = 16, 7471c9efb0bSTaniya Das .hid_width = 5, 7481c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 7491c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 7501c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 7511c9efb0bSTaniya Das }; 7521c9efb0bSTaniya Das 7531c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 7541c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s0_clk_src", 7551c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 7561c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 7571c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 7581c9efb0bSTaniya Das }; 7591c9efb0bSTaniya Das 7601c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 7611c9efb0bSTaniya Das .cmd_rcgr = 0x28154, 7621c9efb0bSTaniya Das .mnd_width = 16, 7631c9efb0bSTaniya Das .hid_width = 5, 7641c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 7651c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 7661c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 7671c9efb0bSTaniya Das }; 7681c9efb0bSTaniya Das 7691c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 7701c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s1_clk_src", 7711c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 7721c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 7731c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 7741c9efb0bSTaniya Das }; 7751c9efb0bSTaniya Das 7761c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 7771c9efb0bSTaniya Das .cmd_rcgr = 0x28288, 7781c9efb0bSTaniya Das .mnd_width = 16, 7791c9efb0bSTaniya Das .hid_width = 5, 7801c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 7811c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 7821c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 7831c9efb0bSTaniya Das }; 7841c9efb0bSTaniya Das 7851c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 7861c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s2_clk_src", 7871c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 7881c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 7891c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 7901c9efb0bSTaniya Das }; 7911c9efb0bSTaniya Das 7921c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 7931c9efb0bSTaniya Das .cmd_rcgr = 0x283bc, 7941c9efb0bSTaniya Das .mnd_width = 16, 7951c9efb0bSTaniya Das .hid_width = 5, 7961c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 7971c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 7981c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 7991c9efb0bSTaniya Das }; 8001c9efb0bSTaniya Das 8011c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 8021c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s3_clk_src", 8031c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 8041c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 8051c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 8061c9efb0bSTaniya Das }; 8071c9efb0bSTaniya Das 8081c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 8091c9efb0bSTaniya Das .cmd_rcgr = 0x284f0, 8101c9efb0bSTaniya Das .mnd_width = 16, 8111c9efb0bSTaniya Das .hid_width = 5, 8121c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 8131c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 8141c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 8151c9efb0bSTaniya Das }; 8161c9efb0bSTaniya Das 8171c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 8181c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s4_clk_src", 8191c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 8201c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 8211c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 8221c9efb0bSTaniya Das }; 8231c9efb0bSTaniya Das 8241c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 8251c9efb0bSTaniya Das .cmd_rcgr = 0x28624, 8261c9efb0bSTaniya Das .mnd_width = 16, 8271c9efb0bSTaniya Das .hid_width = 5, 8281c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 8291c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 8301c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 8311c9efb0bSTaniya Das }; 8321c9efb0bSTaniya Das 8331c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 8341c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s5_clk_src", 8351c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 8361c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 8371c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 8381c9efb0bSTaniya Das }; 8391c9efb0bSTaniya Das 8401c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 8411c9efb0bSTaniya Das .cmd_rcgr = 0x28758, 8421c9efb0bSTaniya Das .mnd_width = 16, 8431c9efb0bSTaniya Das .hid_width = 5, 8441c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 8451c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 8461c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 8471c9efb0bSTaniya Das }; 8481c9efb0bSTaniya Das 8491c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 8501c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s6_clk_src", 8511c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 8521c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 8531c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 8541c9efb0bSTaniya Das }; 8551c9efb0bSTaniya Das 8561c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 8571c9efb0bSTaniya Das .cmd_rcgr = 0x2888c, 8581c9efb0bSTaniya Das .mnd_width = 16, 8591c9efb0bSTaniya Das .hid_width = 5, 8601c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 8611c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 8621c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 8631c9efb0bSTaniya Das }; 8641c9efb0bSTaniya Das 8651c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 8661c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s7_clk_src", 8671c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 8681c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 8691c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 8701c9efb0bSTaniya Das }; 8711c9efb0bSTaniya Das 8721c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 8731c9efb0bSTaniya Das .cmd_rcgr = 0x289c0, 8741c9efb0bSTaniya Das .mnd_width = 16, 8751c9efb0bSTaniya Das .hid_width = 5, 8761c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 8771c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 8781c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 8791c9efb0bSTaniya Das }; 8801c9efb0bSTaniya Das 8811c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_sdcc5_apps_clk_src[] = { 8821c9efb0bSTaniya Das F(144000, P_BI_TCXO, 16, 3, 25), 8831c9efb0bSTaniya Das F(400000, P_BI_TCXO, 12, 1, 4), 8841c9efb0bSTaniya Das F(19200000, P_BI_TCXO, 1, 0, 0), 8851c9efb0bSTaniya Das F(20000000, P_GCC_GPLL0_OUT_MAIN, 10, 1, 3), 8861c9efb0bSTaniya Das F(25000000, P_GCC_GPLL0_OUT_MAIN, 12, 1, 2), 8871c9efb0bSTaniya Das F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0), 8881c9efb0bSTaniya Das F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 8891c9efb0bSTaniya Das F(192000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0), 8901c9efb0bSTaniya Das F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 8911c9efb0bSTaniya Das F(384000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0), 8921c9efb0bSTaniya Das { } 8931c9efb0bSTaniya Das }; 8941c9efb0bSTaniya Das 8951c9efb0bSTaniya Das static struct clk_rcg2 gcc_sdcc5_apps_clk_src = { 8961c9efb0bSTaniya Das .cmd_rcgr = 0x3b034, 8971c9efb0bSTaniya Das .mnd_width = 8, 8981c9efb0bSTaniya Das .hid_width = 5, 8991c9efb0bSTaniya Das .parent_map = gcc_parent_map_8, 9001c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_sdcc5_apps_clk_src, 9011c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 9021c9efb0bSTaniya Das .name = "gcc_sdcc5_apps_clk_src", 9031c9efb0bSTaniya Das .parent_data = gcc_parent_data_8, 9041c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_8), 9051c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 9061c9efb0bSTaniya Das }, 9071c9efb0bSTaniya Das }; 9081c9efb0bSTaniya Das 9091c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_sdcc5_ice_core_clk_src[] = { 9101c9efb0bSTaniya Das F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 9111c9efb0bSTaniya Das { } 9121c9efb0bSTaniya Das }; 9131c9efb0bSTaniya Das 9141c9efb0bSTaniya Das static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src = { 9151c9efb0bSTaniya Das .cmd_rcgr = 0x3b01c, 9161c9efb0bSTaniya Das .mnd_width = 0, 9171c9efb0bSTaniya Das .hid_width = 5, 9181c9efb0bSTaniya Das .parent_map = gcc_parent_map_2, 9191c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_sdcc5_ice_core_clk_src, 9201c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 9211c9efb0bSTaniya Das .name = "gcc_sdcc5_ice_core_clk_src", 9221c9efb0bSTaniya Das .parent_data = gcc_parent_data_2, 9231c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_2), 9241c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 9251c9efb0bSTaniya Das }, 9261c9efb0bSTaniya Das }; 9271c9efb0bSTaniya Das 9281c9efb0bSTaniya Das static struct clk_rcg2 gcc_sm_bus_xo_clk_src = { 9291c9efb0bSTaniya Das .cmd_rcgr = 0x5b00c, 9301c9efb0bSTaniya Das .mnd_width = 0, 9311c9efb0bSTaniya Das .hid_width = 5, 9321c9efb0bSTaniya Das .parent_map = gcc_parent_map_2, 9331c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 9341c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 9351c9efb0bSTaniya Das .name = "gcc_sm_bus_xo_clk_src", 9361c9efb0bSTaniya Das .parent_data = gcc_parent_data_2, 9371c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_2), 9381c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 9391c9efb0bSTaniya Das }, 9401c9efb0bSTaniya Das }; 9411c9efb0bSTaniya Das 9421c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_tsc_clk_src[] = { 9431c9efb0bSTaniya Das F(500000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0), 9441c9efb0bSTaniya Das { } 9451c9efb0bSTaniya Das }; 9461c9efb0bSTaniya Das 9471c9efb0bSTaniya Das static struct clk_rcg2 gcc_tsc_clk_src = { 9481c9efb0bSTaniya Das .cmd_rcgr = 0x57010, 9491c9efb0bSTaniya Das .mnd_width = 0, 9501c9efb0bSTaniya Das .hid_width = 5, 9511c9efb0bSTaniya Das .parent_map = gcc_parent_map_9, 9521c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_tsc_clk_src, 9531c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 9541c9efb0bSTaniya Das .name = "gcc_tsc_clk_src", 9551c9efb0bSTaniya Das .parent_data = gcc_parent_data_9, 9561c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_9), 9571c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 9581c9efb0bSTaniya Das }, 9591c9efb0bSTaniya Das }; 9601c9efb0bSTaniya Das 9611c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 9621c9efb0bSTaniya Das F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 9631c9efb0bSTaniya Das F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 9641c9efb0bSTaniya Das { } 9651c9efb0bSTaniya Das }; 9661c9efb0bSTaniya Das 9671c9efb0bSTaniya Das static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 9681c9efb0bSTaniya Das .cmd_rcgr = 0x49028, 9691c9efb0bSTaniya Das .mnd_width = 8, 9701c9efb0bSTaniya Das .hid_width = 5, 9711c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 9721c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 9731c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 9741c9efb0bSTaniya Das .name = "gcc_usb30_prim_master_clk_src", 9751c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 9761c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 9771c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 9781c9efb0bSTaniya Das }, 9791c9efb0bSTaniya Das }; 9801c9efb0bSTaniya Das 9811c9efb0bSTaniya Das static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 9821c9efb0bSTaniya Das .cmd_rcgr = 0x49044, 9831c9efb0bSTaniya Das .mnd_width = 0, 9841c9efb0bSTaniya Das .hid_width = 5, 9851c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 9861c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 9871c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 9881c9efb0bSTaniya Das .name = "gcc_usb30_prim_mock_utmi_clk_src", 9891c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 9901c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 9911c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 9921c9efb0bSTaniya Das }, 9931c9efb0bSTaniya Das }; 9941c9efb0bSTaniya Das 9951c9efb0bSTaniya Das static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 9961c9efb0bSTaniya Das .cmd_rcgr = 0x49070, 9971c9efb0bSTaniya Das .mnd_width = 0, 9981c9efb0bSTaniya Das .hid_width = 5, 9991c9efb0bSTaniya Das .parent_map = gcc_parent_map_3, 10001c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 10011c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 10021c9efb0bSTaniya Das .name = "gcc_usb3_prim_phy_aux_clk_src", 10031c9efb0bSTaniya Das .parent_data = gcc_parent_data_3, 10041c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_3), 10051c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 10061c9efb0bSTaniya Das }, 10071c9efb0bSTaniya Das }; 10081c9efb0bSTaniya Das 10091c9efb0bSTaniya Das static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 10101c9efb0bSTaniya Das .reg = 0x4905c, 10111c9efb0bSTaniya Das .shift = 0, 10121c9efb0bSTaniya Das .width = 4, 10131c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 10141c9efb0bSTaniya Das .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 10151c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 10161c9efb0bSTaniya Das &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 10171c9efb0bSTaniya Das }, 10181c9efb0bSTaniya Das .num_parents = 1, 10191c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 10201c9efb0bSTaniya Das .ops = &clk_regmap_div_ro_ops, 10211c9efb0bSTaniya Das }, 10221c9efb0bSTaniya Das }; 10231c9efb0bSTaniya Das 10241c9efb0bSTaniya Das static struct clk_branch gcc_aggre_noc_ecpri_dma_clk = { 10251c9efb0bSTaniya Das .halt_reg = 0x92008, 10261c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 10271c9efb0bSTaniya Das .hwcg_reg = 0x92008, 10281c9efb0bSTaniya Das .hwcg_bit = 1, 10291c9efb0bSTaniya Das .clkr = { 10301c9efb0bSTaniya Das .enable_reg = 0x92008, 10311c9efb0bSTaniya Das .enable_mask = BIT(0), 10321c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 10331c9efb0bSTaniya Das .name = "gcc_aggre_noc_ecpri_dma_clk", 10341c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 10351c9efb0bSTaniya Das &gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw, 10361c9efb0bSTaniya Das }, 10371c9efb0bSTaniya Das .num_parents = 1, 10381c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 10391c9efb0bSTaniya Das .ops = &clk_branch2_ops, 10401c9efb0bSTaniya Das }, 10411c9efb0bSTaniya Das }, 10421c9efb0bSTaniya Das }; 10431c9efb0bSTaniya Das 10441c9efb0bSTaniya Das static struct clk_branch gcc_aggre_noc_ecpri_gsi_clk = { 10451c9efb0bSTaniya Das .halt_reg = 0x9201c, 10461c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 10471c9efb0bSTaniya Das .hwcg_reg = 0x9201c, 10481c9efb0bSTaniya Das .hwcg_bit = 1, 10491c9efb0bSTaniya Das .clkr = { 10501c9efb0bSTaniya Das .enable_reg = 0x9201c, 10511c9efb0bSTaniya Das .enable_mask = BIT(0), 10521c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 10531c9efb0bSTaniya Das .name = "gcc_aggre_noc_ecpri_gsi_clk", 10541c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 10551c9efb0bSTaniya Das &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, 10561c9efb0bSTaniya Das }, 10571c9efb0bSTaniya Das .num_parents = 1, 10581c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 10591c9efb0bSTaniya Das .ops = &clk_branch2_ops, 10601c9efb0bSTaniya Das }, 10611c9efb0bSTaniya Das }, 10621c9efb0bSTaniya Das }; 10631c9efb0bSTaniya Das 10641c9efb0bSTaniya Das static struct clk_branch gcc_boot_rom_ahb_clk = { 10651c9efb0bSTaniya Das .halt_reg = 0x48004, 10661c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 10671c9efb0bSTaniya Das .hwcg_reg = 0x48004, 10681c9efb0bSTaniya Das .hwcg_bit = 1, 10691c9efb0bSTaniya Das .clkr = { 10701c9efb0bSTaniya Das .enable_reg = 0x62000, 10711c9efb0bSTaniya Das .enable_mask = BIT(10), 10721c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 10731c9efb0bSTaniya Das .name = "gcc_boot_rom_ahb_clk", 10741c9efb0bSTaniya Das .ops = &clk_branch2_ops, 10751c9efb0bSTaniya Das }, 10761c9efb0bSTaniya Das }, 10771c9efb0bSTaniya Das }; 10781c9efb0bSTaniya Das 10791c9efb0bSTaniya Das static struct clk_branch gcc_cfg_noc_ecpri_cc_ahb_clk = { 10801c9efb0bSTaniya Das .halt_reg = 0x3e004, 10811c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 10821c9efb0bSTaniya Das .hwcg_reg = 0x3e004, 10831c9efb0bSTaniya Das .hwcg_bit = 1, 10841c9efb0bSTaniya Das .clkr = { 10851c9efb0bSTaniya Das .enable_reg = 0x3e004, 10861c9efb0bSTaniya Das .enable_mask = BIT(0), 10871c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 10881c9efb0bSTaniya Das .name = "gcc_cfg_noc_ecpri_cc_ahb_clk", 10891c9efb0bSTaniya Das .ops = &clk_branch2_ops, 10901c9efb0bSTaniya Das }, 10911c9efb0bSTaniya Das }, 10921c9efb0bSTaniya Das }; 10931c9efb0bSTaniya Das 10941c9efb0bSTaniya Das static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 10951c9efb0bSTaniya Das .halt_reg = 0x8401c, 10961c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 10971c9efb0bSTaniya Das .hwcg_reg = 0x8401c, 10981c9efb0bSTaniya Das .hwcg_bit = 1, 10991c9efb0bSTaniya Das .clkr = { 11001c9efb0bSTaniya Das .enable_reg = 0x8401c, 11011c9efb0bSTaniya Das .enable_mask = BIT(0), 11021c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 11031c9efb0bSTaniya Das .name = "gcc_cfg_noc_usb3_prim_axi_clk", 11041c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 11051c9efb0bSTaniya Das &gcc_usb30_prim_master_clk_src.clkr.hw, 11061c9efb0bSTaniya Das }, 11071c9efb0bSTaniya Das .num_parents = 1, 11081c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 11091c9efb0bSTaniya Das .ops = &clk_branch2_ops, 11101c9efb0bSTaniya Das }, 11111c9efb0bSTaniya Das }, 11121c9efb0bSTaniya Das }; 11131c9efb0bSTaniya Das 11141c9efb0bSTaniya Das static struct clk_branch gcc_ddrss_ecpri_dma_clk = { 11151c9efb0bSTaniya Das .halt_reg = 0x54030, 11161c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 11171c9efb0bSTaniya Das .hwcg_reg = 0x54030, 11181c9efb0bSTaniya Das .hwcg_bit = 1, 11191c9efb0bSTaniya Das .clkr = { 11201c9efb0bSTaniya Das .enable_reg = 0x54030, 11211c9efb0bSTaniya Das .enable_mask = BIT(0), 11221c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 11231c9efb0bSTaniya Das .name = "gcc_ddrss_ecpri_dma_clk", 11241c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 11251c9efb0bSTaniya Das &gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw, 11261c9efb0bSTaniya Das }, 11271c9efb0bSTaniya Das .num_parents = 1, 11281c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 11291c9efb0bSTaniya Das .ops = &clk_branch2_aon_ops, 11301c9efb0bSTaniya Das }, 11311c9efb0bSTaniya Das }, 11321c9efb0bSTaniya Das }; 11331c9efb0bSTaniya Das 11341c9efb0bSTaniya Das static struct clk_branch gcc_ecpri_ahb_clk = { 11351c9efb0bSTaniya Das .halt_reg = 0x3a008, 11361c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 11371c9efb0bSTaniya Das .hwcg_reg = 0x3a008, 11381c9efb0bSTaniya Das .hwcg_bit = 1, 11391c9efb0bSTaniya Das .clkr = { 11401c9efb0bSTaniya Das .enable_reg = 0x3a008, 11411c9efb0bSTaniya Das .enable_mask = BIT(0), 11421c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 11431c9efb0bSTaniya Das .name = "gcc_ecpri_ahb_clk", 11441c9efb0bSTaniya Das .ops = &clk_branch2_ops, 11451c9efb0bSTaniya Das }, 11461c9efb0bSTaniya Das }, 11471c9efb0bSTaniya Das }; 11481c9efb0bSTaniya Das 11491c9efb0bSTaniya Das static struct clk_branch gcc_ecpri_cc_gpll0_clk_src = { 11501c9efb0bSTaniya Das .halt_check = BRANCH_HALT_DELAY, 11511c9efb0bSTaniya Das .clkr = { 11521c9efb0bSTaniya Das .enable_reg = 0x62010, 11531c9efb0bSTaniya Das .enable_mask = BIT(0), 11541c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 11551c9efb0bSTaniya Das .name = "gcc_ecpri_cc_gpll0_clk_src", 11561c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 11571c9efb0bSTaniya Das &gcc_gpll0.clkr.hw, 11581c9efb0bSTaniya Das }, 11591c9efb0bSTaniya Das .num_parents = 1, 11601c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 11611c9efb0bSTaniya Das .ops = &clk_branch2_ops, 11621c9efb0bSTaniya Das }, 11631c9efb0bSTaniya Das }, 11641c9efb0bSTaniya Das }; 11651c9efb0bSTaniya Das 11661c9efb0bSTaniya Das static struct clk_branch gcc_ecpri_cc_gpll1_even_clk_src = { 11671c9efb0bSTaniya Das .halt_check = BRANCH_HALT_DELAY, 11681c9efb0bSTaniya Das .clkr = { 11691c9efb0bSTaniya Das .enable_reg = 0x62010, 11701c9efb0bSTaniya Das .enable_mask = BIT(1), 11711c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 11721c9efb0bSTaniya Das .name = "gcc_ecpri_cc_gpll1_even_clk_src", 11731c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 11741c9efb0bSTaniya Das &gcc_gpll1_out_even.clkr.hw, 11751c9efb0bSTaniya Das }, 11761c9efb0bSTaniya Das .num_parents = 1, 11771c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 11781c9efb0bSTaniya Das .ops = &clk_branch2_ops, 11791c9efb0bSTaniya Das }, 11801c9efb0bSTaniya Das }, 11811c9efb0bSTaniya Das }; 11821c9efb0bSTaniya Das 11831c9efb0bSTaniya Das static struct clk_branch gcc_ecpri_cc_gpll2_even_clk_src = { 11841c9efb0bSTaniya Das .halt_check = BRANCH_HALT_DELAY, 11851c9efb0bSTaniya Das .clkr = { 11861c9efb0bSTaniya Das .enable_reg = 0x62010, 11871c9efb0bSTaniya Das .enable_mask = BIT(2), 11881c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 11891c9efb0bSTaniya Das .name = "gcc_ecpri_cc_gpll2_even_clk_src", 11901c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 11911c9efb0bSTaniya Das &gcc_gpll2_out_even.clkr.hw, 11921c9efb0bSTaniya Das }, 11931c9efb0bSTaniya Das .num_parents = 1, 11941c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 11951c9efb0bSTaniya Das .ops = &clk_branch2_ops, 11961c9efb0bSTaniya Das }, 11971c9efb0bSTaniya Das }, 11981c9efb0bSTaniya Das }; 11991c9efb0bSTaniya Das 12001c9efb0bSTaniya Das static struct clk_branch gcc_ecpri_cc_gpll3_clk_src = { 12011c9efb0bSTaniya Das .halt_check = BRANCH_HALT_DELAY, 12021c9efb0bSTaniya Das .clkr = { 12031c9efb0bSTaniya Das .enable_reg = 0x62010, 12041c9efb0bSTaniya Das .enable_mask = BIT(3), 12051c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 12061c9efb0bSTaniya Das .name = "gcc_ecpri_cc_gpll3_clk_src", 12071c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 12081c9efb0bSTaniya Das &gcc_gpll3.clkr.hw, 12091c9efb0bSTaniya Das }, 12101c9efb0bSTaniya Das .num_parents = 1, 12111c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 12121c9efb0bSTaniya Das .ops = &clk_branch2_ops, 12131c9efb0bSTaniya Das }, 12141c9efb0bSTaniya Das }, 12151c9efb0bSTaniya Das }; 12161c9efb0bSTaniya Das 12171c9efb0bSTaniya Das static struct clk_branch gcc_ecpri_cc_gpll4_clk_src = { 12181c9efb0bSTaniya Das .halt_check = BRANCH_HALT_DELAY, 12191c9efb0bSTaniya Das .clkr = { 12201c9efb0bSTaniya Das .enable_reg = 0x62010, 12211c9efb0bSTaniya Das .enable_mask = BIT(4), 12221c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 12231c9efb0bSTaniya Das .name = "gcc_ecpri_cc_gpll4_clk_src", 12241c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 12251c9efb0bSTaniya Das &gcc_gpll4.clkr.hw, 12261c9efb0bSTaniya Das }, 12271c9efb0bSTaniya Das .num_parents = 1, 12281c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 12291c9efb0bSTaniya Das .ops = &clk_branch2_ops, 12301c9efb0bSTaniya Das }, 12311c9efb0bSTaniya Das }, 12321c9efb0bSTaniya Das }; 12331c9efb0bSTaniya Das 12341c9efb0bSTaniya Das static struct clk_branch gcc_ecpri_cc_gpll5_even_clk_src = { 12351c9efb0bSTaniya Das .halt_check = BRANCH_HALT_DELAY, 12361c9efb0bSTaniya Das .clkr = { 12371c9efb0bSTaniya Das .enable_reg = 0x62010, 12381c9efb0bSTaniya Das .enable_mask = BIT(5), 12391c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 12401c9efb0bSTaniya Das .name = "gcc_ecpri_cc_gpll5_even_clk_src", 12411c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 12421c9efb0bSTaniya Das &gcc_gpll5_out_even.clkr.hw, 12431c9efb0bSTaniya Das }, 12441c9efb0bSTaniya Das .num_parents = 1, 12451c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 12461c9efb0bSTaniya Das .ops = &clk_branch2_ops, 12471c9efb0bSTaniya Das }, 12481c9efb0bSTaniya Das }, 12491c9efb0bSTaniya Das }; 12501c9efb0bSTaniya Das 12511c9efb0bSTaniya Das static struct clk_branch gcc_ecpri_xo_clk = { 12521c9efb0bSTaniya Das .halt_reg = 0x3a004, 12531c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 12541c9efb0bSTaniya Das .clkr = { 12551c9efb0bSTaniya Das .enable_reg = 0x3a004, 12561c9efb0bSTaniya Das .enable_mask = BIT(0), 12571c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 12581c9efb0bSTaniya Das .name = "gcc_ecpri_xo_clk", 12591c9efb0bSTaniya Das .ops = &clk_branch2_ops, 12601c9efb0bSTaniya Das }, 12611c9efb0bSTaniya Das }, 12621c9efb0bSTaniya Das }; 12631c9efb0bSTaniya Das 12641c9efb0bSTaniya Das static struct clk_branch gcc_eth_100g_c2c_hm_apb_clk = { 12651c9efb0bSTaniya Das .halt_reg = 0x39010, 12661c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 12671c9efb0bSTaniya Das .clkr = { 12681c9efb0bSTaniya Das .enable_reg = 0x39010, 12691c9efb0bSTaniya Das .enable_mask = BIT(0), 12701c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 12711c9efb0bSTaniya Das .name = "gcc_eth_100g_c2c_hm_apb_clk", 12721c9efb0bSTaniya Das .ops = &clk_branch2_ops, 12731c9efb0bSTaniya Das }, 12741c9efb0bSTaniya Das }, 12751c9efb0bSTaniya Das }; 12761c9efb0bSTaniya Das 12771c9efb0bSTaniya Das static struct clk_branch gcc_eth_100g_fh_hm_apb_0_clk = { 12781c9efb0bSTaniya Das .halt_reg = 0x39004, 12791c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 12801c9efb0bSTaniya Das .clkr = { 12811c9efb0bSTaniya Das .enable_reg = 0x39004, 12821c9efb0bSTaniya Das .enable_mask = BIT(0), 12831c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 12841c9efb0bSTaniya Das .name = "gcc_eth_100g_fh_hm_apb_0_clk", 12851c9efb0bSTaniya Das .ops = &clk_branch2_ops, 12861c9efb0bSTaniya Das }, 12871c9efb0bSTaniya Das }, 12881c9efb0bSTaniya Das }; 12891c9efb0bSTaniya Das 12901c9efb0bSTaniya Das static struct clk_branch gcc_eth_100g_fh_hm_apb_1_clk = { 12911c9efb0bSTaniya Das .halt_reg = 0x39008, 12921c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 12931c9efb0bSTaniya Das .clkr = { 12941c9efb0bSTaniya Das .enable_reg = 0x39008, 12951c9efb0bSTaniya Das .enable_mask = BIT(0), 12961c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 12971c9efb0bSTaniya Das .name = "gcc_eth_100g_fh_hm_apb_1_clk", 12981c9efb0bSTaniya Das .ops = &clk_branch2_ops, 12991c9efb0bSTaniya Das }, 13001c9efb0bSTaniya Das }, 13011c9efb0bSTaniya Das }; 13021c9efb0bSTaniya Das 13031c9efb0bSTaniya Das static struct clk_branch gcc_eth_100g_fh_hm_apb_2_clk = { 13041c9efb0bSTaniya Das .halt_reg = 0x3900c, 13051c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 13061c9efb0bSTaniya Das .clkr = { 13071c9efb0bSTaniya Das .enable_reg = 0x3900c, 13081c9efb0bSTaniya Das .enable_mask = BIT(0), 13091c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 13101c9efb0bSTaniya Das .name = "gcc_eth_100g_fh_hm_apb_2_clk", 13111c9efb0bSTaniya Das .ops = &clk_branch2_ops, 13121c9efb0bSTaniya Das }, 13131c9efb0bSTaniya Das }, 13141c9efb0bSTaniya Das }; 13151c9efb0bSTaniya Das 13161c9efb0bSTaniya Das static struct clk_branch gcc_eth_dbg_c2c_hm_apb_clk = { 13171c9efb0bSTaniya Das .halt_reg = 0x39014, 13181c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 13191c9efb0bSTaniya Das .clkr = { 13201c9efb0bSTaniya Das .enable_reg = 0x39014, 13211c9efb0bSTaniya Das .enable_mask = BIT(0), 13221c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 13231c9efb0bSTaniya Das .name = "gcc_eth_dbg_c2c_hm_apb_clk", 13241c9efb0bSTaniya Das .ops = &clk_branch2_ops, 13251c9efb0bSTaniya Das }, 13261c9efb0bSTaniya Das }, 13271c9efb0bSTaniya Das }; 13281c9efb0bSTaniya Das 13291c9efb0bSTaniya Das static struct clk_branch gcc_eth_dbg_snoc_axi_clk = { 13301c9efb0bSTaniya Das .halt_reg = 0x3901c, 13311c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 13321c9efb0bSTaniya Das .hwcg_reg = 0x3901c, 13331c9efb0bSTaniya Das .hwcg_bit = 1, 13341c9efb0bSTaniya Das .clkr = { 13351c9efb0bSTaniya Das .enable_reg = 0x3901c, 13361c9efb0bSTaniya Das .enable_mask = BIT(0), 13371c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 13381c9efb0bSTaniya Das .name = "gcc_eth_dbg_snoc_axi_clk", 13391c9efb0bSTaniya Das .ops = &clk_branch2_ops, 13401c9efb0bSTaniya Das }, 13411c9efb0bSTaniya Das }, 13421c9efb0bSTaniya Das }; 13431c9efb0bSTaniya Das 13441c9efb0bSTaniya Das static struct clk_branch gcc_gemnoc_pcie_qx_clk = { 13451c9efb0bSTaniya Das .halt_reg = 0x5402c, 13461c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 13471c9efb0bSTaniya Das .hwcg_reg = 0x5402c, 13481c9efb0bSTaniya Das .hwcg_bit = 1, 13491c9efb0bSTaniya Das .clkr = { 13501c9efb0bSTaniya Das .enable_reg = 0x62008, 13511c9efb0bSTaniya Das .enable_mask = BIT(0), 13521c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 13531c9efb0bSTaniya Das .name = "gcc_gemnoc_pcie_qx_clk", 13541c9efb0bSTaniya Das .ops = &clk_branch2_aon_ops, 13551c9efb0bSTaniya Das }, 13561c9efb0bSTaniya Das }, 13571c9efb0bSTaniya Das }; 13581c9efb0bSTaniya Das 13591c9efb0bSTaniya Das static struct clk_branch gcc_gp1_clk = { 13601c9efb0bSTaniya Das .halt_reg = 0x74000, 13611c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 13621c9efb0bSTaniya Das .clkr = { 13631c9efb0bSTaniya Das .enable_reg = 0x74000, 13641c9efb0bSTaniya Das .enable_mask = BIT(0), 13651c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 13661c9efb0bSTaniya Das .name = "gcc_gp1_clk", 13671c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 13681c9efb0bSTaniya Das &gcc_gp1_clk_src.clkr.hw, 13691c9efb0bSTaniya Das }, 13701c9efb0bSTaniya Das .num_parents = 1, 13711c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 13721c9efb0bSTaniya Das .ops = &clk_branch2_ops, 13731c9efb0bSTaniya Das }, 13741c9efb0bSTaniya Das }, 13751c9efb0bSTaniya Das }; 13761c9efb0bSTaniya Das 13771c9efb0bSTaniya Das static struct clk_branch gcc_gp2_clk = { 13781c9efb0bSTaniya Das .halt_reg = 0x75000, 13791c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 13801c9efb0bSTaniya Das .clkr = { 13811c9efb0bSTaniya Das .enable_reg = 0x75000, 13821c9efb0bSTaniya Das .enable_mask = BIT(0), 13831c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 13841c9efb0bSTaniya Das .name = "gcc_gp2_clk", 13851c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 13861c9efb0bSTaniya Das &gcc_gp2_clk_src.clkr.hw, 13871c9efb0bSTaniya Das }, 13881c9efb0bSTaniya Das .num_parents = 1, 13891c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 13901c9efb0bSTaniya Das .ops = &clk_branch2_ops, 13911c9efb0bSTaniya Das }, 13921c9efb0bSTaniya Das }, 13931c9efb0bSTaniya Das }; 13941c9efb0bSTaniya Das 13951c9efb0bSTaniya Das static struct clk_branch gcc_gp3_clk = { 13961c9efb0bSTaniya Das .halt_reg = 0x76000, 13971c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 13981c9efb0bSTaniya Das .clkr = { 13991c9efb0bSTaniya Das .enable_reg = 0x76000, 14001c9efb0bSTaniya Das .enable_mask = BIT(0), 14011c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 14021c9efb0bSTaniya Das .name = "gcc_gp3_clk", 14031c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 14041c9efb0bSTaniya Das &gcc_gp3_clk_src.clkr.hw, 14051c9efb0bSTaniya Das }, 14061c9efb0bSTaniya Das .num_parents = 1, 14071c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 14081c9efb0bSTaniya Das .ops = &clk_branch2_ops, 14091c9efb0bSTaniya Das }, 14101c9efb0bSTaniya Das }, 14111c9efb0bSTaniya Das }; 14121c9efb0bSTaniya Das 14131c9efb0bSTaniya Das static struct clk_branch gcc_pcie_0_aux_clk = { 14141c9efb0bSTaniya Das .halt_reg = 0x9d030, 14151c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 14161c9efb0bSTaniya Das .hwcg_reg = 0x9d030, 14171c9efb0bSTaniya Das .hwcg_bit = 1, 14181c9efb0bSTaniya Das .clkr = { 14191c9efb0bSTaniya Das .enable_reg = 0x62000, 14201c9efb0bSTaniya Das .enable_mask = BIT(29), 14211c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 14221c9efb0bSTaniya Das .name = "gcc_pcie_0_aux_clk", 14231c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 14241c9efb0bSTaniya Das &gcc_pcie_0_aux_clk_src.clkr.hw, 14251c9efb0bSTaniya Das }, 14261c9efb0bSTaniya Das .num_parents = 1, 14271c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 14281c9efb0bSTaniya Das .ops = &clk_branch2_ops, 14291c9efb0bSTaniya Das }, 14301c9efb0bSTaniya Das }, 14311c9efb0bSTaniya Das }; 14321c9efb0bSTaniya Das 14331c9efb0bSTaniya Das static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 14341c9efb0bSTaniya Das .halt_reg = 0x9d02c, 14351c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 14361c9efb0bSTaniya Das .hwcg_reg = 0x9d02c, 14371c9efb0bSTaniya Das .hwcg_bit = 1, 14381c9efb0bSTaniya Das .clkr = { 14391c9efb0bSTaniya Das .enable_reg = 0x62000, 14401c9efb0bSTaniya Das .enable_mask = BIT(28), 14411c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 14421c9efb0bSTaniya Das .name = "gcc_pcie_0_cfg_ahb_clk", 14431c9efb0bSTaniya Das .ops = &clk_branch2_ops, 14441c9efb0bSTaniya Das }, 14451c9efb0bSTaniya Das }, 14461c9efb0bSTaniya Das }; 14471c9efb0bSTaniya Das 14481c9efb0bSTaniya Das static struct clk_branch gcc_pcie_0_clkref_en = { 14491c9efb0bSTaniya Das .halt_reg = 0x9c004, 14501c9efb0bSTaniya Das .halt_bit = 31, 14511c9efb0bSTaniya Das .halt_check = BRANCH_HALT_ENABLE, 14521c9efb0bSTaniya Das .clkr = { 14531c9efb0bSTaniya Das .enable_reg = 0x9c004, 14541c9efb0bSTaniya Das .enable_mask = BIT(0), 14551c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 14561c9efb0bSTaniya Das .name = "gcc_pcie_0_clkref_en", 14571c9efb0bSTaniya Das .ops = &clk_branch_ops, 14581c9efb0bSTaniya Das }, 14591c9efb0bSTaniya Das }, 14601c9efb0bSTaniya Das }; 14611c9efb0bSTaniya Das 14621c9efb0bSTaniya Das static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 14631c9efb0bSTaniya Das .halt_reg = 0x9d024, 14641c9efb0bSTaniya Das .halt_check = BRANCH_HALT_SKIP, 14651c9efb0bSTaniya Das .hwcg_reg = 0x9d024, 14661c9efb0bSTaniya Das .hwcg_bit = 1, 14671c9efb0bSTaniya Das .clkr = { 14681c9efb0bSTaniya Das .enable_reg = 0x62000, 14691c9efb0bSTaniya Das .enable_mask = BIT(27), 14701c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 14711c9efb0bSTaniya Das .name = "gcc_pcie_0_mstr_axi_clk", 14721c9efb0bSTaniya Das .ops = &clk_branch2_ops, 14731c9efb0bSTaniya Das }, 14741c9efb0bSTaniya Das }, 14751c9efb0bSTaniya Das }; 14761c9efb0bSTaniya Das 14771c9efb0bSTaniya Das static struct clk_branch gcc_pcie_0_phy_aux_clk = { 14781c9efb0bSTaniya Das .halt_reg = 0x9d038, 14791c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 14801c9efb0bSTaniya Das .hwcg_reg = 0x9d038, 14811c9efb0bSTaniya Das .hwcg_bit = 1, 14821c9efb0bSTaniya Das .clkr = { 14831c9efb0bSTaniya Das .enable_reg = 0x62000, 14841c9efb0bSTaniya Das .enable_mask = BIT(24), 14851c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 14861c9efb0bSTaniya Das .name = "gcc_pcie_0_phy_aux_clk", 14871c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 14881c9efb0bSTaniya Das &gcc_pcie_0_phy_aux_clk_src.clkr.hw, 14891c9efb0bSTaniya Das }, 14901c9efb0bSTaniya Das .num_parents = 1, 14911c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 14921c9efb0bSTaniya Das .ops = &clk_branch2_ops, 14931c9efb0bSTaniya Das }, 14941c9efb0bSTaniya Das }, 14951c9efb0bSTaniya Das }; 14961c9efb0bSTaniya Das 14971c9efb0bSTaniya Das static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 14981c9efb0bSTaniya Das .halt_reg = 0x9d048, 14991c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 15001c9efb0bSTaniya Das .hwcg_reg = 0x9d048, 15011c9efb0bSTaniya Das .hwcg_bit = 1, 15021c9efb0bSTaniya Das .clkr = { 15031c9efb0bSTaniya Das .enable_reg = 0x62000, 15041c9efb0bSTaniya Das .enable_mask = BIT(23), 15051c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 15061c9efb0bSTaniya Das .name = "gcc_pcie_0_phy_rchng_clk", 15071c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 15081c9efb0bSTaniya Das &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 15091c9efb0bSTaniya Das }, 15101c9efb0bSTaniya Das .num_parents = 1, 15111c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 15121c9efb0bSTaniya Das .ops = &clk_branch2_ops, 15131c9efb0bSTaniya Das }, 15141c9efb0bSTaniya Das }, 15151c9efb0bSTaniya Das }; 15161c9efb0bSTaniya Das 15171c9efb0bSTaniya Das static struct clk_branch gcc_pcie_0_pipe_clk = { 15181c9efb0bSTaniya Das .halt_reg = 0x9d040, 15191c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 15201c9efb0bSTaniya Das .hwcg_reg = 0x9d040, 15211c9efb0bSTaniya Das .hwcg_bit = 1, 15221c9efb0bSTaniya Das .clkr = { 15231c9efb0bSTaniya Das .enable_reg = 0x62000, 15241c9efb0bSTaniya Das .enable_mask = BIT(30), 15251c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 15261c9efb0bSTaniya Das .name = "gcc_pcie_0_pipe_clk", 15271c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 15281c9efb0bSTaniya Das &gcc_pcie_0_pipe_clk_src.clkr.hw, 15291c9efb0bSTaniya Das }, 15301c9efb0bSTaniya Das .num_parents = 1, 15311c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 15321c9efb0bSTaniya Das .ops = &clk_branch2_ops, 15331c9efb0bSTaniya Das }, 15341c9efb0bSTaniya Das }, 15351c9efb0bSTaniya Das }; 15361c9efb0bSTaniya Das 15371c9efb0bSTaniya Das static struct clk_branch gcc_pcie_0_slv_axi_clk = { 15381c9efb0bSTaniya Das .halt_reg = 0x9d01c, 15391c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 15401c9efb0bSTaniya Das .hwcg_reg = 0x9d01c, 15411c9efb0bSTaniya Das .hwcg_bit = 1, 15421c9efb0bSTaniya Das .clkr = { 15431c9efb0bSTaniya Das .enable_reg = 0x62000, 15441c9efb0bSTaniya Das .enable_mask = BIT(26), 15451c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 15461c9efb0bSTaniya Das .name = "gcc_pcie_0_slv_axi_clk", 15471c9efb0bSTaniya Das .ops = &clk_branch2_ops, 15481c9efb0bSTaniya Das }, 15491c9efb0bSTaniya Das }, 15501c9efb0bSTaniya Das }; 15511c9efb0bSTaniya Das 15521c9efb0bSTaniya Das static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 15531c9efb0bSTaniya Das .halt_reg = 0x9d018, 15541c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 15551c9efb0bSTaniya Das .hwcg_reg = 0x9d018, 15561c9efb0bSTaniya Das .hwcg_bit = 1, 15571c9efb0bSTaniya Das .clkr = { 15581c9efb0bSTaniya Das .enable_reg = 0x62000, 15591c9efb0bSTaniya Das .enable_mask = BIT(25), 15601c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 15611c9efb0bSTaniya Das .name = "gcc_pcie_0_slv_q2a_axi_clk", 15621c9efb0bSTaniya Das .ops = &clk_branch2_ops, 15631c9efb0bSTaniya Das }, 15641c9efb0bSTaniya Das }, 15651c9efb0bSTaniya Das }; 15661c9efb0bSTaniya Das 15671c9efb0bSTaniya Das static struct clk_branch gcc_pdm2_clk = { 15681c9efb0bSTaniya Das .halt_reg = 0x4300c, 15691c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 15701c9efb0bSTaniya Das .clkr = { 15711c9efb0bSTaniya Das .enable_reg = 0x4300c, 15721c9efb0bSTaniya Das .enable_mask = BIT(0), 15731c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 15741c9efb0bSTaniya Das .name = "gcc_pdm2_clk", 15751c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 15761c9efb0bSTaniya Das &gcc_pdm2_clk_src.clkr.hw, 15771c9efb0bSTaniya Das }, 15781c9efb0bSTaniya Das .num_parents = 1, 15791c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 15801c9efb0bSTaniya Das .ops = &clk_branch2_ops, 15811c9efb0bSTaniya Das }, 15821c9efb0bSTaniya Das }, 15831c9efb0bSTaniya Das }; 15841c9efb0bSTaniya Das 15851c9efb0bSTaniya Das static struct clk_branch gcc_pdm_ahb_clk = { 15861c9efb0bSTaniya Das .halt_reg = 0x43004, 15871c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 15881c9efb0bSTaniya Das .hwcg_reg = 0x43004, 15891c9efb0bSTaniya Das .hwcg_bit = 1, 15901c9efb0bSTaniya Das .clkr = { 15911c9efb0bSTaniya Das .enable_reg = 0x43004, 15921c9efb0bSTaniya Das .enable_mask = BIT(0), 15931c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 15941c9efb0bSTaniya Das .name = "gcc_pdm_ahb_clk", 15951c9efb0bSTaniya Das .ops = &clk_branch2_ops, 15961c9efb0bSTaniya Das }, 15971c9efb0bSTaniya Das }, 15981c9efb0bSTaniya Das }; 15991c9efb0bSTaniya Das 16001c9efb0bSTaniya Das static struct clk_branch gcc_pdm_xo4_clk = { 16011c9efb0bSTaniya Das .halt_reg = 0x43008, 16021c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 16031c9efb0bSTaniya Das .clkr = { 16041c9efb0bSTaniya Das .enable_reg = 0x43008, 16051c9efb0bSTaniya Das .enable_mask = BIT(0), 16061c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 16071c9efb0bSTaniya Das .name = "gcc_pdm_xo4_clk", 16081c9efb0bSTaniya Das .ops = &clk_branch2_ops, 16091c9efb0bSTaniya Das }, 16101c9efb0bSTaniya Das }, 16111c9efb0bSTaniya Das }; 16121c9efb0bSTaniya Das 16131c9efb0bSTaniya Das static struct clk_branch gcc_qmip_anoc_pcie_clk = { 16141c9efb0bSTaniya Das .halt_reg = 0x84044, 16151c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 16161c9efb0bSTaniya Das .hwcg_reg = 0x84044, 16171c9efb0bSTaniya Das .hwcg_bit = 1, 16181c9efb0bSTaniya Das .clkr = { 16191c9efb0bSTaniya Das .enable_reg = 0x84044, 16201c9efb0bSTaniya Das .enable_mask = BIT(0), 16211c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 16221c9efb0bSTaniya Das .name = "gcc_qmip_anoc_pcie_clk", 16231c9efb0bSTaniya Das .ops = &clk_branch2_ops, 16241c9efb0bSTaniya Das }, 16251c9efb0bSTaniya Das }, 16261c9efb0bSTaniya Das }; 16271c9efb0bSTaniya Das 16281c9efb0bSTaniya Das static struct clk_branch gcc_qmip_ecpri_dma0_clk = { 16291c9efb0bSTaniya Das .halt_reg = 0x84038, 16301c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 16311c9efb0bSTaniya Das .hwcg_reg = 0x84038, 16321c9efb0bSTaniya Das .hwcg_bit = 1, 16331c9efb0bSTaniya Das .clkr = { 16341c9efb0bSTaniya Das .enable_reg = 0x84038, 16351c9efb0bSTaniya Das .enable_mask = BIT(0), 16361c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 16371c9efb0bSTaniya Das .name = "gcc_qmip_ecpri_dma0_clk", 16381c9efb0bSTaniya Das .ops = &clk_branch2_ops, 16391c9efb0bSTaniya Das }, 16401c9efb0bSTaniya Das }, 16411c9efb0bSTaniya Das }; 16421c9efb0bSTaniya Das 16431c9efb0bSTaniya Das static struct clk_branch gcc_qmip_ecpri_dma1_clk = { 16441c9efb0bSTaniya Das .halt_reg = 0x8403c, 16451c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 16461c9efb0bSTaniya Das .hwcg_reg = 0x8403c, 16471c9efb0bSTaniya Das .hwcg_bit = 1, 16481c9efb0bSTaniya Das .clkr = { 16491c9efb0bSTaniya Das .enable_reg = 0x8403c, 16501c9efb0bSTaniya Das .enable_mask = BIT(0), 16511c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 16521c9efb0bSTaniya Das .name = "gcc_qmip_ecpri_dma1_clk", 16531c9efb0bSTaniya Das .ops = &clk_branch2_ops, 16541c9efb0bSTaniya Das }, 16551c9efb0bSTaniya Das }, 16561c9efb0bSTaniya Das }; 16571c9efb0bSTaniya Das 16581c9efb0bSTaniya Das static struct clk_branch gcc_qmip_ecpri_gsi_clk = { 16591c9efb0bSTaniya Das .halt_reg = 0x84040, 16601c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 16611c9efb0bSTaniya Das .hwcg_reg = 0x84040, 16621c9efb0bSTaniya Das .hwcg_bit = 1, 16631c9efb0bSTaniya Das .clkr = { 16641c9efb0bSTaniya Das .enable_reg = 0x84040, 16651c9efb0bSTaniya Das .enable_mask = BIT(0), 16661c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 16671c9efb0bSTaniya Das .name = "gcc_qmip_ecpri_gsi_clk", 16681c9efb0bSTaniya Das .ops = &clk_branch2_ops, 16691c9efb0bSTaniya Das }, 16701c9efb0bSTaniya Das }, 16711c9efb0bSTaniya Das }; 16721c9efb0bSTaniya Das 16731c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 16741c9efb0bSTaniya Das .halt_reg = 0x27018, 16751c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 16761c9efb0bSTaniya Das .clkr = { 16771c9efb0bSTaniya Das .enable_reg = 0x62008, 16781c9efb0bSTaniya Das .enable_mask = BIT(9), 16791c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 16801c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_core_2x_clk", 16811c9efb0bSTaniya Das .ops = &clk_branch2_ops, 16821c9efb0bSTaniya Das }, 16831c9efb0bSTaniya Das }, 16841c9efb0bSTaniya Das }; 16851c9efb0bSTaniya Das 16861c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap0_core_clk = { 16871c9efb0bSTaniya Das .halt_reg = 0x2700c, 16881c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 16891c9efb0bSTaniya Das .clkr = { 16901c9efb0bSTaniya Das .enable_reg = 0x62008, 16911c9efb0bSTaniya Das .enable_mask = BIT(8), 16921c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 16931c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_core_clk", 16941c9efb0bSTaniya Das .ops = &clk_branch2_ops, 16951c9efb0bSTaniya Das }, 16961c9efb0bSTaniya Das }, 16971c9efb0bSTaniya Das }; 16981c9efb0bSTaniya Das 16991c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 17001c9efb0bSTaniya Das .halt_reg = 0x2714c, 17011c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 17021c9efb0bSTaniya Das .clkr = { 17031c9efb0bSTaniya Das .enable_reg = 0x62008, 17041c9efb0bSTaniya Das .enable_mask = BIT(10), 17051c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 17061c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s0_clk", 17071c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 17081c9efb0bSTaniya Das &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 17091c9efb0bSTaniya Das }, 17101c9efb0bSTaniya Das .num_parents = 1, 17111c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 17121c9efb0bSTaniya Das .ops = &clk_branch2_ops, 17131c9efb0bSTaniya Das }, 17141c9efb0bSTaniya Das }, 17151c9efb0bSTaniya Das }; 17161c9efb0bSTaniya Das 17171c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 17181c9efb0bSTaniya Das .halt_reg = 0x27280, 17191c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 17201c9efb0bSTaniya Das .clkr = { 17211c9efb0bSTaniya Das .enable_reg = 0x62008, 17221c9efb0bSTaniya Das .enable_mask = BIT(11), 17231c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 17241c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s1_clk", 17251c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 17261c9efb0bSTaniya Das &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 17271c9efb0bSTaniya Das }, 17281c9efb0bSTaniya Das .num_parents = 1, 17291c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 17301c9efb0bSTaniya Das .ops = &clk_branch2_ops, 17311c9efb0bSTaniya Das }, 17321c9efb0bSTaniya Das }, 17331c9efb0bSTaniya Das }; 17341c9efb0bSTaniya Das 17351c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 17361c9efb0bSTaniya Das .halt_reg = 0x273b4, 17371c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 17381c9efb0bSTaniya Das .clkr = { 17391c9efb0bSTaniya Das .enable_reg = 0x62008, 17401c9efb0bSTaniya Das .enable_mask = BIT(12), 17411c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 17421c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s2_clk", 17431c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 17441c9efb0bSTaniya Das &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 17451c9efb0bSTaniya Das }, 17461c9efb0bSTaniya Das .num_parents = 1, 17471c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 17481c9efb0bSTaniya Das .ops = &clk_branch2_ops, 17491c9efb0bSTaniya Das }, 17501c9efb0bSTaniya Das }, 17511c9efb0bSTaniya Das }; 17521c9efb0bSTaniya Das 17531c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 17541c9efb0bSTaniya Das .halt_reg = 0x274e8, 17551c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 17561c9efb0bSTaniya Das .clkr = { 17571c9efb0bSTaniya Das .enable_reg = 0x62008, 17581c9efb0bSTaniya Das .enable_mask = BIT(13), 17591c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 17601c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s3_clk", 17611c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 17621c9efb0bSTaniya Das &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 17631c9efb0bSTaniya Das }, 17641c9efb0bSTaniya Das .num_parents = 1, 17651c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 17661c9efb0bSTaniya Das .ops = &clk_branch2_ops, 17671c9efb0bSTaniya Das }, 17681c9efb0bSTaniya Das }, 17691c9efb0bSTaniya Das }; 17701c9efb0bSTaniya Das 17711c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 17721c9efb0bSTaniya Das .halt_reg = 0x2761c, 17731c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 17741c9efb0bSTaniya Das .clkr = { 17751c9efb0bSTaniya Das .enable_reg = 0x62008, 17761c9efb0bSTaniya Das .enable_mask = BIT(14), 17771c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 17781c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s4_clk", 17791c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 17801c9efb0bSTaniya Das &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 17811c9efb0bSTaniya Das }, 17821c9efb0bSTaniya Das .num_parents = 1, 17831c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 17841c9efb0bSTaniya Das .ops = &clk_branch2_ops, 17851c9efb0bSTaniya Das }, 17861c9efb0bSTaniya Das }, 17871c9efb0bSTaniya Das }; 17881c9efb0bSTaniya Das 17891c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 17901c9efb0bSTaniya Das .halt_reg = 0x27750, 17911c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 17921c9efb0bSTaniya Das .clkr = { 17931c9efb0bSTaniya Das .enable_reg = 0x62008, 17941c9efb0bSTaniya Das .enable_mask = BIT(15), 17951c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 17961c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s5_clk", 17971c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 17981c9efb0bSTaniya Das &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 17991c9efb0bSTaniya Das }, 18001c9efb0bSTaniya Das .num_parents = 1, 18011c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 18021c9efb0bSTaniya Das .ops = &clk_branch2_ops, 18031c9efb0bSTaniya Das }, 18041c9efb0bSTaniya Das }, 18051c9efb0bSTaniya Das }; 18061c9efb0bSTaniya Das 18071c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 18081c9efb0bSTaniya Das .halt_reg = 0x27884, 18091c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 18101c9efb0bSTaniya Das .clkr = { 18111c9efb0bSTaniya Das .enable_reg = 0x62008, 18121c9efb0bSTaniya Das .enable_mask = BIT(16), 18131c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 18141c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s6_clk", 18151c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 18161c9efb0bSTaniya Das &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 18171c9efb0bSTaniya Das }, 18181c9efb0bSTaniya Das .num_parents = 1, 18191c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 18201c9efb0bSTaniya Das .ops = &clk_branch2_ops, 18211c9efb0bSTaniya Das }, 18221c9efb0bSTaniya Das }, 18231c9efb0bSTaniya Das }; 18241c9efb0bSTaniya Das 18251c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 18261c9efb0bSTaniya Das .halt_reg = 0x279b8, 18271c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 18281c9efb0bSTaniya Das .clkr = { 18291c9efb0bSTaniya Das .enable_reg = 0x62008, 18301c9efb0bSTaniya Das .enable_mask = BIT(17), 18311c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 18321c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s7_clk", 18331c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 18341c9efb0bSTaniya Das &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 18351c9efb0bSTaniya Das }, 18361c9efb0bSTaniya Das .num_parents = 1, 18371c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 18381c9efb0bSTaniya Das .ops = &clk_branch2_ops, 18391c9efb0bSTaniya Das }, 18401c9efb0bSTaniya Das }, 18411c9efb0bSTaniya Das }; 18421c9efb0bSTaniya Das 18431c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 18441c9efb0bSTaniya Das .halt_reg = 0x28018, 18451c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 18461c9efb0bSTaniya Das .clkr = { 18471c9efb0bSTaniya Das .enable_reg = 0x62008, 18481c9efb0bSTaniya Das .enable_mask = BIT(18), 18491c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 18501c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_core_2x_clk", 18511c9efb0bSTaniya Das .ops = &clk_branch2_ops, 18521c9efb0bSTaniya Das }, 18531c9efb0bSTaniya Das }, 18541c9efb0bSTaniya Das }; 18551c9efb0bSTaniya Das 18561c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap1_core_clk = { 18571c9efb0bSTaniya Das .halt_reg = 0x2800c, 18581c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 18591c9efb0bSTaniya Das .clkr = { 18601c9efb0bSTaniya Das .enable_reg = 0x62008, 18611c9efb0bSTaniya Das .enable_mask = BIT(19), 18621c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 18631c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_core_clk", 18641c9efb0bSTaniya Das .ops = &clk_branch2_ops, 18651c9efb0bSTaniya Das }, 18661c9efb0bSTaniya Das }, 18671c9efb0bSTaniya Das }; 18681c9efb0bSTaniya Das 18691c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 18701c9efb0bSTaniya Das .halt_reg = 0x2814c, 18711c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 18721c9efb0bSTaniya Das .clkr = { 18731c9efb0bSTaniya Das .enable_reg = 0x62008, 18741c9efb0bSTaniya Das .enable_mask = BIT(22), 18751c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 18761c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s0_clk", 18771c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 18781c9efb0bSTaniya Das &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 18791c9efb0bSTaniya Das }, 18801c9efb0bSTaniya Das .num_parents = 1, 18811c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 18821c9efb0bSTaniya Das .ops = &clk_branch2_ops, 18831c9efb0bSTaniya Das }, 18841c9efb0bSTaniya Das }, 18851c9efb0bSTaniya Das }; 18861c9efb0bSTaniya Das 18871c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 18881c9efb0bSTaniya Das .halt_reg = 0x28280, 18891c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 18901c9efb0bSTaniya Das .clkr = { 18911c9efb0bSTaniya Das .enable_reg = 0x62008, 18921c9efb0bSTaniya Das .enable_mask = BIT(23), 18931c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 18941c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s1_clk", 18951c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 18961c9efb0bSTaniya Das &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 18971c9efb0bSTaniya Das }, 18981c9efb0bSTaniya Das .num_parents = 1, 18991c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 19001c9efb0bSTaniya Das .ops = &clk_branch2_ops, 19011c9efb0bSTaniya Das }, 19021c9efb0bSTaniya Das }, 19031c9efb0bSTaniya Das }; 19041c9efb0bSTaniya Das 19051c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 19061c9efb0bSTaniya Das .halt_reg = 0x283b4, 19071c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 19081c9efb0bSTaniya Das .clkr = { 19091c9efb0bSTaniya Das .enable_reg = 0x62008, 19101c9efb0bSTaniya Das .enable_mask = BIT(24), 19111c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 19121c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s2_clk", 19131c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 19141c9efb0bSTaniya Das &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 19151c9efb0bSTaniya Das }, 19161c9efb0bSTaniya Das .num_parents = 1, 19171c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 19181c9efb0bSTaniya Das .ops = &clk_branch2_ops, 19191c9efb0bSTaniya Das }, 19201c9efb0bSTaniya Das }, 19211c9efb0bSTaniya Das }; 19221c9efb0bSTaniya Das 19231c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 19241c9efb0bSTaniya Das .halt_reg = 0x284e8, 19251c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 19261c9efb0bSTaniya Das .clkr = { 19271c9efb0bSTaniya Das .enable_reg = 0x62008, 19281c9efb0bSTaniya Das .enable_mask = BIT(25), 19291c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 19301c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s3_clk", 19311c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 19321c9efb0bSTaniya Das &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 19331c9efb0bSTaniya Das }, 19341c9efb0bSTaniya Das .num_parents = 1, 19351c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 19361c9efb0bSTaniya Das .ops = &clk_branch2_ops, 19371c9efb0bSTaniya Das }, 19381c9efb0bSTaniya Das }, 19391c9efb0bSTaniya Das }; 19401c9efb0bSTaniya Das 19411c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 19421c9efb0bSTaniya Das .halt_reg = 0x2861c, 19431c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 19441c9efb0bSTaniya Das .clkr = { 19451c9efb0bSTaniya Das .enable_reg = 0x62008, 19461c9efb0bSTaniya Das .enable_mask = BIT(26), 19471c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 19481c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s4_clk", 19491c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 19501c9efb0bSTaniya Das &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 19511c9efb0bSTaniya Das }, 19521c9efb0bSTaniya Das .num_parents = 1, 19531c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 19541c9efb0bSTaniya Das .ops = &clk_branch2_ops, 19551c9efb0bSTaniya Das }, 19561c9efb0bSTaniya Das }, 19571c9efb0bSTaniya Das }; 19581c9efb0bSTaniya Das 19591c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 19601c9efb0bSTaniya Das .halt_reg = 0x28750, 19611c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 19621c9efb0bSTaniya Das .clkr = { 19631c9efb0bSTaniya Das .enable_reg = 0x62008, 19641c9efb0bSTaniya Das .enable_mask = BIT(27), 19651c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 19661c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s5_clk", 19671c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 19681c9efb0bSTaniya Das &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 19691c9efb0bSTaniya Das }, 19701c9efb0bSTaniya Das .num_parents = 1, 19711c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 19721c9efb0bSTaniya Das .ops = &clk_branch2_ops, 19731c9efb0bSTaniya Das }, 19741c9efb0bSTaniya Das }, 19751c9efb0bSTaniya Das }; 19761c9efb0bSTaniya Das 19771c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 19781c9efb0bSTaniya Das .halt_reg = 0x28884, 19791c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 19801c9efb0bSTaniya Das .clkr = { 19811c9efb0bSTaniya Das .enable_reg = 0x62008, 19821c9efb0bSTaniya Das .enable_mask = BIT(28), 19831c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 19841c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s6_clk", 19851c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 19861c9efb0bSTaniya Das &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 19871c9efb0bSTaniya Das }, 19881c9efb0bSTaniya Das .num_parents = 1, 19891c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 19901c9efb0bSTaniya Das .ops = &clk_branch2_ops, 19911c9efb0bSTaniya Das }, 19921c9efb0bSTaniya Das }, 19931c9efb0bSTaniya Das }; 19941c9efb0bSTaniya Das 19951c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 19961c9efb0bSTaniya Das .halt_reg = 0x289b8, 19971c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 19981c9efb0bSTaniya Das .clkr = { 19991c9efb0bSTaniya Das .enable_reg = 0x62008, 20001c9efb0bSTaniya Das .enable_mask = BIT(29), 20011c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 20021c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s7_clk", 20031c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 20041c9efb0bSTaniya Das &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 20051c9efb0bSTaniya Das }, 20061c9efb0bSTaniya Das .num_parents = 1, 20071c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 20081c9efb0bSTaniya Das .ops = &clk_branch2_ops, 20091c9efb0bSTaniya Das }, 20101c9efb0bSTaniya Das }, 20111c9efb0bSTaniya Das }; 20121c9efb0bSTaniya Das 20131c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 20141c9efb0bSTaniya Das .halt_reg = 0x27004, 20151c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 20161c9efb0bSTaniya Das .hwcg_reg = 0x27004, 20171c9efb0bSTaniya Das .hwcg_bit = 1, 20181c9efb0bSTaniya Das .clkr = { 20191c9efb0bSTaniya Das .enable_reg = 0x62008, 20201c9efb0bSTaniya Das .enable_mask = BIT(6), 20211c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 20221c9efb0bSTaniya Das .name = "gcc_qupv3_wrap_0_m_ahb_clk", 20231c9efb0bSTaniya Das .ops = &clk_branch2_ops, 20241c9efb0bSTaniya Das }, 20251c9efb0bSTaniya Das }, 20261c9efb0bSTaniya Das }; 20271c9efb0bSTaniya Das 20281c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 20291c9efb0bSTaniya Das .halt_reg = 0x27008, 20301c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 20311c9efb0bSTaniya Das .hwcg_reg = 0x27008, 20321c9efb0bSTaniya Das .hwcg_bit = 1, 20331c9efb0bSTaniya Das .clkr = { 20341c9efb0bSTaniya Das .enable_reg = 0x62008, 20351c9efb0bSTaniya Das .enable_mask = BIT(7), 20361c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 20371c9efb0bSTaniya Das .name = "gcc_qupv3_wrap_0_s_ahb_clk", 20381c9efb0bSTaniya Das .ops = &clk_branch2_ops, 20391c9efb0bSTaniya Das }, 20401c9efb0bSTaniya Das }, 20411c9efb0bSTaniya Das }; 20421c9efb0bSTaniya Das 20431c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 20441c9efb0bSTaniya Das .halt_reg = 0x28004, 20451c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 20461c9efb0bSTaniya Das .hwcg_reg = 0x28004, 20471c9efb0bSTaniya Das .hwcg_bit = 1, 20481c9efb0bSTaniya Das .clkr = { 20491c9efb0bSTaniya Das .enable_reg = 0x62008, 20501c9efb0bSTaniya Das .enable_mask = BIT(20), 20511c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 20521c9efb0bSTaniya Das .name = "gcc_qupv3_wrap_1_m_ahb_clk", 20531c9efb0bSTaniya Das .ops = &clk_branch2_ops, 20541c9efb0bSTaniya Das }, 20551c9efb0bSTaniya Das }, 20561c9efb0bSTaniya Das }; 20571c9efb0bSTaniya Das 20581c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 20591c9efb0bSTaniya Das .halt_reg = 0x28008, 20601c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 20611c9efb0bSTaniya Das .hwcg_reg = 0x28008, 20621c9efb0bSTaniya Das .hwcg_bit = 1, 20631c9efb0bSTaniya Das .clkr = { 20641c9efb0bSTaniya Das .enable_reg = 0x62008, 20651c9efb0bSTaniya Das .enable_mask = BIT(21), 20661c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 20671c9efb0bSTaniya Das .name = "gcc_qupv3_wrap_1_s_ahb_clk", 20681c9efb0bSTaniya Das .ops = &clk_branch2_ops, 20691c9efb0bSTaniya Das }, 20701c9efb0bSTaniya Das }, 20711c9efb0bSTaniya Das }; 20721c9efb0bSTaniya Das 20731c9efb0bSTaniya Das static struct clk_branch gcc_sdcc5_ahb_clk = { 20741c9efb0bSTaniya Das .halt_reg = 0x3b00c, 20751c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 20761c9efb0bSTaniya Das .clkr = { 20771c9efb0bSTaniya Das .enable_reg = 0x3b00c, 20781c9efb0bSTaniya Das .enable_mask = BIT(0), 20791c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 20801c9efb0bSTaniya Das .name = "gcc_sdcc5_ahb_clk", 20811c9efb0bSTaniya Das .ops = &clk_branch2_ops, 20821c9efb0bSTaniya Das }, 20831c9efb0bSTaniya Das }, 20841c9efb0bSTaniya Das }; 20851c9efb0bSTaniya Das 20861c9efb0bSTaniya Das static struct clk_branch gcc_sdcc5_apps_clk = { 20871c9efb0bSTaniya Das .halt_reg = 0x3b004, 20881c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 20891c9efb0bSTaniya Das .clkr = { 20901c9efb0bSTaniya Das .enable_reg = 0x3b004, 20911c9efb0bSTaniya Das .enable_mask = BIT(0), 20921c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 20931c9efb0bSTaniya Das .name = "gcc_sdcc5_apps_clk", 20941c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 20951c9efb0bSTaniya Das &gcc_sdcc5_apps_clk_src.clkr.hw, 20961c9efb0bSTaniya Das }, 20971c9efb0bSTaniya Das .num_parents = 1, 20981c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 20991c9efb0bSTaniya Das .ops = &clk_branch2_ops, 21001c9efb0bSTaniya Das }, 21011c9efb0bSTaniya Das }, 21021c9efb0bSTaniya Das }; 21031c9efb0bSTaniya Das 21041c9efb0bSTaniya Das static struct clk_branch gcc_sdcc5_ice_core_clk = { 21051c9efb0bSTaniya Das .halt_reg = 0x3b010, 21061c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 21071c9efb0bSTaniya Das .clkr = { 21081c9efb0bSTaniya Das .enable_reg = 0x3b010, 21091c9efb0bSTaniya Das .enable_mask = BIT(0), 21101c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 21111c9efb0bSTaniya Das .name = "gcc_sdcc5_ice_core_clk", 21121c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 21131c9efb0bSTaniya Das &gcc_sdcc5_ice_core_clk_src.clkr.hw, 21141c9efb0bSTaniya Das }, 21151c9efb0bSTaniya Das .num_parents = 1, 21161c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 21171c9efb0bSTaniya Das .ops = &clk_branch2_ops, 21181c9efb0bSTaniya Das }, 21191c9efb0bSTaniya Das }, 21201c9efb0bSTaniya Das }; 21211c9efb0bSTaniya Das 21221c9efb0bSTaniya Das static struct clk_branch gcc_sm_bus_ahb_clk = { 21231c9efb0bSTaniya Das .halt_reg = 0x5b004, 21241c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 21251c9efb0bSTaniya Das .clkr = { 21261c9efb0bSTaniya Das .enable_reg = 0x5b004, 21271c9efb0bSTaniya Das .enable_mask = BIT(0), 21281c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 21291c9efb0bSTaniya Das .name = "gcc_sm_bus_ahb_clk", 21301c9efb0bSTaniya Das .ops = &clk_branch2_ops, 21311c9efb0bSTaniya Das }, 21321c9efb0bSTaniya Das }, 21331c9efb0bSTaniya Das }; 21341c9efb0bSTaniya Das 21351c9efb0bSTaniya Das static struct clk_branch gcc_sm_bus_xo_clk = { 21361c9efb0bSTaniya Das .halt_reg = 0x5b008, 21371c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 21381c9efb0bSTaniya Das .clkr = { 21391c9efb0bSTaniya Das .enable_reg = 0x5b008, 21401c9efb0bSTaniya Das .enable_mask = BIT(0), 21411c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 21421c9efb0bSTaniya Das .name = "gcc_sm_bus_xo_clk", 21431c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 21441c9efb0bSTaniya Das &gcc_sm_bus_xo_clk_src.clkr.hw, 21451c9efb0bSTaniya Das }, 21461c9efb0bSTaniya Das .num_parents = 1, 21471c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 21481c9efb0bSTaniya Das .ops = &clk_branch2_ops, 21491c9efb0bSTaniya Das }, 21501c9efb0bSTaniya Das }, 21511c9efb0bSTaniya Das }; 21521c9efb0bSTaniya Das 21531c9efb0bSTaniya Das static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_qx_clk = { 21541c9efb0bSTaniya Das .halt_reg = 0x9200c, 21551c9efb0bSTaniya Das .halt_check = BRANCH_HALT_SKIP, 21561c9efb0bSTaniya Das .hwcg_reg = 0x9200c, 21571c9efb0bSTaniya Das .hwcg_bit = 1, 21581c9efb0bSTaniya Das .clkr = { 21591c9efb0bSTaniya Das .enable_reg = 0x62000, 21601c9efb0bSTaniya Das .enable_mask = BIT(11), 21611c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 21621c9efb0bSTaniya Das .name = "gcc_snoc_cnoc_gemnoc_pcie_qx_clk", 21631c9efb0bSTaniya Das .ops = &clk_branch2_ops, 21641c9efb0bSTaniya Das }, 21651c9efb0bSTaniya Das }, 21661c9efb0bSTaniya Das }; 21671c9efb0bSTaniya Das 21681c9efb0bSTaniya Das static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk = { 21691c9efb0bSTaniya Das .halt_reg = 0x92010, 21701c9efb0bSTaniya Das .halt_check = BRANCH_HALT_SKIP, 21711c9efb0bSTaniya Das .hwcg_reg = 0x92010, 21721c9efb0bSTaniya Das .hwcg_bit = 1, 21731c9efb0bSTaniya Das .clkr = { 21741c9efb0bSTaniya Das .enable_reg = 0x62000, 21751c9efb0bSTaniya Das .enable_mask = BIT(12), 21761c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 21771c9efb0bSTaniya Das .name = "gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk", 21781c9efb0bSTaniya Das .ops = &clk_branch2_ops, 21791c9efb0bSTaniya Das }, 21801c9efb0bSTaniya Das }, 21811c9efb0bSTaniya Das }; 21821c9efb0bSTaniya Das 21831c9efb0bSTaniya Das static struct clk_branch gcc_snoc_cnoc_pcie_qx_clk = { 21841c9efb0bSTaniya Das .halt_reg = 0x84030, 21851c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 21861c9efb0bSTaniya Das .clkr = { 21871c9efb0bSTaniya Das .enable_reg = 0x84030, 21881c9efb0bSTaniya Das .enable_mask = BIT(0), 21891c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 21901c9efb0bSTaniya Das .name = "gcc_snoc_cnoc_pcie_qx_clk", 21911c9efb0bSTaniya Das .ops = &clk_branch2_ops, 21921c9efb0bSTaniya Das }, 21931c9efb0bSTaniya Das }, 21941c9efb0bSTaniya Das }; 21951c9efb0bSTaniya Das 21961c9efb0bSTaniya Das static struct clk_branch gcc_snoc_pcie_sf_center_qx_clk = { 21971c9efb0bSTaniya Das .halt_reg = 0x92014, 21981c9efb0bSTaniya Das .halt_check = BRANCH_HALT_SKIP, 21991c9efb0bSTaniya Das .hwcg_reg = 0x92014, 22001c9efb0bSTaniya Das .hwcg_bit = 1, 22011c9efb0bSTaniya Das .clkr = { 22021c9efb0bSTaniya Das .enable_reg = 0x62000, 22031c9efb0bSTaniya Das .enable_mask = BIT(19), 22041c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 22051c9efb0bSTaniya Das .name = "gcc_snoc_pcie_sf_center_qx_clk", 22061c9efb0bSTaniya Das .ops = &clk_branch2_ops, 22071c9efb0bSTaniya Das }, 22081c9efb0bSTaniya Das }, 22091c9efb0bSTaniya Das }; 22101c9efb0bSTaniya Das 22111c9efb0bSTaniya Das static struct clk_branch gcc_snoc_pcie_sf_south_qx_clk = { 22121c9efb0bSTaniya Das .halt_reg = 0x92018, 22131c9efb0bSTaniya Das .halt_check = BRANCH_HALT_SKIP, 22141c9efb0bSTaniya Das .hwcg_reg = 0x92018, 22151c9efb0bSTaniya Das .hwcg_bit = 1, 22161c9efb0bSTaniya Das .clkr = { 22171c9efb0bSTaniya Das .enable_reg = 0x62000, 22181c9efb0bSTaniya Das .enable_mask = BIT(22), 22191c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 22201c9efb0bSTaniya Das .name = "gcc_snoc_pcie_sf_south_qx_clk", 22211c9efb0bSTaniya Das .ops = &clk_branch2_ops, 22221c9efb0bSTaniya Das }, 22231c9efb0bSTaniya Das }, 22241c9efb0bSTaniya Das }; 22251c9efb0bSTaniya Das 22261c9efb0bSTaniya Das static struct clk_branch gcc_tsc_cfg_ahb_clk = { 22271c9efb0bSTaniya Das .halt_reg = 0x5700c, 22281c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 22291c9efb0bSTaniya Das .clkr = { 22301c9efb0bSTaniya Das .enable_reg = 0x5700c, 22311c9efb0bSTaniya Das .enable_mask = BIT(0), 22321c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 22331c9efb0bSTaniya Das .name = "gcc_tsc_cfg_ahb_clk", 22341c9efb0bSTaniya Das .ops = &clk_branch2_ops, 22351c9efb0bSTaniya Das }, 22361c9efb0bSTaniya Das }, 22371c9efb0bSTaniya Das }; 22381c9efb0bSTaniya Das 22391c9efb0bSTaniya Das static struct clk_branch gcc_tsc_cntr_clk = { 22401c9efb0bSTaniya Das .halt_reg = 0x57004, 22411c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 22421c9efb0bSTaniya Das .clkr = { 22431c9efb0bSTaniya Das .enable_reg = 0x57004, 22441c9efb0bSTaniya Das .enable_mask = BIT(0), 22451c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 22461c9efb0bSTaniya Das .name = "gcc_tsc_cntr_clk", 22471c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 22481c9efb0bSTaniya Das &gcc_tsc_clk_src.clkr.hw, 22491c9efb0bSTaniya Das }, 22501c9efb0bSTaniya Das .num_parents = 1, 22511c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 22521c9efb0bSTaniya Das .ops = &clk_branch2_ops, 22531c9efb0bSTaniya Das }, 22541c9efb0bSTaniya Das }, 22551c9efb0bSTaniya Das }; 22561c9efb0bSTaniya Das 22571c9efb0bSTaniya Das static struct clk_branch gcc_tsc_etu_clk = { 22581c9efb0bSTaniya Das .halt_reg = 0x57008, 22591c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 22601c9efb0bSTaniya Das .clkr = { 22611c9efb0bSTaniya Das .enable_reg = 0x57008, 22621c9efb0bSTaniya Das .enable_mask = BIT(0), 22631c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 22641c9efb0bSTaniya Das .name = "gcc_tsc_etu_clk", 22651c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 22661c9efb0bSTaniya Das &gcc_tsc_clk_src.clkr.hw, 22671c9efb0bSTaniya Das }, 22681c9efb0bSTaniya Das .num_parents = 1, 22691c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 22701c9efb0bSTaniya Das .ops = &clk_branch2_ops, 22711c9efb0bSTaniya Das }, 22721c9efb0bSTaniya Das }, 22731c9efb0bSTaniya Das }; 22741c9efb0bSTaniya Das 22751c9efb0bSTaniya Das static struct clk_branch gcc_usb2_clkref_en = { 22761c9efb0bSTaniya Das .halt_reg = 0x9c008, 22771c9efb0bSTaniya Das .halt_bit = 31, 22781c9efb0bSTaniya Das .halt_check = BRANCH_HALT_ENABLE, 22791c9efb0bSTaniya Das .clkr = { 22801c9efb0bSTaniya Das .enable_reg = 0x9c008, 22811c9efb0bSTaniya Das .enable_mask = BIT(0), 22821c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 22831c9efb0bSTaniya Das .name = "gcc_usb2_clkref_en", 22841c9efb0bSTaniya Das .ops = &clk_branch_ops, 22851c9efb0bSTaniya Das }, 22861c9efb0bSTaniya Das }, 22871c9efb0bSTaniya Das }; 22881c9efb0bSTaniya Das 22891c9efb0bSTaniya Das static struct clk_branch gcc_usb30_prim_master_clk = { 22901c9efb0bSTaniya Das .halt_reg = 0x49018, 22911c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 22921c9efb0bSTaniya Das .clkr = { 22931c9efb0bSTaniya Das .enable_reg = 0x49018, 22941c9efb0bSTaniya Das .enable_mask = BIT(0), 22951c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 22961c9efb0bSTaniya Das .name = "gcc_usb30_prim_master_clk", 22971c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 22981c9efb0bSTaniya Das &gcc_usb30_prim_master_clk_src.clkr.hw, 22991c9efb0bSTaniya Das }, 23001c9efb0bSTaniya Das .num_parents = 1, 23011c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 23021c9efb0bSTaniya Das .ops = &clk_branch2_ops, 23031c9efb0bSTaniya Das }, 23041c9efb0bSTaniya Das }, 23051c9efb0bSTaniya Das }; 23061c9efb0bSTaniya Das 23071c9efb0bSTaniya Das static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 23081c9efb0bSTaniya Das .halt_reg = 0x49024, 23091c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 23101c9efb0bSTaniya Das .clkr = { 23111c9efb0bSTaniya Das .enable_reg = 0x49024, 23121c9efb0bSTaniya Das .enable_mask = BIT(0), 23131c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 23141c9efb0bSTaniya Das .name = "gcc_usb30_prim_mock_utmi_clk", 23151c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 23161c9efb0bSTaniya Das &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 23171c9efb0bSTaniya Das }, 23181c9efb0bSTaniya Das .num_parents = 1, 23191c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 23201c9efb0bSTaniya Das .ops = &clk_branch2_ops, 23211c9efb0bSTaniya Das }, 23221c9efb0bSTaniya Das }, 23231c9efb0bSTaniya Das }; 23241c9efb0bSTaniya Das 23251c9efb0bSTaniya Das static struct clk_branch gcc_usb30_prim_sleep_clk = { 23261c9efb0bSTaniya Das .halt_reg = 0x49020, 23271c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 23281c9efb0bSTaniya Das .clkr = { 23291c9efb0bSTaniya Das .enable_reg = 0x49020, 23301c9efb0bSTaniya Das .enable_mask = BIT(0), 23311c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 23321c9efb0bSTaniya Das .name = "gcc_usb30_prim_sleep_clk", 23331c9efb0bSTaniya Das .ops = &clk_branch2_ops, 23341c9efb0bSTaniya Das }, 23351c9efb0bSTaniya Das }, 23361c9efb0bSTaniya Das }; 23371c9efb0bSTaniya Das 23381c9efb0bSTaniya Das static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 23391c9efb0bSTaniya Das .halt_reg = 0x49060, 23401c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 23411c9efb0bSTaniya Das .clkr = { 23421c9efb0bSTaniya Das .enable_reg = 0x49060, 23431c9efb0bSTaniya Das .enable_mask = BIT(0), 23441c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 23451c9efb0bSTaniya Das .name = "gcc_usb3_prim_phy_aux_clk", 23461c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 23471c9efb0bSTaniya Das &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 23481c9efb0bSTaniya Das }, 23491c9efb0bSTaniya Das .num_parents = 1, 23501c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 23511c9efb0bSTaniya Das .ops = &clk_branch2_ops, 23521c9efb0bSTaniya Das }, 23531c9efb0bSTaniya Das }, 23541c9efb0bSTaniya Das }; 23551c9efb0bSTaniya Das 23561c9efb0bSTaniya Das static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 23571c9efb0bSTaniya Das .halt_reg = 0x49064, 23581c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 23591c9efb0bSTaniya Das .clkr = { 23601c9efb0bSTaniya Das .enable_reg = 0x49064, 23611c9efb0bSTaniya Das .enable_mask = BIT(0), 23621c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 23631c9efb0bSTaniya Das .name = "gcc_usb3_prim_phy_com_aux_clk", 23641c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 23651c9efb0bSTaniya Das &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 23661c9efb0bSTaniya Das }, 23671c9efb0bSTaniya Das .num_parents = 1, 23681c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 23691c9efb0bSTaniya Das .ops = &clk_branch2_ops, 23701c9efb0bSTaniya Das }, 23711c9efb0bSTaniya Das }, 23721c9efb0bSTaniya Das }; 23731c9efb0bSTaniya Das 23741c9efb0bSTaniya Das static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 23751c9efb0bSTaniya Das .halt_reg = 0x49068, 23761c9efb0bSTaniya Das .halt_check = BRANCH_HALT_DELAY, 23771c9efb0bSTaniya Das .hwcg_reg = 0x49068, 23781c9efb0bSTaniya Das .hwcg_bit = 1, 23791c9efb0bSTaniya Das .clkr = { 23801c9efb0bSTaniya Das .enable_reg = 0x49068, 23811c9efb0bSTaniya Das .enable_mask = BIT(0), 23821c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 23831c9efb0bSTaniya Das .name = "gcc_usb3_prim_phy_pipe_clk", 23841c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 23851c9efb0bSTaniya Das &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 23861c9efb0bSTaniya Das }, 23871c9efb0bSTaniya Das .num_parents = 1, 23881c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 23891c9efb0bSTaniya Das .ops = &clk_branch2_ops, 23901c9efb0bSTaniya Das }, 23911c9efb0bSTaniya Das }, 23921c9efb0bSTaniya Das }; 23931c9efb0bSTaniya Das 23941c9efb0bSTaniya Das static struct clk_regmap *gcc_qdu1000_clocks[] = { 23951c9efb0bSTaniya Das [GCC_AGGRE_NOC_ECPRI_DMA_CLK] = &gcc_aggre_noc_ecpri_dma_clk.clkr, 23961c9efb0bSTaniya Das [GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC] = &gcc_aggre_noc_ecpri_dma_clk_src.clkr, 23971c9efb0bSTaniya Das [GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC] = &gcc_aggre_noc_ecpri_gsi_clk_src.clkr, 23981c9efb0bSTaniya Das [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 23991c9efb0bSTaniya Das [GCC_CFG_NOC_ECPRI_CC_AHB_CLK] = &gcc_cfg_noc_ecpri_cc_ahb_clk.clkr, 24001c9efb0bSTaniya Das [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 24011c9efb0bSTaniya Das [GCC_DDRSS_ECPRI_DMA_CLK] = &gcc_ddrss_ecpri_dma_clk.clkr, 24021c9efb0bSTaniya Das [GCC_ECPRI_AHB_CLK] = &gcc_ecpri_ahb_clk.clkr, 24031c9efb0bSTaniya Das [GCC_ECPRI_CC_GPLL0_CLK_SRC] = &gcc_ecpri_cc_gpll0_clk_src.clkr, 24041c9efb0bSTaniya Das [GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll1_even_clk_src.clkr, 24051c9efb0bSTaniya Das [GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll2_even_clk_src.clkr, 24061c9efb0bSTaniya Das [GCC_ECPRI_CC_GPLL3_CLK_SRC] = &gcc_ecpri_cc_gpll3_clk_src.clkr, 24071c9efb0bSTaniya Das [GCC_ECPRI_CC_GPLL4_CLK_SRC] = &gcc_ecpri_cc_gpll4_clk_src.clkr, 24081c9efb0bSTaniya Das [GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll5_even_clk_src.clkr, 24091c9efb0bSTaniya Das [GCC_ECPRI_XO_CLK] = &gcc_ecpri_xo_clk.clkr, 24101c9efb0bSTaniya Das [GCC_ETH_DBG_SNOC_AXI_CLK] = &gcc_eth_dbg_snoc_axi_clk.clkr, 24111c9efb0bSTaniya Das [GCC_GEMNOC_PCIE_QX_CLK] = &gcc_gemnoc_pcie_qx_clk.clkr, 24121c9efb0bSTaniya Das [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 24131c9efb0bSTaniya Das [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 24141c9efb0bSTaniya Das [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 24151c9efb0bSTaniya Das [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 24161c9efb0bSTaniya Das [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 24171c9efb0bSTaniya Das [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 24181c9efb0bSTaniya Das [GCC_GPLL0] = &gcc_gpll0.clkr, 24191c9efb0bSTaniya Das [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 24201c9efb0bSTaniya Das [GCC_GPLL1] = &gcc_gpll1.clkr, 24211c9efb0bSTaniya Das [GCC_GPLL2] = &gcc_gpll2.clkr, 24221c9efb0bSTaniya Das [GCC_GPLL2_OUT_EVEN] = &gcc_gpll2_out_even.clkr, 24231c9efb0bSTaniya Das [GCC_GPLL3] = &gcc_gpll3.clkr, 24241c9efb0bSTaniya Das [GCC_GPLL4] = &gcc_gpll4.clkr, 24251c9efb0bSTaniya Das [GCC_GPLL5] = &gcc_gpll5.clkr, 24261c9efb0bSTaniya Das [GCC_GPLL5_OUT_EVEN] = &gcc_gpll5_out_even.clkr, 24271c9efb0bSTaniya Das [GCC_GPLL6] = &gcc_gpll6.clkr, 24281c9efb0bSTaniya Das [GCC_GPLL7] = &gcc_gpll7.clkr, 24291c9efb0bSTaniya Das [GCC_GPLL8] = &gcc_gpll8.clkr, 24301c9efb0bSTaniya Das [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 24311c9efb0bSTaniya Das [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 24321c9efb0bSTaniya Das [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 24331c9efb0bSTaniya Das [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr, 24341c9efb0bSTaniya Das [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 24351c9efb0bSTaniya Das [GCC_PCIE_0_PHY_AUX_CLK] = &gcc_pcie_0_phy_aux_clk.clkr, 24361c9efb0bSTaniya Das [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 24371c9efb0bSTaniya Das [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 24381c9efb0bSTaniya Das [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 24391c9efb0bSTaniya Das [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 24401c9efb0bSTaniya Das [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 24411c9efb0bSTaniya Das [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 24421c9efb0bSTaniya Das [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 24431c9efb0bSTaniya Das [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 24441c9efb0bSTaniya Das [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 24451c9efb0bSTaniya Das [GCC_QMIP_ANOC_PCIE_CLK] = &gcc_qmip_anoc_pcie_clk.clkr, 24461c9efb0bSTaniya Das [GCC_QMIP_ECPRI_DMA0_CLK] = &gcc_qmip_ecpri_dma0_clk.clkr, 24471c9efb0bSTaniya Das [GCC_QMIP_ECPRI_DMA1_CLK] = &gcc_qmip_ecpri_dma1_clk.clkr, 24481c9efb0bSTaniya Das [GCC_QMIP_ECPRI_GSI_CLK] = &gcc_qmip_ecpri_gsi_clk.clkr, 24491c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 24501c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 24511c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 24521c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 24531c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 24541c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 24551c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 24561c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 24571c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 24581c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 24591c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 24601c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 24611c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 24621c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 24631c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 24641c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 24651c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 24661c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 24671c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 24681c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 24691c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 24701c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 24711c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 24721c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 24731c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 24741c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 24751c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 24761c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 24771c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 24781c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 24791c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 24801c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 24811c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 24821c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 24831c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 24841c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 24851c9efb0bSTaniya Das [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 24861c9efb0bSTaniya Das [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 24871c9efb0bSTaniya Das [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 24881c9efb0bSTaniya Das [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 24891c9efb0bSTaniya Das [GCC_SDCC5_AHB_CLK] = &gcc_sdcc5_ahb_clk.clkr, 24901c9efb0bSTaniya Das [GCC_SDCC5_APPS_CLK] = &gcc_sdcc5_apps_clk.clkr, 24911c9efb0bSTaniya Das [GCC_SDCC5_APPS_CLK_SRC] = &gcc_sdcc5_apps_clk_src.clkr, 24921c9efb0bSTaniya Das [GCC_SDCC5_ICE_CORE_CLK] = &gcc_sdcc5_ice_core_clk.clkr, 24931c9efb0bSTaniya Das [GCC_SDCC5_ICE_CORE_CLK_SRC] = &gcc_sdcc5_ice_core_clk_src.clkr, 24941c9efb0bSTaniya Das [GCC_SM_BUS_AHB_CLK] = &gcc_sm_bus_ahb_clk.clkr, 24951c9efb0bSTaniya Das [GCC_SM_BUS_XO_CLK] = &gcc_sm_bus_xo_clk.clkr, 24961c9efb0bSTaniya Das [GCC_SM_BUS_XO_CLK_SRC] = &gcc_sm_bus_xo_clk_src.clkr, 24971c9efb0bSTaniya Das [GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK] = &gcc_snoc_cnoc_gemnoc_pcie_qx_clk.clkr, 24981c9efb0bSTaniya Das [GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK] = &gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk.clkr, 24991c9efb0bSTaniya Das [GCC_SNOC_CNOC_PCIE_QX_CLK] = &gcc_snoc_cnoc_pcie_qx_clk.clkr, 25001c9efb0bSTaniya Das [GCC_SNOC_PCIE_SF_CENTER_QX_CLK] = &gcc_snoc_pcie_sf_center_qx_clk.clkr, 25011c9efb0bSTaniya Das [GCC_SNOC_PCIE_SF_SOUTH_QX_CLK] = &gcc_snoc_pcie_sf_south_qx_clk.clkr, 25021c9efb0bSTaniya Das [GCC_TSC_CFG_AHB_CLK] = &gcc_tsc_cfg_ahb_clk.clkr, 25031c9efb0bSTaniya Das [GCC_TSC_CLK_SRC] = &gcc_tsc_clk_src.clkr, 25041c9efb0bSTaniya Das [GCC_TSC_CNTR_CLK] = &gcc_tsc_cntr_clk.clkr, 25051c9efb0bSTaniya Das [GCC_TSC_ETU_CLK] = &gcc_tsc_etu_clk.clkr, 25061c9efb0bSTaniya Das [GCC_USB2_CLKREF_EN] = &gcc_usb2_clkref_en.clkr, 25071c9efb0bSTaniya Das [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 25081c9efb0bSTaniya Das [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 25091c9efb0bSTaniya Das [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 25101c9efb0bSTaniya Das [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 25111c9efb0bSTaniya Das [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 25121c9efb0bSTaniya Das [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 25131c9efb0bSTaniya Das [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 25141c9efb0bSTaniya Das [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 25151c9efb0bSTaniya Das [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 25161c9efb0bSTaniya Das [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 25171c9efb0bSTaniya Das [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 25181c9efb0bSTaniya Das [GCC_ETH_100G_C2C_HM_APB_CLK] = &gcc_eth_100g_c2c_hm_apb_clk.clkr, 25191c9efb0bSTaniya Das [GCC_ETH_100G_FH_HM_APB_0_CLK] = &gcc_eth_100g_fh_hm_apb_0_clk.clkr, 25201c9efb0bSTaniya Das [GCC_ETH_100G_FH_HM_APB_1_CLK] = &gcc_eth_100g_fh_hm_apb_1_clk.clkr, 25211c9efb0bSTaniya Das [GCC_ETH_100G_FH_HM_APB_2_CLK] = &gcc_eth_100g_fh_hm_apb_2_clk.clkr, 25221c9efb0bSTaniya Das [GCC_ETH_DBG_C2C_HM_APB_CLK] = &gcc_eth_dbg_c2c_hm_apb_clk.clkr, 25231c9efb0bSTaniya Das [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr, 25241c9efb0bSTaniya Das [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, 25251c9efb0bSTaniya Das [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 25261c9efb0bSTaniya Das }; 25271c9efb0bSTaniya Das 25281c9efb0bSTaniya Das static const struct qcom_reset_map gcc_qdu1000_resets[] = { 25291c9efb0bSTaniya Das [GCC_ECPRI_CC_BCR] = { 0x3e000 }, 25301c9efb0bSTaniya Das [GCC_ECPRI_SS_BCR] = { 0x3a000 }, 25311c9efb0bSTaniya Das [GCC_ETH_WRAPPER_BCR] = { 0x39000 }, 25321c9efb0bSTaniya Das [GCC_PCIE_0_BCR] = { 0x9d000 }, 25331c9efb0bSTaniya Das [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x9e014 }, 25341c9efb0bSTaniya Das [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x9e020 }, 25351c9efb0bSTaniya Das [GCC_PCIE_0_PHY_BCR] = { 0x7c000 }, 25361c9efb0bSTaniya Das [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 }, 25371c9efb0bSTaniya Das [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c }, 25381c9efb0bSTaniya Das [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 }, 25391c9efb0bSTaniya Das [GCC_PDM_BCR] = { 0x43000 }, 25401c9efb0bSTaniya Das [GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 }, 25411c9efb0bSTaniya Das [GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 }, 25421c9efb0bSTaniya Das [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 }, 25431c9efb0bSTaniya Das [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 }, 25441c9efb0bSTaniya Das [GCC_SDCC5_BCR] = { 0x3b000 }, 25451c9efb0bSTaniya Das [GCC_TSC_BCR] = { 0x57000 }, 25461c9efb0bSTaniya Das [GCC_USB30_PRIM_BCR] = { 0x49000 }, 25471c9efb0bSTaniya Das [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 }, 25481c9efb0bSTaniya Das [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 }, 25491c9efb0bSTaniya Das [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 }, 25501c9efb0bSTaniya Das [GCC_USB3_PHY_SEC_BCR] = { 0x6000c }, 25511c9efb0bSTaniya Das [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 }, 25521c9efb0bSTaniya Das [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 }, 25531c9efb0bSTaniya Das [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 }, 25541c9efb0bSTaniya Das }; 25551c9efb0bSTaniya Das 25561c9efb0bSTaniya Das static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 25571c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 25581c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 25591c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 25601c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 25611c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 25621c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 25631c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 25641c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 25651c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 25661c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 25671c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 25681c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 25691c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 25701c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 25711c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 25721c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 25731c9efb0bSTaniya Das }; 25741c9efb0bSTaniya Das 25751c9efb0bSTaniya Das static const struct regmap_config gcc_qdu1000_regmap_config = { 25761c9efb0bSTaniya Das .reg_bits = 32, 25771c9efb0bSTaniya Das .reg_stride = 4, 25781c9efb0bSTaniya Das .val_bits = 32, 25791c9efb0bSTaniya Das .max_register = 0x1f41f0, 25801c9efb0bSTaniya Das .fast_io = true, 25811c9efb0bSTaniya Das }; 25821c9efb0bSTaniya Das 25831c9efb0bSTaniya Das static const struct qcom_cc_desc gcc_qdu1000_desc = { 25841c9efb0bSTaniya Das .config = &gcc_qdu1000_regmap_config, 25851c9efb0bSTaniya Das .clks = gcc_qdu1000_clocks, 25861c9efb0bSTaniya Das .num_clks = ARRAY_SIZE(gcc_qdu1000_clocks), 25871c9efb0bSTaniya Das .resets = gcc_qdu1000_resets, 25881c9efb0bSTaniya Das .num_resets = ARRAY_SIZE(gcc_qdu1000_resets), 25891c9efb0bSTaniya Das }; 25901c9efb0bSTaniya Das 25911c9efb0bSTaniya Das static const struct of_device_id gcc_qdu1000_match_table[] = { 25921c9efb0bSTaniya Das { .compatible = "qcom,qdu1000-gcc" }, 25931c9efb0bSTaniya Das { } 25941c9efb0bSTaniya Das }; 25951c9efb0bSTaniya Das MODULE_DEVICE_TABLE(of, gcc_qdu1000_match_table); 25961c9efb0bSTaniya Das 25971c9efb0bSTaniya Das static int gcc_qdu1000_probe(struct platform_device *pdev) 25981c9efb0bSTaniya Das { 25991c9efb0bSTaniya Das struct regmap *regmap; 26001c9efb0bSTaniya Das int ret; 26011c9efb0bSTaniya Das 26021c9efb0bSTaniya Das regmap = qcom_cc_map(pdev, &gcc_qdu1000_desc); 26031c9efb0bSTaniya Das if (IS_ERR(regmap)) 26041c9efb0bSTaniya Das return PTR_ERR(regmap); 26051c9efb0bSTaniya Das 26061c9efb0bSTaniya Das /* Update FORCE_MEM_CORE_ON for gcc_pcie_0_mstr_axi_clk */ 26071c9efb0bSTaniya Das regmap_update_bits(regmap, 0x9d024, BIT(14), BIT(14)); 26081c9efb0bSTaniya Das 26091c9efb0bSTaniya Das ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 26101c9efb0bSTaniya Das ARRAY_SIZE(gcc_dfs_clocks)); 26111c9efb0bSTaniya Das if (ret) 26121c9efb0bSTaniya Das return ret; 26131c9efb0bSTaniya Das 26141c9efb0bSTaniya Das ret = qcom_cc_really_probe(pdev, &gcc_qdu1000_desc, regmap); 26151c9efb0bSTaniya Das if (ret) 26161c9efb0bSTaniya Das return dev_err_probe(&pdev->dev, ret, "Failed to register GCC clocks\n"); 26171c9efb0bSTaniya Das 26181c9efb0bSTaniya Das return ret; 26191c9efb0bSTaniya Das } 26201c9efb0bSTaniya Das 26211c9efb0bSTaniya Das static struct platform_driver gcc_qdu1000_driver = { 26221c9efb0bSTaniya Das .probe = gcc_qdu1000_probe, 26231c9efb0bSTaniya Das .driver = { 26241c9efb0bSTaniya Das .name = "gcc-qdu1000", 26251c9efb0bSTaniya Das .of_match_table = gcc_qdu1000_match_table, 26261c9efb0bSTaniya Das }, 26271c9efb0bSTaniya Das }; 26281c9efb0bSTaniya Das 26291c9efb0bSTaniya Das static int __init gcc_qdu1000_init(void) 26301c9efb0bSTaniya Das { 26311c9efb0bSTaniya Das return platform_driver_register(&gcc_qdu1000_driver); 26321c9efb0bSTaniya Das } 26331c9efb0bSTaniya Das subsys_initcall(gcc_qdu1000_init); 26341c9efb0bSTaniya Das 26351c9efb0bSTaniya Das static void __exit gcc_qdu1000_exit(void) 26361c9efb0bSTaniya Das { 26371c9efb0bSTaniya Das platform_driver_unregister(&gcc_qdu1000_driver); 26381c9efb0bSTaniya Das } 26391c9efb0bSTaniya Das module_exit(gcc_qdu1000_exit); 26401c9efb0bSTaniya Das 26411c9efb0bSTaniya Das MODULE_DESCRIPTION("QTI GCC QDU1000 Driver"); 26421c9efb0bSTaniya Das MODULE_LICENSE("GPL"); 2643