1*1c9efb0bSTaniya Das // SPDX-License-Identifier: GPL-2.0-only 2*1c9efb0bSTaniya Das /* 3*1c9efb0bSTaniya Das * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4*1c9efb0bSTaniya Das */ 5*1c9efb0bSTaniya Das 6*1c9efb0bSTaniya Das #include <linux/clk-provider.h> 7*1c9efb0bSTaniya Das #include <linux/module.h> 8*1c9efb0bSTaniya Das #include <linux/of_device.h> 9*1c9efb0bSTaniya Das #include <linux/regmap.h> 10*1c9efb0bSTaniya Das 11*1c9efb0bSTaniya Das #include <dt-bindings/clock/qcom,qdu1000-gcc.h> 12*1c9efb0bSTaniya Das 13*1c9efb0bSTaniya Das #include "clk-alpha-pll.h" 14*1c9efb0bSTaniya Das #include "clk-branch.h" 15*1c9efb0bSTaniya Das #include "clk-rcg.h" 16*1c9efb0bSTaniya Das #include "clk-regmap.h" 17*1c9efb0bSTaniya Das #include "clk-regmap-divider.h" 18*1c9efb0bSTaniya Das #include "clk-regmap-mux.h" 19*1c9efb0bSTaniya Das #include "clk-regmap-phy-mux.h" 20*1c9efb0bSTaniya Das #include "reset.h" 21*1c9efb0bSTaniya Das 22*1c9efb0bSTaniya Das enum { 23*1c9efb0bSTaniya Das P_BI_TCXO, 24*1c9efb0bSTaniya Das P_GCC_GPLL0_OUT_EVEN, 25*1c9efb0bSTaniya Das P_GCC_GPLL0_OUT_MAIN, 26*1c9efb0bSTaniya Das P_GCC_GPLL1_OUT_MAIN, 27*1c9efb0bSTaniya Das P_GCC_GPLL2_OUT_MAIN, 28*1c9efb0bSTaniya Das P_GCC_GPLL3_OUT_MAIN, 29*1c9efb0bSTaniya Das P_GCC_GPLL4_OUT_MAIN, 30*1c9efb0bSTaniya Das P_GCC_GPLL5_OUT_MAIN, 31*1c9efb0bSTaniya Das P_GCC_GPLL6_OUT_MAIN, 32*1c9efb0bSTaniya Das P_GCC_GPLL7_OUT_MAIN, 33*1c9efb0bSTaniya Das P_GCC_GPLL8_OUT_MAIN, 34*1c9efb0bSTaniya Das P_PCIE_0_PHY_AUX_CLK, 35*1c9efb0bSTaniya Das P_PCIE_0_PIPE_CLK, 36*1c9efb0bSTaniya Das P_SLEEP_CLK, 37*1c9efb0bSTaniya Das P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 38*1c9efb0bSTaniya Das }; 39*1c9efb0bSTaniya Das 40*1c9efb0bSTaniya Das enum { 41*1c9efb0bSTaniya Das DT_TCXO_IDX, 42*1c9efb0bSTaniya Das DT_SLEEP_CLK_IDX, 43*1c9efb0bSTaniya Das DT_PCIE_0_PIPE_CLK_IDX, 44*1c9efb0bSTaniya Das DT_PCIE_0_PHY_AUX_CLK_IDX, 45*1c9efb0bSTaniya Das DT_USB3_PHY_WRAPPER_PIPE_CLK_IDX, 46*1c9efb0bSTaniya Das }; 47*1c9efb0bSTaniya Das 48*1c9efb0bSTaniya Das static struct clk_alpha_pll gcc_gpll0 = { 49*1c9efb0bSTaniya Das .offset = 0x0, 50*1c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 51*1c9efb0bSTaniya Das .clkr = { 52*1c9efb0bSTaniya Das .enable_reg = 0x62018, 53*1c9efb0bSTaniya Das .enable_mask = BIT(0), 54*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 55*1c9efb0bSTaniya Das .name = "gcc_gpll0", 56*1c9efb0bSTaniya Das .parent_data = &(const struct clk_parent_data) { 57*1c9efb0bSTaniya Das .index = DT_TCXO_IDX, 58*1c9efb0bSTaniya Das }, 59*1c9efb0bSTaniya Das .num_parents = 1, 60*1c9efb0bSTaniya Das .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 61*1c9efb0bSTaniya Das }, 62*1c9efb0bSTaniya Das }, 63*1c9efb0bSTaniya Das }; 64*1c9efb0bSTaniya Das 65*1c9efb0bSTaniya Das static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 66*1c9efb0bSTaniya Das { 0x1, 2 } 67*1c9efb0bSTaniya Das }; 68*1c9efb0bSTaniya Das 69*1c9efb0bSTaniya Das static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 70*1c9efb0bSTaniya Das .offset = 0x0, 71*1c9efb0bSTaniya Das .post_div_shift = 10, 72*1c9efb0bSTaniya Das .post_div_table = post_div_table_gcc_gpll0_out_even, 73*1c9efb0bSTaniya Das .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 74*1c9efb0bSTaniya Das .width = 4, 75*1c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 76*1c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 77*1c9efb0bSTaniya Das .name = "gcc_gpll0_out_even", 78*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 79*1c9efb0bSTaniya Das &gcc_gpll0.clkr.hw, 80*1c9efb0bSTaniya Das }, 81*1c9efb0bSTaniya Das .num_parents = 1, 82*1c9efb0bSTaniya Das .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 83*1c9efb0bSTaniya Das }, 84*1c9efb0bSTaniya Das }; 85*1c9efb0bSTaniya Das 86*1c9efb0bSTaniya Das static struct clk_alpha_pll gcc_gpll1 = { 87*1c9efb0bSTaniya Das .offset = 0x1000, 88*1c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 89*1c9efb0bSTaniya Das .clkr = { 90*1c9efb0bSTaniya Das .enable_reg = 0x62018, 91*1c9efb0bSTaniya Das .enable_mask = BIT(1), 92*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 93*1c9efb0bSTaniya Das .name = "gcc_gpll1", 94*1c9efb0bSTaniya Das .parent_data = &(const struct clk_parent_data) { 95*1c9efb0bSTaniya Das .index = DT_TCXO_IDX, 96*1c9efb0bSTaniya Das }, 97*1c9efb0bSTaniya Das .num_parents = 1, 98*1c9efb0bSTaniya Das .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 99*1c9efb0bSTaniya Das }, 100*1c9efb0bSTaniya Das }, 101*1c9efb0bSTaniya Das }; 102*1c9efb0bSTaniya Das 103*1c9efb0bSTaniya Das static struct clk_alpha_pll_postdiv gcc_gpll1_out_even = { 104*1c9efb0bSTaniya Das .offset = 0x1000, 105*1c9efb0bSTaniya Das .post_div_shift = 10, 106*1c9efb0bSTaniya Das .post_div_table = post_div_table_gcc_gpll0_out_even, 107*1c9efb0bSTaniya Das .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 108*1c9efb0bSTaniya Das .width = 4, 109*1c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 110*1c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 111*1c9efb0bSTaniya Das .name = "gcc_gpll1_out_even", 112*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 113*1c9efb0bSTaniya Das &gcc_gpll1.clkr.hw, 114*1c9efb0bSTaniya Das }, 115*1c9efb0bSTaniya Das .num_parents = 1, 116*1c9efb0bSTaniya Das .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 117*1c9efb0bSTaniya Das }, 118*1c9efb0bSTaniya Das }; 119*1c9efb0bSTaniya Das 120*1c9efb0bSTaniya Das static struct clk_alpha_pll gcc_gpll2 = { 121*1c9efb0bSTaniya Das .offset = 0x2000, 122*1c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 123*1c9efb0bSTaniya Das .clkr = { 124*1c9efb0bSTaniya Das .enable_reg = 0x62018, 125*1c9efb0bSTaniya Das .enable_mask = BIT(2), 126*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 127*1c9efb0bSTaniya Das .name = "gcc_gpll2", 128*1c9efb0bSTaniya Das .parent_data = &(const struct clk_parent_data) { 129*1c9efb0bSTaniya Das .index = DT_TCXO_IDX, 130*1c9efb0bSTaniya Das }, 131*1c9efb0bSTaniya Das .num_parents = 1, 132*1c9efb0bSTaniya Das .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 133*1c9efb0bSTaniya Das }, 134*1c9efb0bSTaniya Das }, 135*1c9efb0bSTaniya Das }; 136*1c9efb0bSTaniya Das 137*1c9efb0bSTaniya Das static struct clk_alpha_pll_postdiv gcc_gpll2_out_even = { 138*1c9efb0bSTaniya Das .offset = 0x2000, 139*1c9efb0bSTaniya Das .post_div_shift = 10, 140*1c9efb0bSTaniya Das .post_div_table = post_div_table_gcc_gpll0_out_even, 141*1c9efb0bSTaniya Das .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 142*1c9efb0bSTaniya Das .width = 4, 143*1c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 144*1c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 145*1c9efb0bSTaniya Das .name = "gcc_gpll2_out_even", 146*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 147*1c9efb0bSTaniya Das &gcc_gpll2.clkr.hw, 148*1c9efb0bSTaniya Das }, 149*1c9efb0bSTaniya Das .num_parents = 1, 150*1c9efb0bSTaniya Das .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 151*1c9efb0bSTaniya Das }, 152*1c9efb0bSTaniya Das }; 153*1c9efb0bSTaniya Das 154*1c9efb0bSTaniya Das static struct clk_alpha_pll gcc_gpll3 = { 155*1c9efb0bSTaniya Das .offset = 0x3000, 156*1c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 157*1c9efb0bSTaniya Das .clkr = { 158*1c9efb0bSTaniya Das .enable_reg = 0x62018, 159*1c9efb0bSTaniya Das .enable_mask = BIT(3), 160*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 161*1c9efb0bSTaniya Das .name = "gcc_gpll3", 162*1c9efb0bSTaniya Das .parent_data = &(const struct clk_parent_data) { 163*1c9efb0bSTaniya Das .index = DT_TCXO_IDX, 164*1c9efb0bSTaniya Das }, 165*1c9efb0bSTaniya Das .num_parents = 1, 166*1c9efb0bSTaniya Das .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 167*1c9efb0bSTaniya Das }, 168*1c9efb0bSTaniya Das }, 169*1c9efb0bSTaniya Das }; 170*1c9efb0bSTaniya Das 171*1c9efb0bSTaniya Das static struct clk_alpha_pll gcc_gpll4 = { 172*1c9efb0bSTaniya Das .offset = 0x4000, 173*1c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 174*1c9efb0bSTaniya Das .clkr = { 175*1c9efb0bSTaniya Das .enable_reg = 0x62018, 176*1c9efb0bSTaniya Das .enable_mask = BIT(4), 177*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 178*1c9efb0bSTaniya Das .name = "gcc_gpll4", 179*1c9efb0bSTaniya Das .parent_data = &(const struct clk_parent_data) { 180*1c9efb0bSTaniya Das .index = DT_TCXO_IDX, 181*1c9efb0bSTaniya Das }, 182*1c9efb0bSTaniya Das .num_parents = 1, 183*1c9efb0bSTaniya Das .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 184*1c9efb0bSTaniya Das }, 185*1c9efb0bSTaniya Das }, 186*1c9efb0bSTaniya Das }; 187*1c9efb0bSTaniya Das 188*1c9efb0bSTaniya Das static struct clk_alpha_pll gcc_gpll5 = { 189*1c9efb0bSTaniya Das .offset = 0x5000, 190*1c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 191*1c9efb0bSTaniya Das .clkr = { 192*1c9efb0bSTaniya Das .enable_reg = 0x62018, 193*1c9efb0bSTaniya Das .enable_mask = BIT(5), 194*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 195*1c9efb0bSTaniya Das .name = "gcc_gpll5", 196*1c9efb0bSTaniya Das .parent_data = &(const struct clk_parent_data) { 197*1c9efb0bSTaniya Das .index = DT_TCXO_IDX, 198*1c9efb0bSTaniya Das }, 199*1c9efb0bSTaniya Das .num_parents = 1, 200*1c9efb0bSTaniya Das .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 201*1c9efb0bSTaniya Das }, 202*1c9efb0bSTaniya Das }, 203*1c9efb0bSTaniya Das }; 204*1c9efb0bSTaniya Das 205*1c9efb0bSTaniya Das static struct clk_alpha_pll_postdiv gcc_gpll5_out_even = { 206*1c9efb0bSTaniya Das .offset = 0x5000, 207*1c9efb0bSTaniya Das .post_div_shift = 10, 208*1c9efb0bSTaniya Das .post_div_table = post_div_table_gcc_gpll0_out_even, 209*1c9efb0bSTaniya Das .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 210*1c9efb0bSTaniya Das .width = 4, 211*1c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 212*1c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 213*1c9efb0bSTaniya Das .name = "gcc_gpll5_out_even", 214*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 215*1c9efb0bSTaniya Das &gcc_gpll5.clkr.hw, 216*1c9efb0bSTaniya Das }, 217*1c9efb0bSTaniya Das .num_parents = 1, 218*1c9efb0bSTaniya Das .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 219*1c9efb0bSTaniya Das }, 220*1c9efb0bSTaniya Das }; 221*1c9efb0bSTaniya Das 222*1c9efb0bSTaniya Das static struct clk_alpha_pll gcc_gpll6 = { 223*1c9efb0bSTaniya Das .offset = 0x6000, 224*1c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 225*1c9efb0bSTaniya Das .clkr = { 226*1c9efb0bSTaniya Das .enable_reg = 0x62018, 227*1c9efb0bSTaniya Das .enable_mask = BIT(6), 228*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 229*1c9efb0bSTaniya Das .name = "gcc_gpll6", 230*1c9efb0bSTaniya Das .parent_data = &(const struct clk_parent_data) { 231*1c9efb0bSTaniya Das .index = DT_TCXO_IDX, 232*1c9efb0bSTaniya Das }, 233*1c9efb0bSTaniya Das .num_parents = 1, 234*1c9efb0bSTaniya Das .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 235*1c9efb0bSTaniya Das }, 236*1c9efb0bSTaniya Das }, 237*1c9efb0bSTaniya Das }; 238*1c9efb0bSTaniya Das 239*1c9efb0bSTaniya Das static struct clk_alpha_pll gcc_gpll7 = { 240*1c9efb0bSTaniya Das .offset = 0x7000, 241*1c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 242*1c9efb0bSTaniya Das .clkr = { 243*1c9efb0bSTaniya Das .enable_reg = 0x62018, 244*1c9efb0bSTaniya Das .enable_mask = BIT(7), 245*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 246*1c9efb0bSTaniya Das .name = "gcc_gpll7", 247*1c9efb0bSTaniya Das .parent_data = &(const struct clk_parent_data) { 248*1c9efb0bSTaniya Das .index = DT_TCXO_IDX, 249*1c9efb0bSTaniya Das }, 250*1c9efb0bSTaniya Das .num_parents = 1, 251*1c9efb0bSTaniya Das .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 252*1c9efb0bSTaniya Das }, 253*1c9efb0bSTaniya Das }, 254*1c9efb0bSTaniya Das }; 255*1c9efb0bSTaniya Das 256*1c9efb0bSTaniya Das static struct clk_alpha_pll gcc_gpll8 = { 257*1c9efb0bSTaniya Das .offset = 0x8000, 258*1c9efb0bSTaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 259*1c9efb0bSTaniya Das .clkr = { 260*1c9efb0bSTaniya Das .enable_reg = 0x62018, 261*1c9efb0bSTaniya Das .enable_mask = BIT(8), 262*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 263*1c9efb0bSTaniya Das .name = "gcc_gpll8", 264*1c9efb0bSTaniya Das .parent_data = &(const struct clk_parent_data) { 265*1c9efb0bSTaniya Das .index = DT_TCXO_IDX, 266*1c9efb0bSTaniya Das }, 267*1c9efb0bSTaniya Das .num_parents = 1, 268*1c9efb0bSTaniya Das .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 269*1c9efb0bSTaniya Das }, 270*1c9efb0bSTaniya Das }, 271*1c9efb0bSTaniya Das }; 272*1c9efb0bSTaniya Das 273*1c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_0[] = { 274*1c9efb0bSTaniya Das { P_BI_TCXO, 0 }, 275*1c9efb0bSTaniya Das { P_GCC_GPLL0_OUT_MAIN, 1 }, 276*1c9efb0bSTaniya Das { P_GCC_GPLL0_OUT_EVEN, 6 }, 277*1c9efb0bSTaniya Das }; 278*1c9efb0bSTaniya Das 279*1c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_0[] = { 280*1c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 281*1c9efb0bSTaniya Das { .hw = &gcc_gpll0.clkr.hw }, 282*1c9efb0bSTaniya Das { .hw = &gcc_gpll0_out_even.clkr.hw }, 283*1c9efb0bSTaniya Das }; 284*1c9efb0bSTaniya Das 285*1c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_1[] = { 286*1c9efb0bSTaniya Das { P_BI_TCXO, 0 }, 287*1c9efb0bSTaniya Das { P_GCC_GPLL0_OUT_MAIN, 1 }, 288*1c9efb0bSTaniya Das { P_SLEEP_CLK, 5 }, 289*1c9efb0bSTaniya Das { P_GCC_GPLL0_OUT_EVEN, 6 }, 290*1c9efb0bSTaniya Das }; 291*1c9efb0bSTaniya Das 292*1c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_1[] = { 293*1c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 294*1c9efb0bSTaniya Das { .hw = &gcc_gpll0.clkr.hw }, 295*1c9efb0bSTaniya Das { .index = DT_SLEEP_CLK_IDX }, 296*1c9efb0bSTaniya Das { .hw = &gcc_gpll0_out_even.clkr.hw }, 297*1c9efb0bSTaniya Das }; 298*1c9efb0bSTaniya Das 299*1c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_2[] = { 300*1c9efb0bSTaniya Das { P_BI_TCXO, 0 }, 301*1c9efb0bSTaniya Das { P_GCC_GPLL0_OUT_MAIN, 1 }, 302*1c9efb0bSTaniya Das { P_GCC_GPLL5_OUT_MAIN, 3 }, 303*1c9efb0bSTaniya Das { P_GCC_GPLL4_OUT_MAIN, 5 }, 304*1c9efb0bSTaniya Das }; 305*1c9efb0bSTaniya Das 306*1c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_2[] = { 307*1c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 308*1c9efb0bSTaniya Das { .hw = &gcc_gpll0.clkr.hw }, 309*1c9efb0bSTaniya Das { .hw = &gcc_gpll5.clkr.hw }, 310*1c9efb0bSTaniya Das { .hw = &gcc_gpll4.clkr.hw }, 311*1c9efb0bSTaniya Das }; 312*1c9efb0bSTaniya Das 313*1c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_3[] = { 314*1c9efb0bSTaniya Das { P_BI_TCXO, 0 }, 315*1c9efb0bSTaniya Das { P_SLEEP_CLK, 5 }, 316*1c9efb0bSTaniya Das }; 317*1c9efb0bSTaniya Das 318*1c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_3[] = { 319*1c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 320*1c9efb0bSTaniya Das { .index = DT_SLEEP_CLK_IDX }, 321*1c9efb0bSTaniya Das }; 322*1c9efb0bSTaniya Das 323*1c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_4[] = { 324*1c9efb0bSTaniya Das { P_BI_TCXO, 0 }, 325*1c9efb0bSTaniya Das { P_GCC_GPLL0_OUT_MAIN, 1 }, 326*1c9efb0bSTaniya Das { P_GCC_GPLL2_OUT_MAIN, 2 }, 327*1c9efb0bSTaniya Das { P_GCC_GPLL5_OUT_MAIN, 3 }, 328*1c9efb0bSTaniya Das { P_GCC_GPLL1_OUT_MAIN, 4 }, 329*1c9efb0bSTaniya Das { P_GCC_GPLL4_OUT_MAIN, 5 }, 330*1c9efb0bSTaniya Das { P_GCC_GPLL3_OUT_MAIN, 6 }, 331*1c9efb0bSTaniya Das }; 332*1c9efb0bSTaniya Das 333*1c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_4[] = { 334*1c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 335*1c9efb0bSTaniya Das { .hw = &gcc_gpll0.clkr.hw }, 336*1c9efb0bSTaniya Das { .hw = &gcc_gpll2.clkr.hw }, 337*1c9efb0bSTaniya Das { .hw = &gcc_gpll5.clkr.hw }, 338*1c9efb0bSTaniya Das { .hw = &gcc_gpll1.clkr.hw }, 339*1c9efb0bSTaniya Das { .hw = &gcc_gpll4.clkr.hw }, 340*1c9efb0bSTaniya Das { .hw = &gcc_gpll3.clkr.hw }, 341*1c9efb0bSTaniya Das }; 342*1c9efb0bSTaniya Das 343*1c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_5[] = { 344*1c9efb0bSTaniya Das { P_BI_TCXO, 0 }, 345*1c9efb0bSTaniya Das { P_GCC_GPLL0_OUT_MAIN, 1 }, 346*1c9efb0bSTaniya Das { P_GCC_GPLL2_OUT_MAIN, 2 }, 347*1c9efb0bSTaniya Das { P_GCC_GPLL6_OUT_MAIN, 3 }, 348*1c9efb0bSTaniya Das { P_GCC_GPLL1_OUT_MAIN, 4 }, 349*1c9efb0bSTaniya Das { P_GCC_GPLL4_OUT_MAIN, 5 }, 350*1c9efb0bSTaniya Das { P_GCC_GPLL3_OUT_MAIN, 6 }, 351*1c9efb0bSTaniya Das }; 352*1c9efb0bSTaniya Das 353*1c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_5[] = { 354*1c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 355*1c9efb0bSTaniya Das { .hw = &gcc_gpll0.clkr.hw }, 356*1c9efb0bSTaniya Das { .hw = &gcc_gpll2.clkr.hw }, 357*1c9efb0bSTaniya Das { .hw = &gcc_gpll6.clkr.hw }, 358*1c9efb0bSTaniya Das { .hw = &gcc_gpll1.clkr.hw }, 359*1c9efb0bSTaniya Das { .hw = &gcc_gpll4.clkr.hw }, 360*1c9efb0bSTaniya Das { .hw = &gcc_gpll3.clkr.hw }, 361*1c9efb0bSTaniya Das }; 362*1c9efb0bSTaniya Das 363*1c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_6[] = { 364*1c9efb0bSTaniya Das { P_PCIE_0_PHY_AUX_CLK, 0 }, 365*1c9efb0bSTaniya Das { P_BI_TCXO, 2 }, 366*1c9efb0bSTaniya Das }; 367*1c9efb0bSTaniya Das 368*1c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_6[] = { 369*1c9efb0bSTaniya Das { .index = DT_PCIE_0_PHY_AUX_CLK_IDX }, 370*1c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 371*1c9efb0bSTaniya Das }; 372*1c9efb0bSTaniya Das 373*1c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_7[] = { 374*1c9efb0bSTaniya Das { P_PCIE_0_PIPE_CLK, 0 }, 375*1c9efb0bSTaniya Das { P_BI_TCXO, 2 }, 376*1c9efb0bSTaniya Das }; 377*1c9efb0bSTaniya Das 378*1c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_7[] = { 379*1c9efb0bSTaniya Das { .index = DT_PCIE_0_PIPE_CLK_IDX }, 380*1c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 381*1c9efb0bSTaniya Das }; 382*1c9efb0bSTaniya Das 383*1c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_8[] = { 384*1c9efb0bSTaniya Das { P_BI_TCXO, 0 }, 385*1c9efb0bSTaniya Das { P_GCC_GPLL0_OUT_MAIN, 1 }, 386*1c9efb0bSTaniya Das { P_GCC_GPLL8_OUT_MAIN, 2 }, 387*1c9efb0bSTaniya Das { P_GCC_GPLL5_OUT_MAIN, 3 }, 388*1c9efb0bSTaniya Das { P_GCC_GPLL4_OUT_MAIN, 5 }, 389*1c9efb0bSTaniya Das }; 390*1c9efb0bSTaniya Das 391*1c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_8[] = { 392*1c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 393*1c9efb0bSTaniya Das { .hw = &gcc_gpll0.clkr.hw }, 394*1c9efb0bSTaniya Das { .hw = &gcc_gpll8.clkr.hw }, 395*1c9efb0bSTaniya Das { .hw = &gcc_gpll5.clkr.hw }, 396*1c9efb0bSTaniya Das { .hw = &gcc_gpll4.clkr.hw }, 397*1c9efb0bSTaniya Das }; 398*1c9efb0bSTaniya Das 399*1c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_9[] = { 400*1c9efb0bSTaniya Das { P_BI_TCXO, 0 }, 401*1c9efb0bSTaniya Das { P_GCC_GPLL0_OUT_MAIN, 1 }, 402*1c9efb0bSTaniya Das { P_GCC_GPLL2_OUT_MAIN, 2 }, 403*1c9efb0bSTaniya Das { P_GCC_GPLL5_OUT_MAIN, 3 }, 404*1c9efb0bSTaniya Das { P_GCC_GPLL7_OUT_MAIN, 4 }, 405*1c9efb0bSTaniya Das { P_GCC_GPLL4_OUT_MAIN, 5 }, 406*1c9efb0bSTaniya Das }; 407*1c9efb0bSTaniya Das 408*1c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_9[] = { 409*1c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 410*1c9efb0bSTaniya Das { .hw = &gcc_gpll0.clkr.hw }, 411*1c9efb0bSTaniya Das { .hw = &gcc_gpll2.clkr.hw }, 412*1c9efb0bSTaniya Das { .hw = &gcc_gpll5.clkr.hw }, 413*1c9efb0bSTaniya Das { .hw = &gcc_gpll7.clkr.hw }, 414*1c9efb0bSTaniya Das { .hw = &gcc_gpll4.clkr.hw }, 415*1c9efb0bSTaniya Das }; 416*1c9efb0bSTaniya Das 417*1c9efb0bSTaniya Das static const struct parent_map gcc_parent_map_10[] = { 418*1c9efb0bSTaniya Das { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 419*1c9efb0bSTaniya Das { P_BI_TCXO, 2 }, 420*1c9efb0bSTaniya Das }; 421*1c9efb0bSTaniya Das 422*1c9efb0bSTaniya Das static const struct clk_parent_data gcc_parent_data_10[] = { 423*1c9efb0bSTaniya Das { .index = DT_USB3_PHY_WRAPPER_PIPE_CLK_IDX }, 424*1c9efb0bSTaniya Das { .index = DT_TCXO_IDX }, 425*1c9efb0bSTaniya Das }; 426*1c9efb0bSTaniya Das 427*1c9efb0bSTaniya Das static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = { 428*1c9efb0bSTaniya Das .reg = 0x9d080, 429*1c9efb0bSTaniya Das .shift = 0, 430*1c9efb0bSTaniya Das .width = 2, 431*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_6, 432*1c9efb0bSTaniya Das .clkr = { 433*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 434*1c9efb0bSTaniya Das .name = "gcc_pcie_0_phy_aux_clk_src", 435*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_6, 436*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_6), 437*1c9efb0bSTaniya Das .ops = &clk_regmap_mux_closest_ops, 438*1c9efb0bSTaniya Das }, 439*1c9efb0bSTaniya Das }, 440*1c9efb0bSTaniya Das }; 441*1c9efb0bSTaniya Das 442*1c9efb0bSTaniya Das static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { 443*1c9efb0bSTaniya Das .reg = 0x9d064, 444*1c9efb0bSTaniya Das .shift = 0, 445*1c9efb0bSTaniya Das .width = 2, 446*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_7, 447*1c9efb0bSTaniya Das .clkr = { 448*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 449*1c9efb0bSTaniya Das .name = "gcc_pcie_0_pipe_clk_src", 450*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_7, 451*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_7), 452*1c9efb0bSTaniya Das .ops = &clk_regmap_phy_mux_ops, 453*1c9efb0bSTaniya Das }, 454*1c9efb0bSTaniya Das }, 455*1c9efb0bSTaniya Das }; 456*1c9efb0bSTaniya Das 457*1c9efb0bSTaniya Das static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 458*1c9efb0bSTaniya Das .reg = 0x4906c, 459*1c9efb0bSTaniya Das .shift = 0, 460*1c9efb0bSTaniya Das .width = 2, 461*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_10, 462*1c9efb0bSTaniya Das .clkr = { 463*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 464*1c9efb0bSTaniya Das .name = "gcc_usb3_prim_phy_pipe_clk_src", 465*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_10, 466*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_10), 467*1c9efb0bSTaniya Das .ops = &clk_regmap_mux_closest_ops, 468*1c9efb0bSTaniya Das }, 469*1c9efb0bSTaniya Das }, 470*1c9efb0bSTaniya Das }; 471*1c9efb0bSTaniya Das 472*1c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_dma_clk_src[] = { 473*1c9efb0bSTaniya Das F(466500000, P_GCC_GPLL5_OUT_MAIN, 2, 0, 0), 474*1c9efb0bSTaniya Das F(500000000, P_GCC_GPLL2_OUT_MAIN, 2, 0, 0), 475*1c9efb0bSTaniya Das { } 476*1c9efb0bSTaniya Das }; 477*1c9efb0bSTaniya Das 478*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_aggre_noc_ecpri_dma_clk_src = { 479*1c9efb0bSTaniya Das .cmd_rcgr = 0x92020, 480*1c9efb0bSTaniya Das .mnd_width = 0, 481*1c9efb0bSTaniya Das .hid_width = 5, 482*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_4, 483*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_aggre_noc_ecpri_dma_clk_src, 484*1c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 485*1c9efb0bSTaniya Das .name = "gcc_aggre_noc_ecpri_dma_clk_src", 486*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_4, 487*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_4), 488*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 489*1c9efb0bSTaniya Das }, 490*1c9efb0bSTaniya Das }; 491*1c9efb0bSTaniya Das 492*1c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_gsi_clk_src[] = { 493*1c9efb0bSTaniya Das F(250000000, P_GCC_GPLL2_OUT_MAIN, 4, 0, 0), 494*1c9efb0bSTaniya Das F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 495*1c9efb0bSTaniya Das { } 496*1c9efb0bSTaniya Das }; 497*1c9efb0bSTaniya Das 498*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_aggre_noc_ecpri_gsi_clk_src = { 499*1c9efb0bSTaniya Das .cmd_rcgr = 0x92038, 500*1c9efb0bSTaniya Das .mnd_width = 0, 501*1c9efb0bSTaniya Das .hid_width = 5, 502*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_5, 503*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_aggre_noc_ecpri_gsi_clk_src, 504*1c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 505*1c9efb0bSTaniya Das .name = "gcc_aggre_noc_ecpri_gsi_clk_src", 506*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_5, 507*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_5), 508*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 509*1c9efb0bSTaniya Das }, 510*1c9efb0bSTaniya Das }; 511*1c9efb0bSTaniya Das 512*1c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 513*1c9efb0bSTaniya Das F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 514*1c9efb0bSTaniya Das { } 515*1c9efb0bSTaniya Das }; 516*1c9efb0bSTaniya Das 517*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_gp1_clk_src = { 518*1c9efb0bSTaniya Das .cmd_rcgr = 0x74004, 519*1c9efb0bSTaniya Das .mnd_width = 16, 520*1c9efb0bSTaniya Das .hid_width = 5, 521*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_1, 522*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_gp1_clk_src, 523*1c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 524*1c9efb0bSTaniya Das .name = "gcc_gp1_clk_src", 525*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_1, 526*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_1), 527*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 528*1c9efb0bSTaniya Das }, 529*1c9efb0bSTaniya Das }; 530*1c9efb0bSTaniya Das 531*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_gp2_clk_src = { 532*1c9efb0bSTaniya Das .cmd_rcgr = 0x75004, 533*1c9efb0bSTaniya Das .mnd_width = 16, 534*1c9efb0bSTaniya Das .hid_width = 5, 535*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_1, 536*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_gp1_clk_src, 537*1c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 538*1c9efb0bSTaniya Das .name = "gcc_gp2_clk_src", 539*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_1, 540*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_1), 541*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 542*1c9efb0bSTaniya Das }, 543*1c9efb0bSTaniya Das }; 544*1c9efb0bSTaniya Das 545*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_gp3_clk_src = { 546*1c9efb0bSTaniya Das .cmd_rcgr = 0x76004, 547*1c9efb0bSTaniya Das .mnd_width = 16, 548*1c9efb0bSTaniya Das .hid_width = 5, 549*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_1, 550*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_gp1_clk_src, 551*1c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 552*1c9efb0bSTaniya Das .name = "gcc_gp3_clk_src", 553*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_1, 554*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_1), 555*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 556*1c9efb0bSTaniya Das }, 557*1c9efb0bSTaniya Das }; 558*1c9efb0bSTaniya Das 559*1c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 560*1c9efb0bSTaniya Das F(19200000, P_BI_TCXO, 1, 0, 0), 561*1c9efb0bSTaniya Das { } 562*1c9efb0bSTaniya Das }; 563*1c9efb0bSTaniya Das 564*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 565*1c9efb0bSTaniya Das .cmd_rcgr = 0x9d068, 566*1c9efb0bSTaniya Das .mnd_width = 16, 567*1c9efb0bSTaniya Das .hid_width = 5, 568*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_3, 569*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 570*1c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 571*1c9efb0bSTaniya Das .name = "gcc_pcie_0_aux_clk_src", 572*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_3, 573*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_3), 574*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 575*1c9efb0bSTaniya Das }, 576*1c9efb0bSTaniya Das }; 577*1c9efb0bSTaniya Das 578*1c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 579*1c9efb0bSTaniya Das F(19200000, P_BI_TCXO, 1, 0, 0), 580*1c9efb0bSTaniya Das F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 581*1c9efb0bSTaniya Das { } 582*1c9efb0bSTaniya Das }; 583*1c9efb0bSTaniya Das 584*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 585*1c9efb0bSTaniya Das .cmd_rcgr = 0x9d04c, 586*1c9efb0bSTaniya Das .mnd_width = 0, 587*1c9efb0bSTaniya Das .hid_width = 5, 588*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 589*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 590*1c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 591*1c9efb0bSTaniya Das .name = "gcc_pcie_0_phy_rchng_clk_src", 592*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 593*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 594*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 595*1c9efb0bSTaniya Das }, 596*1c9efb0bSTaniya Das }; 597*1c9efb0bSTaniya Das 598*1c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 599*1c9efb0bSTaniya Das F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 600*1c9efb0bSTaniya Das { } 601*1c9efb0bSTaniya Das }; 602*1c9efb0bSTaniya Das 603*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_pdm2_clk_src = { 604*1c9efb0bSTaniya Das .cmd_rcgr = 0x43010, 605*1c9efb0bSTaniya Das .mnd_width = 0, 606*1c9efb0bSTaniya Das .hid_width = 5, 607*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 608*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_pdm2_clk_src, 609*1c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 610*1c9efb0bSTaniya Das .name = "gcc_pdm2_clk_src", 611*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 612*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 613*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 614*1c9efb0bSTaniya Das }, 615*1c9efb0bSTaniya Das }; 616*1c9efb0bSTaniya Das 617*1c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 618*1c9efb0bSTaniya Das F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 619*1c9efb0bSTaniya Das F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 620*1c9efb0bSTaniya Das F(19200000, P_BI_TCXO, 1, 0, 0), 621*1c9efb0bSTaniya Das F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 622*1c9efb0bSTaniya Das F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 623*1c9efb0bSTaniya Das F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 624*1c9efb0bSTaniya Das F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 625*1c9efb0bSTaniya Das F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 626*1c9efb0bSTaniya Das F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 627*1c9efb0bSTaniya Das F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 628*1c9efb0bSTaniya Das { } 629*1c9efb0bSTaniya Das }; 630*1c9efb0bSTaniya Das 631*1c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 632*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s0_clk_src", 633*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 634*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 635*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 636*1c9efb0bSTaniya Das }; 637*1c9efb0bSTaniya Das 638*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 639*1c9efb0bSTaniya Das .cmd_rcgr = 0x27154, 640*1c9efb0bSTaniya Das .mnd_width = 16, 641*1c9efb0bSTaniya Das .hid_width = 5, 642*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 643*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 644*1c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 645*1c9efb0bSTaniya Das }; 646*1c9efb0bSTaniya Das 647*1c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 648*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s1_clk_src", 649*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 650*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 651*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 652*1c9efb0bSTaniya Das }; 653*1c9efb0bSTaniya Das 654*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 655*1c9efb0bSTaniya Das .cmd_rcgr = 0x27288, 656*1c9efb0bSTaniya Das .mnd_width = 16, 657*1c9efb0bSTaniya Das .hid_width = 5, 658*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 659*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 660*1c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 661*1c9efb0bSTaniya Das }; 662*1c9efb0bSTaniya Das 663*1c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 664*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s2_clk_src", 665*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 666*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 667*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 668*1c9efb0bSTaniya Das }; 669*1c9efb0bSTaniya Das 670*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 671*1c9efb0bSTaniya Das .cmd_rcgr = 0x273bc, 672*1c9efb0bSTaniya Das .mnd_width = 16, 673*1c9efb0bSTaniya Das .hid_width = 5, 674*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 675*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 676*1c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 677*1c9efb0bSTaniya Das }; 678*1c9efb0bSTaniya Das 679*1c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 680*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s3_clk_src", 681*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 682*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 683*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 684*1c9efb0bSTaniya Das }; 685*1c9efb0bSTaniya Das 686*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 687*1c9efb0bSTaniya Das .cmd_rcgr = 0x274f0, 688*1c9efb0bSTaniya Das .mnd_width = 16, 689*1c9efb0bSTaniya Das .hid_width = 5, 690*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 691*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 692*1c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 693*1c9efb0bSTaniya Das }; 694*1c9efb0bSTaniya Das 695*1c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 696*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s4_clk_src", 697*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 698*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 699*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 700*1c9efb0bSTaniya Das }; 701*1c9efb0bSTaniya Das 702*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 703*1c9efb0bSTaniya Das .cmd_rcgr = 0x27624, 704*1c9efb0bSTaniya Das .mnd_width = 16, 705*1c9efb0bSTaniya Das .hid_width = 5, 706*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 707*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 708*1c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 709*1c9efb0bSTaniya Das }; 710*1c9efb0bSTaniya Das 711*1c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] = { 712*1c9efb0bSTaniya Das F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 713*1c9efb0bSTaniya Das { } 714*1c9efb0bSTaniya Das }; 715*1c9efb0bSTaniya Das 716*1c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 717*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s5_clk_src", 718*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 719*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 720*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 721*1c9efb0bSTaniya Das }; 722*1c9efb0bSTaniya Das 723*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 724*1c9efb0bSTaniya Das .cmd_rcgr = 0x27758, 725*1c9efb0bSTaniya Das .mnd_width = 16, 726*1c9efb0bSTaniya Das .hid_width = 5, 727*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 728*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src, 729*1c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 730*1c9efb0bSTaniya Das }; 731*1c9efb0bSTaniya Das 732*1c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 733*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s6_clk_src", 734*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 735*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 736*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 737*1c9efb0bSTaniya Das }; 738*1c9efb0bSTaniya Das 739*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 740*1c9efb0bSTaniya Das .cmd_rcgr = 0x2788c, 741*1c9efb0bSTaniya Das .mnd_width = 16, 742*1c9efb0bSTaniya Das .hid_width = 5, 743*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 744*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 745*1c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 746*1c9efb0bSTaniya Das }; 747*1c9efb0bSTaniya Das 748*1c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 749*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s7_clk_src", 750*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 751*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 752*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 753*1c9efb0bSTaniya Das }; 754*1c9efb0bSTaniya Das 755*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 756*1c9efb0bSTaniya Das .cmd_rcgr = 0x279c0, 757*1c9efb0bSTaniya Das .mnd_width = 16, 758*1c9efb0bSTaniya Das .hid_width = 5, 759*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 760*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 761*1c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 762*1c9efb0bSTaniya Das }; 763*1c9efb0bSTaniya Das 764*1c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 765*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s0_clk_src", 766*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 767*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 768*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 769*1c9efb0bSTaniya Das }; 770*1c9efb0bSTaniya Das 771*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 772*1c9efb0bSTaniya Das .cmd_rcgr = 0x28154, 773*1c9efb0bSTaniya Das .mnd_width = 16, 774*1c9efb0bSTaniya Das .hid_width = 5, 775*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 776*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 777*1c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 778*1c9efb0bSTaniya Das }; 779*1c9efb0bSTaniya Das 780*1c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 781*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s1_clk_src", 782*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 783*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 784*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 785*1c9efb0bSTaniya Das }; 786*1c9efb0bSTaniya Das 787*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 788*1c9efb0bSTaniya Das .cmd_rcgr = 0x28288, 789*1c9efb0bSTaniya Das .mnd_width = 16, 790*1c9efb0bSTaniya Das .hid_width = 5, 791*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 792*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 793*1c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 794*1c9efb0bSTaniya Das }; 795*1c9efb0bSTaniya Das 796*1c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 797*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s2_clk_src", 798*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 799*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 800*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 801*1c9efb0bSTaniya Das }; 802*1c9efb0bSTaniya Das 803*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 804*1c9efb0bSTaniya Das .cmd_rcgr = 0x283bc, 805*1c9efb0bSTaniya Das .mnd_width = 16, 806*1c9efb0bSTaniya Das .hid_width = 5, 807*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 808*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 809*1c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 810*1c9efb0bSTaniya Das }; 811*1c9efb0bSTaniya Das 812*1c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 813*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s3_clk_src", 814*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 815*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 816*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 817*1c9efb0bSTaniya Das }; 818*1c9efb0bSTaniya Das 819*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 820*1c9efb0bSTaniya Das .cmd_rcgr = 0x284f0, 821*1c9efb0bSTaniya Das .mnd_width = 16, 822*1c9efb0bSTaniya Das .hid_width = 5, 823*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 824*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 825*1c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 826*1c9efb0bSTaniya Das }; 827*1c9efb0bSTaniya Das 828*1c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 829*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s4_clk_src", 830*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 831*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 832*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 833*1c9efb0bSTaniya Das }; 834*1c9efb0bSTaniya Das 835*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 836*1c9efb0bSTaniya Das .cmd_rcgr = 0x28624, 837*1c9efb0bSTaniya Das .mnd_width = 16, 838*1c9efb0bSTaniya Das .hid_width = 5, 839*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 840*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 841*1c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 842*1c9efb0bSTaniya Das }; 843*1c9efb0bSTaniya Das 844*1c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 845*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s5_clk_src", 846*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 847*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 848*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 849*1c9efb0bSTaniya Das }; 850*1c9efb0bSTaniya Das 851*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 852*1c9efb0bSTaniya Das .cmd_rcgr = 0x28758, 853*1c9efb0bSTaniya Das .mnd_width = 16, 854*1c9efb0bSTaniya Das .hid_width = 5, 855*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 856*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 857*1c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 858*1c9efb0bSTaniya Das }; 859*1c9efb0bSTaniya Das 860*1c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 861*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s6_clk_src", 862*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 863*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 864*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 865*1c9efb0bSTaniya Das }; 866*1c9efb0bSTaniya Das 867*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 868*1c9efb0bSTaniya Das .cmd_rcgr = 0x2888c, 869*1c9efb0bSTaniya Das .mnd_width = 16, 870*1c9efb0bSTaniya Das .hid_width = 5, 871*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 872*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 873*1c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 874*1c9efb0bSTaniya Das }; 875*1c9efb0bSTaniya Das 876*1c9efb0bSTaniya Das static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 877*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s7_clk_src", 878*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 879*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 880*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 881*1c9efb0bSTaniya Das }; 882*1c9efb0bSTaniya Das 883*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 884*1c9efb0bSTaniya Das .cmd_rcgr = 0x289c0, 885*1c9efb0bSTaniya Das .mnd_width = 16, 886*1c9efb0bSTaniya Das .hid_width = 5, 887*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 888*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 889*1c9efb0bSTaniya Das .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 890*1c9efb0bSTaniya Das }; 891*1c9efb0bSTaniya Das 892*1c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_sdcc5_apps_clk_src[] = { 893*1c9efb0bSTaniya Das F(144000, P_BI_TCXO, 16, 3, 25), 894*1c9efb0bSTaniya Das F(400000, P_BI_TCXO, 12, 1, 4), 895*1c9efb0bSTaniya Das F(19200000, P_BI_TCXO, 1, 0, 0), 896*1c9efb0bSTaniya Das F(20000000, P_GCC_GPLL0_OUT_MAIN, 10, 1, 3), 897*1c9efb0bSTaniya Das F(25000000, P_GCC_GPLL0_OUT_MAIN, 12, 1, 2), 898*1c9efb0bSTaniya Das F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0), 899*1c9efb0bSTaniya Das F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 900*1c9efb0bSTaniya Das F(192000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0), 901*1c9efb0bSTaniya Das F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 902*1c9efb0bSTaniya Das F(384000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0), 903*1c9efb0bSTaniya Das { } 904*1c9efb0bSTaniya Das }; 905*1c9efb0bSTaniya Das 906*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_sdcc5_apps_clk_src = { 907*1c9efb0bSTaniya Das .cmd_rcgr = 0x3b034, 908*1c9efb0bSTaniya Das .mnd_width = 8, 909*1c9efb0bSTaniya Das .hid_width = 5, 910*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_8, 911*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_sdcc5_apps_clk_src, 912*1c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 913*1c9efb0bSTaniya Das .name = "gcc_sdcc5_apps_clk_src", 914*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_8, 915*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_8), 916*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 917*1c9efb0bSTaniya Das }, 918*1c9efb0bSTaniya Das }; 919*1c9efb0bSTaniya Das 920*1c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_sdcc5_ice_core_clk_src[] = { 921*1c9efb0bSTaniya Das F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 922*1c9efb0bSTaniya Das { } 923*1c9efb0bSTaniya Das }; 924*1c9efb0bSTaniya Das 925*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src = { 926*1c9efb0bSTaniya Das .cmd_rcgr = 0x3b01c, 927*1c9efb0bSTaniya Das .mnd_width = 0, 928*1c9efb0bSTaniya Das .hid_width = 5, 929*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_2, 930*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_sdcc5_ice_core_clk_src, 931*1c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 932*1c9efb0bSTaniya Das .name = "gcc_sdcc5_ice_core_clk_src", 933*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_2, 934*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_2), 935*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 936*1c9efb0bSTaniya Das }, 937*1c9efb0bSTaniya Das }; 938*1c9efb0bSTaniya Das 939*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_sm_bus_xo_clk_src = { 940*1c9efb0bSTaniya Das .cmd_rcgr = 0x5b00c, 941*1c9efb0bSTaniya Das .mnd_width = 0, 942*1c9efb0bSTaniya Das .hid_width = 5, 943*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_2, 944*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 945*1c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 946*1c9efb0bSTaniya Das .name = "gcc_sm_bus_xo_clk_src", 947*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_2, 948*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_2), 949*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 950*1c9efb0bSTaniya Das }, 951*1c9efb0bSTaniya Das }; 952*1c9efb0bSTaniya Das 953*1c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_tsc_clk_src[] = { 954*1c9efb0bSTaniya Das F(500000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0), 955*1c9efb0bSTaniya Das { } 956*1c9efb0bSTaniya Das }; 957*1c9efb0bSTaniya Das 958*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_tsc_clk_src = { 959*1c9efb0bSTaniya Das .cmd_rcgr = 0x57010, 960*1c9efb0bSTaniya Das .mnd_width = 0, 961*1c9efb0bSTaniya Das .hid_width = 5, 962*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_9, 963*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_tsc_clk_src, 964*1c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 965*1c9efb0bSTaniya Das .name = "gcc_tsc_clk_src", 966*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_9, 967*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_9), 968*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 969*1c9efb0bSTaniya Das }, 970*1c9efb0bSTaniya Das }; 971*1c9efb0bSTaniya Das 972*1c9efb0bSTaniya Das static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 973*1c9efb0bSTaniya Das F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 974*1c9efb0bSTaniya Das F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 975*1c9efb0bSTaniya Das { } 976*1c9efb0bSTaniya Das }; 977*1c9efb0bSTaniya Das 978*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 979*1c9efb0bSTaniya Das .cmd_rcgr = 0x49028, 980*1c9efb0bSTaniya Das .mnd_width = 8, 981*1c9efb0bSTaniya Das .hid_width = 5, 982*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 983*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 984*1c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 985*1c9efb0bSTaniya Das .name = "gcc_usb30_prim_master_clk_src", 986*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 987*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 988*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 989*1c9efb0bSTaniya Das }, 990*1c9efb0bSTaniya Das }; 991*1c9efb0bSTaniya Das 992*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 993*1c9efb0bSTaniya Das .cmd_rcgr = 0x49044, 994*1c9efb0bSTaniya Das .mnd_width = 0, 995*1c9efb0bSTaniya Das .hid_width = 5, 996*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_0, 997*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 998*1c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 999*1c9efb0bSTaniya Das .name = "gcc_usb30_prim_mock_utmi_clk_src", 1000*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_0, 1001*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1002*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 1003*1c9efb0bSTaniya Das }, 1004*1c9efb0bSTaniya Das }; 1005*1c9efb0bSTaniya Das 1006*1c9efb0bSTaniya Das static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1007*1c9efb0bSTaniya Das .cmd_rcgr = 0x49070, 1008*1c9efb0bSTaniya Das .mnd_width = 0, 1009*1c9efb0bSTaniya Das .hid_width = 5, 1010*1c9efb0bSTaniya Das .parent_map = gcc_parent_map_3, 1011*1c9efb0bSTaniya Das .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1012*1c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 1013*1c9efb0bSTaniya Das .name = "gcc_usb3_prim_phy_aux_clk_src", 1014*1c9efb0bSTaniya Das .parent_data = gcc_parent_data_3, 1015*1c9efb0bSTaniya Das .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1016*1c9efb0bSTaniya Das .ops = &clk_rcg2_ops, 1017*1c9efb0bSTaniya Das }, 1018*1c9efb0bSTaniya Das }; 1019*1c9efb0bSTaniya Das 1020*1c9efb0bSTaniya Das static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1021*1c9efb0bSTaniya Das .reg = 0x4905c, 1022*1c9efb0bSTaniya Das .shift = 0, 1023*1c9efb0bSTaniya Das .width = 4, 1024*1c9efb0bSTaniya Das .clkr.hw.init = &(const struct clk_init_data) { 1025*1c9efb0bSTaniya Das .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1026*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1027*1c9efb0bSTaniya Das &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1028*1c9efb0bSTaniya Das }, 1029*1c9efb0bSTaniya Das .num_parents = 1, 1030*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1031*1c9efb0bSTaniya Das .ops = &clk_regmap_div_ro_ops, 1032*1c9efb0bSTaniya Das }, 1033*1c9efb0bSTaniya Das }; 1034*1c9efb0bSTaniya Das 1035*1c9efb0bSTaniya Das static struct clk_branch gcc_aggre_noc_ecpri_dma_clk = { 1036*1c9efb0bSTaniya Das .halt_reg = 0x92008, 1037*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1038*1c9efb0bSTaniya Das .hwcg_reg = 0x92008, 1039*1c9efb0bSTaniya Das .hwcg_bit = 1, 1040*1c9efb0bSTaniya Das .clkr = { 1041*1c9efb0bSTaniya Das .enable_reg = 0x92008, 1042*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1043*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1044*1c9efb0bSTaniya Das .name = "gcc_aggre_noc_ecpri_dma_clk", 1045*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1046*1c9efb0bSTaniya Das &gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw, 1047*1c9efb0bSTaniya Das }, 1048*1c9efb0bSTaniya Das .num_parents = 1, 1049*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1050*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1051*1c9efb0bSTaniya Das }, 1052*1c9efb0bSTaniya Das }, 1053*1c9efb0bSTaniya Das }; 1054*1c9efb0bSTaniya Das 1055*1c9efb0bSTaniya Das static struct clk_branch gcc_aggre_noc_ecpri_gsi_clk = { 1056*1c9efb0bSTaniya Das .halt_reg = 0x9201c, 1057*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1058*1c9efb0bSTaniya Das .hwcg_reg = 0x9201c, 1059*1c9efb0bSTaniya Das .hwcg_bit = 1, 1060*1c9efb0bSTaniya Das .clkr = { 1061*1c9efb0bSTaniya Das .enable_reg = 0x9201c, 1062*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1063*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1064*1c9efb0bSTaniya Das .name = "gcc_aggre_noc_ecpri_gsi_clk", 1065*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1066*1c9efb0bSTaniya Das &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, 1067*1c9efb0bSTaniya Das }, 1068*1c9efb0bSTaniya Das .num_parents = 1, 1069*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1070*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1071*1c9efb0bSTaniya Das }, 1072*1c9efb0bSTaniya Das }, 1073*1c9efb0bSTaniya Das }; 1074*1c9efb0bSTaniya Das 1075*1c9efb0bSTaniya Das static struct clk_branch gcc_boot_rom_ahb_clk = { 1076*1c9efb0bSTaniya Das .halt_reg = 0x48004, 1077*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1078*1c9efb0bSTaniya Das .hwcg_reg = 0x48004, 1079*1c9efb0bSTaniya Das .hwcg_bit = 1, 1080*1c9efb0bSTaniya Das .clkr = { 1081*1c9efb0bSTaniya Das .enable_reg = 0x62000, 1082*1c9efb0bSTaniya Das .enable_mask = BIT(10), 1083*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1084*1c9efb0bSTaniya Das .name = "gcc_boot_rom_ahb_clk", 1085*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1086*1c9efb0bSTaniya Das }, 1087*1c9efb0bSTaniya Das }, 1088*1c9efb0bSTaniya Das }; 1089*1c9efb0bSTaniya Das 1090*1c9efb0bSTaniya Das static struct clk_branch gcc_cfg_noc_ecpri_cc_ahb_clk = { 1091*1c9efb0bSTaniya Das .halt_reg = 0x3e004, 1092*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1093*1c9efb0bSTaniya Das .hwcg_reg = 0x3e004, 1094*1c9efb0bSTaniya Das .hwcg_bit = 1, 1095*1c9efb0bSTaniya Das .clkr = { 1096*1c9efb0bSTaniya Das .enable_reg = 0x3e004, 1097*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1098*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1099*1c9efb0bSTaniya Das .name = "gcc_cfg_noc_ecpri_cc_ahb_clk", 1100*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1101*1c9efb0bSTaniya Das }, 1102*1c9efb0bSTaniya Das }, 1103*1c9efb0bSTaniya Das }; 1104*1c9efb0bSTaniya Das 1105*1c9efb0bSTaniya Das static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1106*1c9efb0bSTaniya Das .halt_reg = 0x8401c, 1107*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1108*1c9efb0bSTaniya Das .hwcg_reg = 0x8401c, 1109*1c9efb0bSTaniya Das .hwcg_bit = 1, 1110*1c9efb0bSTaniya Das .clkr = { 1111*1c9efb0bSTaniya Das .enable_reg = 0x8401c, 1112*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1113*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1114*1c9efb0bSTaniya Das .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1115*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1116*1c9efb0bSTaniya Das &gcc_usb30_prim_master_clk_src.clkr.hw, 1117*1c9efb0bSTaniya Das }, 1118*1c9efb0bSTaniya Das .num_parents = 1, 1119*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1120*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1121*1c9efb0bSTaniya Das }, 1122*1c9efb0bSTaniya Das }, 1123*1c9efb0bSTaniya Das }; 1124*1c9efb0bSTaniya Das 1125*1c9efb0bSTaniya Das static struct clk_branch gcc_ddrss_ecpri_dma_clk = { 1126*1c9efb0bSTaniya Das .halt_reg = 0x54030, 1127*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1128*1c9efb0bSTaniya Das .hwcg_reg = 0x54030, 1129*1c9efb0bSTaniya Das .hwcg_bit = 1, 1130*1c9efb0bSTaniya Das .clkr = { 1131*1c9efb0bSTaniya Das .enable_reg = 0x54030, 1132*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1133*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1134*1c9efb0bSTaniya Das .name = "gcc_ddrss_ecpri_dma_clk", 1135*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1136*1c9efb0bSTaniya Das &gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw, 1137*1c9efb0bSTaniya Das }, 1138*1c9efb0bSTaniya Das .num_parents = 1, 1139*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1140*1c9efb0bSTaniya Das .ops = &clk_branch2_aon_ops, 1141*1c9efb0bSTaniya Das }, 1142*1c9efb0bSTaniya Das }, 1143*1c9efb0bSTaniya Das }; 1144*1c9efb0bSTaniya Das 1145*1c9efb0bSTaniya Das static struct clk_branch gcc_ecpri_ahb_clk = { 1146*1c9efb0bSTaniya Das .halt_reg = 0x3a008, 1147*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1148*1c9efb0bSTaniya Das .hwcg_reg = 0x3a008, 1149*1c9efb0bSTaniya Das .hwcg_bit = 1, 1150*1c9efb0bSTaniya Das .clkr = { 1151*1c9efb0bSTaniya Das .enable_reg = 0x3a008, 1152*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1153*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1154*1c9efb0bSTaniya Das .name = "gcc_ecpri_ahb_clk", 1155*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1156*1c9efb0bSTaniya Das }, 1157*1c9efb0bSTaniya Das }, 1158*1c9efb0bSTaniya Das }; 1159*1c9efb0bSTaniya Das 1160*1c9efb0bSTaniya Das static struct clk_branch gcc_ecpri_cc_gpll0_clk_src = { 1161*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_DELAY, 1162*1c9efb0bSTaniya Das .clkr = { 1163*1c9efb0bSTaniya Das .enable_reg = 0x62010, 1164*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1165*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1166*1c9efb0bSTaniya Das .name = "gcc_ecpri_cc_gpll0_clk_src", 1167*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1168*1c9efb0bSTaniya Das &gcc_gpll0.clkr.hw, 1169*1c9efb0bSTaniya Das }, 1170*1c9efb0bSTaniya Das .num_parents = 1, 1171*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1172*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1173*1c9efb0bSTaniya Das }, 1174*1c9efb0bSTaniya Das }, 1175*1c9efb0bSTaniya Das }; 1176*1c9efb0bSTaniya Das 1177*1c9efb0bSTaniya Das static struct clk_branch gcc_ecpri_cc_gpll1_even_clk_src = { 1178*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_DELAY, 1179*1c9efb0bSTaniya Das .clkr = { 1180*1c9efb0bSTaniya Das .enable_reg = 0x62010, 1181*1c9efb0bSTaniya Das .enable_mask = BIT(1), 1182*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1183*1c9efb0bSTaniya Das .name = "gcc_ecpri_cc_gpll1_even_clk_src", 1184*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1185*1c9efb0bSTaniya Das &gcc_gpll1_out_even.clkr.hw, 1186*1c9efb0bSTaniya Das }, 1187*1c9efb0bSTaniya Das .num_parents = 1, 1188*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1189*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1190*1c9efb0bSTaniya Das }, 1191*1c9efb0bSTaniya Das }, 1192*1c9efb0bSTaniya Das }; 1193*1c9efb0bSTaniya Das 1194*1c9efb0bSTaniya Das static struct clk_branch gcc_ecpri_cc_gpll2_even_clk_src = { 1195*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_DELAY, 1196*1c9efb0bSTaniya Das .clkr = { 1197*1c9efb0bSTaniya Das .enable_reg = 0x62010, 1198*1c9efb0bSTaniya Das .enable_mask = BIT(2), 1199*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1200*1c9efb0bSTaniya Das .name = "gcc_ecpri_cc_gpll2_even_clk_src", 1201*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1202*1c9efb0bSTaniya Das &gcc_gpll2_out_even.clkr.hw, 1203*1c9efb0bSTaniya Das }, 1204*1c9efb0bSTaniya Das .num_parents = 1, 1205*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1206*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1207*1c9efb0bSTaniya Das }, 1208*1c9efb0bSTaniya Das }, 1209*1c9efb0bSTaniya Das }; 1210*1c9efb0bSTaniya Das 1211*1c9efb0bSTaniya Das static struct clk_branch gcc_ecpri_cc_gpll3_clk_src = { 1212*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_DELAY, 1213*1c9efb0bSTaniya Das .clkr = { 1214*1c9efb0bSTaniya Das .enable_reg = 0x62010, 1215*1c9efb0bSTaniya Das .enable_mask = BIT(3), 1216*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1217*1c9efb0bSTaniya Das .name = "gcc_ecpri_cc_gpll3_clk_src", 1218*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1219*1c9efb0bSTaniya Das &gcc_gpll3.clkr.hw, 1220*1c9efb0bSTaniya Das }, 1221*1c9efb0bSTaniya Das .num_parents = 1, 1222*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1223*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1224*1c9efb0bSTaniya Das }, 1225*1c9efb0bSTaniya Das }, 1226*1c9efb0bSTaniya Das }; 1227*1c9efb0bSTaniya Das 1228*1c9efb0bSTaniya Das static struct clk_branch gcc_ecpri_cc_gpll4_clk_src = { 1229*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_DELAY, 1230*1c9efb0bSTaniya Das .clkr = { 1231*1c9efb0bSTaniya Das .enable_reg = 0x62010, 1232*1c9efb0bSTaniya Das .enable_mask = BIT(4), 1233*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1234*1c9efb0bSTaniya Das .name = "gcc_ecpri_cc_gpll4_clk_src", 1235*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1236*1c9efb0bSTaniya Das &gcc_gpll4.clkr.hw, 1237*1c9efb0bSTaniya Das }, 1238*1c9efb0bSTaniya Das .num_parents = 1, 1239*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1240*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1241*1c9efb0bSTaniya Das }, 1242*1c9efb0bSTaniya Das }, 1243*1c9efb0bSTaniya Das }; 1244*1c9efb0bSTaniya Das 1245*1c9efb0bSTaniya Das static struct clk_branch gcc_ecpri_cc_gpll5_even_clk_src = { 1246*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_DELAY, 1247*1c9efb0bSTaniya Das .clkr = { 1248*1c9efb0bSTaniya Das .enable_reg = 0x62010, 1249*1c9efb0bSTaniya Das .enable_mask = BIT(5), 1250*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1251*1c9efb0bSTaniya Das .name = "gcc_ecpri_cc_gpll5_even_clk_src", 1252*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1253*1c9efb0bSTaniya Das &gcc_gpll5_out_even.clkr.hw, 1254*1c9efb0bSTaniya Das }, 1255*1c9efb0bSTaniya Das .num_parents = 1, 1256*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1257*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1258*1c9efb0bSTaniya Das }, 1259*1c9efb0bSTaniya Das }, 1260*1c9efb0bSTaniya Das }; 1261*1c9efb0bSTaniya Das 1262*1c9efb0bSTaniya Das static struct clk_branch gcc_ecpri_xo_clk = { 1263*1c9efb0bSTaniya Das .halt_reg = 0x3a004, 1264*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 1265*1c9efb0bSTaniya Das .clkr = { 1266*1c9efb0bSTaniya Das .enable_reg = 0x3a004, 1267*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1268*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1269*1c9efb0bSTaniya Das .name = "gcc_ecpri_xo_clk", 1270*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1271*1c9efb0bSTaniya Das }, 1272*1c9efb0bSTaniya Das }, 1273*1c9efb0bSTaniya Das }; 1274*1c9efb0bSTaniya Das 1275*1c9efb0bSTaniya Das static struct clk_branch gcc_eth_100g_c2c_hm_apb_clk = { 1276*1c9efb0bSTaniya Das .halt_reg = 0x39010, 1277*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 1278*1c9efb0bSTaniya Das .clkr = { 1279*1c9efb0bSTaniya Das .enable_reg = 0x39010, 1280*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1281*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1282*1c9efb0bSTaniya Das .name = "gcc_eth_100g_c2c_hm_apb_clk", 1283*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1284*1c9efb0bSTaniya Das }, 1285*1c9efb0bSTaniya Das }, 1286*1c9efb0bSTaniya Das }; 1287*1c9efb0bSTaniya Das 1288*1c9efb0bSTaniya Das static struct clk_branch gcc_eth_100g_fh_hm_apb_0_clk = { 1289*1c9efb0bSTaniya Das .halt_reg = 0x39004, 1290*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 1291*1c9efb0bSTaniya Das .clkr = { 1292*1c9efb0bSTaniya Das .enable_reg = 0x39004, 1293*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1294*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1295*1c9efb0bSTaniya Das .name = "gcc_eth_100g_fh_hm_apb_0_clk", 1296*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1297*1c9efb0bSTaniya Das }, 1298*1c9efb0bSTaniya Das }, 1299*1c9efb0bSTaniya Das }; 1300*1c9efb0bSTaniya Das 1301*1c9efb0bSTaniya Das static struct clk_branch gcc_eth_100g_fh_hm_apb_1_clk = { 1302*1c9efb0bSTaniya Das .halt_reg = 0x39008, 1303*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 1304*1c9efb0bSTaniya Das .clkr = { 1305*1c9efb0bSTaniya Das .enable_reg = 0x39008, 1306*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1307*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1308*1c9efb0bSTaniya Das .name = "gcc_eth_100g_fh_hm_apb_1_clk", 1309*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1310*1c9efb0bSTaniya Das }, 1311*1c9efb0bSTaniya Das }, 1312*1c9efb0bSTaniya Das }; 1313*1c9efb0bSTaniya Das 1314*1c9efb0bSTaniya Das static struct clk_branch gcc_eth_100g_fh_hm_apb_2_clk = { 1315*1c9efb0bSTaniya Das .halt_reg = 0x3900c, 1316*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 1317*1c9efb0bSTaniya Das .clkr = { 1318*1c9efb0bSTaniya Das .enable_reg = 0x3900c, 1319*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1320*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1321*1c9efb0bSTaniya Das .name = "gcc_eth_100g_fh_hm_apb_2_clk", 1322*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1323*1c9efb0bSTaniya Das }, 1324*1c9efb0bSTaniya Das }, 1325*1c9efb0bSTaniya Das }; 1326*1c9efb0bSTaniya Das 1327*1c9efb0bSTaniya Das static struct clk_branch gcc_eth_dbg_c2c_hm_apb_clk = { 1328*1c9efb0bSTaniya Das .halt_reg = 0x39014, 1329*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 1330*1c9efb0bSTaniya Das .clkr = { 1331*1c9efb0bSTaniya Das .enable_reg = 0x39014, 1332*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1333*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1334*1c9efb0bSTaniya Das .name = "gcc_eth_dbg_c2c_hm_apb_clk", 1335*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1336*1c9efb0bSTaniya Das }, 1337*1c9efb0bSTaniya Das }, 1338*1c9efb0bSTaniya Das }; 1339*1c9efb0bSTaniya Das 1340*1c9efb0bSTaniya Das static struct clk_branch gcc_eth_dbg_snoc_axi_clk = { 1341*1c9efb0bSTaniya Das .halt_reg = 0x3901c, 1342*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1343*1c9efb0bSTaniya Das .hwcg_reg = 0x3901c, 1344*1c9efb0bSTaniya Das .hwcg_bit = 1, 1345*1c9efb0bSTaniya Das .clkr = { 1346*1c9efb0bSTaniya Das .enable_reg = 0x3901c, 1347*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1348*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1349*1c9efb0bSTaniya Das .name = "gcc_eth_dbg_snoc_axi_clk", 1350*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1351*1c9efb0bSTaniya Das }, 1352*1c9efb0bSTaniya Das }, 1353*1c9efb0bSTaniya Das }; 1354*1c9efb0bSTaniya Das 1355*1c9efb0bSTaniya Das static struct clk_branch gcc_gemnoc_pcie_qx_clk = { 1356*1c9efb0bSTaniya Das .halt_reg = 0x5402c, 1357*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1358*1c9efb0bSTaniya Das .hwcg_reg = 0x5402c, 1359*1c9efb0bSTaniya Das .hwcg_bit = 1, 1360*1c9efb0bSTaniya Das .clkr = { 1361*1c9efb0bSTaniya Das .enable_reg = 0x62008, 1362*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1363*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1364*1c9efb0bSTaniya Das .name = "gcc_gemnoc_pcie_qx_clk", 1365*1c9efb0bSTaniya Das .ops = &clk_branch2_aon_ops, 1366*1c9efb0bSTaniya Das }, 1367*1c9efb0bSTaniya Das }, 1368*1c9efb0bSTaniya Das }; 1369*1c9efb0bSTaniya Das 1370*1c9efb0bSTaniya Das static struct clk_branch gcc_gp1_clk = { 1371*1c9efb0bSTaniya Das .halt_reg = 0x74000, 1372*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 1373*1c9efb0bSTaniya Das .clkr = { 1374*1c9efb0bSTaniya Das .enable_reg = 0x74000, 1375*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1376*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1377*1c9efb0bSTaniya Das .name = "gcc_gp1_clk", 1378*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1379*1c9efb0bSTaniya Das &gcc_gp1_clk_src.clkr.hw, 1380*1c9efb0bSTaniya Das }, 1381*1c9efb0bSTaniya Das .num_parents = 1, 1382*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1383*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1384*1c9efb0bSTaniya Das }, 1385*1c9efb0bSTaniya Das }, 1386*1c9efb0bSTaniya Das }; 1387*1c9efb0bSTaniya Das 1388*1c9efb0bSTaniya Das static struct clk_branch gcc_gp2_clk = { 1389*1c9efb0bSTaniya Das .halt_reg = 0x75000, 1390*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 1391*1c9efb0bSTaniya Das .clkr = { 1392*1c9efb0bSTaniya Das .enable_reg = 0x75000, 1393*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1394*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1395*1c9efb0bSTaniya Das .name = "gcc_gp2_clk", 1396*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1397*1c9efb0bSTaniya Das &gcc_gp2_clk_src.clkr.hw, 1398*1c9efb0bSTaniya Das }, 1399*1c9efb0bSTaniya Das .num_parents = 1, 1400*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1401*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1402*1c9efb0bSTaniya Das }, 1403*1c9efb0bSTaniya Das }, 1404*1c9efb0bSTaniya Das }; 1405*1c9efb0bSTaniya Das 1406*1c9efb0bSTaniya Das static struct clk_branch gcc_gp3_clk = { 1407*1c9efb0bSTaniya Das .halt_reg = 0x76000, 1408*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 1409*1c9efb0bSTaniya Das .clkr = { 1410*1c9efb0bSTaniya Das .enable_reg = 0x76000, 1411*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1412*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1413*1c9efb0bSTaniya Das .name = "gcc_gp3_clk", 1414*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1415*1c9efb0bSTaniya Das &gcc_gp3_clk_src.clkr.hw, 1416*1c9efb0bSTaniya Das }, 1417*1c9efb0bSTaniya Das .num_parents = 1, 1418*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1419*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1420*1c9efb0bSTaniya Das }, 1421*1c9efb0bSTaniya Das }, 1422*1c9efb0bSTaniya Das }; 1423*1c9efb0bSTaniya Das 1424*1c9efb0bSTaniya Das static struct clk_branch gcc_pcie_0_aux_clk = { 1425*1c9efb0bSTaniya Das .halt_reg = 0x9d030, 1426*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1427*1c9efb0bSTaniya Das .hwcg_reg = 0x9d030, 1428*1c9efb0bSTaniya Das .hwcg_bit = 1, 1429*1c9efb0bSTaniya Das .clkr = { 1430*1c9efb0bSTaniya Das .enable_reg = 0x62000, 1431*1c9efb0bSTaniya Das .enable_mask = BIT(29), 1432*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1433*1c9efb0bSTaniya Das .name = "gcc_pcie_0_aux_clk", 1434*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1435*1c9efb0bSTaniya Das &gcc_pcie_0_aux_clk_src.clkr.hw, 1436*1c9efb0bSTaniya Das }, 1437*1c9efb0bSTaniya Das .num_parents = 1, 1438*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1439*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1440*1c9efb0bSTaniya Das }, 1441*1c9efb0bSTaniya Das }, 1442*1c9efb0bSTaniya Das }; 1443*1c9efb0bSTaniya Das 1444*1c9efb0bSTaniya Das static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1445*1c9efb0bSTaniya Das .halt_reg = 0x9d02c, 1446*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1447*1c9efb0bSTaniya Das .hwcg_reg = 0x9d02c, 1448*1c9efb0bSTaniya Das .hwcg_bit = 1, 1449*1c9efb0bSTaniya Das .clkr = { 1450*1c9efb0bSTaniya Das .enable_reg = 0x62000, 1451*1c9efb0bSTaniya Das .enable_mask = BIT(28), 1452*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1453*1c9efb0bSTaniya Das .name = "gcc_pcie_0_cfg_ahb_clk", 1454*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1455*1c9efb0bSTaniya Das }, 1456*1c9efb0bSTaniya Das }, 1457*1c9efb0bSTaniya Das }; 1458*1c9efb0bSTaniya Das 1459*1c9efb0bSTaniya Das static struct clk_branch gcc_pcie_0_clkref_en = { 1460*1c9efb0bSTaniya Das .halt_reg = 0x9c004, 1461*1c9efb0bSTaniya Das .halt_bit = 31, 1462*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_ENABLE, 1463*1c9efb0bSTaniya Das .clkr = { 1464*1c9efb0bSTaniya Das .enable_reg = 0x9c004, 1465*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1466*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1467*1c9efb0bSTaniya Das .name = "gcc_pcie_0_clkref_en", 1468*1c9efb0bSTaniya Das .ops = &clk_branch_ops, 1469*1c9efb0bSTaniya Das }, 1470*1c9efb0bSTaniya Das }, 1471*1c9efb0bSTaniya Das }; 1472*1c9efb0bSTaniya Das 1473*1c9efb0bSTaniya Das static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1474*1c9efb0bSTaniya Das .halt_reg = 0x9d024, 1475*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_SKIP, 1476*1c9efb0bSTaniya Das .hwcg_reg = 0x9d024, 1477*1c9efb0bSTaniya Das .hwcg_bit = 1, 1478*1c9efb0bSTaniya Das .clkr = { 1479*1c9efb0bSTaniya Das .enable_reg = 0x62000, 1480*1c9efb0bSTaniya Das .enable_mask = BIT(27), 1481*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1482*1c9efb0bSTaniya Das .name = "gcc_pcie_0_mstr_axi_clk", 1483*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1484*1c9efb0bSTaniya Das }, 1485*1c9efb0bSTaniya Das }, 1486*1c9efb0bSTaniya Das }; 1487*1c9efb0bSTaniya Das 1488*1c9efb0bSTaniya Das static struct clk_branch gcc_pcie_0_phy_aux_clk = { 1489*1c9efb0bSTaniya Das .halt_reg = 0x9d038, 1490*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1491*1c9efb0bSTaniya Das .hwcg_reg = 0x9d038, 1492*1c9efb0bSTaniya Das .hwcg_bit = 1, 1493*1c9efb0bSTaniya Das .clkr = { 1494*1c9efb0bSTaniya Das .enable_reg = 0x62000, 1495*1c9efb0bSTaniya Das .enable_mask = BIT(24), 1496*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1497*1c9efb0bSTaniya Das .name = "gcc_pcie_0_phy_aux_clk", 1498*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1499*1c9efb0bSTaniya Das &gcc_pcie_0_phy_aux_clk_src.clkr.hw, 1500*1c9efb0bSTaniya Das }, 1501*1c9efb0bSTaniya Das .num_parents = 1, 1502*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1503*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1504*1c9efb0bSTaniya Das }, 1505*1c9efb0bSTaniya Das }, 1506*1c9efb0bSTaniya Das }; 1507*1c9efb0bSTaniya Das 1508*1c9efb0bSTaniya Das static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 1509*1c9efb0bSTaniya Das .halt_reg = 0x9d048, 1510*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1511*1c9efb0bSTaniya Das .hwcg_reg = 0x9d048, 1512*1c9efb0bSTaniya Das .hwcg_bit = 1, 1513*1c9efb0bSTaniya Das .clkr = { 1514*1c9efb0bSTaniya Das .enable_reg = 0x62000, 1515*1c9efb0bSTaniya Das .enable_mask = BIT(23), 1516*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1517*1c9efb0bSTaniya Das .name = "gcc_pcie_0_phy_rchng_clk", 1518*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1519*1c9efb0bSTaniya Das &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1520*1c9efb0bSTaniya Das }, 1521*1c9efb0bSTaniya Das .num_parents = 1, 1522*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1523*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1524*1c9efb0bSTaniya Das }, 1525*1c9efb0bSTaniya Das }, 1526*1c9efb0bSTaniya Das }; 1527*1c9efb0bSTaniya Das 1528*1c9efb0bSTaniya Das static struct clk_branch gcc_pcie_0_pipe_clk = { 1529*1c9efb0bSTaniya Das .halt_reg = 0x9d040, 1530*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1531*1c9efb0bSTaniya Das .hwcg_reg = 0x9d040, 1532*1c9efb0bSTaniya Das .hwcg_bit = 1, 1533*1c9efb0bSTaniya Das .clkr = { 1534*1c9efb0bSTaniya Das .enable_reg = 0x62000, 1535*1c9efb0bSTaniya Das .enable_mask = BIT(30), 1536*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1537*1c9efb0bSTaniya Das .name = "gcc_pcie_0_pipe_clk", 1538*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1539*1c9efb0bSTaniya Das &gcc_pcie_0_pipe_clk_src.clkr.hw, 1540*1c9efb0bSTaniya Das }, 1541*1c9efb0bSTaniya Das .num_parents = 1, 1542*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1543*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1544*1c9efb0bSTaniya Das }, 1545*1c9efb0bSTaniya Das }, 1546*1c9efb0bSTaniya Das }; 1547*1c9efb0bSTaniya Das 1548*1c9efb0bSTaniya Das static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1549*1c9efb0bSTaniya Das .halt_reg = 0x9d01c, 1550*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1551*1c9efb0bSTaniya Das .hwcg_reg = 0x9d01c, 1552*1c9efb0bSTaniya Das .hwcg_bit = 1, 1553*1c9efb0bSTaniya Das .clkr = { 1554*1c9efb0bSTaniya Das .enable_reg = 0x62000, 1555*1c9efb0bSTaniya Das .enable_mask = BIT(26), 1556*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1557*1c9efb0bSTaniya Das .name = "gcc_pcie_0_slv_axi_clk", 1558*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1559*1c9efb0bSTaniya Das }, 1560*1c9efb0bSTaniya Das }, 1561*1c9efb0bSTaniya Das }; 1562*1c9efb0bSTaniya Das 1563*1c9efb0bSTaniya Das static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1564*1c9efb0bSTaniya Das .halt_reg = 0x9d018, 1565*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1566*1c9efb0bSTaniya Das .hwcg_reg = 0x9d018, 1567*1c9efb0bSTaniya Das .hwcg_bit = 1, 1568*1c9efb0bSTaniya Das .clkr = { 1569*1c9efb0bSTaniya Das .enable_reg = 0x62000, 1570*1c9efb0bSTaniya Das .enable_mask = BIT(25), 1571*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1572*1c9efb0bSTaniya Das .name = "gcc_pcie_0_slv_q2a_axi_clk", 1573*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1574*1c9efb0bSTaniya Das }, 1575*1c9efb0bSTaniya Das }, 1576*1c9efb0bSTaniya Das }; 1577*1c9efb0bSTaniya Das 1578*1c9efb0bSTaniya Das static struct clk_branch gcc_pdm2_clk = { 1579*1c9efb0bSTaniya Das .halt_reg = 0x4300c, 1580*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 1581*1c9efb0bSTaniya Das .clkr = { 1582*1c9efb0bSTaniya Das .enable_reg = 0x4300c, 1583*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1584*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1585*1c9efb0bSTaniya Das .name = "gcc_pdm2_clk", 1586*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1587*1c9efb0bSTaniya Das &gcc_pdm2_clk_src.clkr.hw, 1588*1c9efb0bSTaniya Das }, 1589*1c9efb0bSTaniya Das .num_parents = 1, 1590*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1591*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1592*1c9efb0bSTaniya Das }, 1593*1c9efb0bSTaniya Das }, 1594*1c9efb0bSTaniya Das }; 1595*1c9efb0bSTaniya Das 1596*1c9efb0bSTaniya Das static struct clk_branch gcc_pdm_ahb_clk = { 1597*1c9efb0bSTaniya Das .halt_reg = 0x43004, 1598*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1599*1c9efb0bSTaniya Das .hwcg_reg = 0x43004, 1600*1c9efb0bSTaniya Das .hwcg_bit = 1, 1601*1c9efb0bSTaniya Das .clkr = { 1602*1c9efb0bSTaniya Das .enable_reg = 0x43004, 1603*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1604*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1605*1c9efb0bSTaniya Das .name = "gcc_pdm_ahb_clk", 1606*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1607*1c9efb0bSTaniya Das }, 1608*1c9efb0bSTaniya Das }, 1609*1c9efb0bSTaniya Das }; 1610*1c9efb0bSTaniya Das 1611*1c9efb0bSTaniya Das static struct clk_branch gcc_pdm_xo4_clk = { 1612*1c9efb0bSTaniya Das .halt_reg = 0x43008, 1613*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 1614*1c9efb0bSTaniya Das .clkr = { 1615*1c9efb0bSTaniya Das .enable_reg = 0x43008, 1616*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1617*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1618*1c9efb0bSTaniya Das .name = "gcc_pdm_xo4_clk", 1619*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1620*1c9efb0bSTaniya Das }, 1621*1c9efb0bSTaniya Das }, 1622*1c9efb0bSTaniya Das }; 1623*1c9efb0bSTaniya Das 1624*1c9efb0bSTaniya Das static struct clk_branch gcc_qmip_anoc_pcie_clk = { 1625*1c9efb0bSTaniya Das .halt_reg = 0x84044, 1626*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1627*1c9efb0bSTaniya Das .hwcg_reg = 0x84044, 1628*1c9efb0bSTaniya Das .hwcg_bit = 1, 1629*1c9efb0bSTaniya Das .clkr = { 1630*1c9efb0bSTaniya Das .enable_reg = 0x84044, 1631*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1632*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1633*1c9efb0bSTaniya Das .name = "gcc_qmip_anoc_pcie_clk", 1634*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1635*1c9efb0bSTaniya Das }, 1636*1c9efb0bSTaniya Das }, 1637*1c9efb0bSTaniya Das }; 1638*1c9efb0bSTaniya Das 1639*1c9efb0bSTaniya Das static struct clk_branch gcc_qmip_ecpri_dma0_clk = { 1640*1c9efb0bSTaniya Das .halt_reg = 0x84038, 1641*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1642*1c9efb0bSTaniya Das .hwcg_reg = 0x84038, 1643*1c9efb0bSTaniya Das .hwcg_bit = 1, 1644*1c9efb0bSTaniya Das .clkr = { 1645*1c9efb0bSTaniya Das .enable_reg = 0x84038, 1646*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1647*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1648*1c9efb0bSTaniya Das .name = "gcc_qmip_ecpri_dma0_clk", 1649*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1650*1c9efb0bSTaniya Das }, 1651*1c9efb0bSTaniya Das }, 1652*1c9efb0bSTaniya Das }; 1653*1c9efb0bSTaniya Das 1654*1c9efb0bSTaniya Das static struct clk_branch gcc_qmip_ecpri_dma1_clk = { 1655*1c9efb0bSTaniya Das .halt_reg = 0x8403c, 1656*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1657*1c9efb0bSTaniya Das .hwcg_reg = 0x8403c, 1658*1c9efb0bSTaniya Das .hwcg_bit = 1, 1659*1c9efb0bSTaniya Das .clkr = { 1660*1c9efb0bSTaniya Das .enable_reg = 0x8403c, 1661*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1662*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1663*1c9efb0bSTaniya Das .name = "gcc_qmip_ecpri_dma1_clk", 1664*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1665*1c9efb0bSTaniya Das }, 1666*1c9efb0bSTaniya Das }, 1667*1c9efb0bSTaniya Das }; 1668*1c9efb0bSTaniya Das 1669*1c9efb0bSTaniya Das static struct clk_branch gcc_qmip_ecpri_gsi_clk = { 1670*1c9efb0bSTaniya Das .halt_reg = 0x84040, 1671*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1672*1c9efb0bSTaniya Das .hwcg_reg = 0x84040, 1673*1c9efb0bSTaniya Das .hwcg_bit = 1, 1674*1c9efb0bSTaniya Das .clkr = { 1675*1c9efb0bSTaniya Das .enable_reg = 0x84040, 1676*1c9efb0bSTaniya Das .enable_mask = BIT(0), 1677*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1678*1c9efb0bSTaniya Das .name = "gcc_qmip_ecpri_gsi_clk", 1679*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1680*1c9efb0bSTaniya Das }, 1681*1c9efb0bSTaniya Das }, 1682*1c9efb0bSTaniya Das }; 1683*1c9efb0bSTaniya Das 1684*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 1685*1c9efb0bSTaniya Das .halt_reg = 0x27018, 1686*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1687*1c9efb0bSTaniya Das .clkr = { 1688*1c9efb0bSTaniya Das .enable_reg = 0x62008, 1689*1c9efb0bSTaniya Das .enable_mask = BIT(9), 1690*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1691*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_core_2x_clk", 1692*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1693*1c9efb0bSTaniya Das }, 1694*1c9efb0bSTaniya Das }, 1695*1c9efb0bSTaniya Das }; 1696*1c9efb0bSTaniya Das 1697*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap0_core_clk = { 1698*1c9efb0bSTaniya Das .halt_reg = 0x2700c, 1699*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1700*1c9efb0bSTaniya Das .clkr = { 1701*1c9efb0bSTaniya Das .enable_reg = 0x62008, 1702*1c9efb0bSTaniya Das .enable_mask = BIT(8), 1703*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1704*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_core_clk", 1705*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1706*1c9efb0bSTaniya Das }, 1707*1c9efb0bSTaniya Das }, 1708*1c9efb0bSTaniya Das }; 1709*1c9efb0bSTaniya Das 1710*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 1711*1c9efb0bSTaniya Das .halt_reg = 0x2714c, 1712*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1713*1c9efb0bSTaniya Das .clkr = { 1714*1c9efb0bSTaniya Das .enable_reg = 0x62008, 1715*1c9efb0bSTaniya Das .enable_mask = BIT(10), 1716*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1717*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s0_clk", 1718*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1719*1c9efb0bSTaniya Das &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 1720*1c9efb0bSTaniya Das }, 1721*1c9efb0bSTaniya Das .num_parents = 1, 1722*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1723*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1724*1c9efb0bSTaniya Das }, 1725*1c9efb0bSTaniya Das }, 1726*1c9efb0bSTaniya Das }; 1727*1c9efb0bSTaniya Das 1728*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 1729*1c9efb0bSTaniya Das .halt_reg = 0x27280, 1730*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1731*1c9efb0bSTaniya Das .clkr = { 1732*1c9efb0bSTaniya Das .enable_reg = 0x62008, 1733*1c9efb0bSTaniya Das .enable_mask = BIT(11), 1734*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1735*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s1_clk", 1736*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1737*1c9efb0bSTaniya Das &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 1738*1c9efb0bSTaniya Das }, 1739*1c9efb0bSTaniya Das .num_parents = 1, 1740*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1741*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1742*1c9efb0bSTaniya Das }, 1743*1c9efb0bSTaniya Das }, 1744*1c9efb0bSTaniya Das }; 1745*1c9efb0bSTaniya Das 1746*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 1747*1c9efb0bSTaniya Das .halt_reg = 0x273b4, 1748*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1749*1c9efb0bSTaniya Das .clkr = { 1750*1c9efb0bSTaniya Das .enable_reg = 0x62008, 1751*1c9efb0bSTaniya Das .enable_mask = BIT(12), 1752*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1753*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s2_clk", 1754*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1755*1c9efb0bSTaniya Das &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 1756*1c9efb0bSTaniya Das }, 1757*1c9efb0bSTaniya Das .num_parents = 1, 1758*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1759*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1760*1c9efb0bSTaniya Das }, 1761*1c9efb0bSTaniya Das }, 1762*1c9efb0bSTaniya Das }; 1763*1c9efb0bSTaniya Das 1764*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 1765*1c9efb0bSTaniya Das .halt_reg = 0x274e8, 1766*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1767*1c9efb0bSTaniya Das .clkr = { 1768*1c9efb0bSTaniya Das .enable_reg = 0x62008, 1769*1c9efb0bSTaniya Das .enable_mask = BIT(13), 1770*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1771*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s3_clk", 1772*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1773*1c9efb0bSTaniya Das &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 1774*1c9efb0bSTaniya Das }, 1775*1c9efb0bSTaniya Das .num_parents = 1, 1776*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1777*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1778*1c9efb0bSTaniya Das }, 1779*1c9efb0bSTaniya Das }, 1780*1c9efb0bSTaniya Das }; 1781*1c9efb0bSTaniya Das 1782*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 1783*1c9efb0bSTaniya Das .halt_reg = 0x2761c, 1784*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1785*1c9efb0bSTaniya Das .clkr = { 1786*1c9efb0bSTaniya Das .enable_reg = 0x62008, 1787*1c9efb0bSTaniya Das .enable_mask = BIT(14), 1788*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1789*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s4_clk", 1790*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1791*1c9efb0bSTaniya Das &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 1792*1c9efb0bSTaniya Das }, 1793*1c9efb0bSTaniya Das .num_parents = 1, 1794*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1795*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1796*1c9efb0bSTaniya Das }, 1797*1c9efb0bSTaniya Das }, 1798*1c9efb0bSTaniya Das }; 1799*1c9efb0bSTaniya Das 1800*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 1801*1c9efb0bSTaniya Das .halt_reg = 0x27750, 1802*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1803*1c9efb0bSTaniya Das .clkr = { 1804*1c9efb0bSTaniya Das .enable_reg = 0x62008, 1805*1c9efb0bSTaniya Das .enable_mask = BIT(15), 1806*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1807*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s5_clk", 1808*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1809*1c9efb0bSTaniya Das &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 1810*1c9efb0bSTaniya Das }, 1811*1c9efb0bSTaniya Das .num_parents = 1, 1812*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1813*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1814*1c9efb0bSTaniya Das }, 1815*1c9efb0bSTaniya Das }, 1816*1c9efb0bSTaniya Das }; 1817*1c9efb0bSTaniya Das 1818*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 1819*1c9efb0bSTaniya Das .halt_reg = 0x27884, 1820*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1821*1c9efb0bSTaniya Das .clkr = { 1822*1c9efb0bSTaniya Das .enable_reg = 0x62008, 1823*1c9efb0bSTaniya Das .enable_mask = BIT(16), 1824*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1825*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s6_clk", 1826*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1827*1c9efb0bSTaniya Das &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 1828*1c9efb0bSTaniya Das }, 1829*1c9efb0bSTaniya Das .num_parents = 1, 1830*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1831*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1832*1c9efb0bSTaniya Das }, 1833*1c9efb0bSTaniya Das }, 1834*1c9efb0bSTaniya Das }; 1835*1c9efb0bSTaniya Das 1836*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 1837*1c9efb0bSTaniya Das .halt_reg = 0x279b8, 1838*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1839*1c9efb0bSTaniya Das .clkr = { 1840*1c9efb0bSTaniya Das .enable_reg = 0x62008, 1841*1c9efb0bSTaniya Das .enable_mask = BIT(17), 1842*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1843*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap0_s7_clk", 1844*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1845*1c9efb0bSTaniya Das &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 1846*1c9efb0bSTaniya Das }, 1847*1c9efb0bSTaniya Das .num_parents = 1, 1848*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1849*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1850*1c9efb0bSTaniya Das }, 1851*1c9efb0bSTaniya Das }, 1852*1c9efb0bSTaniya Das }; 1853*1c9efb0bSTaniya Das 1854*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 1855*1c9efb0bSTaniya Das .halt_reg = 0x28018, 1856*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1857*1c9efb0bSTaniya Das .clkr = { 1858*1c9efb0bSTaniya Das .enable_reg = 0x62008, 1859*1c9efb0bSTaniya Das .enable_mask = BIT(18), 1860*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1861*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_core_2x_clk", 1862*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1863*1c9efb0bSTaniya Das }, 1864*1c9efb0bSTaniya Das }, 1865*1c9efb0bSTaniya Das }; 1866*1c9efb0bSTaniya Das 1867*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap1_core_clk = { 1868*1c9efb0bSTaniya Das .halt_reg = 0x2800c, 1869*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1870*1c9efb0bSTaniya Das .clkr = { 1871*1c9efb0bSTaniya Das .enable_reg = 0x62008, 1872*1c9efb0bSTaniya Das .enable_mask = BIT(19), 1873*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1874*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_core_clk", 1875*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1876*1c9efb0bSTaniya Das }, 1877*1c9efb0bSTaniya Das }, 1878*1c9efb0bSTaniya Das }; 1879*1c9efb0bSTaniya Das 1880*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 1881*1c9efb0bSTaniya Das .halt_reg = 0x2814c, 1882*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1883*1c9efb0bSTaniya Das .clkr = { 1884*1c9efb0bSTaniya Das .enable_reg = 0x62008, 1885*1c9efb0bSTaniya Das .enable_mask = BIT(22), 1886*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1887*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s0_clk", 1888*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1889*1c9efb0bSTaniya Das &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 1890*1c9efb0bSTaniya Das }, 1891*1c9efb0bSTaniya Das .num_parents = 1, 1892*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1893*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1894*1c9efb0bSTaniya Das }, 1895*1c9efb0bSTaniya Das }, 1896*1c9efb0bSTaniya Das }; 1897*1c9efb0bSTaniya Das 1898*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 1899*1c9efb0bSTaniya Das .halt_reg = 0x28280, 1900*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1901*1c9efb0bSTaniya Das .clkr = { 1902*1c9efb0bSTaniya Das .enable_reg = 0x62008, 1903*1c9efb0bSTaniya Das .enable_mask = BIT(23), 1904*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1905*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s1_clk", 1906*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1907*1c9efb0bSTaniya Das &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 1908*1c9efb0bSTaniya Das }, 1909*1c9efb0bSTaniya Das .num_parents = 1, 1910*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1911*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1912*1c9efb0bSTaniya Das }, 1913*1c9efb0bSTaniya Das }, 1914*1c9efb0bSTaniya Das }; 1915*1c9efb0bSTaniya Das 1916*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 1917*1c9efb0bSTaniya Das .halt_reg = 0x283b4, 1918*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1919*1c9efb0bSTaniya Das .clkr = { 1920*1c9efb0bSTaniya Das .enable_reg = 0x62008, 1921*1c9efb0bSTaniya Das .enable_mask = BIT(24), 1922*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1923*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s2_clk", 1924*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1925*1c9efb0bSTaniya Das &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 1926*1c9efb0bSTaniya Das }, 1927*1c9efb0bSTaniya Das .num_parents = 1, 1928*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1929*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1930*1c9efb0bSTaniya Das }, 1931*1c9efb0bSTaniya Das }, 1932*1c9efb0bSTaniya Das }; 1933*1c9efb0bSTaniya Das 1934*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 1935*1c9efb0bSTaniya Das .halt_reg = 0x284e8, 1936*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1937*1c9efb0bSTaniya Das .clkr = { 1938*1c9efb0bSTaniya Das .enable_reg = 0x62008, 1939*1c9efb0bSTaniya Das .enable_mask = BIT(25), 1940*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1941*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s3_clk", 1942*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1943*1c9efb0bSTaniya Das &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 1944*1c9efb0bSTaniya Das }, 1945*1c9efb0bSTaniya Das .num_parents = 1, 1946*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1947*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1948*1c9efb0bSTaniya Das }, 1949*1c9efb0bSTaniya Das }, 1950*1c9efb0bSTaniya Das }; 1951*1c9efb0bSTaniya Das 1952*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 1953*1c9efb0bSTaniya Das .halt_reg = 0x2861c, 1954*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1955*1c9efb0bSTaniya Das .clkr = { 1956*1c9efb0bSTaniya Das .enable_reg = 0x62008, 1957*1c9efb0bSTaniya Das .enable_mask = BIT(26), 1958*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1959*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s4_clk", 1960*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1961*1c9efb0bSTaniya Das &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 1962*1c9efb0bSTaniya Das }, 1963*1c9efb0bSTaniya Das .num_parents = 1, 1964*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1965*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1966*1c9efb0bSTaniya Das }, 1967*1c9efb0bSTaniya Das }, 1968*1c9efb0bSTaniya Das }; 1969*1c9efb0bSTaniya Das 1970*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 1971*1c9efb0bSTaniya Das .halt_reg = 0x28750, 1972*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1973*1c9efb0bSTaniya Das .clkr = { 1974*1c9efb0bSTaniya Das .enable_reg = 0x62008, 1975*1c9efb0bSTaniya Das .enable_mask = BIT(27), 1976*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1977*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s5_clk", 1978*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1979*1c9efb0bSTaniya Das &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 1980*1c9efb0bSTaniya Das }, 1981*1c9efb0bSTaniya Das .num_parents = 1, 1982*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 1983*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 1984*1c9efb0bSTaniya Das }, 1985*1c9efb0bSTaniya Das }, 1986*1c9efb0bSTaniya Das }; 1987*1c9efb0bSTaniya Das 1988*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 1989*1c9efb0bSTaniya Das .halt_reg = 0x28884, 1990*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 1991*1c9efb0bSTaniya Das .clkr = { 1992*1c9efb0bSTaniya Das .enable_reg = 0x62008, 1993*1c9efb0bSTaniya Das .enable_mask = BIT(28), 1994*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 1995*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s6_clk", 1996*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 1997*1c9efb0bSTaniya Das &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 1998*1c9efb0bSTaniya Das }, 1999*1c9efb0bSTaniya Das .num_parents = 1, 2000*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 2001*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2002*1c9efb0bSTaniya Das }, 2003*1c9efb0bSTaniya Das }, 2004*1c9efb0bSTaniya Das }; 2005*1c9efb0bSTaniya Das 2006*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 2007*1c9efb0bSTaniya Das .halt_reg = 0x289b8, 2008*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 2009*1c9efb0bSTaniya Das .clkr = { 2010*1c9efb0bSTaniya Das .enable_reg = 0x62008, 2011*1c9efb0bSTaniya Das .enable_mask = BIT(29), 2012*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2013*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap1_s7_clk", 2014*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 2015*1c9efb0bSTaniya Das &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 2016*1c9efb0bSTaniya Das }, 2017*1c9efb0bSTaniya Das .num_parents = 1, 2018*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 2019*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2020*1c9efb0bSTaniya Das }, 2021*1c9efb0bSTaniya Das }, 2022*1c9efb0bSTaniya Das }; 2023*1c9efb0bSTaniya Das 2024*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2025*1c9efb0bSTaniya Das .halt_reg = 0x27004, 2026*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 2027*1c9efb0bSTaniya Das .hwcg_reg = 0x27004, 2028*1c9efb0bSTaniya Das .hwcg_bit = 1, 2029*1c9efb0bSTaniya Das .clkr = { 2030*1c9efb0bSTaniya Das .enable_reg = 0x62008, 2031*1c9efb0bSTaniya Das .enable_mask = BIT(6), 2032*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2033*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2034*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2035*1c9efb0bSTaniya Das }, 2036*1c9efb0bSTaniya Das }, 2037*1c9efb0bSTaniya Das }; 2038*1c9efb0bSTaniya Das 2039*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2040*1c9efb0bSTaniya Das .halt_reg = 0x27008, 2041*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 2042*1c9efb0bSTaniya Das .hwcg_reg = 0x27008, 2043*1c9efb0bSTaniya Das .hwcg_bit = 1, 2044*1c9efb0bSTaniya Das .clkr = { 2045*1c9efb0bSTaniya Das .enable_reg = 0x62008, 2046*1c9efb0bSTaniya Das .enable_mask = BIT(7), 2047*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2048*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2049*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2050*1c9efb0bSTaniya Das }, 2051*1c9efb0bSTaniya Das }, 2052*1c9efb0bSTaniya Das }; 2053*1c9efb0bSTaniya Das 2054*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2055*1c9efb0bSTaniya Das .halt_reg = 0x28004, 2056*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 2057*1c9efb0bSTaniya Das .hwcg_reg = 0x28004, 2058*1c9efb0bSTaniya Das .hwcg_bit = 1, 2059*1c9efb0bSTaniya Das .clkr = { 2060*1c9efb0bSTaniya Das .enable_reg = 0x62008, 2061*1c9efb0bSTaniya Das .enable_mask = BIT(20), 2062*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2063*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2064*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2065*1c9efb0bSTaniya Das }, 2066*1c9efb0bSTaniya Das }, 2067*1c9efb0bSTaniya Das }; 2068*1c9efb0bSTaniya Das 2069*1c9efb0bSTaniya Das static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2070*1c9efb0bSTaniya Das .halt_reg = 0x28008, 2071*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_VOTED, 2072*1c9efb0bSTaniya Das .hwcg_reg = 0x28008, 2073*1c9efb0bSTaniya Das .hwcg_bit = 1, 2074*1c9efb0bSTaniya Das .clkr = { 2075*1c9efb0bSTaniya Das .enable_reg = 0x62008, 2076*1c9efb0bSTaniya Das .enable_mask = BIT(21), 2077*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2078*1c9efb0bSTaniya Das .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2079*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2080*1c9efb0bSTaniya Das }, 2081*1c9efb0bSTaniya Das }, 2082*1c9efb0bSTaniya Das }; 2083*1c9efb0bSTaniya Das 2084*1c9efb0bSTaniya Das static struct clk_branch gcc_sdcc5_ahb_clk = { 2085*1c9efb0bSTaniya Das .halt_reg = 0x3b00c, 2086*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 2087*1c9efb0bSTaniya Das .clkr = { 2088*1c9efb0bSTaniya Das .enable_reg = 0x3b00c, 2089*1c9efb0bSTaniya Das .enable_mask = BIT(0), 2090*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2091*1c9efb0bSTaniya Das .name = "gcc_sdcc5_ahb_clk", 2092*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2093*1c9efb0bSTaniya Das }, 2094*1c9efb0bSTaniya Das }, 2095*1c9efb0bSTaniya Das }; 2096*1c9efb0bSTaniya Das 2097*1c9efb0bSTaniya Das static struct clk_branch gcc_sdcc5_apps_clk = { 2098*1c9efb0bSTaniya Das .halt_reg = 0x3b004, 2099*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 2100*1c9efb0bSTaniya Das .clkr = { 2101*1c9efb0bSTaniya Das .enable_reg = 0x3b004, 2102*1c9efb0bSTaniya Das .enable_mask = BIT(0), 2103*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2104*1c9efb0bSTaniya Das .name = "gcc_sdcc5_apps_clk", 2105*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 2106*1c9efb0bSTaniya Das &gcc_sdcc5_apps_clk_src.clkr.hw, 2107*1c9efb0bSTaniya Das }, 2108*1c9efb0bSTaniya Das .num_parents = 1, 2109*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 2110*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2111*1c9efb0bSTaniya Das }, 2112*1c9efb0bSTaniya Das }, 2113*1c9efb0bSTaniya Das }; 2114*1c9efb0bSTaniya Das 2115*1c9efb0bSTaniya Das static struct clk_branch gcc_sdcc5_ice_core_clk = { 2116*1c9efb0bSTaniya Das .halt_reg = 0x3b010, 2117*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 2118*1c9efb0bSTaniya Das .clkr = { 2119*1c9efb0bSTaniya Das .enable_reg = 0x3b010, 2120*1c9efb0bSTaniya Das .enable_mask = BIT(0), 2121*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2122*1c9efb0bSTaniya Das .name = "gcc_sdcc5_ice_core_clk", 2123*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 2124*1c9efb0bSTaniya Das &gcc_sdcc5_ice_core_clk_src.clkr.hw, 2125*1c9efb0bSTaniya Das }, 2126*1c9efb0bSTaniya Das .num_parents = 1, 2127*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 2128*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2129*1c9efb0bSTaniya Das }, 2130*1c9efb0bSTaniya Das }, 2131*1c9efb0bSTaniya Das }; 2132*1c9efb0bSTaniya Das 2133*1c9efb0bSTaniya Das static struct clk_branch gcc_sm_bus_ahb_clk = { 2134*1c9efb0bSTaniya Das .halt_reg = 0x5b004, 2135*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 2136*1c9efb0bSTaniya Das .clkr = { 2137*1c9efb0bSTaniya Das .enable_reg = 0x5b004, 2138*1c9efb0bSTaniya Das .enable_mask = BIT(0), 2139*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2140*1c9efb0bSTaniya Das .name = "gcc_sm_bus_ahb_clk", 2141*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2142*1c9efb0bSTaniya Das }, 2143*1c9efb0bSTaniya Das }, 2144*1c9efb0bSTaniya Das }; 2145*1c9efb0bSTaniya Das 2146*1c9efb0bSTaniya Das static struct clk_branch gcc_sm_bus_xo_clk = { 2147*1c9efb0bSTaniya Das .halt_reg = 0x5b008, 2148*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 2149*1c9efb0bSTaniya Das .clkr = { 2150*1c9efb0bSTaniya Das .enable_reg = 0x5b008, 2151*1c9efb0bSTaniya Das .enable_mask = BIT(0), 2152*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2153*1c9efb0bSTaniya Das .name = "gcc_sm_bus_xo_clk", 2154*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 2155*1c9efb0bSTaniya Das &gcc_sm_bus_xo_clk_src.clkr.hw, 2156*1c9efb0bSTaniya Das }, 2157*1c9efb0bSTaniya Das .num_parents = 1, 2158*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 2159*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2160*1c9efb0bSTaniya Das }, 2161*1c9efb0bSTaniya Das }, 2162*1c9efb0bSTaniya Das }; 2163*1c9efb0bSTaniya Das 2164*1c9efb0bSTaniya Das static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_qx_clk = { 2165*1c9efb0bSTaniya Das .halt_reg = 0x9200c, 2166*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_SKIP, 2167*1c9efb0bSTaniya Das .hwcg_reg = 0x9200c, 2168*1c9efb0bSTaniya Das .hwcg_bit = 1, 2169*1c9efb0bSTaniya Das .clkr = { 2170*1c9efb0bSTaniya Das .enable_reg = 0x62000, 2171*1c9efb0bSTaniya Das .enable_mask = BIT(11), 2172*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2173*1c9efb0bSTaniya Das .name = "gcc_snoc_cnoc_gemnoc_pcie_qx_clk", 2174*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2175*1c9efb0bSTaniya Das }, 2176*1c9efb0bSTaniya Das }, 2177*1c9efb0bSTaniya Das }; 2178*1c9efb0bSTaniya Das 2179*1c9efb0bSTaniya Das static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk = { 2180*1c9efb0bSTaniya Das .halt_reg = 0x92010, 2181*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_SKIP, 2182*1c9efb0bSTaniya Das .hwcg_reg = 0x92010, 2183*1c9efb0bSTaniya Das .hwcg_bit = 1, 2184*1c9efb0bSTaniya Das .clkr = { 2185*1c9efb0bSTaniya Das .enable_reg = 0x62000, 2186*1c9efb0bSTaniya Das .enable_mask = BIT(12), 2187*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2188*1c9efb0bSTaniya Das .name = "gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk", 2189*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2190*1c9efb0bSTaniya Das }, 2191*1c9efb0bSTaniya Das }, 2192*1c9efb0bSTaniya Das }; 2193*1c9efb0bSTaniya Das 2194*1c9efb0bSTaniya Das static struct clk_branch gcc_snoc_cnoc_pcie_qx_clk = { 2195*1c9efb0bSTaniya Das .halt_reg = 0x84030, 2196*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 2197*1c9efb0bSTaniya Das .clkr = { 2198*1c9efb0bSTaniya Das .enable_reg = 0x84030, 2199*1c9efb0bSTaniya Das .enable_mask = BIT(0), 2200*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2201*1c9efb0bSTaniya Das .name = "gcc_snoc_cnoc_pcie_qx_clk", 2202*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2203*1c9efb0bSTaniya Das }, 2204*1c9efb0bSTaniya Das }, 2205*1c9efb0bSTaniya Das }; 2206*1c9efb0bSTaniya Das 2207*1c9efb0bSTaniya Das static struct clk_branch gcc_snoc_pcie_sf_center_qx_clk = { 2208*1c9efb0bSTaniya Das .halt_reg = 0x92014, 2209*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_SKIP, 2210*1c9efb0bSTaniya Das .hwcg_reg = 0x92014, 2211*1c9efb0bSTaniya Das .hwcg_bit = 1, 2212*1c9efb0bSTaniya Das .clkr = { 2213*1c9efb0bSTaniya Das .enable_reg = 0x62000, 2214*1c9efb0bSTaniya Das .enable_mask = BIT(19), 2215*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2216*1c9efb0bSTaniya Das .name = "gcc_snoc_pcie_sf_center_qx_clk", 2217*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2218*1c9efb0bSTaniya Das }, 2219*1c9efb0bSTaniya Das }, 2220*1c9efb0bSTaniya Das }; 2221*1c9efb0bSTaniya Das 2222*1c9efb0bSTaniya Das static struct clk_branch gcc_snoc_pcie_sf_south_qx_clk = { 2223*1c9efb0bSTaniya Das .halt_reg = 0x92018, 2224*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_SKIP, 2225*1c9efb0bSTaniya Das .hwcg_reg = 0x92018, 2226*1c9efb0bSTaniya Das .hwcg_bit = 1, 2227*1c9efb0bSTaniya Das .clkr = { 2228*1c9efb0bSTaniya Das .enable_reg = 0x62000, 2229*1c9efb0bSTaniya Das .enable_mask = BIT(22), 2230*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2231*1c9efb0bSTaniya Das .name = "gcc_snoc_pcie_sf_south_qx_clk", 2232*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2233*1c9efb0bSTaniya Das }, 2234*1c9efb0bSTaniya Das }, 2235*1c9efb0bSTaniya Das }; 2236*1c9efb0bSTaniya Das 2237*1c9efb0bSTaniya Das static struct clk_branch gcc_tsc_cfg_ahb_clk = { 2238*1c9efb0bSTaniya Das .halt_reg = 0x5700c, 2239*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 2240*1c9efb0bSTaniya Das .clkr = { 2241*1c9efb0bSTaniya Das .enable_reg = 0x5700c, 2242*1c9efb0bSTaniya Das .enable_mask = BIT(0), 2243*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2244*1c9efb0bSTaniya Das .name = "gcc_tsc_cfg_ahb_clk", 2245*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2246*1c9efb0bSTaniya Das }, 2247*1c9efb0bSTaniya Das }, 2248*1c9efb0bSTaniya Das }; 2249*1c9efb0bSTaniya Das 2250*1c9efb0bSTaniya Das static struct clk_branch gcc_tsc_cntr_clk = { 2251*1c9efb0bSTaniya Das .halt_reg = 0x57004, 2252*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 2253*1c9efb0bSTaniya Das .clkr = { 2254*1c9efb0bSTaniya Das .enable_reg = 0x57004, 2255*1c9efb0bSTaniya Das .enable_mask = BIT(0), 2256*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2257*1c9efb0bSTaniya Das .name = "gcc_tsc_cntr_clk", 2258*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 2259*1c9efb0bSTaniya Das &gcc_tsc_clk_src.clkr.hw, 2260*1c9efb0bSTaniya Das }, 2261*1c9efb0bSTaniya Das .num_parents = 1, 2262*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 2263*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2264*1c9efb0bSTaniya Das }, 2265*1c9efb0bSTaniya Das }, 2266*1c9efb0bSTaniya Das }; 2267*1c9efb0bSTaniya Das 2268*1c9efb0bSTaniya Das static struct clk_branch gcc_tsc_etu_clk = { 2269*1c9efb0bSTaniya Das .halt_reg = 0x57008, 2270*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 2271*1c9efb0bSTaniya Das .clkr = { 2272*1c9efb0bSTaniya Das .enable_reg = 0x57008, 2273*1c9efb0bSTaniya Das .enable_mask = BIT(0), 2274*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2275*1c9efb0bSTaniya Das .name = "gcc_tsc_etu_clk", 2276*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 2277*1c9efb0bSTaniya Das &gcc_tsc_clk_src.clkr.hw, 2278*1c9efb0bSTaniya Das }, 2279*1c9efb0bSTaniya Das .num_parents = 1, 2280*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 2281*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2282*1c9efb0bSTaniya Das }, 2283*1c9efb0bSTaniya Das }, 2284*1c9efb0bSTaniya Das }; 2285*1c9efb0bSTaniya Das 2286*1c9efb0bSTaniya Das static struct clk_branch gcc_usb2_clkref_en = { 2287*1c9efb0bSTaniya Das .halt_reg = 0x9c008, 2288*1c9efb0bSTaniya Das .halt_bit = 31, 2289*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_ENABLE, 2290*1c9efb0bSTaniya Das .clkr = { 2291*1c9efb0bSTaniya Das .enable_reg = 0x9c008, 2292*1c9efb0bSTaniya Das .enable_mask = BIT(0), 2293*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2294*1c9efb0bSTaniya Das .name = "gcc_usb2_clkref_en", 2295*1c9efb0bSTaniya Das .ops = &clk_branch_ops, 2296*1c9efb0bSTaniya Das }, 2297*1c9efb0bSTaniya Das }, 2298*1c9efb0bSTaniya Das }; 2299*1c9efb0bSTaniya Das 2300*1c9efb0bSTaniya Das static struct clk_branch gcc_usb30_prim_master_clk = { 2301*1c9efb0bSTaniya Das .halt_reg = 0x49018, 2302*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 2303*1c9efb0bSTaniya Das .clkr = { 2304*1c9efb0bSTaniya Das .enable_reg = 0x49018, 2305*1c9efb0bSTaniya Das .enable_mask = BIT(0), 2306*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2307*1c9efb0bSTaniya Das .name = "gcc_usb30_prim_master_clk", 2308*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 2309*1c9efb0bSTaniya Das &gcc_usb30_prim_master_clk_src.clkr.hw, 2310*1c9efb0bSTaniya Das }, 2311*1c9efb0bSTaniya Das .num_parents = 1, 2312*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 2313*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2314*1c9efb0bSTaniya Das }, 2315*1c9efb0bSTaniya Das }, 2316*1c9efb0bSTaniya Das }; 2317*1c9efb0bSTaniya Das 2318*1c9efb0bSTaniya Das static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2319*1c9efb0bSTaniya Das .halt_reg = 0x49024, 2320*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 2321*1c9efb0bSTaniya Das .clkr = { 2322*1c9efb0bSTaniya Das .enable_reg = 0x49024, 2323*1c9efb0bSTaniya Das .enable_mask = BIT(0), 2324*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2325*1c9efb0bSTaniya Das .name = "gcc_usb30_prim_mock_utmi_clk", 2326*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 2327*1c9efb0bSTaniya Das &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2328*1c9efb0bSTaniya Das }, 2329*1c9efb0bSTaniya Das .num_parents = 1, 2330*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 2331*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2332*1c9efb0bSTaniya Das }, 2333*1c9efb0bSTaniya Das }, 2334*1c9efb0bSTaniya Das }; 2335*1c9efb0bSTaniya Das 2336*1c9efb0bSTaniya Das static struct clk_branch gcc_usb30_prim_sleep_clk = { 2337*1c9efb0bSTaniya Das .halt_reg = 0x49020, 2338*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 2339*1c9efb0bSTaniya Das .clkr = { 2340*1c9efb0bSTaniya Das .enable_reg = 0x49020, 2341*1c9efb0bSTaniya Das .enable_mask = BIT(0), 2342*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2343*1c9efb0bSTaniya Das .name = "gcc_usb30_prim_sleep_clk", 2344*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2345*1c9efb0bSTaniya Das }, 2346*1c9efb0bSTaniya Das }, 2347*1c9efb0bSTaniya Das }; 2348*1c9efb0bSTaniya Das 2349*1c9efb0bSTaniya Das static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2350*1c9efb0bSTaniya Das .halt_reg = 0x49060, 2351*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 2352*1c9efb0bSTaniya Das .clkr = { 2353*1c9efb0bSTaniya Das .enable_reg = 0x49060, 2354*1c9efb0bSTaniya Das .enable_mask = BIT(0), 2355*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2356*1c9efb0bSTaniya Das .name = "gcc_usb3_prim_phy_aux_clk", 2357*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 2358*1c9efb0bSTaniya Das &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2359*1c9efb0bSTaniya Das }, 2360*1c9efb0bSTaniya Das .num_parents = 1, 2361*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 2362*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2363*1c9efb0bSTaniya Das }, 2364*1c9efb0bSTaniya Das }, 2365*1c9efb0bSTaniya Das }; 2366*1c9efb0bSTaniya Das 2367*1c9efb0bSTaniya Das static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2368*1c9efb0bSTaniya Das .halt_reg = 0x49064, 2369*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT, 2370*1c9efb0bSTaniya Das .clkr = { 2371*1c9efb0bSTaniya Das .enable_reg = 0x49064, 2372*1c9efb0bSTaniya Das .enable_mask = BIT(0), 2373*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2374*1c9efb0bSTaniya Das .name = "gcc_usb3_prim_phy_com_aux_clk", 2375*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 2376*1c9efb0bSTaniya Das &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2377*1c9efb0bSTaniya Das }, 2378*1c9efb0bSTaniya Das .num_parents = 1, 2379*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 2380*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2381*1c9efb0bSTaniya Das }, 2382*1c9efb0bSTaniya Das }, 2383*1c9efb0bSTaniya Das }; 2384*1c9efb0bSTaniya Das 2385*1c9efb0bSTaniya Das static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2386*1c9efb0bSTaniya Das .halt_reg = 0x49068, 2387*1c9efb0bSTaniya Das .halt_check = BRANCH_HALT_DELAY, 2388*1c9efb0bSTaniya Das .hwcg_reg = 0x49068, 2389*1c9efb0bSTaniya Das .hwcg_bit = 1, 2390*1c9efb0bSTaniya Das .clkr = { 2391*1c9efb0bSTaniya Das .enable_reg = 0x49068, 2392*1c9efb0bSTaniya Das .enable_mask = BIT(0), 2393*1c9efb0bSTaniya Das .hw.init = &(const struct clk_init_data) { 2394*1c9efb0bSTaniya Das .name = "gcc_usb3_prim_phy_pipe_clk", 2395*1c9efb0bSTaniya Das .parent_hws = (const struct clk_hw*[]) { 2396*1c9efb0bSTaniya Das &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 2397*1c9efb0bSTaniya Das }, 2398*1c9efb0bSTaniya Das .num_parents = 1, 2399*1c9efb0bSTaniya Das .flags = CLK_SET_RATE_PARENT, 2400*1c9efb0bSTaniya Das .ops = &clk_branch2_ops, 2401*1c9efb0bSTaniya Das }, 2402*1c9efb0bSTaniya Das }, 2403*1c9efb0bSTaniya Das }; 2404*1c9efb0bSTaniya Das 2405*1c9efb0bSTaniya Das static struct clk_regmap *gcc_qdu1000_clocks[] = { 2406*1c9efb0bSTaniya Das [GCC_AGGRE_NOC_ECPRI_DMA_CLK] = &gcc_aggre_noc_ecpri_dma_clk.clkr, 2407*1c9efb0bSTaniya Das [GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC] = &gcc_aggre_noc_ecpri_dma_clk_src.clkr, 2408*1c9efb0bSTaniya Das [GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC] = &gcc_aggre_noc_ecpri_gsi_clk_src.clkr, 2409*1c9efb0bSTaniya Das [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2410*1c9efb0bSTaniya Das [GCC_CFG_NOC_ECPRI_CC_AHB_CLK] = &gcc_cfg_noc_ecpri_cc_ahb_clk.clkr, 2411*1c9efb0bSTaniya Das [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2412*1c9efb0bSTaniya Das [GCC_DDRSS_ECPRI_DMA_CLK] = &gcc_ddrss_ecpri_dma_clk.clkr, 2413*1c9efb0bSTaniya Das [GCC_ECPRI_AHB_CLK] = &gcc_ecpri_ahb_clk.clkr, 2414*1c9efb0bSTaniya Das [GCC_ECPRI_CC_GPLL0_CLK_SRC] = &gcc_ecpri_cc_gpll0_clk_src.clkr, 2415*1c9efb0bSTaniya Das [GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll1_even_clk_src.clkr, 2416*1c9efb0bSTaniya Das [GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll2_even_clk_src.clkr, 2417*1c9efb0bSTaniya Das [GCC_ECPRI_CC_GPLL3_CLK_SRC] = &gcc_ecpri_cc_gpll3_clk_src.clkr, 2418*1c9efb0bSTaniya Das [GCC_ECPRI_CC_GPLL4_CLK_SRC] = &gcc_ecpri_cc_gpll4_clk_src.clkr, 2419*1c9efb0bSTaniya Das [GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll5_even_clk_src.clkr, 2420*1c9efb0bSTaniya Das [GCC_ECPRI_XO_CLK] = &gcc_ecpri_xo_clk.clkr, 2421*1c9efb0bSTaniya Das [GCC_ETH_DBG_SNOC_AXI_CLK] = &gcc_eth_dbg_snoc_axi_clk.clkr, 2422*1c9efb0bSTaniya Das [GCC_GEMNOC_PCIE_QX_CLK] = &gcc_gemnoc_pcie_qx_clk.clkr, 2423*1c9efb0bSTaniya Das [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2424*1c9efb0bSTaniya Das [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2425*1c9efb0bSTaniya Das [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2426*1c9efb0bSTaniya Das [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2427*1c9efb0bSTaniya Das [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2428*1c9efb0bSTaniya Das [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2429*1c9efb0bSTaniya Das [GCC_GPLL0] = &gcc_gpll0.clkr, 2430*1c9efb0bSTaniya Das [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 2431*1c9efb0bSTaniya Das [GCC_GPLL1] = &gcc_gpll1.clkr, 2432*1c9efb0bSTaniya Das [GCC_GPLL2] = &gcc_gpll2.clkr, 2433*1c9efb0bSTaniya Das [GCC_GPLL2_OUT_EVEN] = &gcc_gpll2_out_even.clkr, 2434*1c9efb0bSTaniya Das [GCC_GPLL3] = &gcc_gpll3.clkr, 2435*1c9efb0bSTaniya Das [GCC_GPLL4] = &gcc_gpll4.clkr, 2436*1c9efb0bSTaniya Das [GCC_GPLL5] = &gcc_gpll5.clkr, 2437*1c9efb0bSTaniya Das [GCC_GPLL5_OUT_EVEN] = &gcc_gpll5_out_even.clkr, 2438*1c9efb0bSTaniya Das [GCC_GPLL6] = &gcc_gpll6.clkr, 2439*1c9efb0bSTaniya Das [GCC_GPLL7] = &gcc_gpll7.clkr, 2440*1c9efb0bSTaniya Das [GCC_GPLL8] = &gcc_gpll8.clkr, 2441*1c9efb0bSTaniya Das [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2442*1c9efb0bSTaniya Das [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 2443*1c9efb0bSTaniya Das [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2444*1c9efb0bSTaniya Das [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr, 2445*1c9efb0bSTaniya Das [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2446*1c9efb0bSTaniya Das [GCC_PCIE_0_PHY_AUX_CLK] = &gcc_pcie_0_phy_aux_clk.clkr, 2447*1c9efb0bSTaniya Das [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 2448*1c9efb0bSTaniya Das [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 2449*1c9efb0bSTaniya Das [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2450*1c9efb0bSTaniya Das [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2451*1c9efb0bSTaniya Das [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 2452*1c9efb0bSTaniya Das [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2453*1c9efb0bSTaniya Das [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 2454*1c9efb0bSTaniya Das [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2455*1c9efb0bSTaniya Das [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2456*1c9efb0bSTaniya Das [GCC_QMIP_ANOC_PCIE_CLK] = &gcc_qmip_anoc_pcie_clk.clkr, 2457*1c9efb0bSTaniya Das [GCC_QMIP_ECPRI_DMA0_CLK] = &gcc_qmip_ecpri_dma0_clk.clkr, 2458*1c9efb0bSTaniya Das [GCC_QMIP_ECPRI_DMA1_CLK] = &gcc_qmip_ecpri_dma1_clk.clkr, 2459*1c9efb0bSTaniya Das [GCC_QMIP_ECPRI_GSI_CLK] = &gcc_qmip_ecpri_gsi_clk.clkr, 2460*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 2461*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 2462*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 2463*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 2464*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 2465*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 2466*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 2467*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 2468*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 2469*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 2470*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 2471*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 2472*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 2473*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 2474*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 2475*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 2476*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 2477*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 2478*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 2479*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 2480*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 2481*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 2482*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 2483*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 2484*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 2485*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 2486*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 2487*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 2488*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 2489*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 2490*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 2491*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 2492*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 2493*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 2494*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 2495*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 2496*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 2497*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 2498*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 2499*1c9efb0bSTaniya Das [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 2500*1c9efb0bSTaniya Das [GCC_SDCC5_AHB_CLK] = &gcc_sdcc5_ahb_clk.clkr, 2501*1c9efb0bSTaniya Das [GCC_SDCC5_APPS_CLK] = &gcc_sdcc5_apps_clk.clkr, 2502*1c9efb0bSTaniya Das [GCC_SDCC5_APPS_CLK_SRC] = &gcc_sdcc5_apps_clk_src.clkr, 2503*1c9efb0bSTaniya Das [GCC_SDCC5_ICE_CORE_CLK] = &gcc_sdcc5_ice_core_clk.clkr, 2504*1c9efb0bSTaniya Das [GCC_SDCC5_ICE_CORE_CLK_SRC] = &gcc_sdcc5_ice_core_clk_src.clkr, 2505*1c9efb0bSTaniya Das [GCC_SM_BUS_AHB_CLK] = &gcc_sm_bus_ahb_clk.clkr, 2506*1c9efb0bSTaniya Das [GCC_SM_BUS_XO_CLK] = &gcc_sm_bus_xo_clk.clkr, 2507*1c9efb0bSTaniya Das [GCC_SM_BUS_XO_CLK_SRC] = &gcc_sm_bus_xo_clk_src.clkr, 2508*1c9efb0bSTaniya Das [GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK] = &gcc_snoc_cnoc_gemnoc_pcie_qx_clk.clkr, 2509*1c9efb0bSTaniya Das [GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK] = &gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk.clkr, 2510*1c9efb0bSTaniya Das [GCC_SNOC_CNOC_PCIE_QX_CLK] = &gcc_snoc_cnoc_pcie_qx_clk.clkr, 2511*1c9efb0bSTaniya Das [GCC_SNOC_PCIE_SF_CENTER_QX_CLK] = &gcc_snoc_pcie_sf_center_qx_clk.clkr, 2512*1c9efb0bSTaniya Das [GCC_SNOC_PCIE_SF_SOUTH_QX_CLK] = &gcc_snoc_pcie_sf_south_qx_clk.clkr, 2513*1c9efb0bSTaniya Das [GCC_TSC_CFG_AHB_CLK] = &gcc_tsc_cfg_ahb_clk.clkr, 2514*1c9efb0bSTaniya Das [GCC_TSC_CLK_SRC] = &gcc_tsc_clk_src.clkr, 2515*1c9efb0bSTaniya Das [GCC_TSC_CNTR_CLK] = &gcc_tsc_cntr_clk.clkr, 2516*1c9efb0bSTaniya Das [GCC_TSC_ETU_CLK] = &gcc_tsc_etu_clk.clkr, 2517*1c9efb0bSTaniya Das [GCC_USB2_CLKREF_EN] = &gcc_usb2_clkref_en.clkr, 2518*1c9efb0bSTaniya Das [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 2519*1c9efb0bSTaniya Das [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 2520*1c9efb0bSTaniya Das [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 2521*1c9efb0bSTaniya Das [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 2522*1c9efb0bSTaniya Das [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 2523*1c9efb0bSTaniya Das [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 2524*1c9efb0bSTaniya Das [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 2525*1c9efb0bSTaniya Das [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 2526*1c9efb0bSTaniya Das [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 2527*1c9efb0bSTaniya Das [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 2528*1c9efb0bSTaniya Das [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 2529*1c9efb0bSTaniya Das [GCC_ETH_100G_C2C_HM_APB_CLK] = &gcc_eth_100g_c2c_hm_apb_clk.clkr, 2530*1c9efb0bSTaniya Das [GCC_ETH_100G_FH_HM_APB_0_CLK] = &gcc_eth_100g_fh_hm_apb_0_clk.clkr, 2531*1c9efb0bSTaniya Das [GCC_ETH_100G_FH_HM_APB_1_CLK] = &gcc_eth_100g_fh_hm_apb_1_clk.clkr, 2532*1c9efb0bSTaniya Das [GCC_ETH_100G_FH_HM_APB_2_CLK] = &gcc_eth_100g_fh_hm_apb_2_clk.clkr, 2533*1c9efb0bSTaniya Das [GCC_ETH_DBG_C2C_HM_APB_CLK] = &gcc_eth_dbg_c2c_hm_apb_clk.clkr, 2534*1c9efb0bSTaniya Das [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr, 2535*1c9efb0bSTaniya Das [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, 2536*1c9efb0bSTaniya Das [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 2537*1c9efb0bSTaniya Das }; 2538*1c9efb0bSTaniya Das 2539*1c9efb0bSTaniya Das static const struct qcom_reset_map gcc_qdu1000_resets[] = { 2540*1c9efb0bSTaniya Das [GCC_ECPRI_CC_BCR] = { 0x3e000 }, 2541*1c9efb0bSTaniya Das [GCC_ECPRI_SS_BCR] = { 0x3a000 }, 2542*1c9efb0bSTaniya Das [GCC_ETH_WRAPPER_BCR] = { 0x39000 }, 2543*1c9efb0bSTaniya Das [GCC_PCIE_0_BCR] = { 0x9d000 }, 2544*1c9efb0bSTaniya Das [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x9e014 }, 2545*1c9efb0bSTaniya Das [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x9e020 }, 2546*1c9efb0bSTaniya Das [GCC_PCIE_0_PHY_BCR] = { 0x7c000 }, 2547*1c9efb0bSTaniya Das [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 }, 2548*1c9efb0bSTaniya Das [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c }, 2549*1c9efb0bSTaniya Das [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 }, 2550*1c9efb0bSTaniya Das [GCC_PDM_BCR] = { 0x43000 }, 2551*1c9efb0bSTaniya Das [GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 }, 2552*1c9efb0bSTaniya Das [GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 }, 2553*1c9efb0bSTaniya Das [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 }, 2554*1c9efb0bSTaniya Das [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 }, 2555*1c9efb0bSTaniya Das [GCC_SDCC5_BCR] = { 0x3b000 }, 2556*1c9efb0bSTaniya Das [GCC_TSC_BCR] = { 0x57000 }, 2557*1c9efb0bSTaniya Das [GCC_USB30_PRIM_BCR] = { 0x49000 }, 2558*1c9efb0bSTaniya Das [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 }, 2559*1c9efb0bSTaniya Das [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 }, 2560*1c9efb0bSTaniya Das [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 }, 2561*1c9efb0bSTaniya Das [GCC_USB3_PHY_SEC_BCR] = { 0x6000c }, 2562*1c9efb0bSTaniya Das [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 }, 2563*1c9efb0bSTaniya Das [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 }, 2564*1c9efb0bSTaniya Das [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 }, 2565*1c9efb0bSTaniya Das }; 2566*1c9efb0bSTaniya Das 2567*1c9efb0bSTaniya Das static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 2568*1c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 2569*1c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 2570*1c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 2571*1c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 2572*1c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 2573*1c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 2574*1c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 2575*1c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 2576*1c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 2577*1c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 2578*1c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 2579*1c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 2580*1c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 2581*1c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 2582*1c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 2583*1c9efb0bSTaniya Das DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 2584*1c9efb0bSTaniya Das }; 2585*1c9efb0bSTaniya Das 2586*1c9efb0bSTaniya Das static const struct regmap_config gcc_qdu1000_regmap_config = { 2587*1c9efb0bSTaniya Das .reg_bits = 32, 2588*1c9efb0bSTaniya Das .reg_stride = 4, 2589*1c9efb0bSTaniya Das .val_bits = 32, 2590*1c9efb0bSTaniya Das .max_register = 0x1f41f0, 2591*1c9efb0bSTaniya Das .fast_io = true, 2592*1c9efb0bSTaniya Das }; 2593*1c9efb0bSTaniya Das 2594*1c9efb0bSTaniya Das static const struct qcom_cc_desc gcc_qdu1000_desc = { 2595*1c9efb0bSTaniya Das .config = &gcc_qdu1000_regmap_config, 2596*1c9efb0bSTaniya Das .clks = gcc_qdu1000_clocks, 2597*1c9efb0bSTaniya Das .num_clks = ARRAY_SIZE(gcc_qdu1000_clocks), 2598*1c9efb0bSTaniya Das .resets = gcc_qdu1000_resets, 2599*1c9efb0bSTaniya Das .num_resets = ARRAY_SIZE(gcc_qdu1000_resets), 2600*1c9efb0bSTaniya Das }; 2601*1c9efb0bSTaniya Das 2602*1c9efb0bSTaniya Das static const struct of_device_id gcc_qdu1000_match_table[] = { 2603*1c9efb0bSTaniya Das { .compatible = "qcom,qdu1000-gcc" }, 2604*1c9efb0bSTaniya Das { } 2605*1c9efb0bSTaniya Das }; 2606*1c9efb0bSTaniya Das MODULE_DEVICE_TABLE(of, gcc_qdu1000_match_table); 2607*1c9efb0bSTaniya Das 2608*1c9efb0bSTaniya Das static int gcc_qdu1000_probe(struct platform_device *pdev) 2609*1c9efb0bSTaniya Das { 2610*1c9efb0bSTaniya Das struct regmap *regmap; 2611*1c9efb0bSTaniya Das int ret; 2612*1c9efb0bSTaniya Das 2613*1c9efb0bSTaniya Das regmap = qcom_cc_map(pdev, &gcc_qdu1000_desc); 2614*1c9efb0bSTaniya Das if (IS_ERR(regmap)) 2615*1c9efb0bSTaniya Das return PTR_ERR(regmap); 2616*1c9efb0bSTaniya Das 2617*1c9efb0bSTaniya Das /* Update FORCE_MEM_CORE_ON for gcc_pcie_0_mstr_axi_clk */ 2618*1c9efb0bSTaniya Das regmap_update_bits(regmap, 0x9d024, BIT(14), BIT(14)); 2619*1c9efb0bSTaniya Das 2620*1c9efb0bSTaniya Das ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 2621*1c9efb0bSTaniya Das ARRAY_SIZE(gcc_dfs_clocks)); 2622*1c9efb0bSTaniya Das if (ret) 2623*1c9efb0bSTaniya Das return ret; 2624*1c9efb0bSTaniya Das 2625*1c9efb0bSTaniya Das ret = qcom_cc_really_probe(pdev, &gcc_qdu1000_desc, regmap); 2626*1c9efb0bSTaniya Das if (ret) 2627*1c9efb0bSTaniya Das return dev_err_probe(&pdev->dev, ret, "Failed to register GCC clocks\n"); 2628*1c9efb0bSTaniya Das 2629*1c9efb0bSTaniya Das return ret; 2630*1c9efb0bSTaniya Das } 2631*1c9efb0bSTaniya Das 2632*1c9efb0bSTaniya Das static struct platform_driver gcc_qdu1000_driver = { 2633*1c9efb0bSTaniya Das .probe = gcc_qdu1000_probe, 2634*1c9efb0bSTaniya Das .driver = { 2635*1c9efb0bSTaniya Das .name = "gcc-qdu1000", 2636*1c9efb0bSTaniya Das .of_match_table = gcc_qdu1000_match_table, 2637*1c9efb0bSTaniya Das }, 2638*1c9efb0bSTaniya Das }; 2639*1c9efb0bSTaniya Das 2640*1c9efb0bSTaniya Das static int __init gcc_qdu1000_init(void) 2641*1c9efb0bSTaniya Das { 2642*1c9efb0bSTaniya Das return platform_driver_register(&gcc_qdu1000_driver); 2643*1c9efb0bSTaniya Das } 2644*1c9efb0bSTaniya Das subsys_initcall(gcc_qdu1000_init); 2645*1c9efb0bSTaniya Das 2646*1c9efb0bSTaniya Das static void __exit gcc_qdu1000_exit(void) 2647*1c9efb0bSTaniya Das { 2648*1c9efb0bSTaniya Das platform_driver_unregister(&gcc_qdu1000_driver); 2649*1c9efb0bSTaniya Das } 2650*1c9efb0bSTaniya Das module_exit(gcc_qdu1000_exit); 2651*1c9efb0bSTaniya Das 2652*1c9efb0bSTaniya Das MODULE_DESCRIPTION("QTI GCC QDU1000 Driver"); 2653*1c9efb0bSTaniya Das MODULE_LICENSE("GPL"); 2654