1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/platform_device.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/clk-provider.h> 11 #include <linux/regmap.h> 12 #include <linux/reset-controller.h> 13 14 #include <dt-bindings/clock/qcom,gcc-qcs404.h> 15 16 #include "clk-alpha-pll.h" 17 #include "clk-branch.h" 18 #include "clk-pll.h" 19 #include "clk-rcg.h" 20 #include "clk-regmap.h" 21 #include "common.h" 22 #include "reset.h" 23 24 enum { 25 P_CORE_BI_PLL_TEST_SE, 26 P_DSI0_PHY_PLL_OUT_BYTECLK, 27 P_DSI0_PHY_PLL_OUT_DSICLK, 28 P_GPLL0_OUT_AUX, 29 P_GPLL0_OUT_MAIN, 30 P_GPLL1_OUT_MAIN, 31 P_GPLL3_OUT_MAIN, 32 P_GPLL4_OUT_AUX, 33 P_GPLL4_OUT_MAIN, 34 P_GPLL6_OUT_AUX, 35 P_HDMI_PHY_PLL_CLK, 36 P_PCIE_0_PIPE_CLK, 37 P_SLEEP_CLK, 38 P_XO, 39 }; 40 41 static const struct parent_map gcc_parent_map_0[] = { 42 { P_XO, 0 }, 43 { P_GPLL0_OUT_MAIN, 1 }, 44 { P_CORE_BI_PLL_TEST_SE, 7 }, 45 }; 46 47 static const char * const gcc_parent_names_0[] = { 48 "cxo", 49 "gpll0_out_main", 50 "core_bi_pll_test_se", 51 }; 52 53 static const char * const gcc_parent_names_ao_0[] = { 54 "cxo", 55 "gpll0_ao_out_main", 56 "core_bi_pll_test_se", 57 }; 58 59 static const struct parent_map gcc_parent_map_1[] = { 60 { P_XO, 0 }, 61 { P_CORE_BI_PLL_TEST_SE, 7 }, 62 }; 63 64 static const char * const gcc_parent_names_1[] = { 65 "cxo", 66 "core_bi_pll_test_se", 67 }; 68 69 static const struct parent_map gcc_parent_map_2[] = { 70 { P_XO, 0 }, 71 { P_GPLL0_OUT_MAIN, 1 }, 72 { P_GPLL6_OUT_AUX, 2 }, 73 { P_SLEEP_CLK, 6 }, 74 }; 75 76 static const char * const gcc_parent_names_2[] = { 77 "cxo", 78 "gpll0_out_main", 79 "gpll6_out_aux", 80 "sleep_clk", 81 }; 82 83 static const struct parent_map gcc_parent_map_3[] = { 84 { P_XO, 0 }, 85 { P_GPLL0_OUT_MAIN, 1 }, 86 { P_GPLL6_OUT_AUX, 2 }, 87 { P_CORE_BI_PLL_TEST_SE, 7 }, 88 }; 89 90 static const char * const gcc_parent_names_3[] = { 91 "cxo", 92 "gpll0_out_main", 93 "gpll6_out_aux", 94 "core_bi_pll_test_se", 95 }; 96 97 static const struct parent_map gcc_parent_map_4[] = { 98 { P_XO, 0 }, 99 { P_GPLL1_OUT_MAIN, 1 }, 100 { P_CORE_BI_PLL_TEST_SE, 7 }, 101 }; 102 103 static const char * const gcc_parent_names_4[] = { 104 "cxo", 105 "gpll1_out_main", 106 "core_bi_pll_test_se", 107 }; 108 109 static const struct parent_map gcc_parent_map_5[] = { 110 { P_XO, 0 }, 111 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, 112 { P_GPLL0_OUT_AUX, 2 }, 113 { P_CORE_BI_PLL_TEST_SE, 7 }, 114 }; 115 116 static const char * const gcc_parent_names_5[] = { 117 "cxo", 118 "dsi0pll_byteclk_src", 119 "gpll0_out_aux", 120 "core_bi_pll_test_se", 121 }; 122 123 static const struct parent_map gcc_parent_map_6[] = { 124 { P_XO, 0 }, 125 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 126 { P_GPLL0_OUT_AUX, 3 }, 127 { P_CORE_BI_PLL_TEST_SE, 7 }, 128 }; 129 130 static const char * const gcc_parent_names_6[] = { 131 "cxo", 132 "dsi0_phy_pll_out_byteclk", 133 "gpll0_out_aux", 134 "core_bi_pll_test_se", 135 }; 136 137 static const struct parent_map gcc_parent_map_7[] = { 138 { P_XO, 0 }, 139 { P_GPLL0_OUT_MAIN, 1 }, 140 { P_GPLL3_OUT_MAIN, 2 }, 141 { P_GPLL6_OUT_AUX, 3 }, 142 { P_GPLL4_OUT_AUX, 4 }, 143 { P_CORE_BI_PLL_TEST_SE, 7 }, 144 }; 145 146 static const char * const gcc_parent_names_7[] = { 147 "cxo", 148 "gpll0_out_main", 149 "gpll3_out_main", 150 "gpll6_out_aux", 151 "gpll4_out_aux", 152 "core_bi_pll_test_se", 153 }; 154 155 static const struct parent_map gcc_parent_map_8[] = { 156 { P_XO, 0 }, 157 { P_HDMI_PHY_PLL_CLK, 1 }, 158 { P_CORE_BI_PLL_TEST_SE, 7 }, 159 }; 160 161 static const char * const gcc_parent_names_8[] = { 162 "cxo", 163 "hdmi_phy_pll_clk", 164 "core_bi_pll_test_se", 165 }; 166 167 static const struct parent_map gcc_parent_map_9[] = { 168 { P_XO, 0 }, 169 { P_GPLL0_OUT_MAIN, 1 }, 170 { P_DSI0_PHY_PLL_OUT_DSICLK, 2 }, 171 { P_GPLL6_OUT_AUX, 3 }, 172 { P_CORE_BI_PLL_TEST_SE, 7 }, 173 }; 174 175 static const char * const gcc_parent_names_9[] = { 176 "cxo", 177 "gpll0_out_main", 178 "dsi0_phy_pll_out_dsiclk", 179 "gpll6_out_aux", 180 "core_bi_pll_test_se", 181 }; 182 183 static const struct parent_map gcc_parent_map_10[] = { 184 { P_XO, 0 }, 185 { P_SLEEP_CLK, 1 }, 186 { P_CORE_BI_PLL_TEST_SE, 7 }, 187 }; 188 189 static const char * const gcc_parent_names_10[] = { 190 "cxo", 191 "sleep_clk", 192 "core_bi_pll_test_se", 193 }; 194 195 static const struct parent_map gcc_parent_map_11[] = { 196 { P_XO, 0 }, 197 { P_PCIE_0_PIPE_CLK, 1 }, 198 { P_CORE_BI_PLL_TEST_SE, 7 }, 199 }; 200 201 static const char * const gcc_parent_names_11[] = { 202 "cxo", 203 "pcie_0_pipe_clk", 204 "core_bi_pll_test_se", 205 }; 206 207 static const struct parent_map gcc_parent_map_12[] = { 208 { P_XO, 0 }, 209 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 210 { P_GPLL0_OUT_AUX, 2 }, 211 { P_CORE_BI_PLL_TEST_SE, 7 }, 212 }; 213 214 static const char * const gcc_parent_names_12[] = { 215 "cxo", 216 "dsi0pll_pclk_src", 217 "gpll0_out_aux", 218 "core_bi_pll_test_se", 219 }; 220 221 static const struct parent_map gcc_parent_map_13[] = { 222 { P_XO, 0 }, 223 { P_GPLL0_OUT_MAIN, 1 }, 224 { P_GPLL4_OUT_MAIN, 2 }, 225 { P_GPLL6_OUT_AUX, 3 }, 226 { P_CORE_BI_PLL_TEST_SE, 7 }, 227 }; 228 229 static const char * const gcc_parent_names_13[] = { 230 "cxo", 231 "gpll0_out_main", 232 "gpll4_out_main", 233 "gpll6_out_aux", 234 "core_bi_pll_test_se", 235 }; 236 237 static const struct parent_map gcc_parent_map_14[] = { 238 { P_XO, 0 }, 239 { P_GPLL0_OUT_MAIN, 1 }, 240 { P_GPLL4_OUT_AUX, 2 }, 241 { P_CORE_BI_PLL_TEST_SE, 7 }, 242 }; 243 244 static const char * const gcc_parent_names_14[] = { 245 "cxo", 246 "gpll0_out_main", 247 "gpll4_out_aux", 248 "core_bi_pll_test_se", 249 }; 250 251 static const struct parent_map gcc_parent_map_15[] = { 252 { P_XO, 0 }, 253 { P_GPLL0_OUT_AUX, 2 }, 254 { P_CORE_BI_PLL_TEST_SE, 7 }, 255 }; 256 257 static const char * const gcc_parent_names_15[] = { 258 "cxo", 259 "gpll0_out_aux", 260 "core_bi_pll_test_se", 261 }; 262 263 static struct clk_fixed_factor cxo = { 264 .mult = 1, 265 .div = 1, 266 .hw.init = &(struct clk_init_data){ 267 .name = "cxo", 268 .parent_names = (const char *[]){ "xo-board" }, 269 .num_parents = 1, 270 .ops = &clk_fixed_factor_ops, 271 }, 272 }; 273 274 static struct clk_alpha_pll gpll0_sleep_clk_src = { 275 .offset = 0x21000, 276 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 277 .clkr = { 278 .enable_reg = 0x45008, 279 .enable_mask = BIT(23), 280 .enable_is_inverted = true, 281 .hw.init = &(struct clk_init_data){ 282 .name = "gpll0_sleep_clk_src", 283 .parent_names = (const char *[]){ "cxo" }, 284 .num_parents = 1, 285 .ops = &clk_alpha_pll_ops, 286 }, 287 }, 288 }; 289 290 static struct clk_alpha_pll gpll0_out_main = { 291 .offset = 0x21000, 292 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 293 .flags = SUPPORTS_FSM_MODE, 294 .clkr = { 295 .enable_reg = 0x45000, 296 .enable_mask = BIT(0), 297 .hw.init = &(struct clk_init_data){ 298 .name = "gpll0_out_main", 299 .parent_names = (const char *[]) 300 { "cxo" }, 301 .num_parents = 1, 302 .ops = &clk_alpha_pll_ops, 303 }, 304 }, 305 }; 306 307 static struct clk_alpha_pll gpll0_ao_out_main = { 308 .offset = 0x21000, 309 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 310 .flags = SUPPORTS_FSM_MODE, 311 .clkr = { 312 .enable_reg = 0x45000, 313 .enable_mask = BIT(0), 314 .hw.init = &(struct clk_init_data){ 315 .name = "gpll0_ao_out_main", 316 .parent_names = (const char *[]){ "cxo" }, 317 .num_parents = 1, 318 .flags = CLK_IS_CRITICAL, 319 .ops = &clk_alpha_pll_ops, 320 }, 321 }, 322 }; 323 324 static struct clk_alpha_pll gpll1_out_main = { 325 .offset = 0x20000, 326 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 327 .clkr = { 328 .enable_reg = 0x45000, 329 .enable_mask = BIT(1), 330 .hw.init = &(struct clk_init_data){ 331 .name = "gpll1_out_main", 332 .parent_names = (const char *[]){ "cxo" }, 333 .num_parents = 1, 334 .ops = &clk_alpha_pll_ops, 335 }, 336 }, 337 }; 338 339 /* 930MHz configuration */ 340 static const struct alpha_pll_config gpll3_config = { 341 .l = 48, 342 .alpha = 0x0, 343 .alpha_en_mask = BIT(24), 344 .post_div_mask = 0xf << 8, 345 .post_div_val = 0x1 << 8, 346 .vco_mask = 0x3 << 20, 347 .main_output_mask = 0x1, 348 .config_ctl_val = 0x4001055b, 349 }; 350 351 static const struct pll_vco gpll3_vco[] = { 352 { 700000000, 1400000000, 0 }, 353 }; 354 355 static struct clk_alpha_pll gpll3_out_main = { 356 .offset = 0x22000, 357 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 358 .vco_table = gpll3_vco, 359 .num_vco = ARRAY_SIZE(gpll3_vco), 360 .clkr = { 361 .hw.init = &(struct clk_init_data){ 362 .name = "gpll3_out_main", 363 .parent_names = (const char *[]){ "cxo" }, 364 .num_parents = 1, 365 .ops = &clk_alpha_pll_ops, 366 }, 367 }, 368 }; 369 370 static struct clk_alpha_pll gpll4_out_main = { 371 .offset = 0x24000, 372 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 373 .clkr = { 374 .enable_reg = 0x45000, 375 .enable_mask = BIT(5), 376 .hw.init = &(struct clk_init_data){ 377 .name = "gpll4_out_main", 378 .parent_names = (const char *[]){ "cxo" }, 379 .num_parents = 1, 380 .ops = &clk_alpha_pll_ops, 381 }, 382 }, 383 }; 384 385 static struct clk_pll gpll6 = { 386 .l_reg = 0x37004, 387 .m_reg = 0x37008, 388 .n_reg = 0x3700C, 389 .config_reg = 0x37014, 390 .mode_reg = 0x37000, 391 .status_reg = 0x3701C, 392 .status_bit = 17, 393 .clkr.hw.init = &(struct clk_init_data){ 394 .name = "gpll6", 395 .parent_names = (const char *[]){ "cxo" }, 396 .num_parents = 1, 397 .ops = &clk_pll_ops, 398 }, 399 }; 400 401 static struct clk_regmap gpll6_out_aux = { 402 .enable_reg = 0x45000, 403 .enable_mask = BIT(7), 404 .hw.init = &(struct clk_init_data){ 405 .name = "gpll6_out_aux", 406 .parent_names = (const char *[]){ "gpll6" }, 407 .num_parents = 1, 408 .ops = &clk_pll_vote_ops, 409 }, 410 }; 411 412 static const struct freq_tbl ftbl_apss_ahb_clk_src[] = { 413 F(19200000, P_XO, 1, 0, 0), 414 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 415 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 416 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0), 417 { } 418 }; 419 420 static struct clk_rcg2 apss_ahb_clk_src = { 421 .cmd_rcgr = 0x46000, 422 .mnd_width = 0, 423 .hid_width = 5, 424 .parent_map = gcc_parent_map_0, 425 .freq_tbl = ftbl_apss_ahb_clk_src, 426 .clkr.hw.init = &(struct clk_init_data){ 427 .name = "apss_ahb_clk_src", 428 .parent_names = gcc_parent_names_ao_0, 429 .num_parents = 3, 430 .flags = CLK_IS_CRITICAL, 431 .ops = &clk_rcg2_ops, 432 }, 433 }; 434 435 static const struct freq_tbl ftbl_blsp1_qup0_i2c_apps_clk_src[] = { 436 F(19200000, P_XO, 1, 0, 0), 437 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 438 { } 439 }; 440 441 static struct clk_rcg2 blsp1_qup0_i2c_apps_clk_src = { 442 .cmd_rcgr = 0x602c, 443 .mnd_width = 0, 444 .hid_width = 5, 445 .parent_map = gcc_parent_map_0, 446 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src, 447 .clkr.hw.init = &(struct clk_init_data){ 448 .name = "blsp1_qup0_i2c_apps_clk_src", 449 .parent_names = gcc_parent_names_0, 450 .num_parents = 3, 451 .ops = &clk_rcg2_ops, 452 }, 453 }; 454 455 static const struct freq_tbl ftbl_blsp1_qup0_spi_apps_clk_src[] = { 456 F(960000, P_XO, 10, 1, 2), 457 F(4800000, P_XO, 4, 0, 0), 458 F(9600000, P_XO, 2, 0, 0), 459 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5), 460 F(19200000, P_XO, 1, 0, 0), 461 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), 462 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 463 { } 464 }; 465 466 static struct clk_rcg2 blsp1_qup0_spi_apps_clk_src = { 467 .cmd_rcgr = 0x6034, 468 .mnd_width = 8, 469 .hid_width = 5, 470 .parent_map = gcc_parent_map_0, 471 .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src, 472 .clkr.hw.init = &(struct clk_init_data){ 473 .name = "blsp1_qup0_spi_apps_clk_src", 474 .parent_names = gcc_parent_names_0, 475 .num_parents = 3, 476 .ops = &clk_rcg2_ops, 477 }, 478 }; 479 480 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 481 .cmd_rcgr = 0x200c, 482 .mnd_width = 0, 483 .hid_width = 5, 484 .parent_map = gcc_parent_map_0, 485 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src, 486 .clkr.hw.init = &(struct clk_init_data){ 487 .name = "blsp1_qup1_i2c_apps_clk_src", 488 .parent_names = gcc_parent_names_0, 489 .num_parents = 3, 490 .ops = &clk_rcg2_ops, 491 }, 492 }; 493 494 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { 495 F(960000, P_XO, 10, 1, 2), 496 F(4800000, P_XO, 4, 0, 0), 497 F(9600000, P_XO, 2, 0, 0), 498 F(10480000, P_GPLL0_OUT_MAIN, 1, 3, 229), 499 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5), 500 F(19200000, P_XO, 1, 0, 0), 501 F(20961000, P_GPLL0_OUT_MAIN, 1, 6, 229), 502 { } 503 }; 504 505 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 506 .cmd_rcgr = 0x2024, 507 .mnd_width = 8, 508 .hid_width = 5, 509 .parent_map = gcc_parent_map_0, 510 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 511 .clkr.hw.init = &(struct clk_init_data){ 512 .name = "blsp1_qup1_spi_apps_clk_src", 513 .parent_names = gcc_parent_names_0, 514 .num_parents = 3, 515 .ops = &clk_rcg2_ops, 516 }, 517 }; 518 519 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 520 .cmd_rcgr = 0x3000, 521 .mnd_width = 0, 522 .hid_width = 5, 523 .parent_map = gcc_parent_map_0, 524 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src, 525 .clkr.hw.init = &(struct clk_init_data){ 526 .name = "blsp1_qup2_i2c_apps_clk_src", 527 .parent_names = gcc_parent_names_0, 528 .num_parents = 3, 529 .ops = &clk_rcg2_ops, 530 }, 531 }; 532 533 static const struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = { 534 F(960000, P_XO, 10, 1, 2), 535 F(4800000, P_XO, 4, 0, 0), 536 F(9600000, P_XO, 2, 0, 0), 537 F(15000000, P_GPLL0_OUT_MAIN, 1, 3, 160), 538 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5), 539 F(19200000, P_XO, 1, 0, 0), 540 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), 541 F(30000000, P_GPLL0_OUT_MAIN, 1, 3, 80), 542 { } 543 }; 544 545 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 546 .cmd_rcgr = 0x3014, 547 .mnd_width = 8, 548 .hid_width = 5, 549 .parent_map = gcc_parent_map_0, 550 .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src, 551 .clkr.hw.init = &(struct clk_init_data){ 552 .name = "blsp1_qup2_spi_apps_clk_src", 553 .parent_names = gcc_parent_names_0, 554 .num_parents = 3, 555 .ops = &clk_rcg2_ops, 556 }, 557 }; 558 559 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 560 .cmd_rcgr = 0x4000, 561 .mnd_width = 0, 562 .hid_width = 5, 563 .parent_map = gcc_parent_map_0, 564 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src, 565 .clkr.hw.init = &(struct clk_init_data){ 566 .name = "blsp1_qup3_i2c_apps_clk_src", 567 .parent_names = gcc_parent_names_0, 568 .num_parents = 3, 569 .ops = &clk_rcg2_ops, 570 }, 571 }; 572 573 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 574 .cmd_rcgr = 0x4024, 575 .mnd_width = 8, 576 .hid_width = 5, 577 .parent_map = gcc_parent_map_0, 578 .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src, 579 .clkr.hw.init = &(struct clk_init_data){ 580 .name = "blsp1_qup3_spi_apps_clk_src", 581 .parent_names = gcc_parent_names_0, 582 .num_parents = 3, 583 .ops = &clk_rcg2_ops, 584 }, 585 }; 586 587 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 588 .cmd_rcgr = 0x5000, 589 .mnd_width = 0, 590 .hid_width = 5, 591 .parent_map = gcc_parent_map_0, 592 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src, 593 .clkr.hw.init = &(struct clk_init_data){ 594 .name = "blsp1_qup4_i2c_apps_clk_src", 595 .parent_names = gcc_parent_names_0, 596 .num_parents = 3, 597 .ops = &clk_rcg2_ops, 598 }, 599 }; 600 601 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 602 .cmd_rcgr = 0x5024, 603 .mnd_width = 8, 604 .hid_width = 5, 605 .parent_map = gcc_parent_map_0, 606 .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src, 607 .clkr.hw.init = &(struct clk_init_data){ 608 .name = "blsp1_qup4_spi_apps_clk_src", 609 .parent_names = gcc_parent_names_0, 610 .num_parents = 3, 611 .ops = &clk_rcg2_ops, 612 }, 613 }; 614 615 static const struct freq_tbl ftbl_blsp1_uart0_apps_clk_src[] = { 616 F(3686400, P_GPLL0_OUT_MAIN, 1, 72, 15625), 617 F(7372800, P_GPLL0_OUT_MAIN, 1, 144, 15625), 618 F(14745600, P_GPLL0_OUT_MAIN, 1, 288, 15625), 619 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5), 620 F(19200000, P_XO, 1, 0, 0), 621 F(24000000, P_GPLL0_OUT_MAIN, 1, 3, 100), 622 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), 623 F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25), 624 F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20), 625 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500), 626 F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50), 627 F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125), 628 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100), 629 F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625), 630 F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40), 631 F(64000000, P_GPLL0_OUT_MAIN, 1, 2, 25), 632 { } 633 }; 634 635 static struct clk_rcg2 blsp1_uart0_apps_clk_src = { 636 .cmd_rcgr = 0x600c, 637 .mnd_width = 16, 638 .hid_width = 5, 639 .parent_map = gcc_parent_map_0, 640 .freq_tbl = ftbl_blsp1_uart0_apps_clk_src, 641 .clkr.hw.init = &(struct clk_init_data){ 642 .name = "blsp1_uart0_apps_clk_src", 643 .parent_names = gcc_parent_names_0, 644 .num_parents = 3, 645 .ops = &clk_rcg2_ops, 646 }, 647 }; 648 649 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 650 .cmd_rcgr = 0x2044, 651 .mnd_width = 16, 652 .hid_width = 5, 653 .parent_map = gcc_parent_map_0, 654 .freq_tbl = ftbl_blsp1_uart0_apps_clk_src, 655 .clkr.hw.init = &(struct clk_init_data){ 656 .name = "blsp1_uart1_apps_clk_src", 657 .parent_names = gcc_parent_names_0, 658 .num_parents = 3, 659 .ops = &clk_rcg2_ops, 660 }, 661 }; 662 663 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 664 .cmd_rcgr = 0x3034, 665 .mnd_width = 16, 666 .hid_width = 5, 667 .parent_map = gcc_parent_map_0, 668 .freq_tbl = ftbl_blsp1_uart0_apps_clk_src, 669 .clkr.hw.init = &(struct clk_init_data){ 670 .name = "blsp1_uart2_apps_clk_src", 671 .parent_names = gcc_parent_names_0, 672 .num_parents = 3, 673 .ops = &clk_rcg2_ops, 674 }, 675 }; 676 677 static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 678 .cmd_rcgr = 0x4014, 679 .mnd_width = 16, 680 .hid_width = 5, 681 .cfg_off = 0x20, 682 .parent_map = gcc_parent_map_0, 683 .freq_tbl = ftbl_blsp1_uart0_apps_clk_src, 684 .clkr.hw.init = &(struct clk_init_data){ 685 .name = "blsp1_uart3_apps_clk_src", 686 .parent_names = gcc_parent_names_0, 687 .num_parents = 3, 688 .ops = &clk_rcg2_ops, 689 }, 690 }; 691 692 static struct clk_rcg2 blsp2_qup0_i2c_apps_clk_src = { 693 .cmd_rcgr = 0xc00c, 694 .mnd_width = 0, 695 .hid_width = 5, 696 .parent_map = gcc_parent_map_0, 697 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src, 698 .clkr.hw.init = &(struct clk_init_data){ 699 .name = "blsp2_qup0_i2c_apps_clk_src", 700 .parent_names = gcc_parent_names_0, 701 .num_parents = 3, 702 .ops = &clk_rcg2_ops, 703 }, 704 }; 705 706 static struct clk_rcg2 blsp2_qup0_spi_apps_clk_src = { 707 .cmd_rcgr = 0xc024, 708 .mnd_width = 8, 709 .hid_width = 5, 710 .parent_map = gcc_parent_map_0, 711 .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src, 712 .clkr.hw.init = &(struct clk_init_data){ 713 .name = "blsp2_qup0_spi_apps_clk_src", 714 .parent_names = gcc_parent_names_0, 715 .num_parents = 3, 716 .ops = &clk_rcg2_ops, 717 }, 718 }; 719 720 static struct clk_rcg2 blsp2_uart0_apps_clk_src = { 721 .cmd_rcgr = 0xc044, 722 .mnd_width = 16, 723 .hid_width = 5, 724 .parent_map = gcc_parent_map_0, 725 .freq_tbl = ftbl_blsp1_uart0_apps_clk_src, 726 .clkr.hw.init = &(struct clk_init_data){ 727 .name = "blsp2_uart0_apps_clk_src", 728 .parent_names = gcc_parent_names_0, 729 .num_parents = 3, 730 .ops = &clk_rcg2_ops, 731 }, 732 }; 733 734 static struct clk_rcg2 byte0_clk_src = { 735 .cmd_rcgr = 0x4d044, 736 .mnd_width = 0, 737 .hid_width = 5, 738 .parent_map = gcc_parent_map_5, 739 .clkr.hw.init = &(struct clk_init_data){ 740 .name = "byte0_clk_src", 741 .parent_names = gcc_parent_names_5, 742 .num_parents = 4, 743 .flags = CLK_SET_RATE_PARENT, 744 .ops = &clk_byte2_ops, 745 }, 746 }; 747 748 static const struct freq_tbl ftbl_emac_clk_src[] = { 749 F(5000000, P_GPLL1_OUT_MAIN, 2, 1, 50), 750 F(50000000, P_GPLL1_OUT_MAIN, 10, 0, 0), 751 F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0), 752 F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0), 753 { } 754 }; 755 756 static struct clk_rcg2 emac_clk_src = { 757 .cmd_rcgr = 0x4e01c, 758 .mnd_width = 8, 759 .hid_width = 5, 760 .parent_map = gcc_parent_map_4, 761 .freq_tbl = ftbl_emac_clk_src, 762 .clkr.hw.init = &(struct clk_init_data){ 763 .name = "emac_clk_src", 764 .parent_names = gcc_parent_names_4, 765 .num_parents = 3, 766 .ops = &clk_rcg2_ops, 767 }, 768 }; 769 770 static const struct freq_tbl ftbl_emac_ptp_clk_src[] = { 771 F(50000000, P_GPLL1_OUT_MAIN, 10, 0, 0), 772 F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0), 773 F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0), 774 { } 775 }; 776 777 static struct clk_rcg2 emac_ptp_clk_src = { 778 .cmd_rcgr = 0x4e014, 779 .mnd_width = 0, 780 .hid_width = 5, 781 .parent_map = gcc_parent_map_4, 782 .freq_tbl = ftbl_emac_ptp_clk_src, 783 .clkr.hw.init = &(struct clk_init_data){ 784 .name = "emac_ptp_clk_src", 785 .parent_names = gcc_parent_names_4, 786 .num_parents = 3, 787 .ops = &clk_rcg2_ops, 788 }, 789 }; 790 791 static const struct freq_tbl ftbl_esc0_clk_src[] = { 792 F(19200000, P_XO, 1, 0, 0), 793 { } 794 }; 795 796 static struct clk_rcg2 esc0_clk_src = { 797 .cmd_rcgr = 0x4d05c, 798 .mnd_width = 0, 799 .hid_width = 5, 800 .parent_map = gcc_parent_map_6, 801 .freq_tbl = ftbl_esc0_clk_src, 802 .clkr.hw.init = &(struct clk_init_data){ 803 .name = "esc0_clk_src", 804 .parent_names = gcc_parent_names_6, 805 .num_parents = 4, 806 .ops = &clk_rcg2_ops, 807 }, 808 }; 809 810 static const struct freq_tbl ftbl_gfx3d_clk_src[] = { 811 F(19200000, P_XO, 1, 0, 0), 812 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 813 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 814 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 815 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0), 816 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 817 F(228571429, P_GPLL0_OUT_MAIN, 3.5, 0, 0), 818 F(240000000, P_GPLL6_OUT_AUX, 4.5, 0, 0), 819 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0), 820 F(270000000, P_GPLL6_OUT_AUX, 4, 0, 0), 821 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 822 F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 823 F(484800000, P_GPLL3_OUT_MAIN, 1, 0, 0), 824 F(523200000, P_GPLL3_OUT_MAIN, 1, 0, 0), 825 F(550000000, P_GPLL3_OUT_MAIN, 1, 0, 0), 826 F(598000000, P_GPLL3_OUT_MAIN, 1, 0, 0), 827 { } 828 }; 829 830 static struct clk_rcg2 gfx3d_clk_src = { 831 .cmd_rcgr = 0x59000, 832 .mnd_width = 0, 833 .hid_width = 5, 834 .parent_map = gcc_parent_map_7, 835 .freq_tbl = ftbl_gfx3d_clk_src, 836 .clkr.hw.init = &(struct clk_init_data){ 837 .name = "gfx3d_clk_src", 838 .parent_names = gcc_parent_names_7, 839 .num_parents = 6, 840 .ops = &clk_rcg2_ops, 841 }, 842 }; 843 844 static const struct freq_tbl ftbl_gp1_clk_src[] = { 845 F(19200000, P_XO, 1, 0, 0), 846 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 847 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 848 { } 849 }; 850 851 static struct clk_rcg2 gp1_clk_src = { 852 .cmd_rcgr = 0x8004, 853 .mnd_width = 8, 854 .hid_width = 5, 855 .parent_map = gcc_parent_map_2, 856 .freq_tbl = ftbl_gp1_clk_src, 857 .clkr.hw.init = &(struct clk_init_data){ 858 .name = "gp1_clk_src", 859 .parent_names = gcc_parent_names_2, 860 .num_parents = 4, 861 .ops = &clk_rcg2_ops, 862 }, 863 }; 864 865 static struct clk_rcg2 gp2_clk_src = { 866 .cmd_rcgr = 0x9004, 867 .mnd_width = 8, 868 .hid_width = 5, 869 .parent_map = gcc_parent_map_2, 870 .freq_tbl = ftbl_gp1_clk_src, 871 .clkr.hw.init = &(struct clk_init_data){ 872 .name = "gp2_clk_src", 873 .parent_names = gcc_parent_names_2, 874 .num_parents = 4, 875 .ops = &clk_rcg2_ops, 876 }, 877 }; 878 879 static struct clk_rcg2 gp3_clk_src = { 880 .cmd_rcgr = 0xa004, 881 .mnd_width = 8, 882 .hid_width = 5, 883 .parent_map = gcc_parent_map_2, 884 .freq_tbl = ftbl_gp1_clk_src, 885 .clkr.hw.init = &(struct clk_init_data){ 886 .name = "gp3_clk_src", 887 .parent_names = gcc_parent_names_2, 888 .num_parents = 4, 889 .ops = &clk_rcg2_ops, 890 }, 891 }; 892 893 static struct clk_rcg2 hdmi_app_clk_src = { 894 .cmd_rcgr = 0x4d0e4, 895 .mnd_width = 0, 896 .hid_width = 5, 897 .parent_map = gcc_parent_map_1, 898 .freq_tbl = ftbl_esc0_clk_src, 899 .clkr.hw.init = &(struct clk_init_data){ 900 .name = "hdmi_app_clk_src", 901 .parent_names = gcc_parent_names_1, 902 .num_parents = 2, 903 .ops = &clk_rcg2_ops, 904 }, 905 }; 906 907 static struct clk_rcg2 hdmi_pclk_clk_src = { 908 .cmd_rcgr = 0x4d0dc, 909 .mnd_width = 0, 910 .hid_width = 5, 911 .parent_map = gcc_parent_map_8, 912 .freq_tbl = ftbl_esc0_clk_src, 913 .clkr.hw.init = &(struct clk_init_data){ 914 .name = "hdmi_pclk_clk_src", 915 .parent_names = gcc_parent_names_8, 916 .num_parents = 3, 917 .ops = &clk_rcg2_ops, 918 }, 919 }; 920 921 static const struct freq_tbl ftbl_mdp_clk_src[] = { 922 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 923 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 924 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 925 F(145454545, P_GPLL0_OUT_MAIN, 5.5, 0, 0), 926 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0), 927 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 928 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 929 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0), 930 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 931 { } 932 }; 933 934 static struct clk_rcg2 mdp_clk_src = { 935 .cmd_rcgr = 0x4d014, 936 .mnd_width = 0, 937 .hid_width = 5, 938 .parent_map = gcc_parent_map_9, 939 .freq_tbl = ftbl_mdp_clk_src, 940 .clkr.hw.init = &(struct clk_init_data){ 941 .name = "mdp_clk_src", 942 .parent_names = gcc_parent_names_9, 943 .num_parents = 5, 944 .ops = &clk_rcg2_ops, 945 }, 946 }; 947 948 static const struct freq_tbl ftbl_pcie_0_aux_clk_src[] = { 949 F(1200000, P_XO, 16, 0, 0), 950 { } 951 }; 952 953 static struct clk_rcg2 pcie_0_aux_clk_src = { 954 .cmd_rcgr = 0x3e024, 955 .mnd_width = 16, 956 .hid_width = 5, 957 .parent_map = gcc_parent_map_10, 958 .freq_tbl = ftbl_pcie_0_aux_clk_src, 959 .clkr.hw.init = &(struct clk_init_data){ 960 .name = "pcie_0_aux_clk_src", 961 .parent_names = gcc_parent_names_10, 962 .num_parents = 3, 963 .ops = &clk_rcg2_ops, 964 }, 965 }; 966 967 static const struct freq_tbl ftbl_pcie_0_pipe_clk_src[] = { 968 F(19200000, P_XO, 1, 0, 0), 969 F(125000000, P_PCIE_0_PIPE_CLK, 2, 0, 0), 970 F(250000000, P_PCIE_0_PIPE_CLK, 1, 0, 0), 971 { } 972 }; 973 974 static struct clk_rcg2 pcie_0_pipe_clk_src = { 975 .cmd_rcgr = 0x3e01c, 976 .mnd_width = 0, 977 .hid_width = 5, 978 .parent_map = gcc_parent_map_11, 979 .freq_tbl = ftbl_pcie_0_pipe_clk_src, 980 .clkr.hw.init = &(struct clk_init_data){ 981 .name = "pcie_0_pipe_clk_src", 982 .parent_names = gcc_parent_names_11, 983 .num_parents = 3, 984 .ops = &clk_rcg2_ops, 985 }, 986 }; 987 988 static struct clk_rcg2 pclk0_clk_src = { 989 .cmd_rcgr = 0x4d000, 990 .mnd_width = 8, 991 .hid_width = 5, 992 .parent_map = gcc_parent_map_12, 993 .clkr.hw.init = &(struct clk_init_data){ 994 .name = "pclk0_clk_src", 995 .parent_names = gcc_parent_names_12, 996 .num_parents = 4, 997 .flags = CLK_SET_RATE_PARENT, 998 .ops = &clk_pixel_ops, 999 }, 1000 }; 1001 1002 static const struct freq_tbl ftbl_pdm2_clk_src[] = { 1003 F(19200000, P_XO, 1, 0, 0), 1004 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), 1005 { } 1006 }; 1007 1008 static struct clk_rcg2 pdm2_clk_src = { 1009 .cmd_rcgr = 0x44010, 1010 .mnd_width = 0, 1011 .hid_width = 5, 1012 .parent_map = gcc_parent_map_0, 1013 .freq_tbl = ftbl_pdm2_clk_src, 1014 .clkr.hw.init = &(struct clk_init_data){ 1015 .name = "pdm2_clk_src", 1016 .parent_names = gcc_parent_names_0, 1017 .num_parents = 3, 1018 .ops = &clk_rcg2_ops, 1019 }, 1020 }; 1021 1022 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { 1023 F(144000, P_XO, 16, 3, 25), 1024 F(400000, P_XO, 12, 1, 4), 1025 F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4), 1026 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), 1027 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 1028 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 1029 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 1030 F(192000000, P_GPLL4_OUT_MAIN, 6, 0, 0), 1031 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 1032 F(384000000, P_GPLL4_OUT_MAIN, 3, 0, 0), 1033 { } 1034 }; 1035 1036 static struct clk_rcg2 sdcc1_apps_clk_src = { 1037 .cmd_rcgr = 0x42004, 1038 .mnd_width = 8, 1039 .hid_width = 5, 1040 .parent_map = gcc_parent_map_13, 1041 .freq_tbl = ftbl_sdcc1_apps_clk_src, 1042 .clkr.hw.init = &(struct clk_init_data){ 1043 .name = "sdcc1_apps_clk_src", 1044 .parent_names = gcc_parent_names_13, 1045 .num_parents = 5, 1046 .ops = &clk_rcg2_ops, 1047 }, 1048 }; 1049 1050 static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = { 1051 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0), 1052 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0), 1053 { } 1054 }; 1055 1056 static struct clk_rcg2 sdcc1_ice_core_clk_src = { 1057 .cmd_rcgr = 0x5d000, 1058 .mnd_width = 8, 1059 .hid_width = 5, 1060 .parent_map = gcc_parent_map_3, 1061 .freq_tbl = ftbl_sdcc1_ice_core_clk_src, 1062 .clkr.hw.init = &(struct clk_init_data){ 1063 .name = "sdcc1_ice_core_clk_src", 1064 .parent_names = gcc_parent_names_3, 1065 .num_parents = 4, 1066 .ops = &clk_rcg2_ops, 1067 }, 1068 }; 1069 1070 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = { 1071 F(144000, P_XO, 16, 3, 25), 1072 F(400000, P_XO, 12, 1, 4), 1073 F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4), 1074 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), 1075 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 1076 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 1077 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 1078 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 1079 { } 1080 }; 1081 1082 static struct clk_rcg2 sdcc2_apps_clk_src = { 1083 .cmd_rcgr = 0x43004, 1084 .mnd_width = 8, 1085 .hid_width = 5, 1086 .parent_map = gcc_parent_map_14, 1087 .freq_tbl = ftbl_sdcc2_apps_clk_src, 1088 .clkr.hw.init = &(struct clk_init_data){ 1089 .name = "sdcc2_apps_clk_src", 1090 .parent_names = gcc_parent_names_14, 1091 .num_parents = 4, 1092 .ops = &clk_rcg2_ops, 1093 }, 1094 }; 1095 1096 static struct clk_rcg2 usb20_mock_utmi_clk_src = { 1097 .cmd_rcgr = 0x41048, 1098 .mnd_width = 0, 1099 .hid_width = 5, 1100 .parent_map = gcc_parent_map_1, 1101 .freq_tbl = ftbl_esc0_clk_src, 1102 .clkr.hw.init = &(struct clk_init_data){ 1103 .name = "usb20_mock_utmi_clk_src", 1104 .parent_names = gcc_parent_names_1, 1105 .num_parents = 2, 1106 .ops = &clk_rcg2_ops, 1107 }, 1108 }; 1109 1110 static const struct freq_tbl ftbl_usb30_master_clk_src[] = { 1111 F(19200000, P_XO, 1, 0, 0), 1112 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 1113 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 1114 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0), 1115 { } 1116 }; 1117 1118 static struct clk_rcg2 usb30_master_clk_src = { 1119 .cmd_rcgr = 0x39028, 1120 .mnd_width = 8, 1121 .hid_width = 5, 1122 .parent_map = gcc_parent_map_0, 1123 .freq_tbl = ftbl_usb30_master_clk_src, 1124 .clkr.hw.init = &(struct clk_init_data){ 1125 .name = "usb30_master_clk_src", 1126 .parent_names = gcc_parent_names_0, 1127 .num_parents = 3, 1128 .ops = &clk_rcg2_ops, 1129 }, 1130 }; 1131 1132 static struct clk_rcg2 usb30_mock_utmi_clk_src = { 1133 .cmd_rcgr = 0x3901c, 1134 .mnd_width = 0, 1135 .hid_width = 5, 1136 .parent_map = gcc_parent_map_1, 1137 .freq_tbl = ftbl_esc0_clk_src, 1138 .clkr.hw.init = &(struct clk_init_data){ 1139 .name = "usb30_mock_utmi_clk_src", 1140 .parent_names = gcc_parent_names_1, 1141 .num_parents = 2, 1142 .ops = &clk_rcg2_ops, 1143 }, 1144 }; 1145 1146 static struct clk_rcg2 usb3_phy_aux_clk_src = { 1147 .cmd_rcgr = 0x3903c, 1148 .mnd_width = 0, 1149 .hid_width = 5, 1150 .parent_map = gcc_parent_map_1, 1151 .freq_tbl = ftbl_pcie_0_aux_clk_src, 1152 .clkr.hw.init = &(struct clk_init_data){ 1153 .name = "usb3_phy_aux_clk_src", 1154 .parent_names = gcc_parent_names_1, 1155 .num_parents = 2, 1156 .ops = &clk_rcg2_ops, 1157 }, 1158 }; 1159 1160 static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = { 1161 F(19200000, P_XO, 1, 0, 0), 1162 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 1163 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 1164 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0), 1165 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 1166 { } 1167 }; 1168 1169 static struct clk_rcg2 usb_hs_system_clk_src = { 1170 .cmd_rcgr = 0x41010, 1171 .mnd_width = 0, 1172 .hid_width = 5, 1173 .parent_map = gcc_parent_map_3, 1174 .freq_tbl = ftbl_usb_hs_system_clk_src, 1175 .clkr.hw.init = &(struct clk_init_data){ 1176 .name = "usb_hs_system_clk_src", 1177 .parent_names = gcc_parent_names_3, 1178 .num_parents = 4, 1179 .ops = &clk_rcg2_ops, 1180 }, 1181 }; 1182 1183 static struct clk_rcg2 vsync_clk_src = { 1184 .cmd_rcgr = 0x4d02c, 1185 .mnd_width = 0, 1186 .hid_width = 5, 1187 .parent_map = gcc_parent_map_15, 1188 .freq_tbl = ftbl_esc0_clk_src, 1189 .clkr.hw.init = &(struct clk_init_data){ 1190 .name = "vsync_clk_src", 1191 .parent_names = gcc_parent_names_15, 1192 .num_parents = 3, 1193 .ops = &clk_rcg2_ops, 1194 }, 1195 }; 1196 1197 static struct clk_branch gcc_apss_ahb_clk = { 1198 .halt_reg = 0x4601c, 1199 .halt_check = BRANCH_HALT_VOTED, 1200 .clkr = { 1201 .enable_reg = 0x45004, 1202 .enable_mask = BIT(14), 1203 .hw.init = &(struct clk_init_data){ 1204 .name = "gcc_apss_ahb_clk", 1205 .parent_names = (const char *[]){ 1206 "apss_ahb_clk_src", 1207 }, 1208 .num_parents = 1, 1209 .flags = CLK_SET_RATE_PARENT, 1210 .ops = &clk_branch2_ops, 1211 }, 1212 }, 1213 }; 1214 1215 static struct clk_branch gcc_apss_tcu_clk = { 1216 .halt_reg = 0x5b004, 1217 .halt_check = BRANCH_VOTED, 1218 .clkr = { 1219 .enable_reg = 0x4500c, 1220 .enable_mask = BIT(1), 1221 .hw.init = &(struct clk_init_data){ 1222 .name = "gcc_apss_tcu_clk", 1223 .ops = &clk_branch2_ops, 1224 }, 1225 }, 1226 }; 1227 1228 static struct clk_branch gcc_bimc_gfx_clk = { 1229 .halt_reg = 0x59034, 1230 .halt_check = BRANCH_HALT, 1231 .clkr = { 1232 .enable_reg = 0x59034, 1233 .enable_mask = BIT(0), 1234 .hw.init = &(struct clk_init_data){ 1235 .name = "gcc_bimc_gfx_clk", 1236 .ops = &clk_branch2_ops, 1237 .parent_names = (const char *[]){ 1238 "gcc_apss_tcu_clk", 1239 }, 1240 1241 }, 1242 }, 1243 }; 1244 1245 static struct clk_branch gcc_bimc_gpu_clk = { 1246 .halt_reg = 0x59030, 1247 .halt_check = BRANCH_HALT, 1248 .clkr = { 1249 .enable_reg = 0x59030, 1250 .enable_mask = BIT(0), 1251 .hw.init = &(struct clk_init_data){ 1252 .name = "gcc_bimc_gpu_clk", 1253 .ops = &clk_branch2_ops, 1254 }, 1255 }, 1256 }; 1257 1258 static struct clk_branch gcc_bimc_mdss_clk = { 1259 .halt_reg = 0x31038, 1260 .halt_check = BRANCH_HALT, 1261 .clkr = { 1262 .enable_reg = 0x31038, 1263 .enable_mask = BIT(0), 1264 .hw.init = &(struct clk_init_data){ 1265 .name = "gcc_bimc_mdss_clk", 1266 .ops = &clk_branch2_ops, 1267 }, 1268 }, 1269 }; 1270 1271 static struct clk_branch gcc_blsp1_ahb_clk = { 1272 .halt_reg = 0x1008, 1273 .halt_check = BRANCH_HALT_VOTED, 1274 .clkr = { 1275 .enable_reg = 0x45004, 1276 .enable_mask = BIT(10), 1277 .hw.init = &(struct clk_init_data){ 1278 .name = "gcc_blsp1_ahb_clk", 1279 .ops = &clk_branch2_ops, 1280 }, 1281 }, 1282 }; 1283 1284 static struct clk_branch gcc_dcc_clk = { 1285 .halt_reg = 0x77004, 1286 .halt_check = BRANCH_HALT, 1287 .clkr = { 1288 .enable_reg = 0x77004, 1289 .enable_mask = BIT(0), 1290 .hw.init = &(struct clk_init_data){ 1291 .name = "gcc_dcc_clk", 1292 .ops = &clk_branch2_ops, 1293 }, 1294 }, 1295 }; 1296 1297 static struct clk_branch gcc_dcc_xo_clk = { 1298 .halt_reg = 0x77008, 1299 .halt_check = BRANCH_HALT, 1300 .clkr = { 1301 .enable_reg = 0x77008, 1302 .enable_mask = BIT(0), 1303 .hw.init = &(struct clk_init_data){ 1304 .name = "gcc_dcc_xo_clk", 1305 .ops = &clk_branch2_ops, 1306 }, 1307 }, 1308 }; 1309 1310 static struct clk_branch gcc_blsp1_qup0_i2c_apps_clk = { 1311 .halt_reg = 0x6028, 1312 .halt_check = BRANCH_HALT, 1313 .clkr = { 1314 .enable_reg = 0x6028, 1315 .enable_mask = BIT(0), 1316 .hw.init = &(struct clk_init_data){ 1317 .name = "gcc_blsp1_qup0_i2c_apps_clk", 1318 .parent_names = (const char *[]){ 1319 "blsp1_qup0_i2c_apps_clk_src", 1320 }, 1321 .num_parents = 1, 1322 .flags = CLK_SET_RATE_PARENT, 1323 .ops = &clk_branch2_ops, 1324 }, 1325 }, 1326 }; 1327 1328 static struct clk_branch gcc_blsp1_qup0_spi_apps_clk = { 1329 .halt_reg = 0x6024, 1330 .halt_check = BRANCH_HALT, 1331 .clkr = { 1332 .enable_reg = 0x6024, 1333 .enable_mask = BIT(0), 1334 .hw.init = &(struct clk_init_data){ 1335 .name = "gcc_blsp1_qup0_spi_apps_clk", 1336 .parent_names = (const char *[]){ 1337 "blsp1_qup0_spi_apps_clk_src", 1338 }, 1339 .num_parents = 1, 1340 .flags = CLK_SET_RATE_PARENT, 1341 .ops = &clk_branch2_ops, 1342 }, 1343 }, 1344 }; 1345 1346 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1347 .halt_reg = 0x2008, 1348 .halt_check = BRANCH_HALT, 1349 .clkr = { 1350 .enable_reg = 0x2008, 1351 .enable_mask = BIT(0), 1352 .hw.init = &(struct clk_init_data){ 1353 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1354 .parent_names = (const char *[]){ 1355 "blsp1_qup1_i2c_apps_clk_src", 1356 }, 1357 .num_parents = 1, 1358 .flags = CLK_SET_RATE_PARENT, 1359 .ops = &clk_branch2_ops, 1360 }, 1361 }, 1362 }; 1363 1364 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1365 .halt_reg = 0x2004, 1366 .halt_check = BRANCH_HALT, 1367 .clkr = { 1368 .enable_reg = 0x2004, 1369 .enable_mask = BIT(0), 1370 .hw.init = &(struct clk_init_data){ 1371 .name = "gcc_blsp1_qup1_spi_apps_clk", 1372 .parent_names = (const char *[]){ 1373 "blsp1_qup1_spi_apps_clk_src", 1374 }, 1375 .num_parents = 1, 1376 .flags = CLK_SET_RATE_PARENT, 1377 .ops = &clk_branch2_ops, 1378 }, 1379 }, 1380 }; 1381 1382 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1383 .halt_reg = 0x3010, 1384 .halt_check = BRANCH_HALT, 1385 .clkr = { 1386 .enable_reg = 0x3010, 1387 .enable_mask = BIT(0), 1388 .hw.init = &(struct clk_init_data){ 1389 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1390 .parent_names = (const char *[]){ 1391 "blsp1_qup2_i2c_apps_clk_src", 1392 }, 1393 .num_parents = 1, 1394 .flags = CLK_SET_RATE_PARENT, 1395 .ops = &clk_branch2_ops, 1396 }, 1397 }, 1398 }; 1399 1400 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1401 .halt_reg = 0x300c, 1402 .halt_check = BRANCH_HALT, 1403 .clkr = { 1404 .enable_reg = 0x300c, 1405 .enable_mask = BIT(0), 1406 .hw.init = &(struct clk_init_data){ 1407 .name = "gcc_blsp1_qup2_spi_apps_clk", 1408 .parent_names = (const char *[]){ 1409 "blsp1_qup2_spi_apps_clk_src", 1410 }, 1411 .num_parents = 1, 1412 .flags = CLK_SET_RATE_PARENT, 1413 .ops = &clk_branch2_ops, 1414 }, 1415 }, 1416 }; 1417 1418 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1419 .halt_reg = 0x4020, 1420 .halt_check = BRANCH_HALT, 1421 .clkr = { 1422 .enable_reg = 0x4020, 1423 .enable_mask = BIT(0), 1424 .hw.init = &(struct clk_init_data){ 1425 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1426 .parent_names = (const char *[]){ 1427 "blsp1_qup3_i2c_apps_clk_src", 1428 }, 1429 .num_parents = 1, 1430 .flags = CLK_SET_RATE_PARENT, 1431 .ops = &clk_branch2_ops, 1432 }, 1433 }, 1434 }; 1435 1436 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1437 .halt_reg = 0x401c, 1438 .halt_check = BRANCH_HALT, 1439 .clkr = { 1440 .enable_reg = 0x401c, 1441 .enable_mask = BIT(0), 1442 .hw.init = &(struct clk_init_data){ 1443 .name = "gcc_blsp1_qup3_spi_apps_clk", 1444 .parent_names = (const char *[]){ 1445 "blsp1_qup3_spi_apps_clk_src", 1446 }, 1447 .num_parents = 1, 1448 .flags = CLK_SET_RATE_PARENT, 1449 .ops = &clk_branch2_ops, 1450 }, 1451 }, 1452 }; 1453 1454 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1455 .halt_reg = 0x5020, 1456 .halt_check = BRANCH_HALT, 1457 .clkr = { 1458 .enable_reg = 0x5020, 1459 .enable_mask = BIT(0), 1460 .hw.init = &(struct clk_init_data){ 1461 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1462 .parent_names = (const char *[]){ 1463 "blsp1_qup4_i2c_apps_clk_src", 1464 }, 1465 .num_parents = 1, 1466 .flags = CLK_SET_RATE_PARENT, 1467 .ops = &clk_branch2_ops, 1468 }, 1469 }, 1470 }; 1471 1472 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1473 .halt_reg = 0x501c, 1474 .halt_check = BRANCH_HALT, 1475 .clkr = { 1476 .enable_reg = 0x501c, 1477 .enable_mask = BIT(0), 1478 .hw.init = &(struct clk_init_data){ 1479 .name = "gcc_blsp1_qup4_spi_apps_clk", 1480 .parent_names = (const char *[]){ 1481 "blsp1_qup4_spi_apps_clk_src", 1482 }, 1483 .num_parents = 1, 1484 .flags = CLK_SET_RATE_PARENT, 1485 .ops = &clk_branch2_ops, 1486 }, 1487 }, 1488 }; 1489 1490 static struct clk_branch gcc_blsp1_uart0_apps_clk = { 1491 .halt_reg = 0x6004, 1492 .halt_check = BRANCH_HALT, 1493 .clkr = { 1494 .enable_reg = 0x6004, 1495 .enable_mask = BIT(0), 1496 .hw.init = &(struct clk_init_data){ 1497 .name = "gcc_blsp1_uart0_apps_clk", 1498 .parent_names = (const char *[]){ 1499 "blsp1_uart0_apps_clk_src", 1500 }, 1501 .num_parents = 1, 1502 .flags = CLK_SET_RATE_PARENT, 1503 .ops = &clk_branch2_ops, 1504 }, 1505 }, 1506 }; 1507 1508 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1509 .halt_reg = 0x203c, 1510 .halt_check = BRANCH_HALT, 1511 .clkr = { 1512 .enable_reg = 0x203c, 1513 .enable_mask = BIT(0), 1514 .hw.init = &(struct clk_init_data){ 1515 .name = "gcc_blsp1_uart1_apps_clk", 1516 .parent_names = (const char *[]){ 1517 "blsp1_uart1_apps_clk_src", 1518 }, 1519 .num_parents = 1, 1520 .flags = CLK_SET_RATE_PARENT, 1521 .ops = &clk_branch2_ops, 1522 }, 1523 }, 1524 }; 1525 1526 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1527 .halt_reg = 0x302c, 1528 .halt_check = BRANCH_HALT, 1529 .clkr = { 1530 .enable_reg = 0x302c, 1531 .enable_mask = BIT(0), 1532 .hw.init = &(struct clk_init_data){ 1533 .name = "gcc_blsp1_uart2_apps_clk", 1534 .parent_names = (const char *[]){ 1535 "blsp1_uart2_apps_clk_src", 1536 }, 1537 .num_parents = 1, 1538 .flags = CLK_SET_RATE_PARENT, 1539 .ops = &clk_branch2_ops, 1540 }, 1541 }, 1542 }; 1543 1544 static struct clk_branch gcc_blsp1_uart3_apps_clk = { 1545 .halt_reg = 0x400c, 1546 .halt_check = BRANCH_HALT, 1547 .clkr = { 1548 .enable_reg = 0x400c, 1549 .enable_mask = BIT(0), 1550 .hw.init = &(struct clk_init_data){ 1551 .name = "gcc_blsp1_uart3_apps_clk", 1552 .parent_names = (const char *[]){ 1553 "blsp1_uart3_apps_clk_src", 1554 }, 1555 .num_parents = 1, 1556 .flags = CLK_SET_RATE_PARENT, 1557 .ops = &clk_branch2_ops, 1558 }, 1559 }, 1560 }; 1561 1562 static struct clk_branch gcc_blsp2_ahb_clk = { 1563 .halt_reg = 0xb008, 1564 .halt_check = BRANCH_HALT_VOTED, 1565 .clkr = { 1566 .enable_reg = 0x45004, 1567 .enable_mask = BIT(20), 1568 .hw.init = &(struct clk_init_data){ 1569 .name = "gcc_blsp2_ahb_clk", 1570 .ops = &clk_branch2_ops, 1571 }, 1572 }, 1573 }; 1574 1575 static struct clk_branch gcc_blsp2_qup0_i2c_apps_clk = { 1576 .halt_reg = 0xc008, 1577 .halt_check = BRANCH_HALT, 1578 .clkr = { 1579 .enable_reg = 0xc008, 1580 .enable_mask = BIT(0), 1581 .hw.init = &(struct clk_init_data){ 1582 .name = "gcc_blsp2_qup0_i2c_apps_clk", 1583 .parent_names = (const char *[]){ 1584 "blsp2_qup0_i2c_apps_clk_src", 1585 }, 1586 .num_parents = 1, 1587 .flags = CLK_SET_RATE_PARENT, 1588 .ops = &clk_branch2_ops, 1589 }, 1590 }, 1591 }; 1592 1593 static struct clk_branch gcc_blsp2_qup0_spi_apps_clk = { 1594 .halt_reg = 0xc004, 1595 .halt_check = BRANCH_HALT, 1596 .clkr = { 1597 .enable_reg = 0xc004, 1598 .enable_mask = BIT(0), 1599 .hw.init = &(struct clk_init_data){ 1600 .name = "gcc_blsp2_qup0_spi_apps_clk", 1601 .parent_names = (const char *[]){ 1602 "blsp2_qup0_spi_apps_clk_src", 1603 }, 1604 .num_parents = 1, 1605 .flags = CLK_SET_RATE_PARENT, 1606 .ops = &clk_branch2_ops, 1607 }, 1608 }, 1609 }; 1610 1611 static struct clk_branch gcc_blsp2_uart0_apps_clk = { 1612 .halt_reg = 0xc03c, 1613 .halt_check = BRANCH_HALT, 1614 .clkr = { 1615 .enable_reg = 0xc03c, 1616 .enable_mask = BIT(0), 1617 .hw.init = &(struct clk_init_data){ 1618 .name = "gcc_blsp2_uart0_apps_clk", 1619 .parent_names = (const char *[]){ 1620 "blsp2_uart0_apps_clk_src", 1621 }, 1622 .num_parents = 1, 1623 .flags = CLK_SET_RATE_PARENT, 1624 .ops = &clk_branch2_ops, 1625 }, 1626 }, 1627 }; 1628 1629 static struct clk_branch gcc_boot_rom_ahb_clk = { 1630 .halt_reg = 0x1300c, 1631 .halt_check = BRANCH_HALT_VOTED, 1632 .clkr = { 1633 .enable_reg = 0x45004, 1634 .enable_mask = BIT(7), 1635 .hw.init = &(struct clk_init_data){ 1636 .name = "gcc_boot_rom_ahb_clk", 1637 .ops = &clk_branch2_ops, 1638 }, 1639 }, 1640 }; 1641 1642 static struct clk_branch gcc_crypto_ahb_clk = { 1643 .halt_reg = 0x16024, 1644 .halt_check = BRANCH_VOTED, 1645 .clkr = { 1646 .enable_reg = 0x45004, 1647 .enable_mask = BIT(0), 1648 .hw.init = &(struct clk_init_data){ 1649 .name = "gcc_crypto_ahb_clk", 1650 .ops = &clk_branch2_ops, 1651 }, 1652 }, 1653 }; 1654 1655 static struct clk_branch gcc_crypto_axi_clk = { 1656 .halt_reg = 0x16020, 1657 .halt_check = BRANCH_VOTED, 1658 .clkr = { 1659 .enable_reg = 0x45004, 1660 .enable_mask = BIT(1), 1661 .hw.init = &(struct clk_init_data){ 1662 .name = "gcc_crypto_axi_clk", 1663 .ops = &clk_branch2_ops, 1664 }, 1665 }, 1666 }; 1667 1668 static struct clk_branch gcc_crypto_clk = { 1669 .halt_reg = 0x1601c, 1670 .halt_check = BRANCH_VOTED, 1671 .clkr = { 1672 .enable_reg = 0x45004, 1673 .enable_mask = BIT(2), 1674 .hw.init = &(struct clk_init_data){ 1675 .name = "gcc_crypto_clk", 1676 .ops = &clk_branch2_ops, 1677 }, 1678 }, 1679 }; 1680 1681 static struct clk_branch gcc_eth_axi_clk = { 1682 .halt_reg = 0x4e010, 1683 .halt_check = BRANCH_HALT, 1684 .clkr = { 1685 .enable_reg = 0x4e010, 1686 .enable_mask = BIT(0), 1687 .hw.init = &(struct clk_init_data){ 1688 .name = "gcc_eth_axi_clk", 1689 .ops = &clk_branch2_ops, 1690 }, 1691 }, 1692 }; 1693 1694 static struct clk_branch gcc_eth_ptp_clk = { 1695 .halt_reg = 0x4e004, 1696 .halt_check = BRANCH_HALT, 1697 .clkr = { 1698 .enable_reg = 0x4e004, 1699 .enable_mask = BIT(0), 1700 .hw.init = &(struct clk_init_data){ 1701 .name = "gcc_eth_ptp_clk", 1702 .parent_names = (const char *[]){ 1703 "emac_ptp_clk_src", 1704 }, 1705 .num_parents = 1, 1706 .flags = CLK_SET_RATE_PARENT, 1707 .ops = &clk_branch2_ops, 1708 }, 1709 }, 1710 }; 1711 1712 static struct clk_branch gcc_eth_rgmii_clk = { 1713 .halt_reg = 0x4e008, 1714 .halt_check = BRANCH_HALT, 1715 .clkr = { 1716 .enable_reg = 0x4e008, 1717 .enable_mask = BIT(0), 1718 .hw.init = &(struct clk_init_data){ 1719 .name = "gcc_eth_rgmii_clk", 1720 .parent_names = (const char *[]){ 1721 "emac_clk_src", 1722 }, 1723 .num_parents = 1, 1724 .flags = CLK_SET_RATE_PARENT, 1725 .ops = &clk_branch2_ops, 1726 }, 1727 }, 1728 }; 1729 1730 static struct clk_branch gcc_eth_slave_ahb_clk = { 1731 .halt_reg = 0x4e00c, 1732 .halt_check = BRANCH_HALT, 1733 .clkr = { 1734 .enable_reg = 0x4e00c, 1735 .enable_mask = BIT(0), 1736 .hw.init = &(struct clk_init_data){ 1737 .name = "gcc_eth_slave_ahb_clk", 1738 .ops = &clk_branch2_ops, 1739 }, 1740 }, 1741 }; 1742 1743 static struct clk_branch gcc_geni_ir_s_clk = { 1744 .halt_reg = 0xf008, 1745 .halt_check = BRANCH_HALT, 1746 .clkr = { 1747 .enable_reg = 0xf008, 1748 .enable_mask = BIT(0), 1749 .hw.init = &(struct clk_init_data){ 1750 .name = "gcc_geni_ir_s_clk", 1751 .ops = &clk_branch2_ops, 1752 }, 1753 }, 1754 }; 1755 1756 static struct clk_branch gcc_geni_ir_h_clk = { 1757 .halt_reg = 0xf004, 1758 .halt_check = BRANCH_HALT, 1759 .clkr = { 1760 .enable_reg = 0xf004, 1761 .enable_mask = BIT(0), 1762 .hw.init = &(struct clk_init_data){ 1763 .name = "gcc_geni_ir_h_clk", 1764 .ops = &clk_branch2_ops, 1765 }, 1766 }, 1767 }; 1768 1769 static struct clk_branch gcc_gfx_tcu_clk = { 1770 .halt_reg = 0x12020, 1771 .halt_check = BRANCH_VOTED, 1772 .clkr = { 1773 .enable_reg = 0x4500C, 1774 .enable_mask = BIT(2), 1775 .hw.init = &(struct clk_init_data){ 1776 .name = "gcc_gfx_tcu_clk", 1777 .ops = &clk_branch2_ops, 1778 }, 1779 }, 1780 }; 1781 1782 static struct clk_branch gcc_gfx_tbu_clk = { 1783 .halt_reg = 0x12010, 1784 .halt_check = BRANCH_VOTED, 1785 .clkr = { 1786 .enable_reg = 0x4500C, 1787 .enable_mask = BIT(3), 1788 .hw.init = &(struct clk_init_data){ 1789 .name = "gcc_gfx_tbu_clk", 1790 .ops = &clk_branch2_ops, 1791 }, 1792 }, 1793 }; 1794 1795 static struct clk_branch gcc_gp1_clk = { 1796 .halt_reg = 0x8000, 1797 .halt_check = BRANCH_HALT, 1798 .clkr = { 1799 .enable_reg = 0x8000, 1800 .enable_mask = BIT(0), 1801 .hw.init = &(struct clk_init_data){ 1802 .name = "gcc_gp1_clk", 1803 .parent_names = (const char *[]){ 1804 "gp1_clk_src", 1805 }, 1806 .num_parents = 1, 1807 .flags = CLK_SET_RATE_PARENT, 1808 .ops = &clk_branch2_ops, 1809 }, 1810 }, 1811 }; 1812 1813 static struct clk_branch gcc_gp2_clk = { 1814 .halt_reg = 0x9000, 1815 .halt_check = BRANCH_HALT, 1816 .clkr = { 1817 .enable_reg = 0x9000, 1818 .enable_mask = BIT(0), 1819 .hw.init = &(struct clk_init_data){ 1820 .name = "gcc_gp2_clk", 1821 .parent_names = (const char *[]){ 1822 "gp2_clk_src", 1823 }, 1824 .num_parents = 1, 1825 .flags = CLK_SET_RATE_PARENT, 1826 .ops = &clk_branch2_ops, 1827 }, 1828 }, 1829 }; 1830 1831 static struct clk_branch gcc_gp3_clk = { 1832 .halt_reg = 0xa000, 1833 .halt_check = BRANCH_HALT, 1834 .clkr = { 1835 .enable_reg = 0xa000, 1836 .enable_mask = BIT(0), 1837 .hw.init = &(struct clk_init_data){ 1838 .name = "gcc_gp3_clk", 1839 .parent_names = (const char *[]){ 1840 "gp3_clk_src", 1841 }, 1842 .num_parents = 1, 1843 .flags = CLK_SET_RATE_PARENT, 1844 .ops = &clk_branch2_ops, 1845 }, 1846 }, 1847 }; 1848 1849 static struct clk_branch gcc_gtcu_ahb_clk = { 1850 .halt_reg = 0x12044, 1851 .halt_check = BRANCH_VOTED, 1852 .clkr = { 1853 .enable_reg = 0x4500c, 1854 .enable_mask = BIT(13), 1855 .hw.init = &(struct clk_init_data){ 1856 .name = "gcc_gtcu_ahb_clk", 1857 .ops = &clk_branch2_ops, 1858 }, 1859 }, 1860 }; 1861 1862 static struct clk_branch gcc_mdp_tbu_clk = { 1863 .halt_reg = 0x1201c, 1864 .halt_check = BRANCH_VOTED, 1865 .clkr = { 1866 .enable_reg = 0x4500c, 1867 .enable_mask = BIT(4), 1868 .hw.init = &(struct clk_init_data){ 1869 .name = "gcc_mdp_tbu_clk", 1870 .ops = &clk_branch2_ops, 1871 }, 1872 }, 1873 }; 1874 1875 static struct clk_branch gcc_mdss_ahb_clk = { 1876 .halt_reg = 0x4d07c, 1877 .halt_check = BRANCH_HALT, 1878 .clkr = { 1879 .enable_reg = 0x4d07c, 1880 .enable_mask = BIT(0), 1881 .hw.init = &(struct clk_init_data){ 1882 .name = "gcc_mdss_ahb_clk", 1883 .ops = &clk_branch2_ops, 1884 }, 1885 }, 1886 }; 1887 1888 static struct clk_branch gcc_mdss_axi_clk = { 1889 .halt_reg = 0x4d080, 1890 .halt_check = BRANCH_HALT, 1891 .clkr = { 1892 .enable_reg = 0x4d080, 1893 .enable_mask = BIT(0), 1894 .hw.init = &(struct clk_init_data){ 1895 .name = "gcc_mdss_axi_clk", 1896 .ops = &clk_branch2_ops, 1897 }, 1898 }, 1899 }; 1900 1901 static struct clk_branch gcc_mdss_byte0_clk = { 1902 .halt_reg = 0x4d094, 1903 .halt_check = BRANCH_HALT, 1904 .clkr = { 1905 .enable_reg = 0x4d094, 1906 .enable_mask = BIT(0), 1907 .hw.init = &(struct clk_init_data){ 1908 .name = "gcc_mdss_byte0_clk", 1909 .parent_names = (const char *[]){ 1910 "byte0_clk_src", 1911 }, 1912 .num_parents = 1, 1913 .flags = CLK_SET_RATE_PARENT, 1914 .ops = &clk_branch2_ops, 1915 }, 1916 }, 1917 }; 1918 1919 static struct clk_branch gcc_mdss_esc0_clk = { 1920 .halt_reg = 0x4d098, 1921 .halt_check = BRANCH_HALT, 1922 .clkr = { 1923 .enable_reg = 0x4d098, 1924 .enable_mask = BIT(0), 1925 .hw.init = &(struct clk_init_data){ 1926 .name = "gcc_mdss_esc0_clk", 1927 .parent_names = (const char *[]){ 1928 "esc0_clk_src", 1929 }, 1930 .num_parents = 1, 1931 .flags = CLK_SET_RATE_PARENT, 1932 .ops = &clk_branch2_ops, 1933 }, 1934 }, 1935 }; 1936 1937 static struct clk_branch gcc_mdss_hdmi_app_clk = { 1938 .halt_reg = 0x4d0d8, 1939 .halt_check = BRANCH_HALT, 1940 .clkr = { 1941 .enable_reg = 0x4d0d8, 1942 .enable_mask = BIT(0), 1943 .hw.init = &(struct clk_init_data){ 1944 .name = "gcc_mdss_hdmi_app_clk", 1945 .parent_names = (const char *[]){ 1946 "hdmi_app_clk_src", 1947 }, 1948 .num_parents = 1, 1949 .flags = CLK_SET_RATE_PARENT, 1950 .ops = &clk_branch2_ops, 1951 }, 1952 }, 1953 }; 1954 1955 static struct clk_branch gcc_mdss_hdmi_pclk_clk = { 1956 .halt_reg = 0x4d0d4, 1957 .halt_check = BRANCH_HALT, 1958 .clkr = { 1959 .enable_reg = 0x4d0d4, 1960 .enable_mask = BIT(0), 1961 .hw.init = &(struct clk_init_data){ 1962 .name = "gcc_mdss_hdmi_pclk_clk", 1963 .parent_names = (const char *[]){ 1964 "hdmi_pclk_clk_src", 1965 }, 1966 .num_parents = 1, 1967 .flags = CLK_SET_RATE_PARENT, 1968 .ops = &clk_branch2_ops, 1969 }, 1970 }, 1971 }; 1972 1973 static struct clk_branch gcc_mdss_mdp_clk = { 1974 .halt_reg = 0x4d088, 1975 .halt_check = BRANCH_HALT, 1976 .clkr = { 1977 .enable_reg = 0x4d088, 1978 .enable_mask = BIT(0), 1979 .hw.init = &(struct clk_init_data){ 1980 .name = "gcc_mdss_mdp_clk", 1981 .parent_names = (const char *[]){ 1982 "mdp_clk_src", 1983 }, 1984 .num_parents = 1, 1985 .flags = CLK_SET_RATE_PARENT, 1986 .ops = &clk_branch2_ops, 1987 }, 1988 }, 1989 }; 1990 1991 static struct clk_branch gcc_mdss_pclk0_clk = { 1992 .halt_reg = 0x4d084, 1993 .halt_check = BRANCH_HALT, 1994 .clkr = { 1995 .enable_reg = 0x4d084, 1996 .enable_mask = BIT(0), 1997 .hw.init = &(struct clk_init_data){ 1998 .name = "gcc_mdss_pclk0_clk", 1999 .parent_names = (const char *[]){ 2000 "pclk0_clk_src", 2001 }, 2002 .num_parents = 1, 2003 .flags = CLK_SET_RATE_PARENT, 2004 .ops = &clk_branch2_ops, 2005 }, 2006 }, 2007 }; 2008 2009 static struct clk_branch gcc_mdss_vsync_clk = { 2010 .halt_reg = 0x4d090, 2011 .halt_check = BRANCH_HALT, 2012 .clkr = { 2013 .enable_reg = 0x4d090, 2014 .enable_mask = BIT(0), 2015 .hw.init = &(struct clk_init_data){ 2016 .name = "gcc_mdss_vsync_clk", 2017 .parent_names = (const char *[]){ 2018 "vsync_clk_src", 2019 }, 2020 .num_parents = 1, 2021 .flags = CLK_SET_RATE_PARENT, 2022 .ops = &clk_branch2_ops, 2023 }, 2024 }, 2025 }; 2026 2027 static struct clk_branch gcc_oxili_ahb_clk = { 2028 .halt_reg = 0x59028, 2029 .halt_check = BRANCH_HALT, 2030 .clkr = { 2031 .enable_reg = 0x59028, 2032 .enable_mask = BIT(0), 2033 .hw.init = &(struct clk_init_data){ 2034 .name = "gcc_oxili_ahb_clk", 2035 .ops = &clk_branch2_ops, 2036 }, 2037 }, 2038 }; 2039 2040 static struct clk_branch gcc_oxili_gfx3d_clk = { 2041 .halt_reg = 0x59020, 2042 .halt_check = BRANCH_HALT, 2043 .clkr = { 2044 .enable_reg = 0x59020, 2045 .enable_mask = BIT(0), 2046 .hw.init = &(struct clk_init_data){ 2047 .name = "gcc_oxili_gfx3d_clk", 2048 .parent_names = (const char *[]){ 2049 "gfx3d_clk_src", 2050 }, 2051 .num_parents = 1, 2052 .flags = CLK_SET_RATE_PARENT, 2053 .ops = &clk_branch2_ops, 2054 }, 2055 }, 2056 }; 2057 2058 static struct clk_branch gcc_pcie_0_aux_clk = { 2059 .halt_reg = 0x3e014, 2060 .halt_check = BRANCH_HALT_VOTED, 2061 .clkr = { 2062 .enable_reg = 0x45004, 2063 .enable_mask = BIT(27), 2064 .hw.init = &(struct clk_init_data){ 2065 .name = "gcc_pcie_0_aux_clk", 2066 .parent_names = (const char *[]){ 2067 "pcie_0_aux_clk_src", 2068 }, 2069 .num_parents = 1, 2070 .flags = CLK_SET_RATE_PARENT, 2071 .ops = &clk_branch2_ops, 2072 }, 2073 }, 2074 }; 2075 2076 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 2077 .halt_reg = 0x3e008, 2078 .halt_check = BRANCH_HALT_VOTED, 2079 .clkr = { 2080 .enable_reg = 0x45004, 2081 .enable_mask = BIT(11), 2082 .hw.init = &(struct clk_init_data){ 2083 .name = "gcc_pcie_0_cfg_ahb_clk", 2084 .ops = &clk_branch2_ops, 2085 }, 2086 }, 2087 }; 2088 2089 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 2090 .halt_reg = 0x3e018, 2091 .halt_check = BRANCH_HALT_VOTED, 2092 .clkr = { 2093 .enable_reg = 0x45004, 2094 .enable_mask = BIT(18), 2095 .hw.init = &(struct clk_init_data){ 2096 .name = "gcc_pcie_0_mstr_axi_clk", 2097 .ops = &clk_branch2_ops, 2098 }, 2099 }, 2100 }; 2101 2102 static struct clk_branch gcc_pcie_0_pipe_clk = { 2103 .halt_reg = 0x3e00c, 2104 .halt_check = BRANCH_HALT_VOTED, 2105 .clkr = { 2106 .enable_reg = 0x45004, 2107 .enable_mask = BIT(28), 2108 .hw.init = &(struct clk_init_data){ 2109 .name = "gcc_pcie_0_pipe_clk", 2110 .parent_names = (const char *[]){ 2111 "pcie_0_pipe_clk_src", 2112 }, 2113 .num_parents = 1, 2114 .flags = CLK_SET_RATE_PARENT, 2115 .ops = &clk_branch2_ops, 2116 }, 2117 }, 2118 }; 2119 2120 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 2121 .halt_reg = 0x3e010, 2122 .halt_check = BRANCH_HALT_VOTED, 2123 .clkr = { 2124 .enable_reg = 0x45004, 2125 .enable_mask = BIT(22), 2126 .hw.init = &(struct clk_init_data){ 2127 .name = "gcc_pcie_0_slv_axi_clk", 2128 .ops = &clk_branch2_ops, 2129 }, 2130 }, 2131 }; 2132 2133 static struct clk_branch gcc_pcnoc_usb2_clk = { 2134 .halt_reg = 0x27008, 2135 .halt_check = BRANCH_HALT, 2136 .clkr = { 2137 .enable_reg = 0x27008, 2138 .enable_mask = BIT(0), 2139 .hw.init = &(struct clk_init_data){ 2140 .name = "gcc_pcnoc_usb2_clk", 2141 .flags = CLK_IS_CRITICAL, 2142 .ops = &clk_branch2_ops, 2143 }, 2144 }, 2145 }; 2146 2147 static struct clk_branch gcc_pcnoc_usb3_clk = { 2148 .halt_reg = 0x2700c, 2149 .halt_check = BRANCH_HALT, 2150 .clkr = { 2151 .enable_reg = 0x2700c, 2152 .enable_mask = BIT(0), 2153 .hw.init = &(struct clk_init_data){ 2154 .name = "gcc_pcnoc_usb3_clk", 2155 .flags = CLK_IS_CRITICAL, 2156 .ops = &clk_branch2_ops, 2157 }, 2158 }, 2159 }; 2160 2161 static struct clk_branch gcc_pdm2_clk = { 2162 .halt_reg = 0x4400c, 2163 .halt_check = BRANCH_HALT, 2164 .clkr = { 2165 .enable_reg = 0x4400c, 2166 .enable_mask = BIT(0), 2167 .hw.init = &(struct clk_init_data){ 2168 .name = "gcc_pdm2_clk", 2169 .parent_names = (const char *[]){ 2170 "pdm2_clk_src", 2171 }, 2172 .num_parents = 1, 2173 .flags = CLK_SET_RATE_PARENT, 2174 .ops = &clk_branch2_ops, 2175 }, 2176 }, 2177 }; 2178 2179 static struct clk_branch gcc_pdm_ahb_clk = { 2180 .halt_reg = 0x44004, 2181 .halt_check = BRANCH_HALT, 2182 .clkr = { 2183 .enable_reg = 0x44004, 2184 .enable_mask = BIT(0), 2185 .hw.init = &(struct clk_init_data){ 2186 .name = "gcc_pdm_ahb_clk", 2187 .ops = &clk_branch2_ops, 2188 }, 2189 }, 2190 }; 2191 2192 static struct clk_branch gcc_prng_ahb_clk = { 2193 .halt_reg = 0x13004, 2194 .halt_check = BRANCH_HALT_VOTED, 2195 .clkr = { 2196 .enable_reg = 0x45004, 2197 .enable_mask = BIT(8), 2198 .hw.init = &(struct clk_init_data){ 2199 .name = "gcc_prng_ahb_clk", 2200 .ops = &clk_branch2_ops, 2201 }, 2202 }, 2203 }; 2204 2205 /* PWM clks do not have XO as parent as src clk is a balance root */ 2206 static struct clk_branch gcc_pwm0_xo512_clk = { 2207 .halt_reg = 0x44018, 2208 .halt_check = BRANCH_HALT, 2209 .clkr = { 2210 .enable_reg = 0x44018, 2211 .enable_mask = BIT(0), 2212 .hw.init = &(struct clk_init_data){ 2213 .name = "gcc_pwm0_xo512_clk", 2214 .ops = &clk_branch2_ops, 2215 }, 2216 }, 2217 }; 2218 2219 static struct clk_branch gcc_pwm1_xo512_clk = { 2220 .halt_reg = 0x49004, 2221 .halt_check = BRANCH_HALT, 2222 .clkr = { 2223 .enable_reg = 0x49004, 2224 .enable_mask = BIT(0), 2225 .hw.init = &(struct clk_init_data){ 2226 .name = "gcc_pwm1_xo512_clk", 2227 .ops = &clk_branch2_ops, 2228 }, 2229 }, 2230 }; 2231 2232 static struct clk_branch gcc_pwm2_xo512_clk = { 2233 .halt_reg = 0x4a004, 2234 .halt_check = BRANCH_HALT, 2235 .clkr = { 2236 .enable_reg = 0x4a004, 2237 .enable_mask = BIT(0), 2238 .hw.init = &(struct clk_init_data){ 2239 .name = "gcc_pwm2_xo512_clk", 2240 .ops = &clk_branch2_ops, 2241 }, 2242 }, 2243 }; 2244 2245 static struct clk_branch gcc_qdss_dap_clk = { 2246 .halt_reg = 0x29084, 2247 .halt_check = BRANCH_VOTED, 2248 .clkr = { 2249 .enable_reg = 0x45004, 2250 .enable_mask = BIT(21), 2251 .hw.init = &(struct clk_init_data){ 2252 .name = "gcc_qdss_dap_clk", 2253 .ops = &clk_branch2_ops, 2254 }, 2255 }, 2256 }; 2257 2258 static struct clk_branch gcc_sdcc1_ahb_clk = { 2259 .halt_reg = 0x4201c, 2260 .halt_check = BRANCH_HALT, 2261 .clkr = { 2262 .enable_reg = 0x4201c, 2263 .enable_mask = BIT(0), 2264 .hw.init = &(struct clk_init_data){ 2265 .name = "gcc_sdcc1_ahb_clk", 2266 .ops = &clk_branch2_ops, 2267 }, 2268 }, 2269 }; 2270 2271 static struct clk_branch gcc_sdcc1_apps_clk = { 2272 .halt_reg = 0x42018, 2273 .halt_check = BRANCH_HALT, 2274 .clkr = { 2275 .enable_reg = 0x42018, 2276 .enable_mask = BIT(0), 2277 .hw.init = &(struct clk_init_data){ 2278 .name = "gcc_sdcc1_apps_clk", 2279 .parent_names = (const char *[]){ 2280 "sdcc1_apps_clk_src", 2281 }, 2282 .num_parents = 1, 2283 .flags = CLK_SET_RATE_PARENT, 2284 .ops = &clk_branch2_ops, 2285 }, 2286 }, 2287 }; 2288 2289 static struct clk_branch gcc_sdcc1_ice_core_clk = { 2290 .halt_reg = 0x5d014, 2291 .halt_check = BRANCH_HALT, 2292 .clkr = { 2293 .enable_reg = 0x5d014, 2294 .enable_mask = BIT(0), 2295 .hw.init = &(struct clk_init_data){ 2296 .name = "gcc_sdcc1_ice_core_clk", 2297 .parent_names = (const char *[]){ 2298 "sdcc1_ice_core_clk_src", 2299 }, 2300 .num_parents = 1, 2301 .flags = CLK_SET_RATE_PARENT, 2302 .ops = &clk_branch2_ops, 2303 }, 2304 }, 2305 }; 2306 2307 static struct clk_branch gcc_sdcc2_ahb_clk = { 2308 .halt_reg = 0x4301c, 2309 .halt_check = BRANCH_HALT, 2310 .clkr = { 2311 .enable_reg = 0x4301c, 2312 .enable_mask = BIT(0), 2313 .hw.init = &(struct clk_init_data){ 2314 .name = "gcc_sdcc2_ahb_clk", 2315 .ops = &clk_branch2_ops, 2316 }, 2317 }, 2318 }; 2319 2320 static struct clk_branch gcc_sdcc2_apps_clk = { 2321 .halt_reg = 0x43018, 2322 .halt_check = BRANCH_HALT, 2323 .clkr = { 2324 .enable_reg = 0x43018, 2325 .enable_mask = BIT(0), 2326 .hw.init = &(struct clk_init_data){ 2327 .name = "gcc_sdcc2_apps_clk", 2328 .parent_names = (const char *[]){ 2329 "sdcc2_apps_clk_src", 2330 }, 2331 .num_parents = 1, 2332 .flags = CLK_SET_RATE_PARENT, 2333 .ops = &clk_branch2_ops, 2334 }, 2335 }, 2336 }; 2337 2338 static struct clk_branch gcc_smmu_cfg_clk = { 2339 .halt_reg = 0x12038, 2340 .halt_check = BRANCH_VOTED, 2341 .clkr = { 2342 .enable_reg = 0x3600C, 2343 .enable_mask = BIT(12), 2344 .hw.init = &(struct clk_init_data){ 2345 .name = "gcc_smmu_cfg_clk", 2346 .ops = &clk_branch2_ops, 2347 }, 2348 }, 2349 }; 2350 2351 static struct clk_branch gcc_sys_noc_usb3_clk = { 2352 .halt_reg = 0x26014, 2353 .halt_check = BRANCH_HALT, 2354 .clkr = { 2355 .enable_reg = 0x26014, 2356 .enable_mask = BIT(0), 2357 .hw.init = &(struct clk_init_data){ 2358 .name = "gcc_sys_noc_usb3_clk", 2359 .parent_names = (const char *[]){ 2360 "usb30_master_clk_src", 2361 }, 2362 .num_parents = 1, 2363 .ops = &clk_branch2_ops, 2364 }, 2365 }, 2366 }; 2367 2368 static struct clk_branch gcc_usb_hs_inactivity_timers_clk = { 2369 .halt_reg = 0x4100C, 2370 .halt_check = BRANCH_HALT, 2371 .clkr = { 2372 .enable_reg = 0x4100C, 2373 .enable_mask = BIT(0), 2374 .hw.init = &(struct clk_init_data){ 2375 .name = "gcc_usb_hs_inactivity_timers_clk", 2376 .ops = &clk_branch2_ops, 2377 }, 2378 }, 2379 }; 2380 2381 static struct clk_branch gcc_usb20_mock_utmi_clk = { 2382 .halt_reg = 0x41044, 2383 .halt_check = BRANCH_HALT, 2384 .clkr = { 2385 .enable_reg = 0x41044, 2386 .enable_mask = BIT(0), 2387 .hw.init = &(struct clk_init_data){ 2388 .name = "gcc_usb20_mock_utmi_clk", 2389 .parent_names = (const char *[]){ 2390 "usb20_mock_utmi_clk_src", 2391 }, 2392 .num_parents = 1, 2393 .flags = CLK_SET_RATE_PARENT, 2394 .ops = &clk_branch2_ops, 2395 }, 2396 }, 2397 }; 2398 2399 static struct clk_branch gcc_usb2a_phy_sleep_clk = { 2400 .halt_reg = 0x4102c, 2401 .halt_check = BRANCH_HALT, 2402 .clkr = { 2403 .enable_reg = 0x4102c, 2404 .enable_mask = BIT(0), 2405 .hw.init = &(struct clk_init_data){ 2406 .name = "gcc_usb2a_phy_sleep_clk", 2407 .ops = &clk_branch2_ops, 2408 }, 2409 }, 2410 }; 2411 2412 static struct clk_branch gcc_usb30_master_clk = { 2413 .halt_reg = 0x3900c, 2414 .halt_check = BRANCH_HALT, 2415 .clkr = { 2416 .enable_reg = 0x3900c, 2417 .enable_mask = BIT(0), 2418 .hw.init = &(struct clk_init_data){ 2419 .name = "gcc_usb30_master_clk", 2420 .parent_names = (const char *[]){ 2421 "usb30_master_clk_src", 2422 }, 2423 .num_parents = 1, 2424 .flags = CLK_SET_RATE_PARENT, 2425 .ops = &clk_branch2_ops, 2426 }, 2427 }, 2428 }; 2429 2430 static struct clk_branch gcc_usb30_mock_utmi_clk = { 2431 .halt_reg = 0x39014, 2432 .halt_check = BRANCH_HALT, 2433 .clkr = { 2434 .enable_reg = 0x39014, 2435 .enable_mask = BIT(0), 2436 .hw.init = &(struct clk_init_data){ 2437 .name = "gcc_usb30_mock_utmi_clk", 2438 .parent_names = (const char *[]){ 2439 "usb30_mock_utmi_clk_src", 2440 }, 2441 .num_parents = 1, 2442 .flags = CLK_SET_RATE_PARENT, 2443 .ops = &clk_branch2_ops, 2444 }, 2445 }, 2446 }; 2447 2448 static struct clk_branch gcc_usb30_sleep_clk = { 2449 .halt_reg = 0x39010, 2450 .halt_check = BRANCH_HALT, 2451 .clkr = { 2452 .enable_reg = 0x39010, 2453 .enable_mask = BIT(0), 2454 .hw.init = &(struct clk_init_data){ 2455 .name = "gcc_usb30_sleep_clk", 2456 .ops = &clk_branch2_ops, 2457 }, 2458 }, 2459 }; 2460 2461 static struct clk_branch gcc_usb3_phy_aux_clk = { 2462 .halt_reg = 0x39044, 2463 .halt_check = BRANCH_HALT, 2464 .clkr = { 2465 .enable_reg = 0x39044, 2466 .enable_mask = BIT(0), 2467 .hw.init = &(struct clk_init_data){ 2468 .name = "gcc_usb3_phy_aux_clk", 2469 .parent_names = (const char *[]){ 2470 "usb3_phy_aux_clk_src", 2471 }, 2472 .num_parents = 1, 2473 .flags = CLK_SET_RATE_PARENT, 2474 .ops = &clk_branch2_ops, 2475 }, 2476 }, 2477 }; 2478 2479 static struct clk_branch gcc_usb3_phy_pipe_clk = { 2480 .halt_check = BRANCH_HALT_SKIP, 2481 .clkr = { 2482 .enable_reg = 0x39018, 2483 .enable_mask = BIT(0), 2484 .hw.init = &(struct clk_init_data){ 2485 .name = "gcc_usb3_phy_pipe_clk", 2486 .ops = &clk_branch2_ops, 2487 }, 2488 }, 2489 }; 2490 2491 static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = { 2492 .halt_reg = 0x41030, 2493 .halt_check = BRANCH_HALT, 2494 .clkr = { 2495 .enable_reg = 0x41030, 2496 .enable_mask = BIT(0), 2497 .hw.init = &(struct clk_init_data){ 2498 .name = "gcc_usb_hs_phy_cfg_ahb_clk", 2499 .ops = &clk_branch2_ops, 2500 }, 2501 }, 2502 }; 2503 2504 static struct clk_branch gcc_usb_hs_system_clk = { 2505 .halt_reg = 0x41004, 2506 .halt_check = BRANCH_HALT, 2507 .clkr = { 2508 .enable_reg = 0x41004, 2509 .enable_mask = BIT(0), 2510 .hw.init = &(struct clk_init_data){ 2511 .name = "gcc_usb_hs_system_clk", 2512 .parent_names = (const char *[]){ 2513 "usb_hs_system_clk_src", 2514 }, 2515 .num_parents = 1, 2516 .flags = CLK_SET_RATE_PARENT, 2517 .ops = &clk_branch2_ops, 2518 }, 2519 }, 2520 }; 2521 2522 static struct clk_hw *gcc_qcs404_hws[] = { 2523 &cxo.hw, 2524 }; 2525 2526 static struct clk_regmap *gcc_qcs404_clocks[] = { 2527 [GCC_APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr, 2528 [GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC] = &blsp1_qup0_i2c_apps_clk_src.clkr, 2529 [GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC] = &blsp1_qup0_spi_apps_clk_src.clkr, 2530 [GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2531 [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2532 [GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2533 [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2534 [GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2535 [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2536 [GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2537 [GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2538 [GCC_BLSP1_UART0_APPS_CLK_SRC] = &blsp1_uart0_apps_clk_src.clkr, 2539 [GCC_BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2540 [GCC_BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2541 [GCC_BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 2542 [GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC] = &blsp2_qup0_i2c_apps_clk_src.clkr, 2543 [GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC] = &blsp2_qup0_spi_apps_clk_src.clkr, 2544 [GCC_BLSP2_UART0_APPS_CLK_SRC] = &blsp2_uart0_apps_clk_src.clkr, 2545 [GCC_BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 2546 [GCC_EMAC_CLK_SRC] = &emac_clk_src.clkr, 2547 [GCC_EMAC_PTP_CLK_SRC] = &emac_ptp_clk_src.clkr, 2548 [GCC_ESC0_CLK_SRC] = &esc0_clk_src.clkr, 2549 [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr, 2550 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, 2551 [GCC_BIMC_MDSS_CLK] = &gcc_bimc_mdss_clk.clkr, 2552 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2553 [GCC_BLSP1_QUP0_I2C_APPS_CLK] = &gcc_blsp1_qup0_i2c_apps_clk.clkr, 2554 [GCC_BLSP1_QUP0_SPI_APPS_CLK] = &gcc_blsp1_qup0_spi_apps_clk.clkr, 2555 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2556 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2557 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2558 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2559 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2560 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2561 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 2562 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 2563 [GCC_BLSP1_UART0_APPS_CLK] = &gcc_blsp1_uart0_apps_clk.clkr, 2564 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2565 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2566 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 2567 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, 2568 [GCC_BLSP2_QUP0_I2C_APPS_CLK] = &gcc_blsp2_qup0_i2c_apps_clk.clkr, 2569 [GCC_BLSP2_QUP0_SPI_APPS_CLK] = &gcc_blsp2_qup0_spi_apps_clk.clkr, 2570 [GCC_BLSP2_UART0_APPS_CLK] = &gcc_blsp2_uart0_apps_clk.clkr, 2571 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2572 [GCC_ETH_AXI_CLK] = &gcc_eth_axi_clk.clkr, 2573 [GCC_ETH_PTP_CLK] = &gcc_eth_ptp_clk.clkr, 2574 [GCC_ETH_RGMII_CLK] = &gcc_eth_rgmii_clk.clkr, 2575 [GCC_ETH_SLAVE_AHB_CLK] = &gcc_eth_slave_ahb_clk.clkr, 2576 [GCC_GENI_IR_S_CLK] = &gcc_geni_ir_s_clk.clkr, 2577 [GCC_GENI_IR_H_CLK] = &gcc_geni_ir_h_clk.clkr, 2578 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2579 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2580 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2581 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr, 2582 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr, 2583 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr, 2584 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr, 2585 [GCC_MDSS_HDMI_APP_CLK] = &gcc_mdss_hdmi_app_clk.clkr, 2586 [GCC_MDSS_HDMI_PCLK_CLK] = &gcc_mdss_hdmi_pclk_clk.clkr, 2587 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr, 2588 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr, 2589 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr, 2590 [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr, 2591 [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr, 2592 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2593 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2594 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2595 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2596 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2597 [GCC_PCNOC_USB2_CLK] = &gcc_pcnoc_usb2_clk.clkr, 2598 [GCC_PCNOC_USB3_CLK] = &gcc_pcnoc_usb3_clk.clkr, 2599 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2600 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2601 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2602 [GCC_PWM0_XO512_CLK] = &gcc_pwm0_xo512_clk.clkr, 2603 [GCC_PWM1_XO512_CLK] = &gcc_pwm1_xo512_clk.clkr, 2604 [GCC_PWM2_XO512_CLK] = &gcc_pwm2_xo512_clk.clkr, 2605 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2606 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2607 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 2608 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2609 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2610 [GCC_SYS_NOC_USB3_CLK] = &gcc_sys_noc_usb3_clk.clkr, 2611 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr, 2612 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, 2613 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, 2614 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 2615 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 2616 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, 2617 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, 2618 [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr, 2619 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 2620 [GCC_GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, 2621 [GCC_GP1_CLK_SRC] = &gp1_clk_src.clkr, 2622 [GCC_GP2_CLK_SRC] = &gp2_clk_src.clkr, 2623 [GCC_GP3_CLK_SRC] = &gp3_clk_src.clkr, 2624 [GCC_GPLL0_OUT_MAIN] = &gpll0_out_main.clkr, 2625 [GCC_GPLL0_AO_OUT_MAIN] = &gpll0_ao_out_main.clkr, 2626 [GCC_GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr, 2627 [GCC_GPLL1_OUT_MAIN] = &gpll1_out_main.clkr, 2628 [GCC_GPLL3_OUT_MAIN] = &gpll3_out_main.clkr, 2629 [GCC_GPLL4_OUT_MAIN] = &gpll4_out_main.clkr, 2630 [GCC_GPLL6] = &gpll6.clkr, 2631 [GCC_GPLL6_OUT_AUX] = &gpll6_out_aux, 2632 [GCC_HDMI_APP_CLK_SRC] = &hdmi_app_clk_src.clkr, 2633 [GCC_HDMI_PCLK_CLK_SRC] = &hdmi_pclk_clk_src.clkr, 2634 [GCC_MDP_CLK_SRC] = &mdp_clk_src.clkr, 2635 [GCC_PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr, 2636 [GCC_PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr, 2637 [GCC_PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 2638 [GCC_PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 2639 [GCC_SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 2640 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr, 2641 [GCC_SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 2642 [GCC_USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr, 2643 [GCC_USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, 2644 [GCC_USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 2645 [GCC_USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, 2646 [GCC_USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 2647 [GCC_VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 2648 [GCC_USB_HS_INACTIVITY_TIMERS_CLK] = 2649 &gcc_usb_hs_inactivity_timers_clk.clkr, 2650 [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr, 2651 [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr, 2652 [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr, 2653 [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr, 2654 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr, 2655 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr, 2656 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, 2657 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, 2658 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, 2659 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr, 2660 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, 2661 [GCC_DCC_CLK] = &gcc_dcc_clk.clkr, 2662 [GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr, 2663 }; 2664 2665 static const struct qcom_reset_map gcc_qcs404_resets[] = { 2666 [GCC_GENI_IR_BCR] = { 0x0F000 }, 2667 [GCC_USB_HS_BCR] = { 0x41000 }, 2668 [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 }, 2669 [GCC_QUSB2_PHY_BCR] = { 0x4103c }, 2670 [GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 }, 2671 [GCC_USB2A_PHY_BCR] = { 0x0000c, 0 }, 2672 [GCC_USB3_PHY_BCR] = { 0x39004 }, 2673 [GCC_USB_30_BCR] = { 0x39000 }, 2674 [GCC_USB3PHY_PHY_BCR] = { 0x39008 }, 2675 [GCC_PCIE_0_BCR] = { 0x3e000 }, 2676 [GCC_PCIE_0_PHY_BCR] = { 0x3e004 }, 2677 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 }, 2678 [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c }, 2679 [GCC_EMAC_BCR] = { 0x4e000 }, 2680 }; 2681 2682 static const struct regmap_config gcc_qcs404_regmap_config = { 2683 .reg_bits = 32, 2684 .reg_stride = 4, 2685 .val_bits = 32, 2686 .max_register = 0x7f000, 2687 .fast_io = true, 2688 }; 2689 2690 static const struct qcom_cc_desc gcc_qcs404_desc = { 2691 .config = &gcc_qcs404_regmap_config, 2692 .clks = gcc_qcs404_clocks, 2693 .num_clks = ARRAY_SIZE(gcc_qcs404_clocks), 2694 .resets = gcc_qcs404_resets, 2695 .num_resets = ARRAY_SIZE(gcc_qcs404_resets), 2696 .clk_hws = gcc_qcs404_hws, 2697 .num_clk_hws = ARRAY_SIZE(gcc_qcs404_hws), 2698 }; 2699 2700 static const struct of_device_id gcc_qcs404_match_table[] = { 2701 { .compatible = "qcom,gcc-qcs404" }, 2702 { } 2703 }; 2704 MODULE_DEVICE_TABLE(of, gcc_qcs404_match_table); 2705 2706 static int gcc_qcs404_probe(struct platform_device *pdev) 2707 { 2708 struct regmap *regmap; 2709 2710 regmap = qcom_cc_map(pdev, &gcc_qcs404_desc); 2711 if (IS_ERR(regmap)) 2712 return PTR_ERR(regmap); 2713 2714 clk_alpha_pll_configure(&gpll3_out_main, regmap, &gpll3_config); 2715 2716 return qcom_cc_really_probe(pdev, &gcc_qcs404_desc, regmap); 2717 } 2718 2719 static struct platform_driver gcc_qcs404_driver = { 2720 .probe = gcc_qcs404_probe, 2721 .driver = { 2722 .name = "gcc-qcs404", 2723 .of_match_table = gcc_qcs404_match_table, 2724 }, 2725 }; 2726 2727 static int __init gcc_qcs404_init(void) 2728 { 2729 return platform_driver_register(&gcc_qcs404_driver); 2730 } 2731 subsys_initcall(gcc_qcs404_init); 2732 2733 static void __exit gcc_qcs404_exit(void) 2734 { 2735 platform_driver_unregister(&gcc_qcs404_driver); 2736 } 2737 module_exit(gcc_qcs404_exit); 2738 2739 MODULE_DESCRIPTION("Qualcomm GCC QCS404 Driver"); 2740 MODULE_LICENSE("GPL v2"); 2741