1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/err.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/clock/qcom,gcc-qcm2290.h> 14 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap-divider.h" 19 #include "common.h" 20 #include "gdsc.h" 21 #include "reset.h" 22 23 enum { 24 P_BI_TCXO, 25 P_GPLL0_OUT_AUX2, 26 P_GPLL0_OUT_EARLY, 27 P_GPLL10_OUT_MAIN, 28 P_GPLL11_OUT_AUX, 29 P_GPLL11_OUT_AUX2, 30 P_GPLL11_OUT_MAIN, 31 P_GPLL3_OUT_EARLY, 32 P_GPLL3_OUT_MAIN, 33 P_GPLL4_OUT_MAIN, 34 P_GPLL5_OUT_MAIN, 35 P_GPLL6_OUT_EARLY, 36 P_GPLL6_OUT_MAIN, 37 P_GPLL7_OUT_MAIN, 38 P_GPLL8_OUT_EARLY, 39 P_GPLL8_OUT_MAIN, 40 P_GPLL9_OUT_EARLY, 41 P_GPLL9_OUT_MAIN, 42 P_SLEEP_CLK, 43 }; 44 45 static const struct pll_vco brammo_vco[] = { 46 { 500000000, 1250000000, 0 }, 47 }; 48 49 static const struct pll_vco default_vco[] = { 50 { 500000000, 1000000000, 2 }, 51 }; 52 53 static const struct pll_vco spark_vco[] = { 54 { 750000000, 1500000000, 1 }, 55 }; 56 57 static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = { 58 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 59 [PLL_OFF_L_VAL] = 0x04, 60 [PLL_OFF_ALPHA_VAL] = 0x08, 61 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 62 [PLL_OFF_TEST_CTL] = 0x10, 63 [PLL_OFF_TEST_CTL_U] = 0x14, 64 [PLL_OFF_USER_CTL] = 0x18, 65 [PLL_OFF_USER_CTL_U] = 0x1C, 66 [PLL_OFF_CONFIG_CTL] = 0x20, 67 [PLL_OFF_STATUS] = 0x24, 68 }, 69 [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 70 [PLL_OFF_L_VAL] = 0x04, 71 [PLL_OFF_ALPHA_VAL] = 0x08, 72 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 73 [PLL_OFF_TEST_CTL] = 0x10, 74 [PLL_OFF_TEST_CTL_U] = 0x14, 75 [PLL_OFF_USER_CTL] = 0x18, 76 [PLL_OFF_CONFIG_CTL] = 0x1C, 77 [PLL_OFF_STATUS] = 0x20, 78 }, 79 }; 80 81 static struct clk_alpha_pll gpll0 = { 82 .offset = 0x0, 83 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 84 .clkr = { 85 .enable_reg = 0x79000, 86 .enable_mask = BIT(0), 87 .hw.init = &(struct clk_init_data){ 88 .name = "gpll0", 89 .parent_data = &(const struct clk_parent_data){ 90 .fw_name = "bi_tcxo", 91 }, 92 .num_parents = 1, 93 .ops = &clk_alpha_pll_ops, 94 }, 95 }, 96 }; 97 98 static const struct clk_div_table post_div_table_gpll0_out_aux2[] = { 99 { 0x1, 2 }, 100 { } 101 }; 102 103 static struct clk_alpha_pll_postdiv gpll0_out_aux2 = { 104 .offset = 0x0, 105 .post_div_shift = 8, 106 .post_div_table = post_div_table_gpll0_out_aux2, 107 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2), 108 .width = 4, 109 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 110 .clkr.hw.init = &(struct clk_init_data){ 111 .name = "gpll0_out_aux2", 112 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 113 .num_parents = 1, 114 .ops = &clk_alpha_pll_postdiv_ro_ops, 115 }, 116 }; 117 118 static struct clk_alpha_pll gpll1 = { 119 .offset = 0x1000, 120 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 121 .clkr = { 122 .enable_reg = 0x79000, 123 .enable_mask = BIT(1), 124 .hw.init = &(struct clk_init_data){ 125 .name = "gpll1", 126 .parent_data = &(const struct clk_parent_data){ 127 .fw_name = "bi_tcxo", 128 }, 129 .num_parents = 1, 130 .ops = &clk_alpha_pll_ops, 131 }, 132 }, 133 }; 134 135 /* 1152MHz configuration */ 136 static const struct alpha_pll_config gpll10_config = { 137 .l = 0x3c, 138 .alpha = 0x0, 139 .vco_val = 0x1 << 20, 140 .vco_mask = GENMASK(21, 20), 141 .main_output_mask = BIT(0), 142 .config_ctl_val = 0x4001055B, 143 .test_ctl_hi1_val = 0x1, 144 }; 145 146 static struct clk_alpha_pll gpll10 = { 147 .offset = 0xa000, 148 .vco_table = spark_vco, 149 .num_vco = ARRAY_SIZE(spark_vco), 150 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 151 .clkr = { 152 .enable_reg = 0x79000, 153 .enable_mask = BIT(10), 154 .hw.init = &(struct clk_init_data){ 155 .name = "gpll10", 156 .parent_data = &(const struct clk_parent_data){ 157 .fw_name = "bi_tcxo", 158 }, 159 .num_parents = 1, 160 .ops = &clk_alpha_pll_ops, 161 }, 162 }, 163 }; 164 165 /* 532MHz configuration */ 166 static const struct alpha_pll_config gpll11_config = { 167 .l = 0x1B, 168 .alpha = 0x55555555, 169 .alpha_hi = 0xB5, 170 .alpha_en_mask = BIT(24), 171 .vco_val = 0x2 << 20, 172 .vco_mask = GENMASK(21, 20), 173 .main_output_mask = BIT(0), 174 .config_ctl_val = 0x4001055B, 175 .test_ctl_hi1_val = 0x1, 176 }; 177 178 static struct clk_alpha_pll gpll11 = { 179 .offset = 0xb000, 180 .vco_table = default_vco, 181 .num_vco = ARRAY_SIZE(default_vco), 182 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 183 .flags = SUPPORTS_DYNAMIC_UPDATE, 184 .clkr = { 185 .enable_reg = 0x79000, 186 .enable_mask = BIT(11), 187 .hw.init = &(struct clk_init_data){ 188 .name = "gpll11", 189 .parent_data = &(const struct clk_parent_data){ 190 .fw_name = "bi_tcxo", 191 }, 192 .num_parents = 1, 193 .ops = &clk_alpha_pll_ops, 194 }, 195 }, 196 }; 197 198 static struct clk_alpha_pll gpll3 = { 199 .offset = 0x3000, 200 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 201 .clkr = { 202 .enable_reg = 0x79000, 203 .enable_mask = BIT(3), 204 .hw.init = &(struct clk_init_data){ 205 .name = "gpll3", 206 .parent_data = &(const struct clk_parent_data){ 207 .fw_name = "bi_tcxo", 208 }, 209 .num_parents = 1, 210 .ops = &clk_alpha_pll_ops, 211 }, 212 }, 213 }; 214 215 static const struct clk_div_table post_div_table_gpll3_out_main[] = { 216 { 0x1, 2 }, 217 { } 218 }; 219 220 static struct clk_alpha_pll_postdiv gpll3_out_main = { 221 .offset = 0x3000, 222 .post_div_shift = 8, 223 .post_div_table = post_div_table_gpll3_out_main, 224 .num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_main), 225 .width = 4, 226 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 227 .clkr.hw.init = &(struct clk_init_data){ 228 .name = "gpll3_out_main", 229 .parent_hws = (const struct clk_hw *[]){ &gpll3.clkr.hw }, 230 .num_parents = 1, 231 .ops = &clk_alpha_pll_postdiv_ro_ops, 232 }, 233 }; 234 235 static struct clk_alpha_pll gpll4 = { 236 .offset = 0x4000, 237 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 238 .clkr = { 239 .enable_reg = 0x79000, 240 .enable_mask = BIT(4), 241 .hw.init = &(struct clk_init_data){ 242 .name = "gpll4", 243 .parent_data = &(const struct clk_parent_data){ 244 .fw_name = "bi_tcxo", 245 }, 246 .num_parents = 1, 247 .ops = &clk_alpha_pll_ops, 248 }, 249 }, 250 }; 251 252 static struct clk_alpha_pll gpll5 = { 253 .offset = 0x5000, 254 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 255 .clkr = { 256 .enable_reg = 0x79000, 257 .enable_mask = BIT(5), 258 .hw.init = &(struct clk_init_data){ 259 .name = "gpll5", 260 .parent_data = &(const struct clk_parent_data){ 261 .fw_name = "bi_tcxo", 262 }, 263 .num_parents = 1, 264 .ops = &clk_alpha_pll_ops, 265 }, 266 }, 267 }; 268 269 static struct clk_alpha_pll gpll6 = { 270 .offset = 0x6000, 271 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 272 .clkr = { 273 .enable_reg = 0x79000, 274 .enable_mask = BIT(6), 275 .hw.init = &(struct clk_init_data){ 276 .name = "gpll6", 277 .parent_data = &(const struct clk_parent_data){ 278 .fw_name = "bi_tcxo", 279 }, 280 .num_parents = 1, 281 .ops = &clk_alpha_pll_ops, 282 }, 283 }, 284 }; 285 286 static const struct clk_div_table post_div_table_gpll6_out_main[] = { 287 { 0x1, 2 }, 288 { } 289 }; 290 291 static struct clk_alpha_pll_postdiv gpll6_out_main = { 292 .offset = 0x6000, 293 .post_div_shift = 8, 294 .post_div_table = post_div_table_gpll6_out_main, 295 .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main), 296 .width = 4, 297 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 298 .clkr.hw.init = &(struct clk_init_data){ 299 .name = "gpll6_out_main", 300 .parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw }, 301 .num_parents = 1, 302 .ops = &clk_alpha_pll_postdiv_ro_ops, 303 }, 304 }; 305 306 static struct clk_alpha_pll gpll7 = { 307 .offset = 0x7000, 308 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 309 .clkr = { 310 .enable_reg = 0x79000, 311 .enable_mask = BIT(7), 312 .hw.init = &(struct clk_init_data){ 313 .name = "gpll7", 314 .parent_data = &(const struct clk_parent_data){ 315 .fw_name = "bi_tcxo", 316 }, 317 .num_parents = 1, 318 .ops = &clk_alpha_pll_ops, 319 }, 320 }, 321 }; 322 323 /* 533.2MHz configuration */ 324 static const struct alpha_pll_config gpll8_config = { 325 .l = 0x1B, 326 .alpha = 0x55555555, 327 .alpha_hi = 0xC5, 328 .alpha_en_mask = BIT(24), 329 .vco_val = 0x2 << 20, 330 .vco_mask = GENMASK(21, 20), 331 .main_output_mask = BIT(0), 332 .early_output_mask = BIT(3), 333 .post_div_val = 0x1 << 8, 334 .post_div_mask = GENMASK(11, 8), 335 .config_ctl_val = 0x4001055B, 336 .test_ctl_hi1_val = 0x1, 337 }; 338 339 static struct clk_alpha_pll gpll8 = { 340 .offset = 0x8000, 341 .vco_table = default_vco, 342 .num_vco = ARRAY_SIZE(default_vco), 343 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 344 .flags = SUPPORTS_DYNAMIC_UPDATE, 345 .clkr = { 346 .enable_reg = 0x79000, 347 .enable_mask = BIT(8), 348 .hw.init = &(struct clk_init_data){ 349 .name = "gpll8", 350 .parent_data = &(const struct clk_parent_data){ 351 .fw_name = "bi_tcxo", 352 }, 353 .num_parents = 1, 354 .ops = &clk_alpha_pll_ops, 355 }, 356 }, 357 }; 358 359 static const struct clk_div_table post_div_table_gpll8_out_main[] = { 360 { 0x1, 2 }, 361 { } 362 }; 363 364 static struct clk_alpha_pll_postdiv gpll8_out_main = { 365 .offset = 0x8000, 366 .post_div_shift = 8, 367 .post_div_table = post_div_table_gpll8_out_main, 368 .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main), 369 .width = 4, 370 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 371 .clkr.hw.init = &(struct clk_init_data){ 372 .name = "gpll8_out_main", 373 .parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw }, 374 .num_parents = 1, 375 .flags = CLK_SET_RATE_PARENT, 376 .ops = &clk_alpha_pll_postdiv_ro_ops, 377 }, 378 }; 379 380 /* 1152MHz configuration */ 381 static const struct alpha_pll_config gpll9_config = { 382 .l = 0x3C, 383 .alpha = 0x0, 384 .post_div_val = 0x1 << 8, 385 .post_div_mask = GENMASK(9, 8), 386 .main_output_mask = BIT(0), 387 .early_output_mask = BIT(3), 388 .config_ctl_val = 0x00004289, 389 .test_ctl_val = 0x08000000, 390 }; 391 392 static struct clk_alpha_pll gpll9 = { 393 .offset = 0x9000, 394 .vco_table = brammo_vco, 395 .num_vco = ARRAY_SIZE(brammo_vco), 396 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO], 397 .clkr = { 398 .enable_reg = 0x79000, 399 .enable_mask = BIT(9), 400 .hw.init = &(struct clk_init_data){ 401 .name = "gpll9", 402 .parent_data = &(const struct clk_parent_data){ 403 .fw_name = "bi_tcxo", 404 }, 405 .num_parents = 1, 406 .ops = &clk_alpha_pll_ops, 407 }, 408 }, 409 }; 410 411 static const struct clk_div_table post_div_table_gpll9_out_main[] = { 412 { 0x1, 2 }, 413 { } 414 }; 415 416 static struct clk_alpha_pll_postdiv gpll9_out_main = { 417 .offset = 0x9000, 418 .post_div_shift = 8, 419 .post_div_table = post_div_table_gpll9_out_main, 420 .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main), 421 .width = 2, 422 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO], 423 .clkr.hw.init = &(struct clk_init_data){ 424 .name = "gpll9_out_main", 425 .parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw }, 426 .num_parents = 1, 427 .flags = CLK_SET_RATE_PARENT, 428 .ops = &clk_alpha_pll_postdiv_ro_ops, 429 }, 430 }; 431 432 static const struct parent_map gcc_parent_map_0[] = { 433 { P_BI_TCXO, 0 }, 434 { P_GPLL0_OUT_EARLY, 1 }, 435 { P_GPLL0_OUT_AUX2, 2 }, 436 }; 437 438 static const struct clk_parent_data gcc_parents_0[] = { 439 { .fw_name = "bi_tcxo" }, 440 { .hw = &gpll0.clkr.hw }, 441 { .hw = &gpll0_out_aux2.clkr.hw }, 442 }; 443 444 static const struct parent_map gcc_parent_map_1[] = { 445 { P_BI_TCXO, 0 }, 446 { P_GPLL0_OUT_EARLY, 1 }, 447 { P_GPLL0_OUT_AUX2, 2 }, 448 { P_GPLL6_OUT_MAIN, 4 }, 449 }; 450 451 static const struct clk_parent_data gcc_parents_1[] = { 452 { .fw_name = "bi_tcxo" }, 453 { .hw = &gpll0.clkr.hw }, 454 { .hw = &gpll0_out_aux2.clkr.hw }, 455 { .hw = &gpll6_out_main.clkr.hw }, 456 }; 457 458 static const struct parent_map gcc_parent_map_2[] = { 459 { P_BI_TCXO, 0 }, 460 { P_GPLL0_OUT_EARLY, 1 }, 461 { P_GPLL0_OUT_AUX2, 2 }, 462 { P_SLEEP_CLK, 5 }, 463 }; 464 465 static const struct clk_parent_data gcc_parents_2[] = { 466 { .fw_name = "bi_tcxo" }, 467 { .hw = &gpll0.clkr.hw }, 468 { .hw = &gpll0_out_aux2.clkr.hw }, 469 { .fw_name = "sleep_clk" }, 470 }; 471 472 static const struct parent_map gcc_parent_map_3[] = { 473 { P_BI_TCXO, 0 }, 474 { P_GPLL0_OUT_EARLY, 1 }, 475 { P_GPLL9_OUT_EARLY, 2 }, 476 { P_GPLL10_OUT_MAIN, 3 }, 477 { P_GPLL9_OUT_MAIN, 5 }, 478 { P_GPLL3_OUT_MAIN, 6 }, 479 }; 480 481 static const struct clk_parent_data gcc_parents_3[] = { 482 { .fw_name = "bi_tcxo" }, 483 { .hw = &gpll0.clkr.hw }, 484 { .hw = &gpll9.clkr.hw }, 485 { .hw = &gpll10.clkr.hw }, 486 { .hw = &gpll9_out_main.clkr.hw }, 487 { .hw = &gpll3_out_main.clkr.hw }, 488 }; 489 490 static const struct parent_map gcc_parent_map_4[] = { 491 { P_BI_TCXO, 0 }, 492 { P_GPLL0_OUT_EARLY, 1 }, 493 { P_GPLL0_OUT_AUX2, 2 }, 494 { P_GPLL10_OUT_MAIN, 3 }, 495 { P_GPLL4_OUT_MAIN, 5 }, 496 { P_GPLL3_OUT_EARLY, 6 }, 497 }; 498 499 static const struct clk_parent_data gcc_parents_4[] = { 500 { .fw_name = "bi_tcxo" }, 501 { .hw = &gpll0.clkr.hw }, 502 { .hw = &gpll0_out_aux2.clkr.hw }, 503 { .hw = &gpll10.clkr.hw }, 504 { .hw = &gpll4.clkr.hw }, 505 { .hw = &gpll3.clkr.hw }, 506 }; 507 508 static const struct parent_map gcc_parent_map_5[] = { 509 { P_BI_TCXO, 0 }, 510 { P_GPLL0_OUT_EARLY, 1 }, 511 { P_GPLL0_OUT_AUX2, 2 }, 512 { P_GPLL4_OUT_MAIN, 5 }, 513 { P_GPLL3_OUT_MAIN, 6 }, 514 }; 515 516 static const struct clk_parent_data gcc_parents_5[] = { 517 { .fw_name = "bi_tcxo" }, 518 { .hw = &gpll0.clkr.hw }, 519 { .hw = &gpll0_out_aux2.clkr.hw }, 520 { .hw = &gpll4.clkr.hw }, 521 { .hw = &gpll3_out_main.clkr.hw }, 522 }; 523 524 static const struct parent_map gcc_parent_map_6[] = { 525 { P_BI_TCXO, 0 }, 526 { P_GPLL0_OUT_EARLY, 1 }, 527 { P_GPLL8_OUT_EARLY, 2 }, 528 { P_GPLL10_OUT_MAIN, 3 }, 529 { P_GPLL8_OUT_MAIN, 4 }, 530 { P_GPLL9_OUT_MAIN, 5 }, 531 { P_GPLL3_OUT_EARLY, 6 }, 532 }; 533 534 static const struct clk_parent_data gcc_parents_6[] = { 535 { .fw_name = "bi_tcxo" }, 536 { .hw = &gpll0.clkr.hw }, 537 { .hw = &gpll8.clkr.hw }, 538 { .hw = &gpll10.clkr.hw }, 539 { .hw = &gpll8_out_main.clkr.hw }, 540 { .hw = &gpll9_out_main.clkr.hw }, 541 { .hw = &gpll3.clkr.hw }, 542 }; 543 544 static const struct parent_map gcc_parent_map_7[] = { 545 { P_BI_TCXO, 0 }, 546 { P_GPLL0_OUT_EARLY, 1 }, 547 { P_GPLL8_OUT_EARLY, 2 }, 548 { P_GPLL10_OUT_MAIN, 3 }, 549 { P_GPLL8_OUT_MAIN, 4 }, 550 { P_GPLL9_OUT_MAIN, 5 }, 551 { P_GPLL3_OUT_MAIN, 6 }, 552 }; 553 554 static const struct clk_parent_data gcc_parents_7[] = { 555 { .fw_name = "bi_tcxo" }, 556 { .hw = &gpll0.clkr.hw }, 557 { .hw = &gpll8.clkr.hw }, 558 { .hw = &gpll10.clkr.hw }, 559 { .hw = &gpll8_out_main.clkr.hw }, 560 { .hw = &gpll9_out_main.clkr.hw }, 561 { .hw = &gpll3_out_main.clkr.hw }, 562 }; 563 564 static const struct parent_map gcc_parent_map_8[] = { 565 { P_BI_TCXO, 0 }, 566 { P_GPLL0_OUT_EARLY, 1 }, 567 { P_GPLL8_OUT_EARLY, 2 }, 568 { P_GPLL10_OUT_MAIN, 3 }, 569 { P_GPLL6_OUT_MAIN, 4 }, 570 { P_GPLL9_OUT_MAIN, 5 }, 571 { P_GPLL3_OUT_EARLY, 6 }, 572 }; 573 574 static const struct clk_parent_data gcc_parents_8[] = { 575 { .fw_name = "bi_tcxo" }, 576 { .hw = &gpll0.clkr.hw }, 577 { .hw = &gpll8.clkr.hw }, 578 { .hw = &gpll10.clkr.hw }, 579 { .hw = &gpll6_out_main.clkr.hw }, 580 { .hw = &gpll9_out_main.clkr.hw }, 581 { .hw = &gpll3.clkr.hw }, 582 }; 583 584 static const struct parent_map gcc_parent_map_9[] = { 585 { P_BI_TCXO, 0 }, 586 { P_GPLL0_OUT_EARLY, 1 }, 587 { P_GPLL0_OUT_AUX2, 2 }, 588 { P_GPLL10_OUT_MAIN, 3 }, 589 { P_GPLL8_OUT_MAIN, 4 }, 590 { P_GPLL9_OUT_MAIN, 5 }, 591 { P_GPLL3_OUT_EARLY, 6 }, 592 }; 593 594 static const struct clk_parent_data gcc_parents_9[] = { 595 { .fw_name = "bi_tcxo" }, 596 { .hw = &gpll0.clkr.hw }, 597 { .hw = &gpll0_out_aux2.clkr.hw }, 598 { .hw = &gpll10.clkr.hw }, 599 { .hw = &gpll8_out_main.clkr.hw }, 600 { .hw = &gpll9_out_main.clkr.hw }, 601 { .hw = &gpll3.clkr.hw }, 602 }; 603 604 static const struct parent_map gcc_parent_map_10[] = { 605 { P_BI_TCXO, 0 }, 606 { P_GPLL0_OUT_EARLY, 1 }, 607 { P_GPLL8_OUT_EARLY, 2 }, 608 { P_GPLL10_OUT_MAIN, 3 }, 609 { P_GPLL6_OUT_EARLY, 5 }, 610 { P_GPLL3_OUT_MAIN, 6 }, 611 }; 612 613 static const struct clk_parent_data gcc_parents_10[] = { 614 { .fw_name = "bi_tcxo" }, 615 { .hw = &gpll0.clkr.hw }, 616 { .hw = &gpll8.clkr.hw }, 617 { .hw = &gpll10.clkr.hw }, 618 { .hw = &gpll6.clkr.hw }, 619 { .hw = &gpll3_out_main.clkr.hw }, 620 }; 621 622 static const struct parent_map gcc_parent_map_12[] = { 623 { P_BI_TCXO, 0 }, 624 { P_GPLL0_OUT_EARLY, 1 }, 625 { P_GPLL0_OUT_AUX2, 2 }, 626 { P_GPLL7_OUT_MAIN, 3 }, 627 { P_GPLL4_OUT_MAIN, 5 }, 628 }; 629 630 static const struct clk_parent_data gcc_parents_12[] = { 631 { .fw_name = "bi_tcxo" }, 632 { .hw = &gpll0.clkr.hw }, 633 { .hw = &gpll0_out_aux2.clkr.hw }, 634 { .hw = &gpll7.clkr.hw }, 635 { .hw = &gpll4.clkr.hw }, 636 }; 637 638 static const struct parent_map gcc_parent_map_13[] = { 639 { P_BI_TCXO, 0 }, 640 { P_SLEEP_CLK, 5 }, 641 }; 642 643 static const struct clk_parent_data gcc_parents_13[] = { 644 { .fw_name = "bi_tcxo" }, 645 { .fw_name = "sleep_clk" }, 646 }; 647 648 static const struct parent_map gcc_parent_map_14[] = { 649 { P_BI_TCXO, 0 }, 650 { P_GPLL11_OUT_MAIN, 1 }, 651 { P_GPLL11_OUT_AUX, 2 }, 652 { P_GPLL11_OUT_AUX2, 3 }, 653 }; 654 655 static const struct clk_parent_data gcc_parents_14[] = { 656 { .fw_name = "bi_tcxo" }, 657 { .hw = &gpll11.clkr.hw }, 658 { .hw = &gpll11.clkr.hw }, 659 { .hw = &gpll11.clkr.hw }, 660 }; 661 662 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 663 F(19200000, P_BI_TCXO, 1, 0, 0), 664 { } 665 }; 666 667 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 668 .cmd_rcgr = 0x1a034, 669 .mnd_width = 0, 670 .hid_width = 5, 671 .parent_map = gcc_parent_map_0, 672 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 673 .clkr.hw.init = &(struct clk_init_data){ 674 .name = "gcc_usb30_prim_mock_utmi_clk_src", 675 .parent_data = gcc_parents_0, 676 .num_parents = ARRAY_SIZE(gcc_parents_0), 677 .ops = &clk_rcg2_ops, 678 }, 679 }; 680 681 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv = { 682 .reg = 0x1a04c, 683 .shift = 0, 684 .width = 2, 685 .clkr.hw.init = &(struct clk_init_data) { 686 .name = "gcc_usb30_prim_mock_utmi_postdiv", 687 .parent_hws = (const struct clk_hw *[]) 688 { &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw }, 689 .num_parents = 1, 690 .flags = CLK_SET_RATE_PARENT, 691 .ops = &clk_regmap_div_ro_ops, 692 }, 693 }; 694 695 static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = { 696 F(19200000, P_BI_TCXO, 1, 0, 0), 697 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 698 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 699 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 700 { } 701 }; 702 703 static struct clk_rcg2 gcc_camss_axi_clk_src = { 704 .cmd_rcgr = 0x5802c, 705 .mnd_width = 0, 706 .hid_width = 5, 707 .parent_map = gcc_parent_map_4, 708 .freq_tbl = ftbl_gcc_camss_axi_clk_src, 709 .clkr.hw.init = &(struct clk_init_data){ 710 .name = "gcc_camss_axi_clk_src", 711 .parent_data = gcc_parents_4, 712 .num_parents = ARRAY_SIZE(gcc_parents_4), 713 .ops = &clk_rcg2_ops, 714 }, 715 }; 716 717 static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = { 718 F(19200000, P_BI_TCXO, 1, 0, 0), 719 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 720 { } 721 }; 722 723 static struct clk_rcg2 gcc_camss_cci_clk_src = { 724 .cmd_rcgr = 0x56000, 725 .mnd_width = 0, 726 .hid_width = 5, 727 .parent_map = gcc_parent_map_9, 728 .freq_tbl = ftbl_gcc_camss_cci_clk_src, 729 .clkr.hw.init = &(struct clk_init_data){ 730 .name = "gcc_camss_cci_clk_src", 731 .parent_data = gcc_parents_9, 732 .num_parents = ARRAY_SIZE(gcc_parents_9), 733 .ops = &clk_rcg2_ops, 734 }, 735 }; 736 737 static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = { 738 F(19200000, P_BI_TCXO, 1, 0, 0), 739 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 740 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 741 F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0), 742 { } 743 }; 744 745 static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { 746 .cmd_rcgr = 0x45000, 747 .mnd_width = 0, 748 .hid_width = 5, 749 .parent_map = gcc_parent_map_5, 750 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 751 .clkr.hw.init = &(struct clk_init_data){ 752 .name = "gcc_camss_csi0phytimer_clk_src", 753 .parent_data = gcc_parents_5, 754 .num_parents = ARRAY_SIZE(gcc_parents_5), 755 .ops = &clk_rcg2_ops, 756 }, 757 }; 758 759 static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { 760 .cmd_rcgr = 0x4501c, 761 .mnd_width = 0, 762 .hid_width = 5, 763 .parent_map = gcc_parent_map_5, 764 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 765 .clkr.hw.init = &(struct clk_init_data){ 766 .name = "gcc_camss_csi1phytimer_clk_src", 767 .parent_data = gcc_parents_5, 768 .num_parents = ARRAY_SIZE(gcc_parents_5), 769 .ops = &clk_rcg2_ops, 770 }, 771 }; 772 773 static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { 774 F(19200000, P_BI_TCXO, 1, 0, 0), 775 F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24), 776 F(64000000, P_GPLL9_OUT_EARLY, 9, 1, 2), 777 { } 778 }; 779 780 static struct clk_rcg2 gcc_camss_mclk0_clk_src = { 781 .cmd_rcgr = 0x51000, 782 .mnd_width = 8, 783 .hid_width = 5, 784 .parent_map = gcc_parent_map_3, 785 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 786 .clkr.hw.init = &(struct clk_init_data){ 787 .name = "gcc_camss_mclk0_clk_src", 788 .parent_data = gcc_parents_3, 789 .num_parents = ARRAY_SIZE(gcc_parents_3), 790 .flags = CLK_OPS_PARENT_ENABLE, 791 .ops = &clk_rcg2_ops, 792 }, 793 }; 794 795 static struct clk_rcg2 gcc_camss_mclk1_clk_src = { 796 .cmd_rcgr = 0x5101c, 797 .mnd_width = 8, 798 .hid_width = 5, 799 .parent_map = gcc_parent_map_3, 800 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 801 .clkr.hw.init = &(struct clk_init_data){ 802 .name = "gcc_camss_mclk1_clk_src", 803 .parent_data = gcc_parents_3, 804 .num_parents = ARRAY_SIZE(gcc_parents_3), 805 .flags = CLK_OPS_PARENT_ENABLE, 806 .ops = &clk_rcg2_ops, 807 }, 808 }; 809 810 static struct clk_rcg2 gcc_camss_mclk2_clk_src = { 811 .cmd_rcgr = 0x51038, 812 .mnd_width = 8, 813 .hid_width = 5, 814 .parent_map = gcc_parent_map_3, 815 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 816 .clkr.hw.init = &(struct clk_init_data){ 817 .name = "gcc_camss_mclk2_clk_src", 818 .parent_data = gcc_parents_3, 819 .num_parents = ARRAY_SIZE(gcc_parents_3), 820 .flags = CLK_OPS_PARENT_ENABLE, 821 .ops = &clk_rcg2_ops, 822 }, 823 }; 824 825 static struct clk_rcg2 gcc_camss_mclk3_clk_src = { 826 .cmd_rcgr = 0x51054, 827 .mnd_width = 8, 828 .hid_width = 5, 829 .parent_map = gcc_parent_map_3, 830 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 831 .clkr.hw.init = &(struct clk_init_data){ 832 .name = "gcc_camss_mclk3_clk_src", 833 .parent_data = gcc_parents_3, 834 .num_parents = ARRAY_SIZE(gcc_parents_3), 835 .flags = CLK_OPS_PARENT_ENABLE, 836 .ops = &clk_rcg2_ops, 837 }, 838 }; 839 840 static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = { 841 F(19200000, P_BI_TCXO, 1, 0, 0), 842 F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0), 843 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 844 { } 845 }; 846 847 static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = { 848 .cmd_rcgr = 0x55024, 849 .mnd_width = 0, 850 .hid_width = 5, 851 .parent_map = gcc_parent_map_6, 852 .freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src, 853 .clkr.hw.init = &(struct clk_init_data){ 854 .name = "gcc_camss_ope_ahb_clk_src", 855 .parent_data = gcc_parents_6, 856 .num_parents = ARRAY_SIZE(gcc_parents_6), 857 .ops = &clk_rcg2_ops, 858 }, 859 }; 860 861 static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = { 862 F(19200000, P_BI_TCXO, 1, 0, 0), 863 F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0), 864 F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0), 865 F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0), 866 F(580000000, P_GPLL8_OUT_EARLY, 1, 0, 0), 867 { } 868 }; 869 870 static struct clk_rcg2 gcc_camss_ope_clk_src = { 871 .cmd_rcgr = 0x55004, 872 .mnd_width = 0, 873 .hid_width = 5, 874 .parent_map = gcc_parent_map_6, 875 .freq_tbl = ftbl_gcc_camss_ope_clk_src, 876 .clkr.hw.init = &(struct clk_init_data){ 877 .name = "gcc_camss_ope_clk_src", 878 .parent_data = gcc_parents_6, 879 .num_parents = ARRAY_SIZE(gcc_parents_6), 880 .flags = CLK_SET_RATE_PARENT, 881 .ops = &clk_rcg2_ops, 882 }, 883 }; 884 885 static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = { 886 F(19200000, P_BI_TCXO, 1, 0, 0), 887 F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0), 888 F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0), 889 F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0), 890 F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0), 891 F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0), 892 F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0), 893 F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0), 894 F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0), 895 F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0), 896 F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0), 897 F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0), 898 F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0), 899 F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0), 900 F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0), 901 F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0), 902 { } 903 }; 904 905 static struct clk_rcg2 gcc_camss_tfe_0_clk_src = { 906 .cmd_rcgr = 0x52004, 907 .mnd_width = 8, 908 .hid_width = 5, 909 .parent_map = gcc_parent_map_7, 910 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 911 .clkr.hw.init = &(struct clk_init_data){ 912 .name = "gcc_camss_tfe_0_clk_src", 913 .parent_data = gcc_parents_7, 914 .num_parents = ARRAY_SIZE(gcc_parents_7), 915 .ops = &clk_rcg2_ops, 916 }, 917 }; 918 919 static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = { 920 F(19200000, P_BI_TCXO, 1, 0, 0), 921 F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0), 922 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 923 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 924 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 925 F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0), 926 { } 927 }; 928 929 static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = { 930 .cmd_rcgr = 0x52094, 931 .mnd_width = 0, 932 .hid_width = 5, 933 .parent_map = gcc_parent_map_8, 934 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 935 .clkr.hw.init = &(struct clk_init_data){ 936 .name = "gcc_camss_tfe_0_csid_clk_src", 937 .parent_data = gcc_parents_8, 938 .num_parents = ARRAY_SIZE(gcc_parents_8), 939 .ops = &clk_rcg2_ops, 940 }, 941 }; 942 943 static struct clk_rcg2 gcc_camss_tfe_1_clk_src = { 944 .cmd_rcgr = 0x52024, 945 .mnd_width = 8, 946 .hid_width = 5, 947 .parent_map = gcc_parent_map_7, 948 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 949 .clkr.hw.init = &(struct clk_init_data){ 950 .name = "gcc_camss_tfe_1_clk_src", 951 .parent_data = gcc_parents_7, 952 .num_parents = ARRAY_SIZE(gcc_parents_7), 953 .ops = &clk_rcg2_ops, 954 }, 955 }; 956 957 static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = { 958 .cmd_rcgr = 0x520b4, 959 .mnd_width = 0, 960 .hid_width = 5, 961 .parent_map = gcc_parent_map_8, 962 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 963 .clkr.hw.init = &(struct clk_init_data){ 964 .name = "gcc_camss_tfe_1_csid_clk_src", 965 .parent_data = gcc_parents_8, 966 .num_parents = ARRAY_SIZE(gcc_parents_8), 967 .ops = &clk_rcg2_ops, 968 }, 969 }; 970 971 static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = { 972 F(19200000, P_BI_TCXO, 1, 0, 0), 973 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 974 F(341333333, P_GPLL6_OUT_EARLY, 1, 4, 9), 975 F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0), 976 { } 977 }; 978 979 static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = { 980 .cmd_rcgr = 0x52064, 981 .mnd_width = 16, 982 .hid_width = 5, 983 .parent_map = gcc_parent_map_10, 984 .freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src, 985 .clkr.hw.init = &(struct clk_init_data){ 986 .name = "gcc_camss_tfe_cphy_rx_clk_src", 987 .parent_data = gcc_parents_10, 988 .num_parents = ARRAY_SIZE(gcc_parents_10), 989 .flags = CLK_OPS_PARENT_ENABLE, 990 .ops = &clk_rcg2_ops, 991 }, 992 }; 993 994 static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = { 995 F(19200000, P_BI_TCXO, 1, 0, 0), 996 F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0), 997 F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0), 998 { } 999 }; 1000 1001 static struct clk_rcg2 gcc_camss_top_ahb_clk_src = { 1002 .cmd_rcgr = 0x58010, 1003 .mnd_width = 0, 1004 .hid_width = 5, 1005 .parent_map = gcc_parent_map_4, 1006 .freq_tbl = ftbl_gcc_camss_top_ahb_clk_src, 1007 .clkr.hw.init = &(struct clk_init_data){ 1008 .name = "gcc_camss_top_ahb_clk_src", 1009 .parent_data = gcc_parents_4, 1010 .num_parents = ARRAY_SIZE(gcc_parents_4), 1011 .ops = &clk_rcg2_ops, 1012 }, 1013 }; 1014 1015 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 1016 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1017 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1018 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1019 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 1020 { } 1021 }; 1022 1023 static struct clk_rcg2 gcc_gp1_clk_src = { 1024 .cmd_rcgr = 0x4d004, 1025 .mnd_width = 8, 1026 .hid_width = 5, 1027 .parent_map = gcc_parent_map_2, 1028 .freq_tbl = ftbl_gcc_gp1_clk_src, 1029 .clkr.hw.init = &(struct clk_init_data){ 1030 .name = "gcc_gp1_clk_src", 1031 .parent_data = gcc_parents_2, 1032 .num_parents = ARRAY_SIZE(gcc_parents_2), 1033 .ops = &clk_rcg2_ops, 1034 }, 1035 }; 1036 1037 static struct clk_rcg2 gcc_gp2_clk_src = { 1038 .cmd_rcgr = 0x4e004, 1039 .mnd_width = 8, 1040 .hid_width = 5, 1041 .parent_map = gcc_parent_map_2, 1042 .freq_tbl = ftbl_gcc_gp1_clk_src, 1043 .clkr.hw.init = &(struct clk_init_data){ 1044 .name = "gcc_gp2_clk_src", 1045 .parent_data = gcc_parents_2, 1046 .num_parents = ARRAY_SIZE(gcc_parents_2), 1047 .ops = &clk_rcg2_ops, 1048 }, 1049 }; 1050 1051 static struct clk_rcg2 gcc_gp3_clk_src = { 1052 .cmd_rcgr = 0x4f004, 1053 .mnd_width = 8, 1054 .hid_width = 5, 1055 .parent_map = gcc_parent_map_2, 1056 .freq_tbl = ftbl_gcc_gp1_clk_src, 1057 .clkr.hw.init = &(struct clk_init_data){ 1058 .name = "gcc_gp3_clk_src", 1059 .parent_data = gcc_parents_2, 1060 .num_parents = ARRAY_SIZE(gcc_parents_2), 1061 .ops = &clk_rcg2_ops, 1062 }, 1063 }; 1064 1065 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 1066 F(19200000, P_BI_TCXO, 1, 0, 0), 1067 F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0), 1068 { } 1069 }; 1070 1071 static struct clk_rcg2 gcc_pdm2_clk_src = { 1072 .cmd_rcgr = 0x20010, 1073 .mnd_width = 0, 1074 .hid_width = 5, 1075 .parent_map = gcc_parent_map_0, 1076 .freq_tbl = ftbl_gcc_pdm2_clk_src, 1077 .clkr.hw.init = &(struct clk_init_data){ 1078 .name = "gcc_pdm2_clk_src", 1079 .parent_data = gcc_parents_0, 1080 .num_parents = ARRAY_SIZE(gcc_parents_0), 1081 .ops = &clk_rcg2_ops, 1082 }, 1083 }; 1084 1085 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 1086 F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625), 1087 F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625), 1088 F(19200000, P_BI_TCXO, 1, 0, 0), 1089 F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625), 1090 F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75), 1091 F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25), 1092 F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75), 1093 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1094 F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15), 1095 F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25), 1096 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1097 F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375), 1098 F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75), 1099 F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625), 1100 F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0), 1101 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0), 1102 { } 1103 }; 1104 1105 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 1106 .name = "gcc_qupv3_wrap0_s0_clk_src", 1107 .parent_data = gcc_parents_1, 1108 .num_parents = ARRAY_SIZE(gcc_parents_1), 1109 .ops = &clk_rcg2_ops, 1110 }; 1111 1112 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 1113 .cmd_rcgr = 0x1f148, 1114 .mnd_width = 16, 1115 .hid_width = 5, 1116 .parent_map = gcc_parent_map_1, 1117 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1118 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 1119 }; 1120 1121 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 1122 .name = "gcc_qupv3_wrap0_s1_clk_src", 1123 .parent_data = gcc_parents_1, 1124 .num_parents = ARRAY_SIZE(gcc_parents_1), 1125 .ops = &clk_rcg2_ops, 1126 }; 1127 1128 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 1129 .cmd_rcgr = 0x1f278, 1130 .mnd_width = 16, 1131 .hid_width = 5, 1132 .parent_map = gcc_parent_map_1, 1133 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1134 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 1135 }; 1136 1137 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 1138 .name = "gcc_qupv3_wrap0_s2_clk_src", 1139 .parent_data = gcc_parents_1, 1140 .num_parents = ARRAY_SIZE(gcc_parents_1), 1141 .ops = &clk_rcg2_ops, 1142 }; 1143 1144 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 1145 .cmd_rcgr = 0x1f3a8, 1146 .mnd_width = 16, 1147 .hid_width = 5, 1148 .parent_map = gcc_parent_map_1, 1149 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1150 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 1151 }; 1152 1153 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 1154 .name = "gcc_qupv3_wrap0_s3_clk_src", 1155 .parent_data = gcc_parents_1, 1156 .num_parents = ARRAY_SIZE(gcc_parents_1), 1157 .ops = &clk_rcg2_ops, 1158 }; 1159 1160 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 1161 .cmd_rcgr = 0x1f4d8, 1162 .mnd_width = 16, 1163 .hid_width = 5, 1164 .parent_map = gcc_parent_map_1, 1165 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1166 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 1167 }; 1168 1169 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 1170 .name = "gcc_qupv3_wrap0_s4_clk_src", 1171 .parent_data = gcc_parents_1, 1172 .num_parents = ARRAY_SIZE(gcc_parents_1), 1173 .ops = &clk_rcg2_ops, 1174 }; 1175 1176 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 1177 .cmd_rcgr = 0x1f608, 1178 .mnd_width = 16, 1179 .hid_width = 5, 1180 .parent_map = gcc_parent_map_1, 1181 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1182 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 1183 }; 1184 1185 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 1186 .name = "gcc_qupv3_wrap0_s5_clk_src", 1187 .parent_data = gcc_parents_1, 1188 .num_parents = ARRAY_SIZE(gcc_parents_1), 1189 .ops = &clk_rcg2_ops, 1190 }; 1191 1192 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 1193 .cmd_rcgr = 0x1f738, 1194 .mnd_width = 16, 1195 .hid_width = 5, 1196 .parent_map = gcc_parent_map_1, 1197 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1198 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 1199 }; 1200 1201 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 1202 F(144000, P_BI_TCXO, 16, 3, 25), 1203 F(400000, P_BI_TCXO, 12, 1, 4), 1204 F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3), 1205 F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2), 1206 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1207 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1208 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 1209 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 1210 { } 1211 }; 1212 1213 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 1214 .cmd_rcgr = 0x38028, 1215 .mnd_width = 8, 1216 .hid_width = 5, 1217 .parent_map = gcc_parent_map_1, 1218 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 1219 .clkr.hw.init = &(struct clk_init_data){ 1220 .name = "gcc_sdcc1_apps_clk_src", 1221 .parent_data = gcc_parents_1, 1222 .num_parents = ARRAY_SIZE(gcc_parents_1), 1223 .ops = &clk_rcg2_floor_ops, 1224 }, 1225 }; 1226 1227 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 1228 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1229 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1230 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1231 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1232 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 1233 { } 1234 }; 1235 1236 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 1237 .cmd_rcgr = 0x38010, 1238 .mnd_width = 0, 1239 .hid_width = 5, 1240 .parent_map = gcc_parent_map_0, 1241 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 1242 .clkr.hw.init = &(struct clk_init_data){ 1243 .name = "gcc_sdcc1_ice_core_clk_src", 1244 .parent_data = gcc_parents_0, 1245 .num_parents = ARRAY_SIZE(gcc_parents_0), 1246 .ops = &clk_rcg2_ops, 1247 }, 1248 }; 1249 1250 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1251 F(400000, P_BI_TCXO, 12, 1, 4), 1252 F(19200000, P_BI_TCXO, 1, 0, 0), 1253 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1254 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1255 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1256 F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0), 1257 { } 1258 }; 1259 1260 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1261 .cmd_rcgr = 0x1e00c, 1262 .mnd_width = 8, 1263 .hid_width = 5, 1264 .parent_map = gcc_parent_map_12, 1265 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1266 .clkr.hw.init = &(struct clk_init_data){ 1267 .name = "gcc_sdcc2_apps_clk_src", 1268 .parent_data = gcc_parents_12, 1269 .num_parents = ARRAY_SIZE(gcc_parents_12), 1270 .ops = &clk_rcg2_ops, 1271 }, 1272 }; 1273 1274 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1275 F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0), 1276 F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0), 1277 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1278 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1279 { } 1280 }; 1281 1282 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1283 .cmd_rcgr = 0x1a01c, 1284 .mnd_width = 8, 1285 .hid_width = 5, 1286 .parent_map = gcc_parent_map_0, 1287 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1288 .clkr.hw.init = &(struct clk_init_data){ 1289 .name = "gcc_usb30_prim_master_clk_src", 1290 .parent_data = gcc_parents_0, 1291 .num_parents = ARRAY_SIZE(gcc_parents_0), 1292 .ops = &clk_rcg2_ops, 1293 }, 1294 }; 1295 1296 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1297 .cmd_rcgr = 0x1a060, 1298 .mnd_width = 0, 1299 .hid_width = 5, 1300 .parent_map = gcc_parent_map_13, 1301 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1302 .clkr.hw.init = &(struct clk_init_data){ 1303 .name = "gcc_usb3_prim_phy_aux_clk_src", 1304 .parent_data = gcc_parents_13, 1305 .num_parents = ARRAY_SIZE(gcc_parents_13), 1306 .ops = &clk_rcg2_ops, 1307 }, 1308 }; 1309 1310 static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = { 1311 F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0), 1312 F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0), 1313 F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0), 1314 F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0), 1315 { } 1316 }; 1317 1318 static struct clk_rcg2 gcc_video_venus_clk_src = { 1319 .cmd_rcgr = 0x58060, 1320 .mnd_width = 0, 1321 .hid_width = 5, 1322 .parent_map = gcc_parent_map_14, 1323 .freq_tbl = ftbl_gcc_video_venus_clk_src, 1324 .clkr.hw.init = &(struct clk_init_data){ 1325 .name = "gcc_video_venus_clk_src", 1326 .parent_data = gcc_parents_14, 1327 .num_parents = ARRAY_SIZE(gcc_parents_14), 1328 .flags = CLK_SET_RATE_PARENT, 1329 .ops = &clk_rcg2_ops, 1330 }, 1331 }; 1332 1333 static struct clk_branch gcc_ahb2phy_csi_clk = { 1334 .halt_reg = 0x1d004, 1335 .halt_check = BRANCH_HALT_DELAY, 1336 .hwcg_reg = 0x1d004, 1337 .hwcg_bit = 1, 1338 .clkr = { 1339 .enable_reg = 0x1d004, 1340 .enable_mask = BIT(0), 1341 .hw.init = &(struct clk_init_data){ 1342 .name = "gcc_ahb2phy_csi_clk", 1343 .ops = &clk_branch2_ops, 1344 }, 1345 }, 1346 }; 1347 1348 static struct clk_branch gcc_ahb2phy_usb_clk = { 1349 .halt_reg = 0x1d008, 1350 .halt_check = BRANCH_HALT, 1351 .hwcg_reg = 0x1d008, 1352 .hwcg_bit = 1, 1353 .clkr = { 1354 .enable_reg = 0x1d008, 1355 .enable_mask = BIT(0), 1356 .hw.init = &(struct clk_init_data){ 1357 .name = "gcc_ahb2phy_usb_clk", 1358 .ops = &clk_branch2_ops, 1359 }, 1360 }, 1361 }; 1362 1363 static struct clk_branch gcc_bimc_gpu_axi_clk = { 1364 .halt_reg = 0x71154, 1365 .halt_check = BRANCH_HALT_DELAY, 1366 .hwcg_reg = 0x71154, 1367 .hwcg_bit = 1, 1368 .clkr = { 1369 .enable_reg = 0x71154, 1370 .enable_mask = BIT(0), 1371 .hw.init = &(struct clk_init_data){ 1372 .name = "gcc_bimc_gpu_axi_clk", 1373 .ops = &clk_branch2_ops, 1374 }, 1375 }, 1376 }; 1377 1378 static struct clk_branch gcc_boot_rom_ahb_clk = { 1379 .halt_reg = 0x23004, 1380 .halt_check = BRANCH_HALT_VOTED, 1381 .hwcg_reg = 0x23004, 1382 .hwcg_bit = 1, 1383 .clkr = { 1384 .enable_reg = 0x79004, 1385 .enable_mask = BIT(10), 1386 .hw.init = &(struct clk_init_data){ 1387 .name = "gcc_boot_rom_ahb_clk", 1388 .ops = &clk_branch2_ops, 1389 }, 1390 }, 1391 }; 1392 1393 static struct clk_branch gcc_cam_throttle_nrt_clk = { 1394 .halt_reg = 0x17070, 1395 .halt_check = BRANCH_HALT_VOTED, 1396 .hwcg_reg = 0x17070, 1397 .hwcg_bit = 1, 1398 .clkr = { 1399 .enable_reg = 0x79004, 1400 .enable_mask = BIT(27), 1401 .hw.init = &(struct clk_init_data){ 1402 .name = "gcc_cam_throttle_nrt_clk", 1403 .ops = &clk_branch2_ops, 1404 }, 1405 }, 1406 }; 1407 1408 static struct clk_branch gcc_cam_throttle_rt_clk = { 1409 .halt_reg = 0x1706c, 1410 .halt_check = BRANCH_HALT_VOTED, 1411 .hwcg_reg = 0x1706c, 1412 .hwcg_bit = 1, 1413 .clkr = { 1414 .enable_reg = 0x79004, 1415 .enable_mask = BIT(26), 1416 .hw.init = &(struct clk_init_data){ 1417 .name = "gcc_cam_throttle_rt_clk", 1418 .ops = &clk_branch2_ops, 1419 }, 1420 }, 1421 }; 1422 1423 static struct clk_branch gcc_camera_ahb_clk = { 1424 .halt_reg = 0x17008, 1425 .halt_check = BRANCH_HALT_DELAY, 1426 .hwcg_reg = 0x17008, 1427 .hwcg_bit = 1, 1428 .clkr = { 1429 .enable_reg = 0x17008, 1430 .enable_mask = BIT(0), 1431 .hw.init = &(struct clk_init_data){ 1432 .name = "gcc_camera_ahb_clk", 1433 .flags = CLK_IS_CRITICAL, 1434 .ops = &clk_branch2_ops, 1435 }, 1436 }, 1437 }; 1438 1439 static struct clk_branch gcc_camera_xo_clk = { 1440 .halt_reg = 0x17028, 1441 .halt_check = BRANCH_HALT, 1442 .clkr = { 1443 .enable_reg = 0x17028, 1444 .enable_mask = BIT(0), 1445 .hw.init = &(struct clk_init_data){ 1446 .name = "gcc_camera_xo_clk", 1447 .flags = CLK_IS_CRITICAL, 1448 .ops = &clk_branch2_ops, 1449 }, 1450 }, 1451 }; 1452 1453 static struct clk_branch gcc_camss_axi_clk = { 1454 .halt_reg = 0x58044, 1455 .halt_check = BRANCH_HALT, 1456 .clkr = { 1457 .enable_reg = 0x58044, 1458 .enable_mask = BIT(0), 1459 .hw.init = &(struct clk_init_data){ 1460 .name = "gcc_camss_axi_clk", 1461 .parent_hws = (const struct clk_hw *[]) 1462 { &gcc_camss_axi_clk_src.clkr.hw }, 1463 .num_parents = 1, 1464 .flags = CLK_SET_RATE_PARENT, 1465 .ops = &clk_branch2_ops, 1466 }, 1467 }, 1468 }; 1469 1470 static struct clk_branch gcc_camss_camnoc_atb_clk = { 1471 .halt_reg = 0x5804c, 1472 .halt_check = BRANCH_HALT_DELAY, 1473 .hwcg_reg = 0x5804c, 1474 .hwcg_bit = 1, 1475 .clkr = { 1476 .enable_reg = 0x5804c, 1477 .enable_mask = BIT(0), 1478 .hw.init = &(struct clk_init_data){ 1479 .name = "gcc_camss_camnoc_atb_clk", 1480 .ops = &clk_branch2_ops, 1481 }, 1482 }, 1483 }; 1484 1485 static struct clk_branch gcc_camss_camnoc_nts_xo_clk = { 1486 .halt_reg = 0x58050, 1487 .halt_check = BRANCH_HALT_DELAY, 1488 .hwcg_reg = 0x58050, 1489 .hwcg_bit = 1, 1490 .clkr = { 1491 .enable_reg = 0x58050, 1492 .enable_mask = BIT(0), 1493 .hw.init = &(struct clk_init_data){ 1494 .name = "gcc_camss_camnoc_nts_xo_clk", 1495 .ops = &clk_branch2_ops, 1496 }, 1497 }, 1498 }; 1499 1500 static struct clk_branch gcc_camss_cci_0_clk = { 1501 .halt_reg = 0x56018, 1502 .halt_check = BRANCH_HALT, 1503 .clkr = { 1504 .enable_reg = 0x56018, 1505 .enable_mask = BIT(0), 1506 .hw.init = &(struct clk_init_data){ 1507 .name = "gcc_camss_cci_0_clk", 1508 .parent_hws = (const struct clk_hw *[]) 1509 { &gcc_camss_cci_clk_src.clkr.hw }, 1510 .num_parents = 1, 1511 .flags = CLK_SET_RATE_PARENT, 1512 .ops = &clk_branch2_ops, 1513 }, 1514 }, 1515 }; 1516 1517 static struct clk_branch gcc_camss_cphy_0_clk = { 1518 .halt_reg = 0x52088, 1519 .halt_check = BRANCH_HALT, 1520 .clkr = { 1521 .enable_reg = 0x52088, 1522 .enable_mask = BIT(0), 1523 .hw.init = &(struct clk_init_data){ 1524 .name = "gcc_camss_cphy_0_clk", 1525 .parent_hws = (const struct clk_hw *[]) 1526 { &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw }, 1527 .num_parents = 1, 1528 .flags = CLK_SET_RATE_PARENT, 1529 .ops = &clk_branch2_ops, 1530 }, 1531 }, 1532 }; 1533 1534 static struct clk_branch gcc_camss_cphy_1_clk = { 1535 .halt_reg = 0x5208c, 1536 .halt_check = BRANCH_HALT, 1537 .clkr = { 1538 .enable_reg = 0x5208c, 1539 .enable_mask = BIT(0), 1540 .hw.init = &(struct clk_init_data){ 1541 .name = "gcc_camss_cphy_1_clk", 1542 .parent_hws = (const struct clk_hw *[]) 1543 { &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw }, 1544 .num_parents = 1, 1545 .flags = CLK_SET_RATE_PARENT, 1546 .ops = &clk_branch2_ops, 1547 }, 1548 }, 1549 }; 1550 1551 static struct clk_branch gcc_camss_csi0phytimer_clk = { 1552 .halt_reg = 0x45018, 1553 .halt_check = BRANCH_HALT, 1554 .clkr = { 1555 .enable_reg = 0x45018, 1556 .enable_mask = BIT(0), 1557 .hw.init = &(struct clk_init_data){ 1558 .name = "gcc_camss_csi0phytimer_clk", 1559 .parent_hws = (const struct clk_hw *[]) 1560 { &gcc_camss_csi0phytimer_clk_src.clkr.hw }, 1561 .num_parents = 1, 1562 .flags = CLK_SET_RATE_PARENT, 1563 .ops = &clk_branch2_ops, 1564 }, 1565 }, 1566 }; 1567 1568 static struct clk_branch gcc_camss_csi1phytimer_clk = { 1569 .halt_reg = 0x45034, 1570 .halt_check = BRANCH_HALT, 1571 .clkr = { 1572 .enable_reg = 0x45034, 1573 .enable_mask = BIT(0), 1574 .hw.init = &(struct clk_init_data){ 1575 .name = "gcc_camss_csi1phytimer_clk", 1576 .parent_hws = (const struct clk_hw *[]) 1577 { &gcc_camss_csi1phytimer_clk_src.clkr.hw }, 1578 .num_parents = 1, 1579 .flags = CLK_SET_RATE_PARENT, 1580 .ops = &clk_branch2_ops, 1581 }, 1582 }, 1583 }; 1584 1585 static struct clk_branch gcc_camss_mclk0_clk = { 1586 .halt_reg = 0x51018, 1587 .halt_check = BRANCH_HALT, 1588 .clkr = { 1589 .enable_reg = 0x51018, 1590 .enable_mask = BIT(0), 1591 .hw.init = &(struct clk_init_data){ 1592 .name = "gcc_camss_mclk0_clk", 1593 .parent_hws = (const struct clk_hw *[]) 1594 { &gcc_camss_mclk0_clk_src.clkr.hw }, 1595 .num_parents = 1, 1596 .flags = CLK_SET_RATE_PARENT, 1597 .ops = &clk_branch2_ops, 1598 }, 1599 }, 1600 }; 1601 1602 static struct clk_branch gcc_camss_mclk1_clk = { 1603 .halt_reg = 0x51034, 1604 .halt_check = BRANCH_HALT, 1605 .clkr = { 1606 .enable_reg = 0x51034, 1607 .enable_mask = BIT(0), 1608 .hw.init = &(struct clk_init_data){ 1609 .name = "gcc_camss_mclk1_clk", 1610 .parent_hws = (const struct clk_hw *[]) 1611 { &gcc_camss_mclk1_clk_src.clkr.hw }, 1612 .num_parents = 1, 1613 .flags = CLK_SET_RATE_PARENT, 1614 .ops = &clk_branch2_ops, 1615 }, 1616 }, 1617 }; 1618 1619 static struct clk_branch gcc_camss_mclk2_clk = { 1620 .halt_reg = 0x51050, 1621 .halt_check = BRANCH_HALT, 1622 .clkr = { 1623 .enable_reg = 0x51050, 1624 .enable_mask = BIT(0), 1625 .hw.init = &(struct clk_init_data){ 1626 .name = "gcc_camss_mclk2_clk", 1627 .parent_hws = (const struct clk_hw *[]) 1628 { &gcc_camss_mclk2_clk_src.clkr.hw }, 1629 .num_parents = 1, 1630 .flags = CLK_SET_RATE_PARENT, 1631 .ops = &clk_branch2_ops, 1632 }, 1633 }, 1634 }; 1635 1636 static struct clk_branch gcc_camss_mclk3_clk = { 1637 .halt_reg = 0x5106c, 1638 .halt_check = BRANCH_HALT, 1639 .clkr = { 1640 .enable_reg = 0x5106c, 1641 .enable_mask = BIT(0), 1642 .hw.init = &(struct clk_init_data){ 1643 .name = "gcc_camss_mclk3_clk", 1644 .parent_hws = (const struct clk_hw *[]) 1645 { &gcc_camss_mclk3_clk_src.clkr.hw }, 1646 .num_parents = 1, 1647 .flags = CLK_SET_RATE_PARENT, 1648 .ops = &clk_branch2_ops, 1649 }, 1650 }, 1651 }; 1652 1653 static struct clk_branch gcc_camss_nrt_axi_clk = { 1654 .halt_reg = 0x58054, 1655 .halt_check = BRANCH_HALT, 1656 .clkr = { 1657 .enable_reg = 0x58054, 1658 .enable_mask = BIT(0), 1659 .hw.init = &(struct clk_init_data){ 1660 .name = "gcc_camss_nrt_axi_clk", 1661 .ops = &clk_branch2_ops, 1662 }, 1663 }, 1664 }; 1665 1666 static struct clk_branch gcc_camss_ope_ahb_clk = { 1667 .halt_reg = 0x5503c, 1668 .halt_check = BRANCH_HALT, 1669 .clkr = { 1670 .enable_reg = 0x5503c, 1671 .enable_mask = BIT(0), 1672 .hw.init = &(struct clk_init_data){ 1673 .name = "gcc_camss_ope_ahb_clk", 1674 .parent_hws = (const struct clk_hw *[]) 1675 { &gcc_camss_ope_ahb_clk_src.clkr.hw }, 1676 .num_parents = 1, 1677 .flags = CLK_SET_RATE_PARENT, 1678 .ops = &clk_branch2_ops, 1679 }, 1680 }, 1681 }; 1682 1683 static struct clk_branch gcc_camss_ope_clk = { 1684 .halt_reg = 0x5501c, 1685 .halt_check = BRANCH_HALT, 1686 .clkr = { 1687 .enable_reg = 0x5501c, 1688 .enable_mask = BIT(0), 1689 .hw.init = &(struct clk_init_data){ 1690 .name = "gcc_camss_ope_clk", 1691 .parent_hws = (const struct clk_hw *[]) 1692 { &gcc_camss_ope_clk_src.clkr.hw }, 1693 .num_parents = 1, 1694 .flags = CLK_SET_RATE_PARENT, 1695 .ops = &clk_branch2_ops, 1696 }, 1697 }, 1698 }; 1699 1700 static struct clk_branch gcc_camss_rt_axi_clk = { 1701 .halt_reg = 0x5805c, 1702 .halt_check = BRANCH_HALT, 1703 .clkr = { 1704 .enable_reg = 0x5805c, 1705 .enable_mask = BIT(0), 1706 .hw.init = &(struct clk_init_data){ 1707 .name = "gcc_camss_rt_axi_clk", 1708 .ops = &clk_branch2_ops, 1709 }, 1710 }, 1711 }; 1712 1713 static struct clk_branch gcc_camss_tfe_0_clk = { 1714 .halt_reg = 0x5201c, 1715 .halt_check = BRANCH_HALT, 1716 .clkr = { 1717 .enable_reg = 0x5201c, 1718 .enable_mask = BIT(0), 1719 .hw.init = &(struct clk_init_data){ 1720 .name = "gcc_camss_tfe_0_clk", 1721 .parent_hws = (const struct clk_hw *[]) 1722 { &gcc_camss_tfe_0_clk_src.clkr.hw }, 1723 .num_parents = 1, 1724 .flags = CLK_SET_RATE_PARENT, 1725 .ops = &clk_branch2_ops, 1726 }, 1727 }, 1728 }; 1729 1730 static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = { 1731 .halt_reg = 0x5207c, 1732 .halt_check = BRANCH_HALT, 1733 .clkr = { 1734 .enable_reg = 0x5207c, 1735 .enable_mask = BIT(0), 1736 .hw.init = &(struct clk_init_data){ 1737 .name = "gcc_camss_tfe_0_cphy_rx_clk", 1738 .parent_hws = (const struct clk_hw *[]) 1739 { &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw }, 1740 .num_parents = 1, 1741 .flags = CLK_SET_RATE_PARENT, 1742 .ops = &clk_branch2_ops, 1743 }, 1744 }, 1745 }; 1746 1747 static struct clk_branch gcc_camss_tfe_0_csid_clk = { 1748 .halt_reg = 0x520ac, 1749 .halt_check = BRANCH_HALT, 1750 .clkr = { 1751 .enable_reg = 0x520ac, 1752 .enable_mask = BIT(0), 1753 .hw.init = &(struct clk_init_data){ 1754 .name = "gcc_camss_tfe_0_csid_clk", 1755 .parent_hws = (const struct clk_hw *[]) 1756 { &gcc_camss_tfe_0_csid_clk_src.clkr.hw }, 1757 .num_parents = 1, 1758 .flags = CLK_SET_RATE_PARENT, 1759 .ops = &clk_branch2_ops, 1760 }, 1761 }, 1762 }; 1763 1764 static struct clk_branch gcc_camss_tfe_1_clk = { 1765 .halt_reg = 0x5203c, 1766 .halt_check = BRANCH_HALT, 1767 .clkr = { 1768 .enable_reg = 0x5203c, 1769 .enable_mask = BIT(0), 1770 .hw.init = &(struct clk_init_data){ 1771 .name = "gcc_camss_tfe_1_clk", 1772 .parent_hws = (const struct clk_hw *[]) 1773 { &gcc_camss_tfe_1_clk_src.clkr.hw }, 1774 .num_parents = 1, 1775 .flags = CLK_SET_RATE_PARENT, 1776 .ops = &clk_branch2_ops, 1777 }, 1778 }, 1779 }; 1780 1781 static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = { 1782 .halt_reg = 0x52080, 1783 .halt_check = BRANCH_HALT, 1784 .clkr = { 1785 .enable_reg = 0x52080, 1786 .enable_mask = BIT(0), 1787 .hw.init = &(struct clk_init_data){ 1788 .name = "gcc_camss_tfe_1_cphy_rx_clk", 1789 .parent_hws = (const struct clk_hw *[]) 1790 { &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw }, 1791 .num_parents = 1, 1792 .flags = CLK_SET_RATE_PARENT, 1793 .ops = &clk_branch2_ops, 1794 }, 1795 }, 1796 }; 1797 1798 static struct clk_branch gcc_camss_tfe_1_csid_clk = { 1799 .halt_reg = 0x520cc, 1800 .halt_check = BRANCH_HALT, 1801 .clkr = { 1802 .enable_reg = 0x520cc, 1803 .enable_mask = BIT(0), 1804 .hw.init = &(struct clk_init_data){ 1805 .name = "gcc_camss_tfe_1_csid_clk", 1806 .parent_hws = (const struct clk_hw *[]) 1807 { &gcc_camss_tfe_1_csid_clk_src.clkr.hw }, 1808 .num_parents = 1, 1809 .flags = CLK_SET_RATE_PARENT, 1810 .ops = &clk_branch2_ops, 1811 }, 1812 }, 1813 }; 1814 1815 static struct clk_branch gcc_camss_top_ahb_clk = { 1816 .halt_reg = 0x58028, 1817 .halt_check = BRANCH_HALT, 1818 .clkr = { 1819 .enable_reg = 0x58028, 1820 .enable_mask = BIT(0), 1821 .hw.init = &(struct clk_init_data){ 1822 .name = "gcc_camss_top_ahb_clk", 1823 .parent_hws = (const struct clk_hw *[]) 1824 { &gcc_camss_top_ahb_clk_src.clkr.hw }, 1825 .num_parents = 1, 1826 .flags = CLK_SET_RATE_PARENT, 1827 .ops = &clk_branch2_ops, 1828 }, 1829 }, 1830 }; 1831 1832 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1833 .halt_reg = 0x1a084, 1834 .halt_check = BRANCH_HALT, 1835 .hwcg_reg = 0x1a084, 1836 .hwcg_bit = 1, 1837 .clkr = { 1838 .enable_reg = 0x1a084, 1839 .enable_mask = BIT(0), 1840 .hw.init = &(struct clk_init_data){ 1841 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1842 .parent_hws = (const struct clk_hw *[]) 1843 { &gcc_usb30_prim_master_clk_src.clkr.hw }, 1844 .num_parents = 1, 1845 .flags = CLK_SET_RATE_PARENT, 1846 .ops = &clk_branch2_ops, 1847 }, 1848 }, 1849 }; 1850 1851 static struct clk_branch gcc_disp_ahb_clk = { 1852 .halt_reg = 0x1700c, 1853 .halt_check = BRANCH_HALT, 1854 .hwcg_reg = 0x1700c, 1855 .hwcg_bit = 1, 1856 .clkr = { 1857 .enable_reg = 0x1700c, 1858 .enable_mask = BIT(0), 1859 .hw.init = &(struct clk_init_data){ 1860 .name = "gcc_disp_ahb_clk", 1861 .flags = CLK_IS_CRITICAL, 1862 .ops = &clk_branch2_ops, 1863 }, 1864 }, 1865 }; 1866 1867 static struct clk_regmap_div gcc_disp_gpll0_clk_src = { 1868 .reg = 0x17058, 1869 .shift = 0, 1870 .width = 2, 1871 .clkr.hw.init = &(struct clk_init_data) { 1872 .name = "gcc_disp_gpll0_clk_src", 1873 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 1874 .num_parents = 1, 1875 .ops = &clk_regmap_div_ops, 1876 }, 1877 }; 1878 1879 static struct clk_branch gcc_disp_gpll0_div_clk_src = { 1880 .halt_check = BRANCH_HALT_DELAY, 1881 .clkr = { 1882 .enable_reg = 0x79004, 1883 .enable_mask = BIT(20), 1884 .hw.init = &(struct clk_init_data){ 1885 .name = "gcc_disp_gpll0_div_clk_src", 1886 .parent_hws = (const struct clk_hw *[]) 1887 { &gcc_disp_gpll0_clk_src.clkr.hw }, 1888 .num_parents = 1, 1889 .flags = CLK_SET_RATE_PARENT, 1890 .ops = &clk_branch2_ops, 1891 }, 1892 }, 1893 }; 1894 1895 static struct clk_branch gcc_disp_hf_axi_clk = { 1896 .halt_reg = 0x17020, 1897 .halt_check = BRANCH_HALT, 1898 .hwcg_reg = 0x17020, 1899 .hwcg_bit = 1, 1900 .clkr = { 1901 .enable_reg = 0x17020, 1902 .enable_mask = BIT(0), 1903 .hw.init = &(struct clk_init_data){ 1904 .name = "gcc_disp_hf_axi_clk", 1905 .ops = &clk_branch2_ops, 1906 }, 1907 }, 1908 }; 1909 1910 static struct clk_branch gcc_disp_throttle_core_clk = { 1911 .halt_reg = 0x17064, 1912 .halt_check = BRANCH_HALT_VOTED, 1913 .hwcg_reg = 0x17064, 1914 .hwcg_bit = 1, 1915 .clkr = { 1916 .enable_reg = 0x7900c, 1917 .enable_mask = BIT(5), 1918 .hw.init = &(struct clk_init_data){ 1919 .name = "gcc_disp_throttle_core_clk", 1920 .ops = &clk_branch2_ops, 1921 }, 1922 }, 1923 }; 1924 1925 static struct clk_branch gcc_disp_xo_clk = { 1926 .halt_reg = 0x1702c, 1927 .halt_check = BRANCH_HALT, 1928 .clkr = { 1929 .enable_reg = 0x1702c, 1930 .enable_mask = BIT(0), 1931 .hw.init = &(struct clk_init_data){ 1932 .name = "gcc_disp_xo_clk", 1933 .flags = CLK_IS_CRITICAL, 1934 .ops = &clk_branch2_ops, 1935 }, 1936 }, 1937 }; 1938 1939 static struct clk_branch gcc_gp1_clk = { 1940 .halt_reg = 0x4d000, 1941 .halt_check = BRANCH_HALT, 1942 .clkr = { 1943 .enable_reg = 0x4d000, 1944 .enable_mask = BIT(0), 1945 .hw.init = &(struct clk_init_data){ 1946 .name = "gcc_gp1_clk", 1947 .parent_hws = (const struct clk_hw *[]) 1948 { &gcc_gp1_clk_src.clkr.hw }, 1949 .num_parents = 1, 1950 .flags = CLK_SET_RATE_PARENT, 1951 .ops = &clk_branch2_ops, 1952 }, 1953 }, 1954 }; 1955 1956 static struct clk_branch gcc_gp2_clk = { 1957 .halt_reg = 0x4e000, 1958 .halt_check = BRANCH_HALT, 1959 .clkr = { 1960 .enable_reg = 0x4e000, 1961 .enable_mask = BIT(0), 1962 .hw.init = &(struct clk_init_data){ 1963 .name = "gcc_gp2_clk", 1964 .parent_hws = (const struct clk_hw *[]) 1965 { &gcc_gp2_clk_src.clkr.hw }, 1966 .num_parents = 1, 1967 .flags = CLK_SET_RATE_PARENT, 1968 .ops = &clk_branch2_ops, 1969 }, 1970 }, 1971 }; 1972 1973 static struct clk_branch gcc_gp3_clk = { 1974 .halt_reg = 0x4f000, 1975 .halt_check = BRANCH_HALT, 1976 .clkr = { 1977 .enable_reg = 0x4f000, 1978 .enable_mask = BIT(0), 1979 .hw.init = &(struct clk_init_data){ 1980 .name = "gcc_gp3_clk", 1981 .parent_hws = (const struct clk_hw *[]) 1982 { &gcc_gp3_clk_src.clkr.hw }, 1983 .num_parents = 1, 1984 .flags = CLK_SET_RATE_PARENT, 1985 .ops = &clk_branch2_ops, 1986 }, 1987 }, 1988 }; 1989 1990 static struct clk_branch gcc_gpu_cfg_ahb_clk = { 1991 .halt_reg = 0x36004, 1992 .halt_check = BRANCH_HALT, 1993 .hwcg_reg = 0x36004, 1994 .hwcg_bit = 1, 1995 .clkr = { 1996 .enable_reg = 0x36004, 1997 .enable_mask = BIT(0), 1998 .hw.init = &(struct clk_init_data){ 1999 .name = "gcc_gpu_cfg_ahb_clk", 2000 .flags = CLK_IS_CRITICAL, 2001 .ops = &clk_branch2_ops, 2002 }, 2003 }, 2004 }; 2005 2006 static struct clk_branch gcc_gpu_gpll0_clk_src = { 2007 .halt_check = BRANCH_HALT_DELAY, 2008 .clkr = { 2009 .enable_reg = 0x79004, 2010 .enable_mask = BIT(15), 2011 .hw.init = &(struct clk_init_data){ 2012 .name = "gcc_gpu_gpll0_clk_src", 2013 .parent_hws = (const struct clk_hw *[]) 2014 { &gpll0.clkr.hw }, 2015 .num_parents = 1, 2016 .flags = CLK_SET_RATE_PARENT, 2017 .ops = &clk_branch2_ops, 2018 }, 2019 }, 2020 }; 2021 2022 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 2023 .halt_check = BRANCH_HALT_DELAY, 2024 .clkr = { 2025 .enable_reg = 0x79004, 2026 .enable_mask = BIT(16), 2027 .hw.init = &(struct clk_init_data){ 2028 .name = "gcc_gpu_gpll0_div_clk_src", 2029 .parent_hws = (const struct clk_hw *[]) 2030 { &gpll0_out_aux2.clkr.hw }, 2031 .num_parents = 1, 2032 .flags = CLK_SET_RATE_PARENT, 2033 .ops = &clk_branch2_ops, 2034 }, 2035 }, 2036 }; 2037 2038 static struct clk_branch gcc_gpu_iref_clk = { 2039 .halt_reg = 0x36100, 2040 .halt_check = BRANCH_HALT_DELAY, 2041 .clkr = { 2042 .enable_reg = 0x36100, 2043 .enable_mask = BIT(0), 2044 .hw.init = &(struct clk_init_data){ 2045 .name = "gcc_gpu_iref_clk", 2046 .ops = &clk_branch2_ops, 2047 }, 2048 }, 2049 }; 2050 2051 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 2052 .halt_reg = 0x3600c, 2053 .halt_check = BRANCH_VOTED, 2054 .hwcg_reg = 0x3600c, 2055 .hwcg_bit = 1, 2056 .clkr = { 2057 .enable_reg = 0x3600c, 2058 .enable_mask = BIT(0), 2059 .hw.init = &(struct clk_init_data){ 2060 .name = "gcc_gpu_memnoc_gfx_clk", 2061 .ops = &clk_branch2_ops, 2062 }, 2063 }, 2064 }; 2065 2066 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2067 .halt_reg = 0x36018, 2068 .halt_check = BRANCH_HALT, 2069 .clkr = { 2070 .enable_reg = 0x36018, 2071 .enable_mask = BIT(0), 2072 .hw.init = &(struct clk_init_data){ 2073 .name = "gcc_gpu_snoc_dvm_gfx_clk", 2074 .ops = &clk_branch2_ops, 2075 }, 2076 }, 2077 }; 2078 2079 static struct clk_branch gcc_gpu_throttle_core_clk = { 2080 .halt_reg = 0x36048, 2081 .halt_check = BRANCH_HALT_VOTED, 2082 .hwcg_reg = 0x36048, 2083 .hwcg_bit = 1, 2084 .clkr = { 2085 .enable_reg = 0x79004, 2086 .enable_mask = BIT(31), 2087 .hw.init = &(struct clk_init_data){ 2088 .name = "gcc_gpu_throttle_core_clk", 2089 .flags = CLK_SET_RATE_PARENT, 2090 .ops = &clk_branch2_ops, 2091 }, 2092 }, 2093 }; 2094 2095 static struct clk_branch gcc_pdm2_clk = { 2096 .halt_reg = 0x2000c, 2097 .halt_check = BRANCH_HALT, 2098 .clkr = { 2099 .enable_reg = 0x2000c, 2100 .enable_mask = BIT(0), 2101 .hw.init = &(struct clk_init_data){ 2102 .name = "gcc_pdm2_clk", 2103 .parent_hws = (const struct clk_hw *[]) 2104 { &gcc_pdm2_clk_src.clkr.hw }, 2105 .num_parents = 1, 2106 .flags = CLK_SET_RATE_PARENT, 2107 .ops = &clk_branch2_ops, 2108 }, 2109 }, 2110 }; 2111 2112 static struct clk_branch gcc_pdm_ahb_clk = { 2113 .halt_reg = 0x20004, 2114 .halt_check = BRANCH_HALT, 2115 .hwcg_reg = 0x20004, 2116 .hwcg_bit = 1, 2117 .clkr = { 2118 .enable_reg = 0x20004, 2119 .enable_mask = BIT(0), 2120 .hw.init = &(struct clk_init_data){ 2121 .name = "gcc_pdm_ahb_clk", 2122 .ops = &clk_branch2_ops, 2123 }, 2124 }, 2125 }; 2126 2127 static struct clk_branch gcc_pdm_xo4_clk = { 2128 .halt_reg = 0x20008, 2129 .halt_check = BRANCH_HALT, 2130 .clkr = { 2131 .enable_reg = 0x20008, 2132 .enable_mask = BIT(0), 2133 .hw.init = &(struct clk_init_data){ 2134 .name = "gcc_pdm_xo4_clk", 2135 .ops = &clk_branch2_ops, 2136 }, 2137 }, 2138 }; 2139 2140 static struct clk_branch gcc_pwm0_xo512_clk = { 2141 .halt_reg = 0x2002c, 2142 .halt_check = BRANCH_HALT, 2143 .clkr = { 2144 .enable_reg = 0x2002c, 2145 .enable_mask = BIT(0), 2146 .hw.init = &(struct clk_init_data){ 2147 .name = "gcc_pwm0_xo512_clk", 2148 .ops = &clk_branch2_ops, 2149 }, 2150 }, 2151 }; 2152 2153 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2154 .halt_reg = 0x17014, 2155 .halt_check = BRANCH_HALT_VOTED, 2156 .hwcg_reg = 0x17014, 2157 .hwcg_bit = 1, 2158 .clkr = { 2159 .enable_reg = 0x7900c, 2160 .enable_mask = BIT(0), 2161 .hw.init = &(struct clk_init_data){ 2162 .name = "gcc_qmip_camera_nrt_ahb_clk", 2163 .ops = &clk_branch2_ops, 2164 }, 2165 }, 2166 }; 2167 2168 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2169 .halt_reg = 0x17060, 2170 .halt_check = BRANCH_HALT_VOTED, 2171 .hwcg_reg = 0x17060, 2172 .hwcg_bit = 1, 2173 .clkr = { 2174 .enable_reg = 0x7900c, 2175 .enable_mask = BIT(2), 2176 .hw.init = &(struct clk_init_data){ 2177 .name = "gcc_qmip_camera_rt_ahb_clk", 2178 .ops = &clk_branch2_ops, 2179 }, 2180 }, 2181 }; 2182 2183 static struct clk_branch gcc_qmip_disp_ahb_clk = { 2184 .halt_reg = 0x17018, 2185 .halt_check = BRANCH_HALT_VOTED, 2186 .hwcg_reg = 0x17018, 2187 .hwcg_bit = 1, 2188 .clkr = { 2189 .enable_reg = 0x7900c, 2190 .enable_mask = BIT(1), 2191 .hw.init = &(struct clk_init_data){ 2192 .name = "gcc_qmip_disp_ahb_clk", 2193 .ops = &clk_branch2_ops, 2194 }, 2195 }, 2196 }; 2197 2198 static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = { 2199 .halt_reg = 0x36040, 2200 .halt_check = BRANCH_HALT_VOTED, 2201 .hwcg_reg = 0x36040, 2202 .hwcg_bit = 1, 2203 .clkr = { 2204 .enable_reg = 0x7900c, 2205 .enable_mask = BIT(4), 2206 .hw.init = &(struct clk_init_data){ 2207 .name = "gcc_qmip_gpu_cfg_ahb_clk", 2208 .ops = &clk_branch2_ops, 2209 }, 2210 }, 2211 }; 2212 2213 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2214 .halt_reg = 0x17010, 2215 .halt_check = BRANCH_HALT_VOTED, 2216 .hwcg_reg = 0x17010, 2217 .hwcg_bit = 1, 2218 .clkr = { 2219 .enable_reg = 0x79004, 2220 .enable_mask = BIT(25), 2221 .hw.init = &(struct clk_init_data){ 2222 .name = "gcc_qmip_video_vcodec_ahb_clk", 2223 .ops = &clk_branch2_ops, 2224 }, 2225 }, 2226 }; 2227 2228 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2229 .halt_reg = 0x1f014, 2230 .halt_check = BRANCH_HALT_VOTED, 2231 .clkr = { 2232 .enable_reg = 0x7900c, 2233 .enable_mask = BIT(9), 2234 .hw.init = &(struct clk_init_data){ 2235 .name = "gcc_qupv3_wrap0_core_2x_clk", 2236 .ops = &clk_branch2_ops, 2237 }, 2238 }, 2239 }; 2240 2241 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2242 .halt_reg = 0x1f00c, 2243 .halt_check = BRANCH_HALT_VOTED, 2244 .clkr = { 2245 .enable_reg = 0x7900c, 2246 .enable_mask = BIT(8), 2247 .hw.init = &(struct clk_init_data){ 2248 .name = "gcc_qupv3_wrap0_core_clk", 2249 .ops = &clk_branch2_ops, 2250 }, 2251 }, 2252 }; 2253 2254 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2255 .halt_reg = 0x1f144, 2256 .halt_check = BRANCH_HALT_VOTED, 2257 .clkr = { 2258 .enable_reg = 0x7900c, 2259 .enable_mask = BIT(10), 2260 .hw.init = &(struct clk_init_data){ 2261 .name = "gcc_qupv3_wrap0_s0_clk", 2262 .parent_hws = (const struct clk_hw *[]) 2263 { &gcc_qupv3_wrap0_s0_clk_src.clkr.hw }, 2264 .num_parents = 1, 2265 .flags = CLK_SET_RATE_PARENT, 2266 .ops = &clk_branch2_ops, 2267 }, 2268 }, 2269 }; 2270 2271 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2272 .halt_reg = 0x1f274, 2273 .halt_check = BRANCH_HALT_VOTED, 2274 .clkr = { 2275 .enable_reg = 0x7900c, 2276 .enable_mask = BIT(11), 2277 .hw.init = &(struct clk_init_data){ 2278 .name = "gcc_qupv3_wrap0_s1_clk", 2279 .parent_hws = (const struct clk_hw *[]) 2280 { &gcc_qupv3_wrap0_s1_clk_src.clkr.hw }, 2281 .num_parents = 1, 2282 .flags = CLK_SET_RATE_PARENT, 2283 .ops = &clk_branch2_ops, 2284 }, 2285 }, 2286 }; 2287 2288 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2289 .halt_reg = 0x1f3a4, 2290 .halt_check = BRANCH_HALT_VOTED, 2291 .clkr = { 2292 .enable_reg = 0x7900c, 2293 .enable_mask = BIT(12), 2294 .hw.init = &(struct clk_init_data){ 2295 .name = "gcc_qupv3_wrap0_s2_clk", 2296 .parent_hws = (const struct clk_hw *[]) 2297 { &gcc_qupv3_wrap0_s2_clk_src.clkr.hw }, 2298 .num_parents = 1, 2299 .flags = CLK_SET_RATE_PARENT, 2300 .ops = &clk_branch2_ops, 2301 }, 2302 }, 2303 }; 2304 2305 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2306 .halt_reg = 0x1f4d4, 2307 .halt_check = BRANCH_HALT_VOTED, 2308 .clkr = { 2309 .enable_reg = 0x7900c, 2310 .enable_mask = BIT(13), 2311 .hw.init = &(struct clk_init_data){ 2312 .name = "gcc_qupv3_wrap0_s3_clk", 2313 .parent_hws = (const struct clk_hw *[]) 2314 { &gcc_qupv3_wrap0_s3_clk_src.clkr.hw }, 2315 .num_parents = 1, 2316 .flags = CLK_SET_RATE_PARENT, 2317 .ops = &clk_branch2_ops, 2318 }, 2319 }, 2320 }; 2321 2322 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2323 .halt_reg = 0x1f604, 2324 .halt_check = BRANCH_HALT_VOTED, 2325 .clkr = { 2326 .enable_reg = 0x7900c, 2327 .enable_mask = BIT(14), 2328 .hw.init = &(struct clk_init_data){ 2329 .name = "gcc_qupv3_wrap0_s4_clk", 2330 .parent_hws = (const struct clk_hw *[]) 2331 { &gcc_qupv3_wrap0_s4_clk_src.clkr.hw }, 2332 .num_parents = 1, 2333 .flags = CLK_SET_RATE_PARENT, 2334 .ops = &clk_branch2_ops, 2335 }, 2336 }, 2337 }; 2338 2339 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2340 .halt_reg = 0x1f734, 2341 .halt_check = BRANCH_HALT_VOTED, 2342 .clkr = { 2343 .enable_reg = 0x7900c, 2344 .enable_mask = BIT(15), 2345 .hw.init = &(struct clk_init_data){ 2346 .name = "gcc_qupv3_wrap0_s5_clk", 2347 .parent_hws = (const struct clk_hw *[]) 2348 { &gcc_qupv3_wrap0_s5_clk_src.clkr.hw }, 2349 .num_parents = 1, 2350 .flags = CLK_SET_RATE_PARENT, 2351 .ops = &clk_branch2_ops, 2352 }, 2353 }, 2354 }; 2355 2356 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2357 .halt_reg = 0x1f004, 2358 .halt_check = BRANCH_HALT_VOTED, 2359 .hwcg_reg = 0x1f004, 2360 .hwcg_bit = 1, 2361 .clkr = { 2362 .enable_reg = 0x7900c, 2363 .enable_mask = BIT(6), 2364 .hw.init = &(struct clk_init_data){ 2365 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2366 .ops = &clk_branch2_ops, 2367 }, 2368 }, 2369 }; 2370 2371 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2372 .halt_reg = 0x1f008, 2373 .halt_check = BRANCH_HALT_VOTED, 2374 .hwcg_reg = 0x1f008, 2375 .hwcg_bit = 1, 2376 .clkr = { 2377 .enable_reg = 0x7900c, 2378 .enable_mask = BIT(7), 2379 .hw.init = &(struct clk_init_data){ 2380 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2381 .ops = &clk_branch2_ops, 2382 }, 2383 }, 2384 }; 2385 2386 static struct clk_branch gcc_sdcc1_ahb_clk = { 2387 .halt_reg = 0x38008, 2388 .halt_check = BRANCH_HALT, 2389 .clkr = { 2390 .enable_reg = 0x38008, 2391 .enable_mask = BIT(0), 2392 .hw.init = &(struct clk_init_data){ 2393 .name = "gcc_sdcc1_ahb_clk", 2394 .ops = &clk_branch2_ops, 2395 }, 2396 }, 2397 }; 2398 2399 static struct clk_branch gcc_sdcc1_apps_clk = { 2400 .halt_reg = 0x38004, 2401 .halt_check = BRANCH_HALT, 2402 .clkr = { 2403 .enable_reg = 0x38004, 2404 .enable_mask = BIT(0), 2405 .hw.init = &(struct clk_init_data){ 2406 .name = "gcc_sdcc1_apps_clk", 2407 .parent_hws = (const struct clk_hw *[]) 2408 { &gcc_sdcc1_apps_clk_src.clkr.hw }, 2409 .num_parents = 1, 2410 .flags = CLK_SET_RATE_PARENT, 2411 .ops = &clk_branch2_ops, 2412 }, 2413 }, 2414 }; 2415 2416 static struct clk_branch gcc_sdcc1_ice_core_clk = { 2417 .halt_reg = 0x3800c, 2418 .halt_check = BRANCH_HALT, 2419 .hwcg_reg = 0x3800c, 2420 .hwcg_bit = 1, 2421 .clkr = { 2422 .enable_reg = 0x3800c, 2423 .enable_mask = BIT(0), 2424 .hw.init = &(struct clk_init_data){ 2425 .name = "gcc_sdcc1_ice_core_clk", 2426 .parent_hws = (const struct clk_hw *[]) 2427 { &gcc_sdcc1_ice_core_clk_src.clkr.hw }, 2428 .num_parents = 1, 2429 .flags = CLK_SET_RATE_PARENT, 2430 .ops = &clk_branch2_ops, 2431 }, 2432 }, 2433 }; 2434 2435 static struct clk_branch gcc_sdcc2_ahb_clk = { 2436 .halt_reg = 0x1e008, 2437 .halt_check = BRANCH_HALT, 2438 .clkr = { 2439 .enable_reg = 0x1e008, 2440 .enable_mask = BIT(0), 2441 .hw.init = &(struct clk_init_data){ 2442 .name = "gcc_sdcc2_ahb_clk", 2443 .ops = &clk_branch2_ops, 2444 }, 2445 }, 2446 }; 2447 2448 static struct clk_branch gcc_sdcc2_apps_clk = { 2449 .halt_reg = 0x1e004, 2450 .halt_check = BRANCH_HALT, 2451 .clkr = { 2452 .enable_reg = 0x1e004, 2453 .enable_mask = BIT(0), 2454 .hw.init = &(struct clk_init_data){ 2455 .name = "gcc_sdcc2_apps_clk", 2456 .parent_hws = (const struct clk_hw *[]) 2457 { &gcc_sdcc2_apps_clk_src.clkr.hw }, 2458 .num_parents = 1, 2459 .flags = CLK_SET_RATE_PARENT, 2460 .ops = &clk_branch2_ops, 2461 }, 2462 }, 2463 }; 2464 2465 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 2466 .halt_reg = 0x2b06c, 2467 .halt_check = BRANCH_HALT_VOTED, 2468 .hwcg_reg = 0x2b06c, 2469 .hwcg_bit = 1, 2470 .clkr = { 2471 .enable_reg = 0x79004, 2472 .enable_mask = BIT(0), 2473 .hw.init = &(struct clk_init_data){ 2474 .name = "gcc_sys_noc_cpuss_ahb_clk", 2475 .flags = CLK_IS_CRITICAL, 2476 .ops = &clk_branch2_ops, 2477 }, 2478 }, 2479 }; 2480 2481 static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { 2482 .halt_reg = 0x1a080, 2483 .halt_check = BRANCH_HALT, 2484 .hwcg_reg = 0x1a080, 2485 .hwcg_bit = 1, 2486 .clkr = { 2487 .enable_reg = 0x1a080, 2488 .enable_mask = BIT(0), 2489 .hw.init = &(struct clk_init_data){ 2490 .name = "gcc_sys_noc_usb3_prim_axi_clk", 2491 .parent_hws = (const struct clk_hw *[]) 2492 { &gcc_usb30_prim_master_clk_src.clkr.hw }, 2493 .num_parents = 1, 2494 .flags = CLK_SET_RATE_PARENT, 2495 .ops = &clk_branch2_ops, 2496 }, 2497 }, 2498 }; 2499 2500 static struct clk_branch gcc_usb30_prim_master_clk = { 2501 .halt_reg = 0x1a010, 2502 .halt_check = BRANCH_HALT, 2503 .clkr = { 2504 .enable_reg = 0x1a010, 2505 .enable_mask = BIT(0), 2506 .hw.init = &(struct clk_init_data){ 2507 .name = "gcc_usb30_prim_master_clk", 2508 .parent_hws = (const struct clk_hw *[]) 2509 { &gcc_usb30_prim_master_clk_src.clkr.hw }, 2510 .num_parents = 1, 2511 .flags = CLK_SET_RATE_PARENT, 2512 .ops = &clk_branch2_ops, 2513 }, 2514 }, 2515 }; 2516 2517 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2518 .halt_reg = 0x1a018, 2519 .halt_check = BRANCH_HALT, 2520 .clkr = { 2521 .enable_reg = 0x1a018, 2522 .enable_mask = BIT(0), 2523 .hw.init = &(struct clk_init_data){ 2524 .name = "gcc_usb30_prim_mock_utmi_clk", 2525 .parent_hws = (const struct clk_hw *[]) 2526 { &gcc_usb30_prim_mock_utmi_postdiv.clkr.hw }, 2527 .num_parents = 1, 2528 .flags = CLK_SET_RATE_PARENT, 2529 .ops = &clk_branch2_ops, 2530 }, 2531 }, 2532 }; 2533 2534 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2535 .halt_reg = 0x1a014, 2536 .halt_check = BRANCH_HALT, 2537 .clkr = { 2538 .enable_reg = 0x1a014, 2539 .enable_mask = BIT(0), 2540 .hw.init = &(struct clk_init_data){ 2541 .name = "gcc_usb30_prim_sleep_clk", 2542 .ops = &clk_branch2_ops, 2543 }, 2544 }, 2545 }; 2546 2547 static struct clk_branch gcc_usb3_prim_clkref_clk = { 2548 .halt_reg = 0x9f000, 2549 .halt_check = BRANCH_HALT, 2550 .clkr = { 2551 .enable_reg = 0x9f000, 2552 .enable_mask = BIT(0), 2553 .hw.init = &(struct clk_init_data){ 2554 .name = "gcc_usb3_prim_clkref_clk", 2555 .ops = &clk_branch2_ops, 2556 }, 2557 }, 2558 }; 2559 2560 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2561 .halt_reg = 0x1a054, 2562 .halt_check = BRANCH_HALT, 2563 .clkr = { 2564 .enable_reg = 0x1a054, 2565 .enable_mask = BIT(0), 2566 .hw.init = &(struct clk_init_data){ 2567 .name = "gcc_usb3_prim_phy_com_aux_clk", 2568 .parent_hws = (const struct clk_hw *[]) 2569 { &gcc_usb3_prim_phy_aux_clk_src.clkr.hw }, 2570 .num_parents = 1, 2571 .flags = CLK_SET_RATE_PARENT, 2572 .ops = &clk_branch2_ops, 2573 }, 2574 }, 2575 }; 2576 2577 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2578 .halt_reg = 0x1a058, 2579 .halt_check = BRANCH_HALT_SKIP, 2580 .hwcg_reg = 0x1a058, 2581 .hwcg_bit = 1, 2582 .clkr = { 2583 .enable_reg = 0x1a058, 2584 .enable_mask = BIT(0), 2585 .hw.init = &(struct clk_init_data){ 2586 .name = "gcc_usb3_prim_phy_pipe_clk", 2587 .ops = &clk_branch2_ops, 2588 }, 2589 }, 2590 }; 2591 2592 static struct clk_branch gcc_vcodec0_axi_clk = { 2593 .halt_reg = 0x6e008, 2594 .halt_check = BRANCH_HALT, 2595 .clkr = { 2596 .enable_reg = 0x6e008, 2597 .enable_mask = BIT(0), 2598 .hw.init = &(struct clk_init_data){ 2599 .name = "gcc_vcodec0_axi_clk", 2600 .ops = &clk_branch2_ops, 2601 }, 2602 }, 2603 }; 2604 2605 static struct clk_branch gcc_venus_ahb_clk = { 2606 .halt_reg = 0x6e010, 2607 .halt_check = BRANCH_HALT, 2608 .clkr = { 2609 .enable_reg = 0x6e010, 2610 .enable_mask = BIT(0), 2611 .hw.init = &(struct clk_init_data){ 2612 .name = "gcc_venus_ahb_clk", 2613 .ops = &clk_branch2_ops, 2614 }, 2615 }, 2616 }; 2617 2618 static struct clk_branch gcc_venus_ctl_axi_clk = { 2619 .halt_reg = 0x6e004, 2620 .halt_check = BRANCH_HALT, 2621 .clkr = { 2622 .enable_reg = 0x6e004, 2623 .enable_mask = BIT(0), 2624 .hw.init = &(struct clk_init_data){ 2625 .name = "gcc_venus_ctl_axi_clk", 2626 .ops = &clk_branch2_ops, 2627 }, 2628 }, 2629 }; 2630 2631 static struct clk_branch gcc_video_ahb_clk = { 2632 .halt_reg = 0x17004, 2633 .halt_check = BRANCH_HALT, 2634 .hwcg_reg = 0x17004, 2635 .hwcg_bit = 1, 2636 .clkr = { 2637 .enable_reg = 0x17004, 2638 .enable_mask = BIT(0), 2639 .hw.init = &(struct clk_init_data){ 2640 .name = "gcc_video_ahb_clk", 2641 .ops = &clk_branch2_ops, 2642 }, 2643 }, 2644 }; 2645 2646 static struct clk_branch gcc_video_axi0_clk = { 2647 .halt_reg = 0x1701c, 2648 .halt_check = BRANCH_HALT, 2649 .hwcg_reg = 0x1701c, 2650 .hwcg_bit = 1, 2651 .clkr = { 2652 .enable_reg = 0x1701c, 2653 .enable_mask = BIT(0), 2654 .hw.init = &(struct clk_init_data){ 2655 .name = "gcc_video_axi0_clk", 2656 .ops = &clk_branch2_ops, 2657 }, 2658 }, 2659 }; 2660 2661 static struct clk_branch gcc_video_throttle_core_clk = { 2662 .halt_reg = 0x17068, 2663 .halt_check = BRANCH_HALT_VOTED, 2664 .hwcg_reg = 0x17068, 2665 .hwcg_bit = 1, 2666 .clkr = { 2667 .enable_reg = 0x79004, 2668 .enable_mask = BIT(28), 2669 .hw.init = &(struct clk_init_data){ 2670 .name = "gcc_video_throttle_core_clk", 2671 .ops = &clk_branch2_ops, 2672 }, 2673 }, 2674 }; 2675 2676 static struct clk_branch gcc_video_vcodec0_sys_clk = { 2677 .halt_reg = 0x580a4, 2678 .halt_check = BRANCH_HALT_DELAY, 2679 .hwcg_reg = 0x580a4, 2680 .hwcg_bit = 1, 2681 .clkr = { 2682 .enable_reg = 0x580a4, 2683 .enable_mask = BIT(0), 2684 .hw.init = &(struct clk_init_data){ 2685 .name = "gcc_video_vcodec0_sys_clk", 2686 .parent_hws = (const struct clk_hw *[]) 2687 { &gcc_video_venus_clk_src.clkr.hw }, 2688 .num_parents = 1, 2689 .flags = CLK_SET_RATE_PARENT, 2690 .ops = &clk_branch2_ops, 2691 }, 2692 }, 2693 }; 2694 2695 static struct clk_branch gcc_video_venus_ctl_clk = { 2696 .halt_reg = 0x5808c, 2697 .halt_check = BRANCH_HALT, 2698 .clkr = { 2699 .enable_reg = 0x5808c, 2700 .enable_mask = BIT(0), 2701 .hw.init = &(struct clk_init_data){ 2702 .name = "gcc_video_venus_ctl_clk", 2703 .parent_hws = (const struct clk_hw *[]) 2704 { &gcc_video_venus_clk_src.clkr.hw }, 2705 .num_parents = 1, 2706 .flags = CLK_SET_RATE_PARENT, 2707 .ops = &clk_branch2_ops, 2708 }, 2709 }, 2710 }; 2711 2712 static struct clk_branch gcc_video_xo_clk = { 2713 .halt_reg = 0x17024, 2714 .halt_check = BRANCH_HALT, 2715 .clkr = { 2716 .enable_reg = 0x17024, 2717 .enable_mask = BIT(0), 2718 .hw.init = &(struct clk_init_data){ 2719 .name = "gcc_video_xo_clk", 2720 .ops = &clk_branch2_ops, 2721 }, 2722 }, 2723 }; 2724 2725 static struct gdsc gcc_camss_top_gdsc = { 2726 .gdscr = 0x58004, 2727 .pd = { 2728 .name = "gcc_camss_top", 2729 }, 2730 .pwrsts = PWRSTS_OFF_ON, 2731 }; 2732 2733 static struct gdsc gcc_usb30_prim_gdsc = { 2734 .gdscr = 0x1a004, 2735 .pd = { 2736 .name = "gcc_usb30_prim", 2737 }, 2738 .pwrsts = PWRSTS_OFF_ON, 2739 }; 2740 2741 static struct gdsc gcc_vcodec0_gdsc = { 2742 .gdscr = 0x58098, 2743 .pd = { 2744 .name = "gcc_vcodec0", 2745 }, 2746 .pwrsts = PWRSTS_OFF_ON, 2747 }; 2748 2749 static struct gdsc gcc_venus_gdsc = { 2750 .gdscr = 0x5807c, 2751 .pd = { 2752 .name = "gcc_venus", 2753 }, 2754 .pwrsts = PWRSTS_OFF_ON, 2755 }; 2756 2757 static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = { 2758 .gdscr = 0x7d060, 2759 .pd = { 2760 .name = "hlos1_vote_turing_mmu_tbu1", 2761 }, 2762 .pwrsts = PWRSTS_OFF_ON, 2763 .flags = VOTABLE, 2764 }; 2765 2766 static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { 2767 .gdscr = 0x7d07c, 2768 .pd = { 2769 .name = "hlos1_vote_turing_mmu_tbu0", 2770 }, 2771 .pwrsts = PWRSTS_OFF_ON, 2772 .flags = VOTABLE, 2773 }; 2774 2775 static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = { 2776 .gdscr = 0x7d074, 2777 .pd = { 2778 .name = "hlos1_vote_mm_snoc_mmu_tbu_rt", 2779 }, 2780 .pwrsts = PWRSTS_OFF_ON, 2781 .flags = VOTABLE, 2782 }; 2783 2784 static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = { 2785 .gdscr = 0x7d078, 2786 .pd = { 2787 .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt", 2788 }, 2789 .pwrsts = PWRSTS_OFF_ON, 2790 .flags = VOTABLE, 2791 }; 2792 2793 static struct clk_regmap *gcc_qcm2290_clocks[] = { 2794 [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr, 2795 [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr, 2796 [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr, 2797 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2798 [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, 2799 [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, 2800 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 2801 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 2802 [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, 2803 [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, 2804 [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr, 2805 [GCC_CAMSS_CAMNOC_NTS_XO_CLK] = &gcc_camss_camnoc_nts_xo_clk.clkr, 2806 [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr, 2807 [GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr, 2808 [GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr, 2809 [GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr, 2810 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 2811 [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr, 2812 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, 2813 [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr, 2814 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 2815 [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr, 2816 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 2817 [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr, 2818 [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, 2819 [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr, 2820 [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr, 2821 [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr, 2822 [GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr, 2823 [GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr, 2824 [GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr, 2825 [GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr, 2826 [GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr, 2827 [GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr, 2828 [GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr, 2829 [GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr, 2830 [GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr, 2831 [GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr, 2832 [GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr, 2833 [GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr, 2834 [GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr, 2835 [GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr, 2836 [GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr, 2837 [GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr, 2838 [GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr, 2839 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 2840 [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, 2841 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2842 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, 2843 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 2844 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 2845 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 2846 [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, 2847 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 2848 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2849 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2850 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2851 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2852 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2853 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2854 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 2855 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 2856 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 2857 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, 2858 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 2859 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 2860 [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, 2861 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2862 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 2863 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2864 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2865 [GCC_PWM0_XO512_CLK] = &gcc_pwm0_xo512_clk.clkr, 2866 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 2867 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 2868 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 2869 [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr, 2870 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 2871 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 2872 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 2873 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 2874 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 2875 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 2876 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 2877 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 2878 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 2879 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 2880 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 2881 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 2882 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 2883 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 2884 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 2885 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 2886 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 2887 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2888 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2889 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 2890 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 2891 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 2892 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2893 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2894 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 2895 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 2896 [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, 2897 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 2898 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 2899 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 2900 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 2901 &gcc_usb30_prim_mock_utmi_clk_src.clkr, 2902 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV] = 2903 &gcc_usb30_prim_mock_utmi_postdiv.clkr, 2904 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 2905 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 2906 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 2907 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 2908 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 2909 [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr, 2910 [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr, 2911 [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr, 2912 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 2913 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 2914 [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, 2915 [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr, 2916 [GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr, 2917 [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr, 2918 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 2919 [GPLL0] = &gpll0.clkr, 2920 [GPLL0_OUT_AUX2] = &gpll0_out_aux2.clkr, 2921 [GPLL1] = &gpll1.clkr, 2922 [GPLL10] = &gpll10.clkr, 2923 [GPLL11] = &gpll11.clkr, 2924 [GPLL3] = &gpll3.clkr, 2925 [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr, 2926 [GPLL4] = &gpll4.clkr, 2927 [GPLL5] = &gpll5.clkr, 2928 [GPLL6] = &gpll6.clkr, 2929 [GPLL6_OUT_MAIN] = &gpll6_out_main.clkr, 2930 [GPLL7] = &gpll7.clkr, 2931 [GPLL8] = &gpll8.clkr, 2932 [GPLL8_OUT_MAIN] = &gpll8_out_main.clkr, 2933 [GPLL9] = &gpll9.clkr, 2934 [GPLL9_OUT_MAIN] = &gpll9_out_main.clkr, 2935 }; 2936 2937 static const struct qcom_reset_map gcc_qcm2290_resets[] = { 2938 [GCC_CAMSS_OPE_BCR] = { 0x55000 }, 2939 [GCC_CAMSS_TFE_BCR] = { 0x52000 }, 2940 [GCC_CAMSS_TOP_BCR] = { 0x58000 }, 2941 [GCC_GPU_BCR] = { 0x36000 }, 2942 [GCC_MMSS_BCR] = { 0x17000 }, 2943 [GCC_PDM_BCR] = { 0x20000 }, 2944 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 }, 2945 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, 2946 [GCC_SDCC1_BCR] = { 0x38000 }, 2947 [GCC_SDCC2_BCR] = { 0x1e000 }, 2948 [GCC_USB30_PRIM_BCR] = { 0x1a000 }, 2949 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, 2950 [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, 2951 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, 2952 [GCC_VCODEC0_BCR] = { 0x58094 }, 2953 [GCC_VENUS_BCR] = { 0x58078 }, 2954 [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 }, 2955 }; 2956 2957 static struct gdsc *gcc_qcm2290_gdscs[] = { 2958 [GCC_CAMSS_TOP_GDSC] = &gcc_camss_top_gdsc, 2959 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 2960 [GCC_VCODEC0_GDSC] = &gcc_vcodec0_gdsc, 2961 [GCC_VENUS_GDSC] = &gcc_venus_gdsc, 2962 [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, 2963 [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc, 2964 [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc, 2965 [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc, 2966 }; 2967 2968 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 2969 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 2970 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 2971 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 2972 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 2973 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 2974 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 2975 }; 2976 2977 static const struct regmap_config gcc_qcm2290_regmap_config = { 2978 .reg_bits = 32, 2979 .reg_stride = 4, 2980 .val_bits = 32, 2981 .max_register = 0xc7000, 2982 .fast_io = true, 2983 }; 2984 2985 static const struct qcom_cc_desc gcc_qcm2290_desc = { 2986 .config = &gcc_qcm2290_regmap_config, 2987 .clks = gcc_qcm2290_clocks, 2988 .num_clks = ARRAY_SIZE(gcc_qcm2290_clocks), 2989 .resets = gcc_qcm2290_resets, 2990 .num_resets = ARRAY_SIZE(gcc_qcm2290_resets), 2991 .gdscs = gcc_qcm2290_gdscs, 2992 .num_gdscs = ARRAY_SIZE(gcc_qcm2290_gdscs), 2993 }; 2994 2995 static const struct of_device_id gcc_qcm2290_match_table[] = { 2996 { .compatible = "qcom,gcc-qcm2290" }, 2997 { } 2998 }; 2999 MODULE_DEVICE_TABLE(of, gcc_qcm2290_match_table); 3000 3001 static int gcc_qcm2290_probe(struct platform_device *pdev) 3002 { 3003 struct regmap *regmap; 3004 int ret; 3005 3006 regmap = qcom_cc_map(pdev, &gcc_qcm2290_desc); 3007 if (IS_ERR(regmap)) 3008 return PTR_ERR(regmap); 3009 3010 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3011 ARRAY_SIZE(gcc_dfs_clocks)); 3012 if (ret) 3013 return ret; 3014 3015 clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config); 3016 clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config); 3017 clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config); 3018 clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config); 3019 3020 return qcom_cc_really_probe(pdev, &gcc_qcm2290_desc, regmap); 3021 } 3022 3023 static struct platform_driver gcc_qcm2290_driver = { 3024 .probe = gcc_qcm2290_probe, 3025 .driver = { 3026 .name = "gcc-qcm2290", 3027 .of_match_table = gcc_qcm2290_match_table, 3028 }, 3029 }; 3030 3031 static int __init gcc_qcm2290_init(void) 3032 { 3033 return platform_driver_register(&gcc_qcm2290_driver); 3034 } 3035 subsys_initcall(gcc_qcm2290_init); 3036 3037 static void __exit gcc_qcm2290_exit(void) 3038 { 3039 platform_driver_unregister(&gcc_qcm2290_driver); 3040 } 3041 module_exit(gcc_qcm2290_exit); 3042 3043 MODULE_DESCRIPTION("QTI GCC QCM2290 Driver"); 3044 MODULE_LICENSE("GPL v2"); 3045