1496d1a13SShawn Guo // SPDX-License-Identifier: GPL-2.0-only 2496d1a13SShawn Guo /* 3496d1a13SShawn Guo * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4496d1a13SShawn Guo */ 5496d1a13SShawn Guo 6496d1a13SShawn Guo #include <linux/clk-provider.h> 7496d1a13SShawn Guo #include <linux/err.h> 8496d1a13SShawn Guo #include <linux/kernel.h> 9496d1a13SShawn Guo #include <linux/module.h> 10496d1a13SShawn Guo #include <linux/platform_device.h> 11496d1a13SShawn Guo #include <linux/regmap.h> 12496d1a13SShawn Guo 13496d1a13SShawn Guo #include <dt-bindings/clock/qcom,gcc-qcm2290.h> 14496d1a13SShawn Guo 15496d1a13SShawn Guo #include "clk-alpha-pll.h" 16496d1a13SShawn Guo #include "clk-branch.h" 17496d1a13SShawn Guo #include "clk-rcg.h" 18496d1a13SShawn Guo #include "clk-regmap-divider.h" 19496d1a13SShawn Guo #include "common.h" 20496d1a13SShawn Guo #include "gdsc.h" 21496d1a13SShawn Guo #include "reset.h" 22496d1a13SShawn Guo 23496d1a13SShawn Guo enum { 24496d1a13SShawn Guo P_BI_TCXO, 25496d1a13SShawn Guo P_GPLL0_OUT_AUX2, 26496d1a13SShawn Guo P_GPLL0_OUT_EARLY, 27496d1a13SShawn Guo P_GPLL10_OUT_MAIN, 28496d1a13SShawn Guo P_GPLL11_OUT_AUX, 29496d1a13SShawn Guo P_GPLL11_OUT_AUX2, 30496d1a13SShawn Guo P_GPLL11_OUT_MAIN, 31496d1a13SShawn Guo P_GPLL3_OUT_EARLY, 32496d1a13SShawn Guo P_GPLL3_OUT_MAIN, 33496d1a13SShawn Guo P_GPLL4_OUT_MAIN, 34496d1a13SShawn Guo P_GPLL5_OUT_MAIN, 35496d1a13SShawn Guo P_GPLL6_OUT_EARLY, 36496d1a13SShawn Guo P_GPLL6_OUT_MAIN, 37496d1a13SShawn Guo P_GPLL7_OUT_MAIN, 38496d1a13SShawn Guo P_GPLL8_OUT_EARLY, 39496d1a13SShawn Guo P_GPLL8_OUT_MAIN, 40496d1a13SShawn Guo P_GPLL9_OUT_EARLY, 41496d1a13SShawn Guo P_GPLL9_OUT_MAIN, 42496d1a13SShawn Guo P_SLEEP_CLK, 43496d1a13SShawn Guo }; 44496d1a13SShawn Guo 45496d1a13SShawn Guo static const struct pll_vco brammo_vco[] = { 46496d1a13SShawn Guo { 500000000, 1250000000, 0 }, 47496d1a13SShawn Guo }; 48496d1a13SShawn Guo 49496d1a13SShawn Guo static const struct pll_vco default_vco[] = { 50496d1a13SShawn Guo { 500000000, 1000000000, 2 }, 51496d1a13SShawn Guo }; 52496d1a13SShawn Guo 53496d1a13SShawn Guo static const struct pll_vco spark_vco[] = { 54496d1a13SShawn Guo { 750000000, 1500000000, 1 }, 55496d1a13SShawn Guo }; 56496d1a13SShawn Guo 57496d1a13SShawn Guo static struct clk_alpha_pll gpll0 = { 58496d1a13SShawn Guo .offset = 0x0, 59*9e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 60496d1a13SShawn Guo .clkr = { 61496d1a13SShawn Guo .enable_reg = 0x79000, 62496d1a13SShawn Guo .enable_mask = BIT(0), 63496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 64496d1a13SShawn Guo .name = "gpll0", 65496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 66496d1a13SShawn Guo .fw_name = "bi_tcxo", 67496d1a13SShawn Guo }, 68496d1a13SShawn Guo .num_parents = 1, 69496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 70496d1a13SShawn Guo }, 71496d1a13SShawn Guo }, 72496d1a13SShawn Guo }; 73496d1a13SShawn Guo 74496d1a13SShawn Guo static const struct clk_div_table post_div_table_gpll0_out_aux2[] = { 75496d1a13SShawn Guo { 0x1, 2 }, 76496d1a13SShawn Guo { } 77496d1a13SShawn Guo }; 78496d1a13SShawn Guo 79496d1a13SShawn Guo static struct clk_alpha_pll_postdiv gpll0_out_aux2 = { 80496d1a13SShawn Guo .offset = 0x0, 81496d1a13SShawn Guo .post_div_shift = 8, 82496d1a13SShawn Guo .post_div_table = post_div_table_gpll0_out_aux2, 83496d1a13SShawn Guo .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2), 84496d1a13SShawn Guo .width = 4, 85*9e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 86496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 87496d1a13SShawn Guo .name = "gpll0_out_aux2", 88496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 89496d1a13SShawn Guo .num_parents = 1, 90496d1a13SShawn Guo .ops = &clk_alpha_pll_postdiv_ro_ops, 91496d1a13SShawn Guo }, 92496d1a13SShawn Guo }; 93496d1a13SShawn Guo 94496d1a13SShawn Guo static struct clk_alpha_pll gpll1 = { 95496d1a13SShawn Guo .offset = 0x1000, 96*9e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 97496d1a13SShawn Guo .clkr = { 98496d1a13SShawn Guo .enable_reg = 0x79000, 99496d1a13SShawn Guo .enable_mask = BIT(1), 100496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 101496d1a13SShawn Guo .name = "gpll1", 102496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 103496d1a13SShawn Guo .fw_name = "bi_tcxo", 104496d1a13SShawn Guo }, 105496d1a13SShawn Guo .num_parents = 1, 106496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 107496d1a13SShawn Guo }, 108496d1a13SShawn Guo }, 109496d1a13SShawn Guo }; 110496d1a13SShawn Guo 111496d1a13SShawn Guo /* 1152MHz configuration */ 112496d1a13SShawn Guo static const struct alpha_pll_config gpll10_config = { 113496d1a13SShawn Guo .l = 0x3c, 114496d1a13SShawn Guo .alpha = 0x0, 115496d1a13SShawn Guo .vco_val = 0x1 << 20, 116496d1a13SShawn Guo .vco_mask = GENMASK(21, 20), 117496d1a13SShawn Guo .main_output_mask = BIT(0), 118496d1a13SShawn Guo .config_ctl_val = 0x4001055B, 119496d1a13SShawn Guo .test_ctl_hi1_val = 0x1, 120496d1a13SShawn Guo }; 121496d1a13SShawn Guo 122496d1a13SShawn Guo static struct clk_alpha_pll gpll10 = { 123496d1a13SShawn Guo .offset = 0xa000, 124496d1a13SShawn Guo .vco_table = spark_vco, 125496d1a13SShawn Guo .num_vco = ARRAY_SIZE(spark_vco), 126*9e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 127496d1a13SShawn Guo .clkr = { 128496d1a13SShawn Guo .enable_reg = 0x79000, 129496d1a13SShawn Guo .enable_mask = BIT(10), 130496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 131496d1a13SShawn Guo .name = "gpll10", 132496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 133496d1a13SShawn Guo .fw_name = "bi_tcxo", 134496d1a13SShawn Guo }, 135496d1a13SShawn Guo .num_parents = 1, 136496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 137496d1a13SShawn Guo }, 138496d1a13SShawn Guo }, 139496d1a13SShawn Guo }; 140496d1a13SShawn Guo 141496d1a13SShawn Guo /* 532MHz configuration */ 142496d1a13SShawn Guo static const struct alpha_pll_config gpll11_config = { 143496d1a13SShawn Guo .l = 0x1B, 144496d1a13SShawn Guo .alpha = 0x55555555, 145496d1a13SShawn Guo .alpha_hi = 0xB5, 146496d1a13SShawn Guo .alpha_en_mask = BIT(24), 147496d1a13SShawn Guo .vco_val = 0x2 << 20, 148496d1a13SShawn Guo .vco_mask = GENMASK(21, 20), 149496d1a13SShawn Guo .main_output_mask = BIT(0), 150496d1a13SShawn Guo .config_ctl_val = 0x4001055B, 151496d1a13SShawn Guo .test_ctl_hi1_val = 0x1, 152496d1a13SShawn Guo }; 153496d1a13SShawn Guo 154496d1a13SShawn Guo static struct clk_alpha_pll gpll11 = { 155496d1a13SShawn Guo .offset = 0xb000, 156496d1a13SShawn Guo .vco_table = default_vco, 157496d1a13SShawn Guo .num_vco = ARRAY_SIZE(default_vco), 158*9e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 159496d1a13SShawn Guo .flags = SUPPORTS_DYNAMIC_UPDATE, 160496d1a13SShawn Guo .clkr = { 161496d1a13SShawn Guo .enable_reg = 0x79000, 162496d1a13SShawn Guo .enable_mask = BIT(11), 163496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 164496d1a13SShawn Guo .name = "gpll11", 165496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 166496d1a13SShawn Guo .fw_name = "bi_tcxo", 167496d1a13SShawn Guo }, 168496d1a13SShawn Guo .num_parents = 1, 169496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 170496d1a13SShawn Guo }, 171496d1a13SShawn Guo }, 172496d1a13SShawn Guo }; 173496d1a13SShawn Guo 174496d1a13SShawn Guo static struct clk_alpha_pll gpll3 = { 175496d1a13SShawn Guo .offset = 0x3000, 176*9e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 177496d1a13SShawn Guo .clkr = { 178496d1a13SShawn Guo .enable_reg = 0x79000, 179496d1a13SShawn Guo .enable_mask = BIT(3), 180496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 181496d1a13SShawn Guo .name = "gpll3", 182496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 183496d1a13SShawn Guo .fw_name = "bi_tcxo", 184496d1a13SShawn Guo }, 185496d1a13SShawn Guo .num_parents = 1, 186496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 187496d1a13SShawn Guo }, 188496d1a13SShawn Guo }, 189496d1a13SShawn Guo }; 190496d1a13SShawn Guo 191496d1a13SShawn Guo static const struct clk_div_table post_div_table_gpll3_out_main[] = { 192496d1a13SShawn Guo { 0x1, 2 }, 193496d1a13SShawn Guo { } 194496d1a13SShawn Guo }; 195496d1a13SShawn Guo 196496d1a13SShawn Guo static struct clk_alpha_pll_postdiv gpll3_out_main = { 197496d1a13SShawn Guo .offset = 0x3000, 198496d1a13SShawn Guo .post_div_shift = 8, 199496d1a13SShawn Guo .post_div_table = post_div_table_gpll3_out_main, 200496d1a13SShawn Guo .num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_main), 201496d1a13SShawn Guo .width = 4, 202*9e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 203496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 204496d1a13SShawn Guo .name = "gpll3_out_main", 205496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]){ &gpll3.clkr.hw }, 206496d1a13SShawn Guo .num_parents = 1, 207496d1a13SShawn Guo .ops = &clk_alpha_pll_postdiv_ro_ops, 208496d1a13SShawn Guo }, 209496d1a13SShawn Guo }; 210496d1a13SShawn Guo 211496d1a13SShawn Guo static struct clk_alpha_pll gpll4 = { 212496d1a13SShawn Guo .offset = 0x4000, 213*9e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 214496d1a13SShawn Guo .clkr = { 215496d1a13SShawn Guo .enable_reg = 0x79000, 216496d1a13SShawn Guo .enable_mask = BIT(4), 217496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 218496d1a13SShawn Guo .name = "gpll4", 219496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 220496d1a13SShawn Guo .fw_name = "bi_tcxo", 221496d1a13SShawn Guo }, 222496d1a13SShawn Guo .num_parents = 1, 223496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 224496d1a13SShawn Guo }, 225496d1a13SShawn Guo }, 226496d1a13SShawn Guo }; 227496d1a13SShawn Guo 228496d1a13SShawn Guo static struct clk_alpha_pll gpll5 = { 229496d1a13SShawn Guo .offset = 0x5000, 230*9e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 231496d1a13SShawn Guo .clkr = { 232496d1a13SShawn Guo .enable_reg = 0x79000, 233496d1a13SShawn Guo .enable_mask = BIT(5), 234496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 235496d1a13SShawn Guo .name = "gpll5", 236496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 237496d1a13SShawn Guo .fw_name = "bi_tcxo", 238496d1a13SShawn Guo }, 239496d1a13SShawn Guo .num_parents = 1, 240496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 241496d1a13SShawn Guo }, 242496d1a13SShawn Guo }, 243496d1a13SShawn Guo }; 244496d1a13SShawn Guo 245496d1a13SShawn Guo static struct clk_alpha_pll gpll6 = { 246496d1a13SShawn Guo .offset = 0x6000, 247*9e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 248496d1a13SShawn Guo .clkr = { 249496d1a13SShawn Guo .enable_reg = 0x79000, 250496d1a13SShawn Guo .enable_mask = BIT(6), 251496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 252496d1a13SShawn Guo .name = "gpll6", 253496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 254496d1a13SShawn Guo .fw_name = "bi_tcxo", 255496d1a13SShawn Guo }, 256496d1a13SShawn Guo .num_parents = 1, 257496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 258496d1a13SShawn Guo }, 259496d1a13SShawn Guo }, 260496d1a13SShawn Guo }; 261496d1a13SShawn Guo 262496d1a13SShawn Guo static const struct clk_div_table post_div_table_gpll6_out_main[] = { 263496d1a13SShawn Guo { 0x1, 2 }, 264496d1a13SShawn Guo { } 265496d1a13SShawn Guo }; 266496d1a13SShawn Guo 267496d1a13SShawn Guo static struct clk_alpha_pll_postdiv gpll6_out_main = { 268496d1a13SShawn Guo .offset = 0x6000, 269496d1a13SShawn Guo .post_div_shift = 8, 270496d1a13SShawn Guo .post_div_table = post_div_table_gpll6_out_main, 271496d1a13SShawn Guo .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main), 272496d1a13SShawn Guo .width = 4, 273*9e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 274496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 275496d1a13SShawn Guo .name = "gpll6_out_main", 276496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw }, 277496d1a13SShawn Guo .num_parents = 1, 278496d1a13SShawn Guo .ops = &clk_alpha_pll_postdiv_ro_ops, 279496d1a13SShawn Guo }, 280496d1a13SShawn Guo }; 281496d1a13SShawn Guo 282496d1a13SShawn Guo static struct clk_alpha_pll gpll7 = { 283496d1a13SShawn Guo .offset = 0x7000, 284*9e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 285496d1a13SShawn Guo .clkr = { 286496d1a13SShawn Guo .enable_reg = 0x79000, 287496d1a13SShawn Guo .enable_mask = BIT(7), 288496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 289496d1a13SShawn Guo .name = "gpll7", 290496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 291496d1a13SShawn Guo .fw_name = "bi_tcxo", 292496d1a13SShawn Guo }, 293496d1a13SShawn Guo .num_parents = 1, 294496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 295496d1a13SShawn Guo }, 296496d1a13SShawn Guo }, 297496d1a13SShawn Guo }; 298496d1a13SShawn Guo 299496d1a13SShawn Guo /* 533.2MHz configuration */ 300496d1a13SShawn Guo static const struct alpha_pll_config gpll8_config = { 301496d1a13SShawn Guo .l = 0x1B, 302496d1a13SShawn Guo .alpha = 0x55555555, 303496d1a13SShawn Guo .alpha_hi = 0xC5, 304496d1a13SShawn Guo .alpha_en_mask = BIT(24), 305496d1a13SShawn Guo .vco_val = 0x2 << 20, 306496d1a13SShawn Guo .vco_mask = GENMASK(21, 20), 307496d1a13SShawn Guo .main_output_mask = BIT(0), 308496d1a13SShawn Guo .early_output_mask = BIT(3), 309496d1a13SShawn Guo .post_div_val = 0x1 << 8, 310496d1a13SShawn Guo .post_div_mask = GENMASK(11, 8), 311496d1a13SShawn Guo .config_ctl_val = 0x4001055B, 312496d1a13SShawn Guo .test_ctl_hi1_val = 0x1, 313496d1a13SShawn Guo }; 314496d1a13SShawn Guo 315496d1a13SShawn Guo static struct clk_alpha_pll gpll8 = { 316496d1a13SShawn Guo .offset = 0x8000, 317496d1a13SShawn Guo .vco_table = default_vco, 318496d1a13SShawn Guo .num_vco = ARRAY_SIZE(default_vco), 319*9e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 320496d1a13SShawn Guo .flags = SUPPORTS_DYNAMIC_UPDATE, 321496d1a13SShawn Guo .clkr = { 322496d1a13SShawn Guo .enable_reg = 0x79000, 323496d1a13SShawn Guo .enable_mask = BIT(8), 324496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 325496d1a13SShawn Guo .name = "gpll8", 326496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 327496d1a13SShawn Guo .fw_name = "bi_tcxo", 328496d1a13SShawn Guo }, 329496d1a13SShawn Guo .num_parents = 1, 330496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 331496d1a13SShawn Guo }, 332496d1a13SShawn Guo }, 333496d1a13SShawn Guo }; 334496d1a13SShawn Guo 335496d1a13SShawn Guo static const struct clk_div_table post_div_table_gpll8_out_main[] = { 336496d1a13SShawn Guo { 0x1, 2 }, 337496d1a13SShawn Guo { } 338496d1a13SShawn Guo }; 339496d1a13SShawn Guo 340496d1a13SShawn Guo static struct clk_alpha_pll_postdiv gpll8_out_main = { 341496d1a13SShawn Guo .offset = 0x8000, 342496d1a13SShawn Guo .post_div_shift = 8, 343496d1a13SShawn Guo .post_div_table = post_div_table_gpll8_out_main, 344496d1a13SShawn Guo .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main), 345496d1a13SShawn Guo .width = 4, 346*9e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 347496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 348496d1a13SShawn Guo .name = "gpll8_out_main", 349496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw }, 350496d1a13SShawn Guo .num_parents = 1, 351496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 352496d1a13SShawn Guo .ops = &clk_alpha_pll_postdiv_ro_ops, 353496d1a13SShawn Guo }, 354496d1a13SShawn Guo }; 355496d1a13SShawn Guo 356496d1a13SShawn Guo /* 1152MHz configuration */ 357496d1a13SShawn Guo static const struct alpha_pll_config gpll9_config = { 358496d1a13SShawn Guo .l = 0x3C, 359496d1a13SShawn Guo .alpha = 0x0, 360496d1a13SShawn Guo .post_div_val = 0x1 << 8, 361496d1a13SShawn Guo .post_div_mask = GENMASK(9, 8), 362496d1a13SShawn Guo .main_output_mask = BIT(0), 363496d1a13SShawn Guo .early_output_mask = BIT(3), 364496d1a13SShawn Guo .config_ctl_val = 0x00004289, 365496d1a13SShawn Guo .test_ctl_val = 0x08000000, 366496d1a13SShawn Guo }; 367496d1a13SShawn Guo 368496d1a13SShawn Guo static struct clk_alpha_pll gpll9 = { 369496d1a13SShawn Guo .offset = 0x9000, 370496d1a13SShawn Guo .vco_table = brammo_vco, 371496d1a13SShawn Guo .num_vco = ARRAY_SIZE(brammo_vco), 372*9e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO], 373496d1a13SShawn Guo .clkr = { 374496d1a13SShawn Guo .enable_reg = 0x79000, 375496d1a13SShawn Guo .enable_mask = BIT(9), 376496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 377496d1a13SShawn Guo .name = "gpll9", 378496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 379496d1a13SShawn Guo .fw_name = "bi_tcxo", 380496d1a13SShawn Guo }, 381496d1a13SShawn Guo .num_parents = 1, 382496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 383496d1a13SShawn Guo }, 384496d1a13SShawn Guo }, 385496d1a13SShawn Guo }; 386496d1a13SShawn Guo 387496d1a13SShawn Guo static const struct clk_div_table post_div_table_gpll9_out_main[] = { 388496d1a13SShawn Guo { 0x1, 2 }, 389496d1a13SShawn Guo { } 390496d1a13SShawn Guo }; 391496d1a13SShawn Guo 392496d1a13SShawn Guo static struct clk_alpha_pll_postdiv gpll9_out_main = { 393496d1a13SShawn Guo .offset = 0x9000, 394496d1a13SShawn Guo .post_div_shift = 8, 395496d1a13SShawn Guo .post_div_table = post_div_table_gpll9_out_main, 396496d1a13SShawn Guo .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main), 397496d1a13SShawn Guo .width = 2, 398*9e48f051SIskren Chernev .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO], 399496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 400496d1a13SShawn Guo .name = "gpll9_out_main", 401496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw }, 402496d1a13SShawn Guo .num_parents = 1, 403496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 404496d1a13SShawn Guo .ops = &clk_alpha_pll_postdiv_ro_ops, 405496d1a13SShawn Guo }, 406496d1a13SShawn Guo }; 407496d1a13SShawn Guo 408496d1a13SShawn Guo static const struct parent_map gcc_parent_map_0[] = { 409496d1a13SShawn Guo { P_BI_TCXO, 0 }, 410496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 411496d1a13SShawn Guo { P_GPLL0_OUT_AUX2, 2 }, 412496d1a13SShawn Guo }; 413496d1a13SShawn Guo 414496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_0[] = { 415496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 416496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 417496d1a13SShawn Guo { .hw = &gpll0_out_aux2.clkr.hw }, 418496d1a13SShawn Guo }; 419496d1a13SShawn Guo 420496d1a13SShawn Guo static const struct parent_map gcc_parent_map_1[] = { 421496d1a13SShawn Guo { P_BI_TCXO, 0 }, 422496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 423496d1a13SShawn Guo { P_GPLL0_OUT_AUX2, 2 }, 424496d1a13SShawn Guo { P_GPLL6_OUT_MAIN, 4 }, 425496d1a13SShawn Guo }; 426496d1a13SShawn Guo 427496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_1[] = { 428496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 429496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 430496d1a13SShawn Guo { .hw = &gpll0_out_aux2.clkr.hw }, 431496d1a13SShawn Guo { .hw = &gpll6_out_main.clkr.hw }, 432496d1a13SShawn Guo }; 433496d1a13SShawn Guo 434496d1a13SShawn Guo static const struct parent_map gcc_parent_map_2[] = { 435496d1a13SShawn Guo { P_BI_TCXO, 0 }, 436496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 437496d1a13SShawn Guo { P_GPLL0_OUT_AUX2, 2 }, 438496d1a13SShawn Guo { P_SLEEP_CLK, 5 }, 439496d1a13SShawn Guo }; 440496d1a13SShawn Guo 441496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_2[] = { 442496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 443496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 444496d1a13SShawn Guo { .hw = &gpll0_out_aux2.clkr.hw }, 445496d1a13SShawn Guo { .fw_name = "sleep_clk" }, 446496d1a13SShawn Guo }; 447496d1a13SShawn Guo 448496d1a13SShawn Guo static const struct parent_map gcc_parent_map_3[] = { 449496d1a13SShawn Guo { P_BI_TCXO, 0 }, 450496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 451496d1a13SShawn Guo { P_GPLL9_OUT_EARLY, 2 }, 452496d1a13SShawn Guo { P_GPLL10_OUT_MAIN, 3 }, 453496d1a13SShawn Guo { P_GPLL9_OUT_MAIN, 5 }, 454496d1a13SShawn Guo { P_GPLL3_OUT_MAIN, 6 }, 455496d1a13SShawn Guo }; 456496d1a13SShawn Guo 457496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_3[] = { 458496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 459496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 460496d1a13SShawn Guo { .hw = &gpll9.clkr.hw }, 461496d1a13SShawn Guo { .hw = &gpll10.clkr.hw }, 462496d1a13SShawn Guo { .hw = &gpll9_out_main.clkr.hw }, 463496d1a13SShawn Guo { .hw = &gpll3_out_main.clkr.hw }, 464496d1a13SShawn Guo }; 465496d1a13SShawn Guo 466496d1a13SShawn Guo static const struct parent_map gcc_parent_map_4[] = { 467496d1a13SShawn Guo { P_BI_TCXO, 0 }, 468496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 469496d1a13SShawn Guo { P_GPLL0_OUT_AUX2, 2 }, 470496d1a13SShawn Guo { P_GPLL10_OUT_MAIN, 3 }, 471496d1a13SShawn Guo { P_GPLL4_OUT_MAIN, 5 }, 472496d1a13SShawn Guo { P_GPLL3_OUT_EARLY, 6 }, 473496d1a13SShawn Guo }; 474496d1a13SShawn Guo 475496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_4[] = { 476496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 477496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 478496d1a13SShawn Guo { .hw = &gpll0_out_aux2.clkr.hw }, 479496d1a13SShawn Guo { .hw = &gpll10.clkr.hw }, 480496d1a13SShawn Guo { .hw = &gpll4.clkr.hw }, 481496d1a13SShawn Guo { .hw = &gpll3.clkr.hw }, 482496d1a13SShawn Guo }; 483496d1a13SShawn Guo 484496d1a13SShawn Guo static const struct parent_map gcc_parent_map_5[] = { 485496d1a13SShawn Guo { P_BI_TCXO, 0 }, 486496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 487496d1a13SShawn Guo { P_GPLL0_OUT_AUX2, 2 }, 488496d1a13SShawn Guo { P_GPLL4_OUT_MAIN, 5 }, 489496d1a13SShawn Guo { P_GPLL3_OUT_MAIN, 6 }, 490496d1a13SShawn Guo }; 491496d1a13SShawn Guo 492496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_5[] = { 493496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 494496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 495496d1a13SShawn Guo { .hw = &gpll0_out_aux2.clkr.hw }, 496496d1a13SShawn Guo { .hw = &gpll4.clkr.hw }, 497496d1a13SShawn Guo { .hw = &gpll3_out_main.clkr.hw }, 498496d1a13SShawn Guo }; 499496d1a13SShawn Guo 500496d1a13SShawn Guo static const struct parent_map gcc_parent_map_6[] = { 501496d1a13SShawn Guo { P_BI_TCXO, 0 }, 502496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 503496d1a13SShawn Guo { P_GPLL8_OUT_EARLY, 2 }, 504496d1a13SShawn Guo { P_GPLL10_OUT_MAIN, 3 }, 505496d1a13SShawn Guo { P_GPLL8_OUT_MAIN, 4 }, 506496d1a13SShawn Guo { P_GPLL9_OUT_MAIN, 5 }, 507496d1a13SShawn Guo { P_GPLL3_OUT_EARLY, 6 }, 508496d1a13SShawn Guo }; 509496d1a13SShawn Guo 510496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_6[] = { 511496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 512496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 513496d1a13SShawn Guo { .hw = &gpll8.clkr.hw }, 514496d1a13SShawn Guo { .hw = &gpll10.clkr.hw }, 515496d1a13SShawn Guo { .hw = &gpll8_out_main.clkr.hw }, 516496d1a13SShawn Guo { .hw = &gpll9_out_main.clkr.hw }, 517496d1a13SShawn Guo { .hw = &gpll3.clkr.hw }, 518496d1a13SShawn Guo }; 519496d1a13SShawn Guo 520496d1a13SShawn Guo static const struct parent_map gcc_parent_map_7[] = { 521496d1a13SShawn Guo { P_BI_TCXO, 0 }, 522496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 523496d1a13SShawn Guo { P_GPLL8_OUT_EARLY, 2 }, 524496d1a13SShawn Guo { P_GPLL10_OUT_MAIN, 3 }, 525496d1a13SShawn Guo { P_GPLL8_OUT_MAIN, 4 }, 526496d1a13SShawn Guo { P_GPLL9_OUT_MAIN, 5 }, 527496d1a13SShawn Guo { P_GPLL3_OUT_MAIN, 6 }, 528496d1a13SShawn Guo }; 529496d1a13SShawn Guo 530496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_7[] = { 531496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 532496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 533496d1a13SShawn Guo { .hw = &gpll8.clkr.hw }, 534496d1a13SShawn Guo { .hw = &gpll10.clkr.hw }, 535496d1a13SShawn Guo { .hw = &gpll8_out_main.clkr.hw }, 536496d1a13SShawn Guo { .hw = &gpll9_out_main.clkr.hw }, 537496d1a13SShawn Guo { .hw = &gpll3_out_main.clkr.hw }, 538496d1a13SShawn Guo }; 539496d1a13SShawn Guo 540496d1a13SShawn Guo static const struct parent_map gcc_parent_map_8[] = { 541496d1a13SShawn Guo { P_BI_TCXO, 0 }, 542496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 543496d1a13SShawn Guo { P_GPLL8_OUT_EARLY, 2 }, 544496d1a13SShawn Guo { P_GPLL10_OUT_MAIN, 3 }, 545496d1a13SShawn Guo { P_GPLL6_OUT_MAIN, 4 }, 546496d1a13SShawn Guo { P_GPLL9_OUT_MAIN, 5 }, 547496d1a13SShawn Guo { P_GPLL3_OUT_EARLY, 6 }, 548496d1a13SShawn Guo }; 549496d1a13SShawn Guo 550496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_8[] = { 551496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 552496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 553496d1a13SShawn Guo { .hw = &gpll8.clkr.hw }, 554496d1a13SShawn Guo { .hw = &gpll10.clkr.hw }, 555496d1a13SShawn Guo { .hw = &gpll6_out_main.clkr.hw }, 556496d1a13SShawn Guo { .hw = &gpll9_out_main.clkr.hw }, 557496d1a13SShawn Guo { .hw = &gpll3.clkr.hw }, 558496d1a13SShawn Guo }; 559496d1a13SShawn Guo 560496d1a13SShawn Guo static const struct parent_map gcc_parent_map_9[] = { 561496d1a13SShawn Guo { P_BI_TCXO, 0 }, 562496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 563496d1a13SShawn Guo { P_GPLL0_OUT_AUX2, 2 }, 564496d1a13SShawn Guo { P_GPLL10_OUT_MAIN, 3 }, 565496d1a13SShawn Guo { P_GPLL8_OUT_MAIN, 4 }, 566496d1a13SShawn Guo { P_GPLL9_OUT_MAIN, 5 }, 567496d1a13SShawn Guo { P_GPLL3_OUT_EARLY, 6 }, 568496d1a13SShawn Guo }; 569496d1a13SShawn Guo 570496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_9[] = { 571496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 572496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 573496d1a13SShawn Guo { .hw = &gpll0_out_aux2.clkr.hw }, 574496d1a13SShawn Guo { .hw = &gpll10.clkr.hw }, 575496d1a13SShawn Guo { .hw = &gpll8_out_main.clkr.hw }, 576496d1a13SShawn Guo { .hw = &gpll9_out_main.clkr.hw }, 577496d1a13SShawn Guo { .hw = &gpll3.clkr.hw }, 578496d1a13SShawn Guo }; 579496d1a13SShawn Guo 580496d1a13SShawn Guo static const struct parent_map gcc_parent_map_10[] = { 581496d1a13SShawn Guo { P_BI_TCXO, 0 }, 582496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 583496d1a13SShawn Guo { P_GPLL8_OUT_EARLY, 2 }, 584496d1a13SShawn Guo { P_GPLL10_OUT_MAIN, 3 }, 585496d1a13SShawn Guo { P_GPLL6_OUT_EARLY, 5 }, 586496d1a13SShawn Guo { P_GPLL3_OUT_MAIN, 6 }, 587496d1a13SShawn Guo }; 588496d1a13SShawn Guo 589496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_10[] = { 590496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 591496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 592496d1a13SShawn Guo { .hw = &gpll8.clkr.hw }, 593496d1a13SShawn Guo { .hw = &gpll10.clkr.hw }, 594496d1a13SShawn Guo { .hw = &gpll6.clkr.hw }, 595496d1a13SShawn Guo { .hw = &gpll3_out_main.clkr.hw }, 596496d1a13SShawn Guo }; 597496d1a13SShawn Guo 598496d1a13SShawn Guo static const struct parent_map gcc_parent_map_12[] = { 599496d1a13SShawn Guo { P_BI_TCXO, 0 }, 600496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 601496d1a13SShawn Guo { P_GPLL0_OUT_AUX2, 2 }, 602496d1a13SShawn Guo { P_GPLL7_OUT_MAIN, 3 }, 603496d1a13SShawn Guo { P_GPLL4_OUT_MAIN, 5 }, 604496d1a13SShawn Guo }; 605496d1a13SShawn Guo 606496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_12[] = { 607496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 608496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 609496d1a13SShawn Guo { .hw = &gpll0_out_aux2.clkr.hw }, 610496d1a13SShawn Guo { .hw = &gpll7.clkr.hw }, 611496d1a13SShawn Guo { .hw = &gpll4.clkr.hw }, 612496d1a13SShawn Guo }; 613496d1a13SShawn Guo 614496d1a13SShawn Guo static const struct parent_map gcc_parent_map_13[] = { 615496d1a13SShawn Guo { P_BI_TCXO, 0 }, 616496d1a13SShawn Guo { P_SLEEP_CLK, 5 }, 617496d1a13SShawn Guo }; 618496d1a13SShawn Guo 619496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_13[] = { 620496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 621496d1a13SShawn Guo { .fw_name = "sleep_clk" }, 622496d1a13SShawn Guo }; 623496d1a13SShawn Guo 624496d1a13SShawn Guo static const struct parent_map gcc_parent_map_14[] = { 625496d1a13SShawn Guo { P_BI_TCXO, 0 }, 626496d1a13SShawn Guo { P_GPLL11_OUT_MAIN, 1 }, 627496d1a13SShawn Guo { P_GPLL11_OUT_AUX, 2 }, 628496d1a13SShawn Guo { P_GPLL11_OUT_AUX2, 3 }, 629496d1a13SShawn Guo }; 630496d1a13SShawn Guo 631496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_14[] = { 632496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 633496d1a13SShawn Guo { .hw = &gpll11.clkr.hw }, 634496d1a13SShawn Guo { .hw = &gpll11.clkr.hw }, 635496d1a13SShawn Guo { .hw = &gpll11.clkr.hw }, 636496d1a13SShawn Guo }; 637496d1a13SShawn Guo 638496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 639496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 640496d1a13SShawn Guo { } 641496d1a13SShawn Guo }; 642496d1a13SShawn Guo 643496d1a13SShawn Guo static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 644496d1a13SShawn Guo .cmd_rcgr = 0x1a034, 645496d1a13SShawn Guo .mnd_width = 0, 646496d1a13SShawn Guo .hid_width = 5, 647496d1a13SShawn Guo .parent_map = gcc_parent_map_0, 648496d1a13SShawn Guo .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 649496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 650496d1a13SShawn Guo .name = "gcc_usb30_prim_mock_utmi_clk_src", 651496d1a13SShawn Guo .parent_data = gcc_parents_0, 652496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_0), 653496d1a13SShawn Guo .ops = &clk_rcg2_ops, 654496d1a13SShawn Guo }, 655496d1a13SShawn Guo }; 656496d1a13SShawn Guo 657496d1a13SShawn Guo static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv = { 658496d1a13SShawn Guo .reg = 0x1a04c, 659496d1a13SShawn Guo .shift = 0, 660496d1a13SShawn Guo .width = 2, 661496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data) { 662496d1a13SShawn Guo .name = "gcc_usb30_prim_mock_utmi_postdiv", 663496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 664496d1a13SShawn Guo { &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw }, 665496d1a13SShawn Guo .num_parents = 1, 666496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 667496d1a13SShawn Guo .ops = &clk_regmap_div_ro_ops, 668496d1a13SShawn Guo }, 669496d1a13SShawn Guo }; 670496d1a13SShawn Guo 671496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = { 672496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 673496d1a13SShawn Guo F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 674496d1a13SShawn Guo F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 675496d1a13SShawn Guo F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 676496d1a13SShawn Guo { } 677496d1a13SShawn Guo }; 678496d1a13SShawn Guo 679496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_axi_clk_src = { 680496d1a13SShawn Guo .cmd_rcgr = 0x5802c, 681496d1a13SShawn Guo .mnd_width = 0, 682496d1a13SShawn Guo .hid_width = 5, 683496d1a13SShawn Guo .parent_map = gcc_parent_map_4, 684496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_axi_clk_src, 685496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 686496d1a13SShawn Guo .name = "gcc_camss_axi_clk_src", 687496d1a13SShawn Guo .parent_data = gcc_parents_4, 688496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_4), 689496d1a13SShawn Guo .ops = &clk_rcg2_ops, 690496d1a13SShawn Guo }, 691496d1a13SShawn Guo }; 692496d1a13SShawn Guo 693496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = { 694496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 695496d1a13SShawn Guo F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 696496d1a13SShawn Guo { } 697496d1a13SShawn Guo }; 698496d1a13SShawn Guo 699496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_cci_clk_src = { 700496d1a13SShawn Guo .cmd_rcgr = 0x56000, 701496d1a13SShawn Guo .mnd_width = 0, 702496d1a13SShawn Guo .hid_width = 5, 703496d1a13SShawn Guo .parent_map = gcc_parent_map_9, 704496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_cci_clk_src, 705496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 706496d1a13SShawn Guo .name = "gcc_camss_cci_clk_src", 707496d1a13SShawn Guo .parent_data = gcc_parents_9, 708496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_9), 709496d1a13SShawn Guo .ops = &clk_rcg2_ops, 710496d1a13SShawn Guo }, 711496d1a13SShawn Guo }; 712496d1a13SShawn Guo 713496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = { 714496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 715496d1a13SShawn Guo F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 716496d1a13SShawn Guo F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 717496d1a13SShawn Guo F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0), 718496d1a13SShawn Guo { } 719496d1a13SShawn Guo }; 720496d1a13SShawn Guo 721496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { 722496d1a13SShawn Guo .cmd_rcgr = 0x45000, 723496d1a13SShawn Guo .mnd_width = 0, 724496d1a13SShawn Guo .hid_width = 5, 725496d1a13SShawn Guo .parent_map = gcc_parent_map_5, 726496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 727496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 728496d1a13SShawn Guo .name = "gcc_camss_csi0phytimer_clk_src", 729496d1a13SShawn Guo .parent_data = gcc_parents_5, 730496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_5), 731496d1a13SShawn Guo .ops = &clk_rcg2_ops, 732496d1a13SShawn Guo }, 733496d1a13SShawn Guo }; 734496d1a13SShawn Guo 735496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { 736496d1a13SShawn Guo .cmd_rcgr = 0x4501c, 737496d1a13SShawn Guo .mnd_width = 0, 738496d1a13SShawn Guo .hid_width = 5, 739496d1a13SShawn Guo .parent_map = gcc_parent_map_5, 740496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 741496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 742496d1a13SShawn Guo .name = "gcc_camss_csi1phytimer_clk_src", 743496d1a13SShawn Guo .parent_data = gcc_parents_5, 744496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_5), 745496d1a13SShawn Guo .ops = &clk_rcg2_ops, 746496d1a13SShawn Guo }, 747496d1a13SShawn Guo }; 748496d1a13SShawn Guo 749496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { 750496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 751496d1a13SShawn Guo F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24), 752496d1a13SShawn Guo F(64000000, P_GPLL9_OUT_EARLY, 9, 1, 2), 753496d1a13SShawn Guo { } 754496d1a13SShawn Guo }; 755496d1a13SShawn Guo 756496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_mclk0_clk_src = { 757496d1a13SShawn Guo .cmd_rcgr = 0x51000, 758496d1a13SShawn Guo .mnd_width = 8, 759496d1a13SShawn Guo .hid_width = 5, 760496d1a13SShawn Guo .parent_map = gcc_parent_map_3, 761496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 762496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 763496d1a13SShawn Guo .name = "gcc_camss_mclk0_clk_src", 764496d1a13SShawn Guo .parent_data = gcc_parents_3, 765496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_3), 766496d1a13SShawn Guo .flags = CLK_OPS_PARENT_ENABLE, 767496d1a13SShawn Guo .ops = &clk_rcg2_ops, 768496d1a13SShawn Guo }, 769496d1a13SShawn Guo }; 770496d1a13SShawn Guo 771496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_mclk1_clk_src = { 772496d1a13SShawn Guo .cmd_rcgr = 0x5101c, 773496d1a13SShawn Guo .mnd_width = 8, 774496d1a13SShawn Guo .hid_width = 5, 775496d1a13SShawn Guo .parent_map = gcc_parent_map_3, 776496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 777496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 778496d1a13SShawn Guo .name = "gcc_camss_mclk1_clk_src", 779496d1a13SShawn Guo .parent_data = gcc_parents_3, 780496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_3), 781496d1a13SShawn Guo .flags = CLK_OPS_PARENT_ENABLE, 782496d1a13SShawn Guo .ops = &clk_rcg2_ops, 783496d1a13SShawn Guo }, 784496d1a13SShawn Guo }; 785496d1a13SShawn Guo 786496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_mclk2_clk_src = { 787496d1a13SShawn Guo .cmd_rcgr = 0x51038, 788496d1a13SShawn Guo .mnd_width = 8, 789496d1a13SShawn Guo .hid_width = 5, 790496d1a13SShawn Guo .parent_map = gcc_parent_map_3, 791496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 792496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 793496d1a13SShawn Guo .name = "gcc_camss_mclk2_clk_src", 794496d1a13SShawn Guo .parent_data = gcc_parents_3, 795496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_3), 796496d1a13SShawn Guo .flags = CLK_OPS_PARENT_ENABLE, 797496d1a13SShawn Guo .ops = &clk_rcg2_ops, 798496d1a13SShawn Guo }, 799496d1a13SShawn Guo }; 800496d1a13SShawn Guo 801496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_mclk3_clk_src = { 802496d1a13SShawn Guo .cmd_rcgr = 0x51054, 803496d1a13SShawn Guo .mnd_width = 8, 804496d1a13SShawn Guo .hid_width = 5, 805496d1a13SShawn Guo .parent_map = gcc_parent_map_3, 806496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 807496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 808496d1a13SShawn Guo .name = "gcc_camss_mclk3_clk_src", 809496d1a13SShawn Guo .parent_data = gcc_parents_3, 810496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_3), 811496d1a13SShawn Guo .flags = CLK_OPS_PARENT_ENABLE, 812496d1a13SShawn Guo .ops = &clk_rcg2_ops, 813496d1a13SShawn Guo }, 814496d1a13SShawn Guo }; 815496d1a13SShawn Guo 816496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = { 817496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 818496d1a13SShawn Guo F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0), 819496d1a13SShawn Guo F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 820496d1a13SShawn Guo { } 821496d1a13SShawn Guo }; 822496d1a13SShawn Guo 823496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = { 824496d1a13SShawn Guo .cmd_rcgr = 0x55024, 825496d1a13SShawn Guo .mnd_width = 0, 826496d1a13SShawn Guo .hid_width = 5, 827496d1a13SShawn Guo .parent_map = gcc_parent_map_6, 828496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src, 829496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 830496d1a13SShawn Guo .name = "gcc_camss_ope_ahb_clk_src", 831496d1a13SShawn Guo .parent_data = gcc_parents_6, 832496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_6), 833496d1a13SShawn Guo .ops = &clk_rcg2_ops, 834496d1a13SShawn Guo }, 835496d1a13SShawn Guo }; 836496d1a13SShawn Guo 837496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = { 838496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 839496d1a13SShawn Guo F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0), 840496d1a13SShawn Guo F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0), 841496d1a13SShawn Guo F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0), 842496d1a13SShawn Guo F(580000000, P_GPLL8_OUT_EARLY, 1, 0, 0), 843496d1a13SShawn Guo { } 844496d1a13SShawn Guo }; 845496d1a13SShawn Guo 846496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_ope_clk_src = { 847496d1a13SShawn Guo .cmd_rcgr = 0x55004, 848496d1a13SShawn Guo .mnd_width = 0, 849496d1a13SShawn Guo .hid_width = 5, 850496d1a13SShawn Guo .parent_map = gcc_parent_map_6, 851496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_ope_clk_src, 852496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 853496d1a13SShawn Guo .name = "gcc_camss_ope_clk_src", 854496d1a13SShawn Guo .parent_data = gcc_parents_6, 855496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_6), 856496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 857496d1a13SShawn Guo .ops = &clk_rcg2_ops, 858496d1a13SShawn Guo }, 859496d1a13SShawn Guo }; 860496d1a13SShawn Guo 861496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = { 862496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 863496d1a13SShawn Guo F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0), 864496d1a13SShawn Guo F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0), 865496d1a13SShawn Guo F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0), 866496d1a13SShawn Guo F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0), 867496d1a13SShawn Guo F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0), 868496d1a13SShawn Guo F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0), 869496d1a13SShawn Guo F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0), 870496d1a13SShawn Guo F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0), 871496d1a13SShawn Guo F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0), 872496d1a13SShawn Guo F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0), 873496d1a13SShawn Guo F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0), 874496d1a13SShawn Guo F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0), 875496d1a13SShawn Guo F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0), 876496d1a13SShawn Guo F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0), 877496d1a13SShawn Guo F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0), 878496d1a13SShawn Guo { } 879496d1a13SShawn Guo }; 880496d1a13SShawn Guo 881496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_tfe_0_clk_src = { 882496d1a13SShawn Guo .cmd_rcgr = 0x52004, 883496d1a13SShawn Guo .mnd_width = 8, 884496d1a13SShawn Guo .hid_width = 5, 885496d1a13SShawn Guo .parent_map = gcc_parent_map_7, 886496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 887496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 888496d1a13SShawn Guo .name = "gcc_camss_tfe_0_clk_src", 889496d1a13SShawn Guo .parent_data = gcc_parents_7, 890496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_7), 891496d1a13SShawn Guo .ops = &clk_rcg2_ops, 892496d1a13SShawn Guo }, 893496d1a13SShawn Guo }; 894496d1a13SShawn Guo 895496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = { 896496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 897496d1a13SShawn Guo F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0), 898496d1a13SShawn Guo F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 899496d1a13SShawn Guo F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 900496d1a13SShawn Guo F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 901496d1a13SShawn Guo F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0), 902496d1a13SShawn Guo { } 903496d1a13SShawn Guo }; 904496d1a13SShawn Guo 905496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = { 906496d1a13SShawn Guo .cmd_rcgr = 0x52094, 907496d1a13SShawn Guo .mnd_width = 0, 908496d1a13SShawn Guo .hid_width = 5, 909496d1a13SShawn Guo .parent_map = gcc_parent_map_8, 910496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 911496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 912496d1a13SShawn Guo .name = "gcc_camss_tfe_0_csid_clk_src", 913496d1a13SShawn Guo .parent_data = gcc_parents_8, 914496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_8), 915496d1a13SShawn Guo .ops = &clk_rcg2_ops, 916496d1a13SShawn Guo }, 917496d1a13SShawn Guo }; 918496d1a13SShawn Guo 919496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_tfe_1_clk_src = { 920496d1a13SShawn Guo .cmd_rcgr = 0x52024, 921496d1a13SShawn Guo .mnd_width = 8, 922496d1a13SShawn Guo .hid_width = 5, 923496d1a13SShawn Guo .parent_map = gcc_parent_map_7, 924496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 925496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 926496d1a13SShawn Guo .name = "gcc_camss_tfe_1_clk_src", 927496d1a13SShawn Guo .parent_data = gcc_parents_7, 928496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_7), 929496d1a13SShawn Guo .ops = &clk_rcg2_ops, 930496d1a13SShawn Guo }, 931496d1a13SShawn Guo }; 932496d1a13SShawn Guo 933496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = { 934496d1a13SShawn Guo .cmd_rcgr = 0x520b4, 935496d1a13SShawn Guo .mnd_width = 0, 936496d1a13SShawn Guo .hid_width = 5, 937496d1a13SShawn Guo .parent_map = gcc_parent_map_8, 938496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 939496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 940496d1a13SShawn Guo .name = "gcc_camss_tfe_1_csid_clk_src", 941496d1a13SShawn Guo .parent_data = gcc_parents_8, 942496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_8), 943496d1a13SShawn Guo .ops = &clk_rcg2_ops, 944496d1a13SShawn Guo }, 945496d1a13SShawn Guo }; 946496d1a13SShawn Guo 947496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = { 948496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 949496d1a13SShawn Guo F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 950496d1a13SShawn Guo F(341333333, P_GPLL6_OUT_EARLY, 1, 4, 9), 951496d1a13SShawn Guo F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0), 952496d1a13SShawn Guo { } 953496d1a13SShawn Guo }; 954496d1a13SShawn Guo 955496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = { 956496d1a13SShawn Guo .cmd_rcgr = 0x52064, 957496d1a13SShawn Guo .mnd_width = 16, 958496d1a13SShawn Guo .hid_width = 5, 959496d1a13SShawn Guo .parent_map = gcc_parent_map_10, 960496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src, 961496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 962496d1a13SShawn Guo .name = "gcc_camss_tfe_cphy_rx_clk_src", 963496d1a13SShawn Guo .parent_data = gcc_parents_10, 964496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_10), 965496d1a13SShawn Guo .flags = CLK_OPS_PARENT_ENABLE, 966496d1a13SShawn Guo .ops = &clk_rcg2_ops, 967496d1a13SShawn Guo }, 968496d1a13SShawn Guo }; 969496d1a13SShawn Guo 970496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = { 971496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 972496d1a13SShawn Guo F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0), 973496d1a13SShawn Guo F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0), 974496d1a13SShawn Guo { } 975496d1a13SShawn Guo }; 976496d1a13SShawn Guo 977496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_top_ahb_clk_src = { 978496d1a13SShawn Guo .cmd_rcgr = 0x58010, 979496d1a13SShawn Guo .mnd_width = 0, 980496d1a13SShawn Guo .hid_width = 5, 981496d1a13SShawn Guo .parent_map = gcc_parent_map_4, 982496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_top_ahb_clk_src, 983496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 984496d1a13SShawn Guo .name = "gcc_camss_top_ahb_clk_src", 985496d1a13SShawn Guo .parent_data = gcc_parents_4, 986496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_4), 987496d1a13SShawn Guo .ops = &clk_rcg2_ops, 988496d1a13SShawn Guo }, 989496d1a13SShawn Guo }; 990496d1a13SShawn Guo 991496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 992496d1a13SShawn Guo F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 993496d1a13SShawn Guo F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 994496d1a13SShawn Guo F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 995496d1a13SShawn Guo F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 996496d1a13SShawn Guo { } 997496d1a13SShawn Guo }; 998496d1a13SShawn Guo 999496d1a13SShawn Guo static struct clk_rcg2 gcc_gp1_clk_src = { 1000496d1a13SShawn Guo .cmd_rcgr = 0x4d004, 1001496d1a13SShawn Guo .mnd_width = 8, 1002496d1a13SShawn Guo .hid_width = 5, 1003496d1a13SShawn Guo .parent_map = gcc_parent_map_2, 1004496d1a13SShawn Guo .freq_tbl = ftbl_gcc_gp1_clk_src, 1005496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1006496d1a13SShawn Guo .name = "gcc_gp1_clk_src", 1007496d1a13SShawn Guo .parent_data = gcc_parents_2, 1008496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_2), 1009496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1010496d1a13SShawn Guo }, 1011496d1a13SShawn Guo }; 1012496d1a13SShawn Guo 1013496d1a13SShawn Guo static struct clk_rcg2 gcc_gp2_clk_src = { 1014496d1a13SShawn Guo .cmd_rcgr = 0x4e004, 1015496d1a13SShawn Guo .mnd_width = 8, 1016496d1a13SShawn Guo .hid_width = 5, 1017496d1a13SShawn Guo .parent_map = gcc_parent_map_2, 1018496d1a13SShawn Guo .freq_tbl = ftbl_gcc_gp1_clk_src, 1019496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1020496d1a13SShawn Guo .name = "gcc_gp2_clk_src", 1021496d1a13SShawn Guo .parent_data = gcc_parents_2, 1022496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_2), 1023496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1024496d1a13SShawn Guo }, 1025496d1a13SShawn Guo }; 1026496d1a13SShawn Guo 1027496d1a13SShawn Guo static struct clk_rcg2 gcc_gp3_clk_src = { 1028496d1a13SShawn Guo .cmd_rcgr = 0x4f004, 1029496d1a13SShawn Guo .mnd_width = 8, 1030496d1a13SShawn Guo .hid_width = 5, 1031496d1a13SShawn Guo .parent_map = gcc_parent_map_2, 1032496d1a13SShawn Guo .freq_tbl = ftbl_gcc_gp1_clk_src, 1033496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1034496d1a13SShawn Guo .name = "gcc_gp3_clk_src", 1035496d1a13SShawn Guo .parent_data = gcc_parents_2, 1036496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_2), 1037496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1038496d1a13SShawn Guo }, 1039496d1a13SShawn Guo }; 1040496d1a13SShawn Guo 1041496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 1042496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 1043496d1a13SShawn Guo F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0), 1044496d1a13SShawn Guo { } 1045496d1a13SShawn Guo }; 1046496d1a13SShawn Guo 1047496d1a13SShawn Guo static struct clk_rcg2 gcc_pdm2_clk_src = { 1048496d1a13SShawn Guo .cmd_rcgr = 0x20010, 1049496d1a13SShawn Guo .mnd_width = 0, 1050496d1a13SShawn Guo .hid_width = 5, 1051496d1a13SShawn Guo .parent_map = gcc_parent_map_0, 1052496d1a13SShawn Guo .freq_tbl = ftbl_gcc_pdm2_clk_src, 1053496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1054496d1a13SShawn Guo .name = "gcc_pdm2_clk_src", 1055496d1a13SShawn Guo .parent_data = gcc_parents_0, 1056496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_0), 1057496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1058496d1a13SShawn Guo }, 1059496d1a13SShawn Guo }; 1060496d1a13SShawn Guo 1061496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 1062496d1a13SShawn Guo F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625), 1063496d1a13SShawn Guo F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625), 1064496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 1065496d1a13SShawn Guo F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625), 1066496d1a13SShawn Guo F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75), 1067496d1a13SShawn Guo F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25), 1068496d1a13SShawn Guo F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75), 1069496d1a13SShawn Guo F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1070496d1a13SShawn Guo F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15), 1071496d1a13SShawn Guo F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25), 1072496d1a13SShawn Guo F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1073496d1a13SShawn Guo F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375), 1074496d1a13SShawn Guo F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75), 1075496d1a13SShawn Guo F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625), 1076496d1a13SShawn Guo F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0), 1077496d1a13SShawn Guo F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0), 1078496d1a13SShawn Guo { } 1079496d1a13SShawn Guo }; 1080496d1a13SShawn Guo 1081496d1a13SShawn Guo static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 1082496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s0_clk_src", 1083496d1a13SShawn Guo .parent_data = gcc_parents_1, 1084496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_1), 1085496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1086496d1a13SShawn Guo }; 1087496d1a13SShawn Guo 1088496d1a13SShawn Guo static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 1089496d1a13SShawn Guo .cmd_rcgr = 0x1f148, 1090496d1a13SShawn Guo .mnd_width = 16, 1091496d1a13SShawn Guo .hid_width = 5, 1092496d1a13SShawn Guo .parent_map = gcc_parent_map_1, 1093496d1a13SShawn Guo .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1094496d1a13SShawn Guo .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 1095496d1a13SShawn Guo }; 1096496d1a13SShawn Guo 1097496d1a13SShawn Guo static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 1098496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s1_clk_src", 1099496d1a13SShawn Guo .parent_data = gcc_parents_1, 1100496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_1), 1101496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1102496d1a13SShawn Guo }; 1103496d1a13SShawn Guo 1104496d1a13SShawn Guo static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 1105496d1a13SShawn Guo .cmd_rcgr = 0x1f278, 1106496d1a13SShawn Guo .mnd_width = 16, 1107496d1a13SShawn Guo .hid_width = 5, 1108496d1a13SShawn Guo .parent_map = gcc_parent_map_1, 1109496d1a13SShawn Guo .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1110496d1a13SShawn Guo .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 1111496d1a13SShawn Guo }; 1112496d1a13SShawn Guo 1113496d1a13SShawn Guo static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 1114496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s2_clk_src", 1115496d1a13SShawn Guo .parent_data = gcc_parents_1, 1116496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_1), 1117496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1118496d1a13SShawn Guo }; 1119496d1a13SShawn Guo 1120496d1a13SShawn Guo static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 1121496d1a13SShawn Guo .cmd_rcgr = 0x1f3a8, 1122496d1a13SShawn Guo .mnd_width = 16, 1123496d1a13SShawn Guo .hid_width = 5, 1124496d1a13SShawn Guo .parent_map = gcc_parent_map_1, 1125496d1a13SShawn Guo .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1126496d1a13SShawn Guo .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 1127496d1a13SShawn Guo }; 1128496d1a13SShawn Guo 1129496d1a13SShawn Guo static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 1130496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s3_clk_src", 1131496d1a13SShawn Guo .parent_data = gcc_parents_1, 1132496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_1), 1133496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1134496d1a13SShawn Guo }; 1135496d1a13SShawn Guo 1136496d1a13SShawn Guo static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 1137496d1a13SShawn Guo .cmd_rcgr = 0x1f4d8, 1138496d1a13SShawn Guo .mnd_width = 16, 1139496d1a13SShawn Guo .hid_width = 5, 1140496d1a13SShawn Guo .parent_map = gcc_parent_map_1, 1141496d1a13SShawn Guo .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1142496d1a13SShawn Guo .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 1143496d1a13SShawn Guo }; 1144496d1a13SShawn Guo 1145496d1a13SShawn Guo static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 1146496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s4_clk_src", 1147496d1a13SShawn Guo .parent_data = gcc_parents_1, 1148496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_1), 1149496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1150496d1a13SShawn Guo }; 1151496d1a13SShawn Guo 1152496d1a13SShawn Guo static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 1153496d1a13SShawn Guo .cmd_rcgr = 0x1f608, 1154496d1a13SShawn Guo .mnd_width = 16, 1155496d1a13SShawn Guo .hid_width = 5, 1156496d1a13SShawn Guo .parent_map = gcc_parent_map_1, 1157496d1a13SShawn Guo .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1158496d1a13SShawn Guo .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 1159496d1a13SShawn Guo }; 1160496d1a13SShawn Guo 1161496d1a13SShawn Guo static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 1162496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s5_clk_src", 1163496d1a13SShawn Guo .parent_data = gcc_parents_1, 1164496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_1), 1165496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1166496d1a13SShawn Guo }; 1167496d1a13SShawn Guo 1168496d1a13SShawn Guo static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 1169496d1a13SShawn Guo .cmd_rcgr = 0x1f738, 1170496d1a13SShawn Guo .mnd_width = 16, 1171496d1a13SShawn Guo .hid_width = 5, 1172496d1a13SShawn Guo .parent_map = gcc_parent_map_1, 1173496d1a13SShawn Guo .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1174496d1a13SShawn Guo .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 1175496d1a13SShawn Guo }; 1176496d1a13SShawn Guo 1177496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 1178496d1a13SShawn Guo F(144000, P_BI_TCXO, 16, 3, 25), 1179496d1a13SShawn Guo F(400000, P_BI_TCXO, 12, 1, 4), 1180496d1a13SShawn Guo F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3), 1181496d1a13SShawn Guo F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2), 1182496d1a13SShawn Guo F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1183496d1a13SShawn Guo F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1184496d1a13SShawn Guo F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 1185496d1a13SShawn Guo F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 1186496d1a13SShawn Guo { } 1187496d1a13SShawn Guo }; 1188496d1a13SShawn Guo 1189496d1a13SShawn Guo static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 1190496d1a13SShawn Guo .cmd_rcgr = 0x38028, 1191496d1a13SShawn Guo .mnd_width = 8, 1192496d1a13SShawn Guo .hid_width = 5, 1193496d1a13SShawn Guo .parent_map = gcc_parent_map_1, 1194496d1a13SShawn Guo .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 1195496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1196496d1a13SShawn Guo .name = "gcc_sdcc1_apps_clk_src", 1197496d1a13SShawn Guo .parent_data = gcc_parents_1, 1198496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_1), 1199496d1a13SShawn Guo .ops = &clk_rcg2_floor_ops, 1200496d1a13SShawn Guo }, 1201496d1a13SShawn Guo }; 1202496d1a13SShawn Guo 1203496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 1204496d1a13SShawn Guo F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1205496d1a13SShawn Guo F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1206496d1a13SShawn Guo F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1207496d1a13SShawn Guo F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1208496d1a13SShawn Guo F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 1209496d1a13SShawn Guo { } 1210496d1a13SShawn Guo }; 1211496d1a13SShawn Guo 1212496d1a13SShawn Guo static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 1213496d1a13SShawn Guo .cmd_rcgr = 0x38010, 1214496d1a13SShawn Guo .mnd_width = 0, 1215496d1a13SShawn Guo .hid_width = 5, 1216496d1a13SShawn Guo .parent_map = gcc_parent_map_0, 1217496d1a13SShawn Guo .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 1218496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1219496d1a13SShawn Guo .name = "gcc_sdcc1_ice_core_clk_src", 1220496d1a13SShawn Guo .parent_data = gcc_parents_0, 1221496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_0), 1222496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1223496d1a13SShawn Guo }, 1224496d1a13SShawn Guo }; 1225496d1a13SShawn Guo 1226496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1227496d1a13SShawn Guo F(400000, P_BI_TCXO, 12, 1, 4), 1228496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 1229496d1a13SShawn Guo F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1230496d1a13SShawn Guo F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1231496d1a13SShawn Guo F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1232496d1a13SShawn Guo F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0), 1233496d1a13SShawn Guo { } 1234496d1a13SShawn Guo }; 1235496d1a13SShawn Guo 1236496d1a13SShawn Guo static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1237496d1a13SShawn Guo .cmd_rcgr = 0x1e00c, 1238496d1a13SShawn Guo .mnd_width = 8, 1239496d1a13SShawn Guo .hid_width = 5, 1240496d1a13SShawn Guo .parent_map = gcc_parent_map_12, 1241496d1a13SShawn Guo .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1242496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1243496d1a13SShawn Guo .name = "gcc_sdcc2_apps_clk_src", 1244496d1a13SShawn Guo .parent_data = gcc_parents_12, 1245496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_12), 1246496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1247496d1a13SShawn Guo }, 1248496d1a13SShawn Guo }; 1249496d1a13SShawn Guo 1250496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1251496d1a13SShawn Guo F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0), 1252496d1a13SShawn Guo F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0), 1253496d1a13SShawn Guo F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1254496d1a13SShawn Guo F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1255496d1a13SShawn Guo { } 1256496d1a13SShawn Guo }; 1257496d1a13SShawn Guo 1258496d1a13SShawn Guo static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1259496d1a13SShawn Guo .cmd_rcgr = 0x1a01c, 1260496d1a13SShawn Guo .mnd_width = 8, 1261496d1a13SShawn Guo .hid_width = 5, 1262496d1a13SShawn Guo .parent_map = gcc_parent_map_0, 1263496d1a13SShawn Guo .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1264496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1265496d1a13SShawn Guo .name = "gcc_usb30_prim_master_clk_src", 1266496d1a13SShawn Guo .parent_data = gcc_parents_0, 1267496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_0), 1268496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1269496d1a13SShawn Guo }, 1270496d1a13SShawn Guo }; 1271496d1a13SShawn Guo 1272496d1a13SShawn Guo static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1273496d1a13SShawn Guo .cmd_rcgr = 0x1a060, 1274496d1a13SShawn Guo .mnd_width = 0, 1275496d1a13SShawn Guo .hid_width = 5, 1276496d1a13SShawn Guo .parent_map = gcc_parent_map_13, 1277496d1a13SShawn Guo .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1278496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1279496d1a13SShawn Guo .name = "gcc_usb3_prim_phy_aux_clk_src", 1280496d1a13SShawn Guo .parent_data = gcc_parents_13, 1281496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_13), 1282496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1283496d1a13SShawn Guo }, 1284496d1a13SShawn Guo }; 1285496d1a13SShawn Guo 1286496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = { 1287496d1a13SShawn Guo F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0), 1288496d1a13SShawn Guo F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0), 1289496d1a13SShawn Guo F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0), 1290496d1a13SShawn Guo F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0), 1291496d1a13SShawn Guo { } 1292496d1a13SShawn Guo }; 1293496d1a13SShawn Guo 1294496d1a13SShawn Guo static struct clk_rcg2 gcc_video_venus_clk_src = { 1295496d1a13SShawn Guo .cmd_rcgr = 0x58060, 1296496d1a13SShawn Guo .mnd_width = 0, 1297496d1a13SShawn Guo .hid_width = 5, 1298496d1a13SShawn Guo .parent_map = gcc_parent_map_14, 1299496d1a13SShawn Guo .freq_tbl = ftbl_gcc_video_venus_clk_src, 1300496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1301496d1a13SShawn Guo .name = "gcc_video_venus_clk_src", 1302496d1a13SShawn Guo .parent_data = gcc_parents_14, 1303496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_14), 1304496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1305496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1306496d1a13SShawn Guo }, 1307496d1a13SShawn Guo }; 1308496d1a13SShawn Guo 1309496d1a13SShawn Guo static struct clk_branch gcc_ahb2phy_csi_clk = { 1310496d1a13SShawn Guo .halt_reg = 0x1d004, 1311496d1a13SShawn Guo .halt_check = BRANCH_HALT_DELAY, 1312496d1a13SShawn Guo .hwcg_reg = 0x1d004, 1313496d1a13SShawn Guo .hwcg_bit = 1, 1314496d1a13SShawn Guo .clkr = { 1315496d1a13SShawn Guo .enable_reg = 0x1d004, 1316496d1a13SShawn Guo .enable_mask = BIT(0), 1317496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1318496d1a13SShawn Guo .name = "gcc_ahb2phy_csi_clk", 1319496d1a13SShawn Guo .ops = &clk_branch2_ops, 1320496d1a13SShawn Guo }, 1321496d1a13SShawn Guo }, 1322496d1a13SShawn Guo }; 1323496d1a13SShawn Guo 1324496d1a13SShawn Guo static struct clk_branch gcc_ahb2phy_usb_clk = { 1325496d1a13SShawn Guo .halt_reg = 0x1d008, 1326496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1327496d1a13SShawn Guo .hwcg_reg = 0x1d008, 1328496d1a13SShawn Guo .hwcg_bit = 1, 1329496d1a13SShawn Guo .clkr = { 1330496d1a13SShawn Guo .enable_reg = 0x1d008, 1331496d1a13SShawn Guo .enable_mask = BIT(0), 1332496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1333496d1a13SShawn Guo .name = "gcc_ahb2phy_usb_clk", 1334496d1a13SShawn Guo .ops = &clk_branch2_ops, 1335496d1a13SShawn Guo }, 1336496d1a13SShawn Guo }, 1337496d1a13SShawn Guo }; 1338496d1a13SShawn Guo 1339496d1a13SShawn Guo static struct clk_branch gcc_bimc_gpu_axi_clk = { 1340496d1a13SShawn Guo .halt_reg = 0x71154, 1341496d1a13SShawn Guo .halt_check = BRANCH_HALT_DELAY, 1342496d1a13SShawn Guo .hwcg_reg = 0x71154, 1343496d1a13SShawn Guo .hwcg_bit = 1, 1344496d1a13SShawn Guo .clkr = { 1345496d1a13SShawn Guo .enable_reg = 0x71154, 1346496d1a13SShawn Guo .enable_mask = BIT(0), 1347496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1348496d1a13SShawn Guo .name = "gcc_bimc_gpu_axi_clk", 1349496d1a13SShawn Guo .ops = &clk_branch2_ops, 1350496d1a13SShawn Guo }, 1351496d1a13SShawn Guo }, 1352496d1a13SShawn Guo }; 1353496d1a13SShawn Guo 1354496d1a13SShawn Guo static struct clk_branch gcc_boot_rom_ahb_clk = { 1355496d1a13SShawn Guo .halt_reg = 0x23004, 1356496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 1357496d1a13SShawn Guo .hwcg_reg = 0x23004, 1358496d1a13SShawn Guo .hwcg_bit = 1, 1359496d1a13SShawn Guo .clkr = { 1360496d1a13SShawn Guo .enable_reg = 0x79004, 1361496d1a13SShawn Guo .enable_mask = BIT(10), 1362496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1363496d1a13SShawn Guo .name = "gcc_boot_rom_ahb_clk", 1364496d1a13SShawn Guo .ops = &clk_branch2_ops, 1365496d1a13SShawn Guo }, 1366496d1a13SShawn Guo }, 1367496d1a13SShawn Guo }; 1368496d1a13SShawn Guo 1369496d1a13SShawn Guo static struct clk_branch gcc_cam_throttle_nrt_clk = { 1370496d1a13SShawn Guo .halt_reg = 0x17070, 1371496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 1372496d1a13SShawn Guo .hwcg_reg = 0x17070, 1373496d1a13SShawn Guo .hwcg_bit = 1, 1374496d1a13SShawn Guo .clkr = { 1375496d1a13SShawn Guo .enable_reg = 0x79004, 1376496d1a13SShawn Guo .enable_mask = BIT(27), 1377496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1378496d1a13SShawn Guo .name = "gcc_cam_throttle_nrt_clk", 1379496d1a13SShawn Guo .ops = &clk_branch2_ops, 1380496d1a13SShawn Guo }, 1381496d1a13SShawn Guo }, 1382496d1a13SShawn Guo }; 1383496d1a13SShawn Guo 1384496d1a13SShawn Guo static struct clk_branch gcc_cam_throttle_rt_clk = { 1385496d1a13SShawn Guo .halt_reg = 0x1706c, 1386496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 1387496d1a13SShawn Guo .hwcg_reg = 0x1706c, 1388496d1a13SShawn Guo .hwcg_bit = 1, 1389496d1a13SShawn Guo .clkr = { 1390496d1a13SShawn Guo .enable_reg = 0x79004, 1391496d1a13SShawn Guo .enable_mask = BIT(26), 1392496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1393496d1a13SShawn Guo .name = "gcc_cam_throttle_rt_clk", 1394496d1a13SShawn Guo .ops = &clk_branch2_ops, 1395496d1a13SShawn Guo }, 1396496d1a13SShawn Guo }, 1397496d1a13SShawn Guo }; 1398496d1a13SShawn Guo 1399496d1a13SShawn Guo static struct clk_branch gcc_camera_ahb_clk = { 1400496d1a13SShawn Guo .halt_reg = 0x17008, 1401496d1a13SShawn Guo .halt_check = BRANCH_HALT_DELAY, 1402496d1a13SShawn Guo .hwcg_reg = 0x17008, 1403496d1a13SShawn Guo .hwcg_bit = 1, 1404496d1a13SShawn Guo .clkr = { 1405496d1a13SShawn Guo .enable_reg = 0x17008, 1406496d1a13SShawn Guo .enable_mask = BIT(0), 1407496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1408496d1a13SShawn Guo .name = "gcc_camera_ahb_clk", 1409496d1a13SShawn Guo .flags = CLK_IS_CRITICAL, 1410496d1a13SShawn Guo .ops = &clk_branch2_ops, 1411496d1a13SShawn Guo }, 1412496d1a13SShawn Guo }, 1413496d1a13SShawn Guo }; 1414496d1a13SShawn Guo 1415496d1a13SShawn Guo static struct clk_branch gcc_camera_xo_clk = { 1416496d1a13SShawn Guo .halt_reg = 0x17028, 1417496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1418496d1a13SShawn Guo .clkr = { 1419496d1a13SShawn Guo .enable_reg = 0x17028, 1420496d1a13SShawn Guo .enable_mask = BIT(0), 1421496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1422496d1a13SShawn Guo .name = "gcc_camera_xo_clk", 1423496d1a13SShawn Guo .flags = CLK_IS_CRITICAL, 1424496d1a13SShawn Guo .ops = &clk_branch2_ops, 1425496d1a13SShawn Guo }, 1426496d1a13SShawn Guo }, 1427496d1a13SShawn Guo }; 1428496d1a13SShawn Guo 1429496d1a13SShawn Guo static struct clk_branch gcc_camss_axi_clk = { 1430496d1a13SShawn Guo .halt_reg = 0x58044, 1431496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1432496d1a13SShawn Guo .clkr = { 1433496d1a13SShawn Guo .enable_reg = 0x58044, 1434496d1a13SShawn Guo .enable_mask = BIT(0), 1435496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1436496d1a13SShawn Guo .name = "gcc_camss_axi_clk", 1437496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1438496d1a13SShawn Guo { &gcc_camss_axi_clk_src.clkr.hw }, 1439496d1a13SShawn Guo .num_parents = 1, 1440496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1441496d1a13SShawn Guo .ops = &clk_branch2_ops, 1442496d1a13SShawn Guo }, 1443496d1a13SShawn Guo }, 1444496d1a13SShawn Guo }; 1445496d1a13SShawn Guo 1446496d1a13SShawn Guo static struct clk_branch gcc_camss_camnoc_atb_clk = { 1447496d1a13SShawn Guo .halt_reg = 0x5804c, 1448496d1a13SShawn Guo .halt_check = BRANCH_HALT_DELAY, 1449496d1a13SShawn Guo .hwcg_reg = 0x5804c, 1450496d1a13SShawn Guo .hwcg_bit = 1, 1451496d1a13SShawn Guo .clkr = { 1452496d1a13SShawn Guo .enable_reg = 0x5804c, 1453496d1a13SShawn Guo .enable_mask = BIT(0), 1454496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1455496d1a13SShawn Guo .name = "gcc_camss_camnoc_atb_clk", 1456496d1a13SShawn Guo .ops = &clk_branch2_ops, 1457496d1a13SShawn Guo }, 1458496d1a13SShawn Guo }, 1459496d1a13SShawn Guo }; 1460496d1a13SShawn Guo 1461496d1a13SShawn Guo static struct clk_branch gcc_camss_camnoc_nts_xo_clk = { 1462496d1a13SShawn Guo .halt_reg = 0x58050, 1463496d1a13SShawn Guo .halt_check = BRANCH_HALT_DELAY, 1464496d1a13SShawn Guo .hwcg_reg = 0x58050, 1465496d1a13SShawn Guo .hwcg_bit = 1, 1466496d1a13SShawn Guo .clkr = { 1467496d1a13SShawn Guo .enable_reg = 0x58050, 1468496d1a13SShawn Guo .enable_mask = BIT(0), 1469496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1470496d1a13SShawn Guo .name = "gcc_camss_camnoc_nts_xo_clk", 1471496d1a13SShawn Guo .ops = &clk_branch2_ops, 1472496d1a13SShawn Guo }, 1473496d1a13SShawn Guo }, 1474496d1a13SShawn Guo }; 1475496d1a13SShawn Guo 1476496d1a13SShawn Guo static struct clk_branch gcc_camss_cci_0_clk = { 1477496d1a13SShawn Guo .halt_reg = 0x56018, 1478496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1479496d1a13SShawn Guo .clkr = { 1480496d1a13SShawn Guo .enable_reg = 0x56018, 1481496d1a13SShawn Guo .enable_mask = BIT(0), 1482496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1483496d1a13SShawn Guo .name = "gcc_camss_cci_0_clk", 1484496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1485496d1a13SShawn Guo { &gcc_camss_cci_clk_src.clkr.hw }, 1486496d1a13SShawn Guo .num_parents = 1, 1487496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1488496d1a13SShawn Guo .ops = &clk_branch2_ops, 1489496d1a13SShawn Guo }, 1490496d1a13SShawn Guo }, 1491496d1a13SShawn Guo }; 1492496d1a13SShawn Guo 1493496d1a13SShawn Guo static struct clk_branch gcc_camss_cphy_0_clk = { 1494496d1a13SShawn Guo .halt_reg = 0x52088, 1495496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1496496d1a13SShawn Guo .clkr = { 1497496d1a13SShawn Guo .enable_reg = 0x52088, 1498496d1a13SShawn Guo .enable_mask = BIT(0), 1499496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1500496d1a13SShawn Guo .name = "gcc_camss_cphy_0_clk", 1501496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1502496d1a13SShawn Guo { &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw }, 1503496d1a13SShawn Guo .num_parents = 1, 1504496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1505496d1a13SShawn Guo .ops = &clk_branch2_ops, 1506496d1a13SShawn Guo }, 1507496d1a13SShawn Guo }, 1508496d1a13SShawn Guo }; 1509496d1a13SShawn Guo 1510496d1a13SShawn Guo static struct clk_branch gcc_camss_cphy_1_clk = { 1511496d1a13SShawn Guo .halt_reg = 0x5208c, 1512496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1513496d1a13SShawn Guo .clkr = { 1514496d1a13SShawn Guo .enable_reg = 0x5208c, 1515496d1a13SShawn Guo .enable_mask = BIT(0), 1516496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1517496d1a13SShawn Guo .name = "gcc_camss_cphy_1_clk", 1518496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1519496d1a13SShawn Guo { &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw }, 1520496d1a13SShawn Guo .num_parents = 1, 1521496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1522496d1a13SShawn Guo .ops = &clk_branch2_ops, 1523496d1a13SShawn Guo }, 1524496d1a13SShawn Guo }, 1525496d1a13SShawn Guo }; 1526496d1a13SShawn Guo 1527496d1a13SShawn Guo static struct clk_branch gcc_camss_csi0phytimer_clk = { 1528496d1a13SShawn Guo .halt_reg = 0x45018, 1529496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1530496d1a13SShawn Guo .clkr = { 1531496d1a13SShawn Guo .enable_reg = 0x45018, 1532496d1a13SShawn Guo .enable_mask = BIT(0), 1533496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1534496d1a13SShawn Guo .name = "gcc_camss_csi0phytimer_clk", 1535496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1536496d1a13SShawn Guo { &gcc_camss_csi0phytimer_clk_src.clkr.hw }, 1537496d1a13SShawn Guo .num_parents = 1, 1538496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1539496d1a13SShawn Guo .ops = &clk_branch2_ops, 1540496d1a13SShawn Guo }, 1541496d1a13SShawn Guo }, 1542496d1a13SShawn Guo }; 1543496d1a13SShawn Guo 1544496d1a13SShawn Guo static struct clk_branch gcc_camss_csi1phytimer_clk = { 1545496d1a13SShawn Guo .halt_reg = 0x45034, 1546496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1547496d1a13SShawn Guo .clkr = { 1548496d1a13SShawn Guo .enable_reg = 0x45034, 1549496d1a13SShawn Guo .enable_mask = BIT(0), 1550496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1551496d1a13SShawn Guo .name = "gcc_camss_csi1phytimer_clk", 1552496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1553496d1a13SShawn Guo { &gcc_camss_csi1phytimer_clk_src.clkr.hw }, 1554496d1a13SShawn Guo .num_parents = 1, 1555496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1556496d1a13SShawn Guo .ops = &clk_branch2_ops, 1557496d1a13SShawn Guo }, 1558496d1a13SShawn Guo }, 1559496d1a13SShawn Guo }; 1560496d1a13SShawn Guo 1561496d1a13SShawn Guo static struct clk_branch gcc_camss_mclk0_clk = { 1562496d1a13SShawn Guo .halt_reg = 0x51018, 1563496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1564496d1a13SShawn Guo .clkr = { 1565496d1a13SShawn Guo .enable_reg = 0x51018, 1566496d1a13SShawn Guo .enable_mask = BIT(0), 1567496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1568496d1a13SShawn Guo .name = "gcc_camss_mclk0_clk", 1569496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1570496d1a13SShawn Guo { &gcc_camss_mclk0_clk_src.clkr.hw }, 1571496d1a13SShawn Guo .num_parents = 1, 1572496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1573496d1a13SShawn Guo .ops = &clk_branch2_ops, 1574496d1a13SShawn Guo }, 1575496d1a13SShawn Guo }, 1576496d1a13SShawn Guo }; 1577496d1a13SShawn Guo 1578496d1a13SShawn Guo static struct clk_branch gcc_camss_mclk1_clk = { 1579496d1a13SShawn Guo .halt_reg = 0x51034, 1580496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1581496d1a13SShawn Guo .clkr = { 1582496d1a13SShawn Guo .enable_reg = 0x51034, 1583496d1a13SShawn Guo .enable_mask = BIT(0), 1584496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1585496d1a13SShawn Guo .name = "gcc_camss_mclk1_clk", 1586496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1587496d1a13SShawn Guo { &gcc_camss_mclk1_clk_src.clkr.hw }, 1588496d1a13SShawn Guo .num_parents = 1, 1589496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1590496d1a13SShawn Guo .ops = &clk_branch2_ops, 1591496d1a13SShawn Guo }, 1592496d1a13SShawn Guo }, 1593496d1a13SShawn Guo }; 1594496d1a13SShawn Guo 1595496d1a13SShawn Guo static struct clk_branch gcc_camss_mclk2_clk = { 1596496d1a13SShawn Guo .halt_reg = 0x51050, 1597496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1598496d1a13SShawn Guo .clkr = { 1599496d1a13SShawn Guo .enable_reg = 0x51050, 1600496d1a13SShawn Guo .enable_mask = BIT(0), 1601496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1602496d1a13SShawn Guo .name = "gcc_camss_mclk2_clk", 1603496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1604496d1a13SShawn Guo { &gcc_camss_mclk2_clk_src.clkr.hw }, 1605496d1a13SShawn Guo .num_parents = 1, 1606496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1607496d1a13SShawn Guo .ops = &clk_branch2_ops, 1608496d1a13SShawn Guo }, 1609496d1a13SShawn Guo }, 1610496d1a13SShawn Guo }; 1611496d1a13SShawn Guo 1612496d1a13SShawn Guo static struct clk_branch gcc_camss_mclk3_clk = { 1613496d1a13SShawn Guo .halt_reg = 0x5106c, 1614496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1615496d1a13SShawn Guo .clkr = { 1616496d1a13SShawn Guo .enable_reg = 0x5106c, 1617496d1a13SShawn Guo .enable_mask = BIT(0), 1618496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1619496d1a13SShawn Guo .name = "gcc_camss_mclk3_clk", 1620496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1621496d1a13SShawn Guo { &gcc_camss_mclk3_clk_src.clkr.hw }, 1622496d1a13SShawn Guo .num_parents = 1, 1623496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1624496d1a13SShawn Guo .ops = &clk_branch2_ops, 1625496d1a13SShawn Guo }, 1626496d1a13SShawn Guo }, 1627496d1a13SShawn Guo }; 1628496d1a13SShawn Guo 1629496d1a13SShawn Guo static struct clk_branch gcc_camss_nrt_axi_clk = { 1630496d1a13SShawn Guo .halt_reg = 0x58054, 1631496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1632496d1a13SShawn Guo .clkr = { 1633496d1a13SShawn Guo .enable_reg = 0x58054, 1634496d1a13SShawn Guo .enable_mask = BIT(0), 1635496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1636496d1a13SShawn Guo .name = "gcc_camss_nrt_axi_clk", 1637496d1a13SShawn Guo .ops = &clk_branch2_ops, 1638496d1a13SShawn Guo }, 1639496d1a13SShawn Guo }, 1640496d1a13SShawn Guo }; 1641496d1a13SShawn Guo 1642496d1a13SShawn Guo static struct clk_branch gcc_camss_ope_ahb_clk = { 1643496d1a13SShawn Guo .halt_reg = 0x5503c, 1644496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1645496d1a13SShawn Guo .clkr = { 1646496d1a13SShawn Guo .enable_reg = 0x5503c, 1647496d1a13SShawn Guo .enable_mask = BIT(0), 1648496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1649496d1a13SShawn Guo .name = "gcc_camss_ope_ahb_clk", 1650496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1651496d1a13SShawn Guo { &gcc_camss_ope_ahb_clk_src.clkr.hw }, 1652496d1a13SShawn Guo .num_parents = 1, 1653496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1654496d1a13SShawn Guo .ops = &clk_branch2_ops, 1655496d1a13SShawn Guo }, 1656496d1a13SShawn Guo }, 1657496d1a13SShawn Guo }; 1658496d1a13SShawn Guo 1659496d1a13SShawn Guo static struct clk_branch gcc_camss_ope_clk = { 1660496d1a13SShawn Guo .halt_reg = 0x5501c, 1661496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1662496d1a13SShawn Guo .clkr = { 1663496d1a13SShawn Guo .enable_reg = 0x5501c, 1664496d1a13SShawn Guo .enable_mask = BIT(0), 1665496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1666496d1a13SShawn Guo .name = "gcc_camss_ope_clk", 1667496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1668496d1a13SShawn Guo { &gcc_camss_ope_clk_src.clkr.hw }, 1669496d1a13SShawn Guo .num_parents = 1, 1670496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1671496d1a13SShawn Guo .ops = &clk_branch2_ops, 1672496d1a13SShawn Guo }, 1673496d1a13SShawn Guo }, 1674496d1a13SShawn Guo }; 1675496d1a13SShawn Guo 1676496d1a13SShawn Guo static struct clk_branch gcc_camss_rt_axi_clk = { 1677496d1a13SShawn Guo .halt_reg = 0x5805c, 1678496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1679496d1a13SShawn Guo .clkr = { 1680496d1a13SShawn Guo .enable_reg = 0x5805c, 1681496d1a13SShawn Guo .enable_mask = BIT(0), 1682496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1683496d1a13SShawn Guo .name = "gcc_camss_rt_axi_clk", 1684496d1a13SShawn Guo .ops = &clk_branch2_ops, 1685496d1a13SShawn Guo }, 1686496d1a13SShawn Guo }, 1687496d1a13SShawn Guo }; 1688496d1a13SShawn Guo 1689496d1a13SShawn Guo static struct clk_branch gcc_camss_tfe_0_clk = { 1690496d1a13SShawn Guo .halt_reg = 0x5201c, 1691496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1692496d1a13SShawn Guo .clkr = { 1693496d1a13SShawn Guo .enable_reg = 0x5201c, 1694496d1a13SShawn Guo .enable_mask = BIT(0), 1695496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1696496d1a13SShawn Guo .name = "gcc_camss_tfe_0_clk", 1697496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1698496d1a13SShawn Guo { &gcc_camss_tfe_0_clk_src.clkr.hw }, 1699496d1a13SShawn Guo .num_parents = 1, 1700496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1701496d1a13SShawn Guo .ops = &clk_branch2_ops, 1702496d1a13SShawn Guo }, 1703496d1a13SShawn Guo }, 1704496d1a13SShawn Guo }; 1705496d1a13SShawn Guo 1706496d1a13SShawn Guo static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = { 1707496d1a13SShawn Guo .halt_reg = 0x5207c, 1708496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1709496d1a13SShawn Guo .clkr = { 1710496d1a13SShawn Guo .enable_reg = 0x5207c, 1711496d1a13SShawn Guo .enable_mask = BIT(0), 1712496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1713496d1a13SShawn Guo .name = "gcc_camss_tfe_0_cphy_rx_clk", 1714496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1715496d1a13SShawn Guo { &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw }, 1716496d1a13SShawn Guo .num_parents = 1, 1717496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1718496d1a13SShawn Guo .ops = &clk_branch2_ops, 1719496d1a13SShawn Guo }, 1720496d1a13SShawn Guo }, 1721496d1a13SShawn Guo }; 1722496d1a13SShawn Guo 1723496d1a13SShawn Guo static struct clk_branch gcc_camss_tfe_0_csid_clk = { 1724496d1a13SShawn Guo .halt_reg = 0x520ac, 1725496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1726496d1a13SShawn Guo .clkr = { 1727496d1a13SShawn Guo .enable_reg = 0x520ac, 1728496d1a13SShawn Guo .enable_mask = BIT(0), 1729496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1730496d1a13SShawn Guo .name = "gcc_camss_tfe_0_csid_clk", 1731496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1732496d1a13SShawn Guo { &gcc_camss_tfe_0_csid_clk_src.clkr.hw }, 1733496d1a13SShawn Guo .num_parents = 1, 1734496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1735496d1a13SShawn Guo .ops = &clk_branch2_ops, 1736496d1a13SShawn Guo }, 1737496d1a13SShawn Guo }, 1738496d1a13SShawn Guo }; 1739496d1a13SShawn Guo 1740496d1a13SShawn Guo static struct clk_branch gcc_camss_tfe_1_clk = { 1741496d1a13SShawn Guo .halt_reg = 0x5203c, 1742496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1743496d1a13SShawn Guo .clkr = { 1744496d1a13SShawn Guo .enable_reg = 0x5203c, 1745496d1a13SShawn Guo .enable_mask = BIT(0), 1746496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1747496d1a13SShawn Guo .name = "gcc_camss_tfe_1_clk", 1748496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1749496d1a13SShawn Guo { &gcc_camss_tfe_1_clk_src.clkr.hw }, 1750496d1a13SShawn Guo .num_parents = 1, 1751496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1752496d1a13SShawn Guo .ops = &clk_branch2_ops, 1753496d1a13SShawn Guo }, 1754496d1a13SShawn Guo }, 1755496d1a13SShawn Guo }; 1756496d1a13SShawn Guo 1757496d1a13SShawn Guo static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = { 1758496d1a13SShawn Guo .halt_reg = 0x52080, 1759496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1760496d1a13SShawn Guo .clkr = { 1761496d1a13SShawn Guo .enable_reg = 0x52080, 1762496d1a13SShawn Guo .enable_mask = BIT(0), 1763496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1764496d1a13SShawn Guo .name = "gcc_camss_tfe_1_cphy_rx_clk", 1765496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1766496d1a13SShawn Guo { &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw }, 1767496d1a13SShawn Guo .num_parents = 1, 1768496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1769496d1a13SShawn Guo .ops = &clk_branch2_ops, 1770496d1a13SShawn Guo }, 1771496d1a13SShawn Guo }, 1772496d1a13SShawn Guo }; 1773496d1a13SShawn Guo 1774496d1a13SShawn Guo static struct clk_branch gcc_camss_tfe_1_csid_clk = { 1775496d1a13SShawn Guo .halt_reg = 0x520cc, 1776496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1777496d1a13SShawn Guo .clkr = { 1778496d1a13SShawn Guo .enable_reg = 0x520cc, 1779496d1a13SShawn Guo .enable_mask = BIT(0), 1780496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1781496d1a13SShawn Guo .name = "gcc_camss_tfe_1_csid_clk", 1782496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1783496d1a13SShawn Guo { &gcc_camss_tfe_1_csid_clk_src.clkr.hw }, 1784496d1a13SShawn Guo .num_parents = 1, 1785496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1786496d1a13SShawn Guo .ops = &clk_branch2_ops, 1787496d1a13SShawn Guo }, 1788496d1a13SShawn Guo }, 1789496d1a13SShawn Guo }; 1790496d1a13SShawn Guo 1791496d1a13SShawn Guo static struct clk_branch gcc_camss_top_ahb_clk = { 1792496d1a13SShawn Guo .halt_reg = 0x58028, 1793496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1794496d1a13SShawn Guo .clkr = { 1795496d1a13SShawn Guo .enable_reg = 0x58028, 1796496d1a13SShawn Guo .enable_mask = BIT(0), 1797496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1798496d1a13SShawn Guo .name = "gcc_camss_top_ahb_clk", 1799496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1800496d1a13SShawn Guo { &gcc_camss_top_ahb_clk_src.clkr.hw }, 1801496d1a13SShawn Guo .num_parents = 1, 1802496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1803496d1a13SShawn Guo .ops = &clk_branch2_ops, 1804496d1a13SShawn Guo }, 1805496d1a13SShawn Guo }, 1806496d1a13SShawn Guo }; 1807496d1a13SShawn Guo 1808496d1a13SShawn Guo static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1809496d1a13SShawn Guo .halt_reg = 0x1a084, 1810496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1811496d1a13SShawn Guo .hwcg_reg = 0x1a084, 1812496d1a13SShawn Guo .hwcg_bit = 1, 1813496d1a13SShawn Guo .clkr = { 1814496d1a13SShawn Guo .enable_reg = 0x1a084, 1815496d1a13SShawn Guo .enable_mask = BIT(0), 1816496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1817496d1a13SShawn Guo .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1818496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1819496d1a13SShawn Guo { &gcc_usb30_prim_master_clk_src.clkr.hw }, 1820496d1a13SShawn Guo .num_parents = 1, 1821496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1822496d1a13SShawn Guo .ops = &clk_branch2_ops, 1823496d1a13SShawn Guo }, 1824496d1a13SShawn Guo }, 1825496d1a13SShawn Guo }; 1826496d1a13SShawn Guo 1827496d1a13SShawn Guo static struct clk_branch gcc_disp_ahb_clk = { 1828496d1a13SShawn Guo .halt_reg = 0x1700c, 1829496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1830496d1a13SShawn Guo .hwcg_reg = 0x1700c, 1831496d1a13SShawn Guo .hwcg_bit = 1, 1832496d1a13SShawn Guo .clkr = { 1833496d1a13SShawn Guo .enable_reg = 0x1700c, 1834496d1a13SShawn Guo .enable_mask = BIT(0), 1835496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1836496d1a13SShawn Guo .name = "gcc_disp_ahb_clk", 1837496d1a13SShawn Guo .flags = CLK_IS_CRITICAL, 1838496d1a13SShawn Guo .ops = &clk_branch2_ops, 1839496d1a13SShawn Guo }, 1840496d1a13SShawn Guo }, 1841496d1a13SShawn Guo }; 1842496d1a13SShawn Guo 1843496d1a13SShawn Guo static struct clk_regmap_div gcc_disp_gpll0_clk_src = { 1844496d1a13SShawn Guo .reg = 0x17058, 1845496d1a13SShawn Guo .shift = 0, 1846496d1a13SShawn Guo .width = 2, 1847496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data) { 1848496d1a13SShawn Guo .name = "gcc_disp_gpll0_clk_src", 1849496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 1850496d1a13SShawn Guo .num_parents = 1, 1851496d1a13SShawn Guo .ops = &clk_regmap_div_ops, 1852496d1a13SShawn Guo }, 1853496d1a13SShawn Guo }; 1854496d1a13SShawn Guo 1855496d1a13SShawn Guo static struct clk_branch gcc_disp_gpll0_div_clk_src = { 1856496d1a13SShawn Guo .halt_check = BRANCH_HALT_DELAY, 1857496d1a13SShawn Guo .clkr = { 1858496d1a13SShawn Guo .enable_reg = 0x79004, 1859496d1a13SShawn Guo .enable_mask = BIT(20), 1860496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1861496d1a13SShawn Guo .name = "gcc_disp_gpll0_div_clk_src", 1862496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1863496d1a13SShawn Guo { &gcc_disp_gpll0_clk_src.clkr.hw }, 1864496d1a13SShawn Guo .num_parents = 1, 1865496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1866496d1a13SShawn Guo .ops = &clk_branch2_ops, 1867496d1a13SShawn Guo }, 1868496d1a13SShawn Guo }, 1869496d1a13SShawn Guo }; 1870496d1a13SShawn Guo 1871496d1a13SShawn Guo static struct clk_branch gcc_disp_hf_axi_clk = { 1872496d1a13SShawn Guo .halt_reg = 0x17020, 1873496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1874496d1a13SShawn Guo .hwcg_reg = 0x17020, 1875496d1a13SShawn Guo .hwcg_bit = 1, 1876496d1a13SShawn Guo .clkr = { 1877496d1a13SShawn Guo .enable_reg = 0x17020, 1878496d1a13SShawn Guo .enable_mask = BIT(0), 1879496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1880496d1a13SShawn Guo .name = "gcc_disp_hf_axi_clk", 1881496d1a13SShawn Guo .ops = &clk_branch2_ops, 1882496d1a13SShawn Guo }, 1883496d1a13SShawn Guo }, 1884496d1a13SShawn Guo }; 1885496d1a13SShawn Guo 1886496d1a13SShawn Guo static struct clk_branch gcc_disp_throttle_core_clk = { 1887496d1a13SShawn Guo .halt_reg = 0x17064, 1888496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 1889496d1a13SShawn Guo .hwcg_reg = 0x17064, 1890496d1a13SShawn Guo .hwcg_bit = 1, 1891496d1a13SShawn Guo .clkr = { 1892496d1a13SShawn Guo .enable_reg = 0x7900c, 1893496d1a13SShawn Guo .enable_mask = BIT(5), 1894496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1895496d1a13SShawn Guo .name = "gcc_disp_throttle_core_clk", 1896496d1a13SShawn Guo .ops = &clk_branch2_ops, 1897496d1a13SShawn Guo }, 1898496d1a13SShawn Guo }, 1899496d1a13SShawn Guo }; 1900496d1a13SShawn Guo 1901496d1a13SShawn Guo static struct clk_branch gcc_disp_xo_clk = { 1902496d1a13SShawn Guo .halt_reg = 0x1702c, 1903496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1904496d1a13SShawn Guo .clkr = { 1905496d1a13SShawn Guo .enable_reg = 0x1702c, 1906496d1a13SShawn Guo .enable_mask = BIT(0), 1907496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1908496d1a13SShawn Guo .name = "gcc_disp_xo_clk", 1909496d1a13SShawn Guo .flags = CLK_IS_CRITICAL, 1910496d1a13SShawn Guo .ops = &clk_branch2_ops, 1911496d1a13SShawn Guo }, 1912496d1a13SShawn Guo }, 1913496d1a13SShawn Guo }; 1914496d1a13SShawn Guo 1915496d1a13SShawn Guo static struct clk_branch gcc_gp1_clk = { 1916496d1a13SShawn Guo .halt_reg = 0x4d000, 1917496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1918496d1a13SShawn Guo .clkr = { 1919496d1a13SShawn Guo .enable_reg = 0x4d000, 1920496d1a13SShawn Guo .enable_mask = BIT(0), 1921496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1922496d1a13SShawn Guo .name = "gcc_gp1_clk", 1923496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1924496d1a13SShawn Guo { &gcc_gp1_clk_src.clkr.hw }, 1925496d1a13SShawn Guo .num_parents = 1, 1926496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1927496d1a13SShawn Guo .ops = &clk_branch2_ops, 1928496d1a13SShawn Guo }, 1929496d1a13SShawn Guo }, 1930496d1a13SShawn Guo }; 1931496d1a13SShawn Guo 1932496d1a13SShawn Guo static struct clk_branch gcc_gp2_clk = { 1933496d1a13SShawn Guo .halt_reg = 0x4e000, 1934496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1935496d1a13SShawn Guo .clkr = { 1936496d1a13SShawn Guo .enable_reg = 0x4e000, 1937496d1a13SShawn Guo .enable_mask = BIT(0), 1938496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1939496d1a13SShawn Guo .name = "gcc_gp2_clk", 1940496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1941496d1a13SShawn Guo { &gcc_gp2_clk_src.clkr.hw }, 1942496d1a13SShawn Guo .num_parents = 1, 1943496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1944496d1a13SShawn Guo .ops = &clk_branch2_ops, 1945496d1a13SShawn Guo }, 1946496d1a13SShawn Guo }, 1947496d1a13SShawn Guo }; 1948496d1a13SShawn Guo 1949496d1a13SShawn Guo static struct clk_branch gcc_gp3_clk = { 1950496d1a13SShawn Guo .halt_reg = 0x4f000, 1951496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1952496d1a13SShawn Guo .clkr = { 1953496d1a13SShawn Guo .enable_reg = 0x4f000, 1954496d1a13SShawn Guo .enable_mask = BIT(0), 1955496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1956496d1a13SShawn Guo .name = "gcc_gp3_clk", 1957496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1958496d1a13SShawn Guo { &gcc_gp3_clk_src.clkr.hw }, 1959496d1a13SShawn Guo .num_parents = 1, 1960496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1961496d1a13SShawn Guo .ops = &clk_branch2_ops, 1962496d1a13SShawn Guo }, 1963496d1a13SShawn Guo }, 1964496d1a13SShawn Guo }; 1965496d1a13SShawn Guo 1966496d1a13SShawn Guo static struct clk_branch gcc_gpu_cfg_ahb_clk = { 1967496d1a13SShawn Guo .halt_reg = 0x36004, 1968496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1969496d1a13SShawn Guo .hwcg_reg = 0x36004, 1970496d1a13SShawn Guo .hwcg_bit = 1, 1971496d1a13SShawn Guo .clkr = { 1972496d1a13SShawn Guo .enable_reg = 0x36004, 1973496d1a13SShawn Guo .enable_mask = BIT(0), 1974496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1975496d1a13SShawn Guo .name = "gcc_gpu_cfg_ahb_clk", 1976496d1a13SShawn Guo .flags = CLK_IS_CRITICAL, 1977496d1a13SShawn Guo .ops = &clk_branch2_ops, 1978496d1a13SShawn Guo }, 1979496d1a13SShawn Guo }, 1980496d1a13SShawn Guo }; 1981496d1a13SShawn Guo 1982496d1a13SShawn Guo static struct clk_branch gcc_gpu_gpll0_clk_src = { 1983496d1a13SShawn Guo .halt_check = BRANCH_HALT_DELAY, 1984496d1a13SShawn Guo .clkr = { 1985496d1a13SShawn Guo .enable_reg = 0x79004, 1986496d1a13SShawn Guo .enable_mask = BIT(15), 1987496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1988496d1a13SShawn Guo .name = "gcc_gpu_gpll0_clk_src", 1989496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1990496d1a13SShawn Guo { &gpll0.clkr.hw }, 1991496d1a13SShawn Guo .num_parents = 1, 1992496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1993496d1a13SShawn Guo .ops = &clk_branch2_ops, 1994496d1a13SShawn Guo }, 1995496d1a13SShawn Guo }, 1996496d1a13SShawn Guo }; 1997496d1a13SShawn Guo 1998496d1a13SShawn Guo static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1999496d1a13SShawn Guo .halt_check = BRANCH_HALT_DELAY, 2000496d1a13SShawn Guo .clkr = { 2001496d1a13SShawn Guo .enable_reg = 0x79004, 2002496d1a13SShawn Guo .enable_mask = BIT(16), 2003496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2004496d1a13SShawn Guo .name = "gcc_gpu_gpll0_div_clk_src", 2005496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2006496d1a13SShawn Guo { &gpll0_out_aux2.clkr.hw }, 2007496d1a13SShawn Guo .num_parents = 1, 2008496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2009496d1a13SShawn Guo .ops = &clk_branch2_ops, 2010496d1a13SShawn Guo }, 2011496d1a13SShawn Guo }, 2012496d1a13SShawn Guo }; 2013496d1a13SShawn Guo 2014496d1a13SShawn Guo static struct clk_branch gcc_gpu_iref_clk = { 2015496d1a13SShawn Guo .halt_reg = 0x36100, 2016496d1a13SShawn Guo .halt_check = BRANCH_HALT_DELAY, 2017496d1a13SShawn Guo .clkr = { 2018496d1a13SShawn Guo .enable_reg = 0x36100, 2019496d1a13SShawn Guo .enable_mask = BIT(0), 2020496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2021496d1a13SShawn Guo .name = "gcc_gpu_iref_clk", 2022496d1a13SShawn Guo .ops = &clk_branch2_ops, 2023496d1a13SShawn Guo }, 2024496d1a13SShawn Guo }, 2025496d1a13SShawn Guo }; 2026496d1a13SShawn Guo 2027496d1a13SShawn Guo static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 2028496d1a13SShawn Guo .halt_reg = 0x3600c, 2029496d1a13SShawn Guo .halt_check = BRANCH_VOTED, 2030496d1a13SShawn Guo .hwcg_reg = 0x3600c, 2031496d1a13SShawn Guo .hwcg_bit = 1, 2032496d1a13SShawn Guo .clkr = { 2033496d1a13SShawn Guo .enable_reg = 0x3600c, 2034496d1a13SShawn Guo .enable_mask = BIT(0), 2035496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2036496d1a13SShawn Guo .name = "gcc_gpu_memnoc_gfx_clk", 2037496d1a13SShawn Guo .ops = &clk_branch2_ops, 2038496d1a13SShawn Guo }, 2039496d1a13SShawn Guo }, 2040496d1a13SShawn Guo }; 2041496d1a13SShawn Guo 2042496d1a13SShawn Guo static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2043496d1a13SShawn Guo .halt_reg = 0x36018, 2044496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2045496d1a13SShawn Guo .clkr = { 2046496d1a13SShawn Guo .enable_reg = 0x36018, 2047496d1a13SShawn Guo .enable_mask = BIT(0), 2048496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2049496d1a13SShawn Guo .name = "gcc_gpu_snoc_dvm_gfx_clk", 2050496d1a13SShawn Guo .ops = &clk_branch2_ops, 2051496d1a13SShawn Guo }, 2052496d1a13SShawn Guo }, 2053496d1a13SShawn Guo }; 2054496d1a13SShawn Guo 2055496d1a13SShawn Guo static struct clk_branch gcc_gpu_throttle_core_clk = { 2056496d1a13SShawn Guo .halt_reg = 0x36048, 2057496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2058496d1a13SShawn Guo .hwcg_reg = 0x36048, 2059496d1a13SShawn Guo .hwcg_bit = 1, 2060496d1a13SShawn Guo .clkr = { 2061496d1a13SShawn Guo .enable_reg = 0x79004, 2062496d1a13SShawn Guo .enable_mask = BIT(31), 2063496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2064496d1a13SShawn Guo .name = "gcc_gpu_throttle_core_clk", 2065496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2066496d1a13SShawn Guo .ops = &clk_branch2_ops, 2067496d1a13SShawn Guo }, 2068496d1a13SShawn Guo }, 2069496d1a13SShawn Guo }; 2070496d1a13SShawn Guo 2071496d1a13SShawn Guo static struct clk_branch gcc_pdm2_clk = { 2072496d1a13SShawn Guo .halt_reg = 0x2000c, 2073496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2074496d1a13SShawn Guo .clkr = { 2075496d1a13SShawn Guo .enable_reg = 0x2000c, 2076496d1a13SShawn Guo .enable_mask = BIT(0), 2077496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2078496d1a13SShawn Guo .name = "gcc_pdm2_clk", 2079496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2080496d1a13SShawn Guo { &gcc_pdm2_clk_src.clkr.hw }, 2081496d1a13SShawn Guo .num_parents = 1, 2082496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2083496d1a13SShawn Guo .ops = &clk_branch2_ops, 2084496d1a13SShawn Guo }, 2085496d1a13SShawn Guo }, 2086496d1a13SShawn Guo }; 2087496d1a13SShawn Guo 2088496d1a13SShawn Guo static struct clk_branch gcc_pdm_ahb_clk = { 2089496d1a13SShawn Guo .halt_reg = 0x20004, 2090496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2091496d1a13SShawn Guo .hwcg_reg = 0x20004, 2092496d1a13SShawn Guo .hwcg_bit = 1, 2093496d1a13SShawn Guo .clkr = { 2094496d1a13SShawn Guo .enable_reg = 0x20004, 2095496d1a13SShawn Guo .enable_mask = BIT(0), 2096496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2097496d1a13SShawn Guo .name = "gcc_pdm_ahb_clk", 2098496d1a13SShawn Guo .ops = &clk_branch2_ops, 2099496d1a13SShawn Guo }, 2100496d1a13SShawn Guo }, 2101496d1a13SShawn Guo }; 2102496d1a13SShawn Guo 2103496d1a13SShawn Guo static struct clk_branch gcc_pdm_xo4_clk = { 2104496d1a13SShawn Guo .halt_reg = 0x20008, 2105496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2106496d1a13SShawn Guo .clkr = { 2107496d1a13SShawn Guo .enable_reg = 0x20008, 2108496d1a13SShawn Guo .enable_mask = BIT(0), 2109496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2110496d1a13SShawn Guo .name = "gcc_pdm_xo4_clk", 2111496d1a13SShawn Guo .ops = &clk_branch2_ops, 2112496d1a13SShawn Guo }, 2113496d1a13SShawn Guo }, 2114496d1a13SShawn Guo }; 2115496d1a13SShawn Guo 2116496d1a13SShawn Guo static struct clk_branch gcc_pwm0_xo512_clk = { 2117496d1a13SShawn Guo .halt_reg = 0x2002c, 2118496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2119496d1a13SShawn Guo .clkr = { 2120496d1a13SShawn Guo .enable_reg = 0x2002c, 2121496d1a13SShawn Guo .enable_mask = BIT(0), 2122496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2123496d1a13SShawn Guo .name = "gcc_pwm0_xo512_clk", 2124496d1a13SShawn Guo .ops = &clk_branch2_ops, 2125496d1a13SShawn Guo }, 2126496d1a13SShawn Guo }, 2127496d1a13SShawn Guo }; 2128496d1a13SShawn Guo 2129496d1a13SShawn Guo static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2130496d1a13SShawn Guo .halt_reg = 0x17014, 2131496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2132496d1a13SShawn Guo .hwcg_reg = 0x17014, 2133496d1a13SShawn Guo .hwcg_bit = 1, 2134496d1a13SShawn Guo .clkr = { 2135496d1a13SShawn Guo .enable_reg = 0x7900c, 2136496d1a13SShawn Guo .enable_mask = BIT(0), 2137496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2138496d1a13SShawn Guo .name = "gcc_qmip_camera_nrt_ahb_clk", 2139496d1a13SShawn Guo .ops = &clk_branch2_ops, 2140496d1a13SShawn Guo }, 2141496d1a13SShawn Guo }, 2142496d1a13SShawn Guo }; 2143496d1a13SShawn Guo 2144496d1a13SShawn Guo static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2145496d1a13SShawn Guo .halt_reg = 0x17060, 2146496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2147496d1a13SShawn Guo .hwcg_reg = 0x17060, 2148496d1a13SShawn Guo .hwcg_bit = 1, 2149496d1a13SShawn Guo .clkr = { 2150496d1a13SShawn Guo .enable_reg = 0x7900c, 2151496d1a13SShawn Guo .enable_mask = BIT(2), 2152496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2153496d1a13SShawn Guo .name = "gcc_qmip_camera_rt_ahb_clk", 2154496d1a13SShawn Guo .ops = &clk_branch2_ops, 2155496d1a13SShawn Guo }, 2156496d1a13SShawn Guo }, 2157496d1a13SShawn Guo }; 2158496d1a13SShawn Guo 2159496d1a13SShawn Guo static struct clk_branch gcc_qmip_disp_ahb_clk = { 2160496d1a13SShawn Guo .halt_reg = 0x17018, 2161496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2162496d1a13SShawn Guo .hwcg_reg = 0x17018, 2163496d1a13SShawn Guo .hwcg_bit = 1, 2164496d1a13SShawn Guo .clkr = { 2165496d1a13SShawn Guo .enable_reg = 0x7900c, 2166496d1a13SShawn Guo .enable_mask = BIT(1), 2167496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2168496d1a13SShawn Guo .name = "gcc_qmip_disp_ahb_clk", 2169496d1a13SShawn Guo .ops = &clk_branch2_ops, 2170496d1a13SShawn Guo }, 2171496d1a13SShawn Guo }, 2172496d1a13SShawn Guo }; 2173496d1a13SShawn Guo 2174496d1a13SShawn Guo static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = { 2175496d1a13SShawn Guo .halt_reg = 0x36040, 2176496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2177496d1a13SShawn Guo .hwcg_reg = 0x36040, 2178496d1a13SShawn Guo .hwcg_bit = 1, 2179496d1a13SShawn Guo .clkr = { 2180496d1a13SShawn Guo .enable_reg = 0x7900c, 2181496d1a13SShawn Guo .enable_mask = BIT(4), 2182496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2183496d1a13SShawn Guo .name = "gcc_qmip_gpu_cfg_ahb_clk", 2184496d1a13SShawn Guo .ops = &clk_branch2_ops, 2185496d1a13SShawn Guo }, 2186496d1a13SShawn Guo }, 2187496d1a13SShawn Guo }; 2188496d1a13SShawn Guo 2189496d1a13SShawn Guo static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2190496d1a13SShawn Guo .halt_reg = 0x17010, 2191496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2192496d1a13SShawn Guo .hwcg_reg = 0x17010, 2193496d1a13SShawn Guo .hwcg_bit = 1, 2194496d1a13SShawn Guo .clkr = { 2195496d1a13SShawn Guo .enable_reg = 0x79004, 2196496d1a13SShawn Guo .enable_mask = BIT(25), 2197496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2198496d1a13SShawn Guo .name = "gcc_qmip_video_vcodec_ahb_clk", 2199496d1a13SShawn Guo .ops = &clk_branch2_ops, 2200496d1a13SShawn Guo }, 2201496d1a13SShawn Guo }, 2202496d1a13SShawn Guo }; 2203496d1a13SShawn Guo 2204496d1a13SShawn Guo static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2205496d1a13SShawn Guo .halt_reg = 0x1f014, 2206496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2207496d1a13SShawn Guo .clkr = { 2208496d1a13SShawn Guo .enable_reg = 0x7900c, 2209496d1a13SShawn Guo .enable_mask = BIT(9), 2210496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2211496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_core_2x_clk", 2212496d1a13SShawn Guo .ops = &clk_branch2_ops, 2213496d1a13SShawn Guo }, 2214496d1a13SShawn Guo }, 2215496d1a13SShawn Guo }; 2216496d1a13SShawn Guo 2217496d1a13SShawn Guo static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2218496d1a13SShawn Guo .halt_reg = 0x1f00c, 2219496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2220496d1a13SShawn Guo .clkr = { 2221496d1a13SShawn Guo .enable_reg = 0x7900c, 2222496d1a13SShawn Guo .enable_mask = BIT(8), 2223496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2224496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_core_clk", 2225496d1a13SShawn Guo .ops = &clk_branch2_ops, 2226496d1a13SShawn Guo }, 2227496d1a13SShawn Guo }, 2228496d1a13SShawn Guo }; 2229496d1a13SShawn Guo 2230496d1a13SShawn Guo static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2231496d1a13SShawn Guo .halt_reg = 0x1f144, 2232496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2233496d1a13SShawn Guo .clkr = { 2234496d1a13SShawn Guo .enable_reg = 0x7900c, 2235496d1a13SShawn Guo .enable_mask = BIT(10), 2236496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2237496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s0_clk", 2238496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2239496d1a13SShawn Guo { &gcc_qupv3_wrap0_s0_clk_src.clkr.hw }, 2240496d1a13SShawn Guo .num_parents = 1, 2241496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2242496d1a13SShawn Guo .ops = &clk_branch2_ops, 2243496d1a13SShawn Guo }, 2244496d1a13SShawn Guo }, 2245496d1a13SShawn Guo }; 2246496d1a13SShawn Guo 2247496d1a13SShawn Guo static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2248496d1a13SShawn Guo .halt_reg = 0x1f274, 2249496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2250496d1a13SShawn Guo .clkr = { 2251496d1a13SShawn Guo .enable_reg = 0x7900c, 2252496d1a13SShawn Guo .enable_mask = BIT(11), 2253496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2254496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s1_clk", 2255496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2256496d1a13SShawn Guo { &gcc_qupv3_wrap0_s1_clk_src.clkr.hw }, 2257496d1a13SShawn Guo .num_parents = 1, 2258496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2259496d1a13SShawn Guo .ops = &clk_branch2_ops, 2260496d1a13SShawn Guo }, 2261496d1a13SShawn Guo }, 2262496d1a13SShawn Guo }; 2263496d1a13SShawn Guo 2264496d1a13SShawn Guo static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2265496d1a13SShawn Guo .halt_reg = 0x1f3a4, 2266496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2267496d1a13SShawn Guo .clkr = { 2268496d1a13SShawn Guo .enable_reg = 0x7900c, 2269496d1a13SShawn Guo .enable_mask = BIT(12), 2270496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2271496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s2_clk", 2272496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2273496d1a13SShawn Guo { &gcc_qupv3_wrap0_s2_clk_src.clkr.hw }, 2274496d1a13SShawn Guo .num_parents = 1, 2275496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2276496d1a13SShawn Guo .ops = &clk_branch2_ops, 2277496d1a13SShawn Guo }, 2278496d1a13SShawn Guo }, 2279496d1a13SShawn Guo }; 2280496d1a13SShawn Guo 2281496d1a13SShawn Guo static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2282496d1a13SShawn Guo .halt_reg = 0x1f4d4, 2283496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2284496d1a13SShawn Guo .clkr = { 2285496d1a13SShawn Guo .enable_reg = 0x7900c, 2286496d1a13SShawn Guo .enable_mask = BIT(13), 2287496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2288496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s3_clk", 2289496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2290496d1a13SShawn Guo { &gcc_qupv3_wrap0_s3_clk_src.clkr.hw }, 2291496d1a13SShawn Guo .num_parents = 1, 2292496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2293496d1a13SShawn Guo .ops = &clk_branch2_ops, 2294496d1a13SShawn Guo }, 2295496d1a13SShawn Guo }, 2296496d1a13SShawn Guo }; 2297496d1a13SShawn Guo 2298496d1a13SShawn Guo static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2299496d1a13SShawn Guo .halt_reg = 0x1f604, 2300496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2301496d1a13SShawn Guo .clkr = { 2302496d1a13SShawn Guo .enable_reg = 0x7900c, 2303496d1a13SShawn Guo .enable_mask = BIT(14), 2304496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2305496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s4_clk", 2306496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2307496d1a13SShawn Guo { &gcc_qupv3_wrap0_s4_clk_src.clkr.hw }, 2308496d1a13SShawn Guo .num_parents = 1, 2309496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2310496d1a13SShawn Guo .ops = &clk_branch2_ops, 2311496d1a13SShawn Guo }, 2312496d1a13SShawn Guo }, 2313496d1a13SShawn Guo }; 2314496d1a13SShawn Guo 2315496d1a13SShawn Guo static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2316496d1a13SShawn Guo .halt_reg = 0x1f734, 2317496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2318496d1a13SShawn Guo .clkr = { 2319496d1a13SShawn Guo .enable_reg = 0x7900c, 2320496d1a13SShawn Guo .enable_mask = BIT(15), 2321496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2322496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s5_clk", 2323496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2324496d1a13SShawn Guo { &gcc_qupv3_wrap0_s5_clk_src.clkr.hw }, 2325496d1a13SShawn Guo .num_parents = 1, 2326496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2327496d1a13SShawn Guo .ops = &clk_branch2_ops, 2328496d1a13SShawn Guo }, 2329496d1a13SShawn Guo }, 2330496d1a13SShawn Guo }; 2331496d1a13SShawn Guo 2332496d1a13SShawn Guo static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2333496d1a13SShawn Guo .halt_reg = 0x1f004, 2334496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2335496d1a13SShawn Guo .hwcg_reg = 0x1f004, 2336496d1a13SShawn Guo .hwcg_bit = 1, 2337496d1a13SShawn Guo .clkr = { 2338496d1a13SShawn Guo .enable_reg = 0x7900c, 2339496d1a13SShawn Guo .enable_mask = BIT(6), 2340496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2341496d1a13SShawn Guo .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2342496d1a13SShawn Guo .ops = &clk_branch2_ops, 2343496d1a13SShawn Guo }, 2344496d1a13SShawn Guo }, 2345496d1a13SShawn Guo }; 2346496d1a13SShawn Guo 2347496d1a13SShawn Guo static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2348496d1a13SShawn Guo .halt_reg = 0x1f008, 2349496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2350496d1a13SShawn Guo .hwcg_reg = 0x1f008, 2351496d1a13SShawn Guo .hwcg_bit = 1, 2352496d1a13SShawn Guo .clkr = { 2353496d1a13SShawn Guo .enable_reg = 0x7900c, 2354496d1a13SShawn Guo .enable_mask = BIT(7), 2355496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2356496d1a13SShawn Guo .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2357496d1a13SShawn Guo .ops = &clk_branch2_ops, 2358496d1a13SShawn Guo }, 2359496d1a13SShawn Guo }, 2360496d1a13SShawn Guo }; 2361496d1a13SShawn Guo 2362496d1a13SShawn Guo static struct clk_branch gcc_sdcc1_ahb_clk = { 2363496d1a13SShawn Guo .halt_reg = 0x38008, 2364496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2365496d1a13SShawn Guo .clkr = { 2366496d1a13SShawn Guo .enable_reg = 0x38008, 2367496d1a13SShawn Guo .enable_mask = BIT(0), 2368496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2369496d1a13SShawn Guo .name = "gcc_sdcc1_ahb_clk", 2370496d1a13SShawn Guo .ops = &clk_branch2_ops, 2371496d1a13SShawn Guo }, 2372496d1a13SShawn Guo }, 2373496d1a13SShawn Guo }; 2374496d1a13SShawn Guo 2375496d1a13SShawn Guo static struct clk_branch gcc_sdcc1_apps_clk = { 2376496d1a13SShawn Guo .halt_reg = 0x38004, 2377496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2378496d1a13SShawn Guo .clkr = { 2379496d1a13SShawn Guo .enable_reg = 0x38004, 2380496d1a13SShawn Guo .enable_mask = BIT(0), 2381496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2382496d1a13SShawn Guo .name = "gcc_sdcc1_apps_clk", 2383496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2384496d1a13SShawn Guo { &gcc_sdcc1_apps_clk_src.clkr.hw }, 2385496d1a13SShawn Guo .num_parents = 1, 2386496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2387496d1a13SShawn Guo .ops = &clk_branch2_ops, 2388496d1a13SShawn Guo }, 2389496d1a13SShawn Guo }, 2390496d1a13SShawn Guo }; 2391496d1a13SShawn Guo 2392496d1a13SShawn Guo static struct clk_branch gcc_sdcc1_ice_core_clk = { 2393496d1a13SShawn Guo .halt_reg = 0x3800c, 2394496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2395496d1a13SShawn Guo .hwcg_reg = 0x3800c, 2396496d1a13SShawn Guo .hwcg_bit = 1, 2397496d1a13SShawn Guo .clkr = { 2398496d1a13SShawn Guo .enable_reg = 0x3800c, 2399496d1a13SShawn Guo .enable_mask = BIT(0), 2400496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2401496d1a13SShawn Guo .name = "gcc_sdcc1_ice_core_clk", 2402496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2403496d1a13SShawn Guo { &gcc_sdcc1_ice_core_clk_src.clkr.hw }, 2404496d1a13SShawn Guo .num_parents = 1, 2405496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2406496d1a13SShawn Guo .ops = &clk_branch2_ops, 2407496d1a13SShawn Guo }, 2408496d1a13SShawn Guo }, 2409496d1a13SShawn Guo }; 2410496d1a13SShawn Guo 2411496d1a13SShawn Guo static struct clk_branch gcc_sdcc2_ahb_clk = { 2412496d1a13SShawn Guo .halt_reg = 0x1e008, 2413496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2414496d1a13SShawn Guo .clkr = { 2415496d1a13SShawn Guo .enable_reg = 0x1e008, 2416496d1a13SShawn Guo .enable_mask = BIT(0), 2417496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2418496d1a13SShawn Guo .name = "gcc_sdcc2_ahb_clk", 2419496d1a13SShawn Guo .ops = &clk_branch2_ops, 2420496d1a13SShawn Guo }, 2421496d1a13SShawn Guo }, 2422496d1a13SShawn Guo }; 2423496d1a13SShawn Guo 2424496d1a13SShawn Guo static struct clk_branch gcc_sdcc2_apps_clk = { 2425496d1a13SShawn Guo .halt_reg = 0x1e004, 2426496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2427496d1a13SShawn Guo .clkr = { 2428496d1a13SShawn Guo .enable_reg = 0x1e004, 2429496d1a13SShawn Guo .enable_mask = BIT(0), 2430496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2431496d1a13SShawn Guo .name = "gcc_sdcc2_apps_clk", 2432496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2433496d1a13SShawn Guo { &gcc_sdcc2_apps_clk_src.clkr.hw }, 2434496d1a13SShawn Guo .num_parents = 1, 2435496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2436496d1a13SShawn Guo .ops = &clk_branch2_ops, 2437496d1a13SShawn Guo }, 2438496d1a13SShawn Guo }, 2439496d1a13SShawn Guo }; 2440496d1a13SShawn Guo 2441496d1a13SShawn Guo static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 2442496d1a13SShawn Guo .halt_reg = 0x2b06c, 2443496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2444496d1a13SShawn Guo .hwcg_reg = 0x2b06c, 2445496d1a13SShawn Guo .hwcg_bit = 1, 2446496d1a13SShawn Guo .clkr = { 2447496d1a13SShawn Guo .enable_reg = 0x79004, 2448496d1a13SShawn Guo .enable_mask = BIT(0), 2449496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2450496d1a13SShawn Guo .name = "gcc_sys_noc_cpuss_ahb_clk", 2451496d1a13SShawn Guo .flags = CLK_IS_CRITICAL, 2452496d1a13SShawn Guo .ops = &clk_branch2_ops, 2453496d1a13SShawn Guo }, 2454496d1a13SShawn Guo }, 2455496d1a13SShawn Guo }; 2456496d1a13SShawn Guo 2457496d1a13SShawn Guo static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { 2458496d1a13SShawn Guo .halt_reg = 0x1a080, 2459496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2460496d1a13SShawn Guo .hwcg_reg = 0x1a080, 2461496d1a13SShawn Guo .hwcg_bit = 1, 2462496d1a13SShawn Guo .clkr = { 2463496d1a13SShawn Guo .enable_reg = 0x1a080, 2464496d1a13SShawn Guo .enable_mask = BIT(0), 2465496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2466496d1a13SShawn Guo .name = "gcc_sys_noc_usb3_prim_axi_clk", 2467496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2468496d1a13SShawn Guo { &gcc_usb30_prim_master_clk_src.clkr.hw }, 2469496d1a13SShawn Guo .num_parents = 1, 2470496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2471496d1a13SShawn Guo .ops = &clk_branch2_ops, 2472496d1a13SShawn Guo }, 2473496d1a13SShawn Guo }, 2474496d1a13SShawn Guo }; 2475496d1a13SShawn Guo 2476496d1a13SShawn Guo static struct clk_branch gcc_usb30_prim_master_clk = { 2477496d1a13SShawn Guo .halt_reg = 0x1a010, 2478496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2479496d1a13SShawn Guo .clkr = { 2480496d1a13SShawn Guo .enable_reg = 0x1a010, 2481496d1a13SShawn Guo .enable_mask = BIT(0), 2482496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2483496d1a13SShawn Guo .name = "gcc_usb30_prim_master_clk", 2484496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2485496d1a13SShawn Guo { &gcc_usb30_prim_master_clk_src.clkr.hw }, 2486496d1a13SShawn Guo .num_parents = 1, 2487496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2488496d1a13SShawn Guo .ops = &clk_branch2_ops, 2489496d1a13SShawn Guo }, 2490496d1a13SShawn Guo }, 2491496d1a13SShawn Guo }; 2492496d1a13SShawn Guo 2493496d1a13SShawn Guo static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2494496d1a13SShawn Guo .halt_reg = 0x1a018, 2495496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2496496d1a13SShawn Guo .clkr = { 2497496d1a13SShawn Guo .enable_reg = 0x1a018, 2498496d1a13SShawn Guo .enable_mask = BIT(0), 2499496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2500496d1a13SShawn Guo .name = "gcc_usb30_prim_mock_utmi_clk", 2501496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2502496d1a13SShawn Guo { &gcc_usb30_prim_mock_utmi_postdiv.clkr.hw }, 2503496d1a13SShawn Guo .num_parents = 1, 2504496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2505496d1a13SShawn Guo .ops = &clk_branch2_ops, 2506496d1a13SShawn Guo }, 2507496d1a13SShawn Guo }, 2508496d1a13SShawn Guo }; 2509496d1a13SShawn Guo 2510496d1a13SShawn Guo static struct clk_branch gcc_usb30_prim_sleep_clk = { 2511496d1a13SShawn Guo .halt_reg = 0x1a014, 2512496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2513496d1a13SShawn Guo .clkr = { 2514496d1a13SShawn Guo .enable_reg = 0x1a014, 2515496d1a13SShawn Guo .enable_mask = BIT(0), 2516496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2517496d1a13SShawn Guo .name = "gcc_usb30_prim_sleep_clk", 2518496d1a13SShawn Guo .ops = &clk_branch2_ops, 2519496d1a13SShawn Guo }, 2520496d1a13SShawn Guo }, 2521496d1a13SShawn Guo }; 2522496d1a13SShawn Guo 2523496d1a13SShawn Guo static struct clk_branch gcc_usb3_prim_clkref_clk = { 2524496d1a13SShawn Guo .halt_reg = 0x9f000, 2525496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2526496d1a13SShawn Guo .clkr = { 2527496d1a13SShawn Guo .enable_reg = 0x9f000, 2528496d1a13SShawn Guo .enable_mask = BIT(0), 2529496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2530496d1a13SShawn Guo .name = "gcc_usb3_prim_clkref_clk", 2531496d1a13SShawn Guo .ops = &clk_branch2_ops, 2532496d1a13SShawn Guo }, 2533496d1a13SShawn Guo }, 2534496d1a13SShawn Guo }; 2535496d1a13SShawn Guo 2536496d1a13SShawn Guo static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2537496d1a13SShawn Guo .halt_reg = 0x1a054, 2538496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2539496d1a13SShawn Guo .clkr = { 2540496d1a13SShawn Guo .enable_reg = 0x1a054, 2541496d1a13SShawn Guo .enable_mask = BIT(0), 2542496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2543496d1a13SShawn Guo .name = "gcc_usb3_prim_phy_com_aux_clk", 2544496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2545496d1a13SShawn Guo { &gcc_usb3_prim_phy_aux_clk_src.clkr.hw }, 2546496d1a13SShawn Guo .num_parents = 1, 2547496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2548496d1a13SShawn Guo .ops = &clk_branch2_ops, 2549496d1a13SShawn Guo }, 2550496d1a13SShawn Guo }, 2551496d1a13SShawn Guo }; 2552496d1a13SShawn Guo 2553496d1a13SShawn Guo static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2554496d1a13SShawn Guo .halt_reg = 0x1a058, 2555496d1a13SShawn Guo .halt_check = BRANCH_HALT_SKIP, 2556496d1a13SShawn Guo .hwcg_reg = 0x1a058, 2557496d1a13SShawn Guo .hwcg_bit = 1, 2558496d1a13SShawn Guo .clkr = { 2559496d1a13SShawn Guo .enable_reg = 0x1a058, 2560496d1a13SShawn Guo .enable_mask = BIT(0), 2561496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2562496d1a13SShawn Guo .name = "gcc_usb3_prim_phy_pipe_clk", 2563496d1a13SShawn Guo .ops = &clk_branch2_ops, 2564496d1a13SShawn Guo }, 2565496d1a13SShawn Guo }, 2566496d1a13SShawn Guo }; 2567496d1a13SShawn Guo 2568496d1a13SShawn Guo static struct clk_branch gcc_vcodec0_axi_clk = { 2569496d1a13SShawn Guo .halt_reg = 0x6e008, 2570496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2571496d1a13SShawn Guo .clkr = { 2572496d1a13SShawn Guo .enable_reg = 0x6e008, 2573496d1a13SShawn Guo .enable_mask = BIT(0), 2574496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2575496d1a13SShawn Guo .name = "gcc_vcodec0_axi_clk", 2576496d1a13SShawn Guo .ops = &clk_branch2_ops, 2577496d1a13SShawn Guo }, 2578496d1a13SShawn Guo }, 2579496d1a13SShawn Guo }; 2580496d1a13SShawn Guo 2581496d1a13SShawn Guo static struct clk_branch gcc_venus_ahb_clk = { 2582496d1a13SShawn Guo .halt_reg = 0x6e010, 2583496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2584496d1a13SShawn Guo .clkr = { 2585496d1a13SShawn Guo .enable_reg = 0x6e010, 2586496d1a13SShawn Guo .enable_mask = BIT(0), 2587496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2588496d1a13SShawn Guo .name = "gcc_venus_ahb_clk", 2589496d1a13SShawn Guo .ops = &clk_branch2_ops, 2590496d1a13SShawn Guo }, 2591496d1a13SShawn Guo }, 2592496d1a13SShawn Guo }; 2593496d1a13SShawn Guo 2594496d1a13SShawn Guo static struct clk_branch gcc_venus_ctl_axi_clk = { 2595496d1a13SShawn Guo .halt_reg = 0x6e004, 2596496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2597496d1a13SShawn Guo .clkr = { 2598496d1a13SShawn Guo .enable_reg = 0x6e004, 2599496d1a13SShawn Guo .enable_mask = BIT(0), 2600496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2601496d1a13SShawn Guo .name = "gcc_venus_ctl_axi_clk", 2602496d1a13SShawn Guo .ops = &clk_branch2_ops, 2603496d1a13SShawn Guo }, 2604496d1a13SShawn Guo }, 2605496d1a13SShawn Guo }; 2606496d1a13SShawn Guo 2607496d1a13SShawn Guo static struct clk_branch gcc_video_ahb_clk = { 2608496d1a13SShawn Guo .halt_reg = 0x17004, 2609496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2610496d1a13SShawn Guo .hwcg_reg = 0x17004, 2611496d1a13SShawn Guo .hwcg_bit = 1, 2612496d1a13SShawn Guo .clkr = { 2613496d1a13SShawn Guo .enable_reg = 0x17004, 2614496d1a13SShawn Guo .enable_mask = BIT(0), 2615496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2616496d1a13SShawn Guo .name = "gcc_video_ahb_clk", 2617496d1a13SShawn Guo .ops = &clk_branch2_ops, 2618496d1a13SShawn Guo }, 2619496d1a13SShawn Guo }, 2620496d1a13SShawn Guo }; 2621496d1a13SShawn Guo 2622496d1a13SShawn Guo static struct clk_branch gcc_video_axi0_clk = { 2623496d1a13SShawn Guo .halt_reg = 0x1701c, 2624496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2625496d1a13SShawn Guo .hwcg_reg = 0x1701c, 2626496d1a13SShawn Guo .hwcg_bit = 1, 2627496d1a13SShawn Guo .clkr = { 2628496d1a13SShawn Guo .enable_reg = 0x1701c, 2629496d1a13SShawn Guo .enable_mask = BIT(0), 2630496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2631496d1a13SShawn Guo .name = "gcc_video_axi0_clk", 2632496d1a13SShawn Guo .ops = &clk_branch2_ops, 2633496d1a13SShawn Guo }, 2634496d1a13SShawn Guo }, 2635496d1a13SShawn Guo }; 2636496d1a13SShawn Guo 2637496d1a13SShawn Guo static struct clk_branch gcc_video_throttle_core_clk = { 2638496d1a13SShawn Guo .halt_reg = 0x17068, 2639496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2640496d1a13SShawn Guo .hwcg_reg = 0x17068, 2641496d1a13SShawn Guo .hwcg_bit = 1, 2642496d1a13SShawn Guo .clkr = { 2643496d1a13SShawn Guo .enable_reg = 0x79004, 2644496d1a13SShawn Guo .enable_mask = BIT(28), 2645496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2646496d1a13SShawn Guo .name = "gcc_video_throttle_core_clk", 2647496d1a13SShawn Guo .ops = &clk_branch2_ops, 2648496d1a13SShawn Guo }, 2649496d1a13SShawn Guo }, 2650496d1a13SShawn Guo }; 2651496d1a13SShawn Guo 2652496d1a13SShawn Guo static struct clk_branch gcc_video_vcodec0_sys_clk = { 2653496d1a13SShawn Guo .halt_reg = 0x580a4, 2654496d1a13SShawn Guo .halt_check = BRANCH_HALT_DELAY, 2655496d1a13SShawn Guo .hwcg_reg = 0x580a4, 2656496d1a13SShawn Guo .hwcg_bit = 1, 2657496d1a13SShawn Guo .clkr = { 2658496d1a13SShawn Guo .enable_reg = 0x580a4, 2659496d1a13SShawn Guo .enable_mask = BIT(0), 2660496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2661496d1a13SShawn Guo .name = "gcc_video_vcodec0_sys_clk", 2662496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2663496d1a13SShawn Guo { &gcc_video_venus_clk_src.clkr.hw }, 2664496d1a13SShawn Guo .num_parents = 1, 2665496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2666496d1a13SShawn Guo .ops = &clk_branch2_ops, 2667496d1a13SShawn Guo }, 2668496d1a13SShawn Guo }, 2669496d1a13SShawn Guo }; 2670496d1a13SShawn Guo 2671496d1a13SShawn Guo static struct clk_branch gcc_video_venus_ctl_clk = { 2672496d1a13SShawn Guo .halt_reg = 0x5808c, 2673496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2674496d1a13SShawn Guo .clkr = { 2675496d1a13SShawn Guo .enable_reg = 0x5808c, 2676496d1a13SShawn Guo .enable_mask = BIT(0), 2677496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2678496d1a13SShawn Guo .name = "gcc_video_venus_ctl_clk", 2679496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2680496d1a13SShawn Guo { &gcc_video_venus_clk_src.clkr.hw }, 2681496d1a13SShawn Guo .num_parents = 1, 2682496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2683496d1a13SShawn Guo .ops = &clk_branch2_ops, 2684496d1a13SShawn Guo }, 2685496d1a13SShawn Guo }, 2686496d1a13SShawn Guo }; 2687496d1a13SShawn Guo 2688496d1a13SShawn Guo static struct clk_branch gcc_video_xo_clk = { 2689496d1a13SShawn Guo .halt_reg = 0x17024, 2690496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2691496d1a13SShawn Guo .clkr = { 2692496d1a13SShawn Guo .enable_reg = 0x17024, 2693496d1a13SShawn Guo .enable_mask = BIT(0), 2694496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2695496d1a13SShawn Guo .name = "gcc_video_xo_clk", 2696496d1a13SShawn Guo .ops = &clk_branch2_ops, 2697496d1a13SShawn Guo }, 2698496d1a13SShawn Guo }, 2699496d1a13SShawn Guo }; 2700496d1a13SShawn Guo 2701496d1a13SShawn Guo static struct gdsc gcc_camss_top_gdsc = { 2702496d1a13SShawn Guo .gdscr = 0x58004, 2703496d1a13SShawn Guo .pd = { 2704496d1a13SShawn Guo .name = "gcc_camss_top", 2705496d1a13SShawn Guo }, 2706496d1a13SShawn Guo .pwrsts = PWRSTS_OFF_ON, 2707496d1a13SShawn Guo }; 2708496d1a13SShawn Guo 2709496d1a13SShawn Guo static struct gdsc gcc_usb30_prim_gdsc = { 2710496d1a13SShawn Guo .gdscr = 0x1a004, 2711496d1a13SShawn Guo .pd = { 2712496d1a13SShawn Guo .name = "gcc_usb30_prim", 2713496d1a13SShawn Guo }, 2714496d1a13SShawn Guo .pwrsts = PWRSTS_OFF_ON, 2715496d1a13SShawn Guo }; 2716496d1a13SShawn Guo 2717496d1a13SShawn Guo static struct gdsc gcc_vcodec0_gdsc = { 2718496d1a13SShawn Guo .gdscr = 0x58098, 2719496d1a13SShawn Guo .pd = { 2720496d1a13SShawn Guo .name = "gcc_vcodec0", 2721496d1a13SShawn Guo }, 2722496d1a13SShawn Guo .pwrsts = PWRSTS_OFF_ON, 2723496d1a13SShawn Guo }; 2724496d1a13SShawn Guo 2725496d1a13SShawn Guo static struct gdsc gcc_venus_gdsc = { 2726496d1a13SShawn Guo .gdscr = 0x5807c, 2727496d1a13SShawn Guo .pd = { 2728496d1a13SShawn Guo .name = "gcc_venus", 2729496d1a13SShawn Guo }, 2730496d1a13SShawn Guo .pwrsts = PWRSTS_OFF_ON, 2731496d1a13SShawn Guo }; 2732496d1a13SShawn Guo 2733496d1a13SShawn Guo static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = { 2734496d1a13SShawn Guo .gdscr = 0x7d060, 2735496d1a13SShawn Guo .pd = { 2736496d1a13SShawn Guo .name = "hlos1_vote_turing_mmu_tbu1", 2737496d1a13SShawn Guo }, 2738496d1a13SShawn Guo .pwrsts = PWRSTS_OFF_ON, 2739496d1a13SShawn Guo .flags = VOTABLE, 2740496d1a13SShawn Guo }; 2741496d1a13SShawn Guo 2742496d1a13SShawn Guo static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { 2743496d1a13SShawn Guo .gdscr = 0x7d07c, 2744496d1a13SShawn Guo .pd = { 2745496d1a13SShawn Guo .name = "hlos1_vote_turing_mmu_tbu0", 2746496d1a13SShawn Guo }, 2747496d1a13SShawn Guo .pwrsts = PWRSTS_OFF_ON, 2748496d1a13SShawn Guo .flags = VOTABLE, 2749496d1a13SShawn Guo }; 2750496d1a13SShawn Guo 2751496d1a13SShawn Guo static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = { 2752496d1a13SShawn Guo .gdscr = 0x7d074, 2753496d1a13SShawn Guo .pd = { 2754496d1a13SShawn Guo .name = "hlos1_vote_mm_snoc_mmu_tbu_rt", 2755496d1a13SShawn Guo }, 2756496d1a13SShawn Guo .pwrsts = PWRSTS_OFF_ON, 2757496d1a13SShawn Guo .flags = VOTABLE, 2758496d1a13SShawn Guo }; 2759496d1a13SShawn Guo 2760496d1a13SShawn Guo static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = { 2761496d1a13SShawn Guo .gdscr = 0x7d078, 2762496d1a13SShawn Guo .pd = { 2763496d1a13SShawn Guo .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt", 2764496d1a13SShawn Guo }, 2765496d1a13SShawn Guo .pwrsts = PWRSTS_OFF_ON, 2766496d1a13SShawn Guo .flags = VOTABLE, 2767496d1a13SShawn Guo }; 2768496d1a13SShawn Guo 2769496d1a13SShawn Guo static struct clk_regmap *gcc_qcm2290_clocks[] = { 2770496d1a13SShawn Guo [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr, 2771496d1a13SShawn Guo [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr, 2772496d1a13SShawn Guo [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr, 2773496d1a13SShawn Guo [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2774496d1a13SShawn Guo [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, 2775496d1a13SShawn Guo [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, 2776496d1a13SShawn Guo [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 2777496d1a13SShawn Guo [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 2778496d1a13SShawn Guo [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, 2779496d1a13SShawn Guo [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, 2780496d1a13SShawn Guo [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr, 2781496d1a13SShawn Guo [GCC_CAMSS_CAMNOC_NTS_XO_CLK] = &gcc_camss_camnoc_nts_xo_clk.clkr, 2782496d1a13SShawn Guo [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr, 2783496d1a13SShawn Guo [GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr, 2784496d1a13SShawn Guo [GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr, 2785496d1a13SShawn Guo [GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr, 2786496d1a13SShawn Guo [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 2787496d1a13SShawn Guo [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr, 2788496d1a13SShawn Guo [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, 2789496d1a13SShawn Guo [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr, 2790496d1a13SShawn Guo [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 2791496d1a13SShawn Guo [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr, 2792496d1a13SShawn Guo [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 2793496d1a13SShawn Guo [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr, 2794496d1a13SShawn Guo [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, 2795496d1a13SShawn Guo [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr, 2796496d1a13SShawn Guo [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr, 2797496d1a13SShawn Guo [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr, 2798496d1a13SShawn Guo [GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr, 2799496d1a13SShawn Guo [GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr, 2800496d1a13SShawn Guo [GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr, 2801496d1a13SShawn Guo [GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr, 2802496d1a13SShawn Guo [GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr, 2803496d1a13SShawn Guo [GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr, 2804496d1a13SShawn Guo [GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr, 2805496d1a13SShawn Guo [GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr, 2806496d1a13SShawn Guo [GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr, 2807496d1a13SShawn Guo [GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr, 2808496d1a13SShawn Guo [GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr, 2809496d1a13SShawn Guo [GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr, 2810496d1a13SShawn Guo [GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr, 2811496d1a13SShawn Guo [GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr, 2812496d1a13SShawn Guo [GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr, 2813496d1a13SShawn Guo [GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr, 2814496d1a13SShawn Guo [GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr, 2815496d1a13SShawn Guo [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 2816496d1a13SShawn Guo [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, 2817496d1a13SShawn Guo [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2818496d1a13SShawn Guo [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, 2819496d1a13SShawn Guo [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 2820496d1a13SShawn Guo [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 2821496d1a13SShawn Guo [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 2822496d1a13SShawn Guo [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, 2823496d1a13SShawn Guo [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 2824496d1a13SShawn Guo [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2825496d1a13SShawn Guo [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2826496d1a13SShawn Guo [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2827496d1a13SShawn Guo [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2828496d1a13SShawn Guo [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2829496d1a13SShawn Guo [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2830496d1a13SShawn Guo [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 2831496d1a13SShawn Guo [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 2832496d1a13SShawn Guo [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 2833496d1a13SShawn Guo [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, 2834496d1a13SShawn Guo [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 2835496d1a13SShawn Guo [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 2836496d1a13SShawn Guo [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, 2837496d1a13SShawn Guo [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2838496d1a13SShawn Guo [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 2839496d1a13SShawn Guo [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2840496d1a13SShawn Guo [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2841496d1a13SShawn Guo [GCC_PWM0_XO512_CLK] = &gcc_pwm0_xo512_clk.clkr, 2842496d1a13SShawn Guo [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 2843496d1a13SShawn Guo [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 2844496d1a13SShawn Guo [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 2845496d1a13SShawn Guo [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr, 2846496d1a13SShawn Guo [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 2847496d1a13SShawn Guo [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 2848496d1a13SShawn Guo [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 2849496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 2850496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 2851496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 2852496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 2853496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 2854496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 2855496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 2856496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 2857496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 2858496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 2859496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 2860496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 2861496d1a13SShawn Guo [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 2862496d1a13SShawn Guo [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 2863496d1a13SShawn Guo [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2864496d1a13SShawn Guo [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2865496d1a13SShawn Guo [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 2866496d1a13SShawn Guo [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 2867496d1a13SShawn Guo [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 2868496d1a13SShawn Guo [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2869496d1a13SShawn Guo [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2870496d1a13SShawn Guo [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 2871496d1a13SShawn Guo [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 2872496d1a13SShawn Guo [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, 2873496d1a13SShawn Guo [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 2874496d1a13SShawn Guo [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 2875496d1a13SShawn Guo [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 2876496d1a13SShawn Guo [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 2877496d1a13SShawn Guo &gcc_usb30_prim_mock_utmi_clk_src.clkr, 2878496d1a13SShawn Guo [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV] = 2879496d1a13SShawn Guo &gcc_usb30_prim_mock_utmi_postdiv.clkr, 2880496d1a13SShawn Guo [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 2881496d1a13SShawn Guo [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 2882496d1a13SShawn Guo [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 2883496d1a13SShawn Guo [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 2884496d1a13SShawn Guo [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 2885496d1a13SShawn Guo [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr, 2886496d1a13SShawn Guo [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr, 2887496d1a13SShawn Guo [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr, 2888496d1a13SShawn Guo [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 2889496d1a13SShawn Guo [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 2890496d1a13SShawn Guo [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, 2891496d1a13SShawn Guo [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr, 2892496d1a13SShawn Guo [GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr, 2893496d1a13SShawn Guo [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr, 2894496d1a13SShawn Guo [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 2895496d1a13SShawn Guo [GPLL0] = &gpll0.clkr, 2896496d1a13SShawn Guo [GPLL0_OUT_AUX2] = &gpll0_out_aux2.clkr, 2897496d1a13SShawn Guo [GPLL1] = &gpll1.clkr, 2898496d1a13SShawn Guo [GPLL10] = &gpll10.clkr, 2899496d1a13SShawn Guo [GPLL11] = &gpll11.clkr, 2900496d1a13SShawn Guo [GPLL3] = &gpll3.clkr, 2901496d1a13SShawn Guo [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr, 2902496d1a13SShawn Guo [GPLL4] = &gpll4.clkr, 2903496d1a13SShawn Guo [GPLL5] = &gpll5.clkr, 2904496d1a13SShawn Guo [GPLL6] = &gpll6.clkr, 2905496d1a13SShawn Guo [GPLL6_OUT_MAIN] = &gpll6_out_main.clkr, 2906496d1a13SShawn Guo [GPLL7] = &gpll7.clkr, 2907496d1a13SShawn Guo [GPLL8] = &gpll8.clkr, 2908496d1a13SShawn Guo [GPLL8_OUT_MAIN] = &gpll8_out_main.clkr, 2909496d1a13SShawn Guo [GPLL9] = &gpll9.clkr, 2910496d1a13SShawn Guo [GPLL9_OUT_MAIN] = &gpll9_out_main.clkr, 2911496d1a13SShawn Guo }; 2912496d1a13SShawn Guo 2913496d1a13SShawn Guo static const struct qcom_reset_map gcc_qcm2290_resets[] = { 2914496d1a13SShawn Guo [GCC_CAMSS_OPE_BCR] = { 0x55000 }, 2915496d1a13SShawn Guo [GCC_CAMSS_TFE_BCR] = { 0x52000 }, 2916496d1a13SShawn Guo [GCC_CAMSS_TOP_BCR] = { 0x58000 }, 2917496d1a13SShawn Guo [GCC_GPU_BCR] = { 0x36000 }, 2918496d1a13SShawn Guo [GCC_MMSS_BCR] = { 0x17000 }, 2919496d1a13SShawn Guo [GCC_PDM_BCR] = { 0x20000 }, 2920496d1a13SShawn Guo [GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 }, 2921496d1a13SShawn Guo [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, 2922496d1a13SShawn Guo [GCC_SDCC1_BCR] = { 0x38000 }, 2923496d1a13SShawn Guo [GCC_SDCC2_BCR] = { 0x1e000 }, 2924496d1a13SShawn Guo [GCC_USB30_PRIM_BCR] = { 0x1a000 }, 2925496d1a13SShawn Guo [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, 2926496d1a13SShawn Guo [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, 2927496d1a13SShawn Guo [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, 2928496d1a13SShawn Guo [GCC_VCODEC0_BCR] = { 0x58094 }, 2929496d1a13SShawn Guo [GCC_VENUS_BCR] = { 0x58078 }, 2930496d1a13SShawn Guo [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 }, 2931496d1a13SShawn Guo }; 2932496d1a13SShawn Guo 2933496d1a13SShawn Guo static struct gdsc *gcc_qcm2290_gdscs[] = { 2934496d1a13SShawn Guo [GCC_CAMSS_TOP_GDSC] = &gcc_camss_top_gdsc, 2935496d1a13SShawn Guo [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 2936496d1a13SShawn Guo [GCC_VCODEC0_GDSC] = &gcc_vcodec0_gdsc, 2937496d1a13SShawn Guo [GCC_VENUS_GDSC] = &gcc_venus_gdsc, 2938496d1a13SShawn Guo [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, 2939496d1a13SShawn Guo [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc, 2940496d1a13SShawn Guo [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc, 2941496d1a13SShawn Guo [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc, 2942496d1a13SShawn Guo }; 2943496d1a13SShawn Guo 2944496d1a13SShawn Guo static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 2945496d1a13SShawn Guo DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 2946496d1a13SShawn Guo DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 2947496d1a13SShawn Guo DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 2948496d1a13SShawn Guo DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 2949496d1a13SShawn Guo DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 2950496d1a13SShawn Guo DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 2951496d1a13SShawn Guo }; 2952496d1a13SShawn Guo 2953496d1a13SShawn Guo static const struct regmap_config gcc_qcm2290_regmap_config = { 2954496d1a13SShawn Guo .reg_bits = 32, 2955496d1a13SShawn Guo .reg_stride = 4, 2956496d1a13SShawn Guo .val_bits = 32, 2957496d1a13SShawn Guo .max_register = 0xc7000, 2958496d1a13SShawn Guo .fast_io = true, 2959496d1a13SShawn Guo }; 2960496d1a13SShawn Guo 2961496d1a13SShawn Guo static const struct qcom_cc_desc gcc_qcm2290_desc = { 2962496d1a13SShawn Guo .config = &gcc_qcm2290_regmap_config, 2963496d1a13SShawn Guo .clks = gcc_qcm2290_clocks, 2964496d1a13SShawn Guo .num_clks = ARRAY_SIZE(gcc_qcm2290_clocks), 2965496d1a13SShawn Guo .resets = gcc_qcm2290_resets, 2966496d1a13SShawn Guo .num_resets = ARRAY_SIZE(gcc_qcm2290_resets), 2967496d1a13SShawn Guo .gdscs = gcc_qcm2290_gdscs, 2968496d1a13SShawn Guo .num_gdscs = ARRAY_SIZE(gcc_qcm2290_gdscs), 2969496d1a13SShawn Guo }; 2970496d1a13SShawn Guo 2971496d1a13SShawn Guo static const struct of_device_id gcc_qcm2290_match_table[] = { 2972496d1a13SShawn Guo { .compatible = "qcom,gcc-qcm2290" }, 2973496d1a13SShawn Guo { } 2974496d1a13SShawn Guo }; 2975496d1a13SShawn Guo MODULE_DEVICE_TABLE(of, gcc_qcm2290_match_table); 2976496d1a13SShawn Guo 2977496d1a13SShawn Guo static int gcc_qcm2290_probe(struct platform_device *pdev) 2978496d1a13SShawn Guo { 2979496d1a13SShawn Guo struct regmap *regmap; 2980496d1a13SShawn Guo int ret; 2981496d1a13SShawn Guo 2982496d1a13SShawn Guo regmap = qcom_cc_map(pdev, &gcc_qcm2290_desc); 2983496d1a13SShawn Guo if (IS_ERR(regmap)) 2984496d1a13SShawn Guo return PTR_ERR(regmap); 2985496d1a13SShawn Guo 2986496d1a13SShawn Guo ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 2987496d1a13SShawn Guo ARRAY_SIZE(gcc_dfs_clocks)); 2988496d1a13SShawn Guo if (ret) 2989496d1a13SShawn Guo return ret; 2990496d1a13SShawn Guo 2991496d1a13SShawn Guo clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config); 2992496d1a13SShawn Guo clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config); 2993496d1a13SShawn Guo clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config); 2994496d1a13SShawn Guo clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config); 2995496d1a13SShawn Guo 2996496d1a13SShawn Guo return qcom_cc_really_probe(pdev, &gcc_qcm2290_desc, regmap); 2997496d1a13SShawn Guo } 2998496d1a13SShawn Guo 2999496d1a13SShawn Guo static struct platform_driver gcc_qcm2290_driver = { 3000496d1a13SShawn Guo .probe = gcc_qcm2290_probe, 3001496d1a13SShawn Guo .driver = { 3002496d1a13SShawn Guo .name = "gcc-qcm2290", 3003496d1a13SShawn Guo .of_match_table = gcc_qcm2290_match_table, 3004496d1a13SShawn Guo }, 3005496d1a13SShawn Guo }; 3006496d1a13SShawn Guo 3007496d1a13SShawn Guo static int __init gcc_qcm2290_init(void) 3008496d1a13SShawn Guo { 3009496d1a13SShawn Guo return platform_driver_register(&gcc_qcm2290_driver); 3010496d1a13SShawn Guo } 3011496d1a13SShawn Guo subsys_initcall(gcc_qcm2290_init); 3012496d1a13SShawn Guo 3013496d1a13SShawn Guo static void __exit gcc_qcm2290_exit(void) 3014496d1a13SShawn Guo { 3015496d1a13SShawn Guo platform_driver_unregister(&gcc_qcm2290_driver); 3016496d1a13SShawn Guo } 3017496d1a13SShawn Guo module_exit(gcc_qcm2290_exit); 3018496d1a13SShawn Guo 3019496d1a13SShawn Guo MODULE_DESCRIPTION("QTI GCC QCM2290 Driver"); 3020496d1a13SShawn Guo MODULE_LICENSE("GPL v2"); 3021