1*496d1a13SShawn Guo // SPDX-License-Identifier: GPL-2.0-only 2*496d1a13SShawn Guo /* 3*496d1a13SShawn Guo * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4*496d1a13SShawn Guo */ 5*496d1a13SShawn Guo 6*496d1a13SShawn Guo #include <linux/clk-provider.h> 7*496d1a13SShawn Guo #include <linux/err.h> 8*496d1a13SShawn Guo #include <linux/kernel.h> 9*496d1a13SShawn Guo #include <linux/module.h> 10*496d1a13SShawn Guo #include <linux/platform_device.h> 11*496d1a13SShawn Guo #include <linux/regmap.h> 12*496d1a13SShawn Guo 13*496d1a13SShawn Guo #include <dt-bindings/clock/qcom,gcc-qcm2290.h> 14*496d1a13SShawn Guo 15*496d1a13SShawn Guo #include "clk-alpha-pll.h" 16*496d1a13SShawn Guo #include "clk-branch.h" 17*496d1a13SShawn Guo #include "clk-rcg.h" 18*496d1a13SShawn Guo #include "clk-regmap-divider.h" 19*496d1a13SShawn Guo #include "common.h" 20*496d1a13SShawn Guo #include "gdsc.h" 21*496d1a13SShawn Guo #include "reset.h" 22*496d1a13SShawn Guo 23*496d1a13SShawn Guo enum { 24*496d1a13SShawn Guo P_BI_TCXO, 25*496d1a13SShawn Guo P_GPLL0_OUT_AUX2, 26*496d1a13SShawn Guo P_GPLL0_OUT_EARLY, 27*496d1a13SShawn Guo P_GPLL10_OUT_MAIN, 28*496d1a13SShawn Guo P_GPLL11_OUT_AUX, 29*496d1a13SShawn Guo P_GPLL11_OUT_AUX2, 30*496d1a13SShawn Guo P_GPLL11_OUT_MAIN, 31*496d1a13SShawn Guo P_GPLL3_OUT_EARLY, 32*496d1a13SShawn Guo P_GPLL3_OUT_MAIN, 33*496d1a13SShawn Guo P_GPLL4_OUT_MAIN, 34*496d1a13SShawn Guo P_GPLL5_OUT_MAIN, 35*496d1a13SShawn Guo P_GPLL6_OUT_EARLY, 36*496d1a13SShawn Guo P_GPLL6_OUT_MAIN, 37*496d1a13SShawn Guo P_GPLL7_OUT_MAIN, 38*496d1a13SShawn Guo P_GPLL8_OUT_EARLY, 39*496d1a13SShawn Guo P_GPLL8_OUT_MAIN, 40*496d1a13SShawn Guo P_GPLL9_OUT_EARLY, 41*496d1a13SShawn Guo P_GPLL9_OUT_MAIN, 42*496d1a13SShawn Guo P_SLEEP_CLK, 43*496d1a13SShawn Guo }; 44*496d1a13SShawn Guo 45*496d1a13SShawn Guo static const struct pll_vco brammo_vco[] = { 46*496d1a13SShawn Guo { 500000000, 1250000000, 0 }, 47*496d1a13SShawn Guo }; 48*496d1a13SShawn Guo 49*496d1a13SShawn Guo static const struct pll_vco default_vco[] = { 50*496d1a13SShawn Guo { 500000000, 1000000000, 2 }, 51*496d1a13SShawn Guo }; 52*496d1a13SShawn Guo 53*496d1a13SShawn Guo static const struct pll_vco spark_vco[] = { 54*496d1a13SShawn Guo { 750000000, 1500000000, 1 }, 55*496d1a13SShawn Guo }; 56*496d1a13SShawn Guo 57*496d1a13SShawn Guo static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = { 58*496d1a13SShawn Guo [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 59*496d1a13SShawn Guo [PLL_OFF_L_VAL] = 0x04, 60*496d1a13SShawn Guo [PLL_OFF_ALPHA_VAL] = 0x08, 61*496d1a13SShawn Guo [PLL_OFF_ALPHA_VAL_U] = 0x0c, 62*496d1a13SShawn Guo [PLL_OFF_TEST_CTL] = 0x10, 63*496d1a13SShawn Guo [PLL_OFF_TEST_CTL_U] = 0x14, 64*496d1a13SShawn Guo [PLL_OFF_USER_CTL] = 0x18, 65*496d1a13SShawn Guo [PLL_OFF_USER_CTL_U] = 0x1C, 66*496d1a13SShawn Guo [PLL_OFF_CONFIG_CTL] = 0x20, 67*496d1a13SShawn Guo [PLL_OFF_STATUS] = 0x24, 68*496d1a13SShawn Guo }, 69*496d1a13SShawn Guo [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 70*496d1a13SShawn Guo [PLL_OFF_L_VAL] = 0x04, 71*496d1a13SShawn Guo [PLL_OFF_ALPHA_VAL] = 0x08, 72*496d1a13SShawn Guo [PLL_OFF_ALPHA_VAL_U] = 0x0c, 73*496d1a13SShawn Guo [PLL_OFF_TEST_CTL] = 0x10, 74*496d1a13SShawn Guo [PLL_OFF_TEST_CTL_U] = 0x14, 75*496d1a13SShawn Guo [PLL_OFF_USER_CTL] = 0x18, 76*496d1a13SShawn Guo [PLL_OFF_CONFIG_CTL] = 0x1C, 77*496d1a13SShawn Guo [PLL_OFF_STATUS] = 0x20, 78*496d1a13SShawn Guo }, 79*496d1a13SShawn Guo }; 80*496d1a13SShawn Guo 81*496d1a13SShawn Guo static struct clk_alpha_pll gpll0 = { 82*496d1a13SShawn Guo .offset = 0x0, 83*496d1a13SShawn Guo .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 84*496d1a13SShawn Guo .clkr = { 85*496d1a13SShawn Guo .enable_reg = 0x79000, 86*496d1a13SShawn Guo .enable_mask = BIT(0), 87*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 88*496d1a13SShawn Guo .name = "gpll0", 89*496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 90*496d1a13SShawn Guo .fw_name = "bi_tcxo", 91*496d1a13SShawn Guo }, 92*496d1a13SShawn Guo .num_parents = 1, 93*496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 94*496d1a13SShawn Guo }, 95*496d1a13SShawn Guo }, 96*496d1a13SShawn Guo }; 97*496d1a13SShawn Guo 98*496d1a13SShawn Guo static const struct clk_div_table post_div_table_gpll0_out_aux2[] = { 99*496d1a13SShawn Guo { 0x1, 2 }, 100*496d1a13SShawn Guo { } 101*496d1a13SShawn Guo }; 102*496d1a13SShawn Guo 103*496d1a13SShawn Guo static struct clk_alpha_pll_postdiv gpll0_out_aux2 = { 104*496d1a13SShawn Guo .offset = 0x0, 105*496d1a13SShawn Guo .post_div_shift = 8, 106*496d1a13SShawn Guo .post_div_table = post_div_table_gpll0_out_aux2, 107*496d1a13SShawn Guo .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2), 108*496d1a13SShawn Guo .width = 4, 109*496d1a13SShawn Guo .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 110*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 111*496d1a13SShawn Guo .name = "gpll0_out_aux2", 112*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 113*496d1a13SShawn Guo .num_parents = 1, 114*496d1a13SShawn Guo .ops = &clk_alpha_pll_postdiv_ro_ops, 115*496d1a13SShawn Guo }, 116*496d1a13SShawn Guo }; 117*496d1a13SShawn Guo 118*496d1a13SShawn Guo static struct clk_alpha_pll gpll1 = { 119*496d1a13SShawn Guo .offset = 0x1000, 120*496d1a13SShawn Guo .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 121*496d1a13SShawn Guo .clkr = { 122*496d1a13SShawn Guo .enable_reg = 0x79000, 123*496d1a13SShawn Guo .enable_mask = BIT(1), 124*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 125*496d1a13SShawn Guo .name = "gpll1", 126*496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 127*496d1a13SShawn Guo .fw_name = "bi_tcxo", 128*496d1a13SShawn Guo }, 129*496d1a13SShawn Guo .num_parents = 1, 130*496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 131*496d1a13SShawn Guo }, 132*496d1a13SShawn Guo }, 133*496d1a13SShawn Guo }; 134*496d1a13SShawn Guo 135*496d1a13SShawn Guo /* 1152MHz configuration */ 136*496d1a13SShawn Guo static const struct alpha_pll_config gpll10_config = { 137*496d1a13SShawn Guo .l = 0x3c, 138*496d1a13SShawn Guo .alpha = 0x0, 139*496d1a13SShawn Guo .vco_val = 0x1 << 20, 140*496d1a13SShawn Guo .vco_mask = GENMASK(21, 20), 141*496d1a13SShawn Guo .main_output_mask = BIT(0), 142*496d1a13SShawn Guo .config_ctl_val = 0x4001055B, 143*496d1a13SShawn Guo .test_ctl_hi1_val = 0x1, 144*496d1a13SShawn Guo }; 145*496d1a13SShawn Guo 146*496d1a13SShawn Guo static struct clk_alpha_pll gpll10 = { 147*496d1a13SShawn Guo .offset = 0xa000, 148*496d1a13SShawn Guo .vco_table = spark_vco, 149*496d1a13SShawn Guo .num_vco = ARRAY_SIZE(spark_vco), 150*496d1a13SShawn Guo .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 151*496d1a13SShawn Guo .clkr = { 152*496d1a13SShawn Guo .enable_reg = 0x79000, 153*496d1a13SShawn Guo .enable_mask = BIT(10), 154*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 155*496d1a13SShawn Guo .name = "gpll10", 156*496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 157*496d1a13SShawn Guo .fw_name = "bi_tcxo", 158*496d1a13SShawn Guo }, 159*496d1a13SShawn Guo .num_parents = 1, 160*496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 161*496d1a13SShawn Guo }, 162*496d1a13SShawn Guo }, 163*496d1a13SShawn Guo }; 164*496d1a13SShawn Guo 165*496d1a13SShawn Guo /* 532MHz configuration */ 166*496d1a13SShawn Guo static const struct alpha_pll_config gpll11_config = { 167*496d1a13SShawn Guo .l = 0x1B, 168*496d1a13SShawn Guo .alpha = 0x55555555, 169*496d1a13SShawn Guo .alpha_hi = 0xB5, 170*496d1a13SShawn Guo .alpha_en_mask = BIT(24), 171*496d1a13SShawn Guo .vco_val = 0x2 << 20, 172*496d1a13SShawn Guo .vco_mask = GENMASK(21, 20), 173*496d1a13SShawn Guo .main_output_mask = BIT(0), 174*496d1a13SShawn Guo .config_ctl_val = 0x4001055B, 175*496d1a13SShawn Guo .test_ctl_hi1_val = 0x1, 176*496d1a13SShawn Guo }; 177*496d1a13SShawn Guo 178*496d1a13SShawn Guo static struct clk_alpha_pll gpll11 = { 179*496d1a13SShawn Guo .offset = 0xb000, 180*496d1a13SShawn Guo .vco_table = default_vco, 181*496d1a13SShawn Guo .num_vco = ARRAY_SIZE(default_vco), 182*496d1a13SShawn Guo .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 183*496d1a13SShawn Guo .flags = SUPPORTS_DYNAMIC_UPDATE, 184*496d1a13SShawn Guo .clkr = { 185*496d1a13SShawn Guo .enable_reg = 0x79000, 186*496d1a13SShawn Guo .enable_mask = BIT(11), 187*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 188*496d1a13SShawn Guo .name = "gpll11", 189*496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 190*496d1a13SShawn Guo .fw_name = "bi_tcxo", 191*496d1a13SShawn Guo }, 192*496d1a13SShawn Guo .num_parents = 1, 193*496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 194*496d1a13SShawn Guo }, 195*496d1a13SShawn Guo }, 196*496d1a13SShawn Guo }; 197*496d1a13SShawn Guo 198*496d1a13SShawn Guo static struct clk_alpha_pll gpll3 = { 199*496d1a13SShawn Guo .offset = 0x3000, 200*496d1a13SShawn Guo .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 201*496d1a13SShawn Guo .clkr = { 202*496d1a13SShawn Guo .enable_reg = 0x79000, 203*496d1a13SShawn Guo .enable_mask = BIT(3), 204*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 205*496d1a13SShawn Guo .name = "gpll3", 206*496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 207*496d1a13SShawn Guo .fw_name = "bi_tcxo", 208*496d1a13SShawn Guo }, 209*496d1a13SShawn Guo .num_parents = 1, 210*496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 211*496d1a13SShawn Guo }, 212*496d1a13SShawn Guo }, 213*496d1a13SShawn Guo }; 214*496d1a13SShawn Guo 215*496d1a13SShawn Guo static const struct clk_div_table post_div_table_gpll3_out_main[] = { 216*496d1a13SShawn Guo { 0x1, 2 }, 217*496d1a13SShawn Guo { } 218*496d1a13SShawn Guo }; 219*496d1a13SShawn Guo 220*496d1a13SShawn Guo static struct clk_alpha_pll_postdiv gpll3_out_main = { 221*496d1a13SShawn Guo .offset = 0x3000, 222*496d1a13SShawn Guo .post_div_shift = 8, 223*496d1a13SShawn Guo .post_div_table = post_div_table_gpll3_out_main, 224*496d1a13SShawn Guo .num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_main), 225*496d1a13SShawn Guo .width = 4, 226*496d1a13SShawn Guo .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 227*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 228*496d1a13SShawn Guo .name = "gpll3_out_main", 229*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]){ &gpll3.clkr.hw }, 230*496d1a13SShawn Guo .num_parents = 1, 231*496d1a13SShawn Guo .ops = &clk_alpha_pll_postdiv_ro_ops, 232*496d1a13SShawn Guo }, 233*496d1a13SShawn Guo }; 234*496d1a13SShawn Guo 235*496d1a13SShawn Guo static struct clk_alpha_pll gpll4 = { 236*496d1a13SShawn Guo .offset = 0x4000, 237*496d1a13SShawn Guo .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 238*496d1a13SShawn Guo .clkr = { 239*496d1a13SShawn Guo .enable_reg = 0x79000, 240*496d1a13SShawn Guo .enable_mask = BIT(4), 241*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 242*496d1a13SShawn Guo .name = "gpll4", 243*496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 244*496d1a13SShawn Guo .fw_name = "bi_tcxo", 245*496d1a13SShawn Guo }, 246*496d1a13SShawn Guo .num_parents = 1, 247*496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 248*496d1a13SShawn Guo }, 249*496d1a13SShawn Guo }, 250*496d1a13SShawn Guo }; 251*496d1a13SShawn Guo 252*496d1a13SShawn Guo static struct clk_alpha_pll gpll5 = { 253*496d1a13SShawn Guo .offset = 0x5000, 254*496d1a13SShawn Guo .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 255*496d1a13SShawn Guo .clkr = { 256*496d1a13SShawn Guo .enable_reg = 0x79000, 257*496d1a13SShawn Guo .enable_mask = BIT(5), 258*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 259*496d1a13SShawn Guo .name = "gpll5", 260*496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 261*496d1a13SShawn Guo .fw_name = "bi_tcxo", 262*496d1a13SShawn Guo }, 263*496d1a13SShawn Guo .num_parents = 1, 264*496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 265*496d1a13SShawn Guo }, 266*496d1a13SShawn Guo }, 267*496d1a13SShawn Guo }; 268*496d1a13SShawn Guo 269*496d1a13SShawn Guo static struct clk_alpha_pll gpll6 = { 270*496d1a13SShawn Guo .offset = 0x6000, 271*496d1a13SShawn Guo .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 272*496d1a13SShawn Guo .clkr = { 273*496d1a13SShawn Guo .enable_reg = 0x79000, 274*496d1a13SShawn Guo .enable_mask = BIT(6), 275*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 276*496d1a13SShawn Guo .name = "gpll6", 277*496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 278*496d1a13SShawn Guo .fw_name = "bi_tcxo", 279*496d1a13SShawn Guo }, 280*496d1a13SShawn Guo .num_parents = 1, 281*496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 282*496d1a13SShawn Guo }, 283*496d1a13SShawn Guo }, 284*496d1a13SShawn Guo }; 285*496d1a13SShawn Guo 286*496d1a13SShawn Guo static const struct clk_div_table post_div_table_gpll6_out_main[] = { 287*496d1a13SShawn Guo { 0x1, 2 }, 288*496d1a13SShawn Guo { } 289*496d1a13SShawn Guo }; 290*496d1a13SShawn Guo 291*496d1a13SShawn Guo static struct clk_alpha_pll_postdiv gpll6_out_main = { 292*496d1a13SShawn Guo .offset = 0x6000, 293*496d1a13SShawn Guo .post_div_shift = 8, 294*496d1a13SShawn Guo .post_div_table = post_div_table_gpll6_out_main, 295*496d1a13SShawn Guo .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main), 296*496d1a13SShawn Guo .width = 4, 297*496d1a13SShawn Guo .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 298*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 299*496d1a13SShawn Guo .name = "gpll6_out_main", 300*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw }, 301*496d1a13SShawn Guo .num_parents = 1, 302*496d1a13SShawn Guo .ops = &clk_alpha_pll_postdiv_ro_ops, 303*496d1a13SShawn Guo }, 304*496d1a13SShawn Guo }; 305*496d1a13SShawn Guo 306*496d1a13SShawn Guo static struct clk_alpha_pll gpll7 = { 307*496d1a13SShawn Guo .offset = 0x7000, 308*496d1a13SShawn Guo .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 309*496d1a13SShawn Guo .clkr = { 310*496d1a13SShawn Guo .enable_reg = 0x79000, 311*496d1a13SShawn Guo .enable_mask = BIT(7), 312*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 313*496d1a13SShawn Guo .name = "gpll7", 314*496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 315*496d1a13SShawn Guo .fw_name = "bi_tcxo", 316*496d1a13SShawn Guo }, 317*496d1a13SShawn Guo .num_parents = 1, 318*496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 319*496d1a13SShawn Guo }, 320*496d1a13SShawn Guo }, 321*496d1a13SShawn Guo }; 322*496d1a13SShawn Guo 323*496d1a13SShawn Guo /* 533.2MHz configuration */ 324*496d1a13SShawn Guo static const struct alpha_pll_config gpll8_config = { 325*496d1a13SShawn Guo .l = 0x1B, 326*496d1a13SShawn Guo .alpha = 0x55555555, 327*496d1a13SShawn Guo .alpha_hi = 0xC5, 328*496d1a13SShawn Guo .alpha_en_mask = BIT(24), 329*496d1a13SShawn Guo .vco_val = 0x2 << 20, 330*496d1a13SShawn Guo .vco_mask = GENMASK(21, 20), 331*496d1a13SShawn Guo .main_output_mask = BIT(0), 332*496d1a13SShawn Guo .early_output_mask = BIT(3), 333*496d1a13SShawn Guo .post_div_val = 0x1 << 8, 334*496d1a13SShawn Guo .post_div_mask = GENMASK(11, 8), 335*496d1a13SShawn Guo .config_ctl_val = 0x4001055B, 336*496d1a13SShawn Guo .test_ctl_hi1_val = 0x1, 337*496d1a13SShawn Guo }; 338*496d1a13SShawn Guo 339*496d1a13SShawn Guo static struct clk_alpha_pll gpll8 = { 340*496d1a13SShawn Guo .offset = 0x8000, 341*496d1a13SShawn Guo .vco_table = default_vco, 342*496d1a13SShawn Guo .num_vco = ARRAY_SIZE(default_vco), 343*496d1a13SShawn Guo .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 344*496d1a13SShawn Guo .flags = SUPPORTS_DYNAMIC_UPDATE, 345*496d1a13SShawn Guo .clkr = { 346*496d1a13SShawn Guo .enable_reg = 0x79000, 347*496d1a13SShawn Guo .enable_mask = BIT(8), 348*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 349*496d1a13SShawn Guo .name = "gpll8", 350*496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 351*496d1a13SShawn Guo .fw_name = "bi_tcxo", 352*496d1a13SShawn Guo }, 353*496d1a13SShawn Guo .num_parents = 1, 354*496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 355*496d1a13SShawn Guo }, 356*496d1a13SShawn Guo }, 357*496d1a13SShawn Guo }; 358*496d1a13SShawn Guo 359*496d1a13SShawn Guo static const struct clk_div_table post_div_table_gpll8_out_main[] = { 360*496d1a13SShawn Guo { 0x1, 2 }, 361*496d1a13SShawn Guo { } 362*496d1a13SShawn Guo }; 363*496d1a13SShawn Guo 364*496d1a13SShawn Guo static struct clk_alpha_pll_postdiv gpll8_out_main = { 365*496d1a13SShawn Guo .offset = 0x8000, 366*496d1a13SShawn Guo .post_div_shift = 8, 367*496d1a13SShawn Guo .post_div_table = post_div_table_gpll8_out_main, 368*496d1a13SShawn Guo .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main), 369*496d1a13SShawn Guo .width = 4, 370*496d1a13SShawn Guo .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 371*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 372*496d1a13SShawn Guo .name = "gpll8_out_main", 373*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw }, 374*496d1a13SShawn Guo .num_parents = 1, 375*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 376*496d1a13SShawn Guo .ops = &clk_alpha_pll_postdiv_ro_ops, 377*496d1a13SShawn Guo }, 378*496d1a13SShawn Guo }; 379*496d1a13SShawn Guo 380*496d1a13SShawn Guo /* 1152MHz configuration */ 381*496d1a13SShawn Guo static const struct alpha_pll_config gpll9_config = { 382*496d1a13SShawn Guo .l = 0x3C, 383*496d1a13SShawn Guo .alpha = 0x0, 384*496d1a13SShawn Guo .post_div_val = 0x1 << 8, 385*496d1a13SShawn Guo .post_div_mask = GENMASK(9, 8), 386*496d1a13SShawn Guo .main_output_mask = BIT(0), 387*496d1a13SShawn Guo .early_output_mask = BIT(3), 388*496d1a13SShawn Guo .config_ctl_val = 0x00004289, 389*496d1a13SShawn Guo .test_ctl_val = 0x08000000, 390*496d1a13SShawn Guo }; 391*496d1a13SShawn Guo 392*496d1a13SShawn Guo static struct clk_alpha_pll gpll9 = { 393*496d1a13SShawn Guo .offset = 0x9000, 394*496d1a13SShawn Guo .vco_table = brammo_vco, 395*496d1a13SShawn Guo .num_vco = ARRAY_SIZE(brammo_vco), 396*496d1a13SShawn Guo .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO], 397*496d1a13SShawn Guo .clkr = { 398*496d1a13SShawn Guo .enable_reg = 0x79000, 399*496d1a13SShawn Guo .enable_mask = BIT(9), 400*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 401*496d1a13SShawn Guo .name = "gpll9", 402*496d1a13SShawn Guo .parent_data = &(const struct clk_parent_data){ 403*496d1a13SShawn Guo .fw_name = "bi_tcxo", 404*496d1a13SShawn Guo }, 405*496d1a13SShawn Guo .num_parents = 1, 406*496d1a13SShawn Guo .ops = &clk_alpha_pll_ops, 407*496d1a13SShawn Guo }, 408*496d1a13SShawn Guo }, 409*496d1a13SShawn Guo }; 410*496d1a13SShawn Guo 411*496d1a13SShawn Guo static const struct clk_div_table post_div_table_gpll9_out_main[] = { 412*496d1a13SShawn Guo { 0x1, 2 }, 413*496d1a13SShawn Guo { } 414*496d1a13SShawn Guo }; 415*496d1a13SShawn Guo 416*496d1a13SShawn Guo static struct clk_alpha_pll_postdiv gpll9_out_main = { 417*496d1a13SShawn Guo .offset = 0x9000, 418*496d1a13SShawn Guo .post_div_shift = 8, 419*496d1a13SShawn Guo .post_div_table = post_div_table_gpll9_out_main, 420*496d1a13SShawn Guo .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main), 421*496d1a13SShawn Guo .width = 2, 422*496d1a13SShawn Guo .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO], 423*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 424*496d1a13SShawn Guo .name = "gpll9_out_main", 425*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw }, 426*496d1a13SShawn Guo .num_parents = 1, 427*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 428*496d1a13SShawn Guo .ops = &clk_alpha_pll_postdiv_ro_ops, 429*496d1a13SShawn Guo }, 430*496d1a13SShawn Guo }; 431*496d1a13SShawn Guo 432*496d1a13SShawn Guo static const struct parent_map gcc_parent_map_0[] = { 433*496d1a13SShawn Guo { P_BI_TCXO, 0 }, 434*496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 435*496d1a13SShawn Guo { P_GPLL0_OUT_AUX2, 2 }, 436*496d1a13SShawn Guo }; 437*496d1a13SShawn Guo 438*496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_0[] = { 439*496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 440*496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 441*496d1a13SShawn Guo { .hw = &gpll0_out_aux2.clkr.hw }, 442*496d1a13SShawn Guo }; 443*496d1a13SShawn Guo 444*496d1a13SShawn Guo static const struct parent_map gcc_parent_map_1[] = { 445*496d1a13SShawn Guo { P_BI_TCXO, 0 }, 446*496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 447*496d1a13SShawn Guo { P_GPLL0_OUT_AUX2, 2 }, 448*496d1a13SShawn Guo { P_GPLL6_OUT_MAIN, 4 }, 449*496d1a13SShawn Guo }; 450*496d1a13SShawn Guo 451*496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_1[] = { 452*496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 453*496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 454*496d1a13SShawn Guo { .hw = &gpll0_out_aux2.clkr.hw }, 455*496d1a13SShawn Guo { .hw = &gpll6_out_main.clkr.hw }, 456*496d1a13SShawn Guo }; 457*496d1a13SShawn Guo 458*496d1a13SShawn Guo static const struct parent_map gcc_parent_map_2[] = { 459*496d1a13SShawn Guo { P_BI_TCXO, 0 }, 460*496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 461*496d1a13SShawn Guo { P_GPLL0_OUT_AUX2, 2 }, 462*496d1a13SShawn Guo { P_SLEEP_CLK, 5 }, 463*496d1a13SShawn Guo }; 464*496d1a13SShawn Guo 465*496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_2[] = { 466*496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 467*496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 468*496d1a13SShawn Guo { .hw = &gpll0_out_aux2.clkr.hw }, 469*496d1a13SShawn Guo { .fw_name = "sleep_clk" }, 470*496d1a13SShawn Guo }; 471*496d1a13SShawn Guo 472*496d1a13SShawn Guo static const struct parent_map gcc_parent_map_3[] = { 473*496d1a13SShawn Guo { P_BI_TCXO, 0 }, 474*496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 475*496d1a13SShawn Guo { P_GPLL9_OUT_EARLY, 2 }, 476*496d1a13SShawn Guo { P_GPLL10_OUT_MAIN, 3 }, 477*496d1a13SShawn Guo { P_GPLL9_OUT_MAIN, 5 }, 478*496d1a13SShawn Guo { P_GPLL3_OUT_MAIN, 6 }, 479*496d1a13SShawn Guo }; 480*496d1a13SShawn Guo 481*496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_3[] = { 482*496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 483*496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 484*496d1a13SShawn Guo { .hw = &gpll9.clkr.hw }, 485*496d1a13SShawn Guo { .hw = &gpll10.clkr.hw }, 486*496d1a13SShawn Guo { .hw = &gpll9_out_main.clkr.hw }, 487*496d1a13SShawn Guo { .hw = &gpll3_out_main.clkr.hw }, 488*496d1a13SShawn Guo }; 489*496d1a13SShawn Guo 490*496d1a13SShawn Guo static const struct parent_map gcc_parent_map_4[] = { 491*496d1a13SShawn Guo { P_BI_TCXO, 0 }, 492*496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 493*496d1a13SShawn Guo { P_GPLL0_OUT_AUX2, 2 }, 494*496d1a13SShawn Guo { P_GPLL10_OUT_MAIN, 3 }, 495*496d1a13SShawn Guo { P_GPLL4_OUT_MAIN, 5 }, 496*496d1a13SShawn Guo { P_GPLL3_OUT_EARLY, 6 }, 497*496d1a13SShawn Guo }; 498*496d1a13SShawn Guo 499*496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_4[] = { 500*496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 501*496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 502*496d1a13SShawn Guo { .hw = &gpll0_out_aux2.clkr.hw }, 503*496d1a13SShawn Guo { .hw = &gpll10.clkr.hw }, 504*496d1a13SShawn Guo { .hw = &gpll4.clkr.hw }, 505*496d1a13SShawn Guo { .hw = &gpll3.clkr.hw }, 506*496d1a13SShawn Guo }; 507*496d1a13SShawn Guo 508*496d1a13SShawn Guo static const struct parent_map gcc_parent_map_5[] = { 509*496d1a13SShawn Guo { P_BI_TCXO, 0 }, 510*496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 511*496d1a13SShawn Guo { P_GPLL0_OUT_AUX2, 2 }, 512*496d1a13SShawn Guo { P_GPLL4_OUT_MAIN, 5 }, 513*496d1a13SShawn Guo { P_GPLL3_OUT_MAIN, 6 }, 514*496d1a13SShawn Guo }; 515*496d1a13SShawn Guo 516*496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_5[] = { 517*496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 518*496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 519*496d1a13SShawn Guo { .hw = &gpll0_out_aux2.clkr.hw }, 520*496d1a13SShawn Guo { .hw = &gpll4.clkr.hw }, 521*496d1a13SShawn Guo { .hw = &gpll3_out_main.clkr.hw }, 522*496d1a13SShawn Guo }; 523*496d1a13SShawn Guo 524*496d1a13SShawn Guo static const struct parent_map gcc_parent_map_6[] = { 525*496d1a13SShawn Guo { P_BI_TCXO, 0 }, 526*496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 527*496d1a13SShawn Guo { P_GPLL8_OUT_EARLY, 2 }, 528*496d1a13SShawn Guo { P_GPLL10_OUT_MAIN, 3 }, 529*496d1a13SShawn Guo { P_GPLL8_OUT_MAIN, 4 }, 530*496d1a13SShawn Guo { P_GPLL9_OUT_MAIN, 5 }, 531*496d1a13SShawn Guo { P_GPLL3_OUT_EARLY, 6 }, 532*496d1a13SShawn Guo }; 533*496d1a13SShawn Guo 534*496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_6[] = { 535*496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 536*496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 537*496d1a13SShawn Guo { .hw = &gpll8.clkr.hw }, 538*496d1a13SShawn Guo { .hw = &gpll10.clkr.hw }, 539*496d1a13SShawn Guo { .hw = &gpll8_out_main.clkr.hw }, 540*496d1a13SShawn Guo { .hw = &gpll9_out_main.clkr.hw }, 541*496d1a13SShawn Guo { .hw = &gpll3.clkr.hw }, 542*496d1a13SShawn Guo }; 543*496d1a13SShawn Guo 544*496d1a13SShawn Guo static const struct parent_map gcc_parent_map_7[] = { 545*496d1a13SShawn Guo { P_BI_TCXO, 0 }, 546*496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 547*496d1a13SShawn Guo { P_GPLL8_OUT_EARLY, 2 }, 548*496d1a13SShawn Guo { P_GPLL10_OUT_MAIN, 3 }, 549*496d1a13SShawn Guo { P_GPLL8_OUT_MAIN, 4 }, 550*496d1a13SShawn Guo { P_GPLL9_OUT_MAIN, 5 }, 551*496d1a13SShawn Guo { P_GPLL3_OUT_MAIN, 6 }, 552*496d1a13SShawn Guo }; 553*496d1a13SShawn Guo 554*496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_7[] = { 555*496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 556*496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 557*496d1a13SShawn Guo { .hw = &gpll8.clkr.hw }, 558*496d1a13SShawn Guo { .hw = &gpll10.clkr.hw }, 559*496d1a13SShawn Guo { .hw = &gpll8_out_main.clkr.hw }, 560*496d1a13SShawn Guo { .hw = &gpll9_out_main.clkr.hw }, 561*496d1a13SShawn Guo { .hw = &gpll3_out_main.clkr.hw }, 562*496d1a13SShawn Guo }; 563*496d1a13SShawn Guo 564*496d1a13SShawn Guo static const struct parent_map gcc_parent_map_8[] = { 565*496d1a13SShawn Guo { P_BI_TCXO, 0 }, 566*496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 567*496d1a13SShawn Guo { P_GPLL8_OUT_EARLY, 2 }, 568*496d1a13SShawn Guo { P_GPLL10_OUT_MAIN, 3 }, 569*496d1a13SShawn Guo { P_GPLL6_OUT_MAIN, 4 }, 570*496d1a13SShawn Guo { P_GPLL9_OUT_MAIN, 5 }, 571*496d1a13SShawn Guo { P_GPLL3_OUT_EARLY, 6 }, 572*496d1a13SShawn Guo }; 573*496d1a13SShawn Guo 574*496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_8[] = { 575*496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 576*496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 577*496d1a13SShawn Guo { .hw = &gpll8.clkr.hw }, 578*496d1a13SShawn Guo { .hw = &gpll10.clkr.hw }, 579*496d1a13SShawn Guo { .hw = &gpll6_out_main.clkr.hw }, 580*496d1a13SShawn Guo { .hw = &gpll9_out_main.clkr.hw }, 581*496d1a13SShawn Guo { .hw = &gpll3.clkr.hw }, 582*496d1a13SShawn Guo }; 583*496d1a13SShawn Guo 584*496d1a13SShawn Guo static const struct parent_map gcc_parent_map_9[] = { 585*496d1a13SShawn Guo { P_BI_TCXO, 0 }, 586*496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 587*496d1a13SShawn Guo { P_GPLL0_OUT_AUX2, 2 }, 588*496d1a13SShawn Guo { P_GPLL10_OUT_MAIN, 3 }, 589*496d1a13SShawn Guo { P_GPLL8_OUT_MAIN, 4 }, 590*496d1a13SShawn Guo { P_GPLL9_OUT_MAIN, 5 }, 591*496d1a13SShawn Guo { P_GPLL3_OUT_EARLY, 6 }, 592*496d1a13SShawn Guo }; 593*496d1a13SShawn Guo 594*496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_9[] = { 595*496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 596*496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 597*496d1a13SShawn Guo { .hw = &gpll0_out_aux2.clkr.hw }, 598*496d1a13SShawn Guo { .hw = &gpll10.clkr.hw }, 599*496d1a13SShawn Guo { .hw = &gpll8_out_main.clkr.hw }, 600*496d1a13SShawn Guo { .hw = &gpll9_out_main.clkr.hw }, 601*496d1a13SShawn Guo { .hw = &gpll3.clkr.hw }, 602*496d1a13SShawn Guo }; 603*496d1a13SShawn Guo 604*496d1a13SShawn Guo static const struct parent_map gcc_parent_map_10[] = { 605*496d1a13SShawn Guo { P_BI_TCXO, 0 }, 606*496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 607*496d1a13SShawn Guo { P_GPLL8_OUT_EARLY, 2 }, 608*496d1a13SShawn Guo { P_GPLL10_OUT_MAIN, 3 }, 609*496d1a13SShawn Guo { P_GPLL6_OUT_EARLY, 5 }, 610*496d1a13SShawn Guo { P_GPLL3_OUT_MAIN, 6 }, 611*496d1a13SShawn Guo }; 612*496d1a13SShawn Guo 613*496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_10[] = { 614*496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 615*496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 616*496d1a13SShawn Guo { .hw = &gpll8.clkr.hw }, 617*496d1a13SShawn Guo { .hw = &gpll10.clkr.hw }, 618*496d1a13SShawn Guo { .hw = &gpll6.clkr.hw }, 619*496d1a13SShawn Guo { .hw = &gpll3_out_main.clkr.hw }, 620*496d1a13SShawn Guo }; 621*496d1a13SShawn Guo 622*496d1a13SShawn Guo static const struct parent_map gcc_parent_map_12[] = { 623*496d1a13SShawn Guo { P_BI_TCXO, 0 }, 624*496d1a13SShawn Guo { P_GPLL0_OUT_EARLY, 1 }, 625*496d1a13SShawn Guo { P_GPLL0_OUT_AUX2, 2 }, 626*496d1a13SShawn Guo { P_GPLL7_OUT_MAIN, 3 }, 627*496d1a13SShawn Guo { P_GPLL4_OUT_MAIN, 5 }, 628*496d1a13SShawn Guo }; 629*496d1a13SShawn Guo 630*496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_12[] = { 631*496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 632*496d1a13SShawn Guo { .hw = &gpll0.clkr.hw }, 633*496d1a13SShawn Guo { .hw = &gpll0_out_aux2.clkr.hw }, 634*496d1a13SShawn Guo { .hw = &gpll7.clkr.hw }, 635*496d1a13SShawn Guo { .hw = &gpll4.clkr.hw }, 636*496d1a13SShawn Guo }; 637*496d1a13SShawn Guo 638*496d1a13SShawn Guo static const struct parent_map gcc_parent_map_13[] = { 639*496d1a13SShawn Guo { P_BI_TCXO, 0 }, 640*496d1a13SShawn Guo { P_SLEEP_CLK, 5 }, 641*496d1a13SShawn Guo }; 642*496d1a13SShawn Guo 643*496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_13[] = { 644*496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 645*496d1a13SShawn Guo { .fw_name = "sleep_clk" }, 646*496d1a13SShawn Guo }; 647*496d1a13SShawn Guo 648*496d1a13SShawn Guo static const struct parent_map gcc_parent_map_14[] = { 649*496d1a13SShawn Guo { P_BI_TCXO, 0 }, 650*496d1a13SShawn Guo { P_GPLL11_OUT_MAIN, 1 }, 651*496d1a13SShawn Guo { P_GPLL11_OUT_AUX, 2 }, 652*496d1a13SShawn Guo { P_GPLL11_OUT_AUX2, 3 }, 653*496d1a13SShawn Guo }; 654*496d1a13SShawn Guo 655*496d1a13SShawn Guo static const struct clk_parent_data gcc_parents_14[] = { 656*496d1a13SShawn Guo { .fw_name = "bi_tcxo" }, 657*496d1a13SShawn Guo { .hw = &gpll11.clkr.hw }, 658*496d1a13SShawn Guo { .hw = &gpll11.clkr.hw }, 659*496d1a13SShawn Guo { .hw = &gpll11.clkr.hw }, 660*496d1a13SShawn Guo }; 661*496d1a13SShawn Guo 662*496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 663*496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 664*496d1a13SShawn Guo { } 665*496d1a13SShawn Guo }; 666*496d1a13SShawn Guo 667*496d1a13SShawn Guo static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 668*496d1a13SShawn Guo .cmd_rcgr = 0x1a034, 669*496d1a13SShawn Guo .mnd_width = 0, 670*496d1a13SShawn Guo .hid_width = 5, 671*496d1a13SShawn Guo .parent_map = gcc_parent_map_0, 672*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 673*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 674*496d1a13SShawn Guo .name = "gcc_usb30_prim_mock_utmi_clk_src", 675*496d1a13SShawn Guo .parent_data = gcc_parents_0, 676*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_0), 677*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 678*496d1a13SShawn Guo }, 679*496d1a13SShawn Guo }; 680*496d1a13SShawn Guo 681*496d1a13SShawn Guo static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv = { 682*496d1a13SShawn Guo .reg = 0x1a04c, 683*496d1a13SShawn Guo .shift = 0, 684*496d1a13SShawn Guo .width = 2, 685*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data) { 686*496d1a13SShawn Guo .name = "gcc_usb30_prim_mock_utmi_postdiv", 687*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 688*496d1a13SShawn Guo { &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw }, 689*496d1a13SShawn Guo .num_parents = 1, 690*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 691*496d1a13SShawn Guo .ops = &clk_regmap_div_ro_ops, 692*496d1a13SShawn Guo }, 693*496d1a13SShawn Guo }; 694*496d1a13SShawn Guo 695*496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = { 696*496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 697*496d1a13SShawn Guo F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 698*496d1a13SShawn Guo F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 699*496d1a13SShawn Guo F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 700*496d1a13SShawn Guo { } 701*496d1a13SShawn Guo }; 702*496d1a13SShawn Guo 703*496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_axi_clk_src = { 704*496d1a13SShawn Guo .cmd_rcgr = 0x5802c, 705*496d1a13SShawn Guo .mnd_width = 0, 706*496d1a13SShawn Guo .hid_width = 5, 707*496d1a13SShawn Guo .parent_map = gcc_parent_map_4, 708*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_axi_clk_src, 709*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 710*496d1a13SShawn Guo .name = "gcc_camss_axi_clk_src", 711*496d1a13SShawn Guo .parent_data = gcc_parents_4, 712*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_4), 713*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 714*496d1a13SShawn Guo }, 715*496d1a13SShawn Guo }; 716*496d1a13SShawn Guo 717*496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = { 718*496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 719*496d1a13SShawn Guo F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 720*496d1a13SShawn Guo { } 721*496d1a13SShawn Guo }; 722*496d1a13SShawn Guo 723*496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_cci_clk_src = { 724*496d1a13SShawn Guo .cmd_rcgr = 0x56000, 725*496d1a13SShawn Guo .mnd_width = 0, 726*496d1a13SShawn Guo .hid_width = 5, 727*496d1a13SShawn Guo .parent_map = gcc_parent_map_9, 728*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_cci_clk_src, 729*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 730*496d1a13SShawn Guo .name = "gcc_camss_cci_clk_src", 731*496d1a13SShawn Guo .parent_data = gcc_parents_9, 732*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_9), 733*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 734*496d1a13SShawn Guo }, 735*496d1a13SShawn Guo }; 736*496d1a13SShawn Guo 737*496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = { 738*496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 739*496d1a13SShawn Guo F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 740*496d1a13SShawn Guo F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 741*496d1a13SShawn Guo F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0), 742*496d1a13SShawn Guo { } 743*496d1a13SShawn Guo }; 744*496d1a13SShawn Guo 745*496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { 746*496d1a13SShawn Guo .cmd_rcgr = 0x45000, 747*496d1a13SShawn Guo .mnd_width = 0, 748*496d1a13SShawn Guo .hid_width = 5, 749*496d1a13SShawn Guo .parent_map = gcc_parent_map_5, 750*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 751*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 752*496d1a13SShawn Guo .name = "gcc_camss_csi0phytimer_clk_src", 753*496d1a13SShawn Guo .parent_data = gcc_parents_5, 754*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_5), 755*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 756*496d1a13SShawn Guo }, 757*496d1a13SShawn Guo }; 758*496d1a13SShawn Guo 759*496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { 760*496d1a13SShawn Guo .cmd_rcgr = 0x4501c, 761*496d1a13SShawn Guo .mnd_width = 0, 762*496d1a13SShawn Guo .hid_width = 5, 763*496d1a13SShawn Guo .parent_map = gcc_parent_map_5, 764*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 765*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 766*496d1a13SShawn Guo .name = "gcc_camss_csi1phytimer_clk_src", 767*496d1a13SShawn Guo .parent_data = gcc_parents_5, 768*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_5), 769*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 770*496d1a13SShawn Guo }, 771*496d1a13SShawn Guo }; 772*496d1a13SShawn Guo 773*496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { 774*496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 775*496d1a13SShawn Guo F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24), 776*496d1a13SShawn Guo F(64000000, P_GPLL9_OUT_EARLY, 9, 1, 2), 777*496d1a13SShawn Guo { } 778*496d1a13SShawn Guo }; 779*496d1a13SShawn Guo 780*496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_mclk0_clk_src = { 781*496d1a13SShawn Guo .cmd_rcgr = 0x51000, 782*496d1a13SShawn Guo .mnd_width = 8, 783*496d1a13SShawn Guo .hid_width = 5, 784*496d1a13SShawn Guo .parent_map = gcc_parent_map_3, 785*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 786*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 787*496d1a13SShawn Guo .name = "gcc_camss_mclk0_clk_src", 788*496d1a13SShawn Guo .parent_data = gcc_parents_3, 789*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_3), 790*496d1a13SShawn Guo .flags = CLK_OPS_PARENT_ENABLE, 791*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 792*496d1a13SShawn Guo }, 793*496d1a13SShawn Guo }; 794*496d1a13SShawn Guo 795*496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_mclk1_clk_src = { 796*496d1a13SShawn Guo .cmd_rcgr = 0x5101c, 797*496d1a13SShawn Guo .mnd_width = 8, 798*496d1a13SShawn Guo .hid_width = 5, 799*496d1a13SShawn Guo .parent_map = gcc_parent_map_3, 800*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 801*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 802*496d1a13SShawn Guo .name = "gcc_camss_mclk1_clk_src", 803*496d1a13SShawn Guo .parent_data = gcc_parents_3, 804*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_3), 805*496d1a13SShawn Guo .flags = CLK_OPS_PARENT_ENABLE, 806*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 807*496d1a13SShawn Guo }, 808*496d1a13SShawn Guo }; 809*496d1a13SShawn Guo 810*496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_mclk2_clk_src = { 811*496d1a13SShawn Guo .cmd_rcgr = 0x51038, 812*496d1a13SShawn Guo .mnd_width = 8, 813*496d1a13SShawn Guo .hid_width = 5, 814*496d1a13SShawn Guo .parent_map = gcc_parent_map_3, 815*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 816*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 817*496d1a13SShawn Guo .name = "gcc_camss_mclk2_clk_src", 818*496d1a13SShawn Guo .parent_data = gcc_parents_3, 819*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_3), 820*496d1a13SShawn Guo .flags = CLK_OPS_PARENT_ENABLE, 821*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 822*496d1a13SShawn Guo }, 823*496d1a13SShawn Guo }; 824*496d1a13SShawn Guo 825*496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_mclk3_clk_src = { 826*496d1a13SShawn Guo .cmd_rcgr = 0x51054, 827*496d1a13SShawn Guo .mnd_width = 8, 828*496d1a13SShawn Guo .hid_width = 5, 829*496d1a13SShawn Guo .parent_map = gcc_parent_map_3, 830*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 831*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 832*496d1a13SShawn Guo .name = "gcc_camss_mclk3_clk_src", 833*496d1a13SShawn Guo .parent_data = gcc_parents_3, 834*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_3), 835*496d1a13SShawn Guo .flags = CLK_OPS_PARENT_ENABLE, 836*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 837*496d1a13SShawn Guo }, 838*496d1a13SShawn Guo }; 839*496d1a13SShawn Guo 840*496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = { 841*496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 842*496d1a13SShawn Guo F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0), 843*496d1a13SShawn Guo F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 844*496d1a13SShawn Guo { } 845*496d1a13SShawn Guo }; 846*496d1a13SShawn Guo 847*496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = { 848*496d1a13SShawn Guo .cmd_rcgr = 0x55024, 849*496d1a13SShawn Guo .mnd_width = 0, 850*496d1a13SShawn Guo .hid_width = 5, 851*496d1a13SShawn Guo .parent_map = gcc_parent_map_6, 852*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src, 853*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 854*496d1a13SShawn Guo .name = "gcc_camss_ope_ahb_clk_src", 855*496d1a13SShawn Guo .parent_data = gcc_parents_6, 856*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_6), 857*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 858*496d1a13SShawn Guo }, 859*496d1a13SShawn Guo }; 860*496d1a13SShawn Guo 861*496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = { 862*496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 863*496d1a13SShawn Guo F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0), 864*496d1a13SShawn Guo F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0), 865*496d1a13SShawn Guo F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0), 866*496d1a13SShawn Guo F(580000000, P_GPLL8_OUT_EARLY, 1, 0, 0), 867*496d1a13SShawn Guo { } 868*496d1a13SShawn Guo }; 869*496d1a13SShawn Guo 870*496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_ope_clk_src = { 871*496d1a13SShawn Guo .cmd_rcgr = 0x55004, 872*496d1a13SShawn Guo .mnd_width = 0, 873*496d1a13SShawn Guo .hid_width = 5, 874*496d1a13SShawn Guo .parent_map = gcc_parent_map_6, 875*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_ope_clk_src, 876*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 877*496d1a13SShawn Guo .name = "gcc_camss_ope_clk_src", 878*496d1a13SShawn Guo .parent_data = gcc_parents_6, 879*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_6), 880*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 881*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 882*496d1a13SShawn Guo }, 883*496d1a13SShawn Guo }; 884*496d1a13SShawn Guo 885*496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = { 886*496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 887*496d1a13SShawn Guo F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0), 888*496d1a13SShawn Guo F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0), 889*496d1a13SShawn Guo F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0), 890*496d1a13SShawn Guo F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0), 891*496d1a13SShawn Guo F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0), 892*496d1a13SShawn Guo F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0), 893*496d1a13SShawn Guo F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0), 894*496d1a13SShawn Guo F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0), 895*496d1a13SShawn Guo F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0), 896*496d1a13SShawn Guo F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0), 897*496d1a13SShawn Guo F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0), 898*496d1a13SShawn Guo F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0), 899*496d1a13SShawn Guo F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0), 900*496d1a13SShawn Guo F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0), 901*496d1a13SShawn Guo F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0), 902*496d1a13SShawn Guo { } 903*496d1a13SShawn Guo }; 904*496d1a13SShawn Guo 905*496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_tfe_0_clk_src = { 906*496d1a13SShawn Guo .cmd_rcgr = 0x52004, 907*496d1a13SShawn Guo .mnd_width = 8, 908*496d1a13SShawn Guo .hid_width = 5, 909*496d1a13SShawn Guo .parent_map = gcc_parent_map_7, 910*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 911*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 912*496d1a13SShawn Guo .name = "gcc_camss_tfe_0_clk_src", 913*496d1a13SShawn Guo .parent_data = gcc_parents_7, 914*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_7), 915*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 916*496d1a13SShawn Guo }, 917*496d1a13SShawn Guo }; 918*496d1a13SShawn Guo 919*496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = { 920*496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 921*496d1a13SShawn Guo F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0), 922*496d1a13SShawn Guo F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 923*496d1a13SShawn Guo F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 924*496d1a13SShawn Guo F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 925*496d1a13SShawn Guo F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0), 926*496d1a13SShawn Guo { } 927*496d1a13SShawn Guo }; 928*496d1a13SShawn Guo 929*496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = { 930*496d1a13SShawn Guo .cmd_rcgr = 0x52094, 931*496d1a13SShawn Guo .mnd_width = 0, 932*496d1a13SShawn Guo .hid_width = 5, 933*496d1a13SShawn Guo .parent_map = gcc_parent_map_8, 934*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 935*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 936*496d1a13SShawn Guo .name = "gcc_camss_tfe_0_csid_clk_src", 937*496d1a13SShawn Guo .parent_data = gcc_parents_8, 938*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_8), 939*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 940*496d1a13SShawn Guo }, 941*496d1a13SShawn Guo }; 942*496d1a13SShawn Guo 943*496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_tfe_1_clk_src = { 944*496d1a13SShawn Guo .cmd_rcgr = 0x52024, 945*496d1a13SShawn Guo .mnd_width = 8, 946*496d1a13SShawn Guo .hid_width = 5, 947*496d1a13SShawn Guo .parent_map = gcc_parent_map_7, 948*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 949*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 950*496d1a13SShawn Guo .name = "gcc_camss_tfe_1_clk_src", 951*496d1a13SShawn Guo .parent_data = gcc_parents_7, 952*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_7), 953*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 954*496d1a13SShawn Guo }, 955*496d1a13SShawn Guo }; 956*496d1a13SShawn Guo 957*496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = { 958*496d1a13SShawn Guo .cmd_rcgr = 0x520b4, 959*496d1a13SShawn Guo .mnd_width = 0, 960*496d1a13SShawn Guo .hid_width = 5, 961*496d1a13SShawn Guo .parent_map = gcc_parent_map_8, 962*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 963*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 964*496d1a13SShawn Guo .name = "gcc_camss_tfe_1_csid_clk_src", 965*496d1a13SShawn Guo .parent_data = gcc_parents_8, 966*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_8), 967*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 968*496d1a13SShawn Guo }, 969*496d1a13SShawn Guo }; 970*496d1a13SShawn Guo 971*496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = { 972*496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 973*496d1a13SShawn Guo F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 974*496d1a13SShawn Guo F(341333333, P_GPLL6_OUT_EARLY, 1, 4, 9), 975*496d1a13SShawn Guo F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0), 976*496d1a13SShawn Guo { } 977*496d1a13SShawn Guo }; 978*496d1a13SShawn Guo 979*496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = { 980*496d1a13SShawn Guo .cmd_rcgr = 0x52064, 981*496d1a13SShawn Guo .mnd_width = 16, 982*496d1a13SShawn Guo .hid_width = 5, 983*496d1a13SShawn Guo .parent_map = gcc_parent_map_10, 984*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src, 985*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 986*496d1a13SShawn Guo .name = "gcc_camss_tfe_cphy_rx_clk_src", 987*496d1a13SShawn Guo .parent_data = gcc_parents_10, 988*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_10), 989*496d1a13SShawn Guo .flags = CLK_OPS_PARENT_ENABLE, 990*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 991*496d1a13SShawn Guo }, 992*496d1a13SShawn Guo }; 993*496d1a13SShawn Guo 994*496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = { 995*496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 996*496d1a13SShawn Guo F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0), 997*496d1a13SShawn Guo F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0), 998*496d1a13SShawn Guo { } 999*496d1a13SShawn Guo }; 1000*496d1a13SShawn Guo 1001*496d1a13SShawn Guo static struct clk_rcg2 gcc_camss_top_ahb_clk_src = { 1002*496d1a13SShawn Guo .cmd_rcgr = 0x58010, 1003*496d1a13SShawn Guo .mnd_width = 0, 1004*496d1a13SShawn Guo .hid_width = 5, 1005*496d1a13SShawn Guo .parent_map = gcc_parent_map_4, 1006*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_camss_top_ahb_clk_src, 1007*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1008*496d1a13SShawn Guo .name = "gcc_camss_top_ahb_clk_src", 1009*496d1a13SShawn Guo .parent_data = gcc_parents_4, 1010*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_4), 1011*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1012*496d1a13SShawn Guo }, 1013*496d1a13SShawn Guo }; 1014*496d1a13SShawn Guo 1015*496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 1016*496d1a13SShawn Guo F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1017*496d1a13SShawn Guo F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1018*496d1a13SShawn Guo F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1019*496d1a13SShawn Guo F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 1020*496d1a13SShawn Guo { } 1021*496d1a13SShawn Guo }; 1022*496d1a13SShawn Guo 1023*496d1a13SShawn Guo static struct clk_rcg2 gcc_gp1_clk_src = { 1024*496d1a13SShawn Guo .cmd_rcgr = 0x4d004, 1025*496d1a13SShawn Guo .mnd_width = 8, 1026*496d1a13SShawn Guo .hid_width = 5, 1027*496d1a13SShawn Guo .parent_map = gcc_parent_map_2, 1028*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_gp1_clk_src, 1029*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1030*496d1a13SShawn Guo .name = "gcc_gp1_clk_src", 1031*496d1a13SShawn Guo .parent_data = gcc_parents_2, 1032*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_2), 1033*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1034*496d1a13SShawn Guo }, 1035*496d1a13SShawn Guo }; 1036*496d1a13SShawn Guo 1037*496d1a13SShawn Guo static struct clk_rcg2 gcc_gp2_clk_src = { 1038*496d1a13SShawn Guo .cmd_rcgr = 0x4e004, 1039*496d1a13SShawn Guo .mnd_width = 8, 1040*496d1a13SShawn Guo .hid_width = 5, 1041*496d1a13SShawn Guo .parent_map = gcc_parent_map_2, 1042*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_gp1_clk_src, 1043*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1044*496d1a13SShawn Guo .name = "gcc_gp2_clk_src", 1045*496d1a13SShawn Guo .parent_data = gcc_parents_2, 1046*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_2), 1047*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1048*496d1a13SShawn Guo }, 1049*496d1a13SShawn Guo }; 1050*496d1a13SShawn Guo 1051*496d1a13SShawn Guo static struct clk_rcg2 gcc_gp3_clk_src = { 1052*496d1a13SShawn Guo .cmd_rcgr = 0x4f004, 1053*496d1a13SShawn Guo .mnd_width = 8, 1054*496d1a13SShawn Guo .hid_width = 5, 1055*496d1a13SShawn Guo .parent_map = gcc_parent_map_2, 1056*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_gp1_clk_src, 1057*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1058*496d1a13SShawn Guo .name = "gcc_gp3_clk_src", 1059*496d1a13SShawn Guo .parent_data = gcc_parents_2, 1060*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_2), 1061*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1062*496d1a13SShawn Guo }, 1063*496d1a13SShawn Guo }; 1064*496d1a13SShawn Guo 1065*496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 1066*496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 1067*496d1a13SShawn Guo F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0), 1068*496d1a13SShawn Guo { } 1069*496d1a13SShawn Guo }; 1070*496d1a13SShawn Guo 1071*496d1a13SShawn Guo static struct clk_rcg2 gcc_pdm2_clk_src = { 1072*496d1a13SShawn Guo .cmd_rcgr = 0x20010, 1073*496d1a13SShawn Guo .mnd_width = 0, 1074*496d1a13SShawn Guo .hid_width = 5, 1075*496d1a13SShawn Guo .parent_map = gcc_parent_map_0, 1076*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_pdm2_clk_src, 1077*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1078*496d1a13SShawn Guo .name = "gcc_pdm2_clk_src", 1079*496d1a13SShawn Guo .parent_data = gcc_parents_0, 1080*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_0), 1081*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1082*496d1a13SShawn Guo }, 1083*496d1a13SShawn Guo }; 1084*496d1a13SShawn Guo 1085*496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 1086*496d1a13SShawn Guo F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625), 1087*496d1a13SShawn Guo F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625), 1088*496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 1089*496d1a13SShawn Guo F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625), 1090*496d1a13SShawn Guo F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75), 1091*496d1a13SShawn Guo F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25), 1092*496d1a13SShawn Guo F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75), 1093*496d1a13SShawn Guo F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1094*496d1a13SShawn Guo F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15), 1095*496d1a13SShawn Guo F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25), 1096*496d1a13SShawn Guo F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1097*496d1a13SShawn Guo F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375), 1098*496d1a13SShawn Guo F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75), 1099*496d1a13SShawn Guo F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625), 1100*496d1a13SShawn Guo F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0), 1101*496d1a13SShawn Guo F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0), 1102*496d1a13SShawn Guo { } 1103*496d1a13SShawn Guo }; 1104*496d1a13SShawn Guo 1105*496d1a13SShawn Guo static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 1106*496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s0_clk_src", 1107*496d1a13SShawn Guo .parent_data = gcc_parents_1, 1108*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_1), 1109*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1110*496d1a13SShawn Guo }; 1111*496d1a13SShawn Guo 1112*496d1a13SShawn Guo static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 1113*496d1a13SShawn Guo .cmd_rcgr = 0x1f148, 1114*496d1a13SShawn Guo .mnd_width = 16, 1115*496d1a13SShawn Guo .hid_width = 5, 1116*496d1a13SShawn Guo .parent_map = gcc_parent_map_1, 1117*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1118*496d1a13SShawn Guo .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 1119*496d1a13SShawn Guo }; 1120*496d1a13SShawn Guo 1121*496d1a13SShawn Guo static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 1122*496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s1_clk_src", 1123*496d1a13SShawn Guo .parent_data = gcc_parents_1, 1124*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_1), 1125*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1126*496d1a13SShawn Guo }; 1127*496d1a13SShawn Guo 1128*496d1a13SShawn Guo static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 1129*496d1a13SShawn Guo .cmd_rcgr = 0x1f278, 1130*496d1a13SShawn Guo .mnd_width = 16, 1131*496d1a13SShawn Guo .hid_width = 5, 1132*496d1a13SShawn Guo .parent_map = gcc_parent_map_1, 1133*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1134*496d1a13SShawn Guo .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 1135*496d1a13SShawn Guo }; 1136*496d1a13SShawn Guo 1137*496d1a13SShawn Guo static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 1138*496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s2_clk_src", 1139*496d1a13SShawn Guo .parent_data = gcc_parents_1, 1140*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_1), 1141*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1142*496d1a13SShawn Guo }; 1143*496d1a13SShawn Guo 1144*496d1a13SShawn Guo static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 1145*496d1a13SShawn Guo .cmd_rcgr = 0x1f3a8, 1146*496d1a13SShawn Guo .mnd_width = 16, 1147*496d1a13SShawn Guo .hid_width = 5, 1148*496d1a13SShawn Guo .parent_map = gcc_parent_map_1, 1149*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1150*496d1a13SShawn Guo .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 1151*496d1a13SShawn Guo }; 1152*496d1a13SShawn Guo 1153*496d1a13SShawn Guo static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 1154*496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s3_clk_src", 1155*496d1a13SShawn Guo .parent_data = gcc_parents_1, 1156*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_1), 1157*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1158*496d1a13SShawn Guo }; 1159*496d1a13SShawn Guo 1160*496d1a13SShawn Guo static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 1161*496d1a13SShawn Guo .cmd_rcgr = 0x1f4d8, 1162*496d1a13SShawn Guo .mnd_width = 16, 1163*496d1a13SShawn Guo .hid_width = 5, 1164*496d1a13SShawn Guo .parent_map = gcc_parent_map_1, 1165*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1166*496d1a13SShawn Guo .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 1167*496d1a13SShawn Guo }; 1168*496d1a13SShawn Guo 1169*496d1a13SShawn Guo static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 1170*496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s4_clk_src", 1171*496d1a13SShawn Guo .parent_data = gcc_parents_1, 1172*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_1), 1173*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1174*496d1a13SShawn Guo }; 1175*496d1a13SShawn Guo 1176*496d1a13SShawn Guo static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 1177*496d1a13SShawn Guo .cmd_rcgr = 0x1f608, 1178*496d1a13SShawn Guo .mnd_width = 16, 1179*496d1a13SShawn Guo .hid_width = 5, 1180*496d1a13SShawn Guo .parent_map = gcc_parent_map_1, 1181*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1182*496d1a13SShawn Guo .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 1183*496d1a13SShawn Guo }; 1184*496d1a13SShawn Guo 1185*496d1a13SShawn Guo static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 1186*496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s5_clk_src", 1187*496d1a13SShawn Guo .parent_data = gcc_parents_1, 1188*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_1), 1189*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1190*496d1a13SShawn Guo }; 1191*496d1a13SShawn Guo 1192*496d1a13SShawn Guo static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 1193*496d1a13SShawn Guo .cmd_rcgr = 0x1f738, 1194*496d1a13SShawn Guo .mnd_width = 16, 1195*496d1a13SShawn Guo .hid_width = 5, 1196*496d1a13SShawn Guo .parent_map = gcc_parent_map_1, 1197*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1198*496d1a13SShawn Guo .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 1199*496d1a13SShawn Guo }; 1200*496d1a13SShawn Guo 1201*496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 1202*496d1a13SShawn Guo F(144000, P_BI_TCXO, 16, 3, 25), 1203*496d1a13SShawn Guo F(400000, P_BI_TCXO, 12, 1, 4), 1204*496d1a13SShawn Guo F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3), 1205*496d1a13SShawn Guo F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2), 1206*496d1a13SShawn Guo F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1207*496d1a13SShawn Guo F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1208*496d1a13SShawn Guo F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 1209*496d1a13SShawn Guo F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 1210*496d1a13SShawn Guo { } 1211*496d1a13SShawn Guo }; 1212*496d1a13SShawn Guo 1213*496d1a13SShawn Guo static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 1214*496d1a13SShawn Guo .cmd_rcgr = 0x38028, 1215*496d1a13SShawn Guo .mnd_width = 8, 1216*496d1a13SShawn Guo .hid_width = 5, 1217*496d1a13SShawn Guo .parent_map = gcc_parent_map_1, 1218*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 1219*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1220*496d1a13SShawn Guo .name = "gcc_sdcc1_apps_clk_src", 1221*496d1a13SShawn Guo .parent_data = gcc_parents_1, 1222*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_1), 1223*496d1a13SShawn Guo .ops = &clk_rcg2_floor_ops, 1224*496d1a13SShawn Guo }, 1225*496d1a13SShawn Guo }; 1226*496d1a13SShawn Guo 1227*496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 1228*496d1a13SShawn Guo F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1229*496d1a13SShawn Guo F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1230*496d1a13SShawn Guo F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1231*496d1a13SShawn Guo F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1232*496d1a13SShawn Guo F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 1233*496d1a13SShawn Guo { } 1234*496d1a13SShawn Guo }; 1235*496d1a13SShawn Guo 1236*496d1a13SShawn Guo static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 1237*496d1a13SShawn Guo .cmd_rcgr = 0x38010, 1238*496d1a13SShawn Guo .mnd_width = 0, 1239*496d1a13SShawn Guo .hid_width = 5, 1240*496d1a13SShawn Guo .parent_map = gcc_parent_map_0, 1241*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 1242*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1243*496d1a13SShawn Guo .name = "gcc_sdcc1_ice_core_clk_src", 1244*496d1a13SShawn Guo .parent_data = gcc_parents_0, 1245*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_0), 1246*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1247*496d1a13SShawn Guo }, 1248*496d1a13SShawn Guo }; 1249*496d1a13SShawn Guo 1250*496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1251*496d1a13SShawn Guo F(400000, P_BI_TCXO, 12, 1, 4), 1252*496d1a13SShawn Guo F(19200000, P_BI_TCXO, 1, 0, 0), 1253*496d1a13SShawn Guo F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1254*496d1a13SShawn Guo F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1255*496d1a13SShawn Guo F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1256*496d1a13SShawn Guo F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0), 1257*496d1a13SShawn Guo { } 1258*496d1a13SShawn Guo }; 1259*496d1a13SShawn Guo 1260*496d1a13SShawn Guo static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1261*496d1a13SShawn Guo .cmd_rcgr = 0x1e00c, 1262*496d1a13SShawn Guo .mnd_width = 8, 1263*496d1a13SShawn Guo .hid_width = 5, 1264*496d1a13SShawn Guo .parent_map = gcc_parent_map_12, 1265*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1266*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1267*496d1a13SShawn Guo .name = "gcc_sdcc2_apps_clk_src", 1268*496d1a13SShawn Guo .parent_data = gcc_parents_12, 1269*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_12), 1270*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1271*496d1a13SShawn Guo }, 1272*496d1a13SShawn Guo }; 1273*496d1a13SShawn Guo 1274*496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1275*496d1a13SShawn Guo F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0), 1276*496d1a13SShawn Guo F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0), 1277*496d1a13SShawn Guo F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1278*496d1a13SShawn Guo F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1279*496d1a13SShawn Guo { } 1280*496d1a13SShawn Guo }; 1281*496d1a13SShawn Guo 1282*496d1a13SShawn Guo static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1283*496d1a13SShawn Guo .cmd_rcgr = 0x1a01c, 1284*496d1a13SShawn Guo .mnd_width = 8, 1285*496d1a13SShawn Guo .hid_width = 5, 1286*496d1a13SShawn Guo .parent_map = gcc_parent_map_0, 1287*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1288*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1289*496d1a13SShawn Guo .name = "gcc_usb30_prim_master_clk_src", 1290*496d1a13SShawn Guo .parent_data = gcc_parents_0, 1291*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_0), 1292*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1293*496d1a13SShawn Guo }, 1294*496d1a13SShawn Guo }; 1295*496d1a13SShawn Guo 1296*496d1a13SShawn Guo static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1297*496d1a13SShawn Guo .cmd_rcgr = 0x1a060, 1298*496d1a13SShawn Guo .mnd_width = 0, 1299*496d1a13SShawn Guo .hid_width = 5, 1300*496d1a13SShawn Guo .parent_map = gcc_parent_map_13, 1301*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1302*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1303*496d1a13SShawn Guo .name = "gcc_usb3_prim_phy_aux_clk_src", 1304*496d1a13SShawn Guo .parent_data = gcc_parents_13, 1305*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_13), 1306*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1307*496d1a13SShawn Guo }, 1308*496d1a13SShawn Guo }; 1309*496d1a13SShawn Guo 1310*496d1a13SShawn Guo static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = { 1311*496d1a13SShawn Guo F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0), 1312*496d1a13SShawn Guo F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0), 1313*496d1a13SShawn Guo F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0), 1314*496d1a13SShawn Guo F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0), 1315*496d1a13SShawn Guo { } 1316*496d1a13SShawn Guo }; 1317*496d1a13SShawn Guo 1318*496d1a13SShawn Guo static struct clk_rcg2 gcc_video_venus_clk_src = { 1319*496d1a13SShawn Guo .cmd_rcgr = 0x58060, 1320*496d1a13SShawn Guo .mnd_width = 0, 1321*496d1a13SShawn Guo .hid_width = 5, 1322*496d1a13SShawn Guo .parent_map = gcc_parent_map_14, 1323*496d1a13SShawn Guo .freq_tbl = ftbl_gcc_video_venus_clk_src, 1324*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data){ 1325*496d1a13SShawn Guo .name = "gcc_video_venus_clk_src", 1326*496d1a13SShawn Guo .parent_data = gcc_parents_14, 1327*496d1a13SShawn Guo .num_parents = ARRAY_SIZE(gcc_parents_14), 1328*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1329*496d1a13SShawn Guo .ops = &clk_rcg2_ops, 1330*496d1a13SShawn Guo }, 1331*496d1a13SShawn Guo }; 1332*496d1a13SShawn Guo 1333*496d1a13SShawn Guo static struct clk_branch gcc_ahb2phy_csi_clk = { 1334*496d1a13SShawn Guo .halt_reg = 0x1d004, 1335*496d1a13SShawn Guo .halt_check = BRANCH_HALT_DELAY, 1336*496d1a13SShawn Guo .hwcg_reg = 0x1d004, 1337*496d1a13SShawn Guo .hwcg_bit = 1, 1338*496d1a13SShawn Guo .clkr = { 1339*496d1a13SShawn Guo .enable_reg = 0x1d004, 1340*496d1a13SShawn Guo .enable_mask = BIT(0), 1341*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1342*496d1a13SShawn Guo .name = "gcc_ahb2phy_csi_clk", 1343*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1344*496d1a13SShawn Guo }, 1345*496d1a13SShawn Guo }, 1346*496d1a13SShawn Guo }; 1347*496d1a13SShawn Guo 1348*496d1a13SShawn Guo static struct clk_branch gcc_ahb2phy_usb_clk = { 1349*496d1a13SShawn Guo .halt_reg = 0x1d008, 1350*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1351*496d1a13SShawn Guo .hwcg_reg = 0x1d008, 1352*496d1a13SShawn Guo .hwcg_bit = 1, 1353*496d1a13SShawn Guo .clkr = { 1354*496d1a13SShawn Guo .enable_reg = 0x1d008, 1355*496d1a13SShawn Guo .enable_mask = BIT(0), 1356*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1357*496d1a13SShawn Guo .name = "gcc_ahb2phy_usb_clk", 1358*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1359*496d1a13SShawn Guo }, 1360*496d1a13SShawn Guo }, 1361*496d1a13SShawn Guo }; 1362*496d1a13SShawn Guo 1363*496d1a13SShawn Guo static struct clk_branch gcc_bimc_gpu_axi_clk = { 1364*496d1a13SShawn Guo .halt_reg = 0x71154, 1365*496d1a13SShawn Guo .halt_check = BRANCH_HALT_DELAY, 1366*496d1a13SShawn Guo .hwcg_reg = 0x71154, 1367*496d1a13SShawn Guo .hwcg_bit = 1, 1368*496d1a13SShawn Guo .clkr = { 1369*496d1a13SShawn Guo .enable_reg = 0x71154, 1370*496d1a13SShawn Guo .enable_mask = BIT(0), 1371*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1372*496d1a13SShawn Guo .name = "gcc_bimc_gpu_axi_clk", 1373*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1374*496d1a13SShawn Guo }, 1375*496d1a13SShawn Guo }, 1376*496d1a13SShawn Guo }; 1377*496d1a13SShawn Guo 1378*496d1a13SShawn Guo static struct clk_branch gcc_boot_rom_ahb_clk = { 1379*496d1a13SShawn Guo .halt_reg = 0x23004, 1380*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 1381*496d1a13SShawn Guo .hwcg_reg = 0x23004, 1382*496d1a13SShawn Guo .hwcg_bit = 1, 1383*496d1a13SShawn Guo .clkr = { 1384*496d1a13SShawn Guo .enable_reg = 0x79004, 1385*496d1a13SShawn Guo .enable_mask = BIT(10), 1386*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1387*496d1a13SShawn Guo .name = "gcc_boot_rom_ahb_clk", 1388*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1389*496d1a13SShawn Guo }, 1390*496d1a13SShawn Guo }, 1391*496d1a13SShawn Guo }; 1392*496d1a13SShawn Guo 1393*496d1a13SShawn Guo static struct clk_branch gcc_cam_throttle_nrt_clk = { 1394*496d1a13SShawn Guo .halt_reg = 0x17070, 1395*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 1396*496d1a13SShawn Guo .hwcg_reg = 0x17070, 1397*496d1a13SShawn Guo .hwcg_bit = 1, 1398*496d1a13SShawn Guo .clkr = { 1399*496d1a13SShawn Guo .enable_reg = 0x79004, 1400*496d1a13SShawn Guo .enable_mask = BIT(27), 1401*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1402*496d1a13SShawn Guo .name = "gcc_cam_throttle_nrt_clk", 1403*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1404*496d1a13SShawn Guo }, 1405*496d1a13SShawn Guo }, 1406*496d1a13SShawn Guo }; 1407*496d1a13SShawn Guo 1408*496d1a13SShawn Guo static struct clk_branch gcc_cam_throttle_rt_clk = { 1409*496d1a13SShawn Guo .halt_reg = 0x1706c, 1410*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 1411*496d1a13SShawn Guo .hwcg_reg = 0x1706c, 1412*496d1a13SShawn Guo .hwcg_bit = 1, 1413*496d1a13SShawn Guo .clkr = { 1414*496d1a13SShawn Guo .enable_reg = 0x79004, 1415*496d1a13SShawn Guo .enable_mask = BIT(26), 1416*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1417*496d1a13SShawn Guo .name = "gcc_cam_throttle_rt_clk", 1418*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1419*496d1a13SShawn Guo }, 1420*496d1a13SShawn Guo }, 1421*496d1a13SShawn Guo }; 1422*496d1a13SShawn Guo 1423*496d1a13SShawn Guo static struct clk_branch gcc_camera_ahb_clk = { 1424*496d1a13SShawn Guo .halt_reg = 0x17008, 1425*496d1a13SShawn Guo .halt_check = BRANCH_HALT_DELAY, 1426*496d1a13SShawn Guo .hwcg_reg = 0x17008, 1427*496d1a13SShawn Guo .hwcg_bit = 1, 1428*496d1a13SShawn Guo .clkr = { 1429*496d1a13SShawn Guo .enable_reg = 0x17008, 1430*496d1a13SShawn Guo .enable_mask = BIT(0), 1431*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1432*496d1a13SShawn Guo .name = "gcc_camera_ahb_clk", 1433*496d1a13SShawn Guo .flags = CLK_IS_CRITICAL, 1434*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1435*496d1a13SShawn Guo }, 1436*496d1a13SShawn Guo }, 1437*496d1a13SShawn Guo }; 1438*496d1a13SShawn Guo 1439*496d1a13SShawn Guo static struct clk_branch gcc_camera_xo_clk = { 1440*496d1a13SShawn Guo .halt_reg = 0x17028, 1441*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1442*496d1a13SShawn Guo .clkr = { 1443*496d1a13SShawn Guo .enable_reg = 0x17028, 1444*496d1a13SShawn Guo .enable_mask = BIT(0), 1445*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1446*496d1a13SShawn Guo .name = "gcc_camera_xo_clk", 1447*496d1a13SShawn Guo .flags = CLK_IS_CRITICAL, 1448*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1449*496d1a13SShawn Guo }, 1450*496d1a13SShawn Guo }, 1451*496d1a13SShawn Guo }; 1452*496d1a13SShawn Guo 1453*496d1a13SShawn Guo static struct clk_branch gcc_camss_axi_clk = { 1454*496d1a13SShawn Guo .halt_reg = 0x58044, 1455*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1456*496d1a13SShawn Guo .clkr = { 1457*496d1a13SShawn Guo .enable_reg = 0x58044, 1458*496d1a13SShawn Guo .enable_mask = BIT(0), 1459*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1460*496d1a13SShawn Guo .name = "gcc_camss_axi_clk", 1461*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1462*496d1a13SShawn Guo { &gcc_camss_axi_clk_src.clkr.hw }, 1463*496d1a13SShawn Guo .num_parents = 1, 1464*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1465*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1466*496d1a13SShawn Guo }, 1467*496d1a13SShawn Guo }, 1468*496d1a13SShawn Guo }; 1469*496d1a13SShawn Guo 1470*496d1a13SShawn Guo static struct clk_branch gcc_camss_camnoc_atb_clk = { 1471*496d1a13SShawn Guo .halt_reg = 0x5804c, 1472*496d1a13SShawn Guo .halt_check = BRANCH_HALT_DELAY, 1473*496d1a13SShawn Guo .hwcg_reg = 0x5804c, 1474*496d1a13SShawn Guo .hwcg_bit = 1, 1475*496d1a13SShawn Guo .clkr = { 1476*496d1a13SShawn Guo .enable_reg = 0x5804c, 1477*496d1a13SShawn Guo .enable_mask = BIT(0), 1478*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1479*496d1a13SShawn Guo .name = "gcc_camss_camnoc_atb_clk", 1480*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1481*496d1a13SShawn Guo }, 1482*496d1a13SShawn Guo }, 1483*496d1a13SShawn Guo }; 1484*496d1a13SShawn Guo 1485*496d1a13SShawn Guo static struct clk_branch gcc_camss_camnoc_nts_xo_clk = { 1486*496d1a13SShawn Guo .halt_reg = 0x58050, 1487*496d1a13SShawn Guo .halt_check = BRANCH_HALT_DELAY, 1488*496d1a13SShawn Guo .hwcg_reg = 0x58050, 1489*496d1a13SShawn Guo .hwcg_bit = 1, 1490*496d1a13SShawn Guo .clkr = { 1491*496d1a13SShawn Guo .enable_reg = 0x58050, 1492*496d1a13SShawn Guo .enable_mask = BIT(0), 1493*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1494*496d1a13SShawn Guo .name = "gcc_camss_camnoc_nts_xo_clk", 1495*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1496*496d1a13SShawn Guo }, 1497*496d1a13SShawn Guo }, 1498*496d1a13SShawn Guo }; 1499*496d1a13SShawn Guo 1500*496d1a13SShawn Guo static struct clk_branch gcc_camss_cci_0_clk = { 1501*496d1a13SShawn Guo .halt_reg = 0x56018, 1502*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1503*496d1a13SShawn Guo .clkr = { 1504*496d1a13SShawn Guo .enable_reg = 0x56018, 1505*496d1a13SShawn Guo .enable_mask = BIT(0), 1506*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1507*496d1a13SShawn Guo .name = "gcc_camss_cci_0_clk", 1508*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1509*496d1a13SShawn Guo { &gcc_camss_cci_clk_src.clkr.hw }, 1510*496d1a13SShawn Guo .num_parents = 1, 1511*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1512*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1513*496d1a13SShawn Guo }, 1514*496d1a13SShawn Guo }, 1515*496d1a13SShawn Guo }; 1516*496d1a13SShawn Guo 1517*496d1a13SShawn Guo static struct clk_branch gcc_camss_cphy_0_clk = { 1518*496d1a13SShawn Guo .halt_reg = 0x52088, 1519*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1520*496d1a13SShawn Guo .clkr = { 1521*496d1a13SShawn Guo .enable_reg = 0x52088, 1522*496d1a13SShawn Guo .enable_mask = BIT(0), 1523*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1524*496d1a13SShawn Guo .name = "gcc_camss_cphy_0_clk", 1525*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1526*496d1a13SShawn Guo { &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw }, 1527*496d1a13SShawn Guo .num_parents = 1, 1528*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1529*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1530*496d1a13SShawn Guo }, 1531*496d1a13SShawn Guo }, 1532*496d1a13SShawn Guo }; 1533*496d1a13SShawn Guo 1534*496d1a13SShawn Guo static struct clk_branch gcc_camss_cphy_1_clk = { 1535*496d1a13SShawn Guo .halt_reg = 0x5208c, 1536*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1537*496d1a13SShawn Guo .clkr = { 1538*496d1a13SShawn Guo .enable_reg = 0x5208c, 1539*496d1a13SShawn Guo .enable_mask = BIT(0), 1540*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1541*496d1a13SShawn Guo .name = "gcc_camss_cphy_1_clk", 1542*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1543*496d1a13SShawn Guo { &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw }, 1544*496d1a13SShawn Guo .num_parents = 1, 1545*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1546*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1547*496d1a13SShawn Guo }, 1548*496d1a13SShawn Guo }, 1549*496d1a13SShawn Guo }; 1550*496d1a13SShawn Guo 1551*496d1a13SShawn Guo static struct clk_branch gcc_camss_csi0phytimer_clk = { 1552*496d1a13SShawn Guo .halt_reg = 0x45018, 1553*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1554*496d1a13SShawn Guo .clkr = { 1555*496d1a13SShawn Guo .enable_reg = 0x45018, 1556*496d1a13SShawn Guo .enable_mask = BIT(0), 1557*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1558*496d1a13SShawn Guo .name = "gcc_camss_csi0phytimer_clk", 1559*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1560*496d1a13SShawn Guo { &gcc_camss_csi0phytimer_clk_src.clkr.hw }, 1561*496d1a13SShawn Guo .num_parents = 1, 1562*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1563*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1564*496d1a13SShawn Guo }, 1565*496d1a13SShawn Guo }, 1566*496d1a13SShawn Guo }; 1567*496d1a13SShawn Guo 1568*496d1a13SShawn Guo static struct clk_branch gcc_camss_csi1phytimer_clk = { 1569*496d1a13SShawn Guo .halt_reg = 0x45034, 1570*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1571*496d1a13SShawn Guo .clkr = { 1572*496d1a13SShawn Guo .enable_reg = 0x45034, 1573*496d1a13SShawn Guo .enable_mask = BIT(0), 1574*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1575*496d1a13SShawn Guo .name = "gcc_camss_csi1phytimer_clk", 1576*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1577*496d1a13SShawn Guo { &gcc_camss_csi1phytimer_clk_src.clkr.hw }, 1578*496d1a13SShawn Guo .num_parents = 1, 1579*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1580*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1581*496d1a13SShawn Guo }, 1582*496d1a13SShawn Guo }, 1583*496d1a13SShawn Guo }; 1584*496d1a13SShawn Guo 1585*496d1a13SShawn Guo static struct clk_branch gcc_camss_mclk0_clk = { 1586*496d1a13SShawn Guo .halt_reg = 0x51018, 1587*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1588*496d1a13SShawn Guo .clkr = { 1589*496d1a13SShawn Guo .enable_reg = 0x51018, 1590*496d1a13SShawn Guo .enable_mask = BIT(0), 1591*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1592*496d1a13SShawn Guo .name = "gcc_camss_mclk0_clk", 1593*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1594*496d1a13SShawn Guo { &gcc_camss_mclk0_clk_src.clkr.hw }, 1595*496d1a13SShawn Guo .num_parents = 1, 1596*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1597*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1598*496d1a13SShawn Guo }, 1599*496d1a13SShawn Guo }, 1600*496d1a13SShawn Guo }; 1601*496d1a13SShawn Guo 1602*496d1a13SShawn Guo static struct clk_branch gcc_camss_mclk1_clk = { 1603*496d1a13SShawn Guo .halt_reg = 0x51034, 1604*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1605*496d1a13SShawn Guo .clkr = { 1606*496d1a13SShawn Guo .enable_reg = 0x51034, 1607*496d1a13SShawn Guo .enable_mask = BIT(0), 1608*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1609*496d1a13SShawn Guo .name = "gcc_camss_mclk1_clk", 1610*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1611*496d1a13SShawn Guo { &gcc_camss_mclk1_clk_src.clkr.hw }, 1612*496d1a13SShawn Guo .num_parents = 1, 1613*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1614*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1615*496d1a13SShawn Guo }, 1616*496d1a13SShawn Guo }, 1617*496d1a13SShawn Guo }; 1618*496d1a13SShawn Guo 1619*496d1a13SShawn Guo static struct clk_branch gcc_camss_mclk2_clk = { 1620*496d1a13SShawn Guo .halt_reg = 0x51050, 1621*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1622*496d1a13SShawn Guo .clkr = { 1623*496d1a13SShawn Guo .enable_reg = 0x51050, 1624*496d1a13SShawn Guo .enable_mask = BIT(0), 1625*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1626*496d1a13SShawn Guo .name = "gcc_camss_mclk2_clk", 1627*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1628*496d1a13SShawn Guo { &gcc_camss_mclk2_clk_src.clkr.hw }, 1629*496d1a13SShawn Guo .num_parents = 1, 1630*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1631*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1632*496d1a13SShawn Guo }, 1633*496d1a13SShawn Guo }, 1634*496d1a13SShawn Guo }; 1635*496d1a13SShawn Guo 1636*496d1a13SShawn Guo static struct clk_branch gcc_camss_mclk3_clk = { 1637*496d1a13SShawn Guo .halt_reg = 0x5106c, 1638*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1639*496d1a13SShawn Guo .clkr = { 1640*496d1a13SShawn Guo .enable_reg = 0x5106c, 1641*496d1a13SShawn Guo .enable_mask = BIT(0), 1642*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1643*496d1a13SShawn Guo .name = "gcc_camss_mclk3_clk", 1644*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1645*496d1a13SShawn Guo { &gcc_camss_mclk3_clk_src.clkr.hw }, 1646*496d1a13SShawn Guo .num_parents = 1, 1647*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1648*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1649*496d1a13SShawn Guo }, 1650*496d1a13SShawn Guo }, 1651*496d1a13SShawn Guo }; 1652*496d1a13SShawn Guo 1653*496d1a13SShawn Guo static struct clk_branch gcc_camss_nrt_axi_clk = { 1654*496d1a13SShawn Guo .halt_reg = 0x58054, 1655*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1656*496d1a13SShawn Guo .clkr = { 1657*496d1a13SShawn Guo .enable_reg = 0x58054, 1658*496d1a13SShawn Guo .enable_mask = BIT(0), 1659*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1660*496d1a13SShawn Guo .name = "gcc_camss_nrt_axi_clk", 1661*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1662*496d1a13SShawn Guo }, 1663*496d1a13SShawn Guo }, 1664*496d1a13SShawn Guo }; 1665*496d1a13SShawn Guo 1666*496d1a13SShawn Guo static struct clk_branch gcc_camss_ope_ahb_clk = { 1667*496d1a13SShawn Guo .halt_reg = 0x5503c, 1668*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1669*496d1a13SShawn Guo .clkr = { 1670*496d1a13SShawn Guo .enable_reg = 0x5503c, 1671*496d1a13SShawn Guo .enable_mask = BIT(0), 1672*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1673*496d1a13SShawn Guo .name = "gcc_camss_ope_ahb_clk", 1674*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1675*496d1a13SShawn Guo { &gcc_camss_ope_ahb_clk_src.clkr.hw }, 1676*496d1a13SShawn Guo .num_parents = 1, 1677*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1678*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1679*496d1a13SShawn Guo }, 1680*496d1a13SShawn Guo }, 1681*496d1a13SShawn Guo }; 1682*496d1a13SShawn Guo 1683*496d1a13SShawn Guo static struct clk_branch gcc_camss_ope_clk = { 1684*496d1a13SShawn Guo .halt_reg = 0x5501c, 1685*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1686*496d1a13SShawn Guo .clkr = { 1687*496d1a13SShawn Guo .enable_reg = 0x5501c, 1688*496d1a13SShawn Guo .enable_mask = BIT(0), 1689*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1690*496d1a13SShawn Guo .name = "gcc_camss_ope_clk", 1691*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1692*496d1a13SShawn Guo { &gcc_camss_ope_clk_src.clkr.hw }, 1693*496d1a13SShawn Guo .num_parents = 1, 1694*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1695*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1696*496d1a13SShawn Guo }, 1697*496d1a13SShawn Guo }, 1698*496d1a13SShawn Guo }; 1699*496d1a13SShawn Guo 1700*496d1a13SShawn Guo static struct clk_branch gcc_camss_rt_axi_clk = { 1701*496d1a13SShawn Guo .halt_reg = 0x5805c, 1702*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1703*496d1a13SShawn Guo .clkr = { 1704*496d1a13SShawn Guo .enable_reg = 0x5805c, 1705*496d1a13SShawn Guo .enable_mask = BIT(0), 1706*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1707*496d1a13SShawn Guo .name = "gcc_camss_rt_axi_clk", 1708*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1709*496d1a13SShawn Guo }, 1710*496d1a13SShawn Guo }, 1711*496d1a13SShawn Guo }; 1712*496d1a13SShawn Guo 1713*496d1a13SShawn Guo static struct clk_branch gcc_camss_tfe_0_clk = { 1714*496d1a13SShawn Guo .halt_reg = 0x5201c, 1715*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1716*496d1a13SShawn Guo .clkr = { 1717*496d1a13SShawn Guo .enable_reg = 0x5201c, 1718*496d1a13SShawn Guo .enable_mask = BIT(0), 1719*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1720*496d1a13SShawn Guo .name = "gcc_camss_tfe_0_clk", 1721*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1722*496d1a13SShawn Guo { &gcc_camss_tfe_0_clk_src.clkr.hw }, 1723*496d1a13SShawn Guo .num_parents = 1, 1724*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1725*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1726*496d1a13SShawn Guo }, 1727*496d1a13SShawn Guo }, 1728*496d1a13SShawn Guo }; 1729*496d1a13SShawn Guo 1730*496d1a13SShawn Guo static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = { 1731*496d1a13SShawn Guo .halt_reg = 0x5207c, 1732*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1733*496d1a13SShawn Guo .clkr = { 1734*496d1a13SShawn Guo .enable_reg = 0x5207c, 1735*496d1a13SShawn Guo .enable_mask = BIT(0), 1736*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1737*496d1a13SShawn Guo .name = "gcc_camss_tfe_0_cphy_rx_clk", 1738*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1739*496d1a13SShawn Guo { &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw }, 1740*496d1a13SShawn Guo .num_parents = 1, 1741*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1742*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1743*496d1a13SShawn Guo }, 1744*496d1a13SShawn Guo }, 1745*496d1a13SShawn Guo }; 1746*496d1a13SShawn Guo 1747*496d1a13SShawn Guo static struct clk_branch gcc_camss_tfe_0_csid_clk = { 1748*496d1a13SShawn Guo .halt_reg = 0x520ac, 1749*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1750*496d1a13SShawn Guo .clkr = { 1751*496d1a13SShawn Guo .enable_reg = 0x520ac, 1752*496d1a13SShawn Guo .enable_mask = BIT(0), 1753*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1754*496d1a13SShawn Guo .name = "gcc_camss_tfe_0_csid_clk", 1755*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1756*496d1a13SShawn Guo { &gcc_camss_tfe_0_csid_clk_src.clkr.hw }, 1757*496d1a13SShawn Guo .num_parents = 1, 1758*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1759*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1760*496d1a13SShawn Guo }, 1761*496d1a13SShawn Guo }, 1762*496d1a13SShawn Guo }; 1763*496d1a13SShawn Guo 1764*496d1a13SShawn Guo static struct clk_branch gcc_camss_tfe_1_clk = { 1765*496d1a13SShawn Guo .halt_reg = 0x5203c, 1766*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1767*496d1a13SShawn Guo .clkr = { 1768*496d1a13SShawn Guo .enable_reg = 0x5203c, 1769*496d1a13SShawn Guo .enable_mask = BIT(0), 1770*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1771*496d1a13SShawn Guo .name = "gcc_camss_tfe_1_clk", 1772*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1773*496d1a13SShawn Guo { &gcc_camss_tfe_1_clk_src.clkr.hw }, 1774*496d1a13SShawn Guo .num_parents = 1, 1775*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1776*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1777*496d1a13SShawn Guo }, 1778*496d1a13SShawn Guo }, 1779*496d1a13SShawn Guo }; 1780*496d1a13SShawn Guo 1781*496d1a13SShawn Guo static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = { 1782*496d1a13SShawn Guo .halt_reg = 0x52080, 1783*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1784*496d1a13SShawn Guo .clkr = { 1785*496d1a13SShawn Guo .enable_reg = 0x52080, 1786*496d1a13SShawn Guo .enable_mask = BIT(0), 1787*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1788*496d1a13SShawn Guo .name = "gcc_camss_tfe_1_cphy_rx_clk", 1789*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1790*496d1a13SShawn Guo { &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw }, 1791*496d1a13SShawn Guo .num_parents = 1, 1792*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1793*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1794*496d1a13SShawn Guo }, 1795*496d1a13SShawn Guo }, 1796*496d1a13SShawn Guo }; 1797*496d1a13SShawn Guo 1798*496d1a13SShawn Guo static struct clk_branch gcc_camss_tfe_1_csid_clk = { 1799*496d1a13SShawn Guo .halt_reg = 0x520cc, 1800*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1801*496d1a13SShawn Guo .clkr = { 1802*496d1a13SShawn Guo .enable_reg = 0x520cc, 1803*496d1a13SShawn Guo .enable_mask = BIT(0), 1804*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1805*496d1a13SShawn Guo .name = "gcc_camss_tfe_1_csid_clk", 1806*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1807*496d1a13SShawn Guo { &gcc_camss_tfe_1_csid_clk_src.clkr.hw }, 1808*496d1a13SShawn Guo .num_parents = 1, 1809*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1810*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1811*496d1a13SShawn Guo }, 1812*496d1a13SShawn Guo }, 1813*496d1a13SShawn Guo }; 1814*496d1a13SShawn Guo 1815*496d1a13SShawn Guo static struct clk_branch gcc_camss_top_ahb_clk = { 1816*496d1a13SShawn Guo .halt_reg = 0x58028, 1817*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1818*496d1a13SShawn Guo .clkr = { 1819*496d1a13SShawn Guo .enable_reg = 0x58028, 1820*496d1a13SShawn Guo .enable_mask = BIT(0), 1821*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1822*496d1a13SShawn Guo .name = "gcc_camss_top_ahb_clk", 1823*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1824*496d1a13SShawn Guo { &gcc_camss_top_ahb_clk_src.clkr.hw }, 1825*496d1a13SShawn Guo .num_parents = 1, 1826*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1827*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1828*496d1a13SShawn Guo }, 1829*496d1a13SShawn Guo }, 1830*496d1a13SShawn Guo }; 1831*496d1a13SShawn Guo 1832*496d1a13SShawn Guo static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1833*496d1a13SShawn Guo .halt_reg = 0x1a084, 1834*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1835*496d1a13SShawn Guo .hwcg_reg = 0x1a084, 1836*496d1a13SShawn Guo .hwcg_bit = 1, 1837*496d1a13SShawn Guo .clkr = { 1838*496d1a13SShawn Guo .enable_reg = 0x1a084, 1839*496d1a13SShawn Guo .enable_mask = BIT(0), 1840*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1841*496d1a13SShawn Guo .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1842*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1843*496d1a13SShawn Guo { &gcc_usb30_prim_master_clk_src.clkr.hw }, 1844*496d1a13SShawn Guo .num_parents = 1, 1845*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1846*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1847*496d1a13SShawn Guo }, 1848*496d1a13SShawn Guo }, 1849*496d1a13SShawn Guo }; 1850*496d1a13SShawn Guo 1851*496d1a13SShawn Guo static struct clk_branch gcc_disp_ahb_clk = { 1852*496d1a13SShawn Guo .halt_reg = 0x1700c, 1853*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1854*496d1a13SShawn Guo .hwcg_reg = 0x1700c, 1855*496d1a13SShawn Guo .hwcg_bit = 1, 1856*496d1a13SShawn Guo .clkr = { 1857*496d1a13SShawn Guo .enable_reg = 0x1700c, 1858*496d1a13SShawn Guo .enable_mask = BIT(0), 1859*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1860*496d1a13SShawn Guo .name = "gcc_disp_ahb_clk", 1861*496d1a13SShawn Guo .flags = CLK_IS_CRITICAL, 1862*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1863*496d1a13SShawn Guo }, 1864*496d1a13SShawn Guo }, 1865*496d1a13SShawn Guo }; 1866*496d1a13SShawn Guo 1867*496d1a13SShawn Guo static struct clk_regmap_div gcc_disp_gpll0_clk_src = { 1868*496d1a13SShawn Guo .reg = 0x17058, 1869*496d1a13SShawn Guo .shift = 0, 1870*496d1a13SShawn Guo .width = 2, 1871*496d1a13SShawn Guo .clkr.hw.init = &(struct clk_init_data) { 1872*496d1a13SShawn Guo .name = "gcc_disp_gpll0_clk_src", 1873*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 1874*496d1a13SShawn Guo .num_parents = 1, 1875*496d1a13SShawn Guo .ops = &clk_regmap_div_ops, 1876*496d1a13SShawn Guo }, 1877*496d1a13SShawn Guo }; 1878*496d1a13SShawn Guo 1879*496d1a13SShawn Guo static struct clk_branch gcc_disp_gpll0_div_clk_src = { 1880*496d1a13SShawn Guo .halt_check = BRANCH_HALT_DELAY, 1881*496d1a13SShawn Guo .clkr = { 1882*496d1a13SShawn Guo .enable_reg = 0x79004, 1883*496d1a13SShawn Guo .enable_mask = BIT(20), 1884*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1885*496d1a13SShawn Guo .name = "gcc_disp_gpll0_div_clk_src", 1886*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1887*496d1a13SShawn Guo { &gcc_disp_gpll0_clk_src.clkr.hw }, 1888*496d1a13SShawn Guo .num_parents = 1, 1889*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1890*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1891*496d1a13SShawn Guo }, 1892*496d1a13SShawn Guo }, 1893*496d1a13SShawn Guo }; 1894*496d1a13SShawn Guo 1895*496d1a13SShawn Guo static struct clk_branch gcc_disp_hf_axi_clk = { 1896*496d1a13SShawn Guo .halt_reg = 0x17020, 1897*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1898*496d1a13SShawn Guo .hwcg_reg = 0x17020, 1899*496d1a13SShawn Guo .hwcg_bit = 1, 1900*496d1a13SShawn Guo .clkr = { 1901*496d1a13SShawn Guo .enable_reg = 0x17020, 1902*496d1a13SShawn Guo .enable_mask = BIT(0), 1903*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1904*496d1a13SShawn Guo .name = "gcc_disp_hf_axi_clk", 1905*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1906*496d1a13SShawn Guo }, 1907*496d1a13SShawn Guo }, 1908*496d1a13SShawn Guo }; 1909*496d1a13SShawn Guo 1910*496d1a13SShawn Guo static struct clk_branch gcc_disp_throttle_core_clk = { 1911*496d1a13SShawn Guo .halt_reg = 0x17064, 1912*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 1913*496d1a13SShawn Guo .hwcg_reg = 0x17064, 1914*496d1a13SShawn Guo .hwcg_bit = 1, 1915*496d1a13SShawn Guo .clkr = { 1916*496d1a13SShawn Guo .enable_reg = 0x7900c, 1917*496d1a13SShawn Guo .enable_mask = BIT(5), 1918*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1919*496d1a13SShawn Guo .name = "gcc_disp_throttle_core_clk", 1920*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1921*496d1a13SShawn Guo }, 1922*496d1a13SShawn Guo }, 1923*496d1a13SShawn Guo }; 1924*496d1a13SShawn Guo 1925*496d1a13SShawn Guo static struct clk_branch gcc_disp_xo_clk = { 1926*496d1a13SShawn Guo .halt_reg = 0x1702c, 1927*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1928*496d1a13SShawn Guo .clkr = { 1929*496d1a13SShawn Guo .enable_reg = 0x1702c, 1930*496d1a13SShawn Guo .enable_mask = BIT(0), 1931*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1932*496d1a13SShawn Guo .name = "gcc_disp_xo_clk", 1933*496d1a13SShawn Guo .flags = CLK_IS_CRITICAL, 1934*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1935*496d1a13SShawn Guo }, 1936*496d1a13SShawn Guo }, 1937*496d1a13SShawn Guo }; 1938*496d1a13SShawn Guo 1939*496d1a13SShawn Guo static struct clk_branch gcc_gp1_clk = { 1940*496d1a13SShawn Guo .halt_reg = 0x4d000, 1941*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1942*496d1a13SShawn Guo .clkr = { 1943*496d1a13SShawn Guo .enable_reg = 0x4d000, 1944*496d1a13SShawn Guo .enable_mask = BIT(0), 1945*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1946*496d1a13SShawn Guo .name = "gcc_gp1_clk", 1947*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1948*496d1a13SShawn Guo { &gcc_gp1_clk_src.clkr.hw }, 1949*496d1a13SShawn Guo .num_parents = 1, 1950*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1951*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1952*496d1a13SShawn Guo }, 1953*496d1a13SShawn Guo }, 1954*496d1a13SShawn Guo }; 1955*496d1a13SShawn Guo 1956*496d1a13SShawn Guo static struct clk_branch gcc_gp2_clk = { 1957*496d1a13SShawn Guo .halt_reg = 0x4e000, 1958*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1959*496d1a13SShawn Guo .clkr = { 1960*496d1a13SShawn Guo .enable_reg = 0x4e000, 1961*496d1a13SShawn Guo .enable_mask = BIT(0), 1962*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1963*496d1a13SShawn Guo .name = "gcc_gp2_clk", 1964*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1965*496d1a13SShawn Guo { &gcc_gp2_clk_src.clkr.hw }, 1966*496d1a13SShawn Guo .num_parents = 1, 1967*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1968*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1969*496d1a13SShawn Guo }, 1970*496d1a13SShawn Guo }, 1971*496d1a13SShawn Guo }; 1972*496d1a13SShawn Guo 1973*496d1a13SShawn Guo static struct clk_branch gcc_gp3_clk = { 1974*496d1a13SShawn Guo .halt_reg = 0x4f000, 1975*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1976*496d1a13SShawn Guo .clkr = { 1977*496d1a13SShawn Guo .enable_reg = 0x4f000, 1978*496d1a13SShawn Guo .enable_mask = BIT(0), 1979*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1980*496d1a13SShawn Guo .name = "gcc_gp3_clk", 1981*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 1982*496d1a13SShawn Guo { &gcc_gp3_clk_src.clkr.hw }, 1983*496d1a13SShawn Guo .num_parents = 1, 1984*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 1985*496d1a13SShawn Guo .ops = &clk_branch2_ops, 1986*496d1a13SShawn Guo }, 1987*496d1a13SShawn Guo }, 1988*496d1a13SShawn Guo }; 1989*496d1a13SShawn Guo 1990*496d1a13SShawn Guo static struct clk_branch gcc_gpu_cfg_ahb_clk = { 1991*496d1a13SShawn Guo .halt_reg = 0x36004, 1992*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 1993*496d1a13SShawn Guo .hwcg_reg = 0x36004, 1994*496d1a13SShawn Guo .hwcg_bit = 1, 1995*496d1a13SShawn Guo .clkr = { 1996*496d1a13SShawn Guo .enable_reg = 0x36004, 1997*496d1a13SShawn Guo .enable_mask = BIT(0), 1998*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 1999*496d1a13SShawn Guo .name = "gcc_gpu_cfg_ahb_clk", 2000*496d1a13SShawn Guo .flags = CLK_IS_CRITICAL, 2001*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2002*496d1a13SShawn Guo }, 2003*496d1a13SShawn Guo }, 2004*496d1a13SShawn Guo }; 2005*496d1a13SShawn Guo 2006*496d1a13SShawn Guo static struct clk_branch gcc_gpu_gpll0_clk_src = { 2007*496d1a13SShawn Guo .halt_check = BRANCH_HALT_DELAY, 2008*496d1a13SShawn Guo .clkr = { 2009*496d1a13SShawn Guo .enable_reg = 0x79004, 2010*496d1a13SShawn Guo .enable_mask = BIT(15), 2011*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2012*496d1a13SShawn Guo .name = "gcc_gpu_gpll0_clk_src", 2013*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2014*496d1a13SShawn Guo { &gpll0.clkr.hw }, 2015*496d1a13SShawn Guo .num_parents = 1, 2016*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2017*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2018*496d1a13SShawn Guo }, 2019*496d1a13SShawn Guo }, 2020*496d1a13SShawn Guo }; 2021*496d1a13SShawn Guo 2022*496d1a13SShawn Guo static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 2023*496d1a13SShawn Guo .halt_check = BRANCH_HALT_DELAY, 2024*496d1a13SShawn Guo .clkr = { 2025*496d1a13SShawn Guo .enable_reg = 0x79004, 2026*496d1a13SShawn Guo .enable_mask = BIT(16), 2027*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2028*496d1a13SShawn Guo .name = "gcc_gpu_gpll0_div_clk_src", 2029*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2030*496d1a13SShawn Guo { &gpll0_out_aux2.clkr.hw }, 2031*496d1a13SShawn Guo .num_parents = 1, 2032*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2033*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2034*496d1a13SShawn Guo }, 2035*496d1a13SShawn Guo }, 2036*496d1a13SShawn Guo }; 2037*496d1a13SShawn Guo 2038*496d1a13SShawn Guo static struct clk_branch gcc_gpu_iref_clk = { 2039*496d1a13SShawn Guo .halt_reg = 0x36100, 2040*496d1a13SShawn Guo .halt_check = BRANCH_HALT_DELAY, 2041*496d1a13SShawn Guo .clkr = { 2042*496d1a13SShawn Guo .enable_reg = 0x36100, 2043*496d1a13SShawn Guo .enable_mask = BIT(0), 2044*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2045*496d1a13SShawn Guo .name = "gcc_gpu_iref_clk", 2046*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2047*496d1a13SShawn Guo }, 2048*496d1a13SShawn Guo }, 2049*496d1a13SShawn Guo }; 2050*496d1a13SShawn Guo 2051*496d1a13SShawn Guo static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 2052*496d1a13SShawn Guo .halt_reg = 0x3600c, 2053*496d1a13SShawn Guo .halt_check = BRANCH_VOTED, 2054*496d1a13SShawn Guo .hwcg_reg = 0x3600c, 2055*496d1a13SShawn Guo .hwcg_bit = 1, 2056*496d1a13SShawn Guo .clkr = { 2057*496d1a13SShawn Guo .enable_reg = 0x3600c, 2058*496d1a13SShawn Guo .enable_mask = BIT(0), 2059*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2060*496d1a13SShawn Guo .name = "gcc_gpu_memnoc_gfx_clk", 2061*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2062*496d1a13SShawn Guo }, 2063*496d1a13SShawn Guo }, 2064*496d1a13SShawn Guo }; 2065*496d1a13SShawn Guo 2066*496d1a13SShawn Guo static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2067*496d1a13SShawn Guo .halt_reg = 0x36018, 2068*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2069*496d1a13SShawn Guo .clkr = { 2070*496d1a13SShawn Guo .enable_reg = 0x36018, 2071*496d1a13SShawn Guo .enable_mask = BIT(0), 2072*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2073*496d1a13SShawn Guo .name = "gcc_gpu_snoc_dvm_gfx_clk", 2074*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2075*496d1a13SShawn Guo }, 2076*496d1a13SShawn Guo }, 2077*496d1a13SShawn Guo }; 2078*496d1a13SShawn Guo 2079*496d1a13SShawn Guo static struct clk_branch gcc_gpu_throttle_core_clk = { 2080*496d1a13SShawn Guo .halt_reg = 0x36048, 2081*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2082*496d1a13SShawn Guo .hwcg_reg = 0x36048, 2083*496d1a13SShawn Guo .hwcg_bit = 1, 2084*496d1a13SShawn Guo .clkr = { 2085*496d1a13SShawn Guo .enable_reg = 0x79004, 2086*496d1a13SShawn Guo .enable_mask = BIT(31), 2087*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2088*496d1a13SShawn Guo .name = "gcc_gpu_throttle_core_clk", 2089*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2090*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2091*496d1a13SShawn Guo }, 2092*496d1a13SShawn Guo }, 2093*496d1a13SShawn Guo }; 2094*496d1a13SShawn Guo 2095*496d1a13SShawn Guo static struct clk_branch gcc_pdm2_clk = { 2096*496d1a13SShawn Guo .halt_reg = 0x2000c, 2097*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2098*496d1a13SShawn Guo .clkr = { 2099*496d1a13SShawn Guo .enable_reg = 0x2000c, 2100*496d1a13SShawn Guo .enable_mask = BIT(0), 2101*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2102*496d1a13SShawn Guo .name = "gcc_pdm2_clk", 2103*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2104*496d1a13SShawn Guo { &gcc_pdm2_clk_src.clkr.hw }, 2105*496d1a13SShawn Guo .num_parents = 1, 2106*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2107*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2108*496d1a13SShawn Guo }, 2109*496d1a13SShawn Guo }, 2110*496d1a13SShawn Guo }; 2111*496d1a13SShawn Guo 2112*496d1a13SShawn Guo static struct clk_branch gcc_pdm_ahb_clk = { 2113*496d1a13SShawn Guo .halt_reg = 0x20004, 2114*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2115*496d1a13SShawn Guo .hwcg_reg = 0x20004, 2116*496d1a13SShawn Guo .hwcg_bit = 1, 2117*496d1a13SShawn Guo .clkr = { 2118*496d1a13SShawn Guo .enable_reg = 0x20004, 2119*496d1a13SShawn Guo .enable_mask = BIT(0), 2120*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2121*496d1a13SShawn Guo .name = "gcc_pdm_ahb_clk", 2122*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2123*496d1a13SShawn Guo }, 2124*496d1a13SShawn Guo }, 2125*496d1a13SShawn Guo }; 2126*496d1a13SShawn Guo 2127*496d1a13SShawn Guo static struct clk_branch gcc_pdm_xo4_clk = { 2128*496d1a13SShawn Guo .halt_reg = 0x20008, 2129*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2130*496d1a13SShawn Guo .clkr = { 2131*496d1a13SShawn Guo .enable_reg = 0x20008, 2132*496d1a13SShawn Guo .enable_mask = BIT(0), 2133*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2134*496d1a13SShawn Guo .name = "gcc_pdm_xo4_clk", 2135*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2136*496d1a13SShawn Guo }, 2137*496d1a13SShawn Guo }, 2138*496d1a13SShawn Guo }; 2139*496d1a13SShawn Guo 2140*496d1a13SShawn Guo static struct clk_branch gcc_pwm0_xo512_clk = { 2141*496d1a13SShawn Guo .halt_reg = 0x2002c, 2142*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2143*496d1a13SShawn Guo .clkr = { 2144*496d1a13SShawn Guo .enable_reg = 0x2002c, 2145*496d1a13SShawn Guo .enable_mask = BIT(0), 2146*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2147*496d1a13SShawn Guo .name = "gcc_pwm0_xo512_clk", 2148*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2149*496d1a13SShawn Guo }, 2150*496d1a13SShawn Guo }, 2151*496d1a13SShawn Guo }; 2152*496d1a13SShawn Guo 2153*496d1a13SShawn Guo static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2154*496d1a13SShawn Guo .halt_reg = 0x17014, 2155*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2156*496d1a13SShawn Guo .hwcg_reg = 0x17014, 2157*496d1a13SShawn Guo .hwcg_bit = 1, 2158*496d1a13SShawn Guo .clkr = { 2159*496d1a13SShawn Guo .enable_reg = 0x7900c, 2160*496d1a13SShawn Guo .enable_mask = BIT(0), 2161*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2162*496d1a13SShawn Guo .name = "gcc_qmip_camera_nrt_ahb_clk", 2163*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2164*496d1a13SShawn Guo }, 2165*496d1a13SShawn Guo }, 2166*496d1a13SShawn Guo }; 2167*496d1a13SShawn Guo 2168*496d1a13SShawn Guo static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2169*496d1a13SShawn Guo .halt_reg = 0x17060, 2170*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2171*496d1a13SShawn Guo .hwcg_reg = 0x17060, 2172*496d1a13SShawn Guo .hwcg_bit = 1, 2173*496d1a13SShawn Guo .clkr = { 2174*496d1a13SShawn Guo .enable_reg = 0x7900c, 2175*496d1a13SShawn Guo .enable_mask = BIT(2), 2176*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2177*496d1a13SShawn Guo .name = "gcc_qmip_camera_rt_ahb_clk", 2178*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2179*496d1a13SShawn Guo }, 2180*496d1a13SShawn Guo }, 2181*496d1a13SShawn Guo }; 2182*496d1a13SShawn Guo 2183*496d1a13SShawn Guo static struct clk_branch gcc_qmip_disp_ahb_clk = { 2184*496d1a13SShawn Guo .halt_reg = 0x17018, 2185*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2186*496d1a13SShawn Guo .hwcg_reg = 0x17018, 2187*496d1a13SShawn Guo .hwcg_bit = 1, 2188*496d1a13SShawn Guo .clkr = { 2189*496d1a13SShawn Guo .enable_reg = 0x7900c, 2190*496d1a13SShawn Guo .enable_mask = BIT(1), 2191*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2192*496d1a13SShawn Guo .name = "gcc_qmip_disp_ahb_clk", 2193*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2194*496d1a13SShawn Guo }, 2195*496d1a13SShawn Guo }, 2196*496d1a13SShawn Guo }; 2197*496d1a13SShawn Guo 2198*496d1a13SShawn Guo static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = { 2199*496d1a13SShawn Guo .halt_reg = 0x36040, 2200*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2201*496d1a13SShawn Guo .hwcg_reg = 0x36040, 2202*496d1a13SShawn Guo .hwcg_bit = 1, 2203*496d1a13SShawn Guo .clkr = { 2204*496d1a13SShawn Guo .enable_reg = 0x7900c, 2205*496d1a13SShawn Guo .enable_mask = BIT(4), 2206*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2207*496d1a13SShawn Guo .name = "gcc_qmip_gpu_cfg_ahb_clk", 2208*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2209*496d1a13SShawn Guo }, 2210*496d1a13SShawn Guo }, 2211*496d1a13SShawn Guo }; 2212*496d1a13SShawn Guo 2213*496d1a13SShawn Guo static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2214*496d1a13SShawn Guo .halt_reg = 0x17010, 2215*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2216*496d1a13SShawn Guo .hwcg_reg = 0x17010, 2217*496d1a13SShawn Guo .hwcg_bit = 1, 2218*496d1a13SShawn Guo .clkr = { 2219*496d1a13SShawn Guo .enable_reg = 0x79004, 2220*496d1a13SShawn Guo .enable_mask = BIT(25), 2221*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2222*496d1a13SShawn Guo .name = "gcc_qmip_video_vcodec_ahb_clk", 2223*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2224*496d1a13SShawn Guo }, 2225*496d1a13SShawn Guo }, 2226*496d1a13SShawn Guo }; 2227*496d1a13SShawn Guo 2228*496d1a13SShawn Guo static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2229*496d1a13SShawn Guo .halt_reg = 0x1f014, 2230*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2231*496d1a13SShawn Guo .clkr = { 2232*496d1a13SShawn Guo .enable_reg = 0x7900c, 2233*496d1a13SShawn Guo .enable_mask = BIT(9), 2234*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2235*496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_core_2x_clk", 2236*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2237*496d1a13SShawn Guo }, 2238*496d1a13SShawn Guo }, 2239*496d1a13SShawn Guo }; 2240*496d1a13SShawn Guo 2241*496d1a13SShawn Guo static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2242*496d1a13SShawn Guo .halt_reg = 0x1f00c, 2243*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2244*496d1a13SShawn Guo .clkr = { 2245*496d1a13SShawn Guo .enable_reg = 0x7900c, 2246*496d1a13SShawn Guo .enable_mask = BIT(8), 2247*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2248*496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_core_clk", 2249*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2250*496d1a13SShawn Guo }, 2251*496d1a13SShawn Guo }, 2252*496d1a13SShawn Guo }; 2253*496d1a13SShawn Guo 2254*496d1a13SShawn Guo static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2255*496d1a13SShawn Guo .halt_reg = 0x1f144, 2256*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2257*496d1a13SShawn Guo .clkr = { 2258*496d1a13SShawn Guo .enable_reg = 0x7900c, 2259*496d1a13SShawn Guo .enable_mask = BIT(10), 2260*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2261*496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s0_clk", 2262*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2263*496d1a13SShawn Guo { &gcc_qupv3_wrap0_s0_clk_src.clkr.hw }, 2264*496d1a13SShawn Guo .num_parents = 1, 2265*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2266*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2267*496d1a13SShawn Guo }, 2268*496d1a13SShawn Guo }, 2269*496d1a13SShawn Guo }; 2270*496d1a13SShawn Guo 2271*496d1a13SShawn Guo static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2272*496d1a13SShawn Guo .halt_reg = 0x1f274, 2273*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2274*496d1a13SShawn Guo .clkr = { 2275*496d1a13SShawn Guo .enable_reg = 0x7900c, 2276*496d1a13SShawn Guo .enable_mask = BIT(11), 2277*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2278*496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s1_clk", 2279*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2280*496d1a13SShawn Guo { &gcc_qupv3_wrap0_s1_clk_src.clkr.hw }, 2281*496d1a13SShawn Guo .num_parents = 1, 2282*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2283*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2284*496d1a13SShawn Guo }, 2285*496d1a13SShawn Guo }, 2286*496d1a13SShawn Guo }; 2287*496d1a13SShawn Guo 2288*496d1a13SShawn Guo static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2289*496d1a13SShawn Guo .halt_reg = 0x1f3a4, 2290*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2291*496d1a13SShawn Guo .clkr = { 2292*496d1a13SShawn Guo .enable_reg = 0x7900c, 2293*496d1a13SShawn Guo .enable_mask = BIT(12), 2294*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2295*496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s2_clk", 2296*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2297*496d1a13SShawn Guo { &gcc_qupv3_wrap0_s2_clk_src.clkr.hw }, 2298*496d1a13SShawn Guo .num_parents = 1, 2299*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2300*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2301*496d1a13SShawn Guo }, 2302*496d1a13SShawn Guo }, 2303*496d1a13SShawn Guo }; 2304*496d1a13SShawn Guo 2305*496d1a13SShawn Guo static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2306*496d1a13SShawn Guo .halt_reg = 0x1f4d4, 2307*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2308*496d1a13SShawn Guo .clkr = { 2309*496d1a13SShawn Guo .enable_reg = 0x7900c, 2310*496d1a13SShawn Guo .enable_mask = BIT(13), 2311*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2312*496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s3_clk", 2313*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2314*496d1a13SShawn Guo { &gcc_qupv3_wrap0_s3_clk_src.clkr.hw }, 2315*496d1a13SShawn Guo .num_parents = 1, 2316*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2317*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2318*496d1a13SShawn Guo }, 2319*496d1a13SShawn Guo }, 2320*496d1a13SShawn Guo }; 2321*496d1a13SShawn Guo 2322*496d1a13SShawn Guo static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2323*496d1a13SShawn Guo .halt_reg = 0x1f604, 2324*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2325*496d1a13SShawn Guo .clkr = { 2326*496d1a13SShawn Guo .enable_reg = 0x7900c, 2327*496d1a13SShawn Guo .enable_mask = BIT(14), 2328*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2329*496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s4_clk", 2330*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2331*496d1a13SShawn Guo { &gcc_qupv3_wrap0_s4_clk_src.clkr.hw }, 2332*496d1a13SShawn Guo .num_parents = 1, 2333*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2334*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2335*496d1a13SShawn Guo }, 2336*496d1a13SShawn Guo }, 2337*496d1a13SShawn Guo }; 2338*496d1a13SShawn Guo 2339*496d1a13SShawn Guo static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2340*496d1a13SShawn Guo .halt_reg = 0x1f734, 2341*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2342*496d1a13SShawn Guo .clkr = { 2343*496d1a13SShawn Guo .enable_reg = 0x7900c, 2344*496d1a13SShawn Guo .enable_mask = BIT(15), 2345*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2346*496d1a13SShawn Guo .name = "gcc_qupv3_wrap0_s5_clk", 2347*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2348*496d1a13SShawn Guo { &gcc_qupv3_wrap0_s5_clk_src.clkr.hw }, 2349*496d1a13SShawn Guo .num_parents = 1, 2350*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2351*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2352*496d1a13SShawn Guo }, 2353*496d1a13SShawn Guo }, 2354*496d1a13SShawn Guo }; 2355*496d1a13SShawn Guo 2356*496d1a13SShawn Guo static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2357*496d1a13SShawn Guo .halt_reg = 0x1f004, 2358*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2359*496d1a13SShawn Guo .hwcg_reg = 0x1f004, 2360*496d1a13SShawn Guo .hwcg_bit = 1, 2361*496d1a13SShawn Guo .clkr = { 2362*496d1a13SShawn Guo .enable_reg = 0x7900c, 2363*496d1a13SShawn Guo .enable_mask = BIT(6), 2364*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2365*496d1a13SShawn Guo .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2366*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2367*496d1a13SShawn Guo }, 2368*496d1a13SShawn Guo }, 2369*496d1a13SShawn Guo }; 2370*496d1a13SShawn Guo 2371*496d1a13SShawn Guo static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2372*496d1a13SShawn Guo .halt_reg = 0x1f008, 2373*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2374*496d1a13SShawn Guo .hwcg_reg = 0x1f008, 2375*496d1a13SShawn Guo .hwcg_bit = 1, 2376*496d1a13SShawn Guo .clkr = { 2377*496d1a13SShawn Guo .enable_reg = 0x7900c, 2378*496d1a13SShawn Guo .enable_mask = BIT(7), 2379*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2380*496d1a13SShawn Guo .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2381*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2382*496d1a13SShawn Guo }, 2383*496d1a13SShawn Guo }, 2384*496d1a13SShawn Guo }; 2385*496d1a13SShawn Guo 2386*496d1a13SShawn Guo static struct clk_branch gcc_sdcc1_ahb_clk = { 2387*496d1a13SShawn Guo .halt_reg = 0x38008, 2388*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2389*496d1a13SShawn Guo .clkr = { 2390*496d1a13SShawn Guo .enable_reg = 0x38008, 2391*496d1a13SShawn Guo .enable_mask = BIT(0), 2392*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2393*496d1a13SShawn Guo .name = "gcc_sdcc1_ahb_clk", 2394*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2395*496d1a13SShawn Guo }, 2396*496d1a13SShawn Guo }, 2397*496d1a13SShawn Guo }; 2398*496d1a13SShawn Guo 2399*496d1a13SShawn Guo static struct clk_branch gcc_sdcc1_apps_clk = { 2400*496d1a13SShawn Guo .halt_reg = 0x38004, 2401*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2402*496d1a13SShawn Guo .clkr = { 2403*496d1a13SShawn Guo .enable_reg = 0x38004, 2404*496d1a13SShawn Guo .enable_mask = BIT(0), 2405*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2406*496d1a13SShawn Guo .name = "gcc_sdcc1_apps_clk", 2407*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2408*496d1a13SShawn Guo { &gcc_sdcc1_apps_clk_src.clkr.hw }, 2409*496d1a13SShawn Guo .num_parents = 1, 2410*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2411*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2412*496d1a13SShawn Guo }, 2413*496d1a13SShawn Guo }, 2414*496d1a13SShawn Guo }; 2415*496d1a13SShawn Guo 2416*496d1a13SShawn Guo static struct clk_branch gcc_sdcc1_ice_core_clk = { 2417*496d1a13SShawn Guo .halt_reg = 0x3800c, 2418*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2419*496d1a13SShawn Guo .hwcg_reg = 0x3800c, 2420*496d1a13SShawn Guo .hwcg_bit = 1, 2421*496d1a13SShawn Guo .clkr = { 2422*496d1a13SShawn Guo .enable_reg = 0x3800c, 2423*496d1a13SShawn Guo .enable_mask = BIT(0), 2424*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2425*496d1a13SShawn Guo .name = "gcc_sdcc1_ice_core_clk", 2426*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2427*496d1a13SShawn Guo { &gcc_sdcc1_ice_core_clk_src.clkr.hw }, 2428*496d1a13SShawn Guo .num_parents = 1, 2429*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2430*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2431*496d1a13SShawn Guo }, 2432*496d1a13SShawn Guo }, 2433*496d1a13SShawn Guo }; 2434*496d1a13SShawn Guo 2435*496d1a13SShawn Guo static struct clk_branch gcc_sdcc2_ahb_clk = { 2436*496d1a13SShawn Guo .halt_reg = 0x1e008, 2437*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2438*496d1a13SShawn Guo .clkr = { 2439*496d1a13SShawn Guo .enable_reg = 0x1e008, 2440*496d1a13SShawn Guo .enable_mask = BIT(0), 2441*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2442*496d1a13SShawn Guo .name = "gcc_sdcc2_ahb_clk", 2443*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2444*496d1a13SShawn Guo }, 2445*496d1a13SShawn Guo }, 2446*496d1a13SShawn Guo }; 2447*496d1a13SShawn Guo 2448*496d1a13SShawn Guo static struct clk_branch gcc_sdcc2_apps_clk = { 2449*496d1a13SShawn Guo .halt_reg = 0x1e004, 2450*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2451*496d1a13SShawn Guo .clkr = { 2452*496d1a13SShawn Guo .enable_reg = 0x1e004, 2453*496d1a13SShawn Guo .enable_mask = BIT(0), 2454*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2455*496d1a13SShawn Guo .name = "gcc_sdcc2_apps_clk", 2456*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2457*496d1a13SShawn Guo { &gcc_sdcc2_apps_clk_src.clkr.hw }, 2458*496d1a13SShawn Guo .num_parents = 1, 2459*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2460*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2461*496d1a13SShawn Guo }, 2462*496d1a13SShawn Guo }, 2463*496d1a13SShawn Guo }; 2464*496d1a13SShawn Guo 2465*496d1a13SShawn Guo static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 2466*496d1a13SShawn Guo .halt_reg = 0x2b06c, 2467*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2468*496d1a13SShawn Guo .hwcg_reg = 0x2b06c, 2469*496d1a13SShawn Guo .hwcg_bit = 1, 2470*496d1a13SShawn Guo .clkr = { 2471*496d1a13SShawn Guo .enable_reg = 0x79004, 2472*496d1a13SShawn Guo .enable_mask = BIT(0), 2473*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2474*496d1a13SShawn Guo .name = "gcc_sys_noc_cpuss_ahb_clk", 2475*496d1a13SShawn Guo .flags = CLK_IS_CRITICAL, 2476*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2477*496d1a13SShawn Guo }, 2478*496d1a13SShawn Guo }, 2479*496d1a13SShawn Guo }; 2480*496d1a13SShawn Guo 2481*496d1a13SShawn Guo static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { 2482*496d1a13SShawn Guo .halt_reg = 0x1a080, 2483*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2484*496d1a13SShawn Guo .hwcg_reg = 0x1a080, 2485*496d1a13SShawn Guo .hwcg_bit = 1, 2486*496d1a13SShawn Guo .clkr = { 2487*496d1a13SShawn Guo .enable_reg = 0x1a080, 2488*496d1a13SShawn Guo .enable_mask = BIT(0), 2489*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2490*496d1a13SShawn Guo .name = "gcc_sys_noc_usb3_prim_axi_clk", 2491*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2492*496d1a13SShawn Guo { &gcc_usb30_prim_master_clk_src.clkr.hw }, 2493*496d1a13SShawn Guo .num_parents = 1, 2494*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2495*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2496*496d1a13SShawn Guo }, 2497*496d1a13SShawn Guo }, 2498*496d1a13SShawn Guo }; 2499*496d1a13SShawn Guo 2500*496d1a13SShawn Guo static struct clk_branch gcc_usb30_prim_master_clk = { 2501*496d1a13SShawn Guo .halt_reg = 0x1a010, 2502*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2503*496d1a13SShawn Guo .clkr = { 2504*496d1a13SShawn Guo .enable_reg = 0x1a010, 2505*496d1a13SShawn Guo .enable_mask = BIT(0), 2506*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2507*496d1a13SShawn Guo .name = "gcc_usb30_prim_master_clk", 2508*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2509*496d1a13SShawn Guo { &gcc_usb30_prim_master_clk_src.clkr.hw }, 2510*496d1a13SShawn Guo .num_parents = 1, 2511*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2512*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2513*496d1a13SShawn Guo }, 2514*496d1a13SShawn Guo }, 2515*496d1a13SShawn Guo }; 2516*496d1a13SShawn Guo 2517*496d1a13SShawn Guo static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2518*496d1a13SShawn Guo .halt_reg = 0x1a018, 2519*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2520*496d1a13SShawn Guo .clkr = { 2521*496d1a13SShawn Guo .enable_reg = 0x1a018, 2522*496d1a13SShawn Guo .enable_mask = BIT(0), 2523*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2524*496d1a13SShawn Guo .name = "gcc_usb30_prim_mock_utmi_clk", 2525*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2526*496d1a13SShawn Guo { &gcc_usb30_prim_mock_utmi_postdiv.clkr.hw }, 2527*496d1a13SShawn Guo .num_parents = 1, 2528*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2529*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2530*496d1a13SShawn Guo }, 2531*496d1a13SShawn Guo }, 2532*496d1a13SShawn Guo }; 2533*496d1a13SShawn Guo 2534*496d1a13SShawn Guo static struct clk_branch gcc_usb30_prim_sleep_clk = { 2535*496d1a13SShawn Guo .halt_reg = 0x1a014, 2536*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2537*496d1a13SShawn Guo .clkr = { 2538*496d1a13SShawn Guo .enable_reg = 0x1a014, 2539*496d1a13SShawn Guo .enable_mask = BIT(0), 2540*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2541*496d1a13SShawn Guo .name = "gcc_usb30_prim_sleep_clk", 2542*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2543*496d1a13SShawn Guo }, 2544*496d1a13SShawn Guo }, 2545*496d1a13SShawn Guo }; 2546*496d1a13SShawn Guo 2547*496d1a13SShawn Guo static struct clk_branch gcc_usb3_prim_clkref_clk = { 2548*496d1a13SShawn Guo .halt_reg = 0x9f000, 2549*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2550*496d1a13SShawn Guo .clkr = { 2551*496d1a13SShawn Guo .enable_reg = 0x9f000, 2552*496d1a13SShawn Guo .enable_mask = BIT(0), 2553*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2554*496d1a13SShawn Guo .name = "gcc_usb3_prim_clkref_clk", 2555*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2556*496d1a13SShawn Guo }, 2557*496d1a13SShawn Guo }, 2558*496d1a13SShawn Guo }; 2559*496d1a13SShawn Guo 2560*496d1a13SShawn Guo static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2561*496d1a13SShawn Guo .halt_reg = 0x1a054, 2562*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2563*496d1a13SShawn Guo .clkr = { 2564*496d1a13SShawn Guo .enable_reg = 0x1a054, 2565*496d1a13SShawn Guo .enable_mask = BIT(0), 2566*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2567*496d1a13SShawn Guo .name = "gcc_usb3_prim_phy_com_aux_clk", 2568*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2569*496d1a13SShawn Guo { &gcc_usb3_prim_phy_aux_clk_src.clkr.hw }, 2570*496d1a13SShawn Guo .num_parents = 1, 2571*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2572*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2573*496d1a13SShawn Guo }, 2574*496d1a13SShawn Guo }, 2575*496d1a13SShawn Guo }; 2576*496d1a13SShawn Guo 2577*496d1a13SShawn Guo static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2578*496d1a13SShawn Guo .halt_reg = 0x1a058, 2579*496d1a13SShawn Guo .halt_check = BRANCH_HALT_SKIP, 2580*496d1a13SShawn Guo .hwcg_reg = 0x1a058, 2581*496d1a13SShawn Guo .hwcg_bit = 1, 2582*496d1a13SShawn Guo .clkr = { 2583*496d1a13SShawn Guo .enable_reg = 0x1a058, 2584*496d1a13SShawn Guo .enable_mask = BIT(0), 2585*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2586*496d1a13SShawn Guo .name = "gcc_usb3_prim_phy_pipe_clk", 2587*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2588*496d1a13SShawn Guo }, 2589*496d1a13SShawn Guo }, 2590*496d1a13SShawn Guo }; 2591*496d1a13SShawn Guo 2592*496d1a13SShawn Guo static struct clk_branch gcc_vcodec0_axi_clk = { 2593*496d1a13SShawn Guo .halt_reg = 0x6e008, 2594*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2595*496d1a13SShawn Guo .clkr = { 2596*496d1a13SShawn Guo .enable_reg = 0x6e008, 2597*496d1a13SShawn Guo .enable_mask = BIT(0), 2598*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2599*496d1a13SShawn Guo .name = "gcc_vcodec0_axi_clk", 2600*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2601*496d1a13SShawn Guo }, 2602*496d1a13SShawn Guo }, 2603*496d1a13SShawn Guo }; 2604*496d1a13SShawn Guo 2605*496d1a13SShawn Guo static struct clk_branch gcc_venus_ahb_clk = { 2606*496d1a13SShawn Guo .halt_reg = 0x6e010, 2607*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2608*496d1a13SShawn Guo .clkr = { 2609*496d1a13SShawn Guo .enable_reg = 0x6e010, 2610*496d1a13SShawn Guo .enable_mask = BIT(0), 2611*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2612*496d1a13SShawn Guo .name = "gcc_venus_ahb_clk", 2613*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2614*496d1a13SShawn Guo }, 2615*496d1a13SShawn Guo }, 2616*496d1a13SShawn Guo }; 2617*496d1a13SShawn Guo 2618*496d1a13SShawn Guo static struct clk_branch gcc_venus_ctl_axi_clk = { 2619*496d1a13SShawn Guo .halt_reg = 0x6e004, 2620*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2621*496d1a13SShawn Guo .clkr = { 2622*496d1a13SShawn Guo .enable_reg = 0x6e004, 2623*496d1a13SShawn Guo .enable_mask = BIT(0), 2624*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2625*496d1a13SShawn Guo .name = "gcc_venus_ctl_axi_clk", 2626*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2627*496d1a13SShawn Guo }, 2628*496d1a13SShawn Guo }, 2629*496d1a13SShawn Guo }; 2630*496d1a13SShawn Guo 2631*496d1a13SShawn Guo static struct clk_branch gcc_video_ahb_clk = { 2632*496d1a13SShawn Guo .halt_reg = 0x17004, 2633*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2634*496d1a13SShawn Guo .hwcg_reg = 0x17004, 2635*496d1a13SShawn Guo .hwcg_bit = 1, 2636*496d1a13SShawn Guo .clkr = { 2637*496d1a13SShawn Guo .enable_reg = 0x17004, 2638*496d1a13SShawn Guo .enable_mask = BIT(0), 2639*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2640*496d1a13SShawn Guo .name = "gcc_video_ahb_clk", 2641*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2642*496d1a13SShawn Guo }, 2643*496d1a13SShawn Guo }, 2644*496d1a13SShawn Guo }; 2645*496d1a13SShawn Guo 2646*496d1a13SShawn Guo static struct clk_branch gcc_video_axi0_clk = { 2647*496d1a13SShawn Guo .halt_reg = 0x1701c, 2648*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2649*496d1a13SShawn Guo .hwcg_reg = 0x1701c, 2650*496d1a13SShawn Guo .hwcg_bit = 1, 2651*496d1a13SShawn Guo .clkr = { 2652*496d1a13SShawn Guo .enable_reg = 0x1701c, 2653*496d1a13SShawn Guo .enable_mask = BIT(0), 2654*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2655*496d1a13SShawn Guo .name = "gcc_video_axi0_clk", 2656*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2657*496d1a13SShawn Guo }, 2658*496d1a13SShawn Guo }, 2659*496d1a13SShawn Guo }; 2660*496d1a13SShawn Guo 2661*496d1a13SShawn Guo static struct clk_branch gcc_video_throttle_core_clk = { 2662*496d1a13SShawn Guo .halt_reg = 0x17068, 2663*496d1a13SShawn Guo .halt_check = BRANCH_HALT_VOTED, 2664*496d1a13SShawn Guo .hwcg_reg = 0x17068, 2665*496d1a13SShawn Guo .hwcg_bit = 1, 2666*496d1a13SShawn Guo .clkr = { 2667*496d1a13SShawn Guo .enable_reg = 0x79004, 2668*496d1a13SShawn Guo .enable_mask = BIT(28), 2669*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2670*496d1a13SShawn Guo .name = "gcc_video_throttle_core_clk", 2671*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2672*496d1a13SShawn Guo }, 2673*496d1a13SShawn Guo }, 2674*496d1a13SShawn Guo }; 2675*496d1a13SShawn Guo 2676*496d1a13SShawn Guo static struct clk_branch gcc_video_vcodec0_sys_clk = { 2677*496d1a13SShawn Guo .halt_reg = 0x580a4, 2678*496d1a13SShawn Guo .halt_check = BRANCH_HALT_DELAY, 2679*496d1a13SShawn Guo .hwcg_reg = 0x580a4, 2680*496d1a13SShawn Guo .hwcg_bit = 1, 2681*496d1a13SShawn Guo .clkr = { 2682*496d1a13SShawn Guo .enable_reg = 0x580a4, 2683*496d1a13SShawn Guo .enable_mask = BIT(0), 2684*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2685*496d1a13SShawn Guo .name = "gcc_video_vcodec0_sys_clk", 2686*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2687*496d1a13SShawn Guo { &gcc_video_venus_clk_src.clkr.hw }, 2688*496d1a13SShawn Guo .num_parents = 1, 2689*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2690*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2691*496d1a13SShawn Guo }, 2692*496d1a13SShawn Guo }, 2693*496d1a13SShawn Guo }; 2694*496d1a13SShawn Guo 2695*496d1a13SShawn Guo static struct clk_branch gcc_video_venus_ctl_clk = { 2696*496d1a13SShawn Guo .halt_reg = 0x5808c, 2697*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2698*496d1a13SShawn Guo .clkr = { 2699*496d1a13SShawn Guo .enable_reg = 0x5808c, 2700*496d1a13SShawn Guo .enable_mask = BIT(0), 2701*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2702*496d1a13SShawn Guo .name = "gcc_video_venus_ctl_clk", 2703*496d1a13SShawn Guo .parent_hws = (const struct clk_hw *[]) 2704*496d1a13SShawn Guo { &gcc_video_venus_clk_src.clkr.hw }, 2705*496d1a13SShawn Guo .num_parents = 1, 2706*496d1a13SShawn Guo .flags = CLK_SET_RATE_PARENT, 2707*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2708*496d1a13SShawn Guo }, 2709*496d1a13SShawn Guo }, 2710*496d1a13SShawn Guo }; 2711*496d1a13SShawn Guo 2712*496d1a13SShawn Guo static struct clk_branch gcc_video_xo_clk = { 2713*496d1a13SShawn Guo .halt_reg = 0x17024, 2714*496d1a13SShawn Guo .halt_check = BRANCH_HALT, 2715*496d1a13SShawn Guo .clkr = { 2716*496d1a13SShawn Guo .enable_reg = 0x17024, 2717*496d1a13SShawn Guo .enable_mask = BIT(0), 2718*496d1a13SShawn Guo .hw.init = &(struct clk_init_data){ 2719*496d1a13SShawn Guo .name = "gcc_video_xo_clk", 2720*496d1a13SShawn Guo .ops = &clk_branch2_ops, 2721*496d1a13SShawn Guo }, 2722*496d1a13SShawn Guo }, 2723*496d1a13SShawn Guo }; 2724*496d1a13SShawn Guo 2725*496d1a13SShawn Guo static struct gdsc gcc_camss_top_gdsc = { 2726*496d1a13SShawn Guo .gdscr = 0x58004, 2727*496d1a13SShawn Guo .pd = { 2728*496d1a13SShawn Guo .name = "gcc_camss_top", 2729*496d1a13SShawn Guo }, 2730*496d1a13SShawn Guo .pwrsts = PWRSTS_OFF_ON, 2731*496d1a13SShawn Guo }; 2732*496d1a13SShawn Guo 2733*496d1a13SShawn Guo static struct gdsc gcc_usb30_prim_gdsc = { 2734*496d1a13SShawn Guo .gdscr = 0x1a004, 2735*496d1a13SShawn Guo .pd = { 2736*496d1a13SShawn Guo .name = "gcc_usb30_prim", 2737*496d1a13SShawn Guo }, 2738*496d1a13SShawn Guo .pwrsts = PWRSTS_OFF_ON, 2739*496d1a13SShawn Guo }; 2740*496d1a13SShawn Guo 2741*496d1a13SShawn Guo static struct gdsc gcc_vcodec0_gdsc = { 2742*496d1a13SShawn Guo .gdscr = 0x58098, 2743*496d1a13SShawn Guo .pd = { 2744*496d1a13SShawn Guo .name = "gcc_vcodec0", 2745*496d1a13SShawn Guo }, 2746*496d1a13SShawn Guo .pwrsts = PWRSTS_OFF_ON, 2747*496d1a13SShawn Guo }; 2748*496d1a13SShawn Guo 2749*496d1a13SShawn Guo static struct gdsc gcc_venus_gdsc = { 2750*496d1a13SShawn Guo .gdscr = 0x5807c, 2751*496d1a13SShawn Guo .pd = { 2752*496d1a13SShawn Guo .name = "gcc_venus", 2753*496d1a13SShawn Guo }, 2754*496d1a13SShawn Guo .pwrsts = PWRSTS_OFF_ON, 2755*496d1a13SShawn Guo }; 2756*496d1a13SShawn Guo 2757*496d1a13SShawn Guo static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = { 2758*496d1a13SShawn Guo .gdscr = 0x7d060, 2759*496d1a13SShawn Guo .pd = { 2760*496d1a13SShawn Guo .name = "hlos1_vote_turing_mmu_tbu1", 2761*496d1a13SShawn Guo }, 2762*496d1a13SShawn Guo .pwrsts = PWRSTS_OFF_ON, 2763*496d1a13SShawn Guo .flags = VOTABLE, 2764*496d1a13SShawn Guo }; 2765*496d1a13SShawn Guo 2766*496d1a13SShawn Guo static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { 2767*496d1a13SShawn Guo .gdscr = 0x7d07c, 2768*496d1a13SShawn Guo .pd = { 2769*496d1a13SShawn Guo .name = "hlos1_vote_turing_mmu_tbu0", 2770*496d1a13SShawn Guo }, 2771*496d1a13SShawn Guo .pwrsts = PWRSTS_OFF_ON, 2772*496d1a13SShawn Guo .flags = VOTABLE, 2773*496d1a13SShawn Guo }; 2774*496d1a13SShawn Guo 2775*496d1a13SShawn Guo static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = { 2776*496d1a13SShawn Guo .gdscr = 0x7d074, 2777*496d1a13SShawn Guo .pd = { 2778*496d1a13SShawn Guo .name = "hlos1_vote_mm_snoc_mmu_tbu_rt", 2779*496d1a13SShawn Guo }, 2780*496d1a13SShawn Guo .pwrsts = PWRSTS_OFF_ON, 2781*496d1a13SShawn Guo .flags = VOTABLE, 2782*496d1a13SShawn Guo }; 2783*496d1a13SShawn Guo 2784*496d1a13SShawn Guo static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = { 2785*496d1a13SShawn Guo .gdscr = 0x7d078, 2786*496d1a13SShawn Guo .pd = { 2787*496d1a13SShawn Guo .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt", 2788*496d1a13SShawn Guo }, 2789*496d1a13SShawn Guo .pwrsts = PWRSTS_OFF_ON, 2790*496d1a13SShawn Guo .flags = VOTABLE, 2791*496d1a13SShawn Guo }; 2792*496d1a13SShawn Guo 2793*496d1a13SShawn Guo static struct clk_regmap *gcc_qcm2290_clocks[] = { 2794*496d1a13SShawn Guo [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr, 2795*496d1a13SShawn Guo [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr, 2796*496d1a13SShawn Guo [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr, 2797*496d1a13SShawn Guo [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2798*496d1a13SShawn Guo [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, 2799*496d1a13SShawn Guo [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, 2800*496d1a13SShawn Guo [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 2801*496d1a13SShawn Guo [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 2802*496d1a13SShawn Guo [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, 2803*496d1a13SShawn Guo [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, 2804*496d1a13SShawn Guo [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr, 2805*496d1a13SShawn Guo [GCC_CAMSS_CAMNOC_NTS_XO_CLK] = &gcc_camss_camnoc_nts_xo_clk.clkr, 2806*496d1a13SShawn Guo [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr, 2807*496d1a13SShawn Guo [GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr, 2808*496d1a13SShawn Guo [GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr, 2809*496d1a13SShawn Guo [GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr, 2810*496d1a13SShawn Guo [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 2811*496d1a13SShawn Guo [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr, 2812*496d1a13SShawn Guo [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, 2813*496d1a13SShawn Guo [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr, 2814*496d1a13SShawn Guo [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 2815*496d1a13SShawn Guo [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr, 2816*496d1a13SShawn Guo [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 2817*496d1a13SShawn Guo [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr, 2818*496d1a13SShawn Guo [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, 2819*496d1a13SShawn Guo [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr, 2820*496d1a13SShawn Guo [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr, 2821*496d1a13SShawn Guo [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr, 2822*496d1a13SShawn Guo [GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr, 2823*496d1a13SShawn Guo [GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr, 2824*496d1a13SShawn Guo [GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr, 2825*496d1a13SShawn Guo [GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr, 2826*496d1a13SShawn Guo [GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr, 2827*496d1a13SShawn Guo [GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr, 2828*496d1a13SShawn Guo [GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr, 2829*496d1a13SShawn Guo [GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr, 2830*496d1a13SShawn Guo [GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr, 2831*496d1a13SShawn Guo [GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr, 2832*496d1a13SShawn Guo [GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr, 2833*496d1a13SShawn Guo [GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr, 2834*496d1a13SShawn Guo [GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr, 2835*496d1a13SShawn Guo [GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr, 2836*496d1a13SShawn Guo [GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr, 2837*496d1a13SShawn Guo [GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr, 2838*496d1a13SShawn Guo [GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr, 2839*496d1a13SShawn Guo [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 2840*496d1a13SShawn Guo [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, 2841*496d1a13SShawn Guo [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2842*496d1a13SShawn Guo [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, 2843*496d1a13SShawn Guo [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 2844*496d1a13SShawn Guo [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 2845*496d1a13SShawn Guo [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 2846*496d1a13SShawn Guo [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, 2847*496d1a13SShawn Guo [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 2848*496d1a13SShawn Guo [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2849*496d1a13SShawn Guo [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2850*496d1a13SShawn Guo [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2851*496d1a13SShawn Guo [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2852*496d1a13SShawn Guo [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2853*496d1a13SShawn Guo [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2854*496d1a13SShawn Guo [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 2855*496d1a13SShawn Guo [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 2856*496d1a13SShawn Guo [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 2857*496d1a13SShawn Guo [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, 2858*496d1a13SShawn Guo [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 2859*496d1a13SShawn Guo [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 2860*496d1a13SShawn Guo [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, 2861*496d1a13SShawn Guo [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2862*496d1a13SShawn Guo [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 2863*496d1a13SShawn Guo [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2864*496d1a13SShawn Guo [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2865*496d1a13SShawn Guo [GCC_PWM0_XO512_CLK] = &gcc_pwm0_xo512_clk.clkr, 2866*496d1a13SShawn Guo [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 2867*496d1a13SShawn Guo [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 2868*496d1a13SShawn Guo [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 2869*496d1a13SShawn Guo [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr, 2870*496d1a13SShawn Guo [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 2871*496d1a13SShawn Guo [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 2872*496d1a13SShawn Guo [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 2873*496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 2874*496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 2875*496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 2876*496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 2877*496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 2878*496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 2879*496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 2880*496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 2881*496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 2882*496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 2883*496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 2884*496d1a13SShawn Guo [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 2885*496d1a13SShawn Guo [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 2886*496d1a13SShawn Guo [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 2887*496d1a13SShawn Guo [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2888*496d1a13SShawn Guo [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2889*496d1a13SShawn Guo [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 2890*496d1a13SShawn Guo [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 2891*496d1a13SShawn Guo [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 2892*496d1a13SShawn Guo [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2893*496d1a13SShawn Guo [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2894*496d1a13SShawn Guo [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 2895*496d1a13SShawn Guo [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 2896*496d1a13SShawn Guo [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, 2897*496d1a13SShawn Guo [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 2898*496d1a13SShawn Guo [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 2899*496d1a13SShawn Guo [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 2900*496d1a13SShawn Guo [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 2901*496d1a13SShawn Guo &gcc_usb30_prim_mock_utmi_clk_src.clkr, 2902*496d1a13SShawn Guo [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV] = 2903*496d1a13SShawn Guo &gcc_usb30_prim_mock_utmi_postdiv.clkr, 2904*496d1a13SShawn Guo [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 2905*496d1a13SShawn Guo [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 2906*496d1a13SShawn Guo [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 2907*496d1a13SShawn Guo [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 2908*496d1a13SShawn Guo [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 2909*496d1a13SShawn Guo [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr, 2910*496d1a13SShawn Guo [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr, 2911*496d1a13SShawn Guo [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr, 2912*496d1a13SShawn Guo [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 2913*496d1a13SShawn Guo [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 2914*496d1a13SShawn Guo [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, 2915*496d1a13SShawn Guo [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr, 2916*496d1a13SShawn Guo [GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr, 2917*496d1a13SShawn Guo [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr, 2918*496d1a13SShawn Guo [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 2919*496d1a13SShawn Guo [GPLL0] = &gpll0.clkr, 2920*496d1a13SShawn Guo [GPLL0_OUT_AUX2] = &gpll0_out_aux2.clkr, 2921*496d1a13SShawn Guo [GPLL1] = &gpll1.clkr, 2922*496d1a13SShawn Guo [GPLL10] = &gpll10.clkr, 2923*496d1a13SShawn Guo [GPLL11] = &gpll11.clkr, 2924*496d1a13SShawn Guo [GPLL3] = &gpll3.clkr, 2925*496d1a13SShawn Guo [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr, 2926*496d1a13SShawn Guo [GPLL4] = &gpll4.clkr, 2927*496d1a13SShawn Guo [GPLL5] = &gpll5.clkr, 2928*496d1a13SShawn Guo [GPLL6] = &gpll6.clkr, 2929*496d1a13SShawn Guo [GPLL6_OUT_MAIN] = &gpll6_out_main.clkr, 2930*496d1a13SShawn Guo [GPLL7] = &gpll7.clkr, 2931*496d1a13SShawn Guo [GPLL8] = &gpll8.clkr, 2932*496d1a13SShawn Guo [GPLL8_OUT_MAIN] = &gpll8_out_main.clkr, 2933*496d1a13SShawn Guo [GPLL9] = &gpll9.clkr, 2934*496d1a13SShawn Guo [GPLL9_OUT_MAIN] = &gpll9_out_main.clkr, 2935*496d1a13SShawn Guo }; 2936*496d1a13SShawn Guo 2937*496d1a13SShawn Guo static const struct qcom_reset_map gcc_qcm2290_resets[] = { 2938*496d1a13SShawn Guo [GCC_CAMSS_OPE_BCR] = { 0x55000 }, 2939*496d1a13SShawn Guo [GCC_CAMSS_TFE_BCR] = { 0x52000 }, 2940*496d1a13SShawn Guo [GCC_CAMSS_TOP_BCR] = { 0x58000 }, 2941*496d1a13SShawn Guo [GCC_GPU_BCR] = { 0x36000 }, 2942*496d1a13SShawn Guo [GCC_MMSS_BCR] = { 0x17000 }, 2943*496d1a13SShawn Guo [GCC_PDM_BCR] = { 0x20000 }, 2944*496d1a13SShawn Guo [GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 }, 2945*496d1a13SShawn Guo [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, 2946*496d1a13SShawn Guo [GCC_SDCC1_BCR] = { 0x38000 }, 2947*496d1a13SShawn Guo [GCC_SDCC2_BCR] = { 0x1e000 }, 2948*496d1a13SShawn Guo [GCC_USB30_PRIM_BCR] = { 0x1a000 }, 2949*496d1a13SShawn Guo [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, 2950*496d1a13SShawn Guo [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, 2951*496d1a13SShawn Guo [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, 2952*496d1a13SShawn Guo [GCC_VCODEC0_BCR] = { 0x58094 }, 2953*496d1a13SShawn Guo [GCC_VENUS_BCR] = { 0x58078 }, 2954*496d1a13SShawn Guo [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 }, 2955*496d1a13SShawn Guo }; 2956*496d1a13SShawn Guo 2957*496d1a13SShawn Guo static struct gdsc *gcc_qcm2290_gdscs[] = { 2958*496d1a13SShawn Guo [GCC_CAMSS_TOP_GDSC] = &gcc_camss_top_gdsc, 2959*496d1a13SShawn Guo [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 2960*496d1a13SShawn Guo [GCC_VCODEC0_GDSC] = &gcc_vcodec0_gdsc, 2961*496d1a13SShawn Guo [GCC_VENUS_GDSC] = &gcc_venus_gdsc, 2962*496d1a13SShawn Guo [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, 2963*496d1a13SShawn Guo [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc, 2964*496d1a13SShawn Guo [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc, 2965*496d1a13SShawn Guo [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc, 2966*496d1a13SShawn Guo }; 2967*496d1a13SShawn Guo 2968*496d1a13SShawn Guo static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 2969*496d1a13SShawn Guo DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 2970*496d1a13SShawn Guo DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 2971*496d1a13SShawn Guo DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 2972*496d1a13SShawn Guo DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 2973*496d1a13SShawn Guo DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 2974*496d1a13SShawn Guo DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 2975*496d1a13SShawn Guo }; 2976*496d1a13SShawn Guo 2977*496d1a13SShawn Guo static const struct regmap_config gcc_qcm2290_regmap_config = { 2978*496d1a13SShawn Guo .reg_bits = 32, 2979*496d1a13SShawn Guo .reg_stride = 4, 2980*496d1a13SShawn Guo .val_bits = 32, 2981*496d1a13SShawn Guo .max_register = 0xc7000, 2982*496d1a13SShawn Guo .fast_io = true, 2983*496d1a13SShawn Guo }; 2984*496d1a13SShawn Guo 2985*496d1a13SShawn Guo static const struct qcom_cc_desc gcc_qcm2290_desc = { 2986*496d1a13SShawn Guo .config = &gcc_qcm2290_regmap_config, 2987*496d1a13SShawn Guo .clks = gcc_qcm2290_clocks, 2988*496d1a13SShawn Guo .num_clks = ARRAY_SIZE(gcc_qcm2290_clocks), 2989*496d1a13SShawn Guo .resets = gcc_qcm2290_resets, 2990*496d1a13SShawn Guo .num_resets = ARRAY_SIZE(gcc_qcm2290_resets), 2991*496d1a13SShawn Guo .gdscs = gcc_qcm2290_gdscs, 2992*496d1a13SShawn Guo .num_gdscs = ARRAY_SIZE(gcc_qcm2290_gdscs), 2993*496d1a13SShawn Guo }; 2994*496d1a13SShawn Guo 2995*496d1a13SShawn Guo static const struct of_device_id gcc_qcm2290_match_table[] = { 2996*496d1a13SShawn Guo { .compatible = "qcom,gcc-qcm2290" }, 2997*496d1a13SShawn Guo { } 2998*496d1a13SShawn Guo }; 2999*496d1a13SShawn Guo MODULE_DEVICE_TABLE(of, gcc_qcm2290_match_table); 3000*496d1a13SShawn Guo 3001*496d1a13SShawn Guo static int gcc_qcm2290_probe(struct platform_device *pdev) 3002*496d1a13SShawn Guo { 3003*496d1a13SShawn Guo struct regmap *regmap; 3004*496d1a13SShawn Guo int ret; 3005*496d1a13SShawn Guo 3006*496d1a13SShawn Guo regmap = qcom_cc_map(pdev, &gcc_qcm2290_desc); 3007*496d1a13SShawn Guo if (IS_ERR(regmap)) 3008*496d1a13SShawn Guo return PTR_ERR(regmap); 3009*496d1a13SShawn Guo 3010*496d1a13SShawn Guo ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3011*496d1a13SShawn Guo ARRAY_SIZE(gcc_dfs_clocks)); 3012*496d1a13SShawn Guo if (ret) 3013*496d1a13SShawn Guo return ret; 3014*496d1a13SShawn Guo 3015*496d1a13SShawn Guo clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config); 3016*496d1a13SShawn Guo clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config); 3017*496d1a13SShawn Guo clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config); 3018*496d1a13SShawn Guo clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config); 3019*496d1a13SShawn Guo 3020*496d1a13SShawn Guo return qcom_cc_really_probe(pdev, &gcc_qcm2290_desc, regmap); 3021*496d1a13SShawn Guo } 3022*496d1a13SShawn Guo 3023*496d1a13SShawn Guo static struct platform_driver gcc_qcm2290_driver = { 3024*496d1a13SShawn Guo .probe = gcc_qcm2290_probe, 3025*496d1a13SShawn Guo .driver = { 3026*496d1a13SShawn Guo .name = "gcc-qcm2290", 3027*496d1a13SShawn Guo .of_match_table = gcc_qcm2290_match_table, 3028*496d1a13SShawn Guo }, 3029*496d1a13SShawn Guo }; 3030*496d1a13SShawn Guo 3031*496d1a13SShawn Guo static int __init gcc_qcm2290_init(void) 3032*496d1a13SShawn Guo { 3033*496d1a13SShawn Guo return platform_driver_register(&gcc_qcm2290_driver); 3034*496d1a13SShawn Guo } 3035*496d1a13SShawn Guo subsys_initcall(gcc_qcm2290_init); 3036*496d1a13SShawn Guo 3037*496d1a13SShawn Guo static void __exit gcc_qcm2290_exit(void) 3038*496d1a13SShawn Guo { 3039*496d1a13SShawn Guo platform_driver_unregister(&gcc_qcm2290_driver); 3040*496d1a13SShawn Guo } 3041*496d1a13SShawn Guo module_exit(gcc_qcm2290_exit); 3042*496d1a13SShawn Guo 3043*496d1a13SShawn Guo MODULE_DESCRIPTION("QTI GCC QCM2290 Driver"); 3044*496d1a13SShawn Guo MODULE_LICENSE("GPL v2"); 3045