1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2016, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/bitops.h> 8 #include <linux/err.h> 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/clk-provider.h> 14 #include <linux/regmap.h> 15 #include <linux/reset-controller.h> 16 17 #include <dt-bindings/clock/qcom,gcc-msm8998.h> 18 19 #include "common.h" 20 #include "clk-regmap.h" 21 #include "clk-alpha-pll.h" 22 #include "clk-pll.h" 23 #include "clk-rcg.h" 24 #include "clk-branch.h" 25 #include "reset.h" 26 #include "gdsc.h" 27 28 static struct pll_vco fabia_vco[] = { 29 { 250000000, 2000000000, 0 }, 30 { 125000000, 1000000000, 1 }, 31 }; 32 33 static struct clk_alpha_pll gpll0 = { 34 .offset = 0x0, 35 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 36 .vco_table = fabia_vco, 37 .num_vco = ARRAY_SIZE(fabia_vco), 38 .clkr = { 39 .enable_reg = 0x52000, 40 .enable_mask = BIT(0), 41 .hw.init = &(struct clk_init_data){ 42 .name = "gpll0", 43 .parent_data = (const struct clk_parent_data []) { 44 { .fw_name = "xo" }, 45 }, 46 .num_parents = 1, 47 .ops = &clk_alpha_pll_fixed_fabia_ops, 48 } 49 }, 50 }; 51 52 static struct clk_alpha_pll_postdiv gpll0_out_even = { 53 .offset = 0x0, 54 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 55 .clkr.hw.init = &(struct clk_init_data){ 56 .name = "gpll0_out_even", 57 .parent_hws = (const struct clk_hw*[]) { 58 &gpll0.clkr.hw, 59 }, 60 .num_parents = 1, 61 .ops = &clk_alpha_pll_postdiv_fabia_ops, 62 }, 63 }; 64 65 static struct clk_alpha_pll_postdiv gpll0_out_main = { 66 .offset = 0x0, 67 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 68 .clkr.hw.init = &(struct clk_init_data){ 69 .name = "gpll0_out_main", 70 .parent_hws = (const struct clk_hw*[]) { 71 &gpll0.clkr.hw, 72 }, 73 .num_parents = 1, 74 .ops = &clk_alpha_pll_postdiv_fabia_ops, 75 }, 76 }; 77 78 static struct clk_alpha_pll_postdiv gpll0_out_odd = { 79 .offset = 0x0, 80 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 81 .clkr.hw.init = &(struct clk_init_data){ 82 .name = "gpll0_out_odd", 83 .parent_hws = (const struct clk_hw*[]) { 84 &gpll0.clkr.hw, 85 }, 86 .num_parents = 1, 87 .ops = &clk_alpha_pll_postdiv_fabia_ops, 88 }, 89 }; 90 91 static struct clk_alpha_pll_postdiv gpll0_out_test = { 92 .offset = 0x0, 93 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 94 .clkr.hw.init = &(struct clk_init_data){ 95 .name = "gpll0_out_test", 96 .parent_hws = (const struct clk_hw*[]) { 97 &gpll0.clkr.hw, 98 }, 99 .num_parents = 1, 100 .ops = &clk_alpha_pll_postdiv_fabia_ops, 101 }, 102 }; 103 104 static struct clk_alpha_pll gpll1 = { 105 .offset = 0x1000, 106 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 107 .vco_table = fabia_vco, 108 .num_vco = ARRAY_SIZE(fabia_vco), 109 .clkr = { 110 .enable_reg = 0x52000, 111 .enable_mask = BIT(1), 112 .hw.init = &(struct clk_init_data){ 113 .name = "gpll1", 114 .parent_data = (const struct clk_parent_data []) { 115 { .fw_name = "xo" }, 116 }, 117 .num_parents = 1, 118 .ops = &clk_alpha_pll_fixed_fabia_ops, 119 } 120 }, 121 }; 122 123 static struct clk_alpha_pll_postdiv gpll1_out_even = { 124 .offset = 0x1000, 125 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 126 .clkr.hw.init = &(struct clk_init_data){ 127 .name = "gpll1_out_even", 128 .parent_hws = (const struct clk_hw*[]) { 129 &gpll1.clkr.hw, 130 }, 131 .num_parents = 1, 132 .ops = &clk_alpha_pll_postdiv_fabia_ops, 133 }, 134 }; 135 136 static struct clk_alpha_pll_postdiv gpll1_out_main = { 137 .offset = 0x1000, 138 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 139 .clkr.hw.init = &(struct clk_init_data){ 140 .name = "gpll1_out_main", 141 .parent_hws = (const struct clk_hw*[]) { 142 &gpll1.clkr.hw, 143 }, 144 .num_parents = 1, 145 .ops = &clk_alpha_pll_postdiv_fabia_ops, 146 }, 147 }; 148 149 static struct clk_alpha_pll_postdiv gpll1_out_odd = { 150 .offset = 0x1000, 151 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 152 .clkr.hw.init = &(struct clk_init_data){ 153 .name = "gpll1_out_odd", 154 .parent_hws = (const struct clk_hw*[]) { 155 &gpll1.clkr.hw, 156 }, 157 .num_parents = 1, 158 .ops = &clk_alpha_pll_postdiv_fabia_ops, 159 }, 160 }; 161 162 static struct clk_alpha_pll_postdiv gpll1_out_test = { 163 .offset = 0x1000, 164 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 165 .clkr.hw.init = &(struct clk_init_data){ 166 .name = "gpll1_out_test", 167 .parent_hws = (const struct clk_hw*[]) { 168 &gpll1.clkr.hw, 169 }, 170 .num_parents = 1, 171 .ops = &clk_alpha_pll_postdiv_fabia_ops, 172 }, 173 }; 174 175 static struct clk_alpha_pll gpll2 = { 176 .offset = 0x2000, 177 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 178 .vco_table = fabia_vco, 179 .num_vco = ARRAY_SIZE(fabia_vco), 180 .clkr = { 181 .enable_reg = 0x52000, 182 .enable_mask = BIT(2), 183 .hw.init = &(struct clk_init_data){ 184 .name = "gpll2", 185 .parent_data = (const struct clk_parent_data []) { 186 { .fw_name = "xo" }, 187 }, 188 .num_parents = 1, 189 .ops = &clk_alpha_pll_fixed_fabia_ops, 190 } 191 }, 192 }; 193 194 static struct clk_alpha_pll_postdiv gpll2_out_even = { 195 .offset = 0x2000, 196 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 197 .clkr.hw.init = &(struct clk_init_data){ 198 .name = "gpll2_out_even", 199 .parent_hws = (const struct clk_hw*[]) { 200 &gpll2.clkr.hw, 201 }, 202 .num_parents = 1, 203 .ops = &clk_alpha_pll_postdiv_fabia_ops, 204 }, 205 }; 206 207 static struct clk_alpha_pll_postdiv gpll2_out_main = { 208 .offset = 0x2000, 209 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 210 .clkr.hw.init = &(struct clk_init_data){ 211 .name = "gpll2_out_main", 212 .parent_hws = (const struct clk_hw*[]) { 213 &gpll2.clkr.hw, 214 }, 215 .num_parents = 1, 216 .ops = &clk_alpha_pll_postdiv_fabia_ops, 217 }, 218 }; 219 220 static struct clk_alpha_pll_postdiv gpll2_out_odd = { 221 .offset = 0x2000, 222 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 223 .clkr.hw.init = &(struct clk_init_data){ 224 .name = "gpll2_out_odd", 225 .parent_hws = (const struct clk_hw*[]) { 226 &gpll2.clkr.hw, 227 }, 228 .num_parents = 1, 229 .ops = &clk_alpha_pll_postdiv_fabia_ops, 230 }, 231 }; 232 233 static struct clk_alpha_pll_postdiv gpll2_out_test = { 234 .offset = 0x2000, 235 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 236 .clkr.hw.init = &(struct clk_init_data){ 237 .name = "gpll2_out_test", 238 .parent_hws = (const struct clk_hw*[]) { 239 &gpll2.clkr.hw, 240 }, 241 .num_parents = 1, 242 .ops = &clk_alpha_pll_postdiv_fabia_ops, 243 }, 244 }; 245 246 static struct clk_alpha_pll gpll3 = { 247 .offset = 0x3000, 248 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 249 .vco_table = fabia_vco, 250 .num_vco = ARRAY_SIZE(fabia_vco), 251 .clkr = { 252 .enable_reg = 0x52000, 253 .enable_mask = BIT(3), 254 .hw.init = &(struct clk_init_data){ 255 .name = "gpll3", 256 .parent_data = (const struct clk_parent_data []) { 257 { .fw_name = "xo" }, 258 }, 259 .num_parents = 1, 260 .ops = &clk_alpha_pll_fixed_fabia_ops, 261 } 262 }, 263 }; 264 265 static struct clk_alpha_pll_postdiv gpll3_out_even = { 266 .offset = 0x3000, 267 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 268 .clkr.hw.init = &(struct clk_init_data){ 269 .name = "gpll3_out_even", 270 .parent_hws = (const struct clk_hw*[]) { 271 &gpll3.clkr.hw, 272 }, 273 .num_parents = 1, 274 .ops = &clk_alpha_pll_postdiv_fabia_ops, 275 }, 276 }; 277 278 static struct clk_alpha_pll_postdiv gpll3_out_main = { 279 .offset = 0x3000, 280 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 281 .clkr.hw.init = &(struct clk_init_data){ 282 .name = "gpll3_out_main", 283 .parent_hws = (const struct clk_hw*[]) { 284 &gpll3.clkr.hw, 285 }, 286 .num_parents = 1, 287 .ops = &clk_alpha_pll_postdiv_fabia_ops, 288 }, 289 }; 290 291 static struct clk_alpha_pll_postdiv gpll3_out_odd = { 292 .offset = 0x3000, 293 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 294 .clkr.hw.init = &(struct clk_init_data){ 295 .name = "gpll3_out_odd", 296 .parent_hws = (const struct clk_hw*[]) { 297 &gpll3.clkr.hw, 298 }, 299 .num_parents = 1, 300 .ops = &clk_alpha_pll_postdiv_fabia_ops, 301 }, 302 }; 303 304 static struct clk_alpha_pll_postdiv gpll3_out_test = { 305 .offset = 0x3000, 306 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 307 .clkr.hw.init = &(struct clk_init_data){ 308 .name = "gpll3_out_test", 309 .parent_hws = (const struct clk_hw*[]) { 310 &gpll3.clkr.hw, 311 }, 312 .num_parents = 1, 313 .ops = &clk_alpha_pll_postdiv_fabia_ops, 314 }, 315 }; 316 317 static struct clk_alpha_pll gpll4 = { 318 .offset = 0x77000, 319 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 320 .vco_table = fabia_vco, 321 .num_vco = ARRAY_SIZE(fabia_vco), 322 .clkr = { 323 .enable_reg = 0x52000, 324 .enable_mask = BIT(4), 325 .hw.init = &(struct clk_init_data){ 326 .name = "gpll4", 327 .parent_data = (const struct clk_parent_data []) { 328 { .fw_name = "xo" }, 329 }, 330 .num_parents = 1, 331 .ops = &clk_alpha_pll_fixed_fabia_ops, 332 } 333 }, 334 }; 335 336 static struct clk_alpha_pll_postdiv gpll4_out_even = { 337 .offset = 0x77000, 338 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 339 .clkr.hw.init = &(struct clk_init_data){ 340 .name = "gpll4_out_even", 341 .parent_hws = (const struct clk_hw*[]) { 342 &gpll4.clkr.hw, 343 }, 344 .num_parents = 1, 345 .ops = &clk_alpha_pll_postdiv_fabia_ops, 346 }, 347 }; 348 349 static struct clk_alpha_pll_postdiv gpll4_out_main = { 350 .offset = 0x77000, 351 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 352 .clkr.hw.init = &(struct clk_init_data){ 353 .name = "gpll4_out_main", 354 .parent_hws = (const struct clk_hw*[]) { 355 &gpll4.clkr.hw, 356 }, 357 .num_parents = 1, 358 .ops = &clk_alpha_pll_postdiv_fabia_ops, 359 }, 360 }; 361 362 static struct clk_alpha_pll_postdiv gpll4_out_odd = { 363 .offset = 0x77000, 364 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 365 .clkr.hw.init = &(struct clk_init_data){ 366 .name = "gpll4_out_odd", 367 .parent_hws = (const struct clk_hw*[]) { 368 &gpll4.clkr.hw, 369 }, 370 .num_parents = 1, 371 .ops = &clk_alpha_pll_postdiv_fabia_ops, 372 }, 373 }; 374 375 static struct clk_alpha_pll_postdiv gpll4_out_test = { 376 .offset = 0x77000, 377 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 378 .clkr.hw.init = &(struct clk_init_data){ 379 .name = "gpll4_out_test", 380 .parent_hws = (const struct clk_hw*[]) { 381 &gpll4.clkr.hw, 382 }, 383 .num_parents = 1, 384 .ops = &clk_alpha_pll_postdiv_fabia_ops, 385 }, 386 }; 387 388 enum { 389 P_AUD_REF_CLK, 390 P_GPLL0_OUT_MAIN, 391 P_GPLL4_OUT_MAIN, 392 P_PLL0_EARLY_DIV_CLK_SRC, 393 P_SLEEP_CLK, 394 P_XO, 395 }; 396 397 static const struct parent_map gcc_parent_map_0[] = { 398 { P_XO, 0 }, 399 { P_GPLL0_OUT_MAIN, 1 }, 400 { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, 401 }; 402 403 static const struct clk_parent_data gcc_parent_data_0[] = { 404 { .fw_name = "xo" }, 405 { .hw = &gpll0_out_main.clkr.hw }, 406 { .hw = &gpll0_out_main.clkr.hw }, 407 }; 408 409 static const struct parent_map gcc_parent_map_1[] = { 410 { P_XO, 0 }, 411 { P_GPLL0_OUT_MAIN, 1 }, 412 }; 413 414 static const struct clk_parent_data gcc_parent_data_1[] = { 415 { .fw_name = "xo" }, 416 { .hw = &gpll0_out_main.clkr.hw }, 417 }; 418 419 static const struct parent_map gcc_parent_map_2[] = { 420 { P_XO, 0 }, 421 { P_GPLL0_OUT_MAIN, 1 }, 422 { P_SLEEP_CLK, 5 }, 423 { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, 424 }; 425 426 static const struct clk_parent_data gcc_parent_data_2[] = { 427 { .fw_name = "xo" }, 428 { .hw = &gpll0_out_main.clkr.hw }, 429 { .fw_name = "sleep_clk" }, 430 { .hw = &gpll0_out_main.clkr.hw }, 431 }; 432 433 static const struct parent_map gcc_parent_map_3[] = { 434 { P_XO, 0 }, 435 { P_SLEEP_CLK, 5 }, 436 }; 437 438 static const struct clk_parent_data gcc_parent_data_3[] = { 439 { .fw_name = "xo" }, 440 { .fw_name = "sleep_clk" }, 441 }; 442 443 static const struct parent_map gcc_parent_map_4[] = { 444 { P_XO, 0 }, 445 { P_GPLL0_OUT_MAIN, 1 }, 446 { P_GPLL4_OUT_MAIN, 5 }, 447 }; 448 449 static const struct clk_parent_data gcc_parent_data_4[] = { 450 { .fw_name = "xo" }, 451 { .hw = &gpll0_out_main.clkr.hw }, 452 { .hw = &gpll4_out_main.clkr.hw }, 453 }; 454 455 static const struct parent_map gcc_parent_map_5[] = { 456 { P_XO, 0 }, 457 { P_GPLL0_OUT_MAIN, 1 }, 458 { P_AUD_REF_CLK, 2 }, 459 }; 460 461 static const struct clk_parent_data gcc_parent_data_5[] = { 462 { .fw_name = "xo" }, 463 { .hw = &gpll0_out_main.clkr.hw }, 464 { .fw_name = "aud_ref_clk" }, 465 }; 466 467 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = { 468 F(19200000, P_XO, 1, 0, 0), 469 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 470 { } 471 }; 472 473 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 474 .cmd_rcgr = 0x19020, 475 .mnd_width = 0, 476 .hid_width = 5, 477 .parent_map = gcc_parent_map_1, 478 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 479 .clkr.hw.init = &(struct clk_init_data){ 480 .name = "blsp1_qup1_i2c_apps_clk_src", 481 .parent_data = gcc_parent_data_1, 482 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 483 .ops = &clk_rcg2_ops, 484 }, 485 }; 486 487 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { 488 F(960000, P_XO, 10, 1, 2), 489 F(4800000, P_XO, 4, 0, 0), 490 F(9600000, P_XO, 2, 0, 0), 491 F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4), 492 F(19200000, P_XO, 1, 0, 0), 493 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 494 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 495 { } 496 }; 497 498 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 499 .cmd_rcgr = 0x1900c, 500 .mnd_width = 8, 501 .hid_width = 5, 502 .parent_map = gcc_parent_map_0, 503 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 504 .clkr.hw.init = &(struct clk_init_data){ 505 .name = "blsp1_qup1_spi_apps_clk_src", 506 .parent_data = gcc_parent_data_0, 507 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 508 .ops = &clk_rcg2_ops, 509 }, 510 }; 511 512 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 513 .cmd_rcgr = 0x1b020, 514 .mnd_width = 0, 515 .hid_width = 5, 516 .parent_map = gcc_parent_map_1, 517 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 518 .clkr.hw.init = &(struct clk_init_data){ 519 .name = "blsp1_qup2_i2c_apps_clk_src", 520 .parent_data = gcc_parent_data_1, 521 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 522 .ops = &clk_rcg2_ops, 523 }, 524 }; 525 526 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 527 .cmd_rcgr = 0x1b00c, 528 .mnd_width = 8, 529 .hid_width = 5, 530 .parent_map = gcc_parent_map_0, 531 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 532 .clkr.hw.init = &(struct clk_init_data){ 533 .name = "blsp1_qup2_spi_apps_clk_src", 534 .parent_data = gcc_parent_data_0, 535 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 536 .ops = &clk_rcg2_ops, 537 }, 538 }; 539 540 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 541 .cmd_rcgr = 0x1d020, 542 .mnd_width = 0, 543 .hid_width = 5, 544 .parent_map = gcc_parent_map_1, 545 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 546 .clkr.hw.init = &(struct clk_init_data){ 547 .name = "blsp1_qup3_i2c_apps_clk_src", 548 .parent_data = gcc_parent_data_1, 549 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 550 .ops = &clk_rcg2_ops, 551 }, 552 }; 553 554 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 555 .cmd_rcgr = 0x1d00c, 556 .mnd_width = 8, 557 .hid_width = 5, 558 .parent_map = gcc_parent_map_0, 559 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 560 .clkr.hw.init = &(struct clk_init_data){ 561 .name = "blsp1_qup3_spi_apps_clk_src", 562 .parent_data = gcc_parent_data_0, 563 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 564 .ops = &clk_rcg2_ops, 565 }, 566 }; 567 568 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 569 .cmd_rcgr = 0x1f020, 570 .mnd_width = 0, 571 .hid_width = 5, 572 .parent_map = gcc_parent_map_1, 573 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 574 .clkr.hw.init = &(struct clk_init_data){ 575 .name = "blsp1_qup4_i2c_apps_clk_src", 576 .parent_data = gcc_parent_data_1, 577 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 578 .ops = &clk_rcg2_ops, 579 }, 580 }; 581 582 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 583 .cmd_rcgr = 0x1f00c, 584 .mnd_width = 8, 585 .hid_width = 5, 586 .parent_map = gcc_parent_map_0, 587 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 588 .clkr.hw.init = &(struct clk_init_data){ 589 .name = "blsp1_qup4_spi_apps_clk_src", 590 .parent_data = gcc_parent_data_0, 591 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 592 .ops = &clk_rcg2_ops, 593 }, 594 }; 595 596 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 597 .cmd_rcgr = 0x21020, 598 .mnd_width = 0, 599 .hid_width = 5, 600 .parent_map = gcc_parent_map_1, 601 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 602 .clkr.hw.init = &(struct clk_init_data){ 603 .name = "blsp1_qup5_i2c_apps_clk_src", 604 .parent_data = gcc_parent_data_1, 605 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 606 .ops = &clk_rcg2_ops, 607 }, 608 }; 609 610 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 611 .cmd_rcgr = 0x2100c, 612 .mnd_width = 8, 613 .hid_width = 5, 614 .parent_map = gcc_parent_map_0, 615 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 616 .clkr.hw.init = &(struct clk_init_data){ 617 .name = "blsp1_qup5_spi_apps_clk_src", 618 .parent_data = gcc_parent_data_0, 619 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 620 .ops = &clk_rcg2_ops, 621 }, 622 }; 623 624 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 625 .cmd_rcgr = 0x23020, 626 .mnd_width = 0, 627 .hid_width = 5, 628 .parent_map = gcc_parent_map_1, 629 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 630 .clkr.hw.init = &(struct clk_init_data){ 631 .name = "blsp1_qup6_i2c_apps_clk_src", 632 .parent_data = gcc_parent_data_1, 633 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 634 .ops = &clk_rcg2_ops, 635 }, 636 }; 637 638 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 639 .cmd_rcgr = 0x2300c, 640 .mnd_width = 8, 641 .hid_width = 5, 642 .parent_map = gcc_parent_map_0, 643 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 644 .clkr.hw.init = &(struct clk_init_data){ 645 .name = "blsp1_qup6_spi_apps_clk_src", 646 .parent_data = gcc_parent_data_0, 647 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 648 .ops = &clk_rcg2_ops, 649 }, 650 }; 651 652 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = { 653 F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625), 654 F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625), 655 F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625), 656 F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15), 657 F(19200000, P_XO, 1, 0, 0), 658 F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5), 659 F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75), 660 F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0), 661 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375), 662 F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), 663 F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375), 664 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75), 665 F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625), 666 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 667 F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0), 668 { } 669 }; 670 671 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 672 .cmd_rcgr = 0x1a00c, 673 .mnd_width = 16, 674 .hid_width = 5, 675 .parent_map = gcc_parent_map_0, 676 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 677 .clkr.hw.init = &(struct clk_init_data){ 678 .name = "blsp1_uart1_apps_clk_src", 679 .parent_data = gcc_parent_data_0, 680 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 681 .ops = &clk_rcg2_ops, 682 }, 683 }; 684 685 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 686 .cmd_rcgr = 0x1c00c, 687 .mnd_width = 16, 688 .hid_width = 5, 689 .parent_map = gcc_parent_map_0, 690 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 691 .clkr.hw.init = &(struct clk_init_data){ 692 .name = "blsp1_uart2_apps_clk_src", 693 .parent_data = gcc_parent_data_0, 694 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 695 .ops = &clk_rcg2_ops, 696 }, 697 }; 698 699 static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 700 .cmd_rcgr = 0x1e00c, 701 .mnd_width = 16, 702 .hid_width = 5, 703 .parent_map = gcc_parent_map_0, 704 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 705 .clkr.hw.init = &(struct clk_init_data){ 706 .name = "blsp1_uart3_apps_clk_src", 707 .parent_data = gcc_parent_data_0, 708 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 709 .ops = &clk_rcg2_ops, 710 }, 711 }; 712 713 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { 714 .cmd_rcgr = 0x26020, 715 .mnd_width = 0, 716 .hid_width = 5, 717 .parent_map = gcc_parent_map_1, 718 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 719 .clkr.hw.init = &(struct clk_init_data){ 720 .name = "blsp2_qup1_i2c_apps_clk_src", 721 .parent_data = gcc_parent_data_1, 722 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 723 .ops = &clk_rcg2_ops, 724 }, 725 }; 726 727 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { 728 .cmd_rcgr = 0x2600c, 729 .mnd_width = 8, 730 .hid_width = 5, 731 .parent_map = gcc_parent_map_0, 732 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 733 .clkr.hw.init = &(struct clk_init_data){ 734 .name = "blsp2_qup1_spi_apps_clk_src", 735 .parent_data = gcc_parent_data_0, 736 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 737 .ops = &clk_rcg2_ops, 738 }, 739 }; 740 741 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { 742 .cmd_rcgr = 0x28020, 743 .mnd_width = 0, 744 .hid_width = 5, 745 .parent_map = gcc_parent_map_1, 746 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 747 .clkr.hw.init = &(struct clk_init_data){ 748 .name = "blsp2_qup2_i2c_apps_clk_src", 749 .parent_data = gcc_parent_data_1, 750 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 751 .ops = &clk_rcg2_ops, 752 }, 753 }; 754 755 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { 756 .cmd_rcgr = 0x2800c, 757 .mnd_width = 8, 758 .hid_width = 5, 759 .parent_map = gcc_parent_map_0, 760 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 761 .clkr.hw.init = &(struct clk_init_data){ 762 .name = "blsp2_qup2_spi_apps_clk_src", 763 .parent_data = gcc_parent_data_0, 764 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 765 .ops = &clk_rcg2_ops, 766 }, 767 }; 768 769 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { 770 .cmd_rcgr = 0x2a020, 771 .mnd_width = 0, 772 .hid_width = 5, 773 .parent_map = gcc_parent_map_1, 774 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 775 .clkr.hw.init = &(struct clk_init_data){ 776 .name = "blsp2_qup3_i2c_apps_clk_src", 777 .parent_data = gcc_parent_data_1, 778 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 779 .ops = &clk_rcg2_ops, 780 }, 781 }; 782 783 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { 784 .cmd_rcgr = 0x2a00c, 785 .mnd_width = 8, 786 .hid_width = 5, 787 .parent_map = gcc_parent_map_0, 788 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 789 .clkr.hw.init = &(struct clk_init_data){ 790 .name = "blsp2_qup3_spi_apps_clk_src", 791 .parent_data = gcc_parent_data_0, 792 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 793 .ops = &clk_rcg2_ops, 794 }, 795 }; 796 797 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { 798 .cmd_rcgr = 0x2c020, 799 .mnd_width = 0, 800 .hid_width = 5, 801 .parent_map = gcc_parent_map_1, 802 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 803 .clkr.hw.init = &(struct clk_init_data){ 804 .name = "blsp2_qup4_i2c_apps_clk_src", 805 .parent_data = gcc_parent_data_1, 806 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 807 .ops = &clk_rcg2_ops, 808 }, 809 }; 810 811 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { 812 .cmd_rcgr = 0x2c00c, 813 .mnd_width = 8, 814 .hid_width = 5, 815 .parent_map = gcc_parent_map_0, 816 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 817 .clkr.hw.init = &(struct clk_init_data){ 818 .name = "blsp2_qup4_spi_apps_clk_src", 819 .parent_data = gcc_parent_data_0, 820 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 821 .ops = &clk_rcg2_ops, 822 }, 823 }; 824 825 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { 826 .cmd_rcgr = 0x2e020, 827 .mnd_width = 0, 828 .hid_width = 5, 829 .parent_map = gcc_parent_map_1, 830 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 831 .clkr.hw.init = &(struct clk_init_data){ 832 .name = "blsp2_qup5_i2c_apps_clk_src", 833 .parent_data = gcc_parent_data_1, 834 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 835 .ops = &clk_rcg2_ops, 836 }, 837 }; 838 839 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { 840 .cmd_rcgr = 0x2e00c, 841 .mnd_width = 8, 842 .hid_width = 5, 843 .parent_map = gcc_parent_map_0, 844 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 845 .clkr.hw.init = &(struct clk_init_data){ 846 .name = "blsp2_qup5_spi_apps_clk_src", 847 .parent_data = gcc_parent_data_0, 848 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 849 .ops = &clk_rcg2_ops, 850 }, 851 }; 852 853 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { 854 .cmd_rcgr = 0x30020, 855 .mnd_width = 0, 856 .hid_width = 5, 857 .parent_map = gcc_parent_map_1, 858 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 859 .clkr.hw.init = &(struct clk_init_data){ 860 .name = "blsp2_qup6_i2c_apps_clk_src", 861 .parent_data = gcc_parent_data_1, 862 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 863 .ops = &clk_rcg2_ops, 864 }, 865 }; 866 867 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { 868 .cmd_rcgr = 0x3000c, 869 .mnd_width = 8, 870 .hid_width = 5, 871 .parent_map = gcc_parent_map_0, 872 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 873 .clkr.hw.init = &(struct clk_init_data){ 874 .name = "blsp2_qup6_spi_apps_clk_src", 875 .parent_data = gcc_parent_data_0, 876 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 877 .ops = &clk_rcg2_ops, 878 }, 879 }; 880 881 static struct clk_rcg2 blsp2_uart1_apps_clk_src = { 882 .cmd_rcgr = 0x2700c, 883 .mnd_width = 16, 884 .hid_width = 5, 885 .parent_map = gcc_parent_map_0, 886 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 887 .clkr.hw.init = &(struct clk_init_data){ 888 .name = "blsp2_uart1_apps_clk_src", 889 .parent_data = gcc_parent_data_0, 890 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 891 .ops = &clk_rcg2_ops, 892 }, 893 }; 894 895 static struct clk_rcg2 blsp2_uart2_apps_clk_src = { 896 .cmd_rcgr = 0x2900c, 897 .mnd_width = 16, 898 .hid_width = 5, 899 .parent_map = gcc_parent_map_0, 900 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 901 .clkr.hw.init = &(struct clk_init_data){ 902 .name = "blsp2_uart2_apps_clk_src", 903 .parent_data = gcc_parent_data_0, 904 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 905 .ops = &clk_rcg2_ops, 906 }, 907 }; 908 909 static struct clk_rcg2 blsp2_uart3_apps_clk_src = { 910 .cmd_rcgr = 0x2b00c, 911 .mnd_width = 16, 912 .hid_width = 5, 913 .parent_map = gcc_parent_map_0, 914 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 915 .clkr.hw.init = &(struct clk_init_data){ 916 .name = "blsp2_uart3_apps_clk_src", 917 .parent_data = gcc_parent_data_0, 918 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 919 .ops = &clk_rcg2_ops, 920 }, 921 }; 922 923 static const struct freq_tbl ftbl_gp1_clk_src[] = { 924 F(19200000, P_XO, 1, 0, 0), 925 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 926 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 927 { } 928 }; 929 930 static struct clk_rcg2 gp1_clk_src = { 931 .cmd_rcgr = 0x64004, 932 .mnd_width = 8, 933 .hid_width = 5, 934 .parent_map = gcc_parent_map_2, 935 .freq_tbl = ftbl_gp1_clk_src, 936 .clkr.hw.init = &(struct clk_init_data){ 937 .name = "gp1_clk_src", 938 .parent_data = gcc_parent_data_2, 939 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 940 .ops = &clk_rcg2_ops, 941 }, 942 }; 943 944 static struct clk_rcg2 gp2_clk_src = { 945 .cmd_rcgr = 0x65004, 946 .mnd_width = 8, 947 .hid_width = 5, 948 .parent_map = gcc_parent_map_2, 949 .freq_tbl = ftbl_gp1_clk_src, 950 .clkr.hw.init = &(struct clk_init_data){ 951 .name = "gp2_clk_src", 952 .parent_data = gcc_parent_data_2, 953 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 954 .ops = &clk_rcg2_ops, 955 }, 956 }; 957 958 static struct clk_rcg2 gp3_clk_src = { 959 .cmd_rcgr = 0x66004, 960 .mnd_width = 8, 961 .hid_width = 5, 962 .parent_map = gcc_parent_map_2, 963 .freq_tbl = ftbl_gp1_clk_src, 964 .clkr.hw.init = &(struct clk_init_data){ 965 .name = "gp3_clk_src", 966 .parent_data = gcc_parent_data_2, 967 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 968 .ops = &clk_rcg2_ops, 969 }, 970 }; 971 972 static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = { 973 F(19200000, P_XO, 1, 0, 0), 974 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), 975 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 976 { } 977 }; 978 979 static struct clk_rcg2 hmss_ahb_clk_src = { 980 .cmd_rcgr = 0x48014, 981 .mnd_width = 0, 982 .hid_width = 5, 983 .parent_map = gcc_parent_map_1, 984 .freq_tbl = ftbl_hmss_ahb_clk_src, 985 .clkr.hw.init = &(struct clk_init_data){ 986 .name = "hmss_ahb_clk_src", 987 .parent_data = gcc_parent_data_1, 988 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 989 .ops = &clk_rcg2_ops, 990 }, 991 }; 992 993 static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { 994 F(19200000, P_XO, 1, 0, 0), 995 { } 996 }; 997 998 static struct clk_rcg2 hmss_rbcpr_clk_src = { 999 .cmd_rcgr = 0x48044, 1000 .mnd_width = 0, 1001 .hid_width = 5, 1002 .parent_map = gcc_parent_map_1, 1003 .freq_tbl = ftbl_hmss_rbcpr_clk_src, 1004 .clkr.hw.init = &(struct clk_init_data){ 1005 .name = "hmss_rbcpr_clk_src", 1006 .parent_data = gcc_parent_data_1, 1007 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1008 .ops = &clk_rcg2_ops, 1009 }, 1010 }; 1011 1012 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = { 1013 F(1010526, P_XO, 1, 1, 19), 1014 { } 1015 }; 1016 1017 static struct clk_rcg2 pcie_aux_clk_src = { 1018 .cmd_rcgr = 0x6c000, 1019 .mnd_width = 16, 1020 .hid_width = 5, 1021 .parent_map = gcc_parent_map_3, 1022 .freq_tbl = ftbl_pcie_aux_clk_src, 1023 .clkr.hw.init = &(struct clk_init_data){ 1024 .name = "pcie_aux_clk_src", 1025 .parent_data = gcc_parent_data_3, 1026 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1027 .ops = &clk_rcg2_ops, 1028 }, 1029 }; 1030 1031 static const struct freq_tbl ftbl_pdm2_clk_src[] = { 1032 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 1033 { } 1034 }; 1035 1036 static struct clk_rcg2 pdm2_clk_src = { 1037 .cmd_rcgr = 0x33010, 1038 .mnd_width = 0, 1039 .hid_width = 5, 1040 .parent_map = gcc_parent_map_1, 1041 .freq_tbl = ftbl_pdm2_clk_src, 1042 .clkr.hw.init = &(struct clk_init_data){ 1043 .name = "pdm2_clk_src", 1044 .parent_data = gcc_parent_data_1, 1045 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1046 .ops = &clk_rcg2_ops, 1047 }, 1048 }; 1049 1050 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = { 1051 F(144000, P_XO, 16, 3, 25), 1052 F(400000, P_XO, 12, 1, 4), 1053 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2), 1054 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 1055 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 1056 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 1057 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 1058 { } 1059 }; 1060 1061 static struct clk_rcg2 sdcc2_apps_clk_src = { 1062 .cmd_rcgr = 0x14010, 1063 .mnd_width = 8, 1064 .hid_width = 5, 1065 .parent_map = gcc_parent_map_4, 1066 .freq_tbl = ftbl_sdcc2_apps_clk_src, 1067 .clkr.hw.init = &(struct clk_init_data){ 1068 .name = "sdcc2_apps_clk_src", 1069 .parent_data = gcc_parent_data_4, 1070 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1071 .ops = &clk_rcg2_floor_ops, 1072 }, 1073 }; 1074 1075 static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = { 1076 F(144000, P_XO, 16, 3, 25), 1077 F(400000, P_XO, 12, 1, 4), 1078 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2), 1079 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 1080 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 1081 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 1082 { } 1083 }; 1084 1085 static struct clk_rcg2 sdcc4_apps_clk_src = { 1086 .cmd_rcgr = 0x16010, 1087 .mnd_width = 8, 1088 .hid_width = 5, 1089 .parent_map = gcc_parent_map_1, 1090 .freq_tbl = ftbl_sdcc4_apps_clk_src, 1091 .clkr.hw.init = &(struct clk_init_data){ 1092 .name = "sdcc4_apps_clk_src", 1093 .parent_data = gcc_parent_data_1, 1094 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1095 .ops = &clk_rcg2_floor_ops, 1096 }, 1097 }; 1098 1099 static const struct freq_tbl ftbl_tsif_ref_clk_src[] = { 1100 F(105495, P_XO, 1, 1, 182), 1101 { } 1102 }; 1103 1104 static struct clk_rcg2 tsif_ref_clk_src = { 1105 .cmd_rcgr = 0x36010, 1106 .mnd_width = 8, 1107 .hid_width = 5, 1108 .parent_map = gcc_parent_map_5, 1109 .freq_tbl = ftbl_tsif_ref_clk_src, 1110 .clkr.hw.init = &(struct clk_init_data){ 1111 .name = "tsif_ref_clk_src", 1112 .parent_data = gcc_parent_data_5, 1113 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1114 .ops = &clk_rcg2_ops, 1115 }, 1116 }; 1117 1118 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = { 1119 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 1120 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 1121 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 1122 { } 1123 }; 1124 1125 static struct clk_rcg2 ufs_axi_clk_src = { 1126 .cmd_rcgr = 0x75018, 1127 .mnd_width = 8, 1128 .hid_width = 5, 1129 .parent_map = gcc_parent_map_0, 1130 .freq_tbl = ftbl_ufs_axi_clk_src, 1131 .clkr.hw.init = &(struct clk_init_data){ 1132 .name = "ufs_axi_clk_src", 1133 .parent_data = gcc_parent_data_0, 1134 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1135 .ops = &clk_rcg2_ops, 1136 }, 1137 }; 1138 1139 static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = { 1140 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), 1141 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 1142 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 1143 { } 1144 }; 1145 1146 static struct clk_rcg2 ufs_unipro_core_clk_src = { 1147 .cmd_rcgr = 0x76028, 1148 .mnd_width = 8, 1149 .hid_width = 5, 1150 .parent_map = gcc_parent_map_0, 1151 .freq_tbl = ftbl_ufs_unipro_core_clk_src, 1152 .clkr.hw.init = &(struct clk_init_data){ 1153 .name = "ufs_unipro_core_clk_src", 1154 .parent_data = gcc_parent_data_0, 1155 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1156 .ops = &clk_rcg2_ops, 1157 }, 1158 }; 1159 1160 static const struct freq_tbl ftbl_usb30_master_clk_src[] = { 1161 F(19200000, P_XO, 1, 0, 0), 1162 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 1163 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), 1164 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 1165 { } 1166 }; 1167 1168 static struct clk_rcg2 usb30_master_clk_src = { 1169 .cmd_rcgr = 0xf014, 1170 .mnd_width = 8, 1171 .hid_width = 5, 1172 .parent_map = gcc_parent_map_0, 1173 .freq_tbl = ftbl_usb30_master_clk_src, 1174 .clkr.hw.init = &(struct clk_init_data){ 1175 .name = "usb30_master_clk_src", 1176 .parent_data = gcc_parent_data_0, 1177 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1178 .ops = &clk_rcg2_ops, 1179 }, 1180 }; 1181 1182 static struct clk_rcg2 usb30_mock_utmi_clk_src = { 1183 .cmd_rcgr = 0xf028, 1184 .mnd_width = 0, 1185 .hid_width = 5, 1186 .parent_map = gcc_parent_map_0, 1187 .freq_tbl = ftbl_hmss_rbcpr_clk_src, 1188 .clkr.hw.init = &(struct clk_init_data){ 1189 .name = "usb30_mock_utmi_clk_src", 1190 .parent_data = gcc_parent_data_0, 1191 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1192 .ops = &clk_rcg2_ops, 1193 }, 1194 }; 1195 1196 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { 1197 F(1200000, P_XO, 16, 0, 0), 1198 { } 1199 }; 1200 1201 static struct clk_rcg2 usb3_phy_aux_clk_src = { 1202 .cmd_rcgr = 0x5000c, 1203 .mnd_width = 0, 1204 .hid_width = 5, 1205 .parent_map = gcc_parent_map_3, 1206 .freq_tbl = ftbl_usb3_phy_aux_clk_src, 1207 .clkr.hw.init = &(struct clk_init_data){ 1208 .name = "usb3_phy_aux_clk_src", 1209 .parent_data = gcc_parent_data_3, 1210 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1211 .ops = &clk_rcg2_ops, 1212 }, 1213 }; 1214 1215 static struct clk_branch gcc_aggre1_noc_xo_clk = { 1216 .halt_reg = 0x8202c, 1217 .halt_check = BRANCH_HALT, 1218 .clkr = { 1219 .enable_reg = 0x8202c, 1220 .enable_mask = BIT(0), 1221 .hw.init = &(struct clk_init_data){ 1222 .name = "gcc_aggre1_noc_xo_clk", 1223 .ops = &clk_branch2_ops, 1224 }, 1225 }, 1226 }; 1227 1228 static struct clk_branch gcc_aggre1_ufs_axi_clk = { 1229 .halt_reg = 0x82028, 1230 .halt_check = BRANCH_HALT, 1231 .clkr = { 1232 .enable_reg = 0x82028, 1233 .enable_mask = BIT(0), 1234 .hw.init = &(struct clk_init_data){ 1235 .name = "gcc_aggre1_ufs_axi_clk", 1236 .parent_hws = (const struct clk_hw *[]) { 1237 &ufs_axi_clk_src.clkr.hw, 1238 }, 1239 .num_parents = 1, 1240 .flags = CLK_SET_RATE_PARENT, 1241 .ops = &clk_branch2_ops, 1242 }, 1243 }, 1244 }; 1245 1246 static struct clk_branch gcc_aggre1_usb3_axi_clk = { 1247 .halt_reg = 0x82024, 1248 .halt_check = BRANCH_HALT, 1249 .clkr = { 1250 .enable_reg = 0x82024, 1251 .enable_mask = BIT(0), 1252 .hw.init = &(struct clk_init_data){ 1253 .name = "gcc_aggre1_usb3_axi_clk", 1254 .parent_hws = (const struct clk_hw *[]) { 1255 &usb30_master_clk_src.clkr.hw, 1256 }, 1257 .num_parents = 1, 1258 .flags = CLK_SET_RATE_PARENT, 1259 .ops = &clk_branch2_ops, 1260 }, 1261 }, 1262 }; 1263 1264 static struct clk_branch gcc_apss_qdss_tsctr_div2_clk = { 1265 .halt_reg = 0x48090, 1266 .halt_check = BRANCH_HALT, 1267 .clkr = { 1268 .enable_reg = 0x48090, 1269 .enable_mask = BIT(0), 1270 .hw.init = &(struct clk_init_data){ 1271 .name = "gcc_apss_qdss_tsctr_div2_clk", 1272 .ops = &clk_branch2_ops, 1273 }, 1274 }, 1275 }; 1276 1277 static struct clk_branch gcc_apss_qdss_tsctr_div8_clk = { 1278 .halt_reg = 0x48094, 1279 .halt_check = BRANCH_HALT, 1280 .clkr = { 1281 .enable_reg = 0x48094, 1282 .enable_mask = BIT(0), 1283 .hw.init = &(struct clk_init_data){ 1284 .name = "gcc_apss_qdss_tsctr_div8_clk", 1285 .ops = &clk_branch2_ops, 1286 }, 1287 }, 1288 }; 1289 1290 static struct clk_branch gcc_bimc_hmss_axi_clk = { 1291 .halt_reg = 0x48004, 1292 .halt_check = BRANCH_HALT_VOTED, 1293 .clkr = { 1294 .enable_reg = 0x52004, 1295 .enable_mask = BIT(22), 1296 .hw.init = &(struct clk_init_data){ 1297 .name = "gcc_bimc_hmss_axi_clk", 1298 .ops = &clk_branch2_ops, 1299 }, 1300 }, 1301 }; 1302 1303 static struct clk_branch gcc_bimc_mss_q6_axi_clk = { 1304 .halt_reg = 0x4401c, 1305 .halt_check = BRANCH_HALT, 1306 .clkr = { 1307 .enable_reg = 0x4401c, 1308 .enable_mask = BIT(0), 1309 .hw.init = &(struct clk_init_data){ 1310 .name = "gcc_bimc_mss_q6_axi_clk", 1311 .ops = &clk_branch2_ops, 1312 }, 1313 }, 1314 }; 1315 1316 static struct clk_branch gcc_mss_cfg_ahb_clk = { 1317 .halt_reg = 0x8a000, 1318 .halt_check = BRANCH_HALT, 1319 .clkr = { 1320 .enable_reg = 0x8a000, 1321 .enable_mask = BIT(0), 1322 .hw.init = &(struct clk_init_data){ 1323 .name = "gcc_mss_cfg_ahb_clk", 1324 .ops = &clk_branch2_ops, 1325 }, 1326 }, 1327 }; 1328 1329 static struct clk_branch gcc_mss_snoc_axi_clk = { 1330 .halt_reg = 0x8a03c, 1331 .halt_check = BRANCH_HALT, 1332 .clkr = { 1333 .enable_reg = 0x8a03c, 1334 .enable_mask = BIT(0), 1335 .hw.init = &(struct clk_init_data){ 1336 .name = "gcc_mss_snoc_axi_clk", 1337 .ops = &clk_branch2_ops, 1338 }, 1339 }, 1340 }; 1341 1342 static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = { 1343 .halt_reg = 0x8a004, 1344 .halt_check = BRANCH_HALT, 1345 .clkr = { 1346 .enable_reg = 0x8a004, 1347 .enable_mask = BIT(0), 1348 .hw.init = &(struct clk_init_data){ 1349 .name = "gcc_mss_mnoc_bimc_axi_clk", 1350 .ops = &clk_branch2_ops, 1351 }, 1352 }, 1353 }; 1354 1355 static struct clk_branch gcc_boot_rom_ahb_clk = { 1356 .halt_reg = 0x38004, 1357 .halt_check = BRANCH_HALT_VOTED, 1358 .hwcg_reg = 0x38004, 1359 .hwcg_bit = 1, 1360 .clkr = { 1361 .enable_reg = 0x52004, 1362 .enable_mask = BIT(10), 1363 .hw.init = &(struct clk_init_data){ 1364 .name = "gcc_boot_rom_ahb_clk", 1365 .ops = &clk_branch2_ops, 1366 }, 1367 }, 1368 }; 1369 1370 static struct clk_branch gcc_mmss_gpll0_clk = { 1371 .halt_check = BRANCH_HALT_DELAY, 1372 .clkr = { 1373 .enable_reg = 0x5200c, 1374 .enable_mask = BIT(1), 1375 .hw.init = &(struct clk_init_data){ 1376 .name = "gcc_mmss_gpll0_clk", 1377 .parent_hws = (const struct clk_hw *[]) { 1378 &gpll0_out_main.clkr.hw, 1379 }, 1380 .num_parents = 1, 1381 .ops = &clk_branch2_ops, 1382 }, 1383 }, 1384 }; 1385 1386 static struct clk_branch gcc_mss_gpll0_div_clk_src = { 1387 .halt_check = BRANCH_HALT_DELAY, 1388 .clkr = { 1389 .enable_reg = 0x5200c, 1390 .enable_mask = BIT(2), 1391 .hw.init = &(struct clk_init_data){ 1392 .name = "gcc_mss_gpll0_div_clk_src", 1393 .ops = &clk_branch2_ops, 1394 }, 1395 }, 1396 }; 1397 1398 static struct clk_branch gcc_blsp1_ahb_clk = { 1399 .halt_reg = 0x17004, 1400 .halt_check = BRANCH_HALT_VOTED, 1401 .clkr = { 1402 .enable_reg = 0x52004, 1403 .enable_mask = BIT(17), 1404 .hw.init = &(struct clk_init_data){ 1405 .name = "gcc_blsp1_ahb_clk", 1406 .ops = &clk_branch2_ops, 1407 }, 1408 }, 1409 }; 1410 1411 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1412 .halt_reg = 0x19008, 1413 .halt_check = BRANCH_HALT, 1414 .clkr = { 1415 .enable_reg = 0x19008, 1416 .enable_mask = BIT(0), 1417 .hw.init = &(struct clk_init_data){ 1418 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1419 .parent_hws = (const struct clk_hw *[]) { 1420 &blsp1_qup1_i2c_apps_clk_src.clkr.hw, 1421 }, 1422 .num_parents = 1, 1423 .flags = CLK_SET_RATE_PARENT, 1424 .ops = &clk_branch2_ops, 1425 }, 1426 }, 1427 }; 1428 1429 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1430 .halt_reg = 0x19004, 1431 .halt_check = BRANCH_HALT, 1432 .clkr = { 1433 .enable_reg = 0x19004, 1434 .enable_mask = BIT(0), 1435 .hw.init = &(struct clk_init_data){ 1436 .name = "gcc_blsp1_qup1_spi_apps_clk", 1437 .parent_hws = (const struct clk_hw *[]) { 1438 &blsp1_qup1_spi_apps_clk_src.clkr.hw, 1439 }, 1440 .num_parents = 1, 1441 .flags = CLK_SET_RATE_PARENT, 1442 .ops = &clk_branch2_ops, 1443 }, 1444 }, 1445 }; 1446 1447 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1448 .halt_reg = 0x1b008, 1449 .halt_check = BRANCH_HALT, 1450 .clkr = { 1451 .enable_reg = 0x1b008, 1452 .enable_mask = BIT(0), 1453 .hw.init = &(struct clk_init_data){ 1454 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1455 .parent_hws = (const struct clk_hw *[]) { 1456 &blsp1_qup2_i2c_apps_clk_src.clkr.hw, 1457 }, 1458 .num_parents = 1, 1459 .flags = CLK_SET_RATE_PARENT, 1460 .ops = &clk_branch2_ops, 1461 }, 1462 }, 1463 }; 1464 1465 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1466 .halt_reg = 0x1b004, 1467 .halt_check = BRANCH_HALT, 1468 .clkr = { 1469 .enable_reg = 0x1b004, 1470 .enable_mask = BIT(0), 1471 .hw.init = &(struct clk_init_data){ 1472 .name = "gcc_blsp1_qup2_spi_apps_clk", 1473 .parent_hws = (const struct clk_hw *[]) { 1474 &blsp1_qup2_spi_apps_clk_src.clkr.hw, 1475 }, 1476 .num_parents = 1, 1477 .flags = CLK_SET_RATE_PARENT, 1478 .ops = &clk_branch2_ops, 1479 }, 1480 }, 1481 }; 1482 1483 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1484 .halt_reg = 0x1d008, 1485 .halt_check = BRANCH_HALT, 1486 .clkr = { 1487 .enable_reg = 0x1d008, 1488 .enable_mask = BIT(0), 1489 .hw.init = &(struct clk_init_data){ 1490 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1491 .parent_hws = (const struct clk_hw *[]) { 1492 &blsp1_qup3_i2c_apps_clk_src.clkr.hw, 1493 }, 1494 .num_parents = 1, 1495 .flags = CLK_SET_RATE_PARENT, 1496 .ops = &clk_branch2_ops, 1497 }, 1498 }, 1499 }; 1500 1501 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1502 .halt_reg = 0x1d004, 1503 .halt_check = BRANCH_HALT, 1504 .clkr = { 1505 .enable_reg = 0x1d004, 1506 .enable_mask = BIT(0), 1507 .hw.init = &(struct clk_init_data){ 1508 .name = "gcc_blsp1_qup3_spi_apps_clk", 1509 .parent_hws = (const struct clk_hw *[]) { 1510 &blsp1_qup3_spi_apps_clk_src.clkr.hw, 1511 }, 1512 .num_parents = 1, 1513 .flags = CLK_SET_RATE_PARENT, 1514 .ops = &clk_branch2_ops, 1515 }, 1516 }, 1517 }; 1518 1519 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1520 .halt_reg = 0x1f008, 1521 .halt_check = BRANCH_HALT, 1522 .clkr = { 1523 .enable_reg = 0x1f008, 1524 .enable_mask = BIT(0), 1525 .hw.init = &(struct clk_init_data){ 1526 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1527 .parent_hws = (const struct clk_hw *[]) { 1528 &blsp1_qup4_i2c_apps_clk_src.clkr.hw, 1529 }, 1530 .num_parents = 1, 1531 .flags = CLK_SET_RATE_PARENT, 1532 .ops = &clk_branch2_ops, 1533 }, 1534 }, 1535 }; 1536 1537 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1538 .halt_reg = 0x1f004, 1539 .halt_check = BRANCH_HALT, 1540 .clkr = { 1541 .enable_reg = 0x1f004, 1542 .enable_mask = BIT(0), 1543 .hw.init = &(struct clk_init_data){ 1544 .name = "gcc_blsp1_qup4_spi_apps_clk", 1545 .parent_hws = (const struct clk_hw *[]) { 1546 &blsp1_qup4_spi_apps_clk_src.clkr.hw, 1547 }, 1548 .num_parents = 1, 1549 .flags = CLK_SET_RATE_PARENT, 1550 .ops = &clk_branch2_ops, 1551 }, 1552 }, 1553 }; 1554 1555 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1556 .halt_reg = 0x21008, 1557 .halt_check = BRANCH_HALT, 1558 .clkr = { 1559 .enable_reg = 0x21008, 1560 .enable_mask = BIT(0), 1561 .hw.init = &(struct clk_init_data){ 1562 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1563 .parent_hws = (const struct clk_hw *[]) { 1564 &blsp1_qup5_i2c_apps_clk_src.clkr.hw, 1565 }, 1566 .num_parents = 1, 1567 .flags = CLK_SET_RATE_PARENT, 1568 .ops = &clk_branch2_ops, 1569 }, 1570 }, 1571 }; 1572 1573 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1574 .halt_reg = 0x21004, 1575 .halt_check = BRANCH_HALT, 1576 .clkr = { 1577 .enable_reg = 0x21004, 1578 .enable_mask = BIT(0), 1579 .hw.init = &(struct clk_init_data){ 1580 .name = "gcc_blsp1_qup5_spi_apps_clk", 1581 .parent_hws = (const struct clk_hw *[]) { 1582 &blsp1_qup5_spi_apps_clk_src.clkr.hw, 1583 }, 1584 .num_parents = 1, 1585 .flags = CLK_SET_RATE_PARENT, 1586 .ops = &clk_branch2_ops, 1587 }, 1588 }, 1589 }; 1590 1591 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1592 .halt_reg = 0x23008, 1593 .halt_check = BRANCH_HALT, 1594 .clkr = { 1595 .enable_reg = 0x23008, 1596 .enable_mask = BIT(0), 1597 .hw.init = &(struct clk_init_data){ 1598 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1599 .parent_hws = (const struct clk_hw *[]) { 1600 &blsp1_qup6_i2c_apps_clk_src.clkr.hw, 1601 }, 1602 .num_parents = 1, 1603 .flags = CLK_SET_RATE_PARENT, 1604 .ops = &clk_branch2_ops, 1605 }, 1606 }, 1607 }; 1608 1609 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1610 .halt_reg = 0x23004, 1611 .halt_check = BRANCH_HALT, 1612 .clkr = { 1613 .enable_reg = 0x23004, 1614 .enable_mask = BIT(0), 1615 .hw.init = &(struct clk_init_data){ 1616 .name = "gcc_blsp1_qup6_spi_apps_clk", 1617 .parent_hws = (const struct clk_hw *[]) { 1618 &blsp1_qup6_spi_apps_clk_src.clkr.hw, 1619 }, 1620 .num_parents = 1, 1621 .flags = CLK_SET_RATE_PARENT, 1622 .ops = &clk_branch2_ops, 1623 }, 1624 }, 1625 }; 1626 1627 static struct clk_branch gcc_blsp1_sleep_clk = { 1628 .halt_reg = 0x17008, 1629 .halt_check = BRANCH_HALT_VOTED, 1630 .clkr = { 1631 .enable_reg = 0x52004, 1632 .enable_mask = BIT(16), 1633 .hw.init = &(struct clk_init_data){ 1634 .name = "gcc_blsp1_sleep_clk", 1635 .ops = &clk_branch2_ops, 1636 }, 1637 }, 1638 }; 1639 1640 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1641 .halt_reg = 0x1a004, 1642 .halt_check = BRANCH_HALT, 1643 .clkr = { 1644 .enable_reg = 0x1a004, 1645 .enable_mask = BIT(0), 1646 .hw.init = &(struct clk_init_data){ 1647 .name = "gcc_blsp1_uart1_apps_clk", 1648 .parent_hws = (const struct clk_hw *[]) { 1649 &blsp1_uart1_apps_clk_src.clkr.hw, 1650 }, 1651 .num_parents = 1, 1652 .flags = CLK_SET_RATE_PARENT, 1653 .ops = &clk_branch2_ops, 1654 }, 1655 }, 1656 }; 1657 1658 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1659 .halt_reg = 0x1c004, 1660 .halt_check = BRANCH_HALT, 1661 .clkr = { 1662 .enable_reg = 0x1c004, 1663 .enable_mask = BIT(0), 1664 .hw.init = &(struct clk_init_data){ 1665 .name = "gcc_blsp1_uart2_apps_clk", 1666 .parent_hws = (const struct clk_hw *[]) { 1667 &blsp1_uart2_apps_clk_src.clkr.hw, 1668 }, 1669 .num_parents = 1, 1670 .flags = CLK_SET_RATE_PARENT, 1671 .ops = &clk_branch2_ops, 1672 }, 1673 }, 1674 }; 1675 1676 static struct clk_branch gcc_blsp1_uart3_apps_clk = { 1677 .halt_reg = 0x1e004, 1678 .halt_check = BRANCH_HALT, 1679 .clkr = { 1680 .enable_reg = 0x1e004, 1681 .enable_mask = BIT(0), 1682 .hw.init = &(struct clk_init_data){ 1683 .name = "gcc_blsp1_uart3_apps_clk", 1684 .parent_hws = (const struct clk_hw *[]) { 1685 &blsp1_uart3_apps_clk_src.clkr.hw, 1686 }, 1687 .num_parents = 1, 1688 .flags = CLK_SET_RATE_PARENT, 1689 .ops = &clk_branch2_ops, 1690 }, 1691 }, 1692 }; 1693 1694 static struct clk_branch gcc_blsp2_ahb_clk = { 1695 .halt_reg = 0x25004, 1696 .halt_check = BRANCH_HALT_VOTED, 1697 .clkr = { 1698 .enable_reg = 0x52004, 1699 .enable_mask = BIT(15), 1700 .hw.init = &(struct clk_init_data){ 1701 .name = "gcc_blsp2_ahb_clk", 1702 .ops = &clk_branch2_ops, 1703 }, 1704 }, 1705 }; 1706 1707 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { 1708 .halt_reg = 0x26008, 1709 .halt_check = BRANCH_HALT, 1710 .clkr = { 1711 .enable_reg = 0x26008, 1712 .enable_mask = BIT(0), 1713 .hw.init = &(struct clk_init_data){ 1714 .name = "gcc_blsp2_qup1_i2c_apps_clk", 1715 .parent_hws = (const struct clk_hw *[]) { 1716 &blsp2_qup1_i2c_apps_clk_src.clkr.hw, 1717 }, 1718 .num_parents = 1, 1719 .flags = CLK_SET_RATE_PARENT, 1720 .ops = &clk_branch2_ops, 1721 }, 1722 }, 1723 }; 1724 1725 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { 1726 .halt_reg = 0x26004, 1727 .halt_check = BRANCH_HALT, 1728 .clkr = { 1729 .enable_reg = 0x26004, 1730 .enable_mask = BIT(0), 1731 .hw.init = &(struct clk_init_data){ 1732 .name = "gcc_blsp2_qup1_spi_apps_clk", 1733 .parent_hws = (const struct clk_hw *[]) { 1734 &blsp2_qup1_spi_apps_clk_src.clkr.hw, 1735 }, 1736 .num_parents = 1, 1737 .flags = CLK_SET_RATE_PARENT, 1738 .ops = &clk_branch2_ops, 1739 }, 1740 }, 1741 }; 1742 1743 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { 1744 .halt_reg = 0x28008, 1745 .halt_check = BRANCH_HALT, 1746 .clkr = { 1747 .enable_reg = 0x28008, 1748 .enable_mask = BIT(0), 1749 .hw.init = &(struct clk_init_data){ 1750 .name = "gcc_blsp2_qup2_i2c_apps_clk", 1751 .parent_hws = (const struct clk_hw *[]) { 1752 &blsp2_qup2_i2c_apps_clk_src.clkr.hw, 1753 }, 1754 .num_parents = 1, 1755 .flags = CLK_SET_RATE_PARENT, 1756 .ops = &clk_branch2_ops, 1757 }, 1758 }, 1759 }; 1760 1761 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { 1762 .halt_reg = 0x28004, 1763 .halt_check = BRANCH_HALT, 1764 .clkr = { 1765 .enable_reg = 0x28004, 1766 .enable_mask = BIT(0), 1767 .hw.init = &(struct clk_init_data){ 1768 .name = "gcc_blsp2_qup2_spi_apps_clk", 1769 .parent_hws = (const struct clk_hw *[]) { 1770 &blsp2_qup2_spi_apps_clk_src.clkr.hw, 1771 }, 1772 .num_parents = 1, 1773 .flags = CLK_SET_RATE_PARENT, 1774 .ops = &clk_branch2_ops, 1775 }, 1776 }, 1777 }; 1778 1779 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { 1780 .halt_reg = 0x2a008, 1781 .halt_check = BRANCH_HALT, 1782 .clkr = { 1783 .enable_reg = 0x2a008, 1784 .enable_mask = BIT(0), 1785 .hw.init = &(struct clk_init_data){ 1786 .name = "gcc_blsp2_qup3_i2c_apps_clk", 1787 .parent_hws = (const struct clk_hw *[]) { 1788 &blsp2_qup3_i2c_apps_clk_src.clkr.hw, 1789 }, 1790 .num_parents = 1, 1791 .flags = CLK_SET_RATE_PARENT, 1792 .ops = &clk_branch2_ops, 1793 }, 1794 }, 1795 }; 1796 1797 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { 1798 .halt_reg = 0x2a004, 1799 .halt_check = BRANCH_HALT, 1800 .clkr = { 1801 .enable_reg = 0x2a004, 1802 .enable_mask = BIT(0), 1803 .hw.init = &(struct clk_init_data){ 1804 .name = "gcc_blsp2_qup3_spi_apps_clk", 1805 .parent_hws = (const struct clk_hw *[]) { 1806 &blsp2_qup3_spi_apps_clk_src.clkr.hw, 1807 }, 1808 .num_parents = 1, 1809 .flags = CLK_SET_RATE_PARENT, 1810 .ops = &clk_branch2_ops, 1811 }, 1812 }, 1813 }; 1814 1815 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { 1816 .halt_reg = 0x2c008, 1817 .halt_check = BRANCH_HALT, 1818 .clkr = { 1819 .enable_reg = 0x2c008, 1820 .enable_mask = BIT(0), 1821 .hw.init = &(struct clk_init_data){ 1822 .name = "gcc_blsp2_qup4_i2c_apps_clk", 1823 .parent_hws = (const struct clk_hw *[]) { 1824 &blsp2_qup4_i2c_apps_clk_src.clkr.hw, 1825 }, 1826 .num_parents = 1, 1827 .flags = CLK_SET_RATE_PARENT, 1828 .ops = &clk_branch2_ops, 1829 }, 1830 }, 1831 }; 1832 1833 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { 1834 .halt_reg = 0x2c004, 1835 .halt_check = BRANCH_HALT, 1836 .clkr = { 1837 .enable_reg = 0x2c004, 1838 .enable_mask = BIT(0), 1839 .hw.init = &(struct clk_init_data){ 1840 .name = "gcc_blsp2_qup4_spi_apps_clk", 1841 .parent_hws = (const struct clk_hw *[]) { 1842 &blsp2_qup4_spi_apps_clk_src.clkr.hw, 1843 }, 1844 .num_parents = 1, 1845 .flags = CLK_SET_RATE_PARENT, 1846 .ops = &clk_branch2_ops, 1847 }, 1848 }, 1849 }; 1850 1851 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { 1852 .halt_reg = 0x2e008, 1853 .halt_check = BRANCH_HALT, 1854 .clkr = { 1855 .enable_reg = 0x2e008, 1856 .enable_mask = BIT(0), 1857 .hw.init = &(struct clk_init_data){ 1858 .name = "gcc_blsp2_qup5_i2c_apps_clk", 1859 .parent_hws = (const struct clk_hw *[]) { 1860 &blsp2_qup5_i2c_apps_clk_src.clkr.hw, 1861 }, 1862 .num_parents = 1, 1863 .flags = CLK_SET_RATE_PARENT, 1864 .ops = &clk_branch2_ops, 1865 }, 1866 }, 1867 }; 1868 1869 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { 1870 .halt_reg = 0x2e004, 1871 .halt_check = BRANCH_HALT, 1872 .clkr = { 1873 .enable_reg = 0x2e004, 1874 .enable_mask = BIT(0), 1875 .hw.init = &(struct clk_init_data){ 1876 .name = "gcc_blsp2_qup5_spi_apps_clk", 1877 .parent_hws = (const struct clk_hw *[]) { 1878 &blsp2_qup5_spi_apps_clk_src.clkr.hw, 1879 }, 1880 .num_parents = 1, 1881 .flags = CLK_SET_RATE_PARENT, 1882 .ops = &clk_branch2_ops, 1883 }, 1884 }, 1885 }; 1886 1887 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { 1888 .halt_reg = 0x30008, 1889 .halt_check = BRANCH_HALT, 1890 .clkr = { 1891 .enable_reg = 0x30008, 1892 .enable_mask = BIT(0), 1893 .hw.init = &(struct clk_init_data){ 1894 .name = "gcc_blsp2_qup6_i2c_apps_clk", 1895 .parent_hws = (const struct clk_hw *[]) { 1896 &blsp2_qup6_i2c_apps_clk_src.clkr.hw, 1897 }, 1898 .num_parents = 1, 1899 .flags = CLK_SET_RATE_PARENT, 1900 .ops = &clk_branch2_ops, 1901 }, 1902 }, 1903 }; 1904 1905 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { 1906 .halt_reg = 0x30004, 1907 .halt_check = BRANCH_HALT, 1908 .clkr = { 1909 .enable_reg = 0x30004, 1910 .enable_mask = BIT(0), 1911 .hw.init = &(struct clk_init_data){ 1912 .name = "gcc_blsp2_qup6_spi_apps_clk", 1913 .parent_hws = (const struct clk_hw *[]) { 1914 &blsp2_qup6_spi_apps_clk_src.clkr.hw, 1915 }, 1916 .num_parents = 1, 1917 .flags = CLK_SET_RATE_PARENT, 1918 .ops = &clk_branch2_ops, 1919 }, 1920 }, 1921 }; 1922 1923 static struct clk_branch gcc_blsp2_sleep_clk = { 1924 .halt_reg = 0x25008, 1925 .halt_check = BRANCH_HALT_VOTED, 1926 .clkr = { 1927 .enable_reg = 0x52004, 1928 .enable_mask = BIT(14), 1929 .hw.init = &(struct clk_init_data){ 1930 .name = "gcc_blsp2_sleep_clk", 1931 .ops = &clk_branch2_ops, 1932 }, 1933 }, 1934 }; 1935 1936 static struct clk_branch gcc_blsp2_uart1_apps_clk = { 1937 .halt_reg = 0x27004, 1938 .halt_check = BRANCH_HALT, 1939 .clkr = { 1940 .enable_reg = 0x27004, 1941 .enable_mask = BIT(0), 1942 .hw.init = &(struct clk_init_data){ 1943 .name = "gcc_blsp2_uart1_apps_clk", 1944 .parent_hws = (const struct clk_hw *[]) { 1945 &blsp2_uart1_apps_clk_src.clkr.hw, 1946 }, 1947 .num_parents = 1, 1948 .flags = CLK_SET_RATE_PARENT, 1949 .ops = &clk_branch2_ops, 1950 }, 1951 }, 1952 }; 1953 1954 static struct clk_branch gcc_blsp2_uart2_apps_clk = { 1955 .halt_reg = 0x29004, 1956 .halt_check = BRANCH_HALT, 1957 .clkr = { 1958 .enable_reg = 0x29004, 1959 .enable_mask = BIT(0), 1960 .hw.init = &(struct clk_init_data){ 1961 .name = "gcc_blsp2_uart2_apps_clk", 1962 .parent_hws = (const struct clk_hw *[]) { 1963 &blsp2_uart2_apps_clk_src.clkr.hw, 1964 }, 1965 .num_parents = 1, 1966 .flags = CLK_SET_RATE_PARENT, 1967 .ops = &clk_branch2_ops, 1968 }, 1969 }, 1970 }; 1971 1972 static struct clk_branch gcc_blsp2_uart3_apps_clk = { 1973 .halt_reg = 0x2b004, 1974 .halt_check = BRANCH_HALT, 1975 .clkr = { 1976 .enable_reg = 0x2b004, 1977 .enable_mask = BIT(0), 1978 .hw.init = &(struct clk_init_data){ 1979 .name = "gcc_blsp2_uart3_apps_clk", 1980 .parent_hws = (const struct clk_hw *[]) { 1981 &blsp2_uart3_apps_clk_src.clkr.hw, 1982 }, 1983 .num_parents = 1, 1984 .flags = CLK_SET_RATE_PARENT, 1985 .ops = &clk_branch2_ops, 1986 }, 1987 }, 1988 }; 1989 1990 static struct clk_branch gcc_cfg_noc_usb3_axi_clk = { 1991 .halt_reg = 0x5018, 1992 .halt_check = BRANCH_HALT, 1993 .clkr = { 1994 .enable_reg = 0x5018, 1995 .enable_mask = BIT(0), 1996 .hw.init = &(struct clk_init_data){ 1997 .name = "gcc_cfg_noc_usb3_axi_clk", 1998 .parent_hws = (const struct clk_hw *[]) { 1999 &usb30_master_clk_src.clkr.hw, 2000 }, 2001 .num_parents = 1, 2002 .flags = CLK_SET_RATE_PARENT, 2003 .ops = &clk_branch2_ops, 2004 }, 2005 }, 2006 }; 2007 2008 static struct clk_branch gcc_gp1_clk = { 2009 .halt_reg = 0x64000, 2010 .halt_check = BRANCH_HALT, 2011 .clkr = { 2012 .enable_reg = 0x64000, 2013 .enable_mask = BIT(0), 2014 .hw.init = &(struct clk_init_data){ 2015 .name = "gcc_gp1_clk", 2016 .parent_hws = (const struct clk_hw *[]) { 2017 &gp1_clk_src.clkr.hw, 2018 }, 2019 .num_parents = 1, 2020 .flags = CLK_SET_RATE_PARENT, 2021 .ops = &clk_branch2_ops, 2022 }, 2023 }, 2024 }; 2025 2026 static struct clk_branch gcc_gp2_clk = { 2027 .halt_reg = 0x65000, 2028 .halt_check = BRANCH_HALT, 2029 .clkr = { 2030 .enable_reg = 0x65000, 2031 .enable_mask = BIT(0), 2032 .hw.init = &(struct clk_init_data){ 2033 .name = "gcc_gp2_clk", 2034 .parent_hws = (const struct clk_hw *[]) { 2035 &gp2_clk_src.clkr.hw, 2036 }, 2037 .num_parents = 1, 2038 .flags = CLK_SET_RATE_PARENT, 2039 .ops = &clk_branch2_ops, 2040 }, 2041 }, 2042 }; 2043 2044 static struct clk_branch gcc_gp3_clk = { 2045 .halt_reg = 0x66000, 2046 .halt_check = BRANCH_HALT, 2047 .clkr = { 2048 .enable_reg = 0x66000, 2049 .enable_mask = BIT(0), 2050 .hw.init = &(struct clk_init_data){ 2051 .name = "gcc_gp3_clk", 2052 .parent_hws = (const struct clk_hw *[]) { 2053 &gp3_clk_src.clkr.hw, 2054 }, 2055 .num_parents = 1, 2056 .flags = CLK_SET_RATE_PARENT, 2057 .ops = &clk_branch2_ops, 2058 }, 2059 }, 2060 }; 2061 2062 static struct clk_branch gcc_bimc_gfx_clk = { 2063 .halt_reg = 0x46040, 2064 .halt_check = BRANCH_HALT, 2065 .clkr = { 2066 .enable_reg = 0x46040, 2067 .enable_mask = BIT(0), 2068 .hw.init = &(struct clk_init_data){ 2069 .name = "gcc_bimc_gfx_clk", 2070 .ops = &clk_branch2_ops, 2071 }, 2072 }, 2073 }; 2074 2075 static struct clk_branch gcc_gpu_bimc_gfx_clk = { 2076 .halt_reg = 0x71010, 2077 .halt_check = BRANCH_HALT, 2078 .clkr = { 2079 .enable_reg = 0x71010, 2080 .enable_mask = BIT(0), 2081 .hw.init = &(struct clk_init_data){ 2082 .name = "gcc_gpu_bimc_gfx_clk", 2083 .ops = &clk_branch2_ops, 2084 }, 2085 }, 2086 }; 2087 2088 static struct clk_branch gcc_gpu_bimc_gfx_src_clk = { 2089 .halt_reg = 0x7100c, 2090 .halt_check = BRANCH_HALT, 2091 .clkr = { 2092 .enable_reg = 0x7100c, 2093 .enable_mask = BIT(0), 2094 .hw.init = &(struct clk_init_data){ 2095 .name = "gcc_gpu_bimc_gfx_src_clk", 2096 .ops = &clk_branch2_ops, 2097 }, 2098 }, 2099 }; 2100 2101 static struct clk_branch gcc_gpu_cfg_ahb_clk = { 2102 .halt_reg = 0x71004, 2103 .halt_check = BRANCH_HALT, 2104 .clkr = { 2105 .enable_reg = 0x71004, 2106 .enable_mask = BIT(0), 2107 .hw.init = &(struct clk_init_data){ 2108 .name = "gcc_gpu_cfg_ahb_clk", 2109 .ops = &clk_branch2_ops, 2110 /* 2111 * The GPU IOMMU depends on this clock and hypervisor 2112 * will crash the SoC if this clock goes down, due to 2113 * secure contexts protection. 2114 */ 2115 .flags = CLK_IS_CRITICAL, 2116 }, 2117 }, 2118 }; 2119 2120 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2121 .halt_reg = 0x71018, 2122 .halt_check = BRANCH_HALT, 2123 .clkr = { 2124 .enable_reg = 0x71018, 2125 .enable_mask = BIT(0), 2126 .hw.init = &(struct clk_init_data){ 2127 .name = "gcc_gpu_snoc_dvm_gfx_clk", 2128 .ops = &clk_branch2_ops, 2129 }, 2130 }, 2131 }; 2132 2133 static struct clk_branch gcc_hmss_ahb_clk = { 2134 .halt_reg = 0x48000, 2135 .halt_check = BRANCH_HALT_VOTED, 2136 .clkr = { 2137 .enable_reg = 0x52004, 2138 .enable_mask = BIT(21), 2139 .hw.init = &(struct clk_init_data){ 2140 .name = "gcc_hmss_ahb_clk", 2141 .parent_hws = (const struct clk_hw *[]) { 2142 &hmss_ahb_clk_src.clkr.hw, 2143 }, 2144 .num_parents = 1, 2145 .flags = CLK_SET_RATE_PARENT, 2146 .ops = &clk_branch2_ops, 2147 }, 2148 }, 2149 }; 2150 2151 static struct clk_branch gcc_hmss_at_clk = { 2152 .halt_reg = 0x48010, 2153 .halt_check = BRANCH_HALT, 2154 .clkr = { 2155 .enable_reg = 0x48010, 2156 .enable_mask = BIT(0), 2157 .hw.init = &(struct clk_init_data){ 2158 .name = "gcc_hmss_at_clk", 2159 .ops = &clk_branch2_ops, 2160 }, 2161 }, 2162 }; 2163 2164 static struct clk_branch gcc_hmss_rbcpr_clk = { 2165 .halt_reg = 0x48008, 2166 .halt_check = BRANCH_HALT, 2167 .clkr = { 2168 .enable_reg = 0x48008, 2169 .enable_mask = BIT(0), 2170 .hw.init = &(struct clk_init_data){ 2171 .name = "gcc_hmss_rbcpr_clk", 2172 .parent_hws = (const struct clk_hw *[]) { 2173 &hmss_rbcpr_clk_src.clkr.hw, 2174 }, 2175 .num_parents = 1, 2176 .flags = CLK_SET_RATE_PARENT, 2177 .ops = &clk_branch2_ops, 2178 }, 2179 }, 2180 }; 2181 2182 static struct clk_branch gcc_hmss_trig_clk = { 2183 .halt_reg = 0x4800c, 2184 .halt_check = BRANCH_HALT, 2185 .clkr = { 2186 .enable_reg = 0x4800c, 2187 .enable_mask = BIT(0), 2188 .hw.init = &(struct clk_init_data){ 2189 .name = "gcc_hmss_trig_clk", 2190 .ops = &clk_branch2_ops, 2191 }, 2192 }, 2193 }; 2194 2195 static struct freq_tbl ftbl_hmss_gpll0_clk_src[] = { 2196 F( 300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 2197 F( 600000000, P_GPLL0_OUT_MAIN, 1, 0, 0), 2198 { } 2199 }; 2200 2201 static struct clk_rcg2 hmss_gpll0_clk_src = { 2202 .cmd_rcgr = 0x4805c, 2203 .hid_width = 5, 2204 .parent_map = gcc_parent_map_1, 2205 .freq_tbl = ftbl_hmss_gpll0_clk_src, 2206 .clkr.hw.init = &(struct clk_init_data) { 2207 .name = "hmss_gpll0_clk_src", 2208 .parent_data = gcc_parent_data_1, 2209 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2210 .ops = &clk_rcg2_ops, 2211 }, 2212 }; 2213 2214 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { 2215 .halt_reg = 0x9004, 2216 .halt_check = BRANCH_HALT, 2217 .clkr = { 2218 .enable_reg = 0x9004, 2219 .enable_mask = BIT(0), 2220 .hw.init = &(struct clk_init_data){ 2221 .name = "gcc_mmss_noc_cfg_ahb_clk", 2222 .ops = &clk_branch2_ops, 2223 /* 2224 * Any access to mmss depends on this clock. 2225 * Gating this clock has been shown to crash the system 2226 * when mmssnoc_axi_rpm_clk is inited in rpmcc. 2227 */ 2228 .flags = CLK_IS_CRITICAL, 2229 }, 2230 }, 2231 }; 2232 2233 static struct clk_branch gcc_mmss_qm_ahb_clk = { 2234 .halt_reg = 0x9030, 2235 .halt_check = BRANCH_HALT, 2236 .clkr = { 2237 .enable_reg = 0x9030, 2238 .enable_mask = BIT(0), 2239 .hw.init = &(struct clk_init_data){ 2240 .name = "gcc_mmss_qm_ahb_clk", 2241 .ops = &clk_branch2_ops, 2242 }, 2243 }, 2244 }; 2245 2246 static struct clk_branch gcc_mmss_qm_core_clk = { 2247 .halt_reg = 0x900c, 2248 .halt_check = BRANCH_HALT, 2249 .clkr = { 2250 .enable_reg = 0x900c, 2251 .enable_mask = BIT(0), 2252 .hw.init = &(struct clk_init_data){ 2253 .name = "gcc_mmss_qm_core_clk", 2254 .ops = &clk_branch2_ops, 2255 }, 2256 }, 2257 }; 2258 2259 static struct clk_branch gcc_mmss_sys_noc_axi_clk = { 2260 .halt_reg = 0x9000, 2261 .halt_check = BRANCH_HALT, 2262 .clkr = { 2263 .enable_reg = 0x9000, 2264 .enable_mask = BIT(0), 2265 .hw.init = &(struct clk_init_data){ 2266 .name = "gcc_mmss_sys_noc_axi_clk", 2267 .ops = &clk_branch2_ops, 2268 }, 2269 }, 2270 }; 2271 2272 static struct clk_branch gcc_mss_at_clk = { 2273 .halt_reg = 0x8a00c, 2274 .halt_check = BRANCH_HALT, 2275 .clkr = { 2276 .enable_reg = 0x8a00c, 2277 .enable_mask = BIT(0), 2278 .hw.init = &(struct clk_init_data){ 2279 .name = "gcc_mss_at_clk", 2280 .ops = &clk_branch2_ops, 2281 }, 2282 }, 2283 }; 2284 2285 static struct clk_branch gcc_pcie_0_aux_clk = { 2286 .halt_reg = 0x6b014, 2287 .halt_check = BRANCH_HALT, 2288 .clkr = { 2289 .enable_reg = 0x6b014, 2290 .enable_mask = BIT(0), 2291 .hw.init = &(struct clk_init_data){ 2292 .name = "gcc_pcie_0_aux_clk", 2293 .parent_hws = (const struct clk_hw *[]) { 2294 &pcie_aux_clk_src.clkr.hw, 2295 }, 2296 .num_parents = 1, 2297 .flags = CLK_SET_RATE_PARENT, 2298 .ops = &clk_branch2_ops, 2299 }, 2300 }, 2301 }; 2302 2303 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 2304 .halt_reg = 0x6b010, 2305 .halt_check = BRANCH_HALT, 2306 .clkr = { 2307 .enable_reg = 0x6b010, 2308 .enable_mask = BIT(0), 2309 .hw.init = &(struct clk_init_data){ 2310 .name = "gcc_pcie_0_cfg_ahb_clk", 2311 .ops = &clk_branch2_ops, 2312 }, 2313 }, 2314 }; 2315 2316 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 2317 .halt_reg = 0x6b00c, 2318 .halt_check = BRANCH_HALT, 2319 .clkr = { 2320 .enable_reg = 0x6b00c, 2321 .enable_mask = BIT(0), 2322 .hw.init = &(struct clk_init_data){ 2323 .name = "gcc_pcie_0_mstr_axi_clk", 2324 .ops = &clk_branch2_ops, 2325 }, 2326 }, 2327 }; 2328 2329 static struct clk_branch gcc_pcie_0_pipe_clk = { 2330 .halt_reg = 0x6b018, 2331 .halt_check = BRANCH_HALT_SKIP, 2332 .clkr = { 2333 .enable_reg = 0x6b018, 2334 .enable_mask = BIT(0), 2335 .hw.init = &(struct clk_init_data){ 2336 .name = "gcc_pcie_0_pipe_clk", 2337 .ops = &clk_branch2_ops, 2338 }, 2339 }, 2340 }; 2341 2342 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 2343 .halt_reg = 0x6b008, 2344 .halt_check = BRANCH_HALT, 2345 .clkr = { 2346 .enable_reg = 0x6b008, 2347 .enable_mask = BIT(0), 2348 .hw.init = &(struct clk_init_data){ 2349 .name = "gcc_pcie_0_slv_axi_clk", 2350 .ops = &clk_branch2_ops, 2351 }, 2352 }, 2353 }; 2354 2355 static struct clk_branch gcc_pcie_phy_aux_clk = { 2356 .halt_reg = 0x6f004, 2357 .halt_check = BRANCH_HALT, 2358 .clkr = { 2359 .enable_reg = 0x6f004, 2360 .enable_mask = BIT(0), 2361 .hw.init = &(struct clk_init_data){ 2362 .name = "gcc_pcie_phy_aux_clk", 2363 .parent_hws = (const struct clk_hw *[]) { 2364 &pcie_aux_clk_src.clkr.hw, 2365 }, 2366 .num_parents = 1, 2367 .flags = CLK_SET_RATE_PARENT, 2368 .ops = &clk_branch2_ops, 2369 }, 2370 }, 2371 }; 2372 2373 static struct clk_branch gcc_pdm2_clk = { 2374 .halt_reg = 0x3300c, 2375 .halt_check = BRANCH_HALT, 2376 .clkr = { 2377 .enable_reg = 0x3300c, 2378 .enable_mask = BIT(0), 2379 .hw.init = &(struct clk_init_data){ 2380 .name = "gcc_pdm2_clk", 2381 .parent_hws = (const struct clk_hw *[]) { 2382 &pdm2_clk_src.clkr.hw, 2383 }, 2384 .num_parents = 1, 2385 .flags = CLK_SET_RATE_PARENT, 2386 .ops = &clk_branch2_ops, 2387 }, 2388 }, 2389 }; 2390 2391 static struct clk_branch gcc_pdm_ahb_clk = { 2392 .halt_reg = 0x33004, 2393 .halt_check = BRANCH_HALT, 2394 .clkr = { 2395 .enable_reg = 0x33004, 2396 .enable_mask = BIT(0), 2397 .hw.init = &(struct clk_init_data){ 2398 .name = "gcc_pdm_ahb_clk", 2399 .ops = &clk_branch2_ops, 2400 }, 2401 }, 2402 }; 2403 2404 static struct clk_branch gcc_pdm_xo4_clk = { 2405 .halt_reg = 0x33008, 2406 .halt_check = BRANCH_HALT, 2407 .clkr = { 2408 .enable_reg = 0x33008, 2409 .enable_mask = BIT(0), 2410 .hw.init = &(struct clk_init_data){ 2411 .name = "gcc_pdm_xo4_clk", 2412 .ops = &clk_branch2_ops, 2413 }, 2414 }, 2415 }; 2416 2417 static struct clk_branch gcc_prng_ahb_clk = { 2418 .halt_reg = 0x34004, 2419 .halt_check = BRANCH_HALT_VOTED, 2420 .clkr = { 2421 .enable_reg = 0x52004, 2422 .enable_mask = BIT(13), 2423 .hw.init = &(struct clk_init_data){ 2424 .name = "gcc_prng_ahb_clk", 2425 .ops = &clk_branch2_ops, 2426 }, 2427 }, 2428 }; 2429 2430 static struct clk_branch gcc_sdcc2_ahb_clk = { 2431 .halt_reg = 0x14008, 2432 .halt_check = BRANCH_HALT, 2433 .clkr = { 2434 .enable_reg = 0x14008, 2435 .enable_mask = BIT(0), 2436 .hw.init = &(struct clk_init_data){ 2437 .name = "gcc_sdcc2_ahb_clk", 2438 .ops = &clk_branch2_ops, 2439 }, 2440 }, 2441 }; 2442 2443 static struct clk_branch gcc_sdcc2_apps_clk = { 2444 .halt_reg = 0x14004, 2445 .halt_check = BRANCH_HALT, 2446 .clkr = { 2447 .enable_reg = 0x14004, 2448 .enable_mask = BIT(0), 2449 .hw.init = &(struct clk_init_data){ 2450 .name = "gcc_sdcc2_apps_clk", 2451 .parent_hws = (const struct clk_hw *[]) { 2452 &sdcc2_apps_clk_src.clkr.hw, 2453 }, 2454 .num_parents = 1, 2455 .flags = CLK_SET_RATE_PARENT, 2456 .ops = &clk_branch2_ops, 2457 }, 2458 }, 2459 }; 2460 2461 static struct clk_branch gcc_sdcc4_ahb_clk = { 2462 .halt_reg = 0x16008, 2463 .halt_check = BRANCH_HALT, 2464 .clkr = { 2465 .enable_reg = 0x16008, 2466 .enable_mask = BIT(0), 2467 .hw.init = &(struct clk_init_data){ 2468 .name = "gcc_sdcc4_ahb_clk", 2469 .ops = &clk_branch2_ops, 2470 }, 2471 }, 2472 }; 2473 2474 static struct clk_branch gcc_sdcc4_apps_clk = { 2475 .halt_reg = 0x16004, 2476 .halt_check = BRANCH_HALT, 2477 .clkr = { 2478 .enable_reg = 0x16004, 2479 .enable_mask = BIT(0), 2480 .hw.init = &(struct clk_init_data){ 2481 .name = "gcc_sdcc4_apps_clk", 2482 .parent_hws = (const struct clk_hw *[]) { 2483 &sdcc4_apps_clk_src.clkr.hw, 2484 }, 2485 .num_parents = 1, 2486 .flags = CLK_SET_RATE_PARENT, 2487 .ops = &clk_branch2_ops, 2488 }, 2489 }, 2490 }; 2491 2492 static struct clk_branch gcc_tsif_ahb_clk = { 2493 .halt_reg = 0x36004, 2494 .halt_check = BRANCH_HALT, 2495 .clkr = { 2496 .enable_reg = 0x36004, 2497 .enable_mask = BIT(0), 2498 .hw.init = &(struct clk_init_data){ 2499 .name = "gcc_tsif_ahb_clk", 2500 .ops = &clk_branch2_ops, 2501 }, 2502 }, 2503 }; 2504 2505 static struct clk_branch gcc_tsif_inactivity_timers_clk = { 2506 .halt_reg = 0x3600c, 2507 .halt_check = BRANCH_HALT, 2508 .clkr = { 2509 .enable_reg = 0x3600c, 2510 .enable_mask = BIT(0), 2511 .hw.init = &(struct clk_init_data){ 2512 .name = "gcc_tsif_inactivity_timers_clk", 2513 .ops = &clk_branch2_ops, 2514 }, 2515 }, 2516 }; 2517 2518 static struct clk_branch gcc_tsif_ref_clk = { 2519 .halt_reg = 0x36008, 2520 .halt_check = BRANCH_HALT, 2521 .clkr = { 2522 .enable_reg = 0x36008, 2523 .enable_mask = BIT(0), 2524 .hw.init = &(struct clk_init_data){ 2525 .name = "gcc_tsif_ref_clk", 2526 .parent_hws = (const struct clk_hw *[]) { 2527 &tsif_ref_clk_src.clkr.hw, 2528 }, 2529 .num_parents = 1, 2530 .flags = CLK_SET_RATE_PARENT, 2531 .ops = &clk_branch2_ops, 2532 }, 2533 }, 2534 }; 2535 2536 static struct clk_branch gcc_ufs_ahb_clk = { 2537 .halt_reg = 0x7500c, 2538 .halt_check = BRANCH_HALT, 2539 .clkr = { 2540 .enable_reg = 0x7500c, 2541 .enable_mask = BIT(0), 2542 .hw.init = &(struct clk_init_data){ 2543 .name = "gcc_ufs_ahb_clk", 2544 .ops = &clk_branch2_ops, 2545 }, 2546 }, 2547 }; 2548 2549 static struct clk_branch gcc_ufs_axi_clk = { 2550 .halt_reg = 0x75008, 2551 .halt_check = BRANCH_HALT, 2552 .clkr = { 2553 .enable_reg = 0x75008, 2554 .enable_mask = BIT(0), 2555 .hw.init = &(struct clk_init_data){ 2556 .name = "gcc_ufs_axi_clk", 2557 .parent_hws = (const struct clk_hw *[]) { 2558 &ufs_axi_clk_src.clkr.hw, 2559 }, 2560 .num_parents = 1, 2561 .flags = CLK_SET_RATE_PARENT, 2562 .ops = &clk_branch2_ops, 2563 }, 2564 }, 2565 }; 2566 2567 static struct clk_branch gcc_ufs_ice_core_clk = { 2568 .halt_reg = 0x7600c, 2569 .halt_check = BRANCH_HALT, 2570 .clkr = { 2571 .enable_reg = 0x7600c, 2572 .enable_mask = BIT(0), 2573 .hw.init = &(struct clk_init_data){ 2574 .name = "gcc_ufs_ice_core_clk", 2575 .ops = &clk_branch2_ops, 2576 }, 2577 }, 2578 }; 2579 2580 static struct clk_branch gcc_ufs_phy_aux_clk = { 2581 .halt_reg = 0x76040, 2582 .halt_check = BRANCH_HALT, 2583 .clkr = { 2584 .enable_reg = 0x76040, 2585 .enable_mask = BIT(0), 2586 .hw.init = &(struct clk_init_data){ 2587 .name = "gcc_ufs_phy_aux_clk", 2588 .ops = &clk_branch2_ops, 2589 }, 2590 }, 2591 }; 2592 2593 static struct clk_branch gcc_ufs_rx_symbol_0_clk = { 2594 .halt_reg = 0x75014, 2595 .halt_check = BRANCH_HALT_SKIP, 2596 .clkr = { 2597 .enable_reg = 0x75014, 2598 .enable_mask = BIT(0), 2599 .hw.init = &(struct clk_init_data){ 2600 .name = "gcc_ufs_rx_symbol_0_clk", 2601 .ops = &clk_branch2_ops, 2602 }, 2603 }, 2604 }; 2605 2606 static struct clk_branch gcc_ufs_rx_symbol_1_clk = { 2607 .halt_reg = 0x7605c, 2608 .halt_check = BRANCH_HALT_SKIP, 2609 .clkr = { 2610 .enable_reg = 0x7605c, 2611 .enable_mask = BIT(0), 2612 .hw.init = &(struct clk_init_data){ 2613 .name = "gcc_ufs_rx_symbol_1_clk", 2614 .ops = &clk_branch2_ops, 2615 }, 2616 }, 2617 }; 2618 2619 static struct clk_branch gcc_ufs_tx_symbol_0_clk = { 2620 .halt_reg = 0x75010, 2621 .halt_check = BRANCH_HALT_SKIP, 2622 .clkr = { 2623 .enable_reg = 0x75010, 2624 .enable_mask = BIT(0), 2625 .hw.init = &(struct clk_init_data){ 2626 .name = "gcc_ufs_tx_symbol_0_clk", 2627 .ops = &clk_branch2_ops, 2628 }, 2629 }, 2630 }; 2631 2632 static struct clk_branch gcc_ufs_unipro_core_clk = { 2633 .halt_reg = 0x76008, 2634 .halt_check = BRANCH_HALT, 2635 .clkr = { 2636 .enable_reg = 0x76008, 2637 .enable_mask = BIT(0), 2638 .hw.init = &(struct clk_init_data){ 2639 .name = "gcc_ufs_unipro_core_clk", 2640 .parent_hws = (const struct clk_hw *[]) { 2641 &ufs_unipro_core_clk_src.clkr.hw, 2642 }, 2643 .num_parents = 1, 2644 .flags = CLK_SET_RATE_PARENT, 2645 .ops = &clk_branch2_ops, 2646 }, 2647 }, 2648 }; 2649 2650 static struct clk_branch gcc_usb30_master_clk = { 2651 .halt_reg = 0xf008, 2652 .halt_check = BRANCH_HALT, 2653 .clkr = { 2654 .enable_reg = 0xf008, 2655 .enable_mask = BIT(0), 2656 .hw.init = &(struct clk_init_data){ 2657 .name = "gcc_usb30_master_clk", 2658 .parent_hws = (const struct clk_hw *[]) { 2659 &usb30_master_clk_src.clkr.hw, 2660 }, 2661 .num_parents = 1, 2662 .flags = CLK_SET_RATE_PARENT, 2663 .ops = &clk_branch2_ops, 2664 }, 2665 }, 2666 }; 2667 2668 static struct clk_branch gcc_usb30_mock_utmi_clk = { 2669 .halt_reg = 0xf010, 2670 .halt_check = BRANCH_HALT, 2671 .clkr = { 2672 .enable_reg = 0xf010, 2673 .enable_mask = BIT(0), 2674 .hw.init = &(struct clk_init_data){ 2675 .name = "gcc_usb30_mock_utmi_clk", 2676 .parent_hws = (const struct clk_hw *[]) { 2677 &usb30_mock_utmi_clk_src.clkr.hw, 2678 }, 2679 .num_parents = 1, 2680 .flags = CLK_SET_RATE_PARENT, 2681 .ops = &clk_branch2_ops, 2682 }, 2683 }, 2684 }; 2685 2686 static struct clk_branch gcc_usb30_sleep_clk = { 2687 .halt_reg = 0xf00c, 2688 .halt_check = BRANCH_HALT, 2689 .clkr = { 2690 .enable_reg = 0xf00c, 2691 .enable_mask = BIT(0), 2692 .hw.init = &(struct clk_init_data){ 2693 .name = "gcc_usb30_sleep_clk", 2694 .ops = &clk_branch2_ops, 2695 }, 2696 }, 2697 }; 2698 2699 static struct clk_branch gcc_usb3_phy_aux_clk = { 2700 .halt_reg = 0x50000, 2701 .halt_check = BRANCH_HALT, 2702 .clkr = { 2703 .enable_reg = 0x50000, 2704 .enable_mask = BIT(0), 2705 .hw.init = &(struct clk_init_data){ 2706 .name = "gcc_usb3_phy_aux_clk", 2707 .parent_hws = (const struct clk_hw *[]) { 2708 &usb3_phy_aux_clk_src.clkr.hw, 2709 }, 2710 .num_parents = 1, 2711 .flags = CLK_SET_RATE_PARENT, 2712 .ops = &clk_branch2_ops, 2713 }, 2714 }, 2715 }; 2716 2717 static struct clk_branch gcc_usb3_phy_pipe_clk = { 2718 .halt_reg = 0x50004, 2719 .halt_check = BRANCH_HALT_SKIP, 2720 .clkr = { 2721 .enable_reg = 0x50004, 2722 .enable_mask = BIT(0), 2723 .hw.init = &(struct clk_init_data){ 2724 .name = "gcc_usb3_phy_pipe_clk", 2725 .ops = &clk_branch2_ops, 2726 }, 2727 }, 2728 }; 2729 2730 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 2731 .halt_reg = 0x6a004, 2732 .halt_check = BRANCH_HALT, 2733 .clkr = { 2734 .enable_reg = 0x6a004, 2735 .enable_mask = BIT(0), 2736 .hw.init = &(struct clk_init_data){ 2737 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2738 .ops = &clk_branch2_ops, 2739 }, 2740 }, 2741 }; 2742 2743 static struct clk_branch gcc_hdmi_clkref_clk = { 2744 .halt_reg = 0x88000, 2745 .clkr = { 2746 .enable_reg = 0x88000, 2747 .enable_mask = BIT(0), 2748 .hw.init = &(struct clk_init_data){ 2749 .name = "gcc_hdmi_clkref_clk", 2750 .parent_data = (const struct clk_parent_data []) { 2751 { .fw_name = "xo" }, 2752 }, 2753 .num_parents = 1, 2754 .ops = &clk_branch2_ops, 2755 }, 2756 }, 2757 }; 2758 2759 static struct clk_branch gcc_ufs_clkref_clk = { 2760 .halt_reg = 0x88004, 2761 .clkr = { 2762 .enable_reg = 0x88004, 2763 .enable_mask = BIT(0), 2764 .hw.init = &(struct clk_init_data){ 2765 .name = "gcc_ufs_clkref_clk", 2766 .parent_data = (const struct clk_parent_data []) { 2767 { .fw_name = "xo" }, 2768 }, 2769 .num_parents = 1, 2770 .ops = &clk_branch2_ops, 2771 }, 2772 }, 2773 }; 2774 2775 static struct clk_branch gcc_usb3_clkref_clk = { 2776 .halt_reg = 0x88008, 2777 .clkr = { 2778 .enable_reg = 0x88008, 2779 .enable_mask = BIT(0), 2780 .hw.init = &(struct clk_init_data){ 2781 .name = "gcc_usb3_clkref_clk", 2782 .parent_data = (const struct clk_parent_data []) { 2783 { .fw_name = "xo" }, 2784 }, 2785 .num_parents = 1, 2786 .ops = &clk_branch2_ops, 2787 }, 2788 }, 2789 }; 2790 2791 static struct clk_branch gcc_pcie_clkref_clk = { 2792 .halt_reg = 0x8800c, 2793 .clkr = { 2794 .enable_reg = 0x8800c, 2795 .enable_mask = BIT(0), 2796 .hw.init = &(struct clk_init_data){ 2797 .name = "gcc_pcie_clkref_clk", 2798 .parent_data = (const struct clk_parent_data []) { 2799 { .fw_name = "xo" }, 2800 }, 2801 .num_parents = 1, 2802 .ops = &clk_branch2_ops, 2803 }, 2804 }, 2805 }; 2806 2807 static struct clk_branch gcc_rx1_usb2_clkref_clk = { 2808 .halt_reg = 0x88014, 2809 .clkr = { 2810 .enable_reg = 0x88014, 2811 .enable_mask = BIT(0), 2812 .hw.init = &(struct clk_init_data){ 2813 .name = "gcc_rx1_usb2_clkref_clk", 2814 .parent_data = (const struct clk_parent_data []) { 2815 { .fw_name = "xo" }, 2816 }, 2817 .num_parents = 1, 2818 .ops = &clk_branch2_ops, 2819 }, 2820 }, 2821 }; 2822 2823 static struct clk_branch gcc_im_sleep_clk = { 2824 .halt_reg = 0x4300c, 2825 .halt_check = BRANCH_HALT, 2826 .clkr = { 2827 .enable_reg = 0x4300c, 2828 .enable_mask = BIT(0), 2829 .hw.init = &(const struct clk_init_data){ 2830 .name = "gcc_im_sleep_clk", 2831 .ops = &clk_branch2_ops, 2832 }, 2833 }, 2834 }; 2835 2836 static struct clk_branch aggre2_snoc_north_axi_clk = { 2837 .halt_reg = 0x83010, 2838 .halt_check = BRANCH_HALT, 2839 .clkr = { 2840 .enable_reg = 0x83010, 2841 .enable_mask = BIT(0), 2842 .hw.init = &(const struct clk_init_data){ 2843 .name = "aggre2_snoc_north_axi_clk", 2844 .ops = &clk_branch2_ops, 2845 }, 2846 }, 2847 }; 2848 2849 static struct clk_branch ssc_xo_clk = { 2850 .halt_reg = 0x63018, 2851 .halt_check = BRANCH_HALT, 2852 .clkr = { 2853 .enable_reg = 0x63018, 2854 .enable_mask = BIT(0), 2855 .hw.init = &(const struct clk_init_data){ 2856 .name = "ssc_xo_clk", 2857 .ops = &clk_branch2_ops, 2858 }, 2859 }, 2860 }; 2861 2862 static struct clk_branch ssc_cnoc_ahbs_clk = { 2863 .halt_reg = 0x6300c, 2864 .halt_check = BRANCH_HALT, 2865 .clkr = { 2866 .enable_reg = 0x6300c, 2867 .enable_mask = BIT(0), 2868 .hw.init = &(const struct clk_init_data){ 2869 .name = "ssc_cnoc_ahbs_clk", 2870 .ops = &clk_branch2_ops, 2871 }, 2872 }, 2873 }; 2874 2875 static struct gdsc pcie_0_gdsc = { 2876 .gdscr = 0x6b004, 2877 .gds_hw_ctrl = 0x0, 2878 .pd = { 2879 .name = "pcie_0_gdsc", 2880 }, 2881 .pwrsts = PWRSTS_OFF_ON, 2882 .flags = VOTABLE, 2883 }; 2884 2885 static struct gdsc ufs_gdsc = { 2886 .gdscr = 0x75004, 2887 .gds_hw_ctrl = 0x0, 2888 .pd = { 2889 .name = "ufs_gdsc", 2890 }, 2891 .pwrsts = PWRSTS_OFF_ON, 2892 .flags = VOTABLE, 2893 }; 2894 2895 static struct gdsc usb_30_gdsc = { 2896 .gdscr = 0xf004, 2897 .gds_hw_ctrl = 0x0, 2898 .pd = { 2899 .name = "usb_30_gdsc", 2900 }, 2901 /* TODO: Change to OFF_ON when USB drivers get proper suspend support */ 2902 .pwrsts = PWRSTS_RET_ON, 2903 .flags = VOTABLE, 2904 }; 2905 2906 static struct clk_regmap *gcc_msm8998_clocks[] = { 2907 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2908 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2909 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2910 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2911 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2912 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2913 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2914 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2915 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 2916 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 2917 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 2918 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 2919 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2920 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2921 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 2922 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, 2923 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, 2924 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, 2925 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, 2926 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, 2927 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, 2928 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, 2929 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, 2930 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, 2931 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, 2932 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, 2933 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, 2934 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, 2935 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, 2936 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, 2937 [GCC_AGGRE1_NOC_XO_CLK] = &gcc_aggre1_noc_xo_clk.clkr, 2938 [GCC_AGGRE1_UFS_AXI_CLK] = &gcc_aggre1_ufs_axi_clk.clkr, 2939 [GCC_AGGRE1_USB3_AXI_CLK] = &gcc_aggre1_usb3_axi_clk.clkr, 2940 [GCC_APSS_QDSS_TSCTR_DIV2_CLK] = &gcc_apss_qdss_tsctr_div2_clk.clkr, 2941 [GCC_APSS_QDSS_TSCTR_DIV8_CLK] = &gcc_apss_qdss_tsctr_div8_clk.clkr, 2942 [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr, 2943 [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr, 2944 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2945 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2946 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2947 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2948 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2949 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2950 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2951 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 2952 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 2953 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 2954 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 2955 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 2956 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 2957 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, 2958 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2959 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2960 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 2961 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, 2962 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, 2963 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, 2964 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, 2965 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, 2966 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, 2967 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, 2968 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, 2969 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, 2970 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, 2971 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, 2972 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, 2973 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, 2974 [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr, 2975 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, 2976 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, 2977 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, 2978 [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr, 2979 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2980 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2981 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2982 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, 2983 [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr, 2984 [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr, 2985 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 2986 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 2987 [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr, 2988 [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr, 2989 [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr, 2990 [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr, 2991 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr, 2992 [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr, 2993 [GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr, 2994 [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr, 2995 [GCC_MSS_AT_CLK] = &gcc_mss_at_clk.clkr, 2996 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2997 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2998 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2999 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3000 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3001 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, 3002 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3003 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3004 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3005 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3006 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3007 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3008 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3009 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3010 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 3011 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, 3012 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 3013 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, 3014 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, 3015 [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr, 3016 [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr, 3017 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, 3018 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, 3019 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, 3020 [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr, 3021 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, 3022 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 3023 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 3024 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, 3025 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, 3026 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 3027 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 3028 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 3029 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 3030 [GPLL0] = &gpll0.clkr, 3031 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 3032 [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr, 3033 [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr, 3034 [GPLL0_OUT_TEST] = &gpll0_out_test.clkr, 3035 [GPLL1] = &gpll1.clkr, 3036 [GPLL1_OUT_EVEN] = &gpll1_out_even.clkr, 3037 [GPLL1_OUT_MAIN] = &gpll1_out_main.clkr, 3038 [GPLL1_OUT_ODD] = &gpll1_out_odd.clkr, 3039 [GPLL1_OUT_TEST] = &gpll1_out_test.clkr, 3040 [GPLL2] = &gpll2.clkr, 3041 [GPLL2_OUT_EVEN] = &gpll2_out_even.clkr, 3042 [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr, 3043 [GPLL2_OUT_ODD] = &gpll2_out_odd.clkr, 3044 [GPLL2_OUT_TEST] = &gpll2_out_test.clkr, 3045 [GPLL3] = &gpll3.clkr, 3046 [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr, 3047 [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr, 3048 [GPLL3_OUT_ODD] = &gpll3_out_odd.clkr, 3049 [GPLL3_OUT_TEST] = &gpll3_out_test.clkr, 3050 [GPLL4] = &gpll4.clkr, 3051 [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr, 3052 [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr, 3053 [GPLL4_OUT_ODD] = &gpll4_out_odd.clkr, 3054 [GPLL4_OUT_TEST] = &gpll4_out_test.clkr, 3055 [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr, 3056 [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr, 3057 [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr, 3058 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 3059 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 3060 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, 3061 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, 3062 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, 3063 [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr, 3064 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, 3065 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 3066 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, 3067 [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr, 3068 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, 3069 [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr, 3070 [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr, 3071 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr, 3072 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 3073 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3074 [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr, 3075 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, 3076 [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr, 3077 [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr, 3078 [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr, 3079 [GCC_IM_SLEEP] = &gcc_im_sleep_clk.clkr, 3080 [AGGRE2_SNOC_NORTH_AXI] = &aggre2_snoc_north_axi_clk.clkr, 3081 [SSC_XO] = &ssc_xo_clk.clkr, 3082 [SSC_CNOC_AHBS_CLK] = &ssc_cnoc_ahbs_clk.clkr, 3083 }; 3084 3085 static struct gdsc *gcc_msm8998_gdscs[] = { 3086 [PCIE_0_GDSC] = &pcie_0_gdsc, 3087 [UFS_GDSC] = &ufs_gdsc, 3088 [USB_30_GDSC] = &usb_30_gdsc, 3089 }; 3090 3091 static const struct qcom_reset_map gcc_msm8998_resets[] = { 3092 [GCC_BLSP1_QUP1_BCR] = { 0x19000 }, 3093 [GCC_BLSP1_QUP2_BCR] = { 0x1b000 }, 3094 [GCC_BLSP1_QUP3_BCR] = { 0x1d000 }, 3095 [GCC_BLSP1_QUP4_BCR] = { 0x1f000 }, 3096 [GCC_BLSP1_QUP5_BCR] = { 0x21000 }, 3097 [GCC_BLSP1_QUP6_BCR] = { 0x23000 }, 3098 [GCC_BLSP2_QUP1_BCR] = { 0x26000 }, 3099 [GCC_BLSP2_QUP2_BCR] = { 0x28000 }, 3100 [GCC_BLSP2_QUP3_BCR] = { 0x2a000 }, 3101 [GCC_BLSP2_QUP4_BCR] = { 0x2c000 }, 3102 [GCC_BLSP2_QUP5_BCR] = { 0x2e000 }, 3103 [GCC_BLSP2_QUP6_BCR] = { 0x30000 }, 3104 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3105 [GCC_PDM_BCR] = { 0x33000 }, 3106 [GCC_SDCC2_BCR] = { 0x14000 }, 3107 [GCC_SDCC4_BCR] = { 0x16000 }, 3108 [GCC_TSIF_BCR] = { 0x36000 }, 3109 [GCC_UFS_BCR] = { 0x75000 }, 3110 [GCC_USB_30_BCR] = { 0xf000 }, 3111 [GCC_SYSTEM_NOC_BCR] = { 0x4000 }, 3112 [GCC_CONFIG_NOC_BCR] = { 0x5000 }, 3113 [GCC_AHB2PHY_EAST_BCR] = { 0x7000 }, 3114 [GCC_IMEM_BCR] = { 0x8000 }, 3115 [GCC_PIMEM_BCR] = { 0xa000 }, 3116 [GCC_MMSS_BCR] = { 0xb000 }, 3117 [GCC_QDSS_BCR] = { 0xc000 }, 3118 [GCC_WCSS_BCR] = { 0x11000 }, 3119 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3120 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3121 [GCC_BLSP1_BCR] = { 0x17000 }, 3122 [GCC_BLSP1_UART1_BCR] = { 0x1a000 }, 3123 [GCC_BLSP1_UART2_BCR] = { 0x1c000 }, 3124 [GCC_BLSP1_UART3_BCR] = { 0x1e000 }, 3125 [GCC_CM_PHY_REFGEN1_BCR] = { 0x22000 }, 3126 [GCC_CM_PHY_REFGEN2_BCR] = { 0x24000 }, 3127 [GCC_BLSP2_BCR] = { 0x25000 }, 3128 [GCC_BLSP2_UART1_BCR] = { 0x27000 }, 3129 [GCC_BLSP2_UART2_BCR] = { 0x29000 }, 3130 [GCC_BLSP2_UART3_BCR] = { 0x2b000 }, 3131 [GCC_SRAM_SENSOR_BCR] = { 0x2d000 }, 3132 [GCC_PRNG_BCR] = { 0x34000 }, 3133 [GCC_TSIF_0_RESET] = { 0x36024 }, 3134 [GCC_TSIF_1_RESET] = { 0x36028 }, 3135 [GCC_TCSR_BCR] = { 0x37000 }, 3136 [GCC_BOOT_ROM_BCR] = { 0x38000 }, 3137 [GCC_MSG_RAM_BCR] = { 0x39000 }, 3138 [GCC_TLMM_BCR] = { 0x3a000 }, 3139 [GCC_MPM_BCR] = { 0x3b000 }, 3140 [GCC_SEC_CTRL_BCR] = { 0x3d000 }, 3141 [GCC_SPMI_BCR] = { 0x3f000 }, 3142 [GCC_SPDM_BCR] = { 0x40000 }, 3143 [GCC_CE1_BCR] = { 0x41000 }, 3144 [GCC_BIMC_BCR] = { 0x44000 }, 3145 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 }, 3146 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49008 }, 3147 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49010 }, 3148 [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49018 }, 3149 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 }, 3150 [GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR] = { 0x4a004 }, 3151 [GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR] = { 0x4a00c }, 3152 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 }, 3153 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 }, 3154 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 }, 3155 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 }, 3156 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 }, 3157 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 }, 3158 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 }, 3159 [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 }, 3160 [GCC_APB2JTAG_BCR] = { 0x4c000 }, 3161 [GCC_RBCPR_CX_BCR] = { 0x4e000 }, 3162 [GCC_RBCPR_MX_BCR] = { 0x4f000 }, 3163 [GCC_USB3_PHY_BCR] = { 0x50020 }, 3164 [GCC_USB3PHY_PHY_BCR] = { 0x50024 }, 3165 [GCC_USB3_DP_PHY_BCR] = { 0x50028 }, 3166 [GCC_SSC_BCR] = { 0x63000 }, 3167 [GCC_SSC_RESET] = { 0x63020 }, 3168 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 3169 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 3170 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3171 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 3172 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 3173 [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00c }, 3174 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f010 }, 3175 [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 }, 3176 [GCC_GPU_BCR] = { 0x71000 }, 3177 [GCC_SPSS_BCR] = { 0x72000 }, 3178 [GCC_OBT_ODT_BCR] = { 0x73000 }, 3179 [GCC_MSS_RESTART] = { 0x79000 }, 3180 [GCC_VS_BCR] = { 0x7a000 }, 3181 [GCC_MSS_VS_RESET] = { 0x7a100 }, 3182 [GCC_GPU_VS_RESET] = { 0x7a104 }, 3183 [GCC_APC0_VS_RESET] = { 0x7a108 }, 3184 [GCC_APC1_VS_RESET] = { 0x7a10c }, 3185 [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 }, 3186 [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 }, 3187 [GCC_CNOC_BUS_TIMEOUT10_BCR] = { 0x80010 }, 3188 [GCC_CNOC_BUS_TIMEOUT11_BCR] = { 0x80018 }, 3189 [GCC_CNOC_BUS_TIMEOUT12_BCR] = { 0x80020 }, 3190 [GCC_CNOC_BUS_TIMEOUT13_BCR] = { 0x80028 }, 3191 [GCC_CNOC_BUS_TIMEOUT14_BCR] = { 0x80030 }, 3192 [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80038 }, 3193 [GCC_AGGRE1_NOC_BCR] = { 0x82000 }, 3194 [GCC_AGGRE2_NOC_BCR] = { 0x83000 }, 3195 [GCC_DCC_BCR] = { 0x84000 }, 3196 [GCC_QREFS_VBG_CAL_BCR] = { 0x88028 }, 3197 [GCC_IPA_BCR] = { 0x89000 }, 3198 [GCC_GLM_BCR] = { 0x8b000 }, 3199 [GCC_SKL_BCR] = { 0x8c000 }, 3200 [GCC_MSMPU_BCR] = { 0x8d000 }, 3201 }; 3202 3203 static const struct regmap_config gcc_msm8998_regmap_config = { 3204 .reg_bits = 32, 3205 .reg_stride = 4, 3206 .val_bits = 32, 3207 .max_register = 0x8f000, 3208 .fast_io = true, 3209 }; 3210 3211 static const struct qcom_cc_desc gcc_msm8998_desc = { 3212 .config = &gcc_msm8998_regmap_config, 3213 .clks = gcc_msm8998_clocks, 3214 .num_clks = ARRAY_SIZE(gcc_msm8998_clocks), 3215 .resets = gcc_msm8998_resets, 3216 .num_resets = ARRAY_SIZE(gcc_msm8998_resets), 3217 .gdscs = gcc_msm8998_gdscs, 3218 .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs), 3219 }; 3220 3221 static int gcc_msm8998_probe(struct platform_device *pdev) 3222 { 3223 struct regmap *regmap; 3224 int ret; 3225 3226 regmap = qcom_cc_map(pdev, &gcc_msm8998_desc); 3227 if (IS_ERR(regmap)) 3228 return PTR_ERR(regmap); 3229 3230 /* 3231 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be 3232 * turned off by hardware during certain apps low power modes. 3233 */ 3234 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); 3235 if (ret) 3236 return ret; 3237 3238 return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap); 3239 } 3240 3241 static const struct of_device_id gcc_msm8998_match_table[] = { 3242 { .compatible = "qcom,gcc-msm8998" }, 3243 { } 3244 }; 3245 MODULE_DEVICE_TABLE(of, gcc_msm8998_match_table); 3246 3247 static struct platform_driver gcc_msm8998_driver = { 3248 .probe = gcc_msm8998_probe, 3249 .driver = { 3250 .name = "gcc-msm8998", 3251 .of_match_table = gcc_msm8998_match_table, 3252 }, 3253 }; 3254 3255 static int __init gcc_msm8998_init(void) 3256 { 3257 return platform_driver_register(&gcc_msm8998_driver); 3258 } 3259 core_initcall(gcc_msm8998_init); 3260 3261 static void __exit gcc_msm8998_exit(void) 3262 { 3263 platform_driver_unregister(&gcc_msm8998_driver); 3264 } 3265 module_exit(gcc_msm8998_exit); 3266 3267 MODULE_DESCRIPTION("QCOM GCC msm8998 Driver"); 3268 MODULE_LICENSE("GPL v2"); 3269 MODULE_ALIAS("platform:gcc-msm8998"); 3270