1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2016, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/bitops.h> 8 #include <linux/err.h> 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/clk-provider.h> 14 #include <linux/regmap.h> 15 #include <linux/reset-controller.h> 16 17 #include <dt-bindings/clock/qcom,gcc-msm8998.h> 18 19 #include "common.h" 20 #include "clk-regmap.h" 21 #include "clk-alpha-pll.h" 22 #include "clk-pll.h" 23 #include "clk-rcg.h" 24 #include "clk-branch.h" 25 #include "reset.h" 26 #include "gdsc.h" 27 28 enum { 29 P_AUD_REF_CLK, 30 P_CORE_BI_PLL_TEST_SE, 31 P_GPLL0_OUT_MAIN, 32 P_GPLL4_OUT_MAIN, 33 P_PLL0_EARLY_DIV_CLK_SRC, 34 P_SLEEP_CLK, 35 P_XO, 36 }; 37 38 static const struct parent_map gcc_parent_map_0[] = { 39 { P_XO, 0 }, 40 { P_GPLL0_OUT_MAIN, 1 }, 41 { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, 42 { P_CORE_BI_PLL_TEST_SE, 7 }, 43 }; 44 45 static const char * const gcc_parent_names_0[] = { 46 "xo", 47 "gpll0_out_main", 48 "gpll0_out_main", 49 "core_bi_pll_test_se", 50 }; 51 52 static const struct parent_map gcc_parent_map_1[] = { 53 { P_XO, 0 }, 54 { P_GPLL0_OUT_MAIN, 1 }, 55 { P_CORE_BI_PLL_TEST_SE, 7 }, 56 }; 57 58 static const char * const gcc_parent_names_1[] = { 59 "xo", 60 "gpll0_out_main", 61 "core_bi_pll_test_se", 62 }; 63 64 static const struct parent_map gcc_parent_map_2[] = { 65 { P_XO, 0 }, 66 { P_GPLL0_OUT_MAIN, 1 }, 67 { P_SLEEP_CLK, 5 }, 68 { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, 69 { P_CORE_BI_PLL_TEST_SE, 7 }, 70 }; 71 72 static const char * const gcc_parent_names_2[] = { 73 "xo", 74 "gpll0_out_main", 75 "core_pi_sleep_clk", 76 "gpll0_out_main", 77 "core_bi_pll_test_se", 78 }; 79 80 static const struct parent_map gcc_parent_map_3[] = { 81 { P_XO, 0 }, 82 { P_SLEEP_CLK, 5 }, 83 { P_CORE_BI_PLL_TEST_SE, 7 }, 84 }; 85 86 static const char * const gcc_parent_names_3[] = { 87 "xo", 88 "core_pi_sleep_clk", 89 "core_bi_pll_test_se", 90 }; 91 92 static const struct parent_map gcc_parent_map_4[] = { 93 { P_XO, 0 }, 94 { P_GPLL0_OUT_MAIN, 1 }, 95 { P_GPLL4_OUT_MAIN, 5 }, 96 { P_CORE_BI_PLL_TEST_SE, 7 }, 97 }; 98 99 static const char * const gcc_parent_names_4[] = { 100 "xo", 101 "gpll0_out_main", 102 "gpll4_out_main", 103 "core_bi_pll_test_se", 104 }; 105 106 static const struct parent_map gcc_parent_map_5[] = { 107 { P_XO, 0 }, 108 { P_GPLL0_OUT_MAIN, 1 }, 109 { P_AUD_REF_CLK, 2 }, 110 { P_CORE_BI_PLL_TEST_SE, 7 }, 111 }; 112 113 static const char * const gcc_parent_names_5[] = { 114 "xo", 115 "gpll0_out_main", 116 "aud_ref_clk", 117 "core_bi_pll_test_se", 118 }; 119 120 static struct clk_fixed_factor xo = { 121 .mult = 1, 122 .div = 1, 123 .hw.init = &(struct clk_init_data){ 124 .name = "xo", 125 .parent_names = (const char *[]){ "xo_board" }, 126 .num_parents = 1, 127 .ops = &clk_fixed_factor_ops, 128 }, 129 }; 130 131 static struct pll_vco fabia_vco[] = { 132 { 250000000, 2000000000, 0 }, 133 { 125000000, 1000000000, 1 }, 134 }; 135 136 static struct clk_alpha_pll gpll0 = { 137 .offset = 0x0, 138 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 139 .vco_table = fabia_vco, 140 .num_vco = ARRAY_SIZE(fabia_vco), 141 .clkr = { 142 .enable_reg = 0x52000, 143 .enable_mask = BIT(0), 144 .hw.init = &(struct clk_init_data){ 145 .name = "gpll0", 146 .parent_names = (const char *[]){ "xo" }, 147 .num_parents = 1, 148 .ops = &clk_alpha_pll_ops, 149 } 150 }, 151 }; 152 153 static struct clk_alpha_pll_postdiv gpll0_out_even = { 154 .offset = 0x0, 155 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 156 .clkr.hw.init = &(struct clk_init_data){ 157 .name = "gpll0_out_even", 158 .parent_names = (const char *[]){ "gpll0" }, 159 .num_parents = 1, 160 .ops = &clk_alpha_pll_postdiv_ops, 161 }, 162 }; 163 164 static struct clk_alpha_pll_postdiv gpll0_out_main = { 165 .offset = 0x0, 166 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 167 .clkr.hw.init = &(struct clk_init_data){ 168 .name = "gpll0_out_main", 169 .parent_names = (const char *[]){ "gpll0" }, 170 .num_parents = 1, 171 .ops = &clk_alpha_pll_postdiv_ops, 172 }, 173 }; 174 175 static struct clk_alpha_pll_postdiv gpll0_out_odd = { 176 .offset = 0x0, 177 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 178 .clkr.hw.init = &(struct clk_init_data){ 179 .name = "gpll0_out_odd", 180 .parent_names = (const char *[]){ "gpll0" }, 181 .num_parents = 1, 182 .ops = &clk_alpha_pll_postdiv_ops, 183 }, 184 }; 185 186 static struct clk_alpha_pll_postdiv gpll0_out_test = { 187 .offset = 0x0, 188 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 189 .clkr.hw.init = &(struct clk_init_data){ 190 .name = "gpll0_out_test", 191 .parent_names = (const char *[]){ "gpll0" }, 192 .num_parents = 1, 193 .ops = &clk_alpha_pll_postdiv_ops, 194 }, 195 }; 196 197 static struct clk_alpha_pll gpll1 = { 198 .offset = 0x1000, 199 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 200 .vco_table = fabia_vco, 201 .num_vco = ARRAY_SIZE(fabia_vco), 202 .clkr = { 203 .enable_reg = 0x52000, 204 .enable_mask = BIT(1), 205 .hw.init = &(struct clk_init_data){ 206 .name = "gpll1", 207 .parent_names = (const char *[]){ "xo" }, 208 .num_parents = 1, 209 .ops = &clk_alpha_pll_ops, 210 } 211 }, 212 }; 213 214 static struct clk_alpha_pll_postdiv gpll1_out_even = { 215 .offset = 0x1000, 216 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 217 .clkr.hw.init = &(struct clk_init_data){ 218 .name = "gpll1_out_even", 219 .parent_names = (const char *[]){ "gpll1" }, 220 .num_parents = 1, 221 .ops = &clk_alpha_pll_postdiv_ops, 222 }, 223 }; 224 225 static struct clk_alpha_pll_postdiv gpll1_out_main = { 226 .offset = 0x1000, 227 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 228 .clkr.hw.init = &(struct clk_init_data){ 229 .name = "gpll1_out_main", 230 .parent_names = (const char *[]){ "gpll1" }, 231 .num_parents = 1, 232 .ops = &clk_alpha_pll_postdiv_ops, 233 }, 234 }; 235 236 static struct clk_alpha_pll_postdiv gpll1_out_odd = { 237 .offset = 0x1000, 238 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 239 .clkr.hw.init = &(struct clk_init_data){ 240 .name = "gpll1_out_odd", 241 .parent_names = (const char *[]){ "gpll1" }, 242 .num_parents = 1, 243 .ops = &clk_alpha_pll_postdiv_ops, 244 }, 245 }; 246 247 static struct clk_alpha_pll_postdiv gpll1_out_test = { 248 .offset = 0x1000, 249 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 250 .clkr.hw.init = &(struct clk_init_data){ 251 .name = "gpll1_out_test", 252 .parent_names = (const char *[]){ "gpll1" }, 253 .num_parents = 1, 254 .ops = &clk_alpha_pll_postdiv_ops, 255 }, 256 }; 257 258 static struct clk_alpha_pll gpll2 = { 259 .offset = 0x2000, 260 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 261 .vco_table = fabia_vco, 262 .num_vco = ARRAY_SIZE(fabia_vco), 263 .clkr = { 264 .enable_reg = 0x52000, 265 .enable_mask = BIT(2), 266 .hw.init = &(struct clk_init_data){ 267 .name = "gpll2", 268 .parent_names = (const char *[]){ "xo" }, 269 .num_parents = 1, 270 .ops = &clk_alpha_pll_ops, 271 } 272 }, 273 }; 274 275 static struct clk_alpha_pll_postdiv gpll2_out_even = { 276 .offset = 0x2000, 277 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 278 .clkr.hw.init = &(struct clk_init_data){ 279 .name = "gpll2_out_even", 280 .parent_names = (const char *[]){ "gpll2" }, 281 .num_parents = 1, 282 .ops = &clk_alpha_pll_postdiv_ops, 283 }, 284 }; 285 286 static struct clk_alpha_pll_postdiv gpll2_out_main = { 287 .offset = 0x2000, 288 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 289 .clkr.hw.init = &(struct clk_init_data){ 290 .name = "gpll2_out_main", 291 .parent_names = (const char *[]){ "gpll2" }, 292 .num_parents = 1, 293 .ops = &clk_alpha_pll_postdiv_ops, 294 }, 295 }; 296 297 static struct clk_alpha_pll_postdiv gpll2_out_odd = { 298 .offset = 0x2000, 299 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 300 .clkr.hw.init = &(struct clk_init_data){ 301 .name = "gpll2_out_odd", 302 .parent_names = (const char *[]){ "gpll2" }, 303 .num_parents = 1, 304 .ops = &clk_alpha_pll_postdiv_ops, 305 }, 306 }; 307 308 static struct clk_alpha_pll_postdiv gpll2_out_test = { 309 .offset = 0x2000, 310 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 311 .clkr.hw.init = &(struct clk_init_data){ 312 .name = "gpll2_out_test", 313 .parent_names = (const char *[]){ "gpll2" }, 314 .num_parents = 1, 315 .ops = &clk_alpha_pll_postdiv_ops, 316 }, 317 }; 318 319 static struct clk_alpha_pll gpll3 = { 320 .offset = 0x3000, 321 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 322 .vco_table = fabia_vco, 323 .num_vco = ARRAY_SIZE(fabia_vco), 324 .clkr = { 325 .enable_reg = 0x52000, 326 .enable_mask = BIT(3), 327 .hw.init = &(struct clk_init_data){ 328 .name = "gpll3", 329 .parent_names = (const char *[]){ "xo" }, 330 .num_parents = 1, 331 .ops = &clk_alpha_pll_ops, 332 } 333 }, 334 }; 335 336 static struct clk_alpha_pll_postdiv gpll3_out_even = { 337 .offset = 0x3000, 338 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 339 .clkr.hw.init = &(struct clk_init_data){ 340 .name = "gpll3_out_even", 341 .parent_names = (const char *[]){ "gpll3" }, 342 .num_parents = 1, 343 .ops = &clk_alpha_pll_postdiv_ops, 344 }, 345 }; 346 347 static struct clk_alpha_pll_postdiv gpll3_out_main = { 348 .offset = 0x3000, 349 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 350 .clkr.hw.init = &(struct clk_init_data){ 351 .name = "gpll3_out_main", 352 .parent_names = (const char *[]){ "gpll3" }, 353 .num_parents = 1, 354 .ops = &clk_alpha_pll_postdiv_ops, 355 }, 356 }; 357 358 static struct clk_alpha_pll_postdiv gpll3_out_odd = { 359 .offset = 0x3000, 360 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 361 .clkr.hw.init = &(struct clk_init_data){ 362 .name = "gpll3_out_odd", 363 .parent_names = (const char *[]){ "gpll3" }, 364 .num_parents = 1, 365 .ops = &clk_alpha_pll_postdiv_ops, 366 }, 367 }; 368 369 static struct clk_alpha_pll_postdiv gpll3_out_test = { 370 .offset = 0x3000, 371 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 372 .clkr.hw.init = &(struct clk_init_data){ 373 .name = "gpll3_out_test", 374 .parent_names = (const char *[]){ "gpll3" }, 375 .num_parents = 1, 376 .ops = &clk_alpha_pll_postdiv_ops, 377 }, 378 }; 379 380 static struct clk_alpha_pll gpll4 = { 381 .offset = 0x77000, 382 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 383 .vco_table = fabia_vco, 384 .num_vco = ARRAY_SIZE(fabia_vco), 385 .clkr = { 386 .enable_reg = 0x52000, 387 .enable_mask = BIT(4), 388 .hw.init = &(struct clk_init_data){ 389 .name = "gpll4", 390 .parent_names = (const char *[]){ "xo" }, 391 .num_parents = 1, 392 .ops = &clk_alpha_pll_ops, 393 } 394 }, 395 }; 396 397 static struct clk_alpha_pll_postdiv gpll4_out_even = { 398 .offset = 0x77000, 399 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 400 .clkr.hw.init = &(struct clk_init_data){ 401 .name = "gpll4_out_even", 402 .parent_names = (const char *[]){ "gpll4" }, 403 .num_parents = 1, 404 .ops = &clk_alpha_pll_postdiv_ops, 405 }, 406 }; 407 408 static struct clk_alpha_pll_postdiv gpll4_out_main = { 409 .offset = 0x77000, 410 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 411 .clkr.hw.init = &(struct clk_init_data){ 412 .name = "gpll4_out_main", 413 .parent_names = (const char *[]){ "gpll4" }, 414 .num_parents = 1, 415 .ops = &clk_alpha_pll_postdiv_ops, 416 }, 417 }; 418 419 static struct clk_alpha_pll_postdiv gpll4_out_odd = { 420 .offset = 0x77000, 421 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 422 .clkr.hw.init = &(struct clk_init_data){ 423 .name = "gpll4_out_odd", 424 .parent_names = (const char *[]){ "gpll4" }, 425 .num_parents = 1, 426 .ops = &clk_alpha_pll_postdiv_ops, 427 }, 428 }; 429 430 static struct clk_alpha_pll_postdiv gpll4_out_test = { 431 .offset = 0x77000, 432 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 433 .clkr.hw.init = &(struct clk_init_data){ 434 .name = "gpll4_out_test", 435 .parent_names = (const char *[]){ "gpll4" }, 436 .num_parents = 1, 437 .ops = &clk_alpha_pll_postdiv_ops, 438 }, 439 }; 440 441 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = { 442 F(19200000, P_XO, 1, 0, 0), 443 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 444 { } 445 }; 446 447 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 448 .cmd_rcgr = 0x19020, 449 .mnd_width = 0, 450 .hid_width = 5, 451 .parent_map = gcc_parent_map_1, 452 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 453 .clkr.hw.init = &(struct clk_init_data){ 454 .name = "blsp1_qup1_i2c_apps_clk_src", 455 .parent_names = gcc_parent_names_1, 456 .num_parents = 3, 457 .ops = &clk_rcg2_ops, 458 }, 459 }; 460 461 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { 462 F(960000, P_XO, 10, 1, 2), 463 F(4800000, P_XO, 4, 0, 0), 464 F(9600000, P_XO, 2, 0, 0), 465 F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4), 466 F(19200000, P_XO, 1, 0, 0), 467 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 468 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 469 { } 470 }; 471 472 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 473 .cmd_rcgr = 0x1900c, 474 .mnd_width = 8, 475 .hid_width = 5, 476 .parent_map = gcc_parent_map_0, 477 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 478 .clkr.hw.init = &(struct clk_init_data){ 479 .name = "blsp1_qup1_spi_apps_clk_src", 480 .parent_names = gcc_parent_names_0, 481 .num_parents = 4, 482 .ops = &clk_rcg2_ops, 483 }, 484 }; 485 486 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 487 .cmd_rcgr = 0x1b020, 488 .mnd_width = 0, 489 .hid_width = 5, 490 .parent_map = gcc_parent_map_1, 491 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 492 .clkr.hw.init = &(struct clk_init_data){ 493 .name = "blsp1_qup2_i2c_apps_clk_src", 494 .parent_names = gcc_parent_names_1, 495 .num_parents = 3, 496 .ops = &clk_rcg2_ops, 497 }, 498 }; 499 500 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 501 .cmd_rcgr = 0x1b00c, 502 .mnd_width = 8, 503 .hid_width = 5, 504 .parent_map = gcc_parent_map_0, 505 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 506 .clkr.hw.init = &(struct clk_init_data){ 507 .name = "blsp1_qup2_spi_apps_clk_src", 508 .parent_names = gcc_parent_names_0, 509 .num_parents = 4, 510 .ops = &clk_rcg2_ops, 511 }, 512 }; 513 514 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 515 .cmd_rcgr = 0x1d020, 516 .mnd_width = 0, 517 .hid_width = 5, 518 .parent_map = gcc_parent_map_1, 519 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 520 .clkr.hw.init = &(struct clk_init_data){ 521 .name = "blsp1_qup3_i2c_apps_clk_src", 522 .parent_names = gcc_parent_names_1, 523 .num_parents = 3, 524 .ops = &clk_rcg2_ops, 525 }, 526 }; 527 528 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 529 .cmd_rcgr = 0x1d00c, 530 .mnd_width = 8, 531 .hid_width = 5, 532 .parent_map = gcc_parent_map_0, 533 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 534 .clkr.hw.init = &(struct clk_init_data){ 535 .name = "blsp1_qup3_spi_apps_clk_src", 536 .parent_names = gcc_parent_names_0, 537 .num_parents = 4, 538 .ops = &clk_rcg2_ops, 539 }, 540 }; 541 542 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 543 .cmd_rcgr = 0x1f020, 544 .mnd_width = 0, 545 .hid_width = 5, 546 .parent_map = gcc_parent_map_1, 547 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 548 .clkr.hw.init = &(struct clk_init_data){ 549 .name = "blsp1_qup4_i2c_apps_clk_src", 550 .parent_names = gcc_parent_names_1, 551 .num_parents = 3, 552 .ops = &clk_rcg2_ops, 553 }, 554 }; 555 556 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 557 .cmd_rcgr = 0x1f00c, 558 .mnd_width = 8, 559 .hid_width = 5, 560 .parent_map = gcc_parent_map_0, 561 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 562 .clkr.hw.init = &(struct clk_init_data){ 563 .name = "blsp1_qup4_spi_apps_clk_src", 564 .parent_names = gcc_parent_names_0, 565 .num_parents = 4, 566 .ops = &clk_rcg2_ops, 567 }, 568 }; 569 570 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 571 .cmd_rcgr = 0x21020, 572 .mnd_width = 0, 573 .hid_width = 5, 574 .parent_map = gcc_parent_map_1, 575 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 576 .clkr.hw.init = &(struct clk_init_data){ 577 .name = "blsp1_qup5_i2c_apps_clk_src", 578 .parent_names = gcc_parent_names_1, 579 .num_parents = 3, 580 .ops = &clk_rcg2_ops, 581 }, 582 }; 583 584 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 585 .cmd_rcgr = 0x2100c, 586 .mnd_width = 8, 587 .hid_width = 5, 588 .parent_map = gcc_parent_map_0, 589 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 590 .clkr.hw.init = &(struct clk_init_data){ 591 .name = "blsp1_qup5_spi_apps_clk_src", 592 .parent_names = gcc_parent_names_0, 593 .num_parents = 4, 594 .ops = &clk_rcg2_ops, 595 }, 596 }; 597 598 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 599 .cmd_rcgr = 0x23020, 600 .mnd_width = 0, 601 .hid_width = 5, 602 .parent_map = gcc_parent_map_1, 603 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 604 .clkr.hw.init = &(struct clk_init_data){ 605 .name = "blsp1_qup6_i2c_apps_clk_src", 606 .parent_names = gcc_parent_names_1, 607 .num_parents = 3, 608 .ops = &clk_rcg2_ops, 609 }, 610 }; 611 612 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 613 .cmd_rcgr = 0x2300c, 614 .mnd_width = 8, 615 .hid_width = 5, 616 .parent_map = gcc_parent_map_0, 617 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 618 .clkr.hw.init = &(struct clk_init_data){ 619 .name = "blsp1_qup6_spi_apps_clk_src", 620 .parent_names = gcc_parent_names_0, 621 .num_parents = 4, 622 .ops = &clk_rcg2_ops, 623 }, 624 }; 625 626 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = { 627 F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625), 628 F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625), 629 F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625), 630 F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15), 631 F(19200000, P_XO, 1, 0, 0), 632 F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5), 633 F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75), 634 F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0), 635 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375), 636 F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), 637 F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375), 638 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75), 639 F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625), 640 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 641 F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0), 642 { } 643 }; 644 645 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 646 .cmd_rcgr = 0x1a00c, 647 .mnd_width = 16, 648 .hid_width = 5, 649 .parent_map = gcc_parent_map_0, 650 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 651 .clkr.hw.init = &(struct clk_init_data){ 652 .name = "blsp1_uart1_apps_clk_src", 653 .parent_names = gcc_parent_names_0, 654 .num_parents = 4, 655 .ops = &clk_rcg2_ops, 656 }, 657 }; 658 659 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 660 .cmd_rcgr = 0x1c00c, 661 .mnd_width = 16, 662 .hid_width = 5, 663 .parent_map = gcc_parent_map_0, 664 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 665 .clkr.hw.init = &(struct clk_init_data){ 666 .name = "blsp1_uart2_apps_clk_src", 667 .parent_names = gcc_parent_names_0, 668 .num_parents = 4, 669 .ops = &clk_rcg2_ops, 670 }, 671 }; 672 673 static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 674 .cmd_rcgr = 0x1e00c, 675 .mnd_width = 16, 676 .hid_width = 5, 677 .parent_map = gcc_parent_map_0, 678 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 679 .clkr.hw.init = &(struct clk_init_data){ 680 .name = "blsp1_uart3_apps_clk_src", 681 .parent_names = gcc_parent_names_0, 682 .num_parents = 4, 683 .ops = &clk_rcg2_ops, 684 }, 685 }; 686 687 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { 688 .cmd_rcgr = 0x26020, 689 .mnd_width = 0, 690 .hid_width = 5, 691 .parent_map = gcc_parent_map_1, 692 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 693 .clkr.hw.init = &(struct clk_init_data){ 694 .name = "blsp2_qup1_i2c_apps_clk_src", 695 .parent_names = gcc_parent_names_1, 696 .num_parents = 3, 697 .ops = &clk_rcg2_ops, 698 }, 699 }; 700 701 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { 702 .cmd_rcgr = 0x2600c, 703 .mnd_width = 8, 704 .hid_width = 5, 705 .parent_map = gcc_parent_map_0, 706 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 707 .clkr.hw.init = &(struct clk_init_data){ 708 .name = "blsp2_qup1_spi_apps_clk_src", 709 .parent_names = gcc_parent_names_0, 710 .num_parents = 4, 711 .ops = &clk_rcg2_ops, 712 }, 713 }; 714 715 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { 716 .cmd_rcgr = 0x28020, 717 .mnd_width = 0, 718 .hid_width = 5, 719 .parent_map = gcc_parent_map_1, 720 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 721 .clkr.hw.init = &(struct clk_init_data){ 722 .name = "blsp2_qup2_i2c_apps_clk_src", 723 .parent_names = gcc_parent_names_1, 724 .num_parents = 3, 725 .ops = &clk_rcg2_ops, 726 }, 727 }; 728 729 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { 730 .cmd_rcgr = 0x2800c, 731 .mnd_width = 8, 732 .hid_width = 5, 733 .parent_map = gcc_parent_map_0, 734 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 735 .clkr.hw.init = &(struct clk_init_data){ 736 .name = "blsp2_qup2_spi_apps_clk_src", 737 .parent_names = gcc_parent_names_0, 738 .num_parents = 4, 739 .ops = &clk_rcg2_ops, 740 }, 741 }; 742 743 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { 744 .cmd_rcgr = 0x2a020, 745 .mnd_width = 0, 746 .hid_width = 5, 747 .parent_map = gcc_parent_map_1, 748 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 749 .clkr.hw.init = &(struct clk_init_data){ 750 .name = "blsp2_qup3_i2c_apps_clk_src", 751 .parent_names = gcc_parent_names_1, 752 .num_parents = 3, 753 .ops = &clk_rcg2_ops, 754 }, 755 }; 756 757 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { 758 .cmd_rcgr = 0x2a00c, 759 .mnd_width = 8, 760 .hid_width = 5, 761 .parent_map = gcc_parent_map_0, 762 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 763 .clkr.hw.init = &(struct clk_init_data){ 764 .name = "blsp2_qup3_spi_apps_clk_src", 765 .parent_names = gcc_parent_names_0, 766 .num_parents = 4, 767 .ops = &clk_rcg2_ops, 768 }, 769 }; 770 771 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { 772 .cmd_rcgr = 0x2c020, 773 .mnd_width = 0, 774 .hid_width = 5, 775 .parent_map = gcc_parent_map_1, 776 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 777 .clkr.hw.init = &(struct clk_init_data){ 778 .name = "blsp2_qup4_i2c_apps_clk_src", 779 .parent_names = gcc_parent_names_1, 780 .num_parents = 3, 781 .ops = &clk_rcg2_ops, 782 }, 783 }; 784 785 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { 786 .cmd_rcgr = 0x2c00c, 787 .mnd_width = 8, 788 .hid_width = 5, 789 .parent_map = gcc_parent_map_0, 790 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 791 .clkr.hw.init = &(struct clk_init_data){ 792 .name = "blsp2_qup4_spi_apps_clk_src", 793 .parent_names = gcc_parent_names_0, 794 .num_parents = 4, 795 .ops = &clk_rcg2_ops, 796 }, 797 }; 798 799 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { 800 .cmd_rcgr = 0x2e020, 801 .mnd_width = 0, 802 .hid_width = 5, 803 .parent_map = gcc_parent_map_1, 804 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 805 .clkr.hw.init = &(struct clk_init_data){ 806 .name = "blsp2_qup5_i2c_apps_clk_src", 807 .parent_names = gcc_parent_names_1, 808 .num_parents = 3, 809 .ops = &clk_rcg2_ops, 810 }, 811 }; 812 813 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { 814 .cmd_rcgr = 0x2e00c, 815 .mnd_width = 8, 816 .hid_width = 5, 817 .parent_map = gcc_parent_map_0, 818 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 819 .clkr.hw.init = &(struct clk_init_data){ 820 .name = "blsp2_qup5_spi_apps_clk_src", 821 .parent_names = gcc_parent_names_0, 822 .num_parents = 4, 823 .ops = &clk_rcg2_ops, 824 }, 825 }; 826 827 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { 828 .cmd_rcgr = 0x30020, 829 .mnd_width = 0, 830 .hid_width = 5, 831 .parent_map = gcc_parent_map_1, 832 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 833 .clkr.hw.init = &(struct clk_init_data){ 834 .name = "blsp2_qup6_i2c_apps_clk_src", 835 .parent_names = gcc_parent_names_1, 836 .num_parents = 3, 837 .ops = &clk_rcg2_ops, 838 }, 839 }; 840 841 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { 842 .cmd_rcgr = 0x3000c, 843 .mnd_width = 8, 844 .hid_width = 5, 845 .parent_map = gcc_parent_map_0, 846 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 847 .clkr.hw.init = &(struct clk_init_data){ 848 .name = "blsp2_qup6_spi_apps_clk_src", 849 .parent_names = gcc_parent_names_0, 850 .num_parents = 4, 851 .ops = &clk_rcg2_ops, 852 }, 853 }; 854 855 static struct clk_rcg2 blsp2_uart1_apps_clk_src = { 856 .cmd_rcgr = 0x2700c, 857 .mnd_width = 16, 858 .hid_width = 5, 859 .parent_map = gcc_parent_map_0, 860 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 861 .clkr.hw.init = &(struct clk_init_data){ 862 .name = "blsp2_uart1_apps_clk_src", 863 .parent_names = gcc_parent_names_0, 864 .num_parents = 4, 865 .ops = &clk_rcg2_ops, 866 }, 867 }; 868 869 static struct clk_rcg2 blsp2_uart2_apps_clk_src = { 870 .cmd_rcgr = 0x2900c, 871 .mnd_width = 16, 872 .hid_width = 5, 873 .parent_map = gcc_parent_map_0, 874 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 875 .clkr.hw.init = &(struct clk_init_data){ 876 .name = "blsp2_uart2_apps_clk_src", 877 .parent_names = gcc_parent_names_0, 878 .num_parents = 4, 879 .ops = &clk_rcg2_ops, 880 }, 881 }; 882 883 static struct clk_rcg2 blsp2_uart3_apps_clk_src = { 884 .cmd_rcgr = 0x2b00c, 885 .mnd_width = 16, 886 .hid_width = 5, 887 .parent_map = gcc_parent_map_0, 888 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 889 .clkr.hw.init = &(struct clk_init_data){ 890 .name = "blsp2_uart3_apps_clk_src", 891 .parent_names = gcc_parent_names_0, 892 .num_parents = 4, 893 .ops = &clk_rcg2_ops, 894 }, 895 }; 896 897 static const struct freq_tbl ftbl_gp1_clk_src[] = { 898 F(19200000, P_XO, 1, 0, 0), 899 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 900 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 901 { } 902 }; 903 904 static struct clk_rcg2 gp1_clk_src = { 905 .cmd_rcgr = 0x64004, 906 .mnd_width = 8, 907 .hid_width = 5, 908 .parent_map = gcc_parent_map_2, 909 .freq_tbl = ftbl_gp1_clk_src, 910 .clkr.hw.init = &(struct clk_init_data){ 911 .name = "gp1_clk_src", 912 .parent_names = gcc_parent_names_2, 913 .num_parents = 5, 914 .ops = &clk_rcg2_ops, 915 }, 916 }; 917 918 static struct clk_rcg2 gp2_clk_src = { 919 .cmd_rcgr = 0x65004, 920 .mnd_width = 8, 921 .hid_width = 5, 922 .parent_map = gcc_parent_map_2, 923 .freq_tbl = ftbl_gp1_clk_src, 924 .clkr.hw.init = &(struct clk_init_data){ 925 .name = "gp2_clk_src", 926 .parent_names = gcc_parent_names_2, 927 .num_parents = 5, 928 .ops = &clk_rcg2_ops, 929 }, 930 }; 931 932 static struct clk_rcg2 gp3_clk_src = { 933 .cmd_rcgr = 0x66004, 934 .mnd_width = 8, 935 .hid_width = 5, 936 .parent_map = gcc_parent_map_2, 937 .freq_tbl = ftbl_gp1_clk_src, 938 .clkr.hw.init = &(struct clk_init_data){ 939 .name = "gp3_clk_src", 940 .parent_names = gcc_parent_names_2, 941 .num_parents = 5, 942 .ops = &clk_rcg2_ops, 943 }, 944 }; 945 946 static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = { 947 F(19200000, P_XO, 1, 0, 0), 948 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), 949 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 950 { } 951 }; 952 953 static struct clk_rcg2 hmss_ahb_clk_src = { 954 .cmd_rcgr = 0x48014, 955 .mnd_width = 0, 956 .hid_width = 5, 957 .parent_map = gcc_parent_map_1, 958 .freq_tbl = ftbl_hmss_ahb_clk_src, 959 .clkr.hw.init = &(struct clk_init_data){ 960 .name = "hmss_ahb_clk_src", 961 .parent_names = gcc_parent_names_1, 962 .num_parents = 3, 963 .ops = &clk_rcg2_ops, 964 }, 965 }; 966 967 static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { 968 F(19200000, P_XO, 1, 0, 0), 969 { } 970 }; 971 972 static struct clk_rcg2 hmss_rbcpr_clk_src = { 973 .cmd_rcgr = 0x48044, 974 .mnd_width = 0, 975 .hid_width = 5, 976 .parent_map = gcc_parent_map_1, 977 .freq_tbl = ftbl_hmss_rbcpr_clk_src, 978 .clkr.hw.init = &(struct clk_init_data){ 979 .name = "hmss_rbcpr_clk_src", 980 .parent_names = gcc_parent_names_1, 981 .num_parents = 3, 982 .ops = &clk_rcg2_ops, 983 }, 984 }; 985 986 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = { 987 F(1010526, P_XO, 1, 1, 19), 988 { } 989 }; 990 991 static struct clk_rcg2 pcie_aux_clk_src = { 992 .cmd_rcgr = 0x6c000, 993 .mnd_width = 16, 994 .hid_width = 5, 995 .parent_map = gcc_parent_map_3, 996 .freq_tbl = ftbl_pcie_aux_clk_src, 997 .clkr.hw.init = &(struct clk_init_data){ 998 .name = "pcie_aux_clk_src", 999 .parent_names = gcc_parent_names_3, 1000 .num_parents = 3, 1001 .ops = &clk_rcg2_ops, 1002 }, 1003 }; 1004 1005 static const struct freq_tbl ftbl_pdm2_clk_src[] = { 1006 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 1007 { } 1008 }; 1009 1010 static struct clk_rcg2 pdm2_clk_src = { 1011 .cmd_rcgr = 0x33010, 1012 .mnd_width = 0, 1013 .hid_width = 5, 1014 .parent_map = gcc_parent_map_1, 1015 .freq_tbl = ftbl_pdm2_clk_src, 1016 .clkr.hw.init = &(struct clk_init_data){ 1017 .name = "pdm2_clk_src", 1018 .parent_names = gcc_parent_names_1, 1019 .num_parents = 3, 1020 .ops = &clk_rcg2_ops, 1021 }, 1022 }; 1023 1024 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = { 1025 F(144000, P_XO, 16, 3, 25), 1026 F(400000, P_XO, 12, 1, 4), 1027 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2), 1028 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 1029 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 1030 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 1031 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 1032 { } 1033 }; 1034 1035 static struct clk_rcg2 sdcc2_apps_clk_src = { 1036 .cmd_rcgr = 0x14010, 1037 .mnd_width = 8, 1038 .hid_width = 5, 1039 .parent_map = gcc_parent_map_4, 1040 .freq_tbl = ftbl_sdcc2_apps_clk_src, 1041 .clkr.hw.init = &(struct clk_init_data){ 1042 .name = "sdcc2_apps_clk_src", 1043 .parent_names = gcc_parent_names_4, 1044 .num_parents = 4, 1045 .ops = &clk_rcg2_floor_ops, 1046 }, 1047 }; 1048 1049 static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = { 1050 F(144000, P_XO, 16, 3, 25), 1051 F(400000, P_XO, 12, 1, 4), 1052 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2), 1053 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 1054 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 1055 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 1056 { } 1057 }; 1058 1059 static struct clk_rcg2 sdcc4_apps_clk_src = { 1060 .cmd_rcgr = 0x16010, 1061 .mnd_width = 8, 1062 .hid_width = 5, 1063 .parent_map = gcc_parent_map_1, 1064 .freq_tbl = ftbl_sdcc4_apps_clk_src, 1065 .clkr.hw.init = &(struct clk_init_data){ 1066 .name = "sdcc4_apps_clk_src", 1067 .parent_names = gcc_parent_names_1, 1068 .num_parents = 3, 1069 .ops = &clk_rcg2_floor_ops, 1070 }, 1071 }; 1072 1073 static const struct freq_tbl ftbl_tsif_ref_clk_src[] = { 1074 F(105495, P_XO, 1, 1, 182), 1075 { } 1076 }; 1077 1078 static struct clk_rcg2 tsif_ref_clk_src = { 1079 .cmd_rcgr = 0x36010, 1080 .mnd_width = 8, 1081 .hid_width = 5, 1082 .parent_map = gcc_parent_map_5, 1083 .freq_tbl = ftbl_tsif_ref_clk_src, 1084 .clkr.hw.init = &(struct clk_init_data){ 1085 .name = "tsif_ref_clk_src", 1086 .parent_names = gcc_parent_names_5, 1087 .num_parents = 4, 1088 .ops = &clk_rcg2_ops, 1089 }, 1090 }; 1091 1092 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = { 1093 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 1094 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 1095 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 1096 { } 1097 }; 1098 1099 static struct clk_rcg2 ufs_axi_clk_src = { 1100 .cmd_rcgr = 0x75018, 1101 .mnd_width = 8, 1102 .hid_width = 5, 1103 .parent_map = gcc_parent_map_0, 1104 .freq_tbl = ftbl_ufs_axi_clk_src, 1105 .clkr.hw.init = &(struct clk_init_data){ 1106 .name = "ufs_axi_clk_src", 1107 .parent_names = gcc_parent_names_0, 1108 .num_parents = 4, 1109 .ops = &clk_rcg2_ops, 1110 }, 1111 }; 1112 1113 static const struct freq_tbl ftbl_usb30_master_clk_src[] = { 1114 F(19200000, P_XO, 1, 0, 0), 1115 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 1116 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), 1117 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 1118 { } 1119 }; 1120 1121 static struct clk_rcg2 usb30_master_clk_src = { 1122 .cmd_rcgr = 0xf014, 1123 .mnd_width = 8, 1124 .hid_width = 5, 1125 .parent_map = gcc_parent_map_0, 1126 .freq_tbl = ftbl_usb30_master_clk_src, 1127 .clkr.hw.init = &(struct clk_init_data){ 1128 .name = "usb30_master_clk_src", 1129 .parent_names = gcc_parent_names_0, 1130 .num_parents = 4, 1131 .ops = &clk_rcg2_ops, 1132 }, 1133 }; 1134 1135 static struct clk_rcg2 usb30_mock_utmi_clk_src = { 1136 .cmd_rcgr = 0xf028, 1137 .mnd_width = 0, 1138 .hid_width = 5, 1139 .parent_map = gcc_parent_map_0, 1140 .freq_tbl = ftbl_hmss_rbcpr_clk_src, 1141 .clkr.hw.init = &(struct clk_init_data){ 1142 .name = "usb30_mock_utmi_clk_src", 1143 .parent_names = gcc_parent_names_0, 1144 .num_parents = 4, 1145 .ops = &clk_rcg2_ops, 1146 }, 1147 }; 1148 1149 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { 1150 F(1200000, P_XO, 16, 0, 0), 1151 { } 1152 }; 1153 1154 static struct clk_rcg2 usb3_phy_aux_clk_src = { 1155 .cmd_rcgr = 0x5000c, 1156 .mnd_width = 0, 1157 .hid_width = 5, 1158 .parent_map = gcc_parent_map_3, 1159 .freq_tbl = ftbl_usb3_phy_aux_clk_src, 1160 .clkr.hw.init = &(struct clk_init_data){ 1161 .name = "usb3_phy_aux_clk_src", 1162 .parent_names = gcc_parent_names_3, 1163 .num_parents = 3, 1164 .ops = &clk_rcg2_ops, 1165 }, 1166 }; 1167 1168 static struct clk_branch gcc_aggre1_noc_xo_clk = { 1169 .halt_reg = 0x8202c, 1170 .halt_check = BRANCH_HALT, 1171 .clkr = { 1172 .enable_reg = 0x8202c, 1173 .enable_mask = BIT(0), 1174 .hw.init = &(struct clk_init_data){ 1175 .name = "gcc_aggre1_noc_xo_clk", 1176 .ops = &clk_branch2_ops, 1177 }, 1178 }, 1179 }; 1180 1181 static struct clk_branch gcc_aggre1_ufs_axi_clk = { 1182 .halt_reg = 0x82028, 1183 .halt_check = BRANCH_HALT, 1184 .clkr = { 1185 .enable_reg = 0x82028, 1186 .enable_mask = BIT(0), 1187 .hw.init = &(struct clk_init_data){ 1188 .name = "gcc_aggre1_ufs_axi_clk", 1189 .parent_names = (const char *[]){ 1190 "ufs_axi_clk_src", 1191 }, 1192 .num_parents = 1, 1193 .flags = CLK_SET_RATE_PARENT, 1194 .ops = &clk_branch2_ops, 1195 }, 1196 }, 1197 }; 1198 1199 static struct clk_branch gcc_aggre1_usb3_axi_clk = { 1200 .halt_reg = 0x82024, 1201 .halt_check = BRANCH_HALT, 1202 .clkr = { 1203 .enable_reg = 0x82024, 1204 .enable_mask = BIT(0), 1205 .hw.init = &(struct clk_init_data){ 1206 .name = "gcc_aggre1_usb3_axi_clk", 1207 .parent_names = (const char *[]){ 1208 "usb30_master_clk_src", 1209 }, 1210 .num_parents = 1, 1211 .flags = CLK_SET_RATE_PARENT, 1212 .ops = &clk_branch2_ops, 1213 }, 1214 }, 1215 }; 1216 1217 static struct clk_branch gcc_apss_qdss_tsctr_div2_clk = { 1218 .halt_reg = 0x48090, 1219 .halt_check = BRANCH_HALT, 1220 .clkr = { 1221 .enable_reg = 0x48090, 1222 .enable_mask = BIT(0), 1223 .hw.init = &(struct clk_init_data){ 1224 .name = "gcc_apss_qdss_tsctr_div2_clk", 1225 .ops = &clk_branch2_ops, 1226 }, 1227 }, 1228 }; 1229 1230 static struct clk_branch gcc_apss_qdss_tsctr_div8_clk = { 1231 .halt_reg = 0x48094, 1232 .halt_check = BRANCH_HALT, 1233 .clkr = { 1234 .enable_reg = 0x48094, 1235 .enable_mask = BIT(0), 1236 .hw.init = &(struct clk_init_data){ 1237 .name = "gcc_apss_qdss_tsctr_div8_clk", 1238 .ops = &clk_branch2_ops, 1239 }, 1240 }, 1241 }; 1242 1243 static struct clk_branch gcc_bimc_hmss_axi_clk = { 1244 .halt_reg = 0x48004, 1245 .halt_check = BRANCH_HALT_VOTED, 1246 .clkr = { 1247 .enable_reg = 0x52004, 1248 .enable_mask = BIT(22), 1249 .hw.init = &(struct clk_init_data){ 1250 .name = "gcc_bimc_hmss_axi_clk", 1251 .ops = &clk_branch2_ops, 1252 }, 1253 }, 1254 }; 1255 1256 static struct clk_branch gcc_bimc_mss_q6_axi_clk = { 1257 .halt_reg = 0x4401c, 1258 .halt_check = BRANCH_HALT, 1259 .clkr = { 1260 .enable_reg = 0x4401c, 1261 .enable_mask = BIT(0), 1262 .hw.init = &(struct clk_init_data){ 1263 .name = "gcc_bimc_mss_q6_axi_clk", 1264 .ops = &clk_branch2_ops, 1265 }, 1266 }, 1267 }; 1268 1269 static struct clk_branch gcc_blsp1_ahb_clk = { 1270 .halt_reg = 0x17004, 1271 .halt_check = BRANCH_HALT_VOTED, 1272 .clkr = { 1273 .enable_reg = 0x52004, 1274 .enable_mask = BIT(17), 1275 .hw.init = &(struct clk_init_data){ 1276 .name = "gcc_blsp1_ahb_clk", 1277 .ops = &clk_branch2_ops, 1278 }, 1279 }, 1280 }; 1281 1282 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1283 .halt_reg = 0x19008, 1284 .halt_check = BRANCH_HALT, 1285 .clkr = { 1286 .enable_reg = 0x19008, 1287 .enable_mask = BIT(0), 1288 .hw.init = &(struct clk_init_data){ 1289 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1290 .parent_names = (const char *[]){ 1291 "blsp1_qup1_i2c_apps_clk_src", 1292 }, 1293 .num_parents = 1, 1294 .flags = CLK_SET_RATE_PARENT, 1295 .ops = &clk_branch2_ops, 1296 }, 1297 }, 1298 }; 1299 1300 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1301 .halt_reg = 0x19004, 1302 .halt_check = BRANCH_HALT, 1303 .clkr = { 1304 .enable_reg = 0x19004, 1305 .enable_mask = BIT(0), 1306 .hw.init = &(struct clk_init_data){ 1307 .name = "gcc_blsp1_qup1_spi_apps_clk", 1308 .parent_names = (const char *[]){ 1309 "blsp1_qup1_spi_apps_clk_src", 1310 }, 1311 .num_parents = 1, 1312 .flags = CLK_SET_RATE_PARENT, 1313 .ops = &clk_branch2_ops, 1314 }, 1315 }, 1316 }; 1317 1318 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1319 .halt_reg = 0x1b008, 1320 .halt_check = BRANCH_HALT, 1321 .clkr = { 1322 .enable_reg = 0x1b008, 1323 .enable_mask = BIT(0), 1324 .hw.init = &(struct clk_init_data){ 1325 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1326 .parent_names = (const char *[]){ 1327 "blsp1_qup2_i2c_apps_clk_src", 1328 }, 1329 .num_parents = 1, 1330 .flags = CLK_SET_RATE_PARENT, 1331 .ops = &clk_branch2_ops, 1332 }, 1333 }, 1334 }; 1335 1336 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1337 .halt_reg = 0x1b004, 1338 .halt_check = BRANCH_HALT, 1339 .clkr = { 1340 .enable_reg = 0x1b004, 1341 .enable_mask = BIT(0), 1342 .hw.init = &(struct clk_init_data){ 1343 .name = "gcc_blsp1_qup2_spi_apps_clk", 1344 .parent_names = (const char *[]){ 1345 "blsp1_qup2_spi_apps_clk_src", 1346 }, 1347 .num_parents = 1, 1348 .flags = CLK_SET_RATE_PARENT, 1349 .ops = &clk_branch2_ops, 1350 }, 1351 }, 1352 }; 1353 1354 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1355 .halt_reg = 0x1d008, 1356 .halt_check = BRANCH_HALT, 1357 .clkr = { 1358 .enable_reg = 0x1d008, 1359 .enable_mask = BIT(0), 1360 .hw.init = &(struct clk_init_data){ 1361 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1362 .parent_names = (const char *[]){ 1363 "blsp1_qup3_i2c_apps_clk_src", 1364 }, 1365 .num_parents = 1, 1366 .flags = CLK_SET_RATE_PARENT, 1367 .ops = &clk_branch2_ops, 1368 }, 1369 }, 1370 }; 1371 1372 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1373 .halt_reg = 0x1d004, 1374 .halt_check = BRANCH_HALT, 1375 .clkr = { 1376 .enable_reg = 0x1d004, 1377 .enable_mask = BIT(0), 1378 .hw.init = &(struct clk_init_data){ 1379 .name = "gcc_blsp1_qup3_spi_apps_clk", 1380 .parent_names = (const char *[]){ 1381 "blsp1_qup3_spi_apps_clk_src", 1382 }, 1383 .num_parents = 1, 1384 .flags = CLK_SET_RATE_PARENT, 1385 .ops = &clk_branch2_ops, 1386 }, 1387 }, 1388 }; 1389 1390 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1391 .halt_reg = 0x1f008, 1392 .halt_check = BRANCH_HALT, 1393 .clkr = { 1394 .enable_reg = 0x1f008, 1395 .enable_mask = BIT(0), 1396 .hw.init = &(struct clk_init_data){ 1397 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1398 .parent_names = (const char *[]){ 1399 "blsp1_qup4_i2c_apps_clk_src", 1400 }, 1401 .num_parents = 1, 1402 .flags = CLK_SET_RATE_PARENT, 1403 .ops = &clk_branch2_ops, 1404 }, 1405 }, 1406 }; 1407 1408 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1409 .halt_reg = 0x1f004, 1410 .halt_check = BRANCH_HALT, 1411 .clkr = { 1412 .enable_reg = 0x1f004, 1413 .enable_mask = BIT(0), 1414 .hw.init = &(struct clk_init_data){ 1415 .name = "gcc_blsp1_qup4_spi_apps_clk", 1416 .parent_names = (const char *[]){ 1417 "blsp1_qup4_spi_apps_clk_src", 1418 }, 1419 .num_parents = 1, 1420 .flags = CLK_SET_RATE_PARENT, 1421 .ops = &clk_branch2_ops, 1422 }, 1423 }, 1424 }; 1425 1426 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1427 .halt_reg = 0x21008, 1428 .halt_check = BRANCH_HALT, 1429 .clkr = { 1430 .enable_reg = 0x21008, 1431 .enable_mask = BIT(0), 1432 .hw.init = &(struct clk_init_data){ 1433 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1434 .parent_names = (const char *[]){ 1435 "blsp1_qup5_i2c_apps_clk_src", 1436 }, 1437 .num_parents = 1, 1438 .flags = CLK_SET_RATE_PARENT, 1439 .ops = &clk_branch2_ops, 1440 }, 1441 }, 1442 }; 1443 1444 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1445 .halt_reg = 0x21004, 1446 .halt_check = BRANCH_HALT, 1447 .clkr = { 1448 .enable_reg = 0x21004, 1449 .enable_mask = BIT(0), 1450 .hw.init = &(struct clk_init_data){ 1451 .name = "gcc_blsp1_qup5_spi_apps_clk", 1452 .parent_names = (const char *[]){ 1453 "blsp1_qup5_spi_apps_clk_src", 1454 }, 1455 .num_parents = 1, 1456 .flags = CLK_SET_RATE_PARENT, 1457 .ops = &clk_branch2_ops, 1458 }, 1459 }, 1460 }; 1461 1462 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1463 .halt_reg = 0x23008, 1464 .halt_check = BRANCH_HALT, 1465 .clkr = { 1466 .enable_reg = 0x23008, 1467 .enable_mask = BIT(0), 1468 .hw.init = &(struct clk_init_data){ 1469 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1470 .parent_names = (const char *[]){ 1471 "blsp1_qup6_i2c_apps_clk_src", 1472 }, 1473 .num_parents = 1, 1474 .flags = CLK_SET_RATE_PARENT, 1475 .ops = &clk_branch2_ops, 1476 }, 1477 }, 1478 }; 1479 1480 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1481 .halt_reg = 0x23004, 1482 .halt_check = BRANCH_HALT, 1483 .clkr = { 1484 .enable_reg = 0x23004, 1485 .enable_mask = BIT(0), 1486 .hw.init = &(struct clk_init_data){ 1487 .name = "gcc_blsp1_qup6_spi_apps_clk", 1488 .parent_names = (const char *[]){ 1489 "blsp1_qup6_spi_apps_clk_src", 1490 }, 1491 .num_parents = 1, 1492 .flags = CLK_SET_RATE_PARENT, 1493 .ops = &clk_branch2_ops, 1494 }, 1495 }, 1496 }; 1497 1498 static struct clk_branch gcc_blsp1_sleep_clk = { 1499 .halt_reg = 0x17008, 1500 .halt_check = BRANCH_HALT_VOTED, 1501 .clkr = { 1502 .enable_reg = 0x52004, 1503 .enable_mask = BIT(16), 1504 .hw.init = &(struct clk_init_data){ 1505 .name = "gcc_blsp1_sleep_clk", 1506 .ops = &clk_branch2_ops, 1507 }, 1508 }, 1509 }; 1510 1511 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1512 .halt_reg = 0x1a004, 1513 .halt_check = BRANCH_HALT, 1514 .clkr = { 1515 .enable_reg = 0x1a004, 1516 .enable_mask = BIT(0), 1517 .hw.init = &(struct clk_init_data){ 1518 .name = "gcc_blsp1_uart1_apps_clk", 1519 .parent_names = (const char *[]){ 1520 "blsp1_uart1_apps_clk_src", 1521 }, 1522 .num_parents = 1, 1523 .flags = CLK_SET_RATE_PARENT, 1524 .ops = &clk_branch2_ops, 1525 }, 1526 }, 1527 }; 1528 1529 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1530 .halt_reg = 0x1c004, 1531 .halt_check = BRANCH_HALT, 1532 .clkr = { 1533 .enable_reg = 0x1c004, 1534 .enable_mask = BIT(0), 1535 .hw.init = &(struct clk_init_data){ 1536 .name = "gcc_blsp1_uart2_apps_clk", 1537 .parent_names = (const char *[]){ 1538 "blsp1_uart2_apps_clk_src", 1539 }, 1540 .num_parents = 1, 1541 .flags = CLK_SET_RATE_PARENT, 1542 .ops = &clk_branch2_ops, 1543 }, 1544 }, 1545 }; 1546 1547 static struct clk_branch gcc_blsp1_uart3_apps_clk = { 1548 .halt_reg = 0x1e004, 1549 .halt_check = BRANCH_HALT, 1550 .clkr = { 1551 .enable_reg = 0x1e004, 1552 .enable_mask = BIT(0), 1553 .hw.init = &(struct clk_init_data){ 1554 .name = "gcc_blsp1_uart3_apps_clk", 1555 .parent_names = (const char *[]){ 1556 "blsp1_uart3_apps_clk_src", 1557 }, 1558 .num_parents = 1, 1559 .flags = CLK_SET_RATE_PARENT, 1560 .ops = &clk_branch2_ops, 1561 }, 1562 }, 1563 }; 1564 1565 static struct clk_branch gcc_blsp2_ahb_clk = { 1566 .halt_reg = 0x25004, 1567 .halt_check = BRANCH_HALT_VOTED, 1568 .clkr = { 1569 .enable_reg = 0x52004, 1570 .enable_mask = BIT(15), 1571 .hw.init = &(struct clk_init_data){ 1572 .name = "gcc_blsp2_ahb_clk", 1573 .ops = &clk_branch2_ops, 1574 }, 1575 }, 1576 }; 1577 1578 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { 1579 .halt_reg = 0x26008, 1580 .halt_check = BRANCH_HALT, 1581 .clkr = { 1582 .enable_reg = 0x26008, 1583 .enable_mask = BIT(0), 1584 .hw.init = &(struct clk_init_data){ 1585 .name = "gcc_blsp2_qup1_i2c_apps_clk", 1586 .parent_names = (const char *[]){ 1587 "blsp2_qup1_i2c_apps_clk_src", 1588 }, 1589 .num_parents = 1, 1590 .flags = CLK_SET_RATE_PARENT, 1591 .ops = &clk_branch2_ops, 1592 }, 1593 }, 1594 }; 1595 1596 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { 1597 .halt_reg = 0x26004, 1598 .halt_check = BRANCH_HALT, 1599 .clkr = { 1600 .enable_reg = 0x26004, 1601 .enable_mask = BIT(0), 1602 .hw.init = &(struct clk_init_data){ 1603 .name = "gcc_blsp2_qup1_spi_apps_clk", 1604 .parent_names = (const char *[]){ 1605 "blsp2_qup1_spi_apps_clk_src", 1606 }, 1607 .num_parents = 1, 1608 .flags = CLK_SET_RATE_PARENT, 1609 .ops = &clk_branch2_ops, 1610 }, 1611 }, 1612 }; 1613 1614 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { 1615 .halt_reg = 0x28008, 1616 .halt_check = BRANCH_HALT, 1617 .clkr = { 1618 .enable_reg = 0x28008, 1619 .enable_mask = BIT(0), 1620 .hw.init = &(struct clk_init_data){ 1621 .name = "gcc_blsp2_qup2_i2c_apps_clk", 1622 .parent_names = (const char *[]){ 1623 "blsp2_qup2_i2c_apps_clk_src", 1624 }, 1625 .num_parents = 1, 1626 .flags = CLK_SET_RATE_PARENT, 1627 .ops = &clk_branch2_ops, 1628 }, 1629 }, 1630 }; 1631 1632 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { 1633 .halt_reg = 0x28004, 1634 .halt_check = BRANCH_HALT, 1635 .clkr = { 1636 .enable_reg = 0x28004, 1637 .enable_mask = BIT(0), 1638 .hw.init = &(struct clk_init_data){ 1639 .name = "gcc_blsp2_qup2_spi_apps_clk", 1640 .parent_names = (const char *[]){ 1641 "blsp2_qup2_spi_apps_clk_src", 1642 }, 1643 .num_parents = 1, 1644 .flags = CLK_SET_RATE_PARENT, 1645 .ops = &clk_branch2_ops, 1646 }, 1647 }, 1648 }; 1649 1650 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { 1651 .halt_reg = 0x2a008, 1652 .halt_check = BRANCH_HALT, 1653 .clkr = { 1654 .enable_reg = 0x2a008, 1655 .enable_mask = BIT(0), 1656 .hw.init = &(struct clk_init_data){ 1657 .name = "gcc_blsp2_qup3_i2c_apps_clk", 1658 .parent_names = (const char *[]){ 1659 "blsp2_qup3_i2c_apps_clk_src", 1660 }, 1661 .num_parents = 1, 1662 .flags = CLK_SET_RATE_PARENT, 1663 .ops = &clk_branch2_ops, 1664 }, 1665 }, 1666 }; 1667 1668 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { 1669 .halt_reg = 0x2a004, 1670 .halt_check = BRANCH_HALT, 1671 .clkr = { 1672 .enable_reg = 0x2a004, 1673 .enable_mask = BIT(0), 1674 .hw.init = &(struct clk_init_data){ 1675 .name = "gcc_blsp2_qup3_spi_apps_clk", 1676 .parent_names = (const char *[]){ 1677 "blsp2_qup3_spi_apps_clk_src", 1678 }, 1679 .num_parents = 1, 1680 .flags = CLK_SET_RATE_PARENT, 1681 .ops = &clk_branch2_ops, 1682 }, 1683 }, 1684 }; 1685 1686 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { 1687 .halt_reg = 0x2c008, 1688 .halt_check = BRANCH_HALT, 1689 .clkr = { 1690 .enable_reg = 0x2c008, 1691 .enable_mask = BIT(0), 1692 .hw.init = &(struct clk_init_data){ 1693 .name = "gcc_blsp2_qup4_i2c_apps_clk", 1694 .parent_names = (const char *[]){ 1695 "blsp2_qup4_i2c_apps_clk_src", 1696 }, 1697 .num_parents = 1, 1698 .flags = CLK_SET_RATE_PARENT, 1699 .ops = &clk_branch2_ops, 1700 }, 1701 }, 1702 }; 1703 1704 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { 1705 .halt_reg = 0x2c004, 1706 .halt_check = BRANCH_HALT, 1707 .clkr = { 1708 .enable_reg = 0x2c004, 1709 .enable_mask = BIT(0), 1710 .hw.init = &(struct clk_init_data){ 1711 .name = "gcc_blsp2_qup4_spi_apps_clk", 1712 .parent_names = (const char *[]){ 1713 "blsp2_qup4_spi_apps_clk_src", 1714 }, 1715 .num_parents = 1, 1716 .flags = CLK_SET_RATE_PARENT, 1717 .ops = &clk_branch2_ops, 1718 }, 1719 }, 1720 }; 1721 1722 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { 1723 .halt_reg = 0x2e008, 1724 .halt_check = BRANCH_HALT, 1725 .clkr = { 1726 .enable_reg = 0x2e008, 1727 .enable_mask = BIT(0), 1728 .hw.init = &(struct clk_init_data){ 1729 .name = "gcc_blsp2_qup5_i2c_apps_clk", 1730 .parent_names = (const char *[]){ 1731 "blsp2_qup5_i2c_apps_clk_src", 1732 }, 1733 .num_parents = 1, 1734 .flags = CLK_SET_RATE_PARENT, 1735 .ops = &clk_branch2_ops, 1736 }, 1737 }, 1738 }; 1739 1740 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { 1741 .halt_reg = 0x2e004, 1742 .halt_check = BRANCH_HALT, 1743 .clkr = { 1744 .enable_reg = 0x2e004, 1745 .enable_mask = BIT(0), 1746 .hw.init = &(struct clk_init_data){ 1747 .name = "gcc_blsp2_qup5_spi_apps_clk", 1748 .parent_names = (const char *[]){ 1749 "blsp2_qup5_spi_apps_clk_src", 1750 }, 1751 .num_parents = 1, 1752 .flags = CLK_SET_RATE_PARENT, 1753 .ops = &clk_branch2_ops, 1754 }, 1755 }, 1756 }; 1757 1758 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { 1759 .halt_reg = 0x30008, 1760 .halt_check = BRANCH_HALT, 1761 .clkr = { 1762 .enable_reg = 0x30008, 1763 .enable_mask = BIT(0), 1764 .hw.init = &(struct clk_init_data){ 1765 .name = "gcc_blsp2_qup6_i2c_apps_clk", 1766 .parent_names = (const char *[]){ 1767 "blsp2_qup6_i2c_apps_clk_src", 1768 }, 1769 .num_parents = 1, 1770 .flags = CLK_SET_RATE_PARENT, 1771 .ops = &clk_branch2_ops, 1772 }, 1773 }, 1774 }; 1775 1776 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { 1777 .halt_reg = 0x30004, 1778 .halt_check = BRANCH_HALT, 1779 .clkr = { 1780 .enable_reg = 0x30004, 1781 .enable_mask = BIT(0), 1782 .hw.init = &(struct clk_init_data){ 1783 .name = "gcc_blsp2_qup6_spi_apps_clk", 1784 .parent_names = (const char *[]){ 1785 "blsp2_qup6_spi_apps_clk_src", 1786 }, 1787 .num_parents = 1, 1788 .flags = CLK_SET_RATE_PARENT, 1789 .ops = &clk_branch2_ops, 1790 }, 1791 }, 1792 }; 1793 1794 static struct clk_branch gcc_blsp2_sleep_clk = { 1795 .halt_reg = 0x25008, 1796 .halt_check = BRANCH_HALT_VOTED, 1797 .clkr = { 1798 .enable_reg = 0x52004, 1799 .enable_mask = BIT(14), 1800 .hw.init = &(struct clk_init_data){ 1801 .name = "gcc_blsp2_sleep_clk", 1802 .ops = &clk_branch2_ops, 1803 }, 1804 }, 1805 }; 1806 1807 static struct clk_branch gcc_blsp2_uart1_apps_clk = { 1808 .halt_reg = 0x27004, 1809 .halt_check = BRANCH_HALT, 1810 .clkr = { 1811 .enable_reg = 0x27004, 1812 .enable_mask = BIT(0), 1813 .hw.init = &(struct clk_init_data){ 1814 .name = "gcc_blsp2_uart1_apps_clk", 1815 .parent_names = (const char *[]){ 1816 "blsp2_uart1_apps_clk_src", 1817 }, 1818 .num_parents = 1, 1819 .flags = CLK_SET_RATE_PARENT, 1820 .ops = &clk_branch2_ops, 1821 }, 1822 }, 1823 }; 1824 1825 static struct clk_branch gcc_blsp2_uart2_apps_clk = { 1826 .halt_reg = 0x29004, 1827 .halt_check = BRANCH_HALT, 1828 .clkr = { 1829 .enable_reg = 0x29004, 1830 .enable_mask = BIT(0), 1831 .hw.init = &(struct clk_init_data){ 1832 .name = "gcc_blsp2_uart2_apps_clk", 1833 .parent_names = (const char *[]){ 1834 "blsp2_uart2_apps_clk_src", 1835 }, 1836 .num_parents = 1, 1837 .flags = CLK_SET_RATE_PARENT, 1838 .ops = &clk_branch2_ops, 1839 }, 1840 }, 1841 }; 1842 1843 static struct clk_branch gcc_blsp2_uart3_apps_clk = { 1844 .halt_reg = 0x2b004, 1845 .halt_check = BRANCH_HALT, 1846 .clkr = { 1847 .enable_reg = 0x2b004, 1848 .enable_mask = BIT(0), 1849 .hw.init = &(struct clk_init_data){ 1850 .name = "gcc_blsp2_uart3_apps_clk", 1851 .parent_names = (const char *[]){ 1852 "blsp2_uart3_apps_clk_src", 1853 }, 1854 .num_parents = 1, 1855 .flags = CLK_SET_RATE_PARENT, 1856 .ops = &clk_branch2_ops, 1857 }, 1858 }, 1859 }; 1860 1861 static struct clk_branch gcc_cfg_noc_usb3_axi_clk = { 1862 .halt_reg = 0x5018, 1863 .halt_check = BRANCH_HALT, 1864 .clkr = { 1865 .enable_reg = 0x5018, 1866 .enable_mask = BIT(0), 1867 .hw.init = &(struct clk_init_data){ 1868 .name = "gcc_cfg_noc_usb3_axi_clk", 1869 .parent_names = (const char *[]){ 1870 "usb30_master_clk_src", 1871 }, 1872 .num_parents = 1, 1873 .flags = CLK_SET_RATE_PARENT, 1874 .ops = &clk_branch2_ops, 1875 }, 1876 }, 1877 }; 1878 1879 static struct clk_branch gcc_gp1_clk = { 1880 .halt_reg = 0x64000, 1881 .halt_check = BRANCH_HALT, 1882 .clkr = { 1883 .enable_reg = 0x64000, 1884 .enable_mask = BIT(0), 1885 .hw.init = &(struct clk_init_data){ 1886 .name = "gcc_gp1_clk", 1887 .parent_names = (const char *[]){ 1888 "gp1_clk_src", 1889 }, 1890 .num_parents = 1, 1891 .flags = CLK_SET_RATE_PARENT, 1892 .ops = &clk_branch2_ops, 1893 }, 1894 }, 1895 }; 1896 1897 static struct clk_branch gcc_gp2_clk = { 1898 .halt_reg = 0x65000, 1899 .halt_check = BRANCH_HALT, 1900 .clkr = { 1901 .enable_reg = 0x65000, 1902 .enable_mask = BIT(0), 1903 .hw.init = &(struct clk_init_data){ 1904 .name = "gcc_gp2_clk", 1905 .parent_names = (const char *[]){ 1906 "gp2_clk_src", 1907 }, 1908 .num_parents = 1, 1909 .flags = CLK_SET_RATE_PARENT, 1910 .ops = &clk_branch2_ops, 1911 }, 1912 }, 1913 }; 1914 1915 static struct clk_branch gcc_gp3_clk = { 1916 .halt_reg = 0x66000, 1917 .halt_check = BRANCH_HALT, 1918 .clkr = { 1919 .enable_reg = 0x66000, 1920 .enable_mask = BIT(0), 1921 .hw.init = &(struct clk_init_data){ 1922 .name = "gcc_gp3_clk", 1923 .parent_names = (const char *[]){ 1924 "gp3_clk_src", 1925 }, 1926 .num_parents = 1, 1927 .flags = CLK_SET_RATE_PARENT, 1928 .ops = &clk_branch2_ops, 1929 }, 1930 }, 1931 }; 1932 1933 static struct clk_branch gcc_gpu_bimc_gfx_clk = { 1934 .halt_reg = 0x71010, 1935 .halt_check = BRANCH_HALT, 1936 .clkr = { 1937 .enable_reg = 0x71010, 1938 .enable_mask = BIT(0), 1939 .hw.init = &(struct clk_init_data){ 1940 .name = "gcc_gpu_bimc_gfx_clk", 1941 .ops = &clk_branch2_ops, 1942 }, 1943 }, 1944 }; 1945 1946 static struct clk_branch gcc_gpu_bimc_gfx_src_clk = { 1947 .halt_reg = 0x7100c, 1948 .halt_check = BRANCH_HALT, 1949 .clkr = { 1950 .enable_reg = 0x7100c, 1951 .enable_mask = BIT(0), 1952 .hw.init = &(struct clk_init_data){ 1953 .name = "gcc_gpu_bimc_gfx_src_clk", 1954 .ops = &clk_branch2_ops, 1955 }, 1956 }, 1957 }; 1958 1959 static struct clk_branch gcc_gpu_cfg_ahb_clk = { 1960 .halt_reg = 0x71004, 1961 .halt_check = BRANCH_HALT, 1962 .clkr = { 1963 .enable_reg = 0x71004, 1964 .enable_mask = BIT(0), 1965 .hw.init = &(struct clk_init_data){ 1966 .name = "gcc_gpu_cfg_ahb_clk", 1967 .ops = &clk_branch2_ops, 1968 }, 1969 }, 1970 }; 1971 1972 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1973 .halt_reg = 0x71018, 1974 .halt_check = BRANCH_HALT, 1975 .clkr = { 1976 .enable_reg = 0x71018, 1977 .enable_mask = BIT(0), 1978 .hw.init = &(struct clk_init_data){ 1979 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1980 .ops = &clk_branch2_ops, 1981 }, 1982 }, 1983 }; 1984 1985 static struct clk_branch gcc_hmss_ahb_clk = { 1986 .halt_reg = 0x48000, 1987 .halt_check = BRANCH_HALT_VOTED, 1988 .clkr = { 1989 .enable_reg = 0x52004, 1990 .enable_mask = BIT(21), 1991 .hw.init = &(struct clk_init_data){ 1992 .name = "gcc_hmss_ahb_clk", 1993 .parent_names = (const char *[]){ 1994 "hmss_ahb_clk_src", 1995 }, 1996 .num_parents = 1, 1997 .flags = CLK_SET_RATE_PARENT, 1998 .ops = &clk_branch2_ops, 1999 }, 2000 }, 2001 }; 2002 2003 static struct clk_branch gcc_hmss_at_clk = { 2004 .halt_reg = 0x48010, 2005 .halt_check = BRANCH_HALT, 2006 .clkr = { 2007 .enable_reg = 0x48010, 2008 .enable_mask = BIT(0), 2009 .hw.init = &(struct clk_init_data){ 2010 .name = "gcc_hmss_at_clk", 2011 .ops = &clk_branch2_ops, 2012 }, 2013 }, 2014 }; 2015 2016 static struct clk_branch gcc_hmss_rbcpr_clk = { 2017 .halt_reg = 0x48008, 2018 .halt_check = BRANCH_HALT, 2019 .clkr = { 2020 .enable_reg = 0x48008, 2021 .enable_mask = BIT(0), 2022 .hw.init = &(struct clk_init_data){ 2023 .name = "gcc_hmss_rbcpr_clk", 2024 .parent_names = (const char *[]){ 2025 "hmss_rbcpr_clk_src", 2026 }, 2027 .num_parents = 1, 2028 .flags = CLK_SET_RATE_PARENT, 2029 .ops = &clk_branch2_ops, 2030 }, 2031 }, 2032 }; 2033 2034 static struct clk_branch gcc_hmss_trig_clk = { 2035 .halt_reg = 0x4800c, 2036 .halt_check = BRANCH_HALT, 2037 .clkr = { 2038 .enable_reg = 0x4800c, 2039 .enable_mask = BIT(0), 2040 .hw.init = &(struct clk_init_data){ 2041 .name = "gcc_hmss_trig_clk", 2042 .ops = &clk_branch2_ops, 2043 }, 2044 }, 2045 }; 2046 2047 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { 2048 .halt_reg = 0x9004, 2049 .halt_check = BRANCH_HALT, 2050 .clkr = { 2051 .enable_reg = 0x9004, 2052 .enable_mask = BIT(0), 2053 .hw.init = &(struct clk_init_data){ 2054 .name = "gcc_mmss_noc_cfg_ahb_clk", 2055 .ops = &clk_branch2_ops, 2056 /* 2057 * Any access to mmss depends on this clock. 2058 * Gating this clock has been shown to crash the system 2059 * when mmssnoc_axi_rpm_clk is inited in rpmcc. 2060 */ 2061 .flags = CLK_IS_CRITICAL, 2062 }, 2063 }, 2064 }; 2065 2066 static struct clk_branch gcc_mmss_qm_ahb_clk = { 2067 .halt_reg = 0x9030, 2068 .halt_check = BRANCH_HALT, 2069 .clkr = { 2070 .enable_reg = 0x9030, 2071 .enable_mask = BIT(0), 2072 .hw.init = &(struct clk_init_data){ 2073 .name = "gcc_mmss_qm_ahb_clk", 2074 .ops = &clk_branch2_ops, 2075 }, 2076 }, 2077 }; 2078 2079 static struct clk_branch gcc_mmss_qm_core_clk = { 2080 .halt_reg = 0x900c, 2081 .halt_check = BRANCH_HALT, 2082 .clkr = { 2083 .enable_reg = 0x900c, 2084 .enable_mask = BIT(0), 2085 .hw.init = &(struct clk_init_data){ 2086 .name = "gcc_mmss_qm_core_clk", 2087 .ops = &clk_branch2_ops, 2088 }, 2089 }, 2090 }; 2091 2092 static struct clk_branch gcc_mmss_sys_noc_axi_clk = { 2093 .halt_reg = 0x9000, 2094 .halt_check = BRANCH_HALT, 2095 .clkr = { 2096 .enable_reg = 0x9000, 2097 .enable_mask = BIT(0), 2098 .hw.init = &(struct clk_init_data){ 2099 .name = "gcc_mmss_sys_noc_axi_clk", 2100 .ops = &clk_branch2_ops, 2101 }, 2102 }, 2103 }; 2104 2105 static struct clk_branch gcc_mss_at_clk = { 2106 .halt_reg = 0x8a00c, 2107 .halt_check = BRANCH_HALT, 2108 .clkr = { 2109 .enable_reg = 0x8a00c, 2110 .enable_mask = BIT(0), 2111 .hw.init = &(struct clk_init_data){ 2112 .name = "gcc_mss_at_clk", 2113 .ops = &clk_branch2_ops, 2114 }, 2115 }, 2116 }; 2117 2118 static struct clk_branch gcc_pcie_0_aux_clk = { 2119 .halt_reg = 0x6b014, 2120 .halt_check = BRANCH_HALT, 2121 .clkr = { 2122 .enable_reg = 0x6b014, 2123 .enable_mask = BIT(0), 2124 .hw.init = &(struct clk_init_data){ 2125 .name = "gcc_pcie_0_aux_clk", 2126 .parent_names = (const char *[]){ 2127 "pcie_aux_clk_src", 2128 }, 2129 .num_parents = 1, 2130 .flags = CLK_SET_RATE_PARENT, 2131 .ops = &clk_branch2_ops, 2132 }, 2133 }, 2134 }; 2135 2136 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 2137 .halt_reg = 0x6b010, 2138 .halt_check = BRANCH_HALT, 2139 .clkr = { 2140 .enable_reg = 0x6b010, 2141 .enable_mask = BIT(0), 2142 .hw.init = &(struct clk_init_data){ 2143 .name = "gcc_pcie_0_cfg_ahb_clk", 2144 .ops = &clk_branch2_ops, 2145 }, 2146 }, 2147 }; 2148 2149 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 2150 .halt_reg = 0x6b00c, 2151 .halt_check = BRANCH_HALT, 2152 .clkr = { 2153 .enable_reg = 0x6b00c, 2154 .enable_mask = BIT(0), 2155 .hw.init = &(struct clk_init_data){ 2156 .name = "gcc_pcie_0_mstr_axi_clk", 2157 .ops = &clk_branch2_ops, 2158 }, 2159 }, 2160 }; 2161 2162 static struct clk_branch gcc_pcie_0_pipe_clk = { 2163 .halt_reg = 0x6b018, 2164 .halt_check = BRANCH_HALT_SKIP, 2165 .clkr = { 2166 .enable_reg = 0x6b018, 2167 .enable_mask = BIT(0), 2168 .hw.init = &(struct clk_init_data){ 2169 .name = "gcc_pcie_0_pipe_clk", 2170 .ops = &clk_branch2_ops, 2171 }, 2172 }, 2173 }; 2174 2175 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 2176 .halt_reg = 0x6b008, 2177 .halt_check = BRANCH_HALT, 2178 .clkr = { 2179 .enable_reg = 0x6b008, 2180 .enable_mask = BIT(0), 2181 .hw.init = &(struct clk_init_data){ 2182 .name = "gcc_pcie_0_slv_axi_clk", 2183 .ops = &clk_branch2_ops, 2184 }, 2185 }, 2186 }; 2187 2188 static struct clk_branch gcc_pcie_phy_aux_clk = { 2189 .halt_reg = 0x6f004, 2190 .halt_check = BRANCH_HALT, 2191 .clkr = { 2192 .enable_reg = 0x6f004, 2193 .enable_mask = BIT(0), 2194 .hw.init = &(struct clk_init_data){ 2195 .name = "gcc_pcie_phy_aux_clk", 2196 .parent_names = (const char *[]){ 2197 "pcie_aux_clk_src", 2198 }, 2199 .num_parents = 1, 2200 .flags = CLK_SET_RATE_PARENT, 2201 .ops = &clk_branch2_ops, 2202 }, 2203 }, 2204 }; 2205 2206 static struct clk_branch gcc_pdm2_clk = { 2207 .halt_reg = 0x3300c, 2208 .halt_check = BRANCH_HALT, 2209 .clkr = { 2210 .enable_reg = 0x3300c, 2211 .enable_mask = BIT(0), 2212 .hw.init = &(struct clk_init_data){ 2213 .name = "gcc_pdm2_clk", 2214 .parent_names = (const char *[]){ 2215 "pdm2_clk_src", 2216 }, 2217 .num_parents = 1, 2218 .flags = CLK_SET_RATE_PARENT, 2219 .ops = &clk_branch2_ops, 2220 }, 2221 }, 2222 }; 2223 2224 static struct clk_branch gcc_pdm_ahb_clk = { 2225 .halt_reg = 0x33004, 2226 .halt_check = BRANCH_HALT, 2227 .clkr = { 2228 .enable_reg = 0x33004, 2229 .enable_mask = BIT(0), 2230 .hw.init = &(struct clk_init_data){ 2231 .name = "gcc_pdm_ahb_clk", 2232 .ops = &clk_branch2_ops, 2233 }, 2234 }, 2235 }; 2236 2237 static struct clk_branch gcc_pdm_xo4_clk = { 2238 .halt_reg = 0x33008, 2239 .halt_check = BRANCH_HALT, 2240 .clkr = { 2241 .enable_reg = 0x33008, 2242 .enable_mask = BIT(0), 2243 .hw.init = &(struct clk_init_data){ 2244 .name = "gcc_pdm_xo4_clk", 2245 .ops = &clk_branch2_ops, 2246 }, 2247 }, 2248 }; 2249 2250 static struct clk_branch gcc_prng_ahb_clk = { 2251 .halt_reg = 0x34004, 2252 .halt_check = BRANCH_HALT_VOTED, 2253 .clkr = { 2254 .enable_reg = 0x52004, 2255 .enable_mask = BIT(13), 2256 .hw.init = &(struct clk_init_data){ 2257 .name = "gcc_prng_ahb_clk", 2258 .ops = &clk_branch2_ops, 2259 }, 2260 }, 2261 }; 2262 2263 static struct clk_branch gcc_sdcc2_ahb_clk = { 2264 .halt_reg = 0x14008, 2265 .halt_check = BRANCH_HALT, 2266 .clkr = { 2267 .enable_reg = 0x14008, 2268 .enable_mask = BIT(0), 2269 .hw.init = &(struct clk_init_data){ 2270 .name = "gcc_sdcc2_ahb_clk", 2271 .ops = &clk_branch2_ops, 2272 }, 2273 }, 2274 }; 2275 2276 static struct clk_branch gcc_sdcc2_apps_clk = { 2277 .halt_reg = 0x14004, 2278 .halt_check = BRANCH_HALT, 2279 .clkr = { 2280 .enable_reg = 0x14004, 2281 .enable_mask = BIT(0), 2282 .hw.init = &(struct clk_init_data){ 2283 .name = "gcc_sdcc2_apps_clk", 2284 .parent_names = (const char *[]){ 2285 "sdcc2_apps_clk_src", 2286 }, 2287 .num_parents = 1, 2288 .flags = CLK_SET_RATE_PARENT, 2289 .ops = &clk_branch2_ops, 2290 }, 2291 }, 2292 }; 2293 2294 static struct clk_branch gcc_sdcc4_ahb_clk = { 2295 .halt_reg = 0x16008, 2296 .halt_check = BRANCH_HALT, 2297 .clkr = { 2298 .enable_reg = 0x16008, 2299 .enable_mask = BIT(0), 2300 .hw.init = &(struct clk_init_data){ 2301 .name = "gcc_sdcc4_ahb_clk", 2302 .ops = &clk_branch2_ops, 2303 }, 2304 }, 2305 }; 2306 2307 static struct clk_branch gcc_sdcc4_apps_clk = { 2308 .halt_reg = 0x16004, 2309 .halt_check = BRANCH_HALT, 2310 .clkr = { 2311 .enable_reg = 0x16004, 2312 .enable_mask = BIT(0), 2313 .hw.init = &(struct clk_init_data){ 2314 .name = "gcc_sdcc4_apps_clk", 2315 .parent_names = (const char *[]){ 2316 "sdcc4_apps_clk_src", 2317 }, 2318 .num_parents = 1, 2319 .flags = CLK_SET_RATE_PARENT, 2320 .ops = &clk_branch2_ops, 2321 }, 2322 }, 2323 }; 2324 2325 static struct clk_branch gcc_tsif_ahb_clk = { 2326 .halt_reg = 0x36004, 2327 .halt_check = BRANCH_HALT, 2328 .clkr = { 2329 .enable_reg = 0x36004, 2330 .enable_mask = BIT(0), 2331 .hw.init = &(struct clk_init_data){ 2332 .name = "gcc_tsif_ahb_clk", 2333 .ops = &clk_branch2_ops, 2334 }, 2335 }, 2336 }; 2337 2338 static struct clk_branch gcc_tsif_inactivity_timers_clk = { 2339 .halt_reg = 0x3600c, 2340 .halt_check = BRANCH_HALT, 2341 .clkr = { 2342 .enable_reg = 0x3600c, 2343 .enable_mask = BIT(0), 2344 .hw.init = &(struct clk_init_data){ 2345 .name = "gcc_tsif_inactivity_timers_clk", 2346 .ops = &clk_branch2_ops, 2347 }, 2348 }, 2349 }; 2350 2351 static struct clk_branch gcc_tsif_ref_clk = { 2352 .halt_reg = 0x36008, 2353 .halt_check = BRANCH_HALT, 2354 .clkr = { 2355 .enable_reg = 0x36008, 2356 .enable_mask = BIT(0), 2357 .hw.init = &(struct clk_init_data){ 2358 .name = "gcc_tsif_ref_clk", 2359 .parent_names = (const char *[]){ 2360 "tsif_ref_clk_src", 2361 }, 2362 .num_parents = 1, 2363 .flags = CLK_SET_RATE_PARENT, 2364 .ops = &clk_branch2_ops, 2365 }, 2366 }, 2367 }; 2368 2369 static struct clk_branch gcc_ufs_ahb_clk = { 2370 .halt_reg = 0x7500c, 2371 .halt_check = BRANCH_HALT, 2372 .clkr = { 2373 .enable_reg = 0x7500c, 2374 .enable_mask = BIT(0), 2375 .hw.init = &(struct clk_init_data){ 2376 .name = "gcc_ufs_ahb_clk", 2377 .ops = &clk_branch2_ops, 2378 }, 2379 }, 2380 }; 2381 2382 static struct clk_branch gcc_ufs_axi_clk = { 2383 .halt_reg = 0x75008, 2384 .halt_check = BRANCH_HALT, 2385 .clkr = { 2386 .enable_reg = 0x75008, 2387 .enable_mask = BIT(0), 2388 .hw.init = &(struct clk_init_data){ 2389 .name = "gcc_ufs_axi_clk", 2390 .parent_names = (const char *[]){ 2391 "ufs_axi_clk_src", 2392 }, 2393 .num_parents = 1, 2394 .flags = CLK_SET_RATE_PARENT, 2395 .ops = &clk_branch2_ops, 2396 }, 2397 }, 2398 }; 2399 2400 static struct clk_branch gcc_ufs_ice_core_clk = { 2401 .halt_reg = 0x7600c, 2402 .halt_check = BRANCH_HALT, 2403 .clkr = { 2404 .enable_reg = 0x7600c, 2405 .enable_mask = BIT(0), 2406 .hw.init = &(struct clk_init_data){ 2407 .name = "gcc_ufs_ice_core_clk", 2408 .ops = &clk_branch2_ops, 2409 }, 2410 }, 2411 }; 2412 2413 static struct clk_branch gcc_ufs_phy_aux_clk = { 2414 .halt_reg = 0x76040, 2415 .halt_check = BRANCH_HALT, 2416 .clkr = { 2417 .enable_reg = 0x76040, 2418 .enable_mask = BIT(0), 2419 .hw.init = &(struct clk_init_data){ 2420 .name = "gcc_ufs_phy_aux_clk", 2421 .ops = &clk_branch2_ops, 2422 }, 2423 }, 2424 }; 2425 2426 static struct clk_branch gcc_ufs_rx_symbol_0_clk = { 2427 .halt_reg = 0x75014, 2428 .halt_check = BRANCH_HALT_SKIP, 2429 .clkr = { 2430 .enable_reg = 0x75014, 2431 .enable_mask = BIT(0), 2432 .hw.init = &(struct clk_init_data){ 2433 .name = "gcc_ufs_rx_symbol_0_clk", 2434 .ops = &clk_branch2_ops, 2435 }, 2436 }, 2437 }; 2438 2439 static struct clk_branch gcc_ufs_rx_symbol_1_clk = { 2440 .halt_reg = 0x7605c, 2441 .halt_check = BRANCH_HALT_SKIP, 2442 .clkr = { 2443 .enable_reg = 0x7605c, 2444 .enable_mask = BIT(0), 2445 .hw.init = &(struct clk_init_data){ 2446 .name = "gcc_ufs_rx_symbol_1_clk", 2447 .ops = &clk_branch2_ops, 2448 }, 2449 }, 2450 }; 2451 2452 static struct clk_branch gcc_ufs_tx_symbol_0_clk = { 2453 .halt_reg = 0x75010, 2454 .halt_check = BRANCH_HALT_SKIP, 2455 .clkr = { 2456 .enable_reg = 0x75010, 2457 .enable_mask = BIT(0), 2458 .hw.init = &(struct clk_init_data){ 2459 .name = "gcc_ufs_tx_symbol_0_clk", 2460 .ops = &clk_branch2_ops, 2461 }, 2462 }, 2463 }; 2464 2465 static struct clk_branch gcc_ufs_unipro_core_clk = { 2466 .halt_reg = 0x76008, 2467 .halt_check = BRANCH_HALT, 2468 .clkr = { 2469 .enable_reg = 0x76008, 2470 .enable_mask = BIT(0), 2471 .hw.init = &(struct clk_init_data){ 2472 .name = "gcc_ufs_unipro_core_clk", 2473 .ops = &clk_branch2_ops, 2474 }, 2475 }, 2476 }; 2477 2478 static struct clk_branch gcc_usb30_master_clk = { 2479 .halt_reg = 0xf008, 2480 .halt_check = BRANCH_HALT, 2481 .clkr = { 2482 .enable_reg = 0xf008, 2483 .enable_mask = BIT(0), 2484 .hw.init = &(struct clk_init_data){ 2485 .name = "gcc_usb30_master_clk", 2486 .parent_names = (const char *[]){ 2487 "usb30_master_clk_src", 2488 }, 2489 .num_parents = 1, 2490 .flags = CLK_SET_RATE_PARENT, 2491 .ops = &clk_branch2_ops, 2492 }, 2493 }, 2494 }; 2495 2496 static struct clk_branch gcc_usb30_mock_utmi_clk = { 2497 .halt_reg = 0xf010, 2498 .halt_check = BRANCH_HALT, 2499 .clkr = { 2500 .enable_reg = 0xf010, 2501 .enable_mask = BIT(0), 2502 .hw.init = &(struct clk_init_data){ 2503 .name = "gcc_usb30_mock_utmi_clk", 2504 .parent_names = (const char *[]){ 2505 "usb30_mock_utmi_clk_src", 2506 }, 2507 .num_parents = 1, 2508 .flags = CLK_SET_RATE_PARENT, 2509 .ops = &clk_branch2_ops, 2510 }, 2511 }, 2512 }; 2513 2514 static struct clk_branch gcc_usb30_sleep_clk = { 2515 .halt_reg = 0xf00c, 2516 .halt_check = BRANCH_HALT, 2517 .clkr = { 2518 .enable_reg = 0xf00c, 2519 .enable_mask = BIT(0), 2520 .hw.init = &(struct clk_init_data){ 2521 .name = "gcc_usb30_sleep_clk", 2522 .ops = &clk_branch2_ops, 2523 }, 2524 }, 2525 }; 2526 2527 static struct clk_branch gcc_usb3_phy_aux_clk = { 2528 .halt_reg = 0x50000, 2529 .halt_check = BRANCH_HALT, 2530 .clkr = { 2531 .enable_reg = 0x50000, 2532 .enable_mask = BIT(0), 2533 .hw.init = &(struct clk_init_data){ 2534 .name = "gcc_usb3_phy_aux_clk", 2535 .parent_names = (const char *[]){ 2536 "usb3_phy_aux_clk_src", 2537 }, 2538 .num_parents = 1, 2539 .flags = CLK_SET_RATE_PARENT, 2540 .ops = &clk_branch2_ops, 2541 }, 2542 }, 2543 }; 2544 2545 static struct clk_branch gcc_usb3_phy_pipe_clk = { 2546 .halt_reg = 0x50004, 2547 .halt_check = BRANCH_HALT_SKIP, 2548 .clkr = { 2549 .enable_reg = 0x50004, 2550 .enable_mask = BIT(0), 2551 .hw.init = &(struct clk_init_data){ 2552 .name = "gcc_usb3_phy_pipe_clk", 2553 .ops = &clk_branch2_ops, 2554 }, 2555 }, 2556 }; 2557 2558 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 2559 .halt_reg = 0x6a004, 2560 .halt_check = BRANCH_HALT, 2561 .clkr = { 2562 .enable_reg = 0x6a004, 2563 .enable_mask = BIT(0), 2564 .hw.init = &(struct clk_init_data){ 2565 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2566 .ops = &clk_branch2_ops, 2567 }, 2568 }, 2569 }; 2570 2571 static struct clk_branch gcc_hdmi_clkref_clk = { 2572 .halt_reg = 0x88000, 2573 .clkr = { 2574 .enable_reg = 0x88000, 2575 .enable_mask = BIT(0), 2576 .hw.init = &(struct clk_init_data){ 2577 .name = "gcc_hdmi_clkref_clk", 2578 .parent_names = (const char *[]){ "xo" }, 2579 .num_parents = 1, 2580 .ops = &clk_branch2_ops, 2581 }, 2582 }, 2583 }; 2584 2585 static struct clk_branch gcc_ufs_clkref_clk = { 2586 .halt_reg = 0x88004, 2587 .clkr = { 2588 .enable_reg = 0x88004, 2589 .enable_mask = BIT(0), 2590 .hw.init = &(struct clk_init_data){ 2591 .name = "gcc_ufs_clkref_clk", 2592 .parent_names = (const char *[]){ "xo" }, 2593 .num_parents = 1, 2594 .ops = &clk_branch2_ops, 2595 }, 2596 }, 2597 }; 2598 2599 static struct clk_branch gcc_usb3_clkref_clk = { 2600 .halt_reg = 0x88008, 2601 .clkr = { 2602 .enable_reg = 0x88008, 2603 .enable_mask = BIT(0), 2604 .hw.init = &(struct clk_init_data){ 2605 .name = "gcc_usb3_clkref_clk", 2606 .parent_names = (const char *[]){ "xo" }, 2607 .num_parents = 1, 2608 .ops = &clk_branch2_ops, 2609 }, 2610 }, 2611 }; 2612 2613 static struct clk_branch gcc_pcie_clkref_clk = { 2614 .halt_reg = 0x8800c, 2615 .clkr = { 2616 .enable_reg = 0x8800c, 2617 .enable_mask = BIT(0), 2618 .hw.init = &(struct clk_init_data){ 2619 .name = "gcc_pcie_clkref_clk", 2620 .parent_names = (const char *[]){ "xo" }, 2621 .num_parents = 1, 2622 .ops = &clk_branch2_ops, 2623 }, 2624 }, 2625 }; 2626 2627 static struct clk_branch gcc_rx1_usb2_clkref_clk = { 2628 .halt_reg = 0x88014, 2629 .clkr = { 2630 .enable_reg = 0x88014, 2631 .enable_mask = BIT(0), 2632 .hw.init = &(struct clk_init_data){ 2633 .name = "gcc_rx1_usb2_clkref_clk", 2634 .parent_names = (const char *[]){ "xo" }, 2635 .num_parents = 1, 2636 .ops = &clk_branch2_ops, 2637 }, 2638 }, 2639 }; 2640 2641 static struct gdsc pcie_0_gdsc = { 2642 .gdscr = 0x6b004, 2643 .gds_hw_ctrl = 0x0, 2644 .pd = { 2645 .name = "pcie_0_gdsc", 2646 }, 2647 .pwrsts = PWRSTS_OFF_ON, 2648 .flags = VOTABLE, 2649 }; 2650 2651 static struct gdsc ufs_gdsc = { 2652 .gdscr = 0x75004, 2653 .gds_hw_ctrl = 0x0, 2654 .pd = { 2655 .name = "ufs_gdsc", 2656 }, 2657 .pwrsts = PWRSTS_OFF_ON, 2658 .flags = VOTABLE, 2659 }; 2660 2661 static struct gdsc usb_30_gdsc = { 2662 .gdscr = 0xf004, 2663 .gds_hw_ctrl = 0x0, 2664 .pd = { 2665 .name = "usb_30_gdsc", 2666 }, 2667 .pwrsts = PWRSTS_OFF_ON, 2668 .flags = VOTABLE, 2669 }; 2670 2671 static struct clk_regmap *gcc_msm8998_clocks[] = { 2672 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2673 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2674 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2675 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2676 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2677 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2678 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2679 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2680 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 2681 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 2682 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 2683 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 2684 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2685 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2686 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 2687 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, 2688 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, 2689 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, 2690 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, 2691 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, 2692 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, 2693 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, 2694 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, 2695 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, 2696 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, 2697 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, 2698 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, 2699 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, 2700 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, 2701 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, 2702 [GCC_AGGRE1_NOC_XO_CLK] = &gcc_aggre1_noc_xo_clk.clkr, 2703 [GCC_AGGRE1_UFS_AXI_CLK] = &gcc_aggre1_ufs_axi_clk.clkr, 2704 [GCC_AGGRE1_USB3_AXI_CLK] = &gcc_aggre1_usb3_axi_clk.clkr, 2705 [GCC_APSS_QDSS_TSCTR_DIV2_CLK] = &gcc_apss_qdss_tsctr_div2_clk.clkr, 2706 [GCC_APSS_QDSS_TSCTR_DIV8_CLK] = &gcc_apss_qdss_tsctr_div8_clk.clkr, 2707 [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr, 2708 [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr, 2709 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2710 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2711 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2712 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2713 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2714 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2715 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2716 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 2717 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 2718 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 2719 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 2720 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 2721 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 2722 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, 2723 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2724 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2725 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 2726 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, 2727 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, 2728 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, 2729 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, 2730 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, 2731 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, 2732 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, 2733 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, 2734 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, 2735 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, 2736 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, 2737 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, 2738 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, 2739 [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr, 2740 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, 2741 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, 2742 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, 2743 [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr, 2744 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2745 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2746 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2747 [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr, 2748 [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr, 2749 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 2750 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 2751 [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr, 2752 [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr, 2753 [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr, 2754 [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr, 2755 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr, 2756 [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr, 2757 [GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr, 2758 [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr, 2759 [GCC_MSS_AT_CLK] = &gcc_mss_at_clk.clkr, 2760 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2761 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2762 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2763 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2764 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2765 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, 2766 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2767 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2768 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2769 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2770 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2771 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2772 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 2773 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 2774 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 2775 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, 2776 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 2777 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, 2778 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, 2779 [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr, 2780 [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr, 2781 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, 2782 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, 2783 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, 2784 [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr, 2785 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, 2786 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 2787 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 2788 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, 2789 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, 2790 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 2791 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 2792 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 2793 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 2794 [GPLL0] = &gpll0.clkr, 2795 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 2796 [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr, 2797 [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr, 2798 [GPLL0_OUT_TEST] = &gpll0_out_test.clkr, 2799 [GPLL1] = &gpll1.clkr, 2800 [GPLL1_OUT_EVEN] = &gpll1_out_even.clkr, 2801 [GPLL1_OUT_MAIN] = &gpll1_out_main.clkr, 2802 [GPLL1_OUT_ODD] = &gpll1_out_odd.clkr, 2803 [GPLL1_OUT_TEST] = &gpll1_out_test.clkr, 2804 [GPLL2] = &gpll2.clkr, 2805 [GPLL2_OUT_EVEN] = &gpll2_out_even.clkr, 2806 [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr, 2807 [GPLL2_OUT_ODD] = &gpll2_out_odd.clkr, 2808 [GPLL2_OUT_TEST] = &gpll2_out_test.clkr, 2809 [GPLL3] = &gpll3.clkr, 2810 [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr, 2811 [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr, 2812 [GPLL3_OUT_ODD] = &gpll3_out_odd.clkr, 2813 [GPLL3_OUT_TEST] = &gpll3_out_test.clkr, 2814 [GPLL4] = &gpll4.clkr, 2815 [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr, 2816 [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr, 2817 [GPLL4_OUT_ODD] = &gpll4_out_odd.clkr, 2818 [GPLL4_OUT_TEST] = &gpll4_out_test.clkr, 2819 [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr, 2820 [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr, 2821 [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr, 2822 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 2823 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 2824 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, 2825 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, 2826 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, 2827 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, 2828 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 2829 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, 2830 [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr, 2831 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, 2832 [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr, 2833 [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr, 2834 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr, 2835 }; 2836 2837 static struct gdsc *gcc_msm8998_gdscs[] = { 2838 [PCIE_0_GDSC] = &pcie_0_gdsc, 2839 [UFS_GDSC] = &ufs_gdsc, 2840 [USB_30_GDSC] = &usb_30_gdsc, 2841 }; 2842 2843 static const struct qcom_reset_map gcc_msm8998_resets[] = { 2844 [GCC_BLSP1_QUP1_BCR] = { 0x19000 }, 2845 [GCC_BLSP1_QUP2_BCR] = { 0x1b000 }, 2846 [GCC_BLSP1_QUP3_BCR] = { 0x1d000 }, 2847 [GCC_BLSP1_QUP4_BCR] = { 0x1f000 }, 2848 [GCC_BLSP1_QUP5_BCR] = { 0x21000 }, 2849 [GCC_BLSP1_QUP6_BCR] = { 0x23000 }, 2850 [GCC_BLSP2_QUP1_BCR] = { 0x26000 }, 2851 [GCC_BLSP2_QUP2_BCR] = { 0x28000 }, 2852 [GCC_BLSP2_QUP3_BCR] = { 0x2a000 }, 2853 [GCC_BLSP2_QUP4_BCR] = { 0x2c000 }, 2854 [GCC_BLSP2_QUP5_BCR] = { 0x2e000 }, 2855 [GCC_BLSP2_QUP6_BCR] = { 0x30000 }, 2856 [GCC_PCIE_0_BCR] = { 0x6b000 }, 2857 [GCC_PDM_BCR] = { 0x33000 }, 2858 [GCC_SDCC2_BCR] = { 0x14000 }, 2859 [GCC_SDCC4_BCR] = { 0x16000 }, 2860 [GCC_TSIF_BCR] = { 0x36000 }, 2861 [GCC_UFS_BCR] = { 0x75000 }, 2862 [GCC_USB_30_BCR] = { 0xf000 }, 2863 [GCC_SYSTEM_NOC_BCR] = { 0x4000 }, 2864 [GCC_CONFIG_NOC_BCR] = { 0x5000 }, 2865 [GCC_AHB2PHY_EAST_BCR] = { 0x7000 }, 2866 [GCC_IMEM_BCR] = { 0x8000 }, 2867 [GCC_PIMEM_BCR] = { 0xa000 }, 2868 [GCC_MMSS_BCR] = { 0xb000 }, 2869 [GCC_QDSS_BCR] = { 0xc000 }, 2870 [GCC_WCSS_BCR] = { 0x11000 }, 2871 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 2872 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 2873 [GCC_BLSP1_BCR] = { 0x17000 }, 2874 [GCC_BLSP1_UART1_BCR] = { 0x1a000 }, 2875 [GCC_BLSP1_UART2_BCR] = { 0x1c000 }, 2876 [GCC_BLSP1_UART3_BCR] = { 0x1e000 }, 2877 [GCC_CM_PHY_REFGEN1_BCR] = { 0x22000 }, 2878 [GCC_CM_PHY_REFGEN2_BCR] = { 0x24000 }, 2879 [GCC_BLSP2_BCR] = { 0x25000 }, 2880 [GCC_BLSP2_UART1_BCR] = { 0x27000 }, 2881 [GCC_BLSP2_UART2_BCR] = { 0x29000 }, 2882 [GCC_BLSP2_UART3_BCR] = { 0x2b000 }, 2883 [GCC_SRAM_SENSOR_BCR] = { 0x2d000 }, 2884 [GCC_PRNG_BCR] = { 0x34000 }, 2885 [GCC_TSIF_0_RESET] = { 0x36024 }, 2886 [GCC_TSIF_1_RESET] = { 0x36028 }, 2887 [GCC_TCSR_BCR] = { 0x37000 }, 2888 [GCC_BOOT_ROM_BCR] = { 0x38000 }, 2889 [GCC_MSG_RAM_BCR] = { 0x39000 }, 2890 [GCC_TLMM_BCR] = { 0x3a000 }, 2891 [GCC_MPM_BCR] = { 0x3b000 }, 2892 [GCC_SEC_CTRL_BCR] = { 0x3d000 }, 2893 [GCC_SPMI_BCR] = { 0x3f000 }, 2894 [GCC_SPDM_BCR] = { 0x40000 }, 2895 [GCC_CE1_BCR] = { 0x41000 }, 2896 [GCC_BIMC_BCR] = { 0x44000 }, 2897 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 }, 2898 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49008 }, 2899 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49010 }, 2900 [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49018 }, 2901 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 }, 2902 [GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR] = { 0x4a004 }, 2903 [GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR] = { 0x4a00c }, 2904 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 }, 2905 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 }, 2906 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 }, 2907 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 }, 2908 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 }, 2909 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 }, 2910 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 }, 2911 [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 }, 2912 [GCC_APB2JTAG_BCR] = { 0x4c000 }, 2913 [GCC_RBCPR_CX_BCR] = { 0x4e000 }, 2914 [GCC_RBCPR_MX_BCR] = { 0x4f000 }, 2915 [GCC_USB3_PHY_BCR] = { 0x50020 }, 2916 [GCC_USB3PHY_PHY_BCR] = { 0x50024 }, 2917 [GCC_USB3_DP_PHY_BCR] = { 0x50028 }, 2918 [GCC_SSC_BCR] = { 0x63000 }, 2919 [GCC_SSC_RESET] = { 0x63020 }, 2920 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 2921 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 2922 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 2923 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 2924 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 2925 [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00c }, 2926 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f010 }, 2927 [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 }, 2928 [GCC_GPU_BCR] = { 0x71000 }, 2929 [GCC_SPSS_BCR] = { 0x72000 }, 2930 [GCC_OBT_ODT_BCR] = { 0x73000 }, 2931 [GCC_VS_BCR] = { 0x7a000 }, 2932 [GCC_MSS_VS_RESET] = { 0x7a100 }, 2933 [GCC_GPU_VS_RESET] = { 0x7a104 }, 2934 [GCC_APC0_VS_RESET] = { 0x7a108 }, 2935 [GCC_APC1_VS_RESET] = { 0x7a10c }, 2936 [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 }, 2937 [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 }, 2938 [GCC_CNOC_BUS_TIMEOUT10_BCR] = { 0x80010 }, 2939 [GCC_CNOC_BUS_TIMEOUT11_BCR] = { 0x80018 }, 2940 [GCC_CNOC_BUS_TIMEOUT12_BCR] = { 0x80020 }, 2941 [GCC_CNOC_BUS_TIMEOUT13_BCR] = { 0x80028 }, 2942 [GCC_CNOC_BUS_TIMEOUT14_BCR] = { 0x80030 }, 2943 [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80038 }, 2944 [GCC_AGGRE1_NOC_BCR] = { 0x82000 }, 2945 [GCC_AGGRE2_NOC_BCR] = { 0x83000 }, 2946 [GCC_DCC_BCR] = { 0x84000 }, 2947 [GCC_QREFS_VBG_CAL_BCR] = { 0x88028 }, 2948 [GCC_IPA_BCR] = { 0x89000 }, 2949 [GCC_GLM_BCR] = { 0x8b000 }, 2950 [GCC_SKL_BCR] = { 0x8c000 }, 2951 [GCC_MSMPU_BCR] = { 0x8d000 }, 2952 }; 2953 2954 static const struct regmap_config gcc_msm8998_regmap_config = { 2955 .reg_bits = 32, 2956 .reg_stride = 4, 2957 .val_bits = 32, 2958 .max_register = 0x8f000, 2959 .fast_io = true, 2960 }; 2961 2962 static struct clk_hw *gcc_msm8998_hws[] = { 2963 &xo.hw, 2964 }; 2965 2966 static const struct qcom_cc_desc gcc_msm8998_desc = { 2967 .config = &gcc_msm8998_regmap_config, 2968 .clks = gcc_msm8998_clocks, 2969 .num_clks = ARRAY_SIZE(gcc_msm8998_clocks), 2970 .resets = gcc_msm8998_resets, 2971 .num_resets = ARRAY_SIZE(gcc_msm8998_resets), 2972 .gdscs = gcc_msm8998_gdscs, 2973 .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs), 2974 .clk_hws = gcc_msm8998_hws, 2975 .num_clk_hws = ARRAY_SIZE(gcc_msm8998_hws), 2976 }; 2977 2978 static int gcc_msm8998_probe(struct platform_device *pdev) 2979 { 2980 struct regmap *regmap; 2981 int ret; 2982 2983 regmap = qcom_cc_map(pdev, &gcc_msm8998_desc); 2984 if (IS_ERR(regmap)) 2985 return PTR_ERR(regmap); 2986 2987 /* 2988 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be 2989 * turned off by hardware during certain apps low power modes. 2990 */ 2991 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); 2992 if (ret) 2993 return ret; 2994 2995 return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap); 2996 } 2997 2998 static const struct of_device_id gcc_msm8998_match_table[] = { 2999 { .compatible = "qcom,gcc-msm8998" }, 3000 { } 3001 }; 3002 MODULE_DEVICE_TABLE(of, gcc_msm8998_match_table); 3003 3004 static struct platform_driver gcc_msm8998_driver = { 3005 .probe = gcc_msm8998_probe, 3006 .driver = { 3007 .name = "gcc-msm8998", 3008 .of_match_table = gcc_msm8998_match_table, 3009 }, 3010 }; 3011 3012 static int __init gcc_msm8998_init(void) 3013 { 3014 return platform_driver_register(&gcc_msm8998_driver); 3015 } 3016 core_initcall(gcc_msm8998_init); 3017 3018 static void __exit gcc_msm8998_exit(void) 3019 { 3020 platform_driver_unregister(&gcc_msm8998_driver); 3021 } 3022 module_exit(gcc_msm8998_exit); 3023 3024 MODULE_DESCRIPTION("QCOM GCC msm8998 Driver"); 3025 MODULE_LICENSE("GPL v2"); 3026 MODULE_ALIAS("platform:gcc-msm8998"); 3027