1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2016, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/bitops.h> 8 #include <linux/err.h> 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/clk-provider.h> 14 #include <linux/regmap.h> 15 #include <linux/reset-controller.h> 16 17 #include <dt-bindings/clock/qcom,gcc-msm8998.h> 18 19 #include "common.h" 20 #include "clk-regmap.h" 21 #include "clk-alpha-pll.h" 22 #include "clk-pll.h" 23 #include "clk-rcg.h" 24 #include "clk-branch.h" 25 #include "reset.h" 26 #include "gdsc.h" 27 28 enum { 29 P_AUD_REF_CLK, 30 P_CORE_BI_PLL_TEST_SE, 31 P_GPLL0_OUT_MAIN, 32 P_GPLL4_OUT_MAIN, 33 P_PLL0_EARLY_DIV_CLK_SRC, 34 P_SLEEP_CLK, 35 P_XO, 36 }; 37 38 static const struct parent_map gcc_parent_map_0[] = { 39 { P_XO, 0 }, 40 { P_GPLL0_OUT_MAIN, 1 }, 41 { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, 42 { P_CORE_BI_PLL_TEST_SE, 7 }, 43 }; 44 45 static const char * const gcc_parent_names_0[] = { 46 "xo", 47 "gpll0_out_main", 48 "gpll0_out_main", 49 "core_bi_pll_test_se", 50 }; 51 52 static const struct parent_map gcc_parent_map_1[] = { 53 { P_XO, 0 }, 54 { P_GPLL0_OUT_MAIN, 1 }, 55 { P_CORE_BI_PLL_TEST_SE, 7 }, 56 }; 57 58 static const char * const gcc_parent_names_1[] = { 59 "xo", 60 "gpll0_out_main", 61 "core_bi_pll_test_se", 62 }; 63 64 static const struct parent_map gcc_parent_map_2[] = { 65 { P_XO, 0 }, 66 { P_GPLL0_OUT_MAIN, 1 }, 67 { P_SLEEP_CLK, 5 }, 68 { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, 69 { P_CORE_BI_PLL_TEST_SE, 7 }, 70 }; 71 72 static const char * const gcc_parent_names_2[] = { 73 "xo", 74 "gpll0_out_main", 75 "core_pi_sleep_clk", 76 "gpll0_out_main", 77 "core_bi_pll_test_se", 78 }; 79 80 static const struct parent_map gcc_parent_map_3[] = { 81 { P_XO, 0 }, 82 { P_SLEEP_CLK, 5 }, 83 { P_CORE_BI_PLL_TEST_SE, 7 }, 84 }; 85 86 static const char * const gcc_parent_names_3[] = { 87 "xo", 88 "core_pi_sleep_clk", 89 "core_bi_pll_test_se", 90 }; 91 92 static const struct parent_map gcc_parent_map_4[] = { 93 { P_XO, 0 }, 94 { P_GPLL0_OUT_MAIN, 1 }, 95 { P_GPLL4_OUT_MAIN, 5 }, 96 { P_CORE_BI_PLL_TEST_SE, 7 }, 97 }; 98 99 static const char * const gcc_parent_names_4[] = { 100 "xo", 101 "gpll0_out_main", 102 "gpll4_out_main", 103 "core_bi_pll_test_se", 104 }; 105 106 static const struct parent_map gcc_parent_map_5[] = { 107 { P_XO, 0 }, 108 { P_GPLL0_OUT_MAIN, 1 }, 109 { P_AUD_REF_CLK, 2 }, 110 { P_CORE_BI_PLL_TEST_SE, 7 }, 111 }; 112 113 static const char * const gcc_parent_names_5[] = { 114 "xo", 115 "gpll0_out_main", 116 "aud_ref_clk", 117 "core_bi_pll_test_se", 118 }; 119 120 static struct clk_fixed_factor xo = { 121 .mult = 1, 122 .div = 1, 123 .hw.init = &(struct clk_init_data){ 124 .name = "xo", 125 .parent_names = (const char *[]){ "xo_board" }, 126 .num_parents = 1, 127 .ops = &clk_fixed_factor_ops, 128 }, 129 }; 130 131 static struct pll_vco fabia_vco[] = { 132 { 250000000, 2000000000, 0 }, 133 { 125000000, 1000000000, 1 }, 134 }; 135 136 static struct clk_alpha_pll gpll0 = { 137 .offset = 0x0, 138 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 139 .vco_table = fabia_vco, 140 .num_vco = ARRAY_SIZE(fabia_vco), 141 .clkr = { 142 .enable_reg = 0x52000, 143 .enable_mask = BIT(0), 144 .hw.init = &(struct clk_init_data){ 145 .name = "gpll0", 146 .parent_names = (const char *[]){ "xo" }, 147 .num_parents = 1, 148 .ops = &clk_alpha_pll_fixed_fabia_ops, 149 } 150 }, 151 }; 152 153 static struct clk_alpha_pll_postdiv gpll0_out_even = { 154 .offset = 0x0, 155 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 156 .clkr.hw.init = &(struct clk_init_data){ 157 .name = "gpll0_out_even", 158 .parent_names = (const char *[]){ "gpll0" }, 159 .num_parents = 1, 160 .ops = &clk_alpha_pll_postdiv_fabia_ops, 161 }, 162 }; 163 164 static struct clk_alpha_pll_postdiv gpll0_out_main = { 165 .offset = 0x0, 166 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 167 .clkr.hw.init = &(struct clk_init_data){ 168 .name = "gpll0_out_main", 169 .parent_names = (const char *[]){ "gpll0" }, 170 .num_parents = 1, 171 .ops = &clk_alpha_pll_postdiv_fabia_ops, 172 }, 173 }; 174 175 static struct clk_alpha_pll_postdiv gpll0_out_odd = { 176 .offset = 0x0, 177 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 178 .clkr.hw.init = &(struct clk_init_data){ 179 .name = "gpll0_out_odd", 180 .parent_names = (const char *[]){ "gpll0" }, 181 .num_parents = 1, 182 .ops = &clk_alpha_pll_postdiv_fabia_ops, 183 }, 184 }; 185 186 static struct clk_alpha_pll_postdiv gpll0_out_test = { 187 .offset = 0x0, 188 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 189 .clkr.hw.init = &(struct clk_init_data){ 190 .name = "gpll0_out_test", 191 .parent_names = (const char *[]){ "gpll0" }, 192 .num_parents = 1, 193 .ops = &clk_alpha_pll_postdiv_fabia_ops, 194 }, 195 }; 196 197 static struct clk_alpha_pll gpll1 = { 198 .offset = 0x1000, 199 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 200 .vco_table = fabia_vco, 201 .num_vco = ARRAY_SIZE(fabia_vco), 202 .clkr = { 203 .enable_reg = 0x52000, 204 .enable_mask = BIT(1), 205 .hw.init = &(struct clk_init_data){ 206 .name = "gpll1", 207 .parent_names = (const char *[]){ "xo" }, 208 .num_parents = 1, 209 .ops = &clk_alpha_pll_fixed_fabia_ops, 210 } 211 }, 212 }; 213 214 static struct clk_alpha_pll_postdiv gpll1_out_even = { 215 .offset = 0x1000, 216 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 217 .clkr.hw.init = &(struct clk_init_data){ 218 .name = "gpll1_out_even", 219 .parent_names = (const char *[]){ "gpll1" }, 220 .num_parents = 1, 221 .ops = &clk_alpha_pll_postdiv_fabia_ops, 222 }, 223 }; 224 225 static struct clk_alpha_pll_postdiv gpll1_out_main = { 226 .offset = 0x1000, 227 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 228 .clkr.hw.init = &(struct clk_init_data){ 229 .name = "gpll1_out_main", 230 .parent_names = (const char *[]){ "gpll1" }, 231 .num_parents = 1, 232 .ops = &clk_alpha_pll_postdiv_fabia_ops, 233 }, 234 }; 235 236 static struct clk_alpha_pll_postdiv gpll1_out_odd = { 237 .offset = 0x1000, 238 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 239 .clkr.hw.init = &(struct clk_init_data){ 240 .name = "gpll1_out_odd", 241 .parent_names = (const char *[]){ "gpll1" }, 242 .num_parents = 1, 243 .ops = &clk_alpha_pll_postdiv_fabia_ops, 244 }, 245 }; 246 247 static struct clk_alpha_pll_postdiv gpll1_out_test = { 248 .offset = 0x1000, 249 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 250 .clkr.hw.init = &(struct clk_init_data){ 251 .name = "gpll1_out_test", 252 .parent_names = (const char *[]){ "gpll1" }, 253 .num_parents = 1, 254 .ops = &clk_alpha_pll_postdiv_fabia_ops, 255 }, 256 }; 257 258 static struct clk_alpha_pll gpll2 = { 259 .offset = 0x2000, 260 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 261 .vco_table = fabia_vco, 262 .num_vco = ARRAY_SIZE(fabia_vco), 263 .clkr = { 264 .enable_reg = 0x52000, 265 .enable_mask = BIT(2), 266 .hw.init = &(struct clk_init_data){ 267 .name = "gpll2", 268 .parent_names = (const char *[]){ "xo" }, 269 .num_parents = 1, 270 .ops = &clk_alpha_pll_fixed_fabia_ops, 271 } 272 }, 273 }; 274 275 static struct clk_alpha_pll_postdiv gpll2_out_even = { 276 .offset = 0x2000, 277 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 278 .clkr.hw.init = &(struct clk_init_data){ 279 .name = "gpll2_out_even", 280 .parent_names = (const char *[]){ "gpll2" }, 281 .num_parents = 1, 282 .ops = &clk_alpha_pll_postdiv_fabia_ops, 283 }, 284 }; 285 286 static struct clk_alpha_pll_postdiv gpll2_out_main = { 287 .offset = 0x2000, 288 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 289 .clkr.hw.init = &(struct clk_init_data){ 290 .name = "gpll2_out_main", 291 .parent_names = (const char *[]){ "gpll2" }, 292 .num_parents = 1, 293 .ops = &clk_alpha_pll_postdiv_fabia_ops, 294 }, 295 }; 296 297 static struct clk_alpha_pll_postdiv gpll2_out_odd = { 298 .offset = 0x2000, 299 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 300 .clkr.hw.init = &(struct clk_init_data){ 301 .name = "gpll2_out_odd", 302 .parent_names = (const char *[]){ "gpll2" }, 303 .num_parents = 1, 304 .ops = &clk_alpha_pll_postdiv_fabia_ops, 305 }, 306 }; 307 308 static struct clk_alpha_pll_postdiv gpll2_out_test = { 309 .offset = 0x2000, 310 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 311 .clkr.hw.init = &(struct clk_init_data){ 312 .name = "gpll2_out_test", 313 .parent_names = (const char *[]){ "gpll2" }, 314 .num_parents = 1, 315 .ops = &clk_alpha_pll_postdiv_fabia_ops, 316 }, 317 }; 318 319 static struct clk_alpha_pll gpll3 = { 320 .offset = 0x3000, 321 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 322 .vco_table = fabia_vco, 323 .num_vco = ARRAY_SIZE(fabia_vco), 324 .clkr = { 325 .enable_reg = 0x52000, 326 .enable_mask = BIT(3), 327 .hw.init = &(struct clk_init_data){ 328 .name = "gpll3", 329 .parent_names = (const char *[]){ "xo" }, 330 .num_parents = 1, 331 .ops = &clk_alpha_pll_fixed_fabia_ops, 332 } 333 }, 334 }; 335 336 static struct clk_alpha_pll_postdiv gpll3_out_even = { 337 .offset = 0x3000, 338 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 339 .clkr.hw.init = &(struct clk_init_data){ 340 .name = "gpll3_out_even", 341 .parent_names = (const char *[]){ "gpll3" }, 342 .num_parents = 1, 343 .ops = &clk_alpha_pll_postdiv_fabia_ops, 344 }, 345 }; 346 347 static struct clk_alpha_pll_postdiv gpll3_out_main = { 348 .offset = 0x3000, 349 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 350 .clkr.hw.init = &(struct clk_init_data){ 351 .name = "gpll3_out_main", 352 .parent_names = (const char *[]){ "gpll3" }, 353 .num_parents = 1, 354 .ops = &clk_alpha_pll_postdiv_fabia_ops, 355 }, 356 }; 357 358 static struct clk_alpha_pll_postdiv gpll3_out_odd = { 359 .offset = 0x3000, 360 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 361 .clkr.hw.init = &(struct clk_init_data){ 362 .name = "gpll3_out_odd", 363 .parent_names = (const char *[]){ "gpll3" }, 364 .num_parents = 1, 365 .ops = &clk_alpha_pll_postdiv_fabia_ops, 366 }, 367 }; 368 369 static struct clk_alpha_pll_postdiv gpll3_out_test = { 370 .offset = 0x3000, 371 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 372 .clkr.hw.init = &(struct clk_init_data){ 373 .name = "gpll3_out_test", 374 .parent_names = (const char *[]){ "gpll3" }, 375 .num_parents = 1, 376 .ops = &clk_alpha_pll_postdiv_fabia_ops, 377 }, 378 }; 379 380 static struct clk_alpha_pll gpll4 = { 381 .offset = 0x77000, 382 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 383 .vco_table = fabia_vco, 384 .num_vco = ARRAY_SIZE(fabia_vco), 385 .clkr = { 386 .enable_reg = 0x52000, 387 .enable_mask = BIT(4), 388 .hw.init = &(struct clk_init_data){ 389 .name = "gpll4", 390 .parent_names = (const char *[]){ "xo" }, 391 .num_parents = 1, 392 .ops = &clk_alpha_pll_fixed_fabia_ops, 393 } 394 }, 395 }; 396 397 static struct clk_alpha_pll_postdiv gpll4_out_even = { 398 .offset = 0x77000, 399 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 400 .clkr.hw.init = &(struct clk_init_data){ 401 .name = "gpll4_out_even", 402 .parent_names = (const char *[]){ "gpll4" }, 403 .num_parents = 1, 404 .ops = &clk_alpha_pll_postdiv_fabia_ops, 405 }, 406 }; 407 408 static struct clk_alpha_pll_postdiv gpll4_out_main = { 409 .offset = 0x77000, 410 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 411 .clkr.hw.init = &(struct clk_init_data){ 412 .name = "gpll4_out_main", 413 .parent_names = (const char *[]){ "gpll4" }, 414 .num_parents = 1, 415 .ops = &clk_alpha_pll_postdiv_fabia_ops, 416 }, 417 }; 418 419 static struct clk_alpha_pll_postdiv gpll4_out_odd = { 420 .offset = 0x77000, 421 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 422 .clkr.hw.init = &(struct clk_init_data){ 423 .name = "gpll4_out_odd", 424 .parent_names = (const char *[]){ "gpll4" }, 425 .num_parents = 1, 426 .ops = &clk_alpha_pll_postdiv_fabia_ops, 427 }, 428 }; 429 430 static struct clk_alpha_pll_postdiv gpll4_out_test = { 431 .offset = 0x77000, 432 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 433 .clkr.hw.init = &(struct clk_init_data){ 434 .name = "gpll4_out_test", 435 .parent_names = (const char *[]){ "gpll4" }, 436 .num_parents = 1, 437 .ops = &clk_alpha_pll_postdiv_fabia_ops, 438 }, 439 }; 440 441 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = { 442 F(19200000, P_XO, 1, 0, 0), 443 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 444 { } 445 }; 446 447 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 448 .cmd_rcgr = 0x19020, 449 .mnd_width = 0, 450 .hid_width = 5, 451 .parent_map = gcc_parent_map_1, 452 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 453 .clkr.hw.init = &(struct clk_init_data){ 454 .name = "blsp1_qup1_i2c_apps_clk_src", 455 .parent_names = gcc_parent_names_1, 456 .num_parents = 3, 457 .ops = &clk_rcg2_ops, 458 }, 459 }; 460 461 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { 462 F(960000, P_XO, 10, 1, 2), 463 F(4800000, P_XO, 4, 0, 0), 464 F(9600000, P_XO, 2, 0, 0), 465 F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4), 466 F(19200000, P_XO, 1, 0, 0), 467 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 468 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 469 { } 470 }; 471 472 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 473 .cmd_rcgr = 0x1900c, 474 .mnd_width = 8, 475 .hid_width = 5, 476 .parent_map = gcc_parent_map_0, 477 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 478 .clkr.hw.init = &(struct clk_init_data){ 479 .name = "blsp1_qup1_spi_apps_clk_src", 480 .parent_names = gcc_parent_names_0, 481 .num_parents = 4, 482 .ops = &clk_rcg2_ops, 483 }, 484 }; 485 486 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 487 .cmd_rcgr = 0x1b020, 488 .mnd_width = 0, 489 .hid_width = 5, 490 .parent_map = gcc_parent_map_1, 491 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 492 .clkr.hw.init = &(struct clk_init_data){ 493 .name = "blsp1_qup2_i2c_apps_clk_src", 494 .parent_names = gcc_parent_names_1, 495 .num_parents = 3, 496 .ops = &clk_rcg2_ops, 497 }, 498 }; 499 500 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 501 .cmd_rcgr = 0x1b00c, 502 .mnd_width = 8, 503 .hid_width = 5, 504 .parent_map = gcc_parent_map_0, 505 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 506 .clkr.hw.init = &(struct clk_init_data){ 507 .name = "blsp1_qup2_spi_apps_clk_src", 508 .parent_names = gcc_parent_names_0, 509 .num_parents = 4, 510 .ops = &clk_rcg2_ops, 511 }, 512 }; 513 514 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 515 .cmd_rcgr = 0x1d020, 516 .mnd_width = 0, 517 .hid_width = 5, 518 .parent_map = gcc_parent_map_1, 519 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 520 .clkr.hw.init = &(struct clk_init_data){ 521 .name = "blsp1_qup3_i2c_apps_clk_src", 522 .parent_names = gcc_parent_names_1, 523 .num_parents = 3, 524 .ops = &clk_rcg2_ops, 525 }, 526 }; 527 528 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 529 .cmd_rcgr = 0x1d00c, 530 .mnd_width = 8, 531 .hid_width = 5, 532 .parent_map = gcc_parent_map_0, 533 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 534 .clkr.hw.init = &(struct clk_init_data){ 535 .name = "blsp1_qup3_spi_apps_clk_src", 536 .parent_names = gcc_parent_names_0, 537 .num_parents = 4, 538 .ops = &clk_rcg2_ops, 539 }, 540 }; 541 542 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 543 .cmd_rcgr = 0x1f020, 544 .mnd_width = 0, 545 .hid_width = 5, 546 .parent_map = gcc_parent_map_1, 547 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 548 .clkr.hw.init = &(struct clk_init_data){ 549 .name = "blsp1_qup4_i2c_apps_clk_src", 550 .parent_names = gcc_parent_names_1, 551 .num_parents = 3, 552 .ops = &clk_rcg2_ops, 553 }, 554 }; 555 556 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 557 .cmd_rcgr = 0x1f00c, 558 .mnd_width = 8, 559 .hid_width = 5, 560 .parent_map = gcc_parent_map_0, 561 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 562 .clkr.hw.init = &(struct clk_init_data){ 563 .name = "blsp1_qup4_spi_apps_clk_src", 564 .parent_names = gcc_parent_names_0, 565 .num_parents = 4, 566 .ops = &clk_rcg2_ops, 567 }, 568 }; 569 570 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 571 .cmd_rcgr = 0x21020, 572 .mnd_width = 0, 573 .hid_width = 5, 574 .parent_map = gcc_parent_map_1, 575 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 576 .clkr.hw.init = &(struct clk_init_data){ 577 .name = "blsp1_qup5_i2c_apps_clk_src", 578 .parent_names = gcc_parent_names_1, 579 .num_parents = 3, 580 .ops = &clk_rcg2_ops, 581 }, 582 }; 583 584 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 585 .cmd_rcgr = 0x2100c, 586 .mnd_width = 8, 587 .hid_width = 5, 588 .parent_map = gcc_parent_map_0, 589 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 590 .clkr.hw.init = &(struct clk_init_data){ 591 .name = "blsp1_qup5_spi_apps_clk_src", 592 .parent_names = gcc_parent_names_0, 593 .num_parents = 4, 594 .ops = &clk_rcg2_ops, 595 }, 596 }; 597 598 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 599 .cmd_rcgr = 0x23020, 600 .mnd_width = 0, 601 .hid_width = 5, 602 .parent_map = gcc_parent_map_1, 603 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 604 .clkr.hw.init = &(struct clk_init_data){ 605 .name = "blsp1_qup6_i2c_apps_clk_src", 606 .parent_names = gcc_parent_names_1, 607 .num_parents = 3, 608 .ops = &clk_rcg2_ops, 609 }, 610 }; 611 612 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 613 .cmd_rcgr = 0x2300c, 614 .mnd_width = 8, 615 .hid_width = 5, 616 .parent_map = gcc_parent_map_0, 617 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 618 .clkr.hw.init = &(struct clk_init_data){ 619 .name = "blsp1_qup6_spi_apps_clk_src", 620 .parent_names = gcc_parent_names_0, 621 .num_parents = 4, 622 .ops = &clk_rcg2_ops, 623 }, 624 }; 625 626 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = { 627 F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625), 628 F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625), 629 F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625), 630 F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15), 631 F(19200000, P_XO, 1, 0, 0), 632 F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5), 633 F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75), 634 F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0), 635 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375), 636 F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), 637 F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375), 638 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75), 639 F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625), 640 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 641 F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0), 642 { } 643 }; 644 645 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 646 .cmd_rcgr = 0x1a00c, 647 .mnd_width = 16, 648 .hid_width = 5, 649 .parent_map = gcc_parent_map_0, 650 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 651 .clkr.hw.init = &(struct clk_init_data){ 652 .name = "blsp1_uart1_apps_clk_src", 653 .parent_names = gcc_parent_names_0, 654 .num_parents = 4, 655 .ops = &clk_rcg2_ops, 656 }, 657 }; 658 659 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 660 .cmd_rcgr = 0x1c00c, 661 .mnd_width = 16, 662 .hid_width = 5, 663 .parent_map = gcc_parent_map_0, 664 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 665 .clkr.hw.init = &(struct clk_init_data){ 666 .name = "blsp1_uart2_apps_clk_src", 667 .parent_names = gcc_parent_names_0, 668 .num_parents = 4, 669 .ops = &clk_rcg2_ops, 670 }, 671 }; 672 673 static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 674 .cmd_rcgr = 0x1e00c, 675 .mnd_width = 16, 676 .hid_width = 5, 677 .parent_map = gcc_parent_map_0, 678 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 679 .clkr.hw.init = &(struct clk_init_data){ 680 .name = "blsp1_uart3_apps_clk_src", 681 .parent_names = gcc_parent_names_0, 682 .num_parents = 4, 683 .ops = &clk_rcg2_ops, 684 }, 685 }; 686 687 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { 688 .cmd_rcgr = 0x26020, 689 .mnd_width = 0, 690 .hid_width = 5, 691 .parent_map = gcc_parent_map_1, 692 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 693 .clkr.hw.init = &(struct clk_init_data){ 694 .name = "blsp2_qup1_i2c_apps_clk_src", 695 .parent_names = gcc_parent_names_1, 696 .num_parents = 3, 697 .ops = &clk_rcg2_ops, 698 }, 699 }; 700 701 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { 702 .cmd_rcgr = 0x2600c, 703 .mnd_width = 8, 704 .hid_width = 5, 705 .parent_map = gcc_parent_map_0, 706 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 707 .clkr.hw.init = &(struct clk_init_data){ 708 .name = "blsp2_qup1_spi_apps_clk_src", 709 .parent_names = gcc_parent_names_0, 710 .num_parents = 4, 711 .ops = &clk_rcg2_ops, 712 }, 713 }; 714 715 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { 716 .cmd_rcgr = 0x28020, 717 .mnd_width = 0, 718 .hid_width = 5, 719 .parent_map = gcc_parent_map_1, 720 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 721 .clkr.hw.init = &(struct clk_init_data){ 722 .name = "blsp2_qup2_i2c_apps_clk_src", 723 .parent_names = gcc_parent_names_1, 724 .num_parents = 3, 725 .ops = &clk_rcg2_ops, 726 }, 727 }; 728 729 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { 730 .cmd_rcgr = 0x2800c, 731 .mnd_width = 8, 732 .hid_width = 5, 733 .parent_map = gcc_parent_map_0, 734 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 735 .clkr.hw.init = &(struct clk_init_data){ 736 .name = "blsp2_qup2_spi_apps_clk_src", 737 .parent_names = gcc_parent_names_0, 738 .num_parents = 4, 739 .ops = &clk_rcg2_ops, 740 }, 741 }; 742 743 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { 744 .cmd_rcgr = 0x2a020, 745 .mnd_width = 0, 746 .hid_width = 5, 747 .parent_map = gcc_parent_map_1, 748 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 749 .clkr.hw.init = &(struct clk_init_data){ 750 .name = "blsp2_qup3_i2c_apps_clk_src", 751 .parent_names = gcc_parent_names_1, 752 .num_parents = 3, 753 .ops = &clk_rcg2_ops, 754 }, 755 }; 756 757 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { 758 .cmd_rcgr = 0x2a00c, 759 .mnd_width = 8, 760 .hid_width = 5, 761 .parent_map = gcc_parent_map_0, 762 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 763 .clkr.hw.init = &(struct clk_init_data){ 764 .name = "blsp2_qup3_spi_apps_clk_src", 765 .parent_names = gcc_parent_names_0, 766 .num_parents = 4, 767 .ops = &clk_rcg2_ops, 768 }, 769 }; 770 771 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { 772 .cmd_rcgr = 0x2c020, 773 .mnd_width = 0, 774 .hid_width = 5, 775 .parent_map = gcc_parent_map_1, 776 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 777 .clkr.hw.init = &(struct clk_init_data){ 778 .name = "blsp2_qup4_i2c_apps_clk_src", 779 .parent_names = gcc_parent_names_1, 780 .num_parents = 3, 781 .ops = &clk_rcg2_ops, 782 }, 783 }; 784 785 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { 786 .cmd_rcgr = 0x2c00c, 787 .mnd_width = 8, 788 .hid_width = 5, 789 .parent_map = gcc_parent_map_0, 790 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 791 .clkr.hw.init = &(struct clk_init_data){ 792 .name = "blsp2_qup4_spi_apps_clk_src", 793 .parent_names = gcc_parent_names_0, 794 .num_parents = 4, 795 .ops = &clk_rcg2_ops, 796 }, 797 }; 798 799 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { 800 .cmd_rcgr = 0x2e020, 801 .mnd_width = 0, 802 .hid_width = 5, 803 .parent_map = gcc_parent_map_1, 804 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 805 .clkr.hw.init = &(struct clk_init_data){ 806 .name = "blsp2_qup5_i2c_apps_clk_src", 807 .parent_names = gcc_parent_names_1, 808 .num_parents = 3, 809 .ops = &clk_rcg2_ops, 810 }, 811 }; 812 813 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { 814 .cmd_rcgr = 0x2e00c, 815 .mnd_width = 8, 816 .hid_width = 5, 817 .parent_map = gcc_parent_map_0, 818 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 819 .clkr.hw.init = &(struct clk_init_data){ 820 .name = "blsp2_qup5_spi_apps_clk_src", 821 .parent_names = gcc_parent_names_0, 822 .num_parents = 4, 823 .ops = &clk_rcg2_ops, 824 }, 825 }; 826 827 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { 828 .cmd_rcgr = 0x30020, 829 .mnd_width = 0, 830 .hid_width = 5, 831 .parent_map = gcc_parent_map_1, 832 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 833 .clkr.hw.init = &(struct clk_init_data){ 834 .name = "blsp2_qup6_i2c_apps_clk_src", 835 .parent_names = gcc_parent_names_1, 836 .num_parents = 3, 837 .ops = &clk_rcg2_ops, 838 }, 839 }; 840 841 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { 842 .cmd_rcgr = 0x3000c, 843 .mnd_width = 8, 844 .hid_width = 5, 845 .parent_map = gcc_parent_map_0, 846 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 847 .clkr.hw.init = &(struct clk_init_data){ 848 .name = "blsp2_qup6_spi_apps_clk_src", 849 .parent_names = gcc_parent_names_0, 850 .num_parents = 4, 851 .ops = &clk_rcg2_ops, 852 }, 853 }; 854 855 static struct clk_rcg2 blsp2_uart1_apps_clk_src = { 856 .cmd_rcgr = 0x2700c, 857 .mnd_width = 16, 858 .hid_width = 5, 859 .parent_map = gcc_parent_map_0, 860 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 861 .clkr.hw.init = &(struct clk_init_data){ 862 .name = "blsp2_uart1_apps_clk_src", 863 .parent_names = gcc_parent_names_0, 864 .num_parents = 4, 865 .ops = &clk_rcg2_ops, 866 }, 867 }; 868 869 static struct clk_rcg2 blsp2_uart2_apps_clk_src = { 870 .cmd_rcgr = 0x2900c, 871 .mnd_width = 16, 872 .hid_width = 5, 873 .parent_map = gcc_parent_map_0, 874 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 875 .clkr.hw.init = &(struct clk_init_data){ 876 .name = "blsp2_uart2_apps_clk_src", 877 .parent_names = gcc_parent_names_0, 878 .num_parents = 4, 879 .ops = &clk_rcg2_ops, 880 }, 881 }; 882 883 static struct clk_rcg2 blsp2_uart3_apps_clk_src = { 884 .cmd_rcgr = 0x2b00c, 885 .mnd_width = 16, 886 .hid_width = 5, 887 .parent_map = gcc_parent_map_0, 888 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 889 .clkr.hw.init = &(struct clk_init_data){ 890 .name = "blsp2_uart3_apps_clk_src", 891 .parent_names = gcc_parent_names_0, 892 .num_parents = 4, 893 .ops = &clk_rcg2_ops, 894 }, 895 }; 896 897 static const struct freq_tbl ftbl_gp1_clk_src[] = { 898 F(19200000, P_XO, 1, 0, 0), 899 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 900 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 901 { } 902 }; 903 904 static struct clk_rcg2 gp1_clk_src = { 905 .cmd_rcgr = 0x64004, 906 .mnd_width = 8, 907 .hid_width = 5, 908 .parent_map = gcc_parent_map_2, 909 .freq_tbl = ftbl_gp1_clk_src, 910 .clkr.hw.init = &(struct clk_init_data){ 911 .name = "gp1_clk_src", 912 .parent_names = gcc_parent_names_2, 913 .num_parents = 5, 914 .ops = &clk_rcg2_ops, 915 }, 916 }; 917 918 static struct clk_rcg2 gp2_clk_src = { 919 .cmd_rcgr = 0x65004, 920 .mnd_width = 8, 921 .hid_width = 5, 922 .parent_map = gcc_parent_map_2, 923 .freq_tbl = ftbl_gp1_clk_src, 924 .clkr.hw.init = &(struct clk_init_data){ 925 .name = "gp2_clk_src", 926 .parent_names = gcc_parent_names_2, 927 .num_parents = 5, 928 .ops = &clk_rcg2_ops, 929 }, 930 }; 931 932 static struct clk_rcg2 gp3_clk_src = { 933 .cmd_rcgr = 0x66004, 934 .mnd_width = 8, 935 .hid_width = 5, 936 .parent_map = gcc_parent_map_2, 937 .freq_tbl = ftbl_gp1_clk_src, 938 .clkr.hw.init = &(struct clk_init_data){ 939 .name = "gp3_clk_src", 940 .parent_names = gcc_parent_names_2, 941 .num_parents = 5, 942 .ops = &clk_rcg2_ops, 943 }, 944 }; 945 946 static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = { 947 F(19200000, P_XO, 1, 0, 0), 948 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), 949 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 950 { } 951 }; 952 953 static struct clk_rcg2 hmss_ahb_clk_src = { 954 .cmd_rcgr = 0x48014, 955 .mnd_width = 0, 956 .hid_width = 5, 957 .parent_map = gcc_parent_map_1, 958 .freq_tbl = ftbl_hmss_ahb_clk_src, 959 .clkr.hw.init = &(struct clk_init_data){ 960 .name = "hmss_ahb_clk_src", 961 .parent_names = gcc_parent_names_1, 962 .num_parents = 3, 963 .ops = &clk_rcg2_ops, 964 }, 965 }; 966 967 static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { 968 F(19200000, P_XO, 1, 0, 0), 969 { } 970 }; 971 972 static struct clk_rcg2 hmss_rbcpr_clk_src = { 973 .cmd_rcgr = 0x48044, 974 .mnd_width = 0, 975 .hid_width = 5, 976 .parent_map = gcc_parent_map_1, 977 .freq_tbl = ftbl_hmss_rbcpr_clk_src, 978 .clkr.hw.init = &(struct clk_init_data){ 979 .name = "hmss_rbcpr_clk_src", 980 .parent_names = gcc_parent_names_1, 981 .num_parents = 3, 982 .ops = &clk_rcg2_ops, 983 }, 984 }; 985 986 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = { 987 F(1010526, P_XO, 1, 1, 19), 988 { } 989 }; 990 991 static struct clk_rcg2 pcie_aux_clk_src = { 992 .cmd_rcgr = 0x6c000, 993 .mnd_width = 16, 994 .hid_width = 5, 995 .parent_map = gcc_parent_map_3, 996 .freq_tbl = ftbl_pcie_aux_clk_src, 997 .clkr.hw.init = &(struct clk_init_data){ 998 .name = "pcie_aux_clk_src", 999 .parent_names = gcc_parent_names_3, 1000 .num_parents = 3, 1001 .ops = &clk_rcg2_ops, 1002 }, 1003 }; 1004 1005 static const struct freq_tbl ftbl_pdm2_clk_src[] = { 1006 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 1007 { } 1008 }; 1009 1010 static struct clk_rcg2 pdm2_clk_src = { 1011 .cmd_rcgr = 0x33010, 1012 .mnd_width = 0, 1013 .hid_width = 5, 1014 .parent_map = gcc_parent_map_1, 1015 .freq_tbl = ftbl_pdm2_clk_src, 1016 .clkr.hw.init = &(struct clk_init_data){ 1017 .name = "pdm2_clk_src", 1018 .parent_names = gcc_parent_names_1, 1019 .num_parents = 3, 1020 .ops = &clk_rcg2_ops, 1021 }, 1022 }; 1023 1024 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = { 1025 F(144000, P_XO, 16, 3, 25), 1026 F(400000, P_XO, 12, 1, 4), 1027 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2), 1028 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 1029 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 1030 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 1031 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 1032 { } 1033 }; 1034 1035 static struct clk_rcg2 sdcc2_apps_clk_src = { 1036 .cmd_rcgr = 0x14010, 1037 .mnd_width = 8, 1038 .hid_width = 5, 1039 .parent_map = gcc_parent_map_4, 1040 .freq_tbl = ftbl_sdcc2_apps_clk_src, 1041 .clkr.hw.init = &(struct clk_init_data){ 1042 .name = "sdcc2_apps_clk_src", 1043 .parent_names = gcc_parent_names_4, 1044 .num_parents = 4, 1045 .ops = &clk_rcg2_floor_ops, 1046 }, 1047 }; 1048 1049 static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = { 1050 F(144000, P_XO, 16, 3, 25), 1051 F(400000, P_XO, 12, 1, 4), 1052 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2), 1053 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 1054 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 1055 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 1056 { } 1057 }; 1058 1059 static struct clk_rcg2 sdcc4_apps_clk_src = { 1060 .cmd_rcgr = 0x16010, 1061 .mnd_width = 8, 1062 .hid_width = 5, 1063 .parent_map = gcc_parent_map_1, 1064 .freq_tbl = ftbl_sdcc4_apps_clk_src, 1065 .clkr.hw.init = &(struct clk_init_data){ 1066 .name = "sdcc4_apps_clk_src", 1067 .parent_names = gcc_parent_names_1, 1068 .num_parents = 3, 1069 .ops = &clk_rcg2_floor_ops, 1070 }, 1071 }; 1072 1073 static const struct freq_tbl ftbl_tsif_ref_clk_src[] = { 1074 F(105495, P_XO, 1, 1, 182), 1075 { } 1076 }; 1077 1078 static struct clk_rcg2 tsif_ref_clk_src = { 1079 .cmd_rcgr = 0x36010, 1080 .mnd_width = 8, 1081 .hid_width = 5, 1082 .parent_map = gcc_parent_map_5, 1083 .freq_tbl = ftbl_tsif_ref_clk_src, 1084 .clkr.hw.init = &(struct clk_init_data){ 1085 .name = "tsif_ref_clk_src", 1086 .parent_names = gcc_parent_names_5, 1087 .num_parents = 4, 1088 .ops = &clk_rcg2_ops, 1089 }, 1090 }; 1091 1092 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = { 1093 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 1094 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 1095 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 1096 { } 1097 }; 1098 1099 static struct clk_rcg2 ufs_axi_clk_src = { 1100 .cmd_rcgr = 0x75018, 1101 .mnd_width = 8, 1102 .hid_width = 5, 1103 .parent_map = gcc_parent_map_0, 1104 .freq_tbl = ftbl_ufs_axi_clk_src, 1105 .clkr.hw.init = &(struct clk_init_data){ 1106 .name = "ufs_axi_clk_src", 1107 .parent_names = gcc_parent_names_0, 1108 .num_parents = 4, 1109 .ops = &clk_rcg2_ops, 1110 }, 1111 }; 1112 1113 static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = { 1114 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), 1115 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 1116 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 1117 { } 1118 }; 1119 1120 static struct clk_rcg2 ufs_unipro_core_clk_src = { 1121 .cmd_rcgr = 0x76028, 1122 .mnd_width = 8, 1123 .hid_width = 5, 1124 .parent_map = gcc_parent_map_0, 1125 .freq_tbl = ftbl_ufs_unipro_core_clk_src, 1126 .clkr.hw.init = &(struct clk_init_data){ 1127 .name = "ufs_unipro_core_clk_src", 1128 .parent_names = gcc_parent_names_0, 1129 .num_parents = 4, 1130 .ops = &clk_rcg2_ops, 1131 }, 1132 }; 1133 1134 static const struct freq_tbl ftbl_usb30_master_clk_src[] = { 1135 F(19200000, P_XO, 1, 0, 0), 1136 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 1137 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), 1138 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 1139 { } 1140 }; 1141 1142 static struct clk_rcg2 usb30_master_clk_src = { 1143 .cmd_rcgr = 0xf014, 1144 .mnd_width = 8, 1145 .hid_width = 5, 1146 .parent_map = gcc_parent_map_0, 1147 .freq_tbl = ftbl_usb30_master_clk_src, 1148 .clkr.hw.init = &(struct clk_init_data){ 1149 .name = "usb30_master_clk_src", 1150 .parent_names = gcc_parent_names_0, 1151 .num_parents = 4, 1152 .ops = &clk_rcg2_ops, 1153 }, 1154 }; 1155 1156 static struct clk_rcg2 usb30_mock_utmi_clk_src = { 1157 .cmd_rcgr = 0xf028, 1158 .mnd_width = 0, 1159 .hid_width = 5, 1160 .parent_map = gcc_parent_map_0, 1161 .freq_tbl = ftbl_hmss_rbcpr_clk_src, 1162 .clkr.hw.init = &(struct clk_init_data){ 1163 .name = "usb30_mock_utmi_clk_src", 1164 .parent_names = gcc_parent_names_0, 1165 .num_parents = 4, 1166 .ops = &clk_rcg2_ops, 1167 }, 1168 }; 1169 1170 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { 1171 F(1200000, P_XO, 16, 0, 0), 1172 { } 1173 }; 1174 1175 static struct clk_rcg2 usb3_phy_aux_clk_src = { 1176 .cmd_rcgr = 0x5000c, 1177 .mnd_width = 0, 1178 .hid_width = 5, 1179 .parent_map = gcc_parent_map_3, 1180 .freq_tbl = ftbl_usb3_phy_aux_clk_src, 1181 .clkr.hw.init = &(struct clk_init_data){ 1182 .name = "usb3_phy_aux_clk_src", 1183 .parent_names = gcc_parent_names_3, 1184 .num_parents = 3, 1185 .ops = &clk_rcg2_ops, 1186 }, 1187 }; 1188 1189 static struct clk_branch gcc_aggre1_noc_xo_clk = { 1190 .halt_reg = 0x8202c, 1191 .halt_check = BRANCH_HALT, 1192 .clkr = { 1193 .enable_reg = 0x8202c, 1194 .enable_mask = BIT(0), 1195 .hw.init = &(struct clk_init_data){ 1196 .name = "gcc_aggre1_noc_xo_clk", 1197 .ops = &clk_branch2_ops, 1198 }, 1199 }, 1200 }; 1201 1202 static struct clk_branch gcc_aggre1_ufs_axi_clk = { 1203 .halt_reg = 0x82028, 1204 .halt_check = BRANCH_HALT, 1205 .clkr = { 1206 .enable_reg = 0x82028, 1207 .enable_mask = BIT(0), 1208 .hw.init = &(struct clk_init_data){ 1209 .name = "gcc_aggre1_ufs_axi_clk", 1210 .parent_names = (const char *[]){ 1211 "ufs_axi_clk_src", 1212 }, 1213 .num_parents = 1, 1214 .flags = CLK_SET_RATE_PARENT, 1215 .ops = &clk_branch2_ops, 1216 }, 1217 }, 1218 }; 1219 1220 static struct clk_branch gcc_aggre1_usb3_axi_clk = { 1221 .halt_reg = 0x82024, 1222 .halt_check = BRANCH_HALT, 1223 .clkr = { 1224 .enable_reg = 0x82024, 1225 .enable_mask = BIT(0), 1226 .hw.init = &(struct clk_init_data){ 1227 .name = "gcc_aggre1_usb3_axi_clk", 1228 .parent_names = (const char *[]){ 1229 "usb30_master_clk_src", 1230 }, 1231 .num_parents = 1, 1232 .flags = CLK_SET_RATE_PARENT, 1233 .ops = &clk_branch2_ops, 1234 }, 1235 }, 1236 }; 1237 1238 static struct clk_branch gcc_apss_qdss_tsctr_div2_clk = { 1239 .halt_reg = 0x48090, 1240 .halt_check = BRANCH_HALT, 1241 .clkr = { 1242 .enable_reg = 0x48090, 1243 .enable_mask = BIT(0), 1244 .hw.init = &(struct clk_init_data){ 1245 .name = "gcc_apss_qdss_tsctr_div2_clk", 1246 .ops = &clk_branch2_ops, 1247 }, 1248 }, 1249 }; 1250 1251 static struct clk_branch gcc_apss_qdss_tsctr_div8_clk = { 1252 .halt_reg = 0x48094, 1253 .halt_check = BRANCH_HALT, 1254 .clkr = { 1255 .enable_reg = 0x48094, 1256 .enable_mask = BIT(0), 1257 .hw.init = &(struct clk_init_data){ 1258 .name = "gcc_apss_qdss_tsctr_div8_clk", 1259 .ops = &clk_branch2_ops, 1260 }, 1261 }, 1262 }; 1263 1264 static struct clk_branch gcc_bimc_hmss_axi_clk = { 1265 .halt_reg = 0x48004, 1266 .halt_check = BRANCH_HALT_VOTED, 1267 .clkr = { 1268 .enable_reg = 0x52004, 1269 .enable_mask = BIT(22), 1270 .hw.init = &(struct clk_init_data){ 1271 .name = "gcc_bimc_hmss_axi_clk", 1272 .ops = &clk_branch2_ops, 1273 }, 1274 }, 1275 }; 1276 1277 static struct clk_branch gcc_bimc_mss_q6_axi_clk = { 1278 .halt_reg = 0x4401c, 1279 .halt_check = BRANCH_HALT, 1280 .clkr = { 1281 .enable_reg = 0x4401c, 1282 .enable_mask = BIT(0), 1283 .hw.init = &(struct clk_init_data){ 1284 .name = "gcc_bimc_mss_q6_axi_clk", 1285 .ops = &clk_branch2_ops, 1286 }, 1287 }, 1288 }; 1289 1290 static struct clk_branch gcc_mss_cfg_ahb_clk = { 1291 .halt_reg = 0x8a000, 1292 .halt_check = BRANCH_HALT, 1293 .clkr = { 1294 .enable_reg = 0x8a000, 1295 .enable_mask = BIT(0), 1296 .hw.init = &(struct clk_init_data){ 1297 .name = "gcc_mss_cfg_ahb_clk", 1298 .ops = &clk_branch2_ops, 1299 }, 1300 }, 1301 }; 1302 1303 static struct clk_branch gcc_mss_snoc_axi_clk = { 1304 .halt_reg = 0x8a03c, 1305 .halt_check = BRANCH_HALT, 1306 .clkr = { 1307 .enable_reg = 0x8a03c, 1308 .enable_mask = BIT(0), 1309 .hw.init = &(struct clk_init_data){ 1310 .name = "gcc_mss_snoc_axi_clk", 1311 .ops = &clk_branch2_ops, 1312 }, 1313 }, 1314 }; 1315 1316 static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = { 1317 .halt_reg = 0x8a004, 1318 .halt_check = BRANCH_HALT, 1319 .clkr = { 1320 .enable_reg = 0x8a004, 1321 .enable_mask = BIT(0), 1322 .hw.init = &(struct clk_init_data){ 1323 .name = "gcc_mss_mnoc_bimc_axi_clk", 1324 .ops = &clk_branch2_ops, 1325 }, 1326 }, 1327 }; 1328 1329 static struct clk_branch gcc_boot_rom_ahb_clk = { 1330 .halt_reg = 0x38004, 1331 .halt_check = BRANCH_HALT_VOTED, 1332 .hwcg_reg = 0x38004, 1333 .hwcg_bit = 1, 1334 .clkr = { 1335 .enable_reg = 0x52004, 1336 .enable_mask = BIT(10), 1337 .hw.init = &(struct clk_init_data){ 1338 .name = "gcc_boot_rom_ahb_clk", 1339 .ops = &clk_branch2_ops, 1340 }, 1341 }, 1342 }; 1343 1344 static struct clk_branch gcc_mmss_gpll0_clk = { 1345 .halt_check = BRANCH_HALT_DELAY, 1346 .clkr = { 1347 .enable_reg = 0x5200c, 1348 .enable_mask = BIT(1), 1349 .hw.init = &(struct clk_init_data){ 1350 .name = "gcc_mmss_gpll0_clk", 1351 .parent_names = (const char *[]){ 1352 "gpll0_out_main", 1353 }, 1354 .num_parents = 1, 1355 .ops = &clk_branch2_ops, 1356 }, 1357 }, 1358 }; 1359 1360 static struct clk_branch gcc_mss_gpll0_div_clk_src = { 1361 .halt_check = BRANCH_HALT_DELAY, 1362 .clkr = { 1363 .enable_reg = 0x5200c, 1364 .enable_mask = BIT(2), 1365 .hw.init = &(struct clk_init_data){ 1366 .name = "gcc_mss_gpll0_div_clk_src", 1367 .ops = &clk_branch2_ops, 1368 }, 1369 }, 1370 }; 1371 1372 static struct clk_branch gcc_blsp1_ahb_clk = { 1373 .halt_reg = 0x17004, 1374 .halt_check = BRANCH_HALT_VOTED, 1375 .clkr = { 1376 .enable_reg = 0x52004, 1377 .enable_mask = BIT(17), 1378 .hw.init = &(struct clk_init_data){ 1379 .name = "gcc_blsp1_ahb_clk", 1380 .ops = &clk_branch2_ops, 1381 }, 1382 }, 1383 }; 1384 1385 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1386 .halt_reg = 0x19008, 1387 .halt_check = BRANCH_HALT, 1388 .clkr = { 1389 .enable_reg = 0x19008, 1390 .enable_mask = BIT(0), 1391 .hw.init = &(struct clk_init_data){ 1392 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1393 .parent_names = (const char *[]){ 1394 "blsp1_qup1_i2c_apps_clk_src", 1395 }, 1396 .num_parents = 1, 1397 .flags = CLK_SET_RATE_PARENT, 1398 .ops = &clk_branch2_ops, 1399 }, 1400 }, 1401 }; 1402 1403 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1404 .halt_reg = 0x19004, 1405 .halt_check = BRANCH_HALT, 1406 .clkr = { 1407 .enable_reg = 0x19004, 1408 .enable_mask = BIT(0), 1409 .hw.init = &(struct clk_init_data){ 1410 .name = "gcc_blsp1_qup1_spi_apps_clk", 1411 .parent_names = (const char *[]){ 1412 "blsp1_qup1_spi_apps_clk_src", 1413 }, 1414 .num_parents = 1, 1415 .flags = CLK_SET_RATE_PARENT, 1416 .ops = &clk_branch2_ops, 1417 }, 1418 }, 1419 }; 1420 1421 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1422 .halt_reg = 0x1b008, 1423 .halt_check = BRANCH_HALT, 1424 .clkr = { 1425 .enable_reg = 0x1b008, 1426 .enable_mask = BIT(0), 1427 .hw.init = &(struct clk_init_data){ 1428 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1429 .parent_names = (const char *[]){ 1430 "blsp1_qup2_i2c_apps_clk_src", 1431 }, 1432 .num_parents = 1, 1433 .flags = CLK_SET_RATE_PARENT, 1434 .ops = &clk_branch2_ops, 1435 }, 1436 }, 1437 }; 1438 1439 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1440 .halt_reg = 0x1b004, 1441 .halt_check = BRANCH_HALT, 1442 .clkr = { 1443 .enable_reg = 0x1b004, 1444 .enable_mask = BIT(0), 1445 .hw.init = &(struct clk_init_data){ 1446 .name = "gcc_blsp1_qup2_spi_apps_clk", 1447 .parent_names = (const char *[]){ 1448 "blsp1_qup2_spi_apps_clk_src", 1449 }, 1450 .num_parents = 1, 1451 .flags = CLK_SET_RATE_PARENT, 1452 .ops = &clk_branch2_ops, 1453 }, 1454 }, 1455 }; 1456 1457 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1458 .halt_reg = 0x1d008, 1459 .halt_check = BRANCH_HALT, 1460 .clkr = { 1461 .enable_reg = 0x1d008, 1462 .enable_mask = BIT(0), 1463 .hw.init = &(struct clk_init_data){ 1464 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1465 .parent_names = (const char *[]){ 1466 "blsp1_qup3_i2c_apps_clk_src", 1467 }, 1468 .num_parents = 1, 1469 .flags = CLK_SET_RATE_PARENT, 1470 .ops = &clk_branch2_ops, 1471 }, 1472 }, 1473 }; 1474 1475 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1476 .halt_reg = 0x1d004, 1477 .halt_check = BRANCH_HALT, 1478 .clkr = { 1479 .enable_reg = 0x1d004, 1480 .enable_mask = BIT(0), 1481 .hw.init = &(struct clk_init_data){ 1482 .name = "gcc_blsp1_qup3_spi_apps_clk", 1483 .parent_names = (const char *[]){ 1484 "blsp1_qup3_spi_apps_clk_src", 1485 }, 1486 .num_parents = 1, 1487 .flags = CLK_SET_RATE_PARENT, 1488 .ops = &clk_branch2_ops, 1489 }, 1490 }, 1491 }; 1492 1493 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1494 .halt_reg = 0x1f008, 1495 .halt_check = BRANCH_HALT, 1496 .clkr = { 1497 .enable_reg = 0x1f008, 1498 .enable_mask = BIT(0), 1499 .hw.init = &(struct clk_init_data){ 1500 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1501 .parent_names = (const char *[]){ 1502 "blsp1_qup4_i2c_apps_clk_src", 1503 }, 1504 .num_parents = 1, 1505 .flags = CLK_SET_RATE_PARENT, 1506 .ops = &clk_branch2_ops, 1507 }, 1508 }, 1509 }; 1510 1511 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1512 .halt_reg = 0x1f004, 1513 .halt_check = BRANCH_HALT, 1514 .clkr = { 1515 .enable_reg = 0x1f004, 1516 .enable_mask = BIT(0), 1517 .hw.init = &(struct clk_init_data){ 1518 .name = "gcc_blsp1_qup4_spi_apps_clk", 1519 .parent_names = (const char *[]){ 1520 "blsp1_qup4_spi_apps_clk_src", 1521 }, 1522 .num_parents = 1, 1523 .flags = CLK_SET_RATE_PARENT, 1524 .ops = &clk_branch2_ops, 1525 }, 1526 }, 1527 }; 1528 1529 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1530 .halt_reg = 0x21008, 1531 .halt_check = BRANCH_HALT, 1532 .clkr = { 1533 .enable_reg = 0x21008, 1534 .enable_mask = BIT(0), 1535 .hw.init = &(struct clk_init_data){ 1536 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1537 .parent_names = (const char *[]){ 1538 "blsp1_qup5_i2c_apps_clk_src", 1539 }, 1540 .num_parents = 1, 1541 .flags = CLK_SET_RATE_PARENT, 1542 .ops = &clk_branch2_ops, 1543 }, 1544 }, 1545 }; 1546 1547 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1548 .halt_reg = 0x21004, 1549 .halt_check = BRANCH_HALT, 1550 .clkr = { 1551 .enable_reg = 0x21004, 1552 .enable_mask = BIT(0), 1553 .hw.init = &(struct clk_init_data){ 1554 .name = "gcc_blsp1_qup5_spi_apps_clk", 1555 .parent_names = (const char *[]){ 1556 "blsp1_qup5_spi_apps_clk_src", 1557 }, 1558 .num_parents = 1, 1559 .flags = CLK_SET_RATE_PARENT, 1560 .ops = &clk_branch2_ops, 1561 }, 1562 }, 1563 }; 1564 1565 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1566 .halt_reg = 0x23008, 1567 .halt_check = BRANCH_HALT, 1568 .clkr = { 1569 .enable_reg = 0x23008, 1570 .enable_mask = BIT(0), 1571 .hw.init = &(struct clk_init_data){ 1572 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1573 .parent_names = (const char *[]){ 1574 "blsp1_qup6_i2c_apps_clk_src", 1575 }, 1576 .num_parents = 1, 1577 .flags = CLK_SET_RATE_PARENT, 1578 .ops = &clk_branch2_ops, 1579 }, 1580 }, 1581 }; 1582 1583 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1584 .halt_reg = 0x23004, 1585 .halt_check = BRANCH_HALT, 1586 .clkr = { 1587 .enable_reg = 0x23004, 1588 .enable_mask = BIT(0), 1589 .hw.init = &(struct clk_init_data){ 1590 .name = "gcc_blsp1_qup6_spi_apps_clk", 1591 .parent_names = (const char *[]){ 1592 "blsp1_qup6_spi_apps_clk_src", 1593 }, 1594 .num_parents = 1, 1595 .flags = CLK_SET_RATE_PARENT, 1596 .ops = &clk_branch2_ops, 1597 }, 1598 }, 1599 }; 1600 1601 static struct clk_branch gcc_blsp1_sleep_clk = { 1602 .halt_reg = 0x17008, 1603 .halt_check = BRANCH_HALT_VOTED, 1604 .clkr = { 1605 .enable_reg = 0x52004, 1606 .enable_mask = BIT(16), 1607 .hw.init = &(struct clk_init_data){ 1608 .name = "gcc_blsp1_sleep_clk", 1609 .ops = &clk_branch2_ops, 1610 }, 1611 }, 1612 }; 1613 1614 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1615 .halt_reg = 0x1a004, 1616 .halt_check = BRANCH_HALT, 1617 .clkr = { 1618 .enable_reg = 0x1a004, 1619 .enable_mask = BIT(0), 1620 .hw.init = &(struct clk_init_data){ 1621 .name = "gcc_blsp1_uart1_apps_clk", 1622 .parent_names = (const char *[]){ 1623 "blsp1_uart1_apps_clk_src", 1624 }, 1625 .num_parents = 1, 1626 .flags = CLK_SET_RATE_PARENT, 1627 .ops = &clk_branch2_ops, 1628 }, 1629 }, 1630 }; 1631 1632 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1633 .halt_reg = 0x1c004, 1634 .halt_check = BRANCH_HALT, 1635 .clkr = { 1636 .enable_reg = 0x1c004, 1637 .enable_mask = BIT(0), 1638 .hw.init = &(struct clk_init_data){ 1639 .name = "gcc_blsp1_uart2_apps_clk", 1640 .parent_names = (const char *[]){ 1641 "blsp1_uart2_apps_clk_src", 1642 }, 1643 .num_parents = 1, 1644 .flags = CLK_SET_RATE_PARENT, 1645 .ops = &clk_branch2_ops, 1646 }, 1647 }, 1648 }; 1649 1650 static struct clk_branch gcc_blsp1_uart3_apps_clk = { 1651 .halt_reg = 0x1e004, 1652 .halt_check = BRANCH_HALT, 1653 .clkr = { 1654 .enable_reg = 0x1e004, 1655 .enable_mask = BIT(0), 1656 .hw.init = &(struct clk_init_data){ 1657 .name = "gcc_blsp1_uart3_apps_clk", 1658 .parent_names = (const char *[]){ 1659 "blsp1_uart3_apps_clk_src", 1660 }, 1661 .num_parents = 1, 1662 .flags = CLK_SET_RATE_PARENT, 1663 .ops = &clk_branch2_ops, 1664 }, 1665 }, 1666 }; 1667 1668 static struct clk_branch gcc_blsp2_ahb_clk = { 1669 .halt_reg = 0x25004, 1670 .halt_check = BRANCH_HALT_VOTED, 1671 .clkr = { 1672 .enable_reg = 0x52004, 1673 .enable_mask = BIT(15), 1674 .hw.init = &(struct clk_init_data){ 1675 .name = "gcc_blsp2_ahb_clk", 1676 .ops = &clk_branch2_ops, 1677 }, 1678 }, 1679 }; 1680 1681 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { 1682 .halt_reg = 0x26008, 1683 .halt_check = BRANCH_HALT, 1684 .clkr = { 1685 .enable_reg = 0x26008, 1686 .enable_mask = BIT(0), 1687 .hw.init = &(struct clk_init_data){ 1688 .name = "gcc_blsp2_qup1_i2c_apps_clk", 1689 .parent_names = (const char *[]){ 1690 "blsp2_qup1_i2c_apps_clk_src", 1691 }, 1692 .num_parents = 1, 1693 .flags = CLK_SET_RATE_PARENT, 1694 .ops = &clk_branch2_ops, 1695 }, 1696 }, 1697 }; 1698 1699 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { 1700 .halt_reg = 0x26004, 1701 .halt_check = BRANCH_HALT, 1702 .clkr = { 1703 .enable_reg = 0x26004, 1704 .enable_mask = BIT(0), 1705 .hw.init = &(struct clk_init_data){ 1706 .name = "gcc_blsp2_qup1_spi_apps_clk", 1707 .parent_names = (const char *[]){ 1708 "blsp2_qup1_spi_apps_clk_src", 1709 }, 1710 .num_parents = 1, 1711 .flags = CLK_SET_RATE_PARENT, 1712 .ops = &clk_branch2_ops, 1713 }, 1714 }, 1715 }; 1716 1717 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { 1718 .halt_reg = 0x28008, 1719 .halt_check = BRANCH_HALT, 1720 .clkr = { 1721 .enable_reg = 0x28008, 1722 .enable_mask = BIT(0), 1723 .hw.init = &(struct clk_init_data){ 1724 .name = "gcc_blsp2_qup2_i2c_apps_clk", 1725 .parent_names = (const char *[]){ 1726 "blsp2_qup2_i2c_apps_clk_src", 1727 }, 1728 .num_parents = 1, 1729 .flags = CLK_SET_RATE_PARENT, 1730 .ops = &clk_branch2_ops, 1731 }, 1732 }, 1733 }; 1734 1735 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { 1736 .halt_reg = 0x28004, 1737 .halt_check = BRANCH_HALT, 1738 .clkr = { 1739 .enable_reg = 0x28004, 1740 .enable_mask = BIT(0), 1741 .hw.init = &(struct clk_init_data){ 1742 .name = "gcc_blsp2_qup2_spi_apps_clk", 1743 .parent_names = (const char *[]){ 1744 "blsp2_qup2_spi_apps_clk_src", 1745 }, 1746 .num_parents = 1, 1747 .flags = CLK_SET_RATE_PARENT, 1748 .ops = &clk_branch2_ops, 1749 }, 1750 }, 1751 }; 1752 1753 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { 1754 .halt_reg = 0x2a008, 1755 .halt_check = BRANCH_HALT, 1756 .clkr = { 1757 .enable_reg = 0x2a008, 1758 .enable_mask = BIT(0), 1759 .hw.init = &(struct clk_init_data){ 1760 .name = "gcc_blsp2_qup3_i2c_apps_clk", 1761 .parent_names = (const char *[]){ 1762 "blsp2_qup3_i2c_apps_clk_src", 1763 }, 1764 .num_parents = 1, 1765 .flags = CLK_SET_RATE_PARENT, 1766 .ops = &clk_branch2_ops, 1767 }, 1768 }, 1769 }; 1770 1771 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { 1772 .halt_reg = 0x2a004, 1773 .halt_check = BRANCH_HALT, 1774 .clkr = { 1775 .enable_reg = 0x2a004, 1776 .enable_mask = BIT(0), 1777 .hw.init = &(struct clk_init_data){ 1778 .name = "gcc_blsp2_qup3_spi_apps_clk", 1779 .parent_names = (const char *[]){ 1780 "blsp2_qup3_spi_apps_clk_src", 1781 }, 1782 .num_parents = 1, 1783 .flags = CLK_SET_RATE_PARENT, 1784 .ops = &clk_branch2_ops, 1785 }, 1786 }, 1787 }; 1788 1789 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { 1790 .halt_reg = 0x2c008, 1791 .halt_check = BRANCH_HALT, 1792 .clkr = { 1793 .enable_reg = 0x2c008, 1794 .enable_mask = BIT(0), 1795 .hw.init = &(struct clk_init_data){ 1796 .name = "gcc_blsp2_qup4_i2c_apps_clk", 1797 .parent_names = (const char *[]){ 1798 "blsp2_qup4_i2c_apps_clk_src", 1799 }, 1800 .num_parents = 1, 1801 .flags = CLK_SET_RATE_PARENT, 1802 .ops = &clk_branch2_ops, 1803 }, 1804 }, 1805 }; 1806 1807 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { 1808 .halt_reg = 0x2c004, 1809 .halt_check = BRANCH_HALT, 1810 .clkr = { 1811 .enable_reg = 0x2c004, 1812 .enable_mask = BIT(0), 1813 .hw.init = &(struct clk_init_data){ 1814 .name = "gcc_blsp2_qup4_spi_apps_clk", 1815 .parent_names = (const char *[]){ 1816 "blsp2_qup4_spi_apps_clk_src", 1817 }, 1818 .num_parents = 1, 1819 .flags = CLK_SET_RATE_PARENT, 1820 .ops = &clk_branch2_ops, 1821 }, 1822 }, 1823 }; 1824 1825 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { 1826 .halt_reg = 0x2e008, 1827 .halt_check = BRANCH_HALT, 1828 .clkr = { 1829 .enable_reg = 0x2e008, 1830 .enable_mask = BIT(0), 1831 .hw.init = &(struct clk_init_data){ 1832 .name = "gcc_blsp2_qup5_i2c_apps_clk", 1833 .parent_names = (const char *[]){ 1834 "blsp2_qup5_i2c_apps_clk_src", 1835 }, 1836 .num_parents = 1, 1837 .flags = CLK_SET_RATE_PARENT, 1838 .ops = &clk_branch2_ops, 1839 }, 1840 }, 1841 }; 1842 1843 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { 1844 .halt_reg = 0x2e004, 1845 .halt_check = BRANCH_HALT, 1846 .clkr = { 1847 .enable_reg = 0x2e004, 1848 .enable_mask = BIT(0), 1849 .hw.init = &(struct clk_init_data){ 1850 .name = "gcc_blsp2_qup5_spi_apps_clk", 1851 .parent_names = (const char *[]){ 1852 "blsp2_qup5_spi_apps_clk_src", 1853 }, 1854 .num_parents = 1, 1855 .flags = CLK_SET_RATE_PARENT, 1856 .ops = &clk_branch2_ops, 1857 }, 1858 }, 1859 }; 1860 1861 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { 1862 .halt_reg = 0x30008, 1863 .halt_check = BRANCH_HALT, 1864 .clkr = { 1865 .enable_reg = 0x30008, 1866 .enable_mask = BIT(0), 1867 .hw.init = &(struct clk_init_data){ 1868 .name = "gcc_blsp2_qup6_i2c_apps_clk", 1869 .parent_names = (const char *[]){ 1870 "blsp2_qup6_i2c_apps_clk_src", 1871 }, 1872 .num_parents = 1, 1873 .flags = CLK_SET_RATE_PARENT, 1874 .ops = &clk_branch2_ops, 1875 }, 1876 }, 1877 }; 1878 1879 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { 1880 .halt_reg = 0x30004, 1881 .halt_check = BRANCH_HALT, 1882 .clkr = { 1883 .enable_reg = 0x30004, 1884 .enable_mask = BIT(0), 1885 .hw.init = &(struct clk_init_data){ 1886 .name = "gcc_blsp2_qup6_spi_apps_clk", 1887 .parent_names = (const char *[]){ 1888 "blsp2_qup6_spi_apps_clk_src", 1889 }, 1890 .num_parents = 1, 1891 .flags = CLK_SET_RATE_PARENT, 1892 .ops = &clk_branch2_ops, 1893 }, 1894 }, 1895 }; 1896 1897 static struct clk_branch gcc_blsp2_sleep_clk = { 1898 .halt_reg = 0x25008, 1899 .halt_check = BRANCH_HALT_VOTED, 1900 .clkr = { 1901 .enable_reg = 0x52004, 1902 .enable_mask = BIT(14), 1903 .hw.init = &(struct clk_init_data){ 1904 .name = "gcc_blsp2_sleep_clk", 1905 .ops = &clk_branch2_ops, 1906 }, 1907 }, 1908 }; 1909 1910 static struct clk_branch gcc_blsp2_uart1_apps_clk = { 1911 .halt_reg = 0x27004, 1912 .halt_check = BRANCH_HALT, 1913 .clkr = { 1914 .enable_reg = 0x27004, 1915 .enable_mask = BIT(0), 1916 .hw.init = &(struct clk_init_data){ 1917 .name = "gcc_blsp2_uart1_apps_clk", 1918 .parent_names = (const char *[]){ 1919 "blsp2_uart1_apps_clk_src", 1920 }, 1921 .num_parents = 1, 1922 .flags = CLK_SET_RATE_PARENT, 1923 .ops = &clk_branch2_ops, 1924 }, 1925 }, 1926 }; 1927 1928 static struct clk_branch gcc_blsp2_uart2_apps_clk = { 1929 .halt_reg = 0x29004, 1930 .halt_check = BRANCH_HALT, 1931 .clkr = { 1932 .enable_reg = 0x29004, 1933 .enable_mask = BIT(0), 1934 .hw.init = &(struct clk_init_data){ 1935 .name = "gcc_blsp2_uart2_apps_clk", 1936 .parent_names = (const char *[]){ 1937 "blsp2_uart2_apps_clk_src", 1938 }, 1939 .num_parents = 1, 1940 .flags = CLK_SET_RATE_PARENT, 1941 .ops = &clk_branch2_ops, 1942 }, 1943 }, 1944 }; 1945 1946 static struct clk_branch gcc_blsp2_uart3_apps_clk = { 1947 .halt_reg = 0x2b004, 1948 .halt_check = BRANCH_HALT, 1949 .clkr = { 1950 .enable_reg = 0x2b004, 1951 .enable_mask = BIT(0), 1952 .hw.init = &(struct clk_init_data){ 1953 .name = "gcc_blsp2_uart3_apps_clk", 1954 .parent_names = (const char *[]){ 1955 "blsp2_uart3_apps_clk_src", 1956 }, 1957 .num_parents = 1, 1958 .flags = CLK_SET_RATE_PARENT, 1959 .ops = &clk_branch2_ops, 1960 }, 1961 }, 1962 }; 1963 1964 static struct clk_branch gcc_cfg_noc_usb3_axi_clk = { 1965 .halt_reg = 0x5018, 1966 .halt_check = BRANCH_HALT, 1967 .clkr = { 1968 .enable_reg = 0x5018, 1969 .enable_mask = BIT(0), 1970 .hw.init = &(struct clk_init_data){ 1971 .name = "gcc_cfg_noc_usb3_axi_clk", 1972 .parent_names = (const char *[]){ 1973 "usb30_master_clk_src", 1974 }, 1975 .num_parents = 1, 1976 .flags = CLK_SET_RATE_PARENT, 1977 .ops = &clk_branch2_ops, 1978 }, 1979 }, 1980 }; 1981 1982 static struct clk_branch gcc_gp1_clk = { 1983 .halt_reg = 0x64000, 1984 .halt_check = BRANCH_HALT, 1985 .clkr = { 1986 .enable_reg = 0x64000, 1987 .enable_mask = BIT(0), 1988 .hw.init = &(struct clk_init_data){ 1989 .name = "gcc_gp1_clk", 1990 .parent_names = (const char *[]){ 1991 "gp1_clk_src", 1992 }, 1993 .num_parents = 1, 1994 .flags = CLK_SET_RATE_PARENT, 1995 .ops = &clk_branch2_ops, 1996 }, 1997 }, 1998 }; 1999 2000 static struct clk_branch gcc_gp2_clk = { 2001 .halt_reg = 0x65000, 2002 .halt_check = BRANCH_HALT, 2003 .clkr = { 2004 .enable_reg = 0x65000, 2005 .enable_mask = BIT(0), 2006 .hw.init = &(struct clk_init_data){ 2007 .name = "gcc_gp2_clk", 2008 .parent_names = (const char *[]){ 2009 "gp2_clk_src", 2010 }, 2011 .num_parents = 1, 2012 .flags = CLK_SET_RATE_PARENT, 2013 .ops = &clk_branch2_ops, 2014 }, 2015 }, 2016 }; 2017 2018 static struct clk_branch gcc_gp3_clk = { 2019 .halt_reg = 0x66000, 2020 .halt_check = BRANCH_HALT, 2021 .clkr = { 2022 .enable_reg = 0x66000, 2023 .enable_mask = BIT(0), 2024 .hw.init = &(struct clk_init_data){ 2025 .name = "gcc_gp3_clk", 2026 .parent_names = (const char *[]){ 2027 "gp3_clk_src", 2028 }, 2029 .num_parents = 1, 2030 .flags = CLK_SET_RATE_PARENT, 2031 .ops = &clk_branch2_ops, 2032 }, 2033 }, 2034 }; 2035 2036 static struct clk_branch gcc_bimc_gfx_clk = { 2037 .halt_reg = 0x46040, 2038 .halt_check = BRANCH_HALT, 2039 .clkr = { 2040 .enable_reg = 0x46040, 2041 .enable_mask = BIT(0), 2042 .hw.init = &(struct clk_init_data){ 2043 .name = "gcc_bimc_gfx_clk", 2044 .ops = &clk_branch2_ops, 2045 }, 2046 }, 2047 }; 2048 2049 static struct clk_branch gcc_gpu_bimc_gfx_clk = { 2050 .halt_reg = 0x71010, 2051 .halt_check = BRANCH_HALT, 2052 .clkr = { 2053 .enable_reg = 0x71010, 2054 .enable_mask = BIT(0), 2055 .hw.init = &(struct clk_init_data){ 2056 .name = "gcc_gpu_bimc_gfx_clk", 2057 .ops = &clk_branch2_ops, 2058 }, 2059 }, 2060 }; 2061 2062 static struct clk_branch gcc_gpu_bimc_gfx_src_clk = { 2063 .halt_reg = 0x7100c, 2064 .halt_check = BRANCH_HALT, 2065 .clkr = { 2066 .enable_reg = 0x7100c, 2067 .enable_mask = BIT(0), 2068 .hw.init = &(struct clk_init_data){ 2069 .name = "gcc_gpu_bimc_gfx_src_clk", 2070 .ops = &clk_branch2_ops, 2071 }, 2072 }, 2073 }; 2074 2075 static struct clk_branch gcc_gpu_cfg_ahb_clk = { 2076 .halt_reg = 0x71004, 2077 .halt_check = BRANCH_HALT, 2078 .clkr = { 2079 .enable_reg = 0x71004, 2080 .enable_mask = BIT(0), 2081 .hw.init = &(struct clk_init_data){ 2082 .name = "gcc_gpu_cfg_ahb_clk", 2083 .ops = &clk_branch2_ops, 2084 /* 2085 * The GPU IOMMU depends on this clock and hypervisor 2086 * will crash the SoC if this clock goes down, due to 2087 * secure contexts protection. 2088 */ 2089 .flags = CLK_IS_CRITICAL, 2090 }, 2091 }, 2092 }; 2093 2094 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2095 .halt_reg = 0x71018, 2096 .halt_check = BRANCH_HALT, 2097 .clkr = { 2098 .enable_reg = 0x71018, 2099 .enable_mask = BIT(0), 2100 .hw.init = &(struct clk_init_data){ 2101 .name = "gcc_gpu_snoc_dvm_gfx_clk", 2102 .ops = &clk_branch2_ops, 2103 }, 2104 }, 2105 }; 2106 2107 static struct clk_branch gcc_hmss_ahb_clk = { 2108 .halt_reg = 0x48000, 2109 .halt_check = BRANCH_HALT_VOTED, 2110 .clkr = { 2111 .enable_reg = 0x52004, 2112 .enable_mask = BIT(21), 2113 .hw.init = &(struct clk_init_data){ 2114 .name = "gcc_hmss_ahb_clk", 2115 .parent_names = (const char *[]){ 2116 "hmss_ahb_clk_src", 2117 }, 2118 .num_parents = 1, 2119 .flags = CLK_SET_RATE_PARENT, 2120 .ops = &clk_branch2_ops, 2121 }, 2122 }, 2123 }; 2124 2125 static struct clk_branch gcc_hmss_at_clk = { 2126 .halt_reg = 0x48010, 2127 .halt_check = BRANCH_HALT, 2128 .clkr = { 2129 .enable_reg = 0x48010, 2130 .enable_mask = BIT(0), 2131 .hw.init = &(struct clk_init_data){ 2132 .name = "gcc_hmss_at_clk", 2133 .ops = &clk_branch2_ops, 2134 }, 2135 }, 2136 }; 2137 2138 static struct clk_branch gcc_hmss_rbcpr_clk = { 2139 .halt_reg = 0x48008, 2140 .halt_check = BRANCH_HALT, 2141 .clkr = { 2142 .enable_reg = 0x48008, 2143 .enable_mask = BIT(0), 2144 .hw.init = &(struct clk_init_data){ 2145 .name = "gcc_hmss_rbcpr_clk", 2146 .parent_names = (const char *[]){ 2147 "hmss_rbcpr_clk_src", 2148 }, 2149 .num_parents = 1, 2150 .flags = CLK_SET_RATE_PARENT, 2151 .ops = &clk_branch2_ops, 2152 }, 2153 }, 2154 }; 2155 2156 static struct clk_branch gcc_hmss_trig_clk = { 2157 .halt_reg = 0x4800c, 2158 .halt_check = BRANCH_HALT, 2159 .clkr = { 2160 .enable_reg = 0x4800c, 2161 .enable_mask = BIT(0), 2162 .hw.init = &(struct clk_init_data){ 2163 .name = "gcc_hmss_trig_clk", 2164 .ops = &clk_branch2_ops, 2165 }, 2166 }, 2167 }; 2168 2169 static struct freq_tbl ftbl_hmss_gpll0_clk_src[] = { 2170 F( 300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 2171 F( 600000000, P_GPLL0_OUT_MAIN, 1, 0, 0), 2172 { } 2173 }; 2174 2175 static struct clk_rcg2 hmss_gpll0_clk_src = { 2176 .cmd_rcgr = 0x4805c, 2177 .hid_width = 5, 2178 .parent_map = gcc_parent_map_1, 2179 .freq_tbl = ftbl_hmss_gpll0_clk_src, 2180 .clkr.hw.init = &(struct clk_init_data) { 2181 .name = "hmss_gpll0_clk_src", 2182 .parent_names = gcc_parent_names_1, 2183 .num_parents = ARRAY_SIZE(gcc_parent_names_1), 2184 .ops = &clk_rcg2_ops, 2185 }, 2186 }; 2187 2188 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { 2189 .halt_reg = 0x9004, 2190 .halt_check = BRANCH_HALT, 2191 .clkr = { 2192 .enable_reg = 0x9004, 2193 .enable_mask = BIT(0), 2194 .hw.init = &(struct clk_init_data){ 2195 .name = "gcc_mmss_noc_cfg_ahb_clk", 2196 .ops = &clk_branch2_ops, 2197 /* 2198 * Any access to mmss depends on this clock. 2199 * Gating this clock has been shown to crash the system 2200 * when mmssnoc_axi_rpm_clk is inited in rpmcc. 2201 */ 2202 .flags = CLK_IS_CRITICAL, 2203 }, 2204 }, 2205 }; 2206 2207 static struct clk_branch gcc_mmss_qm_ahb_clk = { 2208 .halt_reg = 0x9030, 2209 .halt_check = BRANCH_HALT, 2210 .clkr = { 2211 .enable_reg = 0x9030, 2212 .enable_mask = BIT(0), 2213 .hw.init = &(struct clk_init_data){ 2214 .name = "gcc_mmss_qm_ahb_clk", 2215 .ops = &clk_branch2_ops, 2216 }, 2217 }, 2218 }; 2219 2220 static struct clk_branch gcc_mmss_qm_core_clk = { 2221 .halt_reg = 0x900c, 2222 .halt_check = BRANCH_HALT, 2223 .clkr = { 2224 .enable_reg = 0x900c, 2225 .enable_mask = BIT(0), 2226 .hw.init = &(struct clk_init_data){ 2227 .name = "gcc_mmss_qm_core_clk", 2228 .ops = &clk_branch2_ops, 2229 }, 2230 }, 2231 }; 2232 2233 static struct clk_branch gcc_mmss_sys_noc_axi_clk = { 2234 .halt_reg = 0x9000, 2235 .halt_check = BRANCH_HALT, 2236 .clkr = { 2237 .enable_reg = 0x9000, 2238 .enable_mask = BIT(0), 2239 .hw.init = &(struct clk_init_data){ 2240 .name = "gcc_mmss_sys_noc_axi_clk", 2241 .ops = &clk_branch2_ops, 2242 }, 2243 }, 2244 }; 2245 2246 static struct clk_branch gcc_mss_at_clk = { 2247 .halt_reg = 0x8a00c, 2248 .halt_check = BRANCH_HALT, 2249 .clkr = { 2250 .enable_reg = 0x8a00c, 2251 .enable_mask = BIT(0), 2252 .hw.init = &(struct clk_init_data){ 2253 .name = "gcc_mss_at_clk", 2254 .ops = &clk_branch2_ops, 2255 }, 2256 }, 2257 }; 2258 2259 static struct clk_branch gcc_pcie_0_aux_clk = { 2260 .halt_reg = 0x6b014, 2261 .halt_check = BRANCH_HALT, 2262 .clkr = { 2263 .enable_reg = 0x6b014, 2264 .enable_mask = BIT(0), 2265 .hw.init = &(struct clk_init_data){ 2266 .name = "gcc_pcie_0_aux_clk", 2267 .parent_names = (const char *[]){ 2268 "pcie_aux_clk_src", 2269 }, 2270 .num_parents = 1, 2271 .flags = CLK_SET_RATE_PARENT, 2272 .ops = &clk_branch2_ops, 2273 }, 2274 }, 2275 }; 2276 2277 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 2278 .halt_reg = 0x6b010, 2279 .halt_check = BRANCH_HALT, 2280 .clkr = { 2281 .enable_reg = 0x6b010, 2282 .enable_mask = BIT(0), 2283 .hw.init = &(struct clk_init_data){ 2284 .name = "gcc_pcie_0_cfg_ahb_clk", 2285 .ops = &clk_branch2_ops, 2286 }, 2287 }, 2288 }; 2289 2290 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 2291 .halt_reg = 0x6b00c, 2292 .halt_check = BRANCH_HALT, 2293 .clkr = { 2294 .enable_reg = 0x6b00c, 2295 .enable_mask = BIT(0), 2296 .hw.init = &(struct clk_init_data){ 2297 .name = "gcc_pcie_0_mstr_axi_clk", 2298 .ops = &clk_branch2_ops, 2299 }, 2300 }, 2301 }; 2302 2303 static struct clk_branch gcc_pcie_0_pipe_clk = { 2304 .halt_reg = 0x6b018, 2305 .halt_check = BRANCH_HALT_SKIP, 2306 .clkr = { 2307 .enable_reg = 0x6b018, 2308 .enable_mask = BIT(0), 2309 .hw.init = &(struct clk_init_data){ 2310 .name = "gcc_pcie_0_pipe_clk", 2311 .ops = &clk_branch2_ops, 2312 }, 2313 }, 2314 }; 2315 2316 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 2317 .halt_reg = 0x6b008, 2318 .halt_check = BRANCH_HALT, 2319 .clkr = { 2320 .enable_reg = 0x6b008, 2321 .enable_mask = BIT(0), 2322 .hw.init = &(struct clk_init_data){ 2323 .name = "gcc_pcie_0_slv_axi_clk", 2324 .ops = &clk_branch2_ops, 2325 }, 2326 }, 2327 }; 2328 2329 static struct clk_branch gcc_pcie_phy_aux_clk = { 2330 .halt_reg = 0x6f004, 2331 .halt_check = BRANCH_HALT, 2332 .clkr = { 2333 .enable_reg = 0x6f004, 2334 .enable_mask = BIT(0), 2335 .hw.init = &(struct clk_init_data){ 2336 .name = "gcc_pcie_phy_aux_clk", 2337 .parent_names = (const char *[]){ 2338 "pcie_aux_clk_src", 2339 }, 2340 .num_parents = 1, 2341 .flags = CLK_SET_RATE_PARENT, 2342 .ops = &clk_branch2_ops, 2343 }, 2344 }, 2345 }; 2346 2347 static struct clk_branch gcc_pdm2_clk = { 2348 .halt_reg = 0x3300c, 2349 .halt_check = BRANCH_HALT, 2350 .clkr = { 2351 .enable_reg = 0x3300c, 2352 .enable_mask = BIT(0), 2353 .hw.init = &(struct clk_init_data){ 2354 .name = "gcc_pdm2_clk", 2355 .parent_names = (const char *[]){ 2356 "pdm2_clk_src", 2357 }, 2358 .num_parents = 1, 2359 .flags = CLK_SET_RATE_PARENT, 2360 .ops = &clk_branch2_ops, 2361 }, 2362 }, 2363 }; 2364 2365 static struct clk_branch gcc_pdm_ahb_clk = { 2366 .halt_reg = 0x33004, 2367 .halt_check = BRANCH_HALT, 2368 .clkr = { 2369 .enable_reg = 0x33004, 2370 .enable_mask = BIT(0), 2371 .hw.init = &(struct clk_init_data){ 2372 .name = "gcc_pdm_ahb_clk", 2373 .ops = &clk_branch2_ops, 2374 }, 2375 }, 2376 }; 2377 2378 static struct clk_branch gcc_pdm_xo4_clk = { 2379 .halt_reg = 0x33008, 2380 .halt_check = BRANCH_HALT, 2381 .clkr = { 2382 .enable_reg = 0x33008, 2383 .enable_mask = BIT(0), 2384 .hw.init = &(struct clk_init_data){ 2385 .name = "gcc_pdm_xo4_clk", 2386 .ops = &clk_branch2_ops, 2387 }, 2388 }, 2389 }; 2390 2391 static struct clk_branch gcc_prng_ahb_clk = { 2392 .halt_reg = 0x34004, 2393 .halt_check = BRANCH_HALT_VOTED, 2394 .clkr = { 2395 .enable_reg = 0x52004, 2396 .enable_mask = BIT(13), 2397 .hw.init = &(struct clk_init_data){ 2398 .name = "gcc_prng_ahb_clk", 2399 .ops = &clk_branch2_ops, 2400 }, 2401 }, 2402 }; 2403 2404 static struct clk_branch gcc_sdcc2_ahb_clk = { 2405 .halt_reg = 0x14008, 2406 .halt_check = BRANCH_HALT, 2407 .clkr = { 2408 .enable_reg = 0x14008, 2409 .enable_mask = BIT(0), 2410 .hw.init = &(struct clk_init_data){ 2411 .name = "gcc_sdcc2_ahb_clk", 2412 .ops = &clk_branch2_ops, 2413 }, 2414 }, 2415 }; 2416 2417 static struct clk_branch gcc_sdcc2_apps_clk = { 2418 .halt_reg = 0x14004, 2419 .halt_check = BRANCH_HALT, 2420 .clkr = { 2421 .enable_reg = 0x14004, 2422 .enable_mask = BIT(0), 2423 .hw.init = &(struct clk_init_data){ 2424 .name = "gcc_sdcc2_apps_clk", 2425 .parent_names = (const char *[]){ 2426 "sdcc2_apps_clk_src", 2427 }, 2428 .num_parents = 1, 2429 .flags = CLK_SET_RATE_PARENT, 2430 .ops = &clk_branch2_ops, 2431 }, 2432 }, 2433 }; 2434 2435 static struct clk_branch gcc_sdcc4_ahb_clk = { 2436 .halt_reg = 0x16008, 2437 .halt_check = BRANCH_HALT, 2438 .clkr = { 2439 .enable_reg = 0x16008, 2440 .enable_mask = BIT(0), 2441 .hw.init = &(struct clk_init_data){ 2442 .name = "gcc_sdcc4_ahb_clk", 2443 .ops = &clk_branch2_ops, 2444 }, 2445 }, 2446 }; 2447 2448 static struct clk_branch gcc_sdcc4_apps_clk = { 2449 .halt_reg = 0x16004, 2450 .halt_check = BRANCH_HALT, 2451 .clkr = { 2452 .enable_reg = 0x16004, 2453 .enable_mask = BIT(0), 2454 .hw.init = &(struct clk_init_data){ 2455 .name = "gcc_sdcc4_apps_clk", 2456 .parent_names = (const char *[]){ 2457 "sdcc4_apps_clk_src", 2458 }, 2459 .num_parents = 1, 2460 .flags = CLK_SET_RATE_PARENT, 2461 .ops = &clk_branch2_ops, 2462 }, 2463 }, 2464 }; 2465 2466 static struct clk_branch gcc_tsif_ahb_clk = { 2467 .halt_reg = 0x36004, 2468 .halt_check = BRANCH_HALT, 2469 .clkr = { 2470 .enable_reg = 0x36004, 2471 .enable_mask = BIT(0), 2472 .hw.init = &(struct clk_init_data){ 2473 .name = "gcc_tsif_ahb_clk", 2474 .ops = &clk_branch2_ops, 2475 }, 2476 }, 2477 }; 2478 2479 static struct clk_branch gcc_tsif_inactivity_timers_clk = { 2480 .halt_reg = 0x3600c, 2481 .halt_check = BRANCH_HALT, 2482 .clkr = { 2483 .enable_reg = 0x3600c, 2484 .enable_mask = BIT(0), 2485 .hw.init = &(struct clk_init_data){ 2486 .name = "gcc_tsif_inactivity_timers_clk", 2487 .ops = &clk_branch2_ops, 2488 }, 2489 }, 2490 }; 2491 2492 static struct clk_branch gcc_tsif_ref_clk = { 2493 .halt_reg = 0x36008, 2494 .halt_check = BRANCH_HALT, 2495 .clkr = { 2496 .enable_reg = 0x36008, 2497 .enable_mask = BIT(0), 2498 .hw.init = &(struct clk_init_data){ 2499 .name = "gcc_tsif_ref_clk", 2500 .parent_names = (const char *[]){ 2501 "tsif_ref_clk_src", 2502 }, 2503 .num_parents = 1, 2504 .flags = CLK_SET_RATE_PARENT, 2505 .ops = &clk_branch2_ops, 2506 }, 2507 }, 2508 }; 2509 2510 static struct clk_branch gcc_ufs_ahb_clk = { 2511 .halt_reg = 0x7500c, 2512 .halt_check = BRANCH_HALT, 2513 .clkr = { 2514 .enable_reg = 0x7500c, 2515 .enable_mask = BIT(0), 2516 .hw.init = &(struct clk_init_data){ 2517 .name = "gcc_ufs_ahb_clk", 2518 .ops = &clk_branch2_ops, 2519 }, 2520 }, 2521 }; 2522 2523 static struct clk_branch gcc_ufs_axi_clk = { 2524 .halt_reg = 0x75008, 2525 .halt_check = BRANCH_HALT, 2526 .clkr = { 2527 .enable_reg = 0x75008, 2528 .enable_mask = BIT(0), 2529 .hw.init = &(struct clk_init_data){ 2530 .name = "gcc_ufs_axi_clk", 2531 .parent_names = (const char *[]){ 2532 "ufs_axi_clk_src", 2533 }, 2534 .num_parents = 1, 2535 .flags = CLK_SET_RATE_PARENT, 2536 .ops = &clk_branch2_ops, 2537 }, 2538 }, 2539 }; 2540 2541 static struct clk_branch gcc_ufs_ice_core_clk = { 2542 .halt_reg = 0x7600c, 2543 .halt_check = BRANCH_HALT, 2544 .clkr = { 2545 .enable_reg = 0x7600c, 2546 .enable_mask = BIT(0), 2547 .hw.init = &(struct clk_init_data){ 2548 .name = "gcc_ufs_ice_core_clk", 2549 .ops = &clk_branch2_ops, 2550 }, 2551 }, 2552 }; 2553 2554 static struct clk_branch gcc_ufs_phy_aux_clk = { 2555 .halt_reg = 0x76040, 2556 .halt_check = BRANCH_HALT, 2557 .clkr = { 2558 .enable_reg = 0x76040, 2559 .enable_mask = BIT(0), 2560 .hw.init = &(struct clk_init_data){ 2561 .name = "gcc_ufs_phy_aux_clk", 2562 .ops = &clk_branch2_ops, 2563 }, 2564 }, 2565 }; 2566 2567 static struct clk_branch gcc_ufs_rx_symbol_0_clk = { 2568 .halt_reg = 0x75014, 2569 .halt_check = BRANCH_HALT_SKIP, 2570 .clkr = { 2571 .enable_reg = 0x75014, 2572 .enable_mask = BIT(0), 2573 .hw.init = &(struct clk_init_data){ 2574 .name = "gcc_ufs_rx_symbol_0_clk", 2575 .ops = &clk_branch2_ops, 2576 }, 2577 }, 2578 }; 2579 2580 static struct clk_branch gcc_ufs_rx_symbol_1_clk = { 2581 .halt_reg = 0x7605c, 2582 .halt_check = BRANCH_HALT_SKIP, 2583 .clkr = { 2584 .enable_reg = 0x7605c, 2585 .enable_mask = BIT(0), 2586 .hw.init = &(struct clk_init_data){ 2587 .name = "gcc_ufs_rx_symbol_1_clk", 2588 .ops = &clk_branch2_ops, 2589 }, 2590 }, 2591 }; 2592 2593 static struct clk_branch gcc_ufs_tx_symbol_0_clk = { 2594 .halt_reg = 0x75010, 2595 .halt_check = BRANCH_HALT_SKIP, 2596 .clkr = { 2597 .enable_reg = 0x75010, 2598 .enable_mask = BIT(0), 2599 .hw.init = &(struct clk_init_data){ 2600 .name = "gcc_ufs_tx_symbol_0_clk", 2601 .ops = &clk_branch2_ops, 2602 }, 2603 }, 2604 }; 2605 2606 static struct clk_branch gcc_ufs_unipro_core_clk = { 2607 .halt_reg = 0x76008, 2608 .halt_check = BRANCH_HALT, 2609 .clkr = { 2610 .enable_reg = 0x76008, 2611 .enable_mask = BIT(0), 2612 .hw.init = &(struct clk_init_data){ 2613 .name = "gcc_ufs_unipro_core_clk", 2614 .parent_names = (const char *[]){ 2615 "ufs_unipro_core_clk_src", 2616 }, 2617 .num_parents = 1, 2618 .flags = CLK_SET_RATE_PARENT, 2619 .ops = &clk_branch2_ops, 2620 }, 2621 }, 2622 }; 2623 2624 static struct clk_branch gcc_usb30_master_clk = { 2625 .halt_reg = 0xf008, 2626 .halt_check = BRANCH_HALT, 2627 .clkr = { 2628 .enable_reg = 0xf008, 2629 .enable_mask = BIT(0), 2630 .hw.init = &(struct clk_init_data){ 2631 .name = "gcc_usb30_master_clk", 2632 .parent_names = (const char *[]){ 2633 "usb30_master_clk_src", 2634 }, 2635 .num_parents = 1, 2636 .flags = CLK_SET_RATE_PARENT, 2637 .ops = &clk_branch2_ops, 2638 }, 2639 }, 2640 }; 2641 2642 static struct clk_branch gcc_usb30_mock_utmi_clk = { 2643 .halt_reg = 0xf010, 2644 .halt_check = BRANCH_HALT, 2645 .clkr = { 2646 .enable_reg = 0xf010, 2647 .enable_mask = BIT(0), 2648 .hw.init = &(struct clk_init_data){ 2649 .name = "gcc_usb30_mock_utmi_clk", 2650 .parent_names = (const char *[]){ 2651 "usb30_mock_utmi_clk_src", 2652 }, 2653 .num_parents = 1, 2654 .flags = CLK_SET_RATE_PARENT, 2655 .ops = &clk_branch2_ops, 2656 }, 2657 }, 2658 }; 2659 2660 static struct clk_branch gcc_usb30_sleep_clk = { 2661 .halt_reg = 0xf00c, 2662 .halt_check = BRANCH_HALT, 2663 .clkr = { 2664 .enable_reg = 0xf00c, 2665 .enable_mask = BIT(0), 2666 .hw.init = &(struct clk_init_data){ 2667 .name = "gcc_usb30_sleep_clk", 2668 .ops = &clk_branch2_ops, 2669 }, 2670 }, 2671 }; 2672 2673 static struct clk_branch gcc_usb3_phy_aux_clk = { 2674 .halt_reg = 0x50000, 2675 .halt_check = BRANCH_HALT, 2676 .clkr = { 2677 .enable_reg = 0x50000, 2678 .enable_mask = BIT(0), 2679 .hw.init = &(struct clk_init_data){ 2680 .name = "gcc_usb3_phy_aux_clk", 2681 .parent_names = (const char *[]){ 2682 "usb3_phy_aux_clk_src", 2683 }, 2684 .num_parents = 1, 2685 .flags = CLK_SET_RATE_PARENT, 2686 .ops = &clk_branch2_ops, 2687 }, 2688 }, 2689 }; 2690 2691 static struct clk_branch gcc_usb3_phy_pipe_clk = { 2692 .halt_reg = 0x50004, 2693 .halt_check = BRANCH_HALT_SKIP, 2694 .clkr = { 2695 .enable_reg = 0x50004, 2696 .enable_mask = BIT(0), 2697 .hw.init = &(struct clk_init_data){ 2698 .name = "gcc_usb3_phy_pipe_clk", 2699 .ops = &clk_branch2_ops, 2700 }, 2701 }, 2702 }; 2703 2704 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 2705 .halt_reg = 0x6a004, 2706 .halt_check = BRANCH_HALT, 2707 .clkr = { 2708 .enable_reg = 0x6a004, 2709 .enable_mask = BIT(0), 2710 .hw.init = &(struct clk_init_data){ 2711 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2712 .ops = &clk_branch2_ops, 2713 }, 2714 }, 2715 }; 2716 2717 static struct clk_branch gcc_hdmi_clkref_clk = { 2718 .halt_reg = 0x88000, 2719 .clkr = { 2720 .enable_reg = 0x88000, 2721 .enable_mask = BIT(0), 2722 .hw.init = &(struct clk_init_data){ 2723 .name = "gcc_hdmi_clkref_clk", 2724 .parent_names = (const char *[]){ "xo" }, 2725 .num_parents = 1, 2726 .ops = &clk_branch2_ops, 2727 }, 2728 }, 2729 }; 2730 2731 static struct clk_branch gcc_ufs_clkref_clk = { 2732 .halt_reg = 0x88004, 2733 .clkr = { 2734 .enable_reg = 0x88004, 2735 .enable_mask = BIT(0), 2736 .hw.init = &(struct clk_init_data){ 2737 .name = "gcc_ufs_clkref_clk", 2738 .parent_names = (const char *[]){ "xo" }, 2739 .num_parents = 1, 2740 .ops = &clk_branch2_ops, 2741 }, 2742 }, 2743 }; 2744 2745 static struct clk_branch gcc_usb3_clkref_clk = { 2746 .halt_reg = 0x88008, 2747 .clkr = { 2748 .enable_reg = 0x88008, 2749 .enable_mask = BIT(0), 2750 .hw.init = &(struct clk_init_data){ 2751 .name = "gcc_usb3_clkref_clk", 2752 .parent_names = (const char *[]){ "xo" }, 2753 .num_parents = 1, 2754 .ops = &clk_branch2_ops, 2755 }, 2756 }, 2757 }; 2758 2759 static struct clk_branch gcc_pcie_clkref_clk = { 2760 .halt_reg = 0x8800c, 2761 .clkr = { 2762 .enable_reg = 0x8800c, 2763 .enable_mask = BIT(0), 2764 .hw.init = &(struct clk_init_data){ 2765 .name = "gcc_pcie_clkref_clk", 2766 .parent_names = (const char *[]){ "xo" }, 2767 .num_parents = 1, 2768 .ops = &clk_branch2_ops, 2769 }, 2770 }, 2771 }; 2772 2773 static struct clk_branch gcc_rx1_usb2_clkref_clk = { 2774 .halt_reg = 0x88014, 2775 .clkr = { 2776 .enable_reg = 0x88014, 2777 .enable_mask = BIT(0), 2778 .hw.init = &(struct clk_init_data){ 2779 .name = "gcc_rx1_usb2_clkref_clk", 2780 .parent_names = (const char *[]){ "xo" }, 2781 .num_parents = 1, 2782 .ops = &clk_branch2_ops, 2783 }, 2784 }, 2785 }; 2786 2787 static struct gdsc pcie_0_gdsc = { 2788 .gdscr = 0x6b004, 2789 .gds_hw_ctrl = 0x0, 2790 .pd = { 2791 .name = "pcie_0_gdsc", 2792 }, 2793 .pwrsts = PWRSTS_OFF_ON, 2794 .flags = VOTABLE, 2795 }; 2796 2797 static struct gdsc ufs_gdsc = { 2798 .gdscr = 0x75004, 2799 .gds_hw_ctrl = 0x0, 2800 .pd = { 2801 .name = "ufs_gdsc", 2802 }, 2803 .pwrsts = PWRSTS_OFF_ON, 2804 .flags = VOTABLE, 2805 }; 2806 2807 static struct gdsc usb_30_gdsc = { 2808 .gdscr = 0xf004, 2809 .gds_hw_ctrl = 0x0, 2810 .pd = { 2811 .name = "usb_30_gdsc", 2812 }, 2813 .pwrsts = PWRSTS_OFF_ON, 2814 .flags = VOTABLE, 2815 }; 2816 2817 static struct clk_regmap *gcc_msm8998_clocks[] = { 2818 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2819 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2820 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2821 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2822 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2823 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2824 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2825 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2826 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 2827 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 2828 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 2829 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 2830 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2831 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2832 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 2833 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, 2834 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, 2835 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, 2836 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, 2837 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, 2838 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, 2839 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, 2840 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, 2841 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, 2842 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, 2843 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, 2844 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, 2845 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, 2846 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, 2847 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, 2848 [GCC_AGGRE1_NOC_XO_CLK] = &gcc_aggre1_noc_xo_clk.clkr, 2849 [GCC_AGGRE1_UFS_AXI_CLK] = &gcc_aggre1_ufs_axi_clk.clkr, 2850 [GCC_AGGRE1_USB3_AXI_CLK] = &gcc_aggre1_usb3_axi_clk.clkr, 2851 [GCC_APSS_QDSS_TSCTR_DIV2_CLK] = &gcc_apss_qdss_tsctr_div2_clk.clkr, 2852 [GCC_APSS_QDSS_TSCTR_DIV8_CLK] = &gcc_apss_qdss_tsctr_div8_clk.clkr, 2853 [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr, 2854 [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr, 2855 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2856 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2857 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2858 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2859 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2860 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2861 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2862 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 2863 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 2864 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 2865 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 2866 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 2867 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 2868 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, 2869 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2870 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2871 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 2872 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, 2873 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, 2874 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, 2875 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, 2876 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, 2877 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, 2878 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, 2879 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, 2880 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, 2881 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, 2882 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, 2883 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, 2884 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, 2885 [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr, 2886 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, 2887 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, 2888 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, 2889 [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr, 2890 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2891 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2892 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2893 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, 2894 [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr, 2895 [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr, 2896 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 2897 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 2898 [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr, 2899 [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr, 2900 [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr, 2901 [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr, 2902 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr, 2903 [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr, 2904 [GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr, 2905 [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr, 2906 [GCC_MSS_AT_CLK] = &gcc_mss_at_clk.clkr, 2907 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2908 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2909 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2910 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2911 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2912 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, 2913 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2914 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2915 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2916 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2917 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2918 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2919 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 2920 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 2921 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 2922 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, 2923 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 2924 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, 2925 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, 2926 [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr, 2927 [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr, 2928 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, 2929 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, 2930 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, 2931 [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr, 2932 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, 2933 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 2934 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 2935 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, 2936 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, 2937 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 2938 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 2939 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 2940 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 2941 [GPLL0] = &gpll0.clkr, 2942 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 2943 [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr, 2944 [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr, 2945 [GPLL0_OUT_TEST] = &gpll0_out_test.clkr, 2946 [GPLL1] = &gpll1.clkr, 2947 [GPLL1_OUT_EVEN] = &gpll1_out_even.clkr, 2948 [GPLL1_OUT_MAIN] = &gpll1_out_main.clkr, 2949 [GPLL1_OUT_ODD] = &gpll1_out_odd.clkr, 2950 [GPLL1_OUT_TEST] = &gpll1_out_test.clkr, 2951 [GPLL2] = &gpll2.clkr, 2952 [GPLL2_OUT_EVEN] = &gpll2_out_even.clkr, 2953 [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr, 2954 [GPLL2_OUT_ODD] = &gpll2_out_odd.clkr, 2955 [GPLL2_OUT_TEST] = &gpll2_out_test.clkr, 2956 [GPLL3] = &gpll3.clkr, 2957 [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr, 2958 [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr, 2959 [GPLL3_OUT_ODD] = &gpll3_out_odd.clkr, 2960 [GPLL3_OUT_TEST] = &gpll3_out_test.clkr, 2961 [GPLL4] = &gpll4.clkr, 2962 [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr, 2963 [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr, 2964 [GPLL4_OUT_ODD] = &gpll4_out_odd.clkr, 2965 [GPLL4_OUT_TEST] = &gpll4_out_test.clkr, 2966 [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr, 2967 [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr, 2968 [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr, 2969 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 2970 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 2971 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, 2972 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, 2973 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, 2974 [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr, 2975 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, 2976 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 2977 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, 2978 [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr, 2979 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, 2980 [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr, 2981 [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr, 2982 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr, 2983 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 2984 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2985 [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr, 2986 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, 2987 [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr, 2988 [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr, 2989 [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr, 2990 }; 2991 2992 static struct gdsc *gcc_msm8998_gdscs[] = { 2993 [PCIE_0_GDSC] = &pcie_0_gdsc, 2994 [UFS_GDSC] = &ufs_gdsc, 2995 [USB_30_GDSC] = &usb_30_gdsc, 2996 }; 2997 2998 static const struct qcom_reset_map gcc_msm8998_resets[] = { 2999 [GCC_BLSP1_QUP1_BCR] = { 0x19000 }, 3000 [GCC_BLSP1_QUP2_BCR] = { 0x1b000 }, 3001 [GCC_BLSP1_QUP3_BCR] = { 0x1d000 }, 3002 [GCC_BLSP1_QUP4_BCR] = { 0x1f000 }, 3003 [GCC_BLSP1_QUP5_BCR] = { 0x21000 }, 3004 [GCC_BLSP1_QUP6_BCR] = { 0x23000 }, 3005 [GCC_BLSP2_QUP1_BCR] = { 0x26000 }, 3006 [GCC_BLSP2_QUP2_BCR] = { 0x28000 }, 3007 [GCC_BLSP2_QUP3_BCR] = { 0x2a000 }, 3008 [GCC_BLSP2_QUP4_BCR] = { 0x2c000 }, 3009 [GCC_BLSP2_QUP5_BCR] = { 0x2e000 }, 3010 [GCC_BLSP2_QUP6_BCR] = { 0x30000 }, 3011 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3012 [GCC_PDM_BCR] = { 0x33000 }, 3013 [GCC_SDCC2_BCR] = { 0x14000 }, 3014 [GCC_SDCC4_BCR] = { 0x16000 }, 3015 [GCC_TSIF_BCR] = { 0x36000 }, 3016 [GCC_UFS_BCR] = { 0x75000 }, 3017 [GCC_USB_30_BCR] = { 0xf000 }, 3018 [GCC_SYSTEM_NOC_BCR] = { 0x4000 }, 3019 [GCC_CONFIG_NOC_BCR] = { 0x5000 }, 3020 [GCC_AHB2PHY_EAST_BCR] = { 0x7000 }, 3021 [GCC_IMEM_BCR] = { 0x8000 }, 3022 [GCC_PIMEM_BCR] = { 0xa000 }, 3023 [GCC_MMSS_BCR] = { 0xb000 }, 3024 [GCC_QDSS_BCR] = { 0xc000 }, 3025 [GCC_WCSS_BCR] = { 0x11000 }, 3026 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3027 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3028 [GCC_BLSP1_BCR] = { 0x17000 }, 3029 [GCC_BLSP1_UART1_BCR] = { 0x1a000 }, 3030 [GCC_BLSP1_UART2_BCR] = { 0x1c000 }, 3031 [GCC_BLSP1_UART3_BCR] = { 0x1e000 }, 3032 [GCC_CM_PHY_REFGEN1_BCR] = { 0x22000 }, 3033 [GCC_CM_PHY_REFGEN2_BCR] = { 0x24000 }, 3034 [GCC_BLSP2_BCR] = { 0x25000 }, 3035 [GCC_BLSP2_UART1_BCR] = { 0x27000 }, 3036 [GCC_BLSP2_UART2_BCR] = { 0x29000 }, 3037 [GCC_BLSP2_UART3_BCR] = { 0x2b000 }, 3038 [GCC_SRAM_SENSOR_BCR] = { 0x2d000 }, 3039 [GCC_PRNG_BCR] = { 0x34000 }, 3040 [GCC_TSIF_0_RESET] = { 0x36024 }, 3041 [GCC_TSIF_1_RESET] = { 0x36028 }, 3042 [GCC_TCSR_BCR] = { 0x37000 }, 3043 [GCC_BOOT_ROM_BCR] = { 0x38000 }, 3044 [GCC_MSG_RAM_BCR] = { 0x39000 }, 3045 [GCC_TLMM_BCR] = { 0x3a000 }, 3046 [GCC_MPM_BCR] = { 0x3b000 }, 3047 [GCC_SEC_CTRL_BCR] = { 0x3d000 }, 3048 [GCC_SPMI_BCR] = { 0x3f000 }, 3049 [GCC_SPDM_BCR] = { 0x40000 }, 3050 [GCC_CE1_BCR] = { 0x41000 }, 3051 [GCC_BIMC_BCR] = { 0x44000 }, 3052 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 }, 3053 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49008 }, 3054 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49010 }, 3055 [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49018 }, 3056 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 }, 3057 [GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR] = { 0x4a004 }, 3058 [GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR] = { 0x4a00c }, 3059 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 }, 3060 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 }, 3061 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 }, 3062 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 }, 3063 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 }, 3064 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 }, 3065 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 }, 3066 [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 }, 3067 [GCC_APB2JTAG_BCR] = { 0x4c000 }, 3068 [GCC_RBCPR_CX_BCR] = { 0x4e000 }, 3069 [GCC_RBCPR_MX_BCR] = { 0x4f000 }, 3070 [GCC_USB3_PHY_BCR] = { 0x50020 }, 3071 [GCC_USB3PHY_PHY_BCR] = { 0x50024 }, 3072 [GCC_USB3_DP_PHY_BCR] = { 0x50028 }, 3073 [GCC_SSC_BCR] = { 0x63000 }, 3074 [GCC_SSC_RESET] = { 0x63020 }, 3075 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 3076 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 3077 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3078 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 3079 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 3080 [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00c }, 3081 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f010 }, 3082 [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 }, 3083 [GCC_GPU_BCR] = { 0x71000 }, 3084 [GCC_SPSS_BCR] = { 0x72000 }, 3085 [GCC_OBT_ODT_BCR] = { 0x73000 }, 3086 [GCC_MSS_RESTART] = { 0x79000 }, 3087 [GCC_VS_BCR] = { 0x7a000 }, 3088 [GCC_MSS_VS_RESET] = { 0x7a100 }, 3089 [GCC_GPU_VS_RESET] = { 0x7a104 }, 3090 [GCC_APC0_VS_RESET] = { 0x7a108 }, 3091 [GCC_APC1_VS_RESET] = { 0x7a10c }, 3092 [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 }, 3093 [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 }, 3094 [GCC_CNOC_BUS_TIMEOUT10_BCR] = { 0x80010 }, 3095 [GCC_CNOC_BUS_TIMEOUT11_BCR] = { 0x80018 }, 3096 [GCC_CNOC_BUS_TIMEOUT12_BCR] = { 0x80020 }, 3097 [GCC_CNOC_BUS_TIMEOUT13_BCR] = { 0x80028 }, 3098 [GCC_CNOC_BUS_TIMEOUT14_BCR] = { 0x80030 }, 3099 [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80038 }, 3100 [GCC_AGGRE1_NOC_BCR] = { 0x82000 }, 3101 [GCC_AGGRE2_NOC_BCR] = { 0x83000 }, 3102 [GCC_DCC_BCR] = { 0x84000 }, 3103 [GCC_QREFS_VBG_CAL_BCR] = { 0x88028 }, 3104 [GCC_IPA_BCR] = { 0x89000 }, 3105 [GCC_GLM_BCR] = { 0x8b000 }, 3106 [GCC_SKL_BCR] = { 0x8c000 }, 3107 [GCC_MSMPU_BCR] = { 0x8d000 }, 3108 }; 3109 3110 static const struct regmap_config gcc_msm8998_regmap_config = { 3111 .reg_bits = 32, 3112 .reg_stride = 4, 3113 .val_bits = 32, 3114 .max_register = 0x8f000, 3115 .fast_io = true, 3116 }; 3117 3118 static struct clk_hw *gcc_msm8998_hws[] = { 3119 &xo.hw, 3120 }; 3121 3122 static const struct qcom_cc_desc gcc_msm8998_desc = { 3123 .config = &gcc_msm8998_regmap_config, 3124 .clks = gcc_msm8998_clocks, 3125 .num_clks = ARRAY_SIZE(gcc_msm8998_clocks), 3126 .resets = gcc_msm8998_resets, 3127 .num_resets = ARRAY_SIZE(gcc_msm8998_resets), 3128 .gdscs = gcc_msm8998_gdscs, 3129 .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs), 3130 .clk_hws = gcc_msm8998_hws, 3131 .num_clk_hws = ARRAY_SIZE(gcc_msm8998_hws), 3132 }; 3133 3134 static int gcc_msm8998_probe(struct platform_device *pdev) 3135 { 3136 struct regmap *regmap; 3137 int ret; 3138 3139 regmap = qcom_cc_map(pdev, &gcc_msm8998_desc); 3140 if (IS_ERR(regmap)) 3141 return PTR_ERR(regmap); 3142 3143 /* 3144 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be 3145 * turned off by hardware during certain apps low power modes. 3146 */ 3147 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); 3148 if (ret) 3149 return ret; 3150 3151 return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap); 3152 } 3153 3154 static const struct of_device_id gcc_msm8998_match_table[] = { 3155 { .compatible = "qcom,gcc-msm8998" }, 3156 { } 3157 }; 3158 MODULE_DEVICE_TABLE(of, gcc_msm8998_match_table); 3159 3160 static struct platform_driver gcc_msm8998_driver = { 3161 .probe = gcc_msm8998_probe, 3162 .driver = { 3163 .name = "gcc-msm8998", 3164 .of_match_table = gcc_msm8998_match_table, 3165 }, 3166 }; 3167 3168 static int __init gcc_msm8998_init(void) 3169 { 3170 return platform_driver_register(&gcc_msm8998_driver); 3171 } 3172 core_initcall(gcc_msm8998_init); 3173 3174 static void __exit gcc_msm8998_exit(void) 3175 { 3176 platform_driver_unregister(&gcc_msm8998_driver); 3177 } 3178 module_exit(gcc_msm8998_exit); 3179 3180 MODULE_DESCRIPTION("QCOM GCC msm8998 Driver"); 3181 MODULE_LICENSE("GPL v2"); 3182 MODULE_ALIAS("platform:gcc-msm8998"); 3183