1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2016, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/bitops.h> 8 #include <linux/err.h> 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/clk-provider.h> 14 #include <linux/regmap.h> 15 #include <linux/reset-controller.h> 16 17 #include <dt-bindings/clock/qcom,gcc-msm8998.h> 18 19 #include "common.h" 20 #include "clk-regmap.h" 21 #include "clk-alpha-pll.h" 22 #include "clk-pll.h" 23 #include "clk-rcg.h" 24 #include "clk-branch.h" 25 #include "reset.h" 26 #include "gdsc.h" 27 28 #define GCC_MMSS_MISC 0x0902C 29 #define GCC_GPU_MISC 0x71028 30 31 static struct pll_vco fabia_vco[] = { 32 { 250000000, 2000000000, 0 }, 33 { 125000000, 1000000000, 1 }, 34 }; 35 36 static struct clk_alpha_pll gpll0 = { 37 .offset = 0x0, 38 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 39 .vco_table = fabia_vco, 40 .num_vco = ARRAY_SIZE(fabia_vco), 41 .clkr = { 42 .enable_reg = 0x52000, 43 .enable_mask = BIT(0), 44 .hw.init = &(struct clk_init_data){ 45 .name = "gpll0", 46 .parent_data = (const struct clk_parent_data []) { 47 { .fw_name = "xo" }, 48 }, 49 .num_parents = 1, 50 .ops = &clk_alpha_pll_fixed_fabia_ops, 51 } 52 }, 53 }; 54 55 static struct clk_alpha_pll_postdiv gpll0_out_even = { 56 .offset = 0x0, 57 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 58 .clkr.hw.init = &(struct clk_init_data){ 59 .name = "gpll0_out_even", 60 .parent_hws = (const struct clk_hw*[]) { 61 &gpll0.clkr.hw, 62 }, 63 .num_parents = 1, 64 .ops = &clk_alpha_pll_postdiv_fabia_ops, 65 }, 66 }; 67 68 static struct clk_alpha_pll_postdiv gpll0_out_main = { 69 .offset = 0x0, 70 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 71 .clkr.hw.init = &(struct clk_init_data){ 72 .name = "gpll0_out_main", 73 .parent_hws = (const struct clk_hw*[]) { 74 &gpll0.clkr.hw, 75 }, 76 .num_parents = 1, 77 .ops = &clk_alpha_pll_postdiv_fabia_ops, 78 }, 79 }; 80 81 static struct clk_alpha_pll_postdiv gpll0_out_odd = { 82 .offset = 0x0, 83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 84 .clkr.hw.init = &(struct clk_init_data){ 85 .name = "gpll0_out_odd", 86 .parent_hws = (const struct clk_hw*[]) { 87 &gpll0.clkr.hw, 88 }, 89 .num_parents = 1, 90 .ops = &clk_alpha_pll_postdiv_fabia_ops, 91 }, 92 }; 93 94 static struct clk_alpha_pll_postdiv gpll0_out_test = { 95 .offset = 0x0, 96 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 97 .clkr.hw.init = &(struct clk_init_data){ 98 .name = "gpll0_out_test", 99 .parent_hws = (const struct clk_hw*[]) { 100 &gpll0.clkr.hw, 101 }, 102 .num_parents = 1, 103 .ops = &clk_alpha_pll_postdiv_fabia_ops, 104 }, 105 }; 106 107 static struct clk_alpha_pll gpll1 = { 108 .offset = 0x1000, 109 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 110 .vco_table = fabia_vco, 111 .num_vco = ARRAY_SIZE(fabia_vco), 112 .clkr = { 113 .enable_reg = 0x52000, 114 .enable_mask = BIT(1), 115 .hw.init = &(struct clk_init_data){ 116 .name = "gpll1", 117 .parent_data = (const struct clk_parent_data []) { 118 { .fw_name = "xo" }, 119 }, 120 .num_parents = 1, 121 .ops = &clk_alpha_pll_fixed_fabia_ops, 122 } 123 }, 124 }; 125 126 static struct clk_alpha_pll_postdiv gpll1_out_even = { 127 .offset = 0x1000, 128 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 129 .clkr.hw.init = &(struct clk_init_data){ 130 .name = "gpll1_out_even", 131 .parent_hws = (const struct clk_hw*[]) { 132 &gpll1.clkr.hw, 133 }, 134 .num_parents = 1, 135 .ops = &clk_alpha_pll_postdiv_fabia_ops, 136 }, 137 }; 138 139 static struct clk_alpha_pll_postdiv gpll1_out_main = { 140 .offset = 0x1000, 141 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 142 .clkr.hw.init = &(struct clk_init_data){ 143 .name = "gpll1_out_main", 144 .parent_hws = (const struct clk_hw*[]) { 145 &gpll1.clkr.hw, 146 }, 147 .num_parents = 1, 148 .ops = &clk_alpha_pll_postdiv_fabia_ops, 149 }, 150 }; 151 152 static struct clk_alpha_pll_postdiv gpll1_out_odd = { 153 .offset = 0x1000, 154 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 155 .clkr.hw.init = &(struct clk_init_data){ 156 .name = "gpll1_out_odd", 157 .parent_hws = (const struct clk_hw*[]) { 158 &gpll1.clkr.hw, 159 }, 160 .num_parents = 1, 161 .ops = &clk_alpha_pll_postdiv_fabia_ops, 162 }, 163 }; 164 165 static struct clk_alpha_pll_postdiv gpll1_out_test = { 166 .offset = 0x1000, 167 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 168 .clkr.hw.init = &(struct clk_init_data){ 169 .name = "gpll1_out_test", 170 .parent_hws = (const struct clk_hw*[]) { 171 &gpll1.clkr.hw, 172 }, 173 .num_parents = 1, 174 .ops = &clk_alpha_pll_postdiv_fabia_ops, 175 }, 176 }; 177 178 static struct clk_alpha_pll gpll2 = { 179 .offset = 0x2000, 180 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 181 .vco_table = fabia_vco, 182 .num_vco = ARRAY_SIZE(fabia_vco), 183 .clkr = { 184 .enable_reg = 0x52000, 185 .enable_mask = BIT(2), 186 .hw.init = &(struct clk_init_data){ 187 .name = "gpll2", 188 .parent_data = (const struct clk_parent_data []) { 189 { .fw_name = "xo" }, 190 }, 191 .num_parents = 1, 192 .ops = &clk_alpha_pll_fixed_fabia_ops, 193 } 194 }, 195 }; 196 197 static struct clk_alpha_pll_postdiv gpll2_out_even = { 198 .offset = 0x2000, 199 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 200 .clkr.hw.init = &(struct clk_init_data){ 201 .name = "gpll2_out_even", 202 .parent_hws = (const struct clk_hw*[]) { 203 &gpll2.clkr.hw, 204 }, 205 .num_parents = 1, 206 .ops = &clk_alpha_pll_postdiv_fabia_ops, 207 }, 208 }; 209 210 static struct clk_alpha_pll_postdiv gpll2_out_main = { 211 .offset = 0x2000, 212 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 213 .clkr.hw.init = &(struct clk_init_data){ 214 .name = "gpll2_out_main", 215 .parent_hws = (const struct clk_hw*[]) { 216 &gpll2.clkr.hw, 217 }, 218 .num_parents = 1, 219 .ops = &clk_alpha_pll_postdiv_fabia_ops, 220 }, 221 }; 222 223 static struct clk_alpha_pll_postdiv gpll2_out_odd = { 224 .offset = 0x2000, 225 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 226 .clkr.hw.init = &(struct clk_init_data){ 227 .name = "gpll2_out_odd", 228 .parent_hws = (const struct clk_hw*[]) { 229 &gpll2.clkr.hw, 230 }, 231 .num_parents = 1, 232 .ops = &clk_alpha_pll_postdiv_fabia_ops, 233 }, 234 }; 235 236 static struct clk_alpha_pll_postdiv gpll2_out_test = { 237 .offset = 0x2000, 238 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 239 .clkr.hw.init = &(struct clk_init_data){ 240 .name = "gpll2_out_test", 241 .parent_hws = (const struct clk_hw*[]) { 242 &gpll2.clkr.hw, 243 }, 244 .num_parents = 1, 245 .ops = &clk_alpha_pll_postdiv_fabia_ops, 246 }, 247 }; 248 249 static struct clk_alpha_pll gpll3 = { 250 .offset = 0x3000, 251 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 252 .vco_table = fabia_vco, 253 .num_vco = ARRAY_SIZE(fabia_vco), 254 .clkr = { 255 .enable_reg = 0x52000, 256 .enable_mask = BIT(3), 257 .hw.init = &(struct clk_init_data){ 258 .name = "gpll3", 259 .parent_data = (const struct clk_parent_data []) { 260 { .fw_name = "xo" }, 261 }, 262 .num_parents = 1, 263 .ops = &clk_alpha_pll_fixed_fabia_ops, 264 } 265 }, 266 }; 267 268 static struct clk_alpha_pll_postdiv gpll3_out_even = { 269 .offset = 0x3000, 270 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 271 .clkr.hw.init = &(struct clk_init_data){ 272 .name = "gpll3_out_even", 273 .parent_hws = (const struct clk_hw*[]) { 274 &gpll3.clkr.hw, 275 }, 276 .num_parents = 1, 277 .ops = &clk_alpha_pll_postdiv_fabia_ops, 278 }, 279 }; 280 281 static struct clk_alpha_pll_postdiv gpll3_out_main = { 282 .offset = 0x3000, 283 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 284 .clkr.hw.init = &(struct clk_init_data){ 285 .name = "gpll3_out_main", 286 .parent_hws = (const struct clk_hw*[]) { 287 &gpll3.clkr.hw, 288 }, 289 .num_parents = 1, 290 .ops = &clk_alpha_pll_postdiv_fabia_ops, 291 }, 292 }; 293 294 static struct clk_alpha_pll_postdiv gpll3_out_odd = { 295 .offset = 0x3000, 296 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 297 .clkr.hw.init = &(struct clk_init_data){ 298 .name = "gpll3_out_odd", 299 .parent_hws = (const struct clk_hw*[]) { 300 &gpll3.clkr.hw, 301 }, 302 .num_parents = 1, 303 .ops = &clk_alpha_pll_postdiv_fabia_ops, 304 }, 305 }; 306 307 static struct clk_alpha_pll_postdiv gpll3_out_test = { 308 .offset = 0x3000, 309 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 310 .clkr.hw.init = &(struct clk_init_data){ 311 .name = "gpll3_out_test", 312 .parent_hws = (const struct clk_hw*[]) { 313 &gpll3.clkr.hw, 314 }, 315 .num_parents = 1, 316 .ops = &clk_alpha_pll_postdiv_fabia_ops, 317 }, 318 }; 319 320 static struct clk_alpha_pll gpll4 = { 321 .offset = 0x77000, 322 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 323 .vco_table = fabia_vco, 324 .num_vco = ARRAY_SIZE(fabia_vco), 325 .clkr = { 326 .enable_reg = 0x52000, 327 .enable_mask = BIT(4), 328 .hw.init = &(struct clk_init_data){ 329 .name = "gpll4", 330 .parent_data = (const struct clk_parent_data []) { 331 { .fw_name = "xo" }, 332 }, 333 .num_parents = 1, 334 .ops = &clk_alpha_pll_fixed_fabia_ops, 335 } 336 }, 337 }; 338 339 static struct clk_alpha_pll_postdiv gpll4_out_even = { 340 .offset = 0x77000, 341 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 342 .clkr.hw.init = &(struct clk_init_data){ 343 .name = "gpll4_out_even", 344 .parent_hws = (const struct clk_hw*[]) { 345 &gpll4.clkr.hw, 346 }, 347 .num_parents = 1, 348 .ops = &clk_alpha_pll_postdiv_fabia_ops, 349 }, 350 }; 351 352 static struct clk_alpha_pll_postdiv gpll4_out_main = { 353 .offset = 0x77000, 354 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 355 .clkr.hw.init = &(struct clk_init_data){ 356 .name = "gpll4_out_main", 357 .parent_hws = (const struct clk_hw*[]) { 358 &gpll4.clkr.hw, 359 }, 360 .num_parents = 1, 361 .ops = &clk_alpha_pll_postdiv_fabia_ops, 362 }, 363 }; 364 365 static struct clk_alpha_pll_postdiv gpll4_out_odd = { 366 .offset = 0x77000, 367 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 368 .clkr.hw.init = &(struct clk_init_data){ 369 .name = "gpll4_out_odd", 370 .parent_hws = (const struct clk_hw*[]) { 371 &gpll4.clkr.hw, 372 }, 373 .num_parents = 1, 374 .ops = &clk_alpha_pll_postdiv_fabia_ops, 375 }, 376 }; 377 378 static struct clk_alpha_pll_postdiv gpll4_out_test = { 379 .offset = 0x77000, 380 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 381 .clkr.hw.init = &(struct clk_init_data){ 382 .name = "gpll4_out_test", 383 .parent_hws = (const struct clk_hw*[]) { 384 &gpll4.clkr.hw, 385 }, 386 .num_parents = 1, 387 .ops = &clk_alpha_pll_postdiv_fabia_ops, 388 }, 389 }; 390 391 enum { 392 P_AUD_REF_CLK, 393 P_GPLL0_OUT_MAIN, 394 P_GPLL4_OUT_MAIN, 395 P_PLL0_EARLY_DIV_CLK_SRC, 396 P_SLEEP_CLK, 397 P_XO, 398 }; 399 400 static const struct parent_map gcc_parent_map_0[] = { 401 { P_XO, 0 }, 402 { P_GPLL0_OUT_MAIN, 1 }, 403 { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, 404 }; 405 406 static const struct clk_parent_data gcc_parent_data_0[] = { 407 { .fw_name = "xo" }, 408 { .hw = &gpll0_out_main.clkr.hw }, 409 { .hw = &gpll0_out_main.clkr.hw }, 410 }; 411 412 static const struct parent_map gcc_parent_map_1[] = { 413 { P_XO, 0 }, 414 { P_GPLL0_OUT_MAIN, 1 }, 415 }; 416 417 static const struct clk_parent_data gcc_parent_data_1[] = { 418 { .fw_name = "xo" }, 419 { .hw = &gpll0_out_main.clkr.hw }, 420 }; 421 422 static const struct parent_map gcc_parent_map_2[] = { 423 { P_XO, 0 }, 424 { P_GPLL0_OUT_MAIN, 1 }, 425 { P_SLEEP_CLK, 5 }, 426 { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, 427 }; 428 429 static const struct clk_parent_data gcc_parent_data_2[] = { 430 { .fw_name = "xo" }, 431 { .hw = &gpll0_out_main.clkr.hw }, 432 { .fw_name = "sleep_clk" }, 433 { .hw = &gpll0_out_main.clkr.hw }, 434 }; 435 436 static const struct parent_map gcc_parent_map_3[] = { 437 { P_XO, 0 }, 438 { P_SLEEP_CLK, 5 }, 439 }; 440 441 static const struct clk_parent_data gcc_parent_data_3[] = { 442 { .fw_name = "xo" }, 443 { .fw_name = "sleep_clk" }, 444 }; 445 446 static const struct parent_map gcc_parent_map_4[] = { 447 { P_XO, 0 }, 448 { P_GPLL0_OUT_MAIN, 1 }, 449 { P_GPLL4_OUT_MAIN, 5 }, 450 }; 451 452 static const struct clk_parent_data gcc_parent_data_4[] = { 453 { .fw_name = "xo" }, 454 { .hw = &gpll0_out_main.clkr.hw }, 455 { .hw = &gpll4_out_main.clkr.hw }, 456 }; 457 458 static const struct parent_map gcc_parent_map_5[] = { 459 { P_XO, 0 }, 460 { P_GPLL0_OUT_MAIN, 1 }, 461 { P_AUD_REF_CLK, 2 }, 462 }; 463 464 static const struct clk_parent_data gcc_parent_data_5[] = { 465 { .fw_name = "xo" }, 466 { .hw = &gpll0_out_main.clkr.hw }, 467 { .fw_name = "aud_ref_clk" }, 468 }; 469 470 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = { 471 F(19200000, P_XO, 1, 0, 0), 472 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 473 { } 474 }; 475 476 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 477 .cmd_rcgr = 0x19020, 478 .mnd_width = 0, 479 .hid_width = 5, 480 .parent_map = gcc_parent_map_1, 481 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 482 .clkr.hw.init = &(struct clk_init_data){ 483 .name = "blsp1_qup1_i2c_apps_clk_src", 484 .parent_data = gcc_parent_data_1, 485 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 486 .ops = &clk_rcg2_ops, 487 }, 488 }; 489 490 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { 491 F(960000, P_XO, 10, 1, 2), 492 F(4800000, P_XO, 4, 0, 0), 493 F(9600000, P_XO, 2, 0, 0), 494 F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4), 495 F(19200000, P_XO, 1, 0, 0), 496 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 497 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 498 { } 499 }; 500 501 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 502 .cmd_rcgr = 0x1900c, 503 .mnd_width = 8, 504 .hid_width = 5, 505 .parent_map = gcc_parent_map_0, 506 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 507 .clkr.hw.init = &(struct clk_init_data){ 508 .name = "blsp1_qup1_spi_apps_clk_src", 509 .parent_data = gcc_parent_data_0, 510 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 511 .ops = &clk_rcg2_ops, 512 }, 513 }; 514 515 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 516 .cmd_rcgr = 0x1b020, 517 .mnd_width = 0, 518 .hid_width = 5, 519 .parent_map = gcc_parent_map_1, 520 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 521 .clkr.hw.init = &(struct clk_init_data){ 522 .name = "blsp1_qup2_i2c_apps_clk_src", 523 .parent_data = gcc_parent_data_1, 524 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 525 .ops = &clk_rcg2_ops, 526 }, 527 }; 528 529 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 530 .cmd_rcgr = 0x1b00c, 531 .mnd_width = 8, 532 .hid_width = 5, 533 .parent_map = gcc_parent_map_0, 534 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 535 .clkr.hw.init = &(struct clk_init_data){ 536 .name = "blsp1_qup2_spi_apps_clk_src", 537 .parent_data = gcc_parent_data_0, 538 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 539 .ops = &clk_rcg2_ops, 540 }, 541 }; 542 543 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 544 .cmd_rcgr = 0x1d020, 545 .mnd_width = 0, 546 .hid_width = 5, 547 .parent_map = gcc_parent_map_1, 548 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 549 .clkr.hw.init = &(struct clk_init_data){ 550 .name = "blsp1_qup3_i2c_apps_clk_src", 551 .parent_data = gcc_parent_data_1, 552 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 553 .ops = &clk_rcg2_ops, 554 }, 555 }; 556 557 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 558 .cmd_rcgr = 0x1d00c, 559 .mnd_width = 8, 560 .hid_width = 5, 561 .parent_map = gcc_parent_map_0, 562 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 563 .clkr.hw.init = &(struct clk_init_data){ 564 .name = "blsp1_qup3_spi_apps_clk_src", 565 .parent_data = gcc_parent_data_0, 566 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 567 .ops = &clk_rcg2_ops, 568 }, 569 }; 570 571 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 572 .cmd_rcgr = 0x1f020, 573 .mnd_width = 0, 574 .hid_width = 5, 575 .parent_map = gcc_parent_map_1, 576 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 577 .clkr.hw.init = &(struct clk_init_data){ 578 .name = "blsp1_qup4_i2c_apps_clk_src", 579 .parent_data = gcc_parent_data_1, 580 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 581 .ops = &clk_rcg2_ops, 582 }, 583 }; 584 585 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 586 .cmd_rcgr = 0x1f00c, 587 .mnd_width = 8, 588 .hid_width = 5, 589 .parent_map = gcc_parent_map_0, 590 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 591 .clkr.hw.init = &(struct clk_init_data){ 592 .name = "blsp1_qup4_spi_apps_clk_src", 593 .parent_data = gcc_parent_data_0, 594 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 595 .ops = &clk_rcg2_ops, 596 }, 597 }; 598 599 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 600 .cmd_rcgr = 0x21020, 601 .mnd_width = 0, 602 .hid_width = 5, 603 .parent_map = gcc_parent_map_1, 604 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 605 .clkr.hw.init = &(struct clk_init_data){ 606 .name = "blsp1_qup5_i2c_apps_clk_src", 607 .parent_data = gcc_parent_data_1, 608 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 609 .ops = &clk_rcg2_ops, 610 }, 611 }; 612 613 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 614 .cmd_rcgr = 0x2100c, 615 .mnd_width = 8, 616 .hid_width = 5, 617 .parent_map = gcc_parent_map_0, 618 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 619 .clkr.hw.init = &(struct clk_init_data){ 620 .name = "blsp1_qup5_spi_apps_clk_src", 621 .parent_data = gcc_parent_data_0, 622 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 623 .ops = &clk_rcg2_ops, 624 }, 625 }; 626 627 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 628 .cmd_rcgr = 0x23020, 629 .mnd_width = 0, 630 .hid_width = 5, 631 .parent_map = gcc_parent_map_1, 632 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 633 .clkr.hw.init = &(struct clk_init_data){ 634 .name = "blsp1_qup6_i2c_apps_clk_src", 635 .parent_data = gcc_parent_data_1, 636 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 637 .ops = &clk_rcg2_ops, 638 }, 639 }; 640 641 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 642 .cmd_rcgr = 0x2300c, 643 .mnd_width = 8, 644 .hid_width = 5, 645 .parent_map = gcc_parent_map_0, 646 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 647 .clkr.hw.init = &(struct clk_init_data){ 648 .name = "blsp1_qup6_spi_apps_clk_src", 649 .parent_data = gcc_parent_data_0, 650 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 651 .ops = &clk_rcg2_ops, 652 }, 653 }; 654 655 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = { 656 F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625), 657 F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625), 658 F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625), 659 F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15), 660 F(19200000, P_XO, 1, 0, 0), 661 F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5), 662 F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75), 663 F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0), 664 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375), 665 F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), 666 F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375), 667 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75), 668 F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625), 669 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 670 F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0), 671 { } 672 }; 673 674 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 675 .cmd_rcgr = 0x1a00c, 676 .mnd_width = 16, 677 .hid_width = 5, 678 .parent_map = gcc_parent_map_0, 679 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 680 .clkr.hw.init = &(struct clk_init_data){ 681 .name = "blsp1_uart1_apps_clk_src", 682 .parent_data = gcc_parent_data_0, 683 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 684 .ops = &clk_rcg2_ops, 685 }, 686 }; 687 688 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 689 .cmd_rcgr = 0x1c00c, 690 .mnd_width = 16, 691 .hid_width = 5, 692 .parent_map = gcc_parent_map_0, 693 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 694 .clkr.hw.init = &(struct clk_init_data){ 695 .name = "blsp1_uart2_apps_clk_src", 696 .parent_data = gcc_parent_data_0, 697 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 698 .ops = &clk_rcg2_ops, 699 }, 700 }; 701 702 static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 703 .cmd_rcgr = 0x1e00c, 704 .mnd_width = 16, 705 .hid_width = 5, 706 .parent_map = gcc_parent_map_0, 707 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 708 .clkr.hw.init = &(struct clk_init_data){ 709 .name = "blsp1_uart3_apps_clk_src", 710 .parent_data = gcc_parent_data_0, 711 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 712 .ops = &clk_rcg2_ops, 713 }, 714 }; 715 716 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { 717 .cmd_rcgr = 0x26020, 718 .mnd_width = 0, 719 .hid_width = 5, 720 .parent_map = gcc_parent_map_1, 721 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 722 .clkr.hw.init = &(struct clk_init_data){ 723 .name = "blsp2_qup1_i2c_apps_clk_src", 724 .parent_data = gcc_parent_data_1, 725 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 726 .ops = &clk_rcg2_ops, 727 }, 728 }; 729 730 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { 731 .cmd_rcgr = 0x2600c, 732 .mnd_width = 8, 733 .hid_width = 5, 734 .parent_map = gcc_parent_map_0, 735 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 736 .clkr.hw.init = &(struct clk_init_data){ 737 .name = "blsp2_qup1_spi_apps_clk_src", 738 .parent_data = gcc_parent_data_0, 739 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 740 .ops = &clk_rcg2_ops, 741 }, 742 }; 743 744 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { 745 .cmd_rcgr = 0x28020, 746 .mnd_width = 0, 747 .hid_width = 5, 748 .parent_map = gcc_parent_map_1, 749 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 750 .clkr.hw.init = &(struct clk_init_data){ 751 .name = "blsp2_qup2_i2c_apps_clk_src", 752 .parent_data = gcc_parent_data_1, 753 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 754 .ops = &clk_rcg2_ops, 755 }, 756 }; 757 758 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { 759 .cmd_rcgr = 0x2800c, 760 .mnd_width = 8, 761 .hid_width = 5, 762 .parent_map = gcc_parent_map_0, 763 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 764 .clkr.hw.init = &(struct clk_init_data){ 765 .name = "blsp2_qup2_spi_apps_clk_src", 766 .parent_data = gcc_parent_data_0, 767 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 768 .ops = &clk_rcg2_ops, 769 }, 770 }; 771 772 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { 773 .cmd_rcgr = 0x2a020, 774 .mnd_width = 0, 775 .hid_width = 5, 776 .parent_map = gcc_parent_map_1, 777 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 778 .clkr.hw.init = &(struct clk_init_data){ 779 .name = "blsp2_qup3_i2c_apps_clk_src", 780 .parent_data = gcc_parent_data_1, 781 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 782 .ops = &clk_rcg2_ops, 783 }, 784 }; 785 786 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { 787 .cmd_rcgr = 0x2a00c, 788 .mnd_width = 8, 789 .hid_width = 5, 790 .parent_map = gcc_parent_map_0, 791 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 792 .clkr.hw.init = &(struct clk_init_data){ 793 .name = "blsp2_qup3_spi_apps_clk_src", 794 .parent_data = gcc_parent_data_0, 795 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 796 .ops = &clk_rcg2_ops, 797 }, 798 }; 799 800 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { 801 .cmd_rcgr = 0x2c020, 802 .mnd_width = 0, 803 .hid_width = 5, 804 .parent_map = gcc_parent_map_1, 805 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 806 .clkr.hw.init = &(struct clk_init_data){ 807 .name = "blsp2_qup4_i2c_apps_clk_src", 808 .parent_data = gcc_parent_data_1, 809 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 810 .ops = &clk_rcg2_ops, 811 }, 812 }; 813 814 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { 815 .cmd_rcgr = 0x2c00c, 816 .mnd_width = 8, 817 .hid_width = 5, 818 .parent_map = gcc_parent_map_0, 819 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 820 .clkr.hw.init = &(struct clk_init_data){ 821 .name = "blsp2_qup4_spi_apps_clk_src", 822 .parent_data = gcc_parent_data_0, 823 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 824 .ops = &clk_rcg2_ops, 825 }, 826 }; 827 828 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { 829 .cmd_rcgr = 0x2e020, 830 .mnd_width = 0, 831 .hid_width = 5, 832 .parent_map = gcc_parent_map_1, 833 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 834 .clkr.hw.init = &(struct clk_init_data){ 835 .name = "blsp2_qup5_i2c_apps_clk_src", 836 .parent_data = gcc_parent_data_1, 837 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 838 .ops = &clk_rcg2_ops, 839 }, 840 }; 841 842 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { 843 .cmd_rcgr = 0x2e00c, 844 .mnd_width = 8, 845 .hid_width = 5, 846 .parent_map = gcc_parent_map_0, 847 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 848 .clkr.hw.init = &(struct clk_init_data){ 849 .name = "blsp2_qup5_spi_apps_clk_src", 850 .parent_data = gcc_parent_data_0, 851 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 852 .ops = &clk_rcg2_ops, 853 }, 854 }; 855 856 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { 857 .cmd_rcgr = 0x30020, 858 .mnd_width = 0, 859 .hid_width = 5, 860 .parent_map = gcc_parent_map_1, 861 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 862 .clkr.hw.init = &(struct clk_init_data){ 863 .name = "blsp2_qup6_i2c_apps_clk_src", 864 .parent_data = gcc_parent_data_1, 865 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 866 .ops = &clk_rcg2_ops, 867 }, 868 }; 869 870 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { 871 .cmd_rcgr = 0x3000c, 872 .mnd_width = 8, 873 .hid_width = 5, 874 .parent_map = gcc_parent_map_0, 875 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 876 .clkr.hw.init = &(struct clk_init_data){ 877 .name = "blsp2_qup6_spi_apps_clk_src", 878 .parent_data = gcc_parent_data_0, 879 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 880 .ops = &clk_rcg2_ops, 881 }, 882 }; 883 884 static struct clk_rcg2 blsp2_uart1_apps_clk_src = { 885 .cmd_rcgr = 0x2700c, 886 .mnd_width = 16, 887 .hid_width = 5, 888 .parent_map = gcc_parent_map_0, 889 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 890 .clkr.hw.init = &(struct clk_init_data){ 891 .name = "blsp2_uart1_apps_clk_src", 892 .parent_data = gcc_parent_data_0, 893 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 894 .ops = &clk_rcg2_ops, 895 }, 896 }; 897 898 static struct clk_rcg2 blsp2_uart2_apps_clk_src = { 899 .cmd_rcgr = 0x2900c, 900 .mnd_width = 16, 901 .hid_width = 5, 902 .parent_map = gcc_parent_map_0, 903 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 904 .clkr.hw.init = &(struct clk_init_data){ 905 .name = "blsp2_uart2_apps_clk_src", 906 .parent_data = gcc_parent_data_0, 907 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 908 .ops = &clk_rcg2_ops, 909 }, 910 }; 911 912 static struct clk_rcg2 blsp2_uart3_apps_clk_src = { 913 .cmd_rcgr = 0x2b00c, 914 .mnd_width = 16, 915 .hid_width = 5, 916 .parent_map = gcc_parent_map_0, 917 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 918 .clkr.hw.init = &(struct clk_init_data){ 919 .name = "blsp2_uart3_apps_clk_src", 920 .parent_data = gcc_parent_data_0, 921 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 922 .ops = &clk_rcg2_ops, 923 }, 924 }; 925 926 static const struct freq_tbl ftbl_gp1_clk_src[] = { 927 F(19200000, P_XO, 1, 0, 0), 928 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 929 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 930 { } 931 }; 932 933 static struct clk_rcg2 gp1_clk_src = { 934 .cmd_rcgr = 0x64004, 935 .mnd_width = 8, 936 .hid_width = 5, 937 .parent_map = gcc_parent_map_2, 938 .freq_tbl = ftbl_gp1_clk_src, 939 .clkr.hw.init = &(struct clk_init_data){ 940 .name = "gp1_clk_src", 941 .parent_data = gcc_parent_data_2, 942 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 943 .ops = &clk_rcg2_ops, 944 }, 945 }; 946 947 static struct clk_rcg2 gp2_clk_src = { 948 .cmd_rcgr = 0x65004, 949 .mnd_width = 8, 950 .hid_width = 5, 951 .parent_map = gcc_parent_map_2, 952 .freq_tbl = ftbl_gp1_clk_src, 953 .clkr.hw.init = &(struct clk_init_data){ 954 .name = "gp2_clk_src", 955 .parent_data = gcc_parent_data_2, 956 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 957 .ops = &clk_rcg2_ops, 958 }, 959 }; 960 961 static struct clk_rcg2 gp3_clk_src = { 962 .cmd_rcgr = 0x66004, 963 .mnd_width = 8, 964 .hid_width = 5, 965 .parent_map = gcc_parent_map_2, 966 .freq_tbl = ftbl_gp1_clk_src, 967 .clkr.hw.init = &(struct clk_init_data){ 968 .name = "gp3_clk_src", 969 .parent_data = gcc_parent_data_2, 970 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 971 .ops = &clk_rcg2_ops, 972 }, 973 }; 974 975 static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = { 976 F(19200000, P_XO, 1, 0, 0), 977 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), 978 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 979 { } 980 }; 981 982 static struct clk_rcg2 hmss_ahb_clk_src = { 983 .cmd_rcgr = 0x48014, 984 .mnd_width = 0, 985 .hid_width = 5, 986 .parent_map = gcc_parent_map_1, 987 .freq_tbl = ftbl_hmss_ahb_clk_src, 988 .clkr.hw.init = &(struct clk_init_data){ 989 .name = "hmss_ahb_clk_src", 990 .parent_data = gcc_parent_data_1, 991 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 992 .ops = &clk_rcg2_ops, 993 }, 994 }; 995 996 static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { 997 F(19200000, P_XO, 1, 0, 0), 998 { } 999 }; 1000 1001 static struct clk_rcg2 hmss_rbcpr_clk_src = { 1002 .cmd_rcgr = 0x48044, 1003 .mnd_width = 0, 1004 .hid_width = 5, 1005 .parent_map = gcc_parent_map_1, 1006 .freq_tbl = ftbl_hmss_rbcpr_clk_src, 1007 .clkr.hw.init = &(struct clk_init_data){ 1008 .name = "hmss_rbcpr_clk_src", 1009 .parent_data = gcc_parent_data_1, 1010 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1011 .ops = &clk_rcg2_ops, 1012 }, 1013 }; 1014 1015 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = { 1016 F(1010526, P_XO, 1, 1, 19), 1017 { } 1018 }; 1019 1020 static struct clk_rcg2 pcie_aux_clk_src = { 1021 .cmd_rcgr = 0x6c000, 1022 .mnd_width = 16, 1023 .hid_width = 5, 1024 .parent_map = gcc_parent_map_3, 1025 .freq_tbl = ftbl_pcie_aux_clk_src, 1026 .clkr.hw.init = &(struct clk_init_data){ 1027 .name = "pcie_aux_clk_src", 1028 .parent_data = gcc_parent_data_3, 1029 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1030 .ops = &clk_rcg2_ops, 1031 }, 1032 }; 1033 1034 static const struct freq_tbl ftbl_pdm2_clk_src[] = { 1035 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 1036 { } 1037 }; 1038 1039 static struct clk_rcg2 pdm2_clk_src = { 1040 .cmd_rcgr = 0x33010, 1041 .mnd_width = 0, 1042 .hid_width = 5, 1043 .parent_map = gcc_parent_map_1, 1044 .freq_tbl = ftbl_pdm2_clk_src, 1045 .clkr.hw.init = &(struct clk_init_data){ 1046 .name = "pdm2_clk_src", 1047 .parent_data = gcc_parent_data_1, 1048 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1049 .ops = &clk_rcg2_ops, 1050 }, 1051 }; 1052 1053 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = { 1054 F(144000, P_XO, 16, 3, 25), 1055 F(400000, P_XO, 12, 1, 4), 1056 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2), 1057 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 1058 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 1059 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 1060 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 1061 { } 1062 }; 1063 1064 static struct clk_rcg2 sdcc2_apps_clk_src = { 1065 .cmd_rcgr = 0x14010, 1066 .mnd_width = 8, 1067 .hid_width = 5, 1068 .parent_map = gcc_parent_map_4, 1069 .freq_tbl = ftbl_sdcc2_apps_clk_src, 1070 .clkr.hw.init = &(struct clk_init_data){ 1071 .name = "sdcc2_apps_clk_src", 1072 .parent_data = gcc_parent_data_4, 1073 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1074 .ops = &clk_rcg2_floor_ops, 1075 }, 1076 }; 1077 1078 static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = { 1079 F(144000, P_XO, 16, 3, 25), 1080 F(400000, P_XO, 12, 1, 4), 1081 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2), 1082 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 1083 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 1084 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 1085 { } 1086 }; 1087 1088 static struct clk_rcg2 sdcc4_apps_clk_src = { 1089 .cmd_rcgr = 0x16010, 1090 .mnd_width = 8, 1091 .hid_width = 5, 1092 .parent_map = gcc_parent_map_1, 1093 .freq_tbl = ftbl_sdcc4_apps_clk_src, 1094 .clkr.hw.init = &(struct clk_init_data){ 1095 .name = "sdcc4_apps_clk_src", 1096 .parent_data = gcc_parent_data_1, 1097 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1098 .ops = &clk_rcg2_floor_ops, 1099 }, 1100 }; 1101 1102 static const struct freq_tbl ftbl_tsif_ref_clk_src[] = { 1103 F(105495, P_XO, 1, 1, 182), 1104 { } 1105 }; 1106 1107 static struct clk_rcg2 tsif_ref_clk_src = { 1108 .cmd_rcgr = 0x36010, 1109 .mnd_width = 8, 1110 .hid_width = 5, 1111 .parent_map = gcc_parent_map_5, 1112 .freq_tbl = ftbl_tsif_ref_clk_src, 1113 .clkr.hw.init = &(struct clk_init_data){ 1114 .name = "tsif_ref_clk_src", 1115 .parent_data = gcc_parent_data_5, 1116 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1117 .ops = &clk_rcg2_ops, 1118 }, 1119 }; 1120 1121 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = { 1122 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 1123 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 1124 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 1125 { } 1126 }; 1127 1128 static struct clk_rcg2 ufs_axi_clk_src = { 1129 .cmd_rcgr = 0x75018, 1130 .mnd_width = 8, 1131 .hid_width = 5, 1132 .parent_map = gcc_parent_map_0, 1133 .freq_tbl = ftbl_ufs_axi_clk_src, 1134 .clkr.hw.init = &(struct clk_init_data){ 1135 .name = "ufs_axi_clk_src", 1136 .parent_data = gcc_parent_data_0, 1137 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1138 .ops = &clk_rcg2_ops, 1139 }, 1140 }; 1141 1142 static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = { 1143 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), 1144 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 1145 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 1146 { } 1147 }; 1148 1149 static struct clk_rcg2 ufs_unipro_core_clk_src = { 1150 .cmd_rcgr = 0x76028, 1151 .mnd_width = 8, 1152 .hid_width = 5, 1153 .parent_map = gcc_parent_map_0, 1154 .freq_tbl = ftbl_ufs_unipro_core_clk_src, 1155 .clkr.hw.init = &(struct clk_init_data){ 1156 .name = "ufs_unipro_core_clk_src", 1157 .parent_data = gcc_parent_data_0, 1158 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1159 .ops = &clk_rcg2_ops, 1160 }, 1161 }; 1162 1163 static const struct freq_tbl ftbl_usb30_master_clk_src[] = { 1164 F(19200000, P_XO, 1, 0, 0), 1165 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 1166 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), 1167 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 1168 { } 1169 }; 1170 1171 static struct clk_rcg2 usb30_master_clk_src = { 1172 .cmd_rcgr = 0xf014, 1173 .mnd_width = 8, 1174 .hid_width = 5, 1175 .parent_map = gcc_parent_map_0, 1176 .freq_tbl = ftbl_usb30_master_clk_src, 1177 .clkr.hw.init = &(struct clk_init_data){ 1178 .name = "usb30_master_clk_src", 1179 .parent_data = gcc_parent_data_0, 1180 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1181 .ops = &clk_rcg2_ops, 1182 }, 1183 }; 1184 1185 static struct clk_rcg2 usb30_mock_utmi_clk_src = { 1186 .cmd_rcgr = 0xf028, 1187 .mnd_width = 0, 1188 .hid_width = 5, 1189 .parent_map = gcc_parent_map_0, 1190 .freq_tbl = ftbl_hmss_rbcpr_clk_src, 1191 .clkr.hw.init = &(struct clk_init_data){ 1192 .name = "usb30_mock_utmi_clk_src", 1193 .parent_data = gcc_parent_data_0, 1194 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1195 .ops = &clk_rcg2_ops, 1196 }, 1197 }; 1198 1199 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { 1200 F(1200000, P_XO, 16, 0, 0), 1201 { } 1202 }; 1203 1204 static struct clk_rcg2 usb3_phy_aux_clk_src = { 1205 .cmd_rcgr = 0x5000c, 1206 .mnd_width = 0, 1207 .hid_width = 5, 1208 .parent_map = gcc_parent_map_3, 1209 .freq_tbl = ftbl_usb3_phy_aux_clk_src, 1210 .clkr.hw.init = &(struct clk_init_data){ 1211 .name = "usb3_phy_aux_clk_src", 1212 .parent_data = gcc_parent_data_3, 1213 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1214 .ops = &clk_rcg2_ops, 1215 }, 1216 }; 1217 1218 static struct clk_branch gcc_aggre1_noc_xo_clk = { 1219 .halt_reg = 0x8202c, 1220 .halt_check = BRANCH_HALT, 1221 .clkr = { 1222 .enable_reg = 0x8202c, 1223 .enable_mask = BIT(0), 1224 .hw.init = &(struct clk_init_data){ 1225 .name = "gcc_aggre1_noc_xo_clk", 1226 .ops = &clk_branch2_ops, 1227 }, 1228 }, 1229 }; 1230 1231 static struct clk_branch gcc_aggre1_ufs_axi_clk = { 1232 .halt_reg = 0x82028, 1233 .halt_check = BRANCH_HALT, 1234 .clkr = { 1235 .enable_reg = 0x82028, 1236 .enable_mask = BIT(0), 1237 .hw.init = &(struct clk_init_data){ 1238 .name = "gcc_aggre1_ufs_axi_clk", 1239 .parent_hws = (const struct clk_hw *[]) { 1240 &ufs_axi_clk_src.clkr.hw, 1241 }, 1242 .num_parents = 1, 1243 .flags = CLK_SET_RATE_PARENT, 1244 .ops = &clk_branch2_ops, 1245 }, 1246 }, 1247 }; 1248 1249 static struct clk_branch gcc_aggre1_usb3_axi_clk = { 1250 .halt_reg = 0x82024, 1251 .halt_check = BRANCH_HALT, 1252 .clkr = { 1253 .enable_reg = 0x82024, 1254 .enable_mask = BIT(0), 1255 .hw.init = &(struct clk_init_data){ 1256 .name = "gcc_aggre1_usb3_axi_clk", 1257 .parent_hws = (const struct clk_hw *[]) { 1258 &usb30_master_clk_src.clkr.hw, 1259 }, 1260 .num_parents = 1, 1261 .flags = CLK_SET_RATE_PARENT, 1262 .ops = &clk_branch2_ops, 1263 }, 1264 }, 1265 }; 1266 1267 static struct clk_branch gcc_apss_qdss_tsctr_div2_clk = { 1268 .halt_reg = 0x48090, 1269 .halt_check = BRANCH_HALT, 1270 .clkr = { 1271 .enable_reg = 0x48090, 1272 .enable_mask = BIT(0), 1273 .hw.init = &(struct clk_init_data){ 1274 .name = "gcc_apss_qdss_tsctr_div2_clk", 1275 .ops = &clk_branch2_ops, 1276 }, 1277 }, 1278 }; 1279 1280 static struct clk_branch gcc_apss_qdss_tsctr_div8_clk = { 1281 .halt_reg = 0x48094, 1282 .halt_check = BRANCH_HALT, 1283 .clkr = { 1284 .enable_reg = 0x48094, 1285 .enable_mask = BIT(0), 1286 .hw.init = &(struct clk_init_data){ 1287 .name = "gcc_apss_qdss_tsctr_div8_clk", 1288 .ops = &clk_branch2_ops, 1289 }, 1290 }, 1291 }; 1292 1293 static struct clk_branch gcc_bimc_hmss_axi_clk = { 1294 .halt_reg = 0x48004, 1295 .halt_check = BRANCH_HALT_VOTED, 1296 .clkr = { 1297 .enable_reg = 0x52004, 1298 .enable_mask = BIT(22), 1299 .hw.init = &(struct clk_init_data){ 1300 .name = "gcc_bimc_hmss_axi_clk", 1301 .ops = &clk_branch2_ops, 1302 }, 1303 }, 1304 }; 1305 1306 static struct clk_branch gcc_bimc_mss_q6_axi_clk = { 1307 .halt_reg = 0x4401c, 1308 .halt_check = BRANCH_HALT, 1309 .clkr = { 1310 .enable_reg = 0x4401c, 1311 .enable_mask = BIT(0), 1312 .hw.init = &(struct clk_init_data){ 1313 .name = "gcc_bimc_mss_q6_axi_clk", 1314 .ops = &clk_branch2_ops, 1315 }, 1316 }, 1317 }; 1318 1319 static struct clk_branch gcc_mss_cfg_ahb_clk = { 1320 .halt_reg = 0x8a000, 1321 .halt_check = BRANCH_HALT, 1322 .clkr = { 1323 .enable_reg = 0x8a000, 1324 .enable_mask = BIT(0), 1325 .hw.init = &(struct clk_init_data){ 1326 .name = "gcc_mss_cfg_ahb_clk", 1327 .ops = &clk_branch2_ops, 1328 }, 1329 }, 1330 }; 1331 1332 static struct clk_branch gcc_mss_snoc_axi_clk = { 1333 .halt_reg = 0x8a03c, 1334 .halt_check = BRANCH_HALT, 1335 .clkr = { 1336 .enable_reg = 0x8a03c, 1337 .enable_mask = BIT(0), 1338 .hw.init = &(struct clk_init_data){ 1339 .name = "gcc_mss_snoc_axi_clk", 1340 .ops = &clk_branch2_ops, 1341 }, 1342 }, 1343 }; 1344 1345 static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = { 1346 .halt_reg = 0x8a004, 1347 .halt_check = BRANCH_HALT, 1348 .clkr = { 1349 .enable_reg = 0x8a004, 1350 .enable_mask = BIT(0), 1351 .hw.init = &(struct clk_init_data){ 1352 .name = "gcc_mss_mnoc_bimc_axi_clk", 1353 .ops = &clk_branch2_ops, 1354 }, 1355 }, 1356 }; 1357 1358 static struct clk_branch gcc_boot_rom_ahb_clk = { 1359 .halt_reg = 0x38004, 1360 .halt_check = BRANCH_HALT_VOTED, 1361 .hwcg_reg = 0x38004, 1362 .hwcg_bit = 1, 1363 .clkr = { 1364 .enable_reg = 0x52004, 1365 .enable_mask = BIT(10), 1366 .hw.init = &(struct clk_init_data){ 1367 .name = "gcc_boot_rom_ahb_clk", 1368 .ops = &clk_branch2_ops, 1369 }, 1370 }, 1371 }; 1372 1373 static struct clk_branch gcc_mmss_gpll0_div_clk = { 1374 .halt_check = BRANCH_HALT_DELAY, 1375 .clkr = { 1376 .enable_reg = 0x5200c, 1377 .enable_mask = BIT(0), 1378 .hw.init = &(struct clk_init_data){ 1379 .name = "gcc_mmss_gpll0_div_clk", 1380 .parent_hws = (const struct clk_hw *[]) { 1381 &gpll0_out_main.clkr.hw, 1382 }, 1383 .num_parents = 1, 1384 .ops = &clk_branch2_ops, 1385 }, 1386 }, 1387 }; 1388 1389 static struct clk_branch gcc_mmss_gpll0_clk = { 1390 .halt_check = BRANCH_HALT_DELAY, 1391 .clkr = { 1392 .enable_reg = 0x5200c, 1393 .enable_mask = BIT(1), 1394 .hw.init = &(struct clk_init_data){ 1395 .name = "gcc_mmss_gpll0_clk", 1396 .parent_hws = (const struct clk_hw *[]) { 1397 &gpll0_out_main.clkr.hw, 1398 }, 1399 .num_parents = 1, 1400 .ops = &clk_branch2_ops, 1401 }, 1402 }, 1403 }; 1404 1405 static struct clk_branch gcc_mss_gpll0_div_clk_src = { 1406 .halt_check = BRANCH_HALT_DELAY, 1407 .clkr = { 1408 .enable_reg = 0x5200c, 1409 .enable_mask = BIT(2), 1410 .hw.init = &(struct clk_init_data){ 1411 .name = "gcc_mss_gpll0_div_clk_src", 1412 .ops = &clk_branch2_ops, 1413 }, 1414 }, 1415 }; 1416 1417 static struct clk_branch gcc_gpu_gpll0_div_clk = { 1418 .halt_check = BRANCH_HALT_DELAY, 1419 .clkr = { 1420 .enable_reg = 0x5200c, 1421 .enable_mask = BIT(3), 1422 .hw.init = &(struct clk_init_data){ 1423 .name = "gcc_gpu_gpll0_div_clk", 1424 .parent_hws = (const struct clk_hw *[]) { 1425 &gpll0_out_main.clkr.hw, 1426 }, 1427 .num_parents = 1, 1428 .ops = &clk_branch2_ops, 1429 }, 1430 }, 1431 }; 1432 1433 static struct clk_branch gcc_gpu_gpll0_clk = { 1434 .halt_check = BRANCH_HALT_DELAY, 1435 .clkr = { 1436 .enable_reg = 0x5200c, 1437 .enable_mask = BIT(4), 1438 .hw.init = &(struct clk_init_data){ 1439 .name = "gcc_gpu_gpll0_clk", 1440 .parent_hws = (const struct clk_hw *[]) { 1441 &gpll0_out_main.clkr.hw, 1442 }, 1443 .num_parents = 1, 1444 .ops = &clk_branch2_ops, 1445 }, 1446 }, 1447 }; 1448 1449 static struct clk_branch gcc_blsp1_ahb_clk = { 1450 .halt_reg = 0x17004, 1451 .halt_check = BRANCH_HALT_VOTED, 1452 .clkr = { 1453 .enable_reg = 0x52004, 1454 .enable_mask = BIT(17), 1455 .hw.init = &(struct clk_init_data){ 1456 .name = "gcc_blsp1_ahb_clk", 1457 .ops = &clk_branch2_ops, 1458 }, 1459 }, 1460 }; 1461 1462 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1463 .halt_reg = 0x19008, 1464 .halt_check = BRANCH_HALT, 1465 .clkr = { 1466 .enable_reg = 0x19008, 1467 .enable_mask = BIT(0), 1468 .hw.init = &(struct clk_init_data){ 1469 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1470 .parent_hws = (const struct clk_hw *[]) { 1471 &blsp1_qup1_i2c_apps_clk_src.clkr.hw, 1472 }, 1473 .num_parents = 1, 1474 .flags = CLK_SET_RATE_PARENT, 1475 .ops = &clk_branch2_ops, 1476 }, 1477 }, 1478 }; 1479 1480 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1481 .halt_reg = 0x19004, 1482 .halt_check = BRANCH_HALT, 1483 .clkr = { 1484 .enable_reg = 0x19004, 1485 .enable_mask = BIT(0), 1486 .hw.init = &(struct clk_init_data){ 1487 .name = "gcc_blsp1_qup1_spi_apps_clk", 1488 .parent_hws = (const struct clk_hw *[]) { 1489 &blsp1_qup1_spi_apps_clk_src.clkr.hw, 1490 }, 1491 .num_parents = 1, 1492 .flags = CLK_SET_RATE_PARENT, 1493 .ops = &clk_branch2_ops, 1494 }, 1495 }, 1496 }; 1497 1498 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1499 .halt_reg = 0x1b008, 1500 .halt_check = BRANCH_HALT, 1501 .clkr = { 1502 .enable_reg = 0x1b008, 1503 .enable_mask = BIT(0), 1504 .hw.init = &(struct clk_init_data){ 1505 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1506 .parent_hws = (const struct clk_hw *[]) { 1507 &blsp1_qup2_i2c_apps_clk_src.clkr.hw, 1508 }, 1509 .num_parents = 1, 1510 .flags = CLK_SET_RATE_PARENT, 1511 .ops = &clk_branch2_ops, 1512 }, 1513 }, 1514 }; 1515 1516 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1517 .halt_reg = 0x1b004, 1518 .halt_check = BRANCH_HALT, 1519 .clkr = { 1520 .enable_reg = 0x1b004, 1521 .enable_mask = BIT(0), 1522 .hw.init = &(struct clk_init_data){ 1523 .name = "gcc_blsp1_qup2_spi_apps_clk", 1524 .parent_hws = (const struct clk_hw *[]) { 1525 &blsp1_qup2_spi_apps_clk_src.clkr.hw, 1526 }, 1527 .num_parents = 1, 1528 .flags = CLK_SET_RATE_PARENT, 1529 .ops = &clk_branch2_ops, 1530 }, 1531 }, 1532 }; 1533 1534 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1535 .halt_reg = 0x1d008, 1536 .halt_check = BRANCH_HALT, 1537 .clkr = { 1538 .enable_reg = 0x1d008, 1539 .enable_mask = BIT(0), 1540 .hw.init = &(struct clk_init_data){ 1541 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1542 .parent_hws = (const struct clk_hw *[]) { 1543 &blsp1_qup3_i2c_apps_clk_src.clkr.hw, 1544 }, 1545 .num_parents = 1, 1546 .flags = CLK_SET_RATE_PARENT, 1547 .ops = &clk_branch2_ops, 1548 }, 1549 }, 1550 }; 1551 1552 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1553 .halt_reg = 0x1d004, 1554 .halt_check = BRANCH_HALT, 1555 .clkr = { 1556 .enable_reg = 0x1d004, 1557 .enable_mask = BIT(0), 1558 .hw.init = &(struct clk_init_data){ 1559 .name = "gcc_blsp1_qup3_spi_apps_clk", 1560 .parent_hws = (const struct clk_hw *[]) { 1561 &blsp1_qup3_spi_apps_clk_src.clkr.hw, 1562 }, 1563 .num_parents = 1, 1564 .flags = CLK_SET_RATE_PARENT, 1565 .ops = &clk_branch2_ops, 1566 }, 1567 }, 1568 }; 1569 1570 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1571 .halt_reg = 0x1f008, 1572 .halt_check = BRANCH_HALT, 1573 .clkr = { 1574 .enable_reg = 0x1f008, 1575 .enable_mask = BIT(0), 1576 .hw.init = &(struct clk_init_data){ 1577 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1578 .parent_hws = (const struct clk_hw *[]) { 1579 &blsp1_qup4_i2c_apps_clk_src.clkr.hw, 1580 }, 1581 .num_parents = 1, 1582 .flags = CLK_SET_RATE_PARENT, 1583 .ops = &clk_branch2_ops, 1584 }, 1585 }, 1586 }; 1587 1588 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1589 .halt_reg = 0x1f004, 1590 .halt_check = BRANCH_HALT, 1591 .clkr = { 1592 .enable_reg = 0x1f004, 1593 .enable_mask = BIT(0), 1594 .hw.init = &(struct clk_init_data){ 1595 .name = "gcc_blsp1_qup4_spi_apps_clk", 1596 .parent_hws = (const struct clk_hw *[]) { 1597 &blsp1_qup4_spi_apps_clk_src.clkr.hw, 1598 }, 1599 .num_parents = 1, 1600 .flags = CLK_SET_RATE_PARENT, 1601 .ops = &clk_branch2_ops, 1602 }, 1603 }, 1604 }; 1605 1606 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1607 .halt_reg = 0x21008, 1608 .halt_check = BRANCH_HALT, 1609 .clkr = { 1610 .enable_reg = 0x21008, 1611 .enable_mask = BIT(0), 1612 .hw.init = &(struct clk_init_data){ 1613 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1614 .parent_hws = (const struct clk_hw *[]) { 1615 &blsp1_qup5_i2c_apps_clk_src.clkr.hw, 1616 }, 1617 .num_parents = 1, 1618 .flags = CLK_SET_RATE_PARENT, 1619 .ops = &clk_branch2_ops, 1620 }, 1621 }, 1622 }; 1623 1624 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1625 .halt_reg = 0x21004, 1626 .halt_check = BRANCH_HALT, 1627 .clkr = { 1628 .enable_reg = 0x21004, 1629 .enable_mask = BIT(0), 1630 .hw.init = &(struct clk_init_data){ 1631 .name = "gcc_blsp1_qup5_spi_apps_clk", 1632 .parent_hws = (const struct clk_hw *[]) { 1633 &blsp1_qup5_spi_apps_clk_src.clkr.hw, 1634 }, 1635 .num_parents = 1, 1636 .flags = CLK_SET_RATE_PARENT, 1637 .ops = &clk_branch2_ops, 1638 }, 1639 }, 1640 }; 1641 1642 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1643 .halt_reg = 0x23008, 1644 .halt_check = BRANCH_HALT, 1645 .clkr = { 1646 .enable_reg = 0x23008, 1647 .enable_mask = BIT(0), 1648 .hw.init = &(struct clk_init_data){ 1649 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1650 .parent_hws = (const struct clk_hw *[]) { 1651 &blsp1_qup6_i2c_apps_clk_src.clkr.hw, 1652 }, 1653 .num_parents = 1, 1654 .flags = CLK_SET_RATE_PARENT, 1655 .ops = &clk_branch2_ops, 1656 }, 1657 }, 1658 }; 1659 1660 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1661 .halt_reg = 0x23004, 1662 .halt_check = BRANCH_HALT, 1663 .clkr = { 1664 .enable_reg = 0x23004, 1665 .enable_mask = BIT(0), 1666 .hw.init = &(struct clk_init_data){ 1667 .name = "gcc_blsp1_qup6_spi_apps_clk", 1668 .parent_hws = (const struct clk_hw *[]) { 1669 &blsp1_qup6_spi_apps_clk_src.clkr.hw, 1670 }, 1671 .num_parents = 1, 1672 .flags = CLK_SET_RATE_PARENT, 1673 .ops = &clk_branch2_ops, 1674 }, 1675 }, 1676 }; 1677 1678 static struct clk_branch gcc_blsp1_sleep_clk = { 1679 .halt_reg = 0x17008, 1680 .halt_check = BRANCH_HALT_VOTED, 1681 .clkr = { 1682 .enable_reg = 0x52004, 1683 .enable_mask = BIT(16), 1684 .hw.init = &(struct clk_init_data){ 1685 .name = "gcc_blsp1_sleep_clk", 1686 .ops = &clk_branch2_ops, 1687 }, 1688 }, 1689 }; 1690 1691 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1692 .halt_reg = 0x1a004, 1693 .halt_check = BRANCH_HALT, 1694 .clkr = { 1695 .enable_reg = 0x1a004, 1696 .enable_mask = BIT(0), 1697 .hw.init = &(struct clk_init_data){ 1698 .name = "gcc_blsp1_uart1_apps_clk", 1699 .parent_hws = (const struct clk_hw *[]) { 1700 &blsp1_uart1_apps_clk_src.clkr.hw, 1701 }, 1702 .num_parents = 1, 1703 .flags = CLK_SET_RATE_PARENT, 1704 .ops = &clk_branch2_ops, 1705 }, 1706 }, 1707 }; 1708 1709 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1710 .halt_reg = 0x1c004, 1711 .halt_check = BRANCH_HALT, 1712 .clkr = { 1713 .enable_reg = 0x1c004, 1714 .enable_mask = BIT(0), 1715 .hw.init = &(struct clk_init_data){ 1716 .name = "gcc_blsp1_uart2_apps_clk", 1717 .parent_hws = (const struct clk_hw *[]) { 1718 &blsp1_uart2_apps_clk_src.clkr.hw, 1719 }, 1720 .num_parents = 1, 1721 .flags = CLK_SET_RATE_PARENT, 1722 .ops = &clk_branch2_ops, 1723 }, 1724 }, 1725 }; 1726 1727 static struct clk_branch gcc_blsp1_uart3_apps_clk = { 1728 .halt_reg = 0x1e004, 1729 .halt_check = BRANCH_HALT, 1730 .clkr = { 1731 .enable_reg = 0x1e004, 1732 .enable_mask = BIT(0), 1733 .hw.init = &(struct clk_init_data){ 1734 .name = "gcc_blsp1_uart3_apps_clk", 1735 .parent_hws = (const struct clk_hw *[]) { 1736 &blsp1_uart3_apps_clk_src.clkr.hw, 1737 }, 1738 .num_parents = 1, 1739 .flags = CLK_SET_RATE_PARENT, 1740 .ops = &clk_branch2_ops, 1741 }, 1742 }, 1743 }; 1744 1745 static struct clk_branch gcc_blsp2_ahb_clk = { 1746 .halt_reg = 0x25004, 1747 .halt_check = BRANCH_HALT_VOTED, 1748 .clkr = { 1749 .enable_reg = 0x52004, 1750 .enable_mask = BIT(15), 1751 .hw.init = &(struct clk_init_data){ 1752 .name = "gcc_blsp2_ahb_clk", 1753 .ops = &clk_branch2_ops, 1754 }, 1755 }, 1756 }; 1757 1758 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { 1759 .halt_reg = 0x26008, 1760 .halt_check = BRANCH_HALT, 1761 .clkr = { 1762 .enable_reg = 0x26008, 1763 .enable_mask = BIT(0), 1764 .hw.init = &(struct clk_init_data){ 1765 .name = "gcc_blsp2_qup1_i2c_apps_clk", 1766 .parent_hws = (const struct clk_hw *[]) { 1767 &blsp2_qup1_i2c_apps_clk_src.clkr.hw, 1768 }, 1769 .num_parents = 1, 1770 .flags = CLK_SET_RATE_PARENT, 1771 .ops = &clk_branch2_ops, 1772 }, 1773 }, 1774 }; 1775 1776 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { 1777 .halt_reg = 0x26004, 1778 .halt_check = BRANCH_HALT, 1779 .clkr = { 1780 .enable_reg = 0x26004, 1781 .enable_mask = BIT(0), 1782 .hw.init = &(struct clk_init_data){ 1783 .name = "gcc_blsp2_qup1_spi_apps_clk", 1784 .parent_hws = (const struct clk_hw *[]) { 1785 &blsp2_qup1_spi_apps_clk_src.clkr.hw, 1786 }, 1787 .num_parents = 1, 1788 .flags = CLK_SET_RATE_PARENT, 1789 .ops = &clk_branch2_ops, 1790 }, 1791 }, 1792 }; 1793 1794 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { 1795 .halt_reg = 0x28008, 1796 .halt_check = BRANCH_HALT, 1797 .clkr = { 1798 .enable_reg = 0x28008, 1799 .enable_mask = BIT(0), 1800 .hw.init = &(struct clk_init_data){ 1801 .name = "gcc_blsp2_qup2_i2c_apps_clk", 1802 .parent_hws = (const struct clk_hw *[]) { 1803 &blsp2_qup2_i2c_apps_clk_src.clkr.hw, 1804 }, 1805 .num_parents = 1, 1806 .flags = CLK_SET_RATE_PARENT, 1807 .ops = &clk_branch2_ops, 1808 }, 1809 }, 1810 }; 1811 1812 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { 1813 .halt_reg = 0x28004, 1814 .halt_check = BRANCH_HALT, 1815 .clkr = { 1816 .enable_reg = 0x28004, 1817 .enable_mask = BIT(0), 1818 .hw.init = &(struct clk_init_data){ 1819 .name = "gcc_blsp2_qup2_spi_apps_clk", 1820 .parent_hws = (const struct clk_hw *[]) { 1821 &blsp2_qup2_spi_apps_clk_src.clkr.hw, 1822 }, 1823 .num_parents = 1, 1824 .flags = CLK_SET_RATE_PARENT, 1825 .ops = &clk_branch2_ops, 1826 }, 1827 }, 1828 }; 1829 1830 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { 1831 .halt_reg = 0x2a008, 1832 .halt_check = BRANCH_HALT, 1833 .clkr = { 1834 .enable_reg = 0x2a008, 1835 .enable_mask = BIT(0), 1836 .hw.init = &(struct clk_init_data){ 1837 .name = "gcc_blsp2_qup3_i2c_apps_clk", 1838 .parent_hws = (const struct clk_hw *[]) { 1839 &blsp2_qup3_i2c_apps_clk_src.clkr.hw, 1840 }, 1841 .num_parents = 1, 1842 .flags = CLK_SET_RATE_PARENT, 1843 .ops = &clk_branch2_ops, 1844 }, 1845 }, 1846 }; 1847 1848 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { 1849 .halt_reg = 0x2a004, 1850 .halt_check = BRANCH_HALT, 1851 .clkr = { 1852 .enable_reg = 0x2a004, 1853 .enable_mask = BIT(0), 1854 .hw.init = &(struct clk_init_data){ 1855 .name = "gcc_blsp2_qup3_spi_apps_clk", 1856 .parent_hws = (const struct clk_hw *[]) { 1857 &blsp2_qup3_spi_apps_clk_src.clkr.hw, 1858 }, 1859 .num_parents = 1, 1860 .flags = CLK_SET_RATE_PARENT, 1861 .ops = &clk_branch2_ops, 1862 }, 1863 }, 1864 }; 1865 1866 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { 1867 .halt_reg = 0x2c008, 1868 .halt_check = BRANCH_HALT, 1869 .clkr = { 1870 .enable_reg = 0x2c008, 1871 .enable_mask = BIT(0), 1872 .hw.init = &(struct clk_init_data){ 1873 .name = "gcc_blsp2_qup4_i2c_apps_clk", 1874 .parent_hws = (const struct clk_hw *[]) { 1875 &blsp2_qup4_i2c_apps_clk_src.clkr.hw, 1876 }, 1877 .num_parents = 1, 1878 .flags = CLK_SET_RATE_PARENT, 1879 .ops = &clk_branch2_ops, 1880 }, 1881 }, 1882 }; 1883 1884 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { 1885 .halt_reg = 0x2c004, 1886 .halt_check = BRANCH_HALT, 1887 .clkr = { 1888 .enable_reg = 0x2c004, 1889 .enable_mask = BIT(0), 1890 .hw.init = &(struct clk_init_data){ 1891 .name = "gcc_blsp2_qup4_spi_apps_clk", 1892 .parent_hws = (const struct clk_hw *[]) { 1893 &blsp2_qup4_spi_apps_clk_src.clkr.hw, 1894 }, 1895 .num_parents = 1, 1896 .flags = CLK_SET_RATE_PARENT, 1897 .ops = &clk_branch2_ops, 1898 }, 1899 }, 1900 }; 1901 1902 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { 1903 .halt_reg = 0x2e008, 1904 .halt_check = BRANCH_HALT, 1905 .clkr = { 1906 .enable_reg = 0x2e008, 1907 .enable_mask = BIT(0), 1908 .hw.init = &(struct clk_init_data){ 1909 .name = "gcc_blsp2_qup5_i2c_apps_clk", 1910 .parent_hws = (const struct clk_hw *[]) { 1911 &blsp2_qup5_i2c_apps_clk_src.clkr.hw, 1912 }, 1913 .num_parents = 1, 1914 .flags = CLK_SET_RATE_PARENT, 1915 .ops = &clk_branch2_ops, 1916 }, 1917 }, 1918 }; 1919 1920 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { 1921 .halt_reg = 0x2e004, 1922 .halt_check = BRANCH_HALT, 1923 .clkr = { 1924 .enable_reg = 0x2e004, 1925 .enable_mask = BIT(0), 1926 .hw.init = &(struct clk_init_data){ 1927 .name = "gcc_blsp2_qup5_spi_apps_clk", 1928 .parent_hws = (const struct clk_hw *[]) { 1929 &blsp2_qup5_spi_apps_clk_src.clkr.hw, 1930 }, 1931 .num_parents = 1, 1932 .flags = CLK_SET_RATE_PARENT, 1933 .ops = &clk_branch2_ops, 1934 }, 1935 }, 1936 }; 1937 1938 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { 1939 .halt_reg = 0x30008, 1940 .halt_check = BRANCH_HALT, 1941 .clkr = { 1942 .enable_reg = 0x30008, 1943 .enable_mask = BIT(0), 1944 .hw.init = &(struct clk_init_data){ 1945 .name = "gcc_blsp2_qup6_i2c_apps_clk", 1946 .parent_hws = (const struct clk_hw *[]) { 1947 &blsp2_qup6_i2c_apps_clk_src.clkr.hw, 1948 }, 1949 .num_parents = 1, 1950 .flags = CLK_SET_RATE_PARENT, 1951 .ops = &clk_branch2_ops, 1952 }, 1953 }, 1954 }; 1955 1956 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { 1957 .halt_reg = 0x30004, 1958 .halt_check = BRANCH_HALT, 1959 .clkr = { 1960 .enable_reg = 0x30004, 1961 .enable_mask = BIT(0), 1962 .hw.init = &(struct clk_init_data){ 1963 .name = "gcc_blsp2_qup6_spi_apps_clk", 1964 .parent_hws = (const struct clk_hw *[]) { 1965 &blsp2_qup6_spi_apps_clk_src.clkr.hw, 1966 }, 1967 .num_parents = 1, 1968 .flags = CLK_SET_RATE_PARENT, 1969 .ops = &clk_branch2_ops, 1970 }, 1971 }, 1972 }; 1973 1974 static struct clk_branch gcc_blsp2_sleep_clk = { 1975 .halt_reg = 0x25008, 1976 .halt_check = BRANCH_HALT_VOTED, 1977 .clkr = { 1978 .enable_reg = 0x52004, 1979 .enable_mask = BIT(14), 1980 .hw.init = &(struct clk_init_data){ 1981 .name = "gcc_blsp2_sleep_clk", 1982 .ops = &clk_branch2_ops, 1983 }, 1984 }, 1985 }; 1986 1987 static struct clk_branch gcc_blsp2_uart1_apps_clk = { 1988 .halt_reg = 0x27004, 1989 .halt_check = BRANCH_HALT, 1990 .clkr = { 1991 .enable_reg = 0x27004, 1992 .enable_mask = BIT(0), 1993 .hw.init = &(struct clk_init_data){ 1994 .name = "gcc_blsp2_uart1_apps_clk", 1995 .parent_hws = (const struct clk_hw *[]) { 1996 &blsp2_uart1_apps_clk_src.clkr.hw, 1997 }, 1998 .num_parents = 1, 1999 .flags = CLK_SET_RATE_PARENT, 2000 .ops = &clk_branch2_ops, 2001 }, 2002 }, 2003 }; 2004 2005 static struct clk_branch gcc_blsp2_uart2_apps_clk = { 2006 .halt_reg = 0x29004, 2007 .halt_check = BRANCH_HALT, 2008 .clkr = { 2009 .enable_reg = 0x29004, 2010 .enable_mask = BIT(0), 2011 .hw.init = &(struct clk_init_data){ 2012 .name = "gcc_blsp2_uart2_apps_clk", 2013 .parent_hws = (const struct clk_hw *[]) { 2014 &blsp2_uart2_apps_clk_src.clkr.hw, 2015 }, 2016 .num_parents = 1, 2017 .flags = CLK_SET_RATE_PARENT, 2018 .ops = &clk_branch2_ops, 2019 }, 2020 }, 2021 }; 2022 2023 static struct clk_branch gcc_blsp2_uart3_apps_clk = { 2024 .halt_reg = 0x2b004, 2025 .halt_check = BRANCH_HALT, 2026 .clkr = { 2027 .enable_reg = 0x2b004, 2028 .enable_mask = BIT(0), 2029 .hw.init = &(struct clk_init_data){ 2030 .name = "gcc_blsp2_uart3_apps_clk", 2031 .parent_hws = (const struct clk_hw *[]) { 2032 &blsp2_uart3_apps_clk_src.clkr.hw, 2033 }, 2034 .num_parents = 1, 2035 .flags = CLK_SET_RATE_PARENT, 2036 .ops = &clk_branch2_ops, 2037 }, 2038 }, 2039 }; 2040 2041 static struct clk_branch gcc_cfg_noc_usb3_axi_clk = { 2042 .halt_reg = 0x5018, 2043 .halt_check = BRANCH_HALT, 2044 .clkr = { 2045 .enable_reg = 0x5018, 2046 .enable_mask = BIT(0), 2047 .hw.init = &(struct clk_init_data){ 2048 .name = "gcc_cfg_noc_usb3_axi_clk", 2049 .parent_hws = (const struct clk_hw *[]) { 2050 &usb30_master_clk_src.clkr.hw, 2051 }, 2052 .num_parents = 1, 2053 .flags = CLK_SET_RATE_PARENT, 2054 .ops = &clk_branch2_ops, 2055 }, 2056 }, 2057 }; 2058 2059 static struct clk_branch gcc_gp1_clk = { 2060 .halt_reg = 0x64000, 2061 .halt_check = BRANCH_HALT, 2062 .clkr = { 2063 .enable_reg = 0x64000, 2064 .enable_mask = BIT(0), 2065 .hw.init = &(struct clk_init_data){ 2066 .name = "gcc_gp1_clk", 2067 .parent_hws = (const struct clk_hw *[]) { 2068 &gp1_clk_src.clkr.hw, 2069 }, 2070 .num_parents = 1, 2071 .flags = CLK_SET_RATE_PARENT, 2072 .ops = &clk_branch2_ops, 2073 }, 2074 }, 2075 }; 2076 2077 static struct clk_branch gcc_gp2_clk = { 2078 .halt_reg = 0x65000, 2079 .halt_check = BRANCH_HALT, 2080 .clkr = { 2081 .enable_reg = 0x65000, 2082 .enable_mask = BIT(0), 2083 .hw.init = &(struct clk_init_data){ 2084 .name = "gcc_gp2_clk", 2085 .parent_hws = (const struct clk_hw *[]) { 2086 &gp2_clk_src.clkr.hw, 2087 }, 2088 .num_parents = 1, 2089 .flags = CLK_SET_RATE_PARENT, 2090 .ops = &clk_branch2_ops, 2091 }, 2092 }, 2093 }; 2094 2095 static struct clk_branch gcc_gp3_clk = { 2096 .halt_reg = 0x66000, 2097 .halt_check = BRANCH_HALT, 2098 .clkr = { 2099 .enable_reg = 0x66000, 2100 .enable_mask = BIT(0), 2101 .hw.init = &(struct clk_init_data){ 2102 .name = "gcc_gp3_clk", 2103 .parent_hws = (const struct clk_hw *[]) { 2104 &gp3_clk_src.clkr.hw, 2105 }, 2106 .num_parents = 1, 2107 .flags = CLK_SET_RATE_PARENT, 2108 .ops = &clk_branch2_ops, 2109 }, 2110 }, 2111 }; 2112 2113 static struct clk_branch gcc_bimc_gfx_clk = { 2114 .halt_reg = 0x46040, 2115 .halt_check = BRANCH_HALT_SKIP, 2116 .clkr = { 2117 .enable_reg = 0x46040, 2118 .enable_mask = BIT(0), 2119 .hw.init = &(struct clk_init_data){ 2120 .name = "gcc_bimc_gfx_clk", 2121 .ops = &clk_branch2_ops, 2122 }, 2123 }, 2124 }; 2125 2126 static struct clk_branch gcc_gpu_bimc_gfx_clk = { 2127 .halt_reg = 0x71010, 2128 .halt_check = BRANCH_HALT_SKIP, 2129 .clkr = { 2130 .enable_reg = 0x71010, 2131 .enable_mask = BIT(0), 2132 .hw.init = &(struct clk_init_data){ 2133 .name = "gcc_gpu_bimc_gfx_clk", 2134 .ops = &clk_branch2_ops, 2135 }, 2136 }, 2137 }; 2138 2139 static struct clk_branch gcc_gpu_bimc_gfx_src_clk = { 2140 .halt_reg = 0x7100c, 2141 .halt_check = BRANCH_HALT, 2142 .clkr = { 2143 .enable_reg = 0x7100c, 2144 .enable_mask = BIT(0), 2145 .hw.init = &(struct clk_init_data){ 2146 .name = "gcc_gpu_bimc_gfx_src_clk", 2147 .ops = &clk_branch2_ops, 2148 }, 2149 }, 2150 }; 2151 2152 static struct clk_branch gcc_gpu_cfg_ahb_clk = { 2153 .halt_reg = 0x71004, 2154 .halt_check = BRANCH_HALT_SKIP, 2155 .clkr = { 2156 .enable_reg = 0x71004, 2157 .enable_mask = BIT(0), 2158 .hw.init = &(struct clk_init_data){ 2159 .name = "gcc_gpu_cfg_ahb_clk", 2160 .ops = &clk_branch2_ops, 2161 /* 2162 * The GPU IOMMU depends on this clock and hypervisor 2163 * will crash the SoC if this clock goes down, due to 2164 * secure contexts protection. 2165 */ 2166 .flags = CLK_IS_CRITICAL, 2167 }, 2168 }, 2169 }; 2170 2171 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2172 .halt_reg = 0x71018, 2173 .halt_check = BRANCH_HALT, 2174 .clkr = { 2175 .enable_reg = 0x71018, 2176 .enable_mask = BIT(0), 2177 .hw.init = &(struct clk_init_data){ 2178 .name = "gcc_gpu_snoc_dvm_gfx_clk", 2179 .ops = &clk_branch2_ops, 2180 }, 2181 }, 2182 }; 2183 2184 static struct clk_branch gcc_hmss_ahb_clk = { 2185 .halt_reg = 0x48000, 2186 .halt_check = BRANCH_HALT_VOTED, 2187 .clkr = { 2188 .enable_reg = 0x52004, 2189 .enable_mask = BIT(21), 2190 .hw.init = &(struct clk_init_data){ 2191 .name = "gcc_hmss_ahb_clk", 2192 .parent_hws = (const struct clk_hw *[]) { 2193 &hmss_ahb_clk_src.clkr.hw, 2194 }, 2195 .num_parents = 1, 2196 .flags = CLK_SET_RATE_PARENT, 2197 .ops = &clk_branch2_ops, 2198 }, 2199 }, 2200 }; 2201 2202 static struct clk_branch gcc_hmss_at_clk = { 2203 .halt_reg = 0x48010, 2204 .halt_check = BRANCH_HALT, 2205 .clkr = { 2206 .enable_reg = 0x48010, 2207 .enable_mask = BIT(0), 2208 .hw.init = &(struct clk_init_data){ 2209 .name = "gcc_hmss_at_clk", 2210 .ops = &clk_branch2_ops, 2211 }, 2212 }, 2213 }; 2214 2215 static struct clk_branch gcc_hmss_rbcpr_clk = { 2216 .halt_reg = 0x48008, 2217 .halt_check = BRANCH_HALT, 2218 .clkr = { 2219 .enable_reg = 0x48008, 2220 .enable_mask = BIT(0), 2221 .hw.init = &(struct clk_init_data){ 2222 .name = "gcc_hmss_rbcpr_clk", 2223 .parent_hws = (const struct clk_hw *[]) { 2224 &hmss_rbcpr_clk_src.clkr.hw, 2225 }, 2226 .num_parents = 1, 2227 .flags = CLK_SET_RATE_PARENT, 2228 .ops = &clk_branch2_ops, 2229 }, 2230 }, 2231 }; 2232 2233 static struct clk_branch gcc_hmss_trig_clk = { 2234 .halt_reg = 0x4800c, 2235 .halt_check = BRANCH_HALT, 2236 .clkr = { 2237 .enable_reg = 0x4800c, 2238 .enable_mask = BIT(0), 2239 .hw.init = &(struct clk_init_data){ 2240 .name = "gcc_hmss_trig_clk", 2241 .ops = &clk_branch2_ops, 2242 }, 2243 }, 2244 }; 2245 2246 static struct freq_tbl ftbl_hmss_gpll0_clk_src[] = { 2247 F( 300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 2248 F( 600000000, P_GPLL0_OUT_MAIN, 1, 0, 0), 2249 { } 2250 }; 2251 2252 static struct clk_rcg2 hmss_gpll0_clk_src = { 2253 .cmd_rcgr = 0x4805c, 2254 .hid_width = 5, 2255 .parent_map = gcc_parent_map_1, 2256 .freq_tbl = ftbl_hmss_gpll0_clk_src, 2257 .clkr.hw.init = &(struct clk_init_data) { 2258 .name = "hmss_gpll0_clk_src", 2259 .parent_data = gcc_parent_data_1, 2260 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2261 .ops = &clk_rcg2_ops, 2262 }, 2263 }; 2264 2265 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { 2266 .halt_reg = 0x9004, 2267 .halt_check = BRANCH_HALT, 2268 .clkr = { 2269 .enable_reg = 0x9004, 2270 .enable_mask = BIT(0), 2271 .hw.init = &(struct clk_init_data){ 2272 .name = "gcc_mmss_noc_cfg_ahb_clk", 2273 .ops = &clk_branch2_ops, 2274 /* 2275 * Any access to mmss depends on this clock. 2276 * Gating this clock has been shown to crash the system 2277 * when mmssnoc_axi_rpm_clk is inited in rpmcc. 2278 */ 2279 .flags = CLK_IS_CRITICAL, 2280 }, 2281 }, 2282 }; 2283 2284 static struct clk_branch gcc_mmss_qm_ahb_clk = { 2285 .halt_reg = 0x9030, 2286 .halt_check = BRANCH_HALT, 2287 .clkr = { 2288 .enable_reg = 0x9030, 2289 .enable_mask = BIT(0), 2290 .hw.init = &(struct clk_init_data){ 2291 .name = "gcc_mmss_qm_ahb_clk", 2292 .ops = &clk_branch2_ops, 2293 }, 2294 }, 2295 }; 2296 2297 static struct clk_branch gcc_mmss_qm_core_clk = { 2298 .halt_reg = 0x900c, 2299 .halt_check = BRANCH_HALT, 2300 .clkr = { 2301 .enable_reg = 0x900c, 2302 .enable_mask = BIT(0), 2303 .hw.init = &(struct clk_init_data){ 2304 .name = "gcc_mmss_qm_core_clk", 2305 .ops = &clk_branch2_ops, 2306 }, 2307 }, 2308 }; 2309 2310 static struct clk_branch gcc_mmss_sys_noc_axi_clk = { 2311 .halt_reg = 0x9000, 2312 .halt_check = BRANCH_HALT, 2313 .clkr = { 2314 .enable_reg = 0x9000, 2315 .enable_mask = BIT(0), 2316 .hw.init = &(struct clk_init_data){ 2317 .name = "gcc_mmss_sys_noc_axi_clk", 2318 .ops = &clk_branch2_ops, 2319 }, 2320 }, 2321 }; 2322 2323 static struct clk_branch gcc_mss_at_clk = { 2324 .halt_reg = 0x8a00c, 2325 .halt_check = BRANCH_HALT, 2326 .clkr = { 2327 .enable_reg = 0x8a00c, 2328 .enable_mask = BIT(0), 2329 .hw.init = &(struct clk_init_data){ 2330 .name = "gcc_mss_at_clk", 2331 .ops = &clk_branch2_ops, 2332 }, 2333 }, 2334 }; 2335 2336 static struct clk_branch gcc_pcie_0_aux_clk = { 2337 .halt_reg = 0x6b014, 2338 .halt_check = BRANCH_HALT, 2339 .clkr = { 2340 .enable_reg = 0x6b014, 2341 .enable_mask = BIT(0), 2342 .hw.init = &(struct clk_init_data){ 2343 .name = "gcc_pcie_0_aux_clk", 2344 .parent_hws = (const struct clk_hw *[]) { 2345 &pcie_aux_clk_src.clkr.hw, 2346 }, 2347 .num_parents = 1, 2348 .flags = CLK_SET_RATE_PARENT, 2349 .ops = &clk_branch2_ops, 2350 }, 2351 }, 2352 }; 2353 2354 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 2355 .halt_reg = 0x6b010, 2356 .halt_check = BRANCH_HALT, 2357 .clkr = { 2358 .enable_reg = 0x6b010, 2359 .enable_mask = BIT(0), 2360 .hw.init = &(struct clk_init_data){ 2361 .name = "gcc_pcie_0_cfg_ahb_clk", 2362 .ops = &clk_branch2_ops, 2363 }, 2364 }, 2365 }; 2366 2367 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 2368 .halt_reg = 0x6b00c, 2369 .halt_check = BRANCH_HALT, 2370 .clkr = { 2371 .enable_reg = 0x6b00c, 2372 .enable_mask = BIT(0), 2373 .hw.init = &(struct clk_init_data){ 2374 .name = "gcc_pcie_0_mstr_axi_clk", 2375 .ops = &clk_branch2_ops, 2376 }, 2377 }, 2378 }; 2379 2380 static struct clk_branch gcc_pcie_0_pipe_clk = { 2381 .halt_reg = 0x6b018, 2382 .halt_check = BRANCH_HALT_SKIP, 2383 .clkr = { 2384 .enable_reg = 0x6b018, 2385 .enable_mask = BIT(0), 2386 .hw.init = &(struct clk_init_data){ 2387 .name = "gcc_pcie_0_pipe_clk", 2388 .ops = &clk_branch2_ops, 2389 }, 2390 }, 2391 }; 2392 2393 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 2394 .halt_reg = 0x6b008, 2395 .halt_check = BRANCH_HALT, 2396 .clkr = { 2397 .enable_reg = 0x6b008, 2398 .enable_mask = BIT(0), 2399 .hw.init = &(struct clk_init_data){ 2400 .name = "gcc_pcie_0_slv_axi_clk", 2401 .ops = &clk_branch2_ops, 2402 }, 2403 }, 2404 }; 2405 2406 static struct clk_branch gcc_pcie_phy_aux_clk = { 2407 .halt_reg = 0x6f004, 2408 .halt_check = BRANCH_HALT, 2409 .clkr = { 2410 .enable_reg = 0x6f004, 2411 .enable_mask = BIT(0), 2412 .hw.init = &(struct clk_init_data){ 2413 .name = "gcc_pcie_phy_aux_clk", 2414 .parent_hws = (const struct clk_hw *[]) { 2415 &pcie_aux_clk_src.clkr.hw, 2416 }, 2417 .num_parents = 1, 2418 .flags = CLK_SET_RATE_PARENT, 2419 .ops = &clk_branch2_ops, 2420 }, 2421 }, 2422 }; 2423 2424 static struct clk_branch gcc_pdm2_clk = { 2425 .halt_reg = 0x3300c, 2426 .halt_check = BRANCH_HALT, 2427 .clkr = { 2428 .enable_reg = 0x3300c, 2429 .enable_mask = BIT(0), 2430 .hw.init = &(struct clk_init_data){ 2431 .name = "gcc_pdm2_clk", 2432 .parent_hws = (const struct clk_hw *[]) { 2433 &pdm2_clk_src.clkr.hw, 2434 }, 2435 .num_parents = 1, 2436 .flags = CLK_SET_RATE_PARENT, 2437 .ops = &clk_branch2_ops, 2438 }, 2439 }, 2440 }; 2441 2442 static struct clk_branch gcc_pdm_ahb_clk = { 2443 .halt_reg = 0x33004, 2444 .halt_check = BRANCH_HALT, 2445 .clkr = { 2446 .enable_reg = 0x33004, 2447 .enable_mask = BIT(0), 2448 .hw.init = &(struct clk_init_data){ 2449 .name = "gcc_pdm_ahb_clk", 2450 .ops = &clk_branch2_ops, 2451 }, 2452 }, 2453 }; 2454 2455 static struct clk_branch gcc_pdm_xo4_clk = { 2456 .halt_reg = 0x33008, 2457 .halt_check = BRANCH_HALT, 2458 .clkr = { 2459 .enable_reg = 0x33008, 2460 .enable_mask = BIT(0), 2461 .hw.init = &(struct clk_init_data){ 2462 .name = "gcc_pdm_xo4_clk", 2463 .ops = &clk_branch2_ops, 2464 }, 2465 }, 2466 }; 2467 2468 static struct clk_branch gcc_prng_ahb_clk = { 2469 .halt_reg = 0x34004, 2470 .halt_check = BRANCH_HALT_VOTED, 2471 .clkr = { 2472 .enable_reg = 0x52004, 2473 .enable_mask = BIT(13), 2474 .hw.init = &(struct clk_init_data){ 2475 .name = "gcc_prng_ahb_clk", 2476 .ops = &clk_branch2_ops, 2477 }, 2478 }, 2479 }; 2480 2481 static struct clk_branch gcc_sdcc2_ahb_clk = { 2482 .halt_reg = 0x14008, 2483 .halt_check = BRANCH_HALT, 2484 .clkr = { 2485 .enable_reg = 0x14008, 2486 .enable_mask = BIT(0), 2487 .hw.init = &(struct clk_init_data){ 2488 .name = "gcc_sdcc2_ahb_clk", 2489 .ops = &clk_branch2_ops, 2490 }, 2491 }, 2492 }; 2493 2494 static struct clk_branch gcc_sdcc2_apps_clk = { 2495 .halt_reg = 0x14004, 2496 .halt_check = BRANCH_HALT, 2497 .clkr = { 2498 .enable_reg = 0x14004, 2499 .enable_mask = BIT(0), 2500 .hw.init = &(struct clk_init_data){ 2501 .name = "gcc_sdcc2_apps_clk", 2502 .parent_hws = (const struct clk_hw *[]) { 2503 &sdcc2_apps_clk_src.clkr.hw, 2504 }, 2505 .num_parents = 1, 2506 .flags = CLK_SET_RATE_PARENT, 2507 .ops = &clk_branch2_ops, 2508 }, 2509 }, 2510 }; 2511 2512 static struct clk_branch gcc_sdcc4_ahb_clk = { 2513 .halt_reg = 0x16008, 2514 .halt_check = BRANCH_HALT, 2515 .clkr = { 2516 .enable_reg = 0x16008, 2517 .enable_mask = BIT(0), 2518 .hw.init = &(struct clk_init_data){ 2519 .name = "gcc_sdcc4_ahb_clk", 2520 .ops = &clk_branch2_ops, 2521 }, 2522 }, 2523 }; 2524 2525 static struct clk_branch gcc_sdcc4_apps_clk = { 2526 .halt_reg = 0x16004, 2527 .halt_check = BRANCH_HALT, 2528 .clkr = { 2529 .enable_reg = 0x16004, 2530 .enable_mask = BIT(0), 2531 .hw.init = &(struct clk_init_data){ 2532 .name = "gcc_sdcc4_apps_clk", 2533 .parent_hws = (const struct clk_hw *[]) { 2534 &sdcc4_apps_clk_src.clkr.hw, 2535 }, 2536 .num_parents = 1, 2537 .flags = CLK_SET_RATE_PARENT, 2538 .ops = &clk_branch2_ops, 2539 }, 2540 }, 2541 }; 2542 2543 static struct clk_branch gcc_tsif_ahb_clk = { 2544 .halt_reg = 0x36004, 2545 .halt_check = BRANCH_HALT, 2546 .clkr = { 2547 .enable_reg = 0x36004, 2548 .enable_mask = BIT(0), 2549 .hw.init = &(struct clk_init_data){ 2550 .name = "gcc_tsif_ahb_clk", 2551 .ops = &clk_branch2_ops, 2552 }, 2553 }, 2554 }; 2555 2556 static struct clk_branch gcc_tsif_inactivity_timers_clk = { 2557 .halt_reg = 0x3600c, 2558 .halt_check = BRANCH_HALT, 2559 .clkr = { 2560 .enable_reg = 0x3600c, 2561 .enable_mask = BIT(0), 2562 .hw.init = &(struct clk_init_data){ 2563 .name = "gcc_tsif_inactivity_timers_clk", 2564 .ops = &clk_branch2_ops, 2565 }, 2566 }, 2567 }; 2568 2569 static struct clk_branch gcc_tsif_ref_clk = { 2570 .halt_reg = 0x36008, 2571 .halt_check = BRANCH_HALT, 2572 .clkr = { 2573 .enable_reg = 0x36008, 2574 .enable_mask = BIT(0), 2575 .hw.init = &(struct clk_init_data){ 2576 .name = "gcc_tsif_ref_clk", 2577 .parent_hws = (const struct clk_hw *[]) { 2578 &tsif_ref_clk_src.clkr.hw, 2579 }, 2580 .num_parents = 1, 2581 .flags = CLK_SET_RATE_PARENT, 2582 .ops = &clk_branch2_ops, 2583 }, 2584 }, 2585 }; 2586 2587 static struct clk_branch gcc_ufs_ahb_clk = { 2588 .halt_reg = 0x7500c, 2589 .halt_check = BRANCH_HALT, 2590 .clkr = { 2591 .enable_reg = 0x7500c, 2592 .enable_mask = BIT(0), 2593 .hw.init = &(struct clk_init_data){ 2594 .name = "gcc_ufs_ahb_clk", 2595 .ops = &clk_branch2_ops, 2596 }, 2597 }, 2598 }; 2599 2600 static struct clk_branch gcc_ufs_axi_clk = { 2601 .halt_reg = 0x75008, 2602 .halt_check = BRANCH_HALT, 2603 .clkr = { 2604 .enable_reg = 0x75008, 2605 .enable_mask = BIT(0), 2606 .hw.init = &(struct clk_init_data){ 2607 .name = "gcc_ufs_axi_clk", 2608 .parent_hws = (const struct clk_hw *[]) { 2609 &ufs_axi_clk_src.clkr.hw, 2610 }, 2611 .num_parents = 1, 2612 .flags = CLK_SET_RATE_PARENT, 2613 .ops = &clk_branch2_ops, 2614 }, 2615 }, 2616 }; 2617 2618 static struct clk_branch gcc_ufs_ice_core_clk = { 2619 .halt_reg = 0x7600c, 2620 .halt_check = BRANCH_HALT, 2621 .clkr = { 2622 .enable_reg = 0x7600c, 2623 .enable_mask = BIT(0), 2624 .hw.init = &(struct clk_init_data){ 2625 .name = "gcc_ufs_ice_core_clk", 2626 .ops = &clk_branch2_ops, 2627 }, 2628 }, 2629 }; 2630 2631 static struct clk_branch gcc_ufs_phy_aux_clk = { 2632 .halt_reg = 0x76040, 2633 .halt_check = BRANCH_HALT, 2634 .clkr = { 2635 .enable_reg = 0x76040, 2636 .enable_mask = BIT(0), 2637 .hw.init = &(struct clk_init_data){ 2638 .name = "gcc_ufs_phy_aux_clk", 2639 .ops = &clk_branch2_ops, 2640 }, 2641 }, 2642 }; 2643 2644 static struct clk_branch gcc_ufs_rx_symbol_0_clk = { 2645 .halt_reg = 0x75014, 2646 .halt_check = BRANCH_HALT_SKIP, 2647 .clkr = { 2648 .enable_reg = 0x75014, 2649 .enable_mask = BIT(0), 2650 .hw.init = &(struct clk_init_data){ 2651 .name = "gcc_ufs_rx_symbol_0_clk", 2652 .ops = &clk_branch2_ops, 2653 }, 2654 }, 2655 }; 2656 2657 static struct clk_branch gcc_ufs_rx_symbol_1_clk = { 2658 .halt_reg = 0x7605c, 2659 .halt_check = BRANCH_HALT_SKIP, 2660 .clkr = { 2661 .enable_reg = 0x7605c, 2662 .enable_mask = BIT(0), 2663 .hw.init = &(struct clk_init_data){ 2664 .name = "gcc_ufs_rx_symbol_1_clk", 2665 .ops = &clk_branch2_ops, 2666 }, 2667 }, 2668 }; 2669 2670 static struct clk_branch gcc_ufs_tx_symbol_0_clk = { 2671 .halt_reg = 0x75010, 2672 .halt_check = BRANCH_HALT_SKIP, 2673 .clkr = { 2674 .enable_reg = 0x75010, 2675 .enable_mask = BIT(0), 2676 .hw.init = &(struct clk_init_data){ 2677 .name = "gcc_ufs_tx_symbol_0_clk", 2678 .ops = &clk_branch2_ops, 2679 }, 2680 }, 2681 }; 2682 2683 static struct clk_branch gcc_ufs_unipro_core_clk = { 2684 .halt_reg = 0x76008, 2685 .halt_check = BRANCH_HALT, 2686 .clkr = { 2687 .enable_reg = 0x76008, 2688 .enable_mask = BIT(0), 2689 .hw.init = &(struct clk_init_data){ 2690 .name = "gcc_ufs_unipro_core_clk", 2691 .parent_hws = (const struct clk_hw *[]) { 2692 &ufs_unipro_core_clk_src.clkr.hw, 2693 }, 2694 .num_parents = 1, 2695 .flags = CLK_SET_RATE_PARENT, 2696 .ops = &clk_branch2_ops, 2697 }, 2698 }, 2699 }; 2700 2701 static struct clk_branch gcc_usb30_master_clk = { 2702 .halt_reg = 0xf008, 2703 .halt_check = BRANCH_HALT, 2704 .clkr = { 2705 .enable_reg = 0xf008, 2706 .enable_mask = BIT(0), 2707 .hw.init = &(struct clk_init_data){ 2708 .name = "gcc_usb30_master_clk", 2709 .parent_hws = (const struct clk_hw *[]) { 2710 &usb30_master_clk_src.clkr.hw, 2711 }, 2712 .num_parents = 1, 2713 .flags = CLK_SET_RATE_PARENT, 2714 .ops = &clk_branch2_ops, 2715 }, 2716 }, 2717 }; 2718 2719 static struct clk_branch gcc_usb30_mock_utmi_clk = { 2720 .halt_reg = 0xf010, 2721 .halt_check = BRANCH_HALT, 2722 .clkr = { 2723 .enable_reg = 0xf010, 2724 .enable_mask = BIT(0), 2725 .hw.init = &(struct clk_init_data){ 2726 .name = "gcc_usb30_mock_utmi_clk", 2727 .parent_hws = (const struct clk_hw *[]) { 2728 &usb30_mock_utmi_clk_src.clkr.hw, 2729 }, 2730 .num_parents = 1, 2731 .flags = CLK_SET_RATE_PARENT, 2732 .ops = &clk_branch2_ops, 2733 }, 2734 }, 2735 }; 2736 2737 static struct clk_branch gcc_usb30_sleep_clk = { 2738 .halt_reg = 0xf00c, 2739 .halt_check = BRANCH_HALT, 2740 .clkr = { 2741 .enable_reg = 0xf00c, 2742 .enable_mask = BIT(0), 2743 .hw.init = &(struct clk_init_data){ 2744 .name = "gcc_usb30_sleep_clk", 2745 .ops = &clk_branch2_ops, 2746 }, 2747 }, 2748 }; 2749 2750 static struct clk_branch gcc_usb3_phy_aux_clk = { 2751 .halt_reg = 0x50000, 2752 .halt_check = BRANCH_HALT, 2753 .clkr = { 2754 .enable_reg = 0x50000, 2755 .enable_mask = BIT(0), 2756 .hw.init = &(struct clk_init_data){ 2757 .name = "gcc_usb3_phy_aux_clk", 2758 .parent_hws = (const struct clk_hw *[]) { 2759 &usb3_phy_aux_clk_src.clkr.hw, 2760 }, 2761 .num_parents = 1, 2762 .flags = CLK_SET_RATE_PARENT, 2763 .ops = &clk_branch2_ops, 2764 }, 2765 }, 2766 }; 2767 2768 static struct clk_branch gcc_usb3_phy_pipe_clk = { 2769 .halt_reg = 0x50004, 2770 .halt_check = BRANCH_HALT_SKIP, 2771 .clkr = { 2772 .enable_reg = 0x50004, 2773 .enable_mask = BIT(0), 2774 .hw.init = &(struct clk_init_data){ 2775 .name = "gcc_usb3_phy_pipe_clk", 2776 .ops = &clk_branch2_ops, 2777 }, 2778 }, 2779 }; 2780 2781 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 2782 .halt_reg = 0x6a004, 2783 .halt_check = BRANCH_HALT, 2784 .clkr = { 2785 .enable_reg = 0x6a004, 2786 .enable_mask = BIT(0), 2787 .hw.init = &(struct clk_init_data){ 2788 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2789 .ops = &clk_branch2_ops, 2790 }, 2791 }, 2792 }; 2793 2794 static struct clk_branch gcc_hdmi_clkref_clk = { 2795 .halt_reg = 0x88000, 2796 .clkr = { 2797 .enable_reg = 0x88000, 2798 .enable_mask = BIT(0), 2799 .hw.init = &(struct clk_init_data){ 2800 .name = "gcc_hdmi_clkref_clk", 2801 .parent_data = (const struct clk_parent_data []) { 2802 { .fw_name = "xo" }, 2803 }, 2804 .num_parents = 1, 2805 .ops = &clk_branch2_ops, 2806 }, 2807 }, 2808 }; 2809 2810 static struct clk_branch gcc_ufs_clkref_clk = { 2811 .halt_reg = 0x88004, 2812 .clkr = { 2813 .enable_reg = 0x88004, 2814 .enable_mask = BIT(0), 2815 .hw.init = &(struct clk_init_data){ 2816 .name = "gcc_ufs_clkref_clk", 2817 .parent_data = (const struct clk_parent_data []) { 2818 { .fw_name = "xo" }, 2819 }, 2820 .num_parents = 1, 2821 .ops = &clk_branch2_ops, 2822 }, 2823 }, 2824 }; 2825 2826 static struct clk_branch gcc_usb3_clkref_clk = { 2827 .halt_reg = 0x88008, 2828 .clkr = { 2829 .enable_reg = 0x88008, 2830 .enable_mask = BIT(0), 2831 .hw.init = &(struct clk_init_data){ 2832 .name = "gcc_usb3_clkref_clk", 2833 .parent_data = (const struct clk_parent_data []) { 2834 { .fw_name = "xo" }, 2835 }, 2836 .num_parents = 1, 2837 .ops = &clk_branch2_ops, 2838 }, 2839 }, 2840 }; 2841 2842 static struct clk_branch gcc_pcie_clkref_clk = { 2843 .halt_reg = 0x8800c, 2844 .clkr = { 2845 .enable_reg = 0x8800c, 2846 .enable_mask = BIT(0), 2847 .hw.init = &(struct clk_init_data){ 2848 .name = "gcc_pcie_clkref_clk", 2849 .parent_data = (const struct clk_parent_data []) { 2850 { .fw_name = "xo" }, 2851 }, 2852 .num_parents = 1, 2853 .ops = &clk_branch2_ops, 2854 }, 2855 }, 2856 }; 2857 2858 static struct clk_branch gcc_rx1_usb2_clkref_clk = { 2859 .halt_reg = 0x88014, 2860 .clkr = { 2861 .enable_reg = 0x88014, 2862 .enable_mask = BIT(0), 2863 .hw.init = &(struct clk_init_data){ 2864 .name = "gcc_rx1_usb2_clkref_clk", 2865 .parent_data = (const struct clk_parent_data []) { 2866 { .fw_name = "xo" }, 2867 }, 2868 .num_parents = 1, 2869 .ops = &clk_branch2_ops, 2870 }, 2871 }, 2872 }; 2873 2874 static struct clk_branch gcc_im_sleep_clk = { 2875 .halt_reg = 0x4300c, 2876 .halt_check = BRANCH_HALT, 2877 .clkr = { 2878 .enable_reg = 0x4300c, 2879 .enable_mask = BIT(0), 2880 .hw.init = &(const struct clk_init_data){ 2881 .name = "gcc_im_sleep_clk", 2882 .ops = &clk_branch2_ops, 2883 }, 2884 }, 2885 }; 2886 2887 static struct clk_branch aggre2_snoc_north_axi_clk = { 2888 .halt_reg = 0x83010, 2889 .halt_check = BRANCH_HALT, 2890 .clkr = { 2891 .enable_reg = 0x83010, 2892 .enable_mask = BIT(0), 2893 .hw.init = &(const struct clk_init_data){ 2894 .name = "aggre2_snoc_north_axi_clk", 2895 .ops = &clk_branch2_ops, 2896 }, 2897 }, 2898 }; 2899 2900 static struct clk_branch ssc_xo_clk = { 2901 .halt_reg = 0x63018, 2902 .halt_check = BRANCH_HALT, 2903 .clkr = { 2904 .enable_reg = 0x63018, 2905 .enable_mask = BIT(0), 2906 .hw.init = &(const struct clk_init_data){ 2907 .name = "ssc_xo_clk", 2908 .ops = &clk_branch2_ops, 2909 }, 2910 }, 2911 }; 2912 2913 static struct clk_branch ssc_cnoc_ahbs_clk = { 2914 .halt_reg = 0x6300c, 2915 .halt_check = BRANCH_HALT, 2916 .clkr = { 2917 .enable_reg = 0x6300c, 2918 .enable_mask = BIT(0), 2919 .hw.init = &(const struct clk_init_data){ 2920 .name = "ssc_cnoc_ahbs_clk", 2921 .ops = &clk_branch2_ops, 2922 }, 2923 }, 2924 }; 2925 2926 static struct gdsc pcie_0_gdsc = { 2927 .gdscr = 0x6b004, 2928 .gds_hw_ctrl = 0x0, 2929 .pd = { 2930 .name = "pcie_0_gdsc", 2931 }, 2932 .pwrsts = PWRSTS_OFF_ON, 2933 .flags = VOTABLE, 2934 }; 2935 2936 static struct gdsc ufs_gdsc = { 2937 .gdscr = 0x75004, 2938 .gds_hw_ctrl = 0x0, 2939 .pd = { 2940 .name = "ufs_gdsc", 2941 }, 2942 .pwrsts = PWRSTS_OFF_ON, 2943 .flags = VOTABLE, 2944 }; 2945 2946 static struct gdsc usb_30_gdsc = { 2947 .gdscr = 0xf004, 2948 .gds_hw_ctrl = 0x0, 2949 .pd = { 2950 .name = "usb_30_gdsc", 2951 }, 2952 /* TODO: Change to OFF_ON when USB drivers get proper suspend support */ 2953 .pwrsts = PWRSTS_RET_ON, 2954 .flags = VOTABLE, 2955 }; 2956 2957 static struct clk_regmap *gcc_msm8998_clocks[] = { 2958 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2959 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2960 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2961 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2962 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2963 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2964 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2965 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2966 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 2967 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 2968 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 2969 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 2970 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2971 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2972 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 2973 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, 2974 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, 2975 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, 2976 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, 2977 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, 2978 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, 2979 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, 2980 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, 2981 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, 2982 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, 2983 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, 2984 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, 2985 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, 2986 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, 2987 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, 2988 [GCC_AGGRE1_NOC_XO_CLK] = &gcc_aggre1_noc_xo_clk.clkr, 2989 [GCC_AGGRE1_UFS_AXI_CLK] = &gcc_aggre1_ufs_axi_clk.clkr, 2990 [GCC_AGGRE1_USB3_AXI_CLK] = &gcc_aggre1_usb3_axi_clk.clkr, 2991 [GCC_APSS_QDSS_TSCTR_DIV2_CLK] = &gcc_apss_qdss_tsctr_div2_clk.clkr, 2992 [GCC_APSS_QDSS_TSCTR_DIV8_CLK] = &gcc_apss_qdss_tsctr_div8_clk.clkr, 2993 [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr, 2994 [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr, 2995 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2996 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2997 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2998 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2999 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 3000 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 3001 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 3002 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 3003 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 3004 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 3005 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 3006 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 3007 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 3008 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, 3009 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 3010 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 3011 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 3012 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, 3013 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, 3014 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, 3015 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, 3016 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, 3017 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, 3018 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, 3019 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, 3020 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, 3021 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, 3022 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, 3023 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, 3024 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, 3025 [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr, 3026 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, 3027 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, 3028 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, 3029 [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr, 3030 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3031 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3032 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3033 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, 3034 [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr, 3035 [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr, 3036 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 3037 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3038 [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr, 3039 [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr, 3040 [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr, 3041 [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr, 3042 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr, 3043 [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr, 3044 [GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr, 3045 [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr, 3046 [GCC_MSS_AT_CLK] = &gcc_mss_at_clk.clkr, 3047 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3048 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3049 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3050 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3051 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3052 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, 3053 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3054 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3055 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3056 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3057 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3058 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3059 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3060 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3061 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 3062 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, 3063 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 3064 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, 3065 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, 3066 [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr, 3067 [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr, 3068 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, 3069 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, 3070 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, 3071 [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr, 3072 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, 3073 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 3074 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 3075 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, 3076 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, 3077 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 3078 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 3079 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 3080 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 3081 [GPLL0] = &gpll0.clkr, 3082 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 3083 [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr, 3084 [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr, 3085 [GPLL0_OUT_TEST] = &gpll0_out_test.clkr, 3086 [GPLL1] = &gpll1.clkr, 3087 [GPLL1_OUT_EVEN] = &gpll1_out_even.clkr, 3088 [GPLL1_OUT_MAIN] = &gpll1_out_main.clkr, 3089 [GPLL1_OUT_ODD] = &gpll1_out_odd.clkr, 3090 [GPLL1_OUT_TEST] = &gpll1_out_test.clkr, 3091 [GPLL2] = &gpll2.clkr, 3092 [GPLL2_OUT_EVEN] = &gpll2_out_even.clkr, 3093 [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr, 3094 [GPLL2_OUT_ODD] = &gpll2_out_odd.clkr, 3095 [GPLL2_OUT_TEST] = &gpll2_out_test.clkr, 3096 [GPLL3] = &gpll3.clkr, 3097 [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr, 3098 [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr, 3099 [GPLL3_OUT_ODD] = &gpll3_out_odd.clkr, 3100 [GPLL3_OUT_TEST] = &gpll3_out_test.clkr, 3101 [GPLL4] = &gpll4.clkr, 3102 [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr, 3103 [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr, 3104 [GPLL4_OUT_ODD] = &gpll4_out_odd.clkr, 3105 [GPLL4_OUT_TEST] = &gpll4_out_test.clkr, 3106 [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr, 3107 [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr, 3108 [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr, 3109 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 3110 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 3111 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, 3112 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, 3113 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, 3114 [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr, 3115 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, 3116 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 3117 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, 3118 [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr, 3119 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, 3120 [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr, 3121 [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr, 3122 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr, 3123 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 3124 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3125 [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr, 3126 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, 3127 [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr, 3128 [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr, 3129 [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr, 3130 [GCC_IM_SLEEP] = &gcc_im_sleep_clk.clkr, 3131 [AGGRE2_SNOC_NORTH_AXI] = &aggre2_snoc_north_axi_clk.clkr, 3132 [SSC_XO] = &ssc_xo_clk.clkr, 3133 [SSC_CNOC_AHBS_CLK] = &ssc_cnoc_ahbs_clk.clkr, 3134 [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr, 3135 [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr, 3136 [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr, 3137 }; 3138 3139 static struct gdsc *gcc_msm8998_gdscs[] = { 3140 [PCIE_0_GDSC] = &pcie_0_gdsc, 3141 [UFS_GDSC] = &ufs_gdsc, 3142 [USB_30_GDSC] = &usb_30_gdsc, 3143 }; 3144 3145 static const struct qcom_reset_map gcc_msm8998_resets[] = { 3146 [GCC_BLSP1_QUP1_BCR] = { 0x19000 }, 3147 [GCC_BLSP1_QUP2_BCR] = { 0x1b000 }, 3148 [GCC_BLSP1_QUP3_BCR] = { 0x1d000 }, 3149 [GCC_BLSP1_QUP4_BCR] = { 0x1f000 }, 3150 [GCC_BLSP1_QUP5_BCR] = { 0x21000 }, 3151 [GCC_BLSP1_QUP6_BCR] = { 0x23000 }, 3152 [GCC_BLSP2_QUP1_BCR] = { 0x26000 }, 3153 [GCC_BLSP2_QUP2_BCR] = { 0x28000 }, 3154 [GCC_BLSP2_QUP3_BCR] = { 0x2a000 }, 3155 [GCC_BLSP2_QUP4_BCR] = { 0x2c000 }, 3156 [GCC_BLSP2_QUP5_BCR] = { 0x2e000 }, 3157 [GCC_BLSP2_QUP6_BCR] = { 0x30000 }, 3158 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3159 [GCC_PDM_BCR] = { 0x33000 }, 3160 [GCC_SDCC2_BCR] = { 0x14000 }, 3161 [GCC_SDCC4_BCR] = { 0x16000 }, 3162 [GCC_TSIF_BCR] = { 0x36000 }, 3163 [GCC_UFS_BCR] = { 0x75000 }, 3164 [GCC_USB_30_BCR] = { 0xf000 }, 3165 [GCC_SYSTEM_NOC_BCR] = { 0x4000 }, 3166 [GCC_CONFIG_NOC_BCR] = { 0x5000 }, 3167 [GCC_AHB2PHY_EAST_BCR] = { 0x7000 }, 3168 [GCC_IMEM_BCR] = { 0x8000 }, 3169 [GCC_PIMEM_BCR] = { 0xa000 }, 3170 [GCC_MMSS_BCR] = { 0xb000 }, 3171 [GCC_QDSS_BCR] = { 0xc000 }, 3172 [GCC_WCSS_BCR] = { 0x11000 }, 3173 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3174 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3175 [GCC_BLSP1_BCR] = { 0x17000 }, 3176 [GCC_BLSP1_UART1_BCR] = { 0x1a000 }, 3177 [GCC_BLSP1_UART2_BCR] = { 0x1c000 }, 3178 [GCC_BLSP1_UART3_BCR] = { 0x1e000 }, 3179 [GCC_CM_PHY_REFGEN1_BCR] = { 0x22000 }, 3180 [GCC_CM_PHY_REFGEN2_BCR] = { 0x24000 }, 3181 [GCC_BLSP2_BCR] = { 0x25000 }, 3182 [GCC_BLSP2_UART1_BCR] = { 0x27000 }, 3183 [GCC_BLSP2_UART2_BCR] = { 0x29000 }, 3184 [GCC_BLSP2_UART3_BCR] = { 0x2b000 }, 3185 [GCC_SRAM_SENSOR_BCR] = { 0x2d000 }, 3186 [GCC_PRNG_BCR] = { 0x34000 }, 3187 [GCC_TSIF_0_RESET] = { 0x36024 }, 3188 [GCC_TSIF_1_RESET] = { 0x36028 }, 3189 [GCC_TCSR_BCR] = { 0x37000 }, 3190 [GCC_BOOT_ROM_BCR] = { 0x38000 }, 3191 [GCC_MSG_RAM_BCR] = { 0x39000 }, 3192 [GCC_TLMM_BCR] = { 0x3a000 }, 3193 [GCC_MPM_BCR] = { 0x3b000 }, 3194 [GCC_SEC_CTRL_BCR] = { 0x3d000 }, 3195 [GCC_SPMI_BCR] = { 0x3f000 }, 3196 [GCC_SPDM_BCR] = { 0x40000 }, 3197 [GCC_CE1_BCR] = { 0x41000 }, 3198 [GCC_BIMC_BCR] = { 0x44000 }, 3199 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 }, 3200 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49008 }, 3201 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49010 }, 3202 [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49018 }, 3203 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 }, 3204 [GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR] = { 0x4a004 }, 3205 [GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR] = { 0x4a00c }, 3206 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 }, 3207 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 }, 3208 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 }, 3209 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 }, 3210 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 }, 3211 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 }, 3212 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 }, 3213 [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 }, 3214 [GCC_APB2JTAG_BCR] = { 0x4c000 }, 3215 [GCC_RBCPR_CX_BCR] = { 0x4e000 }, 3216 [GCC_RBCPR_MX_BCR] = { 0x4f000 }, 3217 [GCC_USB3_PHY_BCR] = { 0x50020 }, 3218 [GCC_USB3PHY_PHY_BCR] = { 0x50024 }, 3219 [GCC_USB3_DP_PHY_BCR] = { 0x50028 }, 3220 [GCC_SSC_BCR] = { 0x63000 }, 3221 [GCC_SSC_RESET] = { 0x63020 }, 3222 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 3223 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 3224 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3225 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 3226 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 3227 [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00c }, 3228 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f010 }, 3229 [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 }, 3230 [GCC_GPU_BCR] = { 0x71000 }, 3231 [GCC_SPSS_BCR] = { 0x72000 }, 3232 [GCC_OBT_ODT_BCR] = { 0x73000 }, 3233 [GCC_MSS_RESTART] = { 0x79000 }, 3234 [GCC_VS_BCR] = { 0x7a000 }, 3235 [GCC_MSS_VS_RESET] = { 0x7a100 }, 3236 [GCC_GPU_VS_RESET] = { 0x7a104 }, 3237 [GCC_APC0_VS_RESET] = { 0x7a108 }, 3238 [GCC_APC1_VS_RESET] = { 0x7a10c }, 3239 [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 }, 3240 [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 }, 3241 [GCC_CNOC_BUS_TIMEOUT10_BCR] = { 0x80010 }, 3242 [GCC_CNOC_BUS_TIMEOUT11_BCR] = { 0x80018 }, 3243 [GCC_CNOC_BUS_TIMEOUT12_BCR] = { 0x80020 }, 3244 [GCC_CNOC_BUS_TIMEOUT13_BCR] = { 0x80028 }, 3245 [GCC_CNOC_BUS_TIMEOUT14_BCR] = { 0x80030 }, 3246 [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80038 }, 3247 [GCC_AGGRE1_NOC_BCR] = { 0x82000 }, 3248 [GCC_AGGRE2_NOC_BCR] = { 0x83000 }, 3249 [GCC_DCC_BCR] = { 0x84000 }, 3250 [GCC_QREFS_VBG_CAL_BCR] = { 0x88028 }, 3251 [GCC_IPA_BCR] = { 0x89000 }, 3252 [GCC_GLM_BCR] = { 0x8b000 }, 3253 [GCC_SKL_BCR] = { 0x8c000 }, 3254 [GCC_MSMPU_BCR] = { 0x8d000 }, 3255 }; 3256 3257 static const struct regmap_config gcc_msm8998_regmap_config = { 3258 .reg_bits = 32, 3259 .reg_stride = 4, 3260 .val_bits = 32, 3261 .max_register = 0x8f000, 3262 .fast_io = true, 3263 }; 3264 3265 static const struct qcom_cc_desc gcc_msm8998_desc = { 3266 .config = &gcc_msm8998_regmap_config, 3267 .clks = gcc_msm8998_clocks, 3268 .num_clks = ARRAY_SIZE(gcc_msm8998_clocks), 3269 .resets = gcc_msm8998_resets, 3270 .num_resets = ARRAY_SIZE(gcc_msm8998_resets), 3271 .gdscs = gcc_msm8998_gdscs, 3272 .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs), 3273 }; 3274 3275 static int gcc_msm8998_probe(struct platform_device *pdev) 3276 { 3277 struct regmap *regmap; 3278 int ret; 3279 3280 regmap = qcom_cc_map(pdev, &gcc_msm8998_desc); 3281 if (IS_ERR(regmap)) 3282 return PTR_ERR(regmap); 3283 3284 /* 3285 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be 3286 * turned off by hardware during certain apps low power modes. 3287 */ 3288 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); 3289 if (ret) 3290 return ret; 3291 3292 /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */ 3293 regmap_write(regmap, GCC_MMSS_MISC, 0x10003); 3294 regmap_write(regmap, GCC_GPU_MISC, 0x10003); 3295 3296 return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap); 3297 } 3298 3299 static const struct of_device_id gcc_msm8998_match_table[] = { 3300 { .compatible = "qcom,gcc-msm8998" }, 3301 { } 3302 }; 3303 MODULE_DEVICE_TABLE(of, gcc_msm8998_match_table); 3304 3305 static struct platform_driver gcc_msm8998_driver = { 3306 .probe = gcc_msm8998_probe, 3307 .driver = { 3308 .name = "gcc-msm8998", 3309 .of_match_table = gcc_msm8998_match_table, 3310 }, 3311 }; 3312 3313 static int __init gcc_msm8998_init(void) 3314 { 3315 return platform_driver_register(&gcc_msm8998_driver); 3316 } 3317 core_initcall(gcc_msm8998_init); 3318 3319 static void __exit gcc_msm8998_exit(void) 3320 { 3321 platform_driver_unregister(&gcc_msm8998_driver); 3322 } 3323 module_exit(gcc_msm8998_exit); 3324 3325 MODULE_DESCRIPTION("QCOM GCC msm8998 Driver"); 3326 MODULE_LICENSE("GPL v2"); 3327 MODULE_ALIAS("platform:gcc-msm8998"); 3328